1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
49 #include "gdb_assert.h"
50 #include "gdb_string.h"
52 #include "i386-tdep.h"
53 #include "i387-tdep.h"
54 #include "i386-xstate.h"
59 #include "features/i386/i386.c"
60 #include "features/i386/i386-avx.c"
64 static const char *i386_register_names[] =
66 "eax", "ecx", "edx", "ebx",
67 "esp", "ebp", "esi", "edi",
68 "eip", "eflags", "cs", "ss",
69 "ds", "es", "fs", "gs",
70 "st0", "st1", "st2", "st3",
71 "st4", "st5", "st6", "st7",
72 "fctrl", "fstat", "ftag", "fiseg",
73 "fioff", "foseg", "fooff", "fop",
74 "xmm0", "xmm1", "xmm2", "xmm3",
75 "xmm4", "xmm5", "xmm6", "xmm7",
79 static const char *i386_ymm_names[] =
81 "ymm0", "ymm1", "ymm2", "ymm3",
82 "ymm4", "ymm5", "ymm6", "ymm7",
85 static const char *i386_ymmh_names[] =
87 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
88 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
91 /* Register names for MMX pseudo-registers. */
93 static const char *i386_mmx_names[] =
95 "mm0", "mm1", "mm2", "mm3",
96 "mm4", "mm5", "mm6", "mm7"
99 /* Register names for byte pseudo-registers. */
101 static const char *i386_byte_names[] =
103 "al", "cl", "dl", "bl",
104 "ah", "ch", "dh", "bh"
107 /* Register names for word pseudo-registers. */
109 static const char *i386_word_names[] =
111 "ax", "cx", "dx", "bx",
118 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
120 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
121 int mm0_regnum = tdep->mm0_regnum;
126 regnum -= mm0_regnum;
127 return regnum >= 0 && regnum < tdep->num_mmx_regs;
133 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
135 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
137 regnum -= tdep->al_regnum;
138 return regnum >= 0 && regnum < tdep->num_byte_regs;
144 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
146 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
148 regnum -= tdep->ax_regnum;
149 return regnum >= 0 && regnum < tdep->num_word_regs;
152 /* Dword register? */
155 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
157 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
158 int eax_regnum = tdep->eax_regnum;
163 regnum -= eax_regnum;
164 return regnum >= 0 && regnum < tdep->num_dword_regs;
168 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
170 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
171 int ymm0h_regnum = tdep->ymm0h_regnum;
173 if (ymm0h_regnum < 0)
176 regnum -= ymm0h_regnum;
177 return regnum >= 0 && regnum < tdep->num_ymm_regs;
183 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
185 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
186 int ymm0_regnum = tdep->ymm0_regnum;
191 regnum -= ymm0_regnum;
192 return regnum >= 0 && regnum < tdep->num_ymm_regs;
198 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
200 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
201 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
203 if (num_xmm_regs == 0)
206 regnum -= I387_XMM0_REGNUM (tdep);
207 return regnum >= 0 && regnum < num_xmm_regs;
211 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
213 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
215 if (I387_NUM_XMM_REGS (tdep) == 0)
218 return (regnum == I387_MXCSR_REGNUM (tdep));
224 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
226 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
228 if (I387_ST0_REGNUM (tdep) < 0)
231 return (I387_ST0_REGNUM (tdep) <= regnum
232 && regnum < I387_FCTRL_REGNUM (tdep));
236 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
238 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
240 if (I387_ST0_REGNUM (tdep) < 0)
243 return (I387_FCTRL_REGNUM (tdep) <= regnum
244 && regnum < I387_XMM0_REGNUM (tdep));
247 /* Return the name of register REGNUM, or the empty string if it is
248 an anonymous register. */
251 i386_register_name (struct gdbarch *gdbarch, int regnum)
253 /* Hide the upper YMM registers. */
254 if (i386_ymmh_regnum_p (gdbarch, regnum))
257 return tdesc_register_name (gdbarch, regnum);
260 /* Return the name of register REGNUM. */
263 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
265 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
266 if (i386_mmx_regnum_p (gdbarch, regnum))
267 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
268 else if (i386_ymm_regnum_p (gdbarch, regnum))
269 return i386_ymm_names[regnum - tdep->ymm0_regnum];
270 else if (i386_byte_regnum_p (gdbarch, regnum))
271 return i386_byte_names[regnum - tdep->al_regnum];
272 else if (i386_word_regnum_p (gdbarch, regnum))
273 return i386_word_names[regnum - tdep->ax_regnum];
275 internal_error (__FILE__, __LINE__, _("invalid regnum"));
278 /* Convert a dbx register number REG to the appropriate register
279 number used by GDB. */
282 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
284 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
286 /* This implements what GCC calls the "default" register map
287 (dbx_register_map[]). */
289 if (reg >= 0 && reg <= 7)
291 /* General-purpose registers. The debug info calls %ebp
292 register 4, and %esp register 5. */
299 else if (reg >= 12 && reg <= 19)
301 /* Floating-point registers. */
302 return reg - 12 + I387_ST0_REGNUM (tdep);
304 else if (reg >= 21 && reg <= 28)
307 int ymm0_regnum = tdep->ymm0_regnum;
310 && i386_xmm_regnum_p (gdbarch, reg))
311 return reg - 21 + ymm0_regnum;
313 return reg - 21 + I387_XMM0_REGNUM (tdep);
315 else if (reg >= 29 && reg <= 36)
318 return reg - 29 + I387_MM0_REGNUM (tdep);
321 /* This will hopefully provoke a warning. */
322 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
325 /* Convert SVR4 register number REG to the appropriate register number
329 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
331 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
333 /* This implements the GCC register map that tries to be compatible
334 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
336 /* The SVR4 register numbering includes %eip and %eflags, and
337 numbers the floating point registers differently. */
338 if (reg >= 0 && reg <= 9)
340 /* General-purpose registers. */
343 else if (reg >= 11 && reg <= 18)
345 /* Floating-point registers. */
346 return reg - 11 + I387_ST0_REGNUM (tdep);
348 else if (reg >= 21 && reg <= 36)
350 /* The SSE and MMX registers have the same numbers as with dbx. */
351 return i386_dbx_reg_to_regnum (gdbarch, reg);
356 case 37: return I387_FCTRL_REGNUM (tdep);
357 case 38: return I387_FSTAT_REGNUM (tdep);
358 case 39: return I387_MXCSR_REGNUM (tdep);
359 case 40: return I386_ES_REGNUM;
360 case 41: return I386_CS_REGNUM;
361 case 42: return I386_SS_REGNUM;
362 case 43: return I386_DS_REGNUM;
363 case 44: return I386_FS_REGNUM;
364 case 45: return I386_GS_REGNUM;
367 /* This will hopefully provoke a warning. */
368 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
373 /* This is the variable that is set with "set disassembly-flavor", and
374 its legitimate values. */
375 static const char att_flavor[] = "att";
376 static const char intel_flavor[] = "intel";
377 static const char *valid_flavors[] =
383 static const char *disassembly_flavor = att_flavor;
386 /* Use the program counter to determine the contents and size of a
387 breakpoint instruction. Return a pointer to a string of bytes that
388 encode a breakpoint instruction, store the length of the string in
389 *LEN and optionally adjust *PC to point to the correct memory
390 location for inserting the breakpoint.
392 On the i386 we have a single breakpoint that fits in a single byte
393 and can be inserted anywhere.
395 This function is 64-bit safe. */
397 static const gdb_byte *
398 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
400 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */
402 *len = sizeof (break_insn);
406 /* Displaced instruction handling. */
408 /* Skip the legacy instruction prefixes in INSN.
409 Not all prefixes are valid for any particular insn
410 but we needn't care, the insn will fault if it's invalid.
411 The result is a pointer to the first opcode byte,
412 or NULL if we run off the end of the buffer. */
415 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
417 gdb_byte *end = insn + max_len;
423 case DATA_PREFIX_OPCODE:
424 case ADDR_PREFIX_OPCODE:
425 case CS_PREFIX_OPCODE:
426 case DS_PREFIX_OPCODE:
427 case ES_PREFIX_OPCODE:
428 case FS_PREFIX_OPCODE:
429 case GS_PREFIX_OPCODE:
430 case SS_PREFIX_OPCODE:
431 case LOCK_PREFIX_OPCODE:
432 case REPE_PREFIX_OPCODE:
433 case REPNE_PREFIX_OPCODE:
445 i386_absolute_jmp_p (const gdb_byte *insn)
447 /* jmp far (absolute address in operand) */
453 /* jump near, absolute indirect (/4) */
454 if ((insn[1] & 0x38) == 0x20)
457 /* jump far, absolute indirect (/5) */
458 if ((insn[1] & 0x38) == 0x28)
466 i386_absolute_call_p (const gdb_byte *insn)
468 /* call far, absolute */
474 /* Call near, absolute indirect (/2) */
475 if ((insn[1] & 0x38) == 0x10)
478 /* Call far, absolute indirect (/3) */
479 if ((insn[1] & 0x38) == 0x18)
487 i386_ret_p (const gdb_byte *insn)
491 case 0xc2: /* ret near, pop N bytes */
492 case 0xc3: /* ret near */
493 case 0xca: /* ret far, pop N bytes */
494 case 0xcb: /* ret far */
495 case 0xcf: /* iret */
504 i386_call_p (const gdb_byte *insn)
506 if (i386_absolute_call_p (insn))
509 /* call near, relative */
516 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
517 length in bytes. Otherwise, return zero. */
520 i386_syscall_p (const gdb_byte *insn, ULONGEST *lengthp)
531 /* Fix up the state of registers and memory after having single-stepped
532 a displaced instruction. */
535 i386_displaced_step_fixup (struct gdbarch *gdbarch,
536 struct displaced_step_closure *closure,
537 CORE_ADDR from, CORE_ADDR to,
538 struct regcache *regs)
540 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
542 /* The offset we applied to the instruction's address.
543 This could well be negative (when viewed as a signed 32-bit
544 value), but ULONGEST won't reflect that, so take care when
546 ULONGEST insn_offset = to - from;
548 /* Since we use simple_displaced_step_copy_insn, our closure is a
549 copy of the instruction. */
550 gdb_byte *insn = (gdb_byte *) closure;
551 /* The start of the insn, needed in case we see some prefixes. */
552 gdb_byte *insn_start = insn;
555 fprintf_unfiltered (gdb_stdlog,
556 "displaced: fixup (%s, %s), "
557 "insn = 0x%02x 0x%02x ...\n",
558 paddress (gdbarch, from), paddress (gdbarch, to),
561 /* The list of issues to contend with here is taken from
562 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
563 Yay for Free Software! */
565 /* Relocate the %eip, if necessary. */
567 /* The instruction recognizers we use assume any leading prefixes
568 have been skipped. */
570 /* This is the size of the buffer in closure. */
571 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
572 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
573 /* If there are too many prefixes, just ignore the insn.
574 It will fault when run. */
579 /* Except in the case of absolute or indirect jump or call
580 instructions, or a return instruction, the new eip is relative to
581 the displaced instruction; make it relative. Well, signal
582 handler returns don't need relocation either, but we use the
583 value of %eip to recognize those; see below. */
584 if (! i386_absolute_jmp_p (insn)
585 && ! i386_absolute_call_p (insn)
586 && ! i386_ret_p (insn))
591 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
593 /* A signal trampoline system call changes the %eip, resuming
594 execution of the main program after the signal handler has
595 returned. That makes them like 'return' instructions; we
596 shouldn't relocate %eip.
598 But most system calls don't, and we do need to relocate %eip.
600 Our heuristic for distinguishing these cases: if stepping
601 over the system call instruction left control directly after
602 the instruction, the we relocate --- control almost certainly
603 doesn't belong in the displaced copy. Otherwise, we assume
604 the instruction has put control where it belongs, and leave
605 it unrelocated. Goodness help us if there are PC-relative
607 if (i386_syscall_p (insn, &insn_len)
608 && orig_eip != to + (insn - insn_start) + insn_len)
611 fprintf_unfiltered (gdb_stdlog,
612 "displaced: syscall changed %%eip; "
617 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
619 /* If we just stepped over a breakpoint insn, we don't backup
620 the pc on purpose; this is to match behaviour without
623 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
626 fprintf_unfiltered (gdb_stdlog,
628 "relocated %%eip from %s to %s\n",
629 paddress (gdbarch, orig_eip),
630 paddress (gdbarch, eip));
634 /* If the instruction was PUSHFL, then the TF bit will be set in the
635 pushed value, and should be cleared. We'll leave this for later,
636 since GDB already messes up the TF flag when stepping over a
639 /* If the instruction was a call, the return address now atop the
640 stack is the address following the copied instruction. We need
641 to make it the address following the original instruction. */
642 if (i386_call_p (insn))
646 const ULONGEST retaddr_len = 4;
648 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
649 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
650 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
651 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
654 fprintf_unfiltered (gdb_stdlog,
655 "displaced: relocated return addr at %s to %s\n",
656 paddress (gdbarch, esp),
657 paddress (gdbarch, retaddr));
661 #ifdef I386_REGNO_TO_SYMMETRY
662 #error "The Sequent Symmetry is no longer supported."
665 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
666 and %esp "belong" to the calling function. Therefore these
667 registers should be saved if they're going to be modified. */
669 /* The maximum number of saved registers. This should include all
670 registers mentioned above, and %eip. */
671 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
673 struct i386_frame_cache
680 /* Saved registers. */
681 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
686 /* Stack space reserved for local variables. */
690 /* Allocate and initialize a frame cache. */
692 static struct i386_frame_cache *
693 i386_alloc_frame_cache (void)
695 struct i386_frame_cache *cache;
698 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
702 cache->sp_offset = -4;
705 /* Saved registers. We initialize these to -1 since zero is a valid
706 offset (that's where %ebp is supposed to be stored). */
707 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
708 cache->saved_regs[i] = -1;
710 cache->saved_sp_reg = -1;
711 cache->pc_in_eax = 0;
713 /* Frameless until proven otherwise. */
719 /* If the instruction at PC is a jump, return the address of its
720 target. Otherwise, return PC. */
723 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
725 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
730 target_read_memory (pc, &op, 1);
734 op = read_memory_unsigned_integer (pc + 1, 1, byte_order);
740 /* Relative jump: if data16 == 0, disp32, else disp16. */
743 delta = read_memory_integer (pc + 2, 2, byte_order);
745 /* Include the size of the jmp instruction (including the
751 delta = read_memory_integer (pc + 1, 4, byte_order);
753 /* Include the size of the jmp instruction. */
758 /* Relative jump, disp8 (ignore data16). */
759 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
768 /* Check whether PC points at a prologue for a function returning a
769 structure or union. If so, it updates CACHE and returns the
770 address of the first instruction after the code sequence that
771 removes the "hidden" argument from the stack or CURRENT_PC,
772 whichever is smaller. Otherwise, return PC. */
775 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
776 struct i386_frame_cache *cache)
778 /* Functions that return a structure or union start with:
781 xchgl %eax, (%esp) 0x87 0x04 0x24
782 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
784 (the System V compiler puts out the second `xchg' instruction,
785 and the assembler doesn't try to optimize it, so the 'sib' form
786 gets generated). This sequence is used to get the address of the
787 return buffer for a function that returns a structure. */
788 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
789 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
793 if (current_pc <= pc)
796 target_read_memory (pc, &op, 1);
798 if (op != 0x58) /* popl %eax */
801 target_read_memory (pc + 1, buf, 4);
802 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
805 if (current_pc == pc)
807 cache->sp_offset += 4;
811 if (current_pc == pc + 1)
813 cache->pc_in_eax = 1;
817 if (buf[1] == proto1[1])
824 i386_skip_probe (CORE_ADDR pc)
826 /* A function may start with
840 target_read_memory (pc, &op, 1);
842 if (op == 0x68 || op == 0x6a)
846 /* Skip past the `pushl' instruction; it has either a one-byte or a
847 four-byte operand, depending on the opcode. */
853 /* Read the following 8 bytes, which should be `call _probe' (6
854 bytes) followed by `addl $4,%esp' (2 bytes). */
855 read_memory (pc + delta, buf, sizeof (buf));
856 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
857 pc += delta + sizeof (buf);
863 /* GCC 4.1 and later, can put code in the prologue to realign the
864 stack pointer. Check whether PC points to such code, and update
865 CACHE accordingly. Return the first instruction after the code
866 sequence or CURRENT_PC, whichever is smaller. If we don't
867 recognize the code, return PC. */
870 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
871 struct i386_frame_cache *cache)
873 /* There are 2 code sequences to re-align stack before the frame
876 1. Use a caller-saved saved register:
882 2. Use a callee-saved saved register:
889 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
891 0x83 0xe4 0xf0 andl $-16, %esp
892 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
897 int offset, offset_and;
898 static int regnums[8] = {
899 I386_EAX_REGNUM, /* %eax */
900 I386_ECX_REGNUM, /* %ecx */
901 I386_EDX_REGNUM, /* %edx */
902 I386_EBX_REGNUM, /* %ebx */
903 I386_ESP_REGNUM, /* %esp */
904 I386_EBP_REGNUM, /* %ebp */
905 I386_ESI_REGNUM, /* %esi */
906 I386_EDI_REGNUM /* %edi */
909 if (target_read_memory (pc, buf, sizeof buf))
912 /* Check caller-saved saved register. The first instruction has
913 to be "leal 4(%esp), %reg". */
914 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
916 /* MOD must be binary 10 and R/M must be binary 100. */
917 if ((buf[1] & 0xc7) != 0x44)
920 /* REG has register number. */
921 reg = (buf[1] >> 3) & 7;
926 /* Check callee-saved saved register. The first instruction
927 has to be "pushl %reg". */
928 if ((buf[0] & 0xf8) != 0x50)
934 /* The next instruction has to be "leal 8(%esp), %reg". */
935 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
938 /* MOD must be binary 10 and R/M must be binary 100. */
939 if ((buf[2] & 0xc7) != 0x44)
942 /* REG has register number. Registers in pushl and leal have to
944 if (reg != ((buf[2] >> 3) & 7))
950 /* Rigister can't be %esp nor %ebp. */
951 if (reg == 4 || reg == 5)
954 /* The next instruction has to be "andl $-XXX, %esp". */
955 if (buf[offset + 1] != 0xe4
956 || (buf[offset] != 0x81 && buf[offset] != 0x83))
960 offset += buf[offset] == 0x81 ? 6 : 3;
962 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
963 0xfc. REG must be binary 110 and MOD must be binary 01. */
964 if (buf[offset] != 0xff
965 || buf[offset + 2] != 0xfc
966 || (buf[offset + 1] & 0xf8) != 0x70)
969 /* R/M has register. Registers in leal and pushl have to be the
971 if (reg != (buf[offset + 1] & 7))
974 if (current_pc > pc + offset_and)
975 cache->saved_sp_reg = regnums[reg];
977 return min (pc + offset + 3, current_pc);
980 /* Maximum instruction length we need to handle. */
981 #define I386_MAX_MATCHED_INSN_LEN 6
983 /* Instruction description. */
987 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
988 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
991 /* Search for the instruction at PC in the list SKIP_INSNS. Return
992 the first instruction description that matches. Otherwise, return
995 static struct i386_insn *
996 i386_match_insn (CORE_ADDR pc, struct i386_insn *skip_insns)
998 struct i386_insn *insn;
1001 target_read_memory (pc, &op, 1);
1003 for (insn = skip_insns; insn->len > 0; insn++)
1005 if ((op & insn->mask[0]) == insn->insn[0])
1007 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1008 int insn_matched = 1;
1011 gdb_assert (insn->len > 1);
1012 gdb_assert (insn->len <= I386_MAX_MATCHED_INSN_LEN);
1014 target_read_memory (pc + 1, buf, insn->len - 1);
1015 for (i = 1; i < insn->len; i++)
1017 if ((buf[i - 1] & insn->mask[i]) != insn->insn[i])
1029 /* Some special instructions that might be migrated by GCC into the
1030 part of the prologue that sets up the new stack frame. Because the
1031 stack frame hasn't been setup yet, no registers have been saved
1032 yet, and only the scratch registers %eax, %ecx and %edx can be
1035 struct i386_insn i386_frame_setup_skip_insns[] =
1037 /* Check for `movb imm8, r' and `movl imm32, r'.
1039 ??? Should we handle 16-bit operand-sizes here? */
1041 /* `movb imm8, %al' and `movb imm8, %ah' */
1042 /* `movb imm8, %cl' and `movb imm8, %ch' */
1043 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1044 /* `movb imm8, %dl' and `movb imm8, %dh' */
1045 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1046 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1047 { 5, { 0xb8 }, { 0xfe } },
1048 /* `movl imm32, %edx' */
1049 { 5, { 0xba }, { 0xff } },
1051 /* Check for `mov imm32, r32'. Note that there is an alternative
1052 encoding for `mov m32, %eax'.
1054 ??? Should we handle SIB adressing here?
1055 ??? Should we handle 16-bit operand-sizes here? */
1057 /* `movl m32, %eax' */
1058 { 5, { 0xa1 }, { 0xff } },
1059 /* `movl m32, %eax' and `mov; m32, %ecx' */
1060 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1061 /* `movl m32, %edx' */
1062 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1064 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1065 Because of the symmetry, there are actually two ways to encode
1066 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1067 opcode bytes 0x31 and 0x33 for `xorl'. */
1069 /* `subl %eax, %eax' */
1070 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1071 /* `subl %ecx, %ecx' */
1072 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1073 /* `subl %edx, %edx' */
1074 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1075 /* `xorl %eax, %eax' */
1076 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1077 /* `xorl %ecx, %ecx' */
1078 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1079 /* `xorl %edx, %edx' */
1080 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1085 /* Check whether PC points to a no-op instruction. */
1087 i386_skip_noop (CORE_ADDR pc)
1092 target_read_memory (pc, &op, 1);
1097 /* Ignore `nop' instruction. */
1101 target_read_memory (pc, &op, 1);
1104 /* Ignore no-op instruction `mov %edi, %edi'.
1105 Microsoft system dlls often start with
1106 a `mov %edi,%edi' instruction.
1107 The 5 bytes before the function start are
1108 filled with `nop' instructions.
1109 This pattern can be used for hot-patching:
1110 The `mov %edi, %edi' instruction can be replaced by a
1111 near jump to the location of the 5 `nop' instructions
1112 which can be replaced by a 32-bit jump to anywhere
1113 in the 32-bit address space. */
1115 else if (op == 0x8b)
1117 target_read_memory (pc + 1, &op, 1);
1121 target_read_memory (pc, &op, 1);
1129 /* Check whether PC points at a code that sets up a new stack frame.
1130 If so, it updates CACHE and returns the address of the first
1131 instruction after the sequence that sets up the frame or LIMIT,
1132 whichever is smaller. If we don't recognize the code, return PC. */
1135 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1136 CORE_ADDR pc, CORE_ADDR limit,
1137 struct i386_frame_cache *cache)
1139 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1140 struct i386_insn *insn;
1147 target_read_memory (pc, &op, 1);
1149 if (op == 0x55) /* pushl %ebp */
1151 /* Take into account that we've executed the `pushl %ebp' that
1152 starts this instruction sequence. */
1153 cache->saved_regs[I386_EBP_REGNUM] = 0;
1154 cache->sp_offset += 4;
1157 /* If that's all, return now. */
1161 /* Check for some special instructions that might be migrated by
1162 GCC into the prologue and skip them. At this point in the
1163 prologue, code should only touch the scratch registers %eax,
1164 %ecx and %edx, so while the number of posibilities is sheer,
1167 Make sure we only skip these instructions if we later see the
1168 `movl %esp, %ebp' that actually sets up the frame. */
1169 while (pc + skip < limit)
1171 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1178 /* If that's all, return now. */
1179 if (limit <= pc + skip)
1182 target_read_memory (pc + skip, &op, 1);
1184 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1188 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1193 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1201 /* OK, we actually have a frame. We just don't know how large
1202 it is yet. Set its size to zero. We'll adjust it if
1203 necessary. We also now commit to skipping the special
1204 instructions mentioned before. */
1208 /* If that's all, return now. */
1212 /* Check for stack adjustment
1216 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1217 reg, so we don't have to worry about a data16 prefix. */
1218 target_read_memory (pc, &op, 1);
1221 /* `subl' with 8-bit immediate. */
1222 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1223 /* Some instruction starting with 0x83 other than `subl'. */
1226 /* `subl' with signed 8-bit immediate (though it wouldn't
1227 make sense to be negative). */
1228 cache->locals = read_memory_integer (pc + 2, 1, byte_order);
1231 else if (op == 0x81)
1233 /* Maybe it is `subl' with a 32-bit immediate. */
1234 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1235 /* Some instruction starting with 0x81 other than `subl'. */
1238 /* It is `subl' with a 32-bit immediate. */
1239 cache->locals = read_memory_integer (pc + 2, 4, byte_order);
1244 /* Some instruction other than `subl'. */
1248 else if (op == 0xc8) /* enter */
1250 cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order);
1257 /* Check whether PC points at code that saves registers on the stack.
1258 If so, it updates CACHE and returns the address of the first
1259 instruction after the register saves or CURRENT_PC, whichever is
1260 smaller. Otherwise, return PC. */
1263 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1264 struct i386_frame_cache *cache)
1266 CORE_ADDR offset = 0;
1270 if (cache->locals > 0)
1271 offset -= cache->locals;
1272 for (i = 0; i < 8 && pc < current_pc; i++)
1274 target_read_memory (pc, &op, 1);
1275 if (op < 0x50 || op > 0x57)
1279 cache->saved_regs[op - 0x50] = offset;
1280 cache->sp_offset += 4;
1287 /* Do a full analysis of the prologue at PC and update CACHE
1288 accordingly. Bail out early if CURRENT_PC is reached. Return the
1289 address where the analysis stopped.
1291 We handle these cases:
1293 The startup sequence can be at the start of the function, or the
1294 function can start with a branch to startup code at the end.
1296 %ebp can be set up with either the 'enter' instruction, or "pushl
1297 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1298 once used in the System V compiler).
1300 Local space is allocated just below the saved %ebp by either the
1301 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1302 16-bit unsigned argument for space to allocate, and the 'addl'
1303 instruction could have either a signed byte, or 32-bit immediate.
1305 Next, the registers used by this function are pushed. With the
1306 System V compiler they will always be in the order: %edi, %esi,
1307 %ebx (and sometimes a harmless bug causes it to also save but not
1308 restore %eax); however, the code below is willing to see the pushes
1309 in any order, and will handle up to 8 of them.
1311 If the setup sequence is at the end of the function, then the next
1312 instruction will be a branch back to the start. */
1315 i386_analyze_prologue (struct gdbarch *gdbarch,
1316 CORE_ADDR pc, CORE_ADDR current_pc,
1317 struct i386_frame_cache *cache)
1319 pc = i386_skip_noop (pc);
1320 pc = i386_follow_jump (gdbarch, pc);
1321 pc = i386_analyze_struct_return (pc, current_pc, cache);
1322 pc = i386_skip_probe (pc);
1323 pc = i386_analyze_stack_align (pc, current_pc, cache);
1324 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1325 return i386_analyze_register_saves (pc, current_pc, cache);
1328 /* Return PC of first real instruction. */
1331 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1333 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1335 static gdb_byte pic_pat[6] =
1337 0xe8, 0, 0, 0, 0, /* call 0x0 */
1338 0x5b, /* popl %ebx */
1340 struct i386_frame_cache cache;
1346 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1347 if (cache.locals < 0)
1350 /* Found valid frame setup. */
1352 /* The native cc on SVR4 in -K PIC mode inserts the following code
1353 to get the address of the global offset table (GOT) into register
1358 movl %ebx,x(%ebp) (optional)
1361 This code is with the rest of the prologue (at the end of the
1362 function), so we have to skip it to get to the first real
1363 instruction at the start of the function. */
1365 for (i = 0; i < 6; i++)
1367 target_read_memory (pc + i, &op, 1);
1368 if (pic_pat[i] != op)
1375 target_read_memory (pc + delta, &op, 1);
1377 if (op == 0x89) /* movl %ebx, x(%ebp) */
1379 op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order);
1381 if (op == 0x5d) /* One byte offset from %ebp. */
1383 else if (op == 0x9d) /* Four byte offset from %ebp. */
1385 else /* Unexpected instruction. */
1388 target_read_memory (pc + delta, &op, 1);
1392 if (delta > 0 && op == 0x81
1393 && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order)
1400 /* If the function starts with a branch (to startup code at the end)
1401 the last instruction should bring us back to the first
1402 instruction of the real code. */
1403 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1404 pc = i386_follow_jump (gdbarch, pc);
1409 /* Check that the code pointed to by PC corresponds to a call to
1410 __main, skip it if so. Return PC otherwise. */
1413 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1415 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1418 target_read_memory (pc, &op, 1);
1423 if (target_read_memory (pc + 1, buf, sizeof buf) == 0)
1425 /* Make sure address is computed correctly as a 32bit
1426 integer even if CORE_ADDR is 64 bit wide. */
1427 struct minimal_symbol *s;
1428 CORE_ADDR call_dest;
1430 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1431 call_dest = call_dest & 0xffffffffU;
1432 s = lookup_minimal_symbol_by_pc (call_dest);
1434 && SYMBOL_LINKAGE_NAME (s) != NULL
1435 && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0)
1443 /* This function is 64-bit safe. */
1446 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1450 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1451 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1455 /* Normal frames. */
1457 static struct i386_frame_cache *
1458 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
1460 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1461 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1462 struct i386_frame_cache *cache;
1469 cache = i386_alloc_frame_cache ();
1470 *this_cache = cache;
1472 /* In principle, for normal frames, %ebp holds the frame pointer,
1473 which holds the base address for the current stack frame.
1474 However, for functions that don't need it, the frame pointer is
1475 optional. For these "frameless" functions the frame pointer is
1476 actually the frame pointer of the calling frame. Signal
1477 trampolines are just a special case of a "frameless" function.
1478 They (usually) share their frame pointer with the frame that was
1479 in progress when the signal occurred. */
1481 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1482 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1483 if (cache->base == 0)
1486 /* For normal frames, %eip is stored at 4(%ebp). */
1487 cache->saved_regs[I386_EIP_REGNUM] = 4;
1489 cache->pc = get_frame_func (this_frame);
1491 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
1494 if (cache->saved_sp_reg != -1)
1496 /* Saved stack pointer has been saved. */
1497 get_frame_register (this_frame, cache->saved_sp_reg, buf);
1498 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
1501 if (cache->locals < 0)
1503 /* We didn't find a valid frame, which means that CACHE->base
1504 currently holds the frame pointer for our calling frame. If
1505 we're at the start of a function, or somewhere half-way its
1506 prologue, the function's frame probably hasn't been fully
1507 setup yet. Try to reconstruct the base address for the stack
1508 frame by looking at the stack pointer. For truly "frameless"
1509 functions this might work too. */
1511 if (cache->saved_sp_reg != -1)
1513 /* We're halfway aligning the stack. */
1514 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
1515 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
1517 /* This will be added back below. */
1518 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
1520 else if (cache->pc != 0
1521 || target_read_memory (get_frame_pc (this_frame), buf, 1))
1523 /* We're in a known function, but did not find a frame
1524 setup. Assume that the function does not use %ebp.
1525 Alternatively, we may have jumped to an invalid
1526 address; in that case there is definitely no new
1528 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1529 cache->base = extract_unsigned_integer (buf, 4, byte_order)
1533 /* We're in an unknown function. We could not find the start
1534 of the function to analyze the prologue; our best option is
1535 to assume a typical frame layout with the caller's %ebp
1537 cache->saved_regs[I386_EBP_REGNUM] = 0;
1540 /* Now that we have the base address for the stack frame we can
1541 calculate the value of %esp in the calling frame. */
1542 if (cache->saved_sp == 0)
1543 cache->saved_sp = cache->base + 8;
1545 /* Adjust all the saved registers such that they contain addresses
1546 instead of offsets. */
1547 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1548 if (cache->saved_regs[i] != -1)
1549 cache->saved_regs[i] += cache->base;
1555 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
1556 struct frame_id *this_id)
1558 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1560 /* This marks the outermost frame. */
1561 if (cache->base == 0)
1564 /* See the end of i386_push_dummy_call. */
1565 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
1568 static struct value *
1569 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
1572 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1574 gdb_assert (regnum >= 0);
1576 /* The System V ABI says that:
1578 "The flags register contains the system flags, such as the
1579 direction flag and the carry flag. The direction flag must be
1580 set to the forward (that is, zero) direction before entry and
1581 upon exit from a function. Other user flags have no specified
1582 role in the standard calling sequence and are not preserved."
1584 To guarantee the "upon exit" part of that statement we fake a
1585 saved flags register that has its direction flag cleared.
1587 Note that GCC doesn't seem to rely on the fact that the direction
1588 flag is cleared after a function return; it always explicitly
1589 clears the flag before operations where it matters.
1591 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1592 right thing to do. The way we fake the flags register here makes
1593 it impossible to change it. */
1595 if (regnum == I386_EFLAGS_REGNUM)
1599 val = get_frame_register_unsigned (this_frame, regnum);
1601 return frame_unwind_got_constant (this_frame, regnum, val);
1604 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
1605 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
1607 if (regnum == I386_ESP_REGNUM && cache->saved_sp)
1608 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
1610 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
1611 return frame_unwind_got_memory (this_frame, regnum,
1612 cache->saved_regs[regnum]);
1614 return frame_unwind_got_register (this_frame, regnum, regnum);
1617 static const struct frame_unwind i386_frame_unwind =
1621 i386_frame_prev_register,
1623 default_frame_sniffer
1626 /* Normal frames, but in a function epilogue. */
1628 /* The epilogue is defined here as the 'ret' instruction, which will
1629 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1630 the function's stack frame. */
1633 i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1637 if (target_read_memory (pc, &insn, 1))
1638 return 0; /* Can't read memory at pc. */
1640 if (insn != 0xc3) /* 'ret' instruction. */
1647 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
1648 struct frame_info *this_frame,
1649 void **this_prologue_cache)
1651 if (frame_relative_level (this_frame) == 0)
1652 return i386_in_function_epilogue_p (get_frame_arch (this_frame),
1653 get_frame_pc (this_frame));
1658 static struct i386_frame_cache *
1659 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
1661 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1662 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1663 struct i386_frame_cache *cache;
1669 cache = i386_alloc_frame_cache ();
1670 *this_cache = cache;
1672 /* Cache base will be %esp plus cache->sp_offset (-4). */
1673 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1674 cache->base = extract_unsigned_integer (buf, 4,
1675 byte_order) + cache->sp_offset;
1677 /* Cache pc will be the frame func. */
1678 cache->pc = get_frame_pc (this_frame);
1680 /* The saved %esp will be at cache->base plus 8. */
1681 cache->saved_sp = cache->base + 8;
1683 /* The saved %eip will be at cache->base plus 4. */
1684 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
1690 i386_epilogue_frame_this_id (struct frame_info *this_frame,
1692 struct frame_id *this_id)
1694 struct i386_frame_cache *cache = i386_epilogue_frame_cache (this_frame,
1697 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
1700 static const struct frame_unwind i386_epilogue_frame_unwind =
1703 i386_epilogue_frame_this_id,
1704 i386_frame_prev_register,
1706 i386_epilogue_frame_sniffer
1710 /* Signal trampolines. */
1712 static struct i386_frame_cache *
1713 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
1715 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1716 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1717 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1718 struct i386_frame_cache *cache;
1725 cache = i386_alloc_frame_cache ();
1727 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1728 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
1730 addr = tdep->sigcontext_addr (this_frame);
1731 if (tdep->sc_reg_offset)
1735 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
1737 for (i = 0; i < tdep->sc_num_regs; i++)
1738 if (tdep->sc_reg_offset[i] != -1)
1739 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
1743 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
1744 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
1747 *this_cache = cache;
1752 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
1753 struct frame_id *this_id)
1755 struct i386_frame_cache *cache =
1756 i386_sigtramp_frame_cache (this_frame, this_cache);
1758 /* See the end of i386_push_dummy_call. */
1759 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
1762 static struct value *
1763 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
1764 void **this_cache, int regnum)
1766 /* Make sure we've initialized the cache. */
1767 i386_sigtramp_frame_cache (this_frame, this_cache);
1769 return i386_frame_prev_register (this_frame, this_cache, regnum);
1773 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
1774 struct frame_info *this_frame,
1775 void **this_prologue_cache)
1777 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
1779 /* We shouldn't even bother if we don't have a sigcontext_addr
1781 if (tdep->sigcontext_addr == NULL)
1784 if (tdep->sigtramp_p != NULL)
1786 if (tdep->sigtramp_p (this_frame))
1790 if (tdep->sigtramp_start != 0)
1792 CORE_ADDR pc = get_frame_pc (this_frame);
1794 gdb_assert (tdep->sigtramp_end != 0);
1795 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
1802 static const struct frame_unwind i386_sigtramp_frame_unwind =
1805 i386_sigtramp_frame_this_id,
1806 i386_sigtramp_frame_prev_register,
1808 i386_sigtramp_frame_sniffer
1813 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
1815 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1820 static const struct frame_base i386_frame_base =
1823 i386_frame_base_address,
1824 i386_frame_base_address,
1825 i386_frame_base_address
1828 static struct frame_id
1829 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1833 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
1835 /* See the end of i386_push_dummy_call. */
1836 return frame_id_build (fp + 8, get_frame_pc (this_frame));
1840 /* Figure out where the longjmp will land. Slurp the args out of the
1841 stack. We expect the first arg to be a pointer to the jmp_buf
1842 structure from which we extract the address that we will land at.
1843 This address is copied into PC. This routine returns non-zero on
1847 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1850 CORE_ADDR sp, jb_addr;
1851 struct gdbarch *gdbarch = get_frame_arch (frame);
1852 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1853 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
1855 /* If JB_PC_OFFSET is -1, we have no way to find out where the
1856 longjmp will land. */
1857 if (jb_pc_offset == -1)
1860 get_frame_register (frame, I386_ESP_REGNUM, buf);
1861 sp = extract_unsigned_integer (buf, 4, byte_order);
1862 if (target_read_memory (sp + 4, buf, 4))
1865 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
1866 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
1869 *pc = extract_unsigned_integer (buf, 4, byte_order);
1874 /* Check whether TYPE must be 16-byte-aligned when passed as a
1875 function argument. 16-byte vectors, _Decimal128 and structures or
1876 unions containing such types must be 16-byte-aligned; other
1877 arguments are 4-byte-aligned. */
1880 i386_16_byte_align_p (struct type *type)
1882 type = check_typedef (type);
1883 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
1884 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
1885 && TYPE_LENGTH (type) == 16)
1887 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
1888 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
1889 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1890 || TYPE_CODE (type) == TYPE_CODE_UNION)
1893 for (i = 0; i < TYPE_NFIELDS (type); i++)
1895 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
1903 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1904 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
1905 struct value **args, CORE_ADDR sp, int struct_return,
1906 CORE_ADDR struct_addr)
1908 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1914 /* Determine the total space required for arguments and struct
1915 return address in a first pass (allowing for 16-byte-aligned
1916 arguments), then push arguments in a second pass. */
1918 for (write_pass = 0; write_pass < 2; write_pass++)
1920 int args_space_used = 0;
1921 int have_16_byte_aligned_arg = 0;
1927 /* Push value address. */
1928 store_unsigned_integer (buf, 4, byte_order, struct_addr);
1929 write_memory (sp, buf, 4);
1930 args_space_used += 4;
1936 for (i = 0; i < nargs; i++)
1938 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
1942 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
1943 args_space_used = align_up (args_space_used, 16);
1945 write_memory (sp + args_space_used,
1946 value_contents_all (args[i]), len);
1947 /* The System V ABI says that:
1949 "An argument's size is increased, if necessary, to make it a
1950 multiple of [32-bit] words. This may require tail padding,
1951 depending on the size of the argument."
1953 This makes sure the stack stays word-aligned. */
1954 args_space_used += align_up (len, 4);
1958 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
1960 args_space = align_up (args_space, 16);
1961 have_16_byte_aligned_arg = 1;
1963 args_space += align_up (len, 4);
1969 if (have_16_byte_aligned_arg)
1970 args_space = align_up (args_space, 16);
1975 /* Store return address. */
1977 store_unsigned_integer (buf, 4, byte_order, bp_addr);
1978 write_memory (sp, buf, 4);
1980 /* Finally, update the stack pointer... */
1981 store_unsigned_integer (buf, 4, byte_order, sp);
1982 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
1984 /* ...and fake a frame pointer. */
1985 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
1987 /* MarkK wrote: This "+ 8" is all over the place:
1988 (i386_frame_this_id, i386_sigtramp_frame_this_id,
1989 i386_dummy_id). It's there, since all frame unwinders for
1990 a given target have to agree (within a certain margin) on the
1991 definition of the stack address of a frame. Otherwise frame id
1992 comparison might not work correctly. Since DWARF2/GCC uses the
1993 stack address *before* the function call as a frame's CFA. On
1994 the i386, when %ebp is used as a frame pointer, the offset
1995 between the contents %ebp and the CFA as defined by GCC. */
1999 /* These registers are used for returning integers (and on some
2000 targets also for returning `struct' and `union' values when their
2001 size and alignment match an integer type). */
2002 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2003 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2005 /* Read, for architecture GDBARCH, a function return value of TYPE
2006 from REGCACHE, and copy that into VALBUF. */
2009 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2010 struct regcache *regcache, gdb_byte *valbuf)
2012 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2013 int len = TYPE_LENGTH (type);
2014 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2016 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2018 if (tdep->st0_regnum < 0)
2020 warning (_("Cannot find floating-point return value."));
2021 memset (valbuf, 0, len);
2025 /* Floating-point return values can be found in %st(0). Convert
2026 its contents to the desired type. This is probably not
2027 exactly how it would happen on the target itself, but it is
2028 the best we can do. */
2029 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2030 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
2034 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2035 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2037 if (len <= low_size)
2039 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2040 memcpy (valbuf, buf, len);
2042 else if (len <= (low_size + high_size))
2044 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2045 memcpy (valbuf, buf, low_size);
2046 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2047 memcpy (valbuf + low_size, buf, len - low_size);
2050 internal_error (__FILE__, __LINE__,
2051 _("Cannot extract return value of %d bytes long."), len);
2055 /* Write, for architecture GDBARCH, a function return value of TYPE
2056 from VALBUF into REGCACHE. */
2059 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2060 struct regcache *regcache, const gdb_byte *valbuf)
2062 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2063 int len = TYPE_LENGTH (type);
2065 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2068 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2070 if (tdep->st0_regnum < 0)
2072 warning (_("Cannot set floating-point return value."));
2076 /* Returning floating-point values is a bit tricky. Apart from
2077 storing the return value in %st(0), we have to simulate the
2078 state of the FPU at function return point. */
2080 /* Convert the value found in VALBUF to the extended
2081 floating-point format used by the FPU. This is probably
2082 not exactly how it would happen on the target itself, but
2083 it is the best we can do. */
2084 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
2085 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2087 /* Set the top of the floating-point register stack to 7. The
2088 actual value doesn't really matter, but 7 is what a normal
2089 function return would end up with if the program started out
2090 with a freshly initialized FPU. */
2091 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2093 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2095 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2096 the floating-point register stack to 7, the appropriate value
2097 for the tag word is 0x3fff. */
2098 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2102 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2103 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2105 if (len <= low_size)
2106 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2107 else if (len <= (low_size + high_size))
2109 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2110 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
2111 len - low_size, valbuf + low_size);
2114 internal_error (__FILE__, __LINE__,
2115 _("Cannot store return value of %d bytes long."), len);
2120 /* This is the variable that is set with "set struct-convention", and
2121 its legitimate values. */
2122 static const char default_struct_convention[] = "default";
2123 static const char pcc_struct_convention[] = "pcc";
2124 static const char reg_struct_convention[] = "reg";
2125 static const char *valid_conventions[] =
2127 default_struct_convention,
2128 pcc_struct_convention,
2129 reg_struct_convention,
2132 static const char *struct_convention = default_struct_convention;
2134 /* Return non-zero if TYPE, which is assumed to be a structure,
2135 a union type, or an array type, should be returned in registers
2136 for architecture GDBARCH. */
2139 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2141 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2142 enum type_code code = TYPE_CODE (type);
2143 int len = TYPE_LENGTH (type);
2145 gdb_assert (code == TYPE_CODE_STRUCT
2146 || code == TYPE_CODE_UNION
2147 || code == TYPE_CODE_ARRAY);
2149 if (struct_convention == pcc_struct_convention
2150 || (struct_convention == default_struct_convention
2151 && tdep->struct_return == pcc_struct_return))
2154 /* Structures consisting of a single `float', `double' or 'long
2155 double' member are returned in %st(0). */
2156 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2158 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2159 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2160 return (len == 4 || len == 8 || len == 12);
2163 return (len == 1 || len == 2 || len == 4 || len == 8);
2166 /* Determine, for architecture GDBARCH, how a return value of TYPE
2167 should be returned. If it is supposed to be returned in registers,
2168 and READBUF is non-zero, read the appropriate value from REGCACHE,
2169 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2170 from WRITEBUF into REGCACHE. */
2172 static enum return_value_convention
2173 i386_return_value (struct gdbarch *gdbarch, struct type *func_type,
2174 struct type *type, struct regcache *regcache,
2175 gdb_byte *readbuf, const gdb_byte *writebuf)
2177 enum type_code code = TYPE_CODE (type);
2179 if (((code == TYPE_CODE_STRUCT
2180 || code == TYPE_CODE_UNION
2181 || code == TYPE_CODE_ARRAY)
2182 && !i386_reg_struct_return_p (gdbarch, type))
2183 /* 128-bit decimal float uses the struct return convention. */
2184 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2186 /* The System V ABI says that:
2188 "A function that returns a structure or union also sets %eax
2189 to the value of the original address of the caller's area
2190 before it returns. Thus when the caller receives control
2191 again, the address of the returned object resides in register
2192 %eax and can be used to access the object."
2194 So the ABI guarantees that we can always find the return
2195 value just after the function has returned. */
2197 /* Note that the ABI doesn't mention functions returning arrays,
2198 which is something possible in certain languages such as Ada.
2199 In this case, the value is returned as if it was wrapped in
2200 a record, so the convention applied to records also applies
2207 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2208 read_memory (addr, readbuf, TYPE_LENGTH (type));
2211 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2214 /* This special case is for structures consisting of a single
2215 `float', `double' or 'long double' member. These structures are
2216 returned in %st(0). For these structures, we call ourselves
2217 recursively, changing TYPE into the type of the first member of
2218 the structure. Since that should work for all structures that
2219 have only one member, we don't bother to check the member's type
2221 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2223 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2224 return i386_return_value (gdbarch, func_type, type, regcache,
2229 i386_extract_return_value (gdbarch, type, regcache, readbuf);
2231 i386_store_return_value (gdbarch, type, regcache, writebuf);
2233 return RETURN_VALUE_REGISTER_CONVENTION;
2238 i387_ext_type (struct gdbarch *gdbarch)
2240 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2242 if (!tdep->i387_ext_type)
2244 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
2245 gdb_assert (tdep->i387_ext_type != NULL);
2248 return tdep->i387_ext_type;
2251 /* Construct vector type for pseudo YMM registers. We can't use
2252 tdesc_find_type since YMM isn't described in target description. */
2254 static struct type *
2255 i386_ymm_type (struct gdbarch *gdbarch)
2257 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2259 if (!tdep->i386_ymm_type)
2261 const struct builtin_type *bt = builtin_type (gdbarch);
2263 /* The type we're building is this: */
2265 union __gdb_builtin_type_vec256i
2267 int128_t uint128[2];
2268 int64_t v2_int64[4];
2269 int32_t v4_int32[8];
2270 int16_t v8_int16[16];
2271 int8_t v16_int8[32];
2272 double v2_double[4];
2279 t = arch_composite_type (gdbarch,
2280 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
2281 append_composite_type_field (t, "v8_float",
2282 init_vector_type (bt->builtin_float, 8));
2283 append_composite_type_field (t, "v4_double",
2284 init_vector_type (bt->builtin_double, 4));
2285 append_composite_type_field (t, "v32_int8",
2286 init_vector_type (bt->builtin_int8, 32));
2287 append_composite_type_field (t, "v16_int16",
2288 init_vector_type (bt->builtin_int16, 16));
2289 append_composite_type_field (t, "v8_int32",
2290 init_vector_type (bt->builtin_int32, 8));
2291 append_composite_type_field (t, "v4_int64",
2292 init_vector_type (bt->builtin_int64, 4));
2293 append_composite_type_field (t, "v2_int128",
2294 init_vector_type (bt->builtin_int128, 2));
2296 TYPE_VECTOR (t) = 1;
2297 TYPE_NAME (t) = "builtin_type_vec128i";
2298 tdep->i386_ymm_type = t;
2301 return tdep->i386_ymm_type;
2304 /* Construct vector type for MMX registers. */
2305 static struct type *
2306 i386_mmx_type (struct gdbarch *gdbarch)
2308 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2310 if (!tdep->i386_mmx_type)
2312 const struct builtin_type *bt = builtin_type (gdbarch);
2314 /* The type we're building is this: */
2316 union __gdb_builtin_type_vec64i
2319 int32_t v2_int32[2];
2320 int16_t v4_int16[4];
2327 t = arch_composite_type (gdbarch,
2328 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
2330 append_composite_type_field (t, "uint64", bt->builtin_int64);
2331 append_composite_type_field (t, "v2_int32",
2332 init_vector_type (bt->builtin_int32, 2));
2333 append_composite_type_field (t, "v4_int16",
2334 init_vector_type (bt->builtin_int16, 4));
2335 append_composite_type_field (t, "v8_int8",
2336 init_vector_type (bt->builtin_int8, 8));
2338 TYPE_VECTOR (t) = 1;
2339 TYPE_NAME (t) = "builtin_type_vec64i";
2340 tdep->i386_mmx_type = t;
2343 return tdep->i386_mmx_type;
2346 /* Return the GDB type object for the "standard" data type of data in
2349 static struct type *
2350 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2352 if (i386_mmx_regnum_p (gdbarch, regnum))
2353 return i386_mmx_type (gdbarch);
2354 else if (i386_ymm_regnum_p (gdbarch, regnum))
2355 return i386_ymm_type (gdbarch);
2358 const struct builtin_type *bt = builtin_type (gdbarch);
2359 if (i386_byte_regnum_p (gdbarch, regnum))
2360 return bt->builtin_int8;
2361 else if (i386_word_regnum_p (gdbarch, regnum))
2362 return bt->builtin_int16;
2363 else if (i386_dword_regnum_p (gdbarch, regnum))
2364 return bt->builtin_int32;
2367 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2370 /* Map a cooked register onto a raw register or memory. For the i386,
2371 the MMX registers need to be mapped onto floating point registers. */
2374 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
2376 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
2381 mmxreg = regnum - tdep->mm0_regnum;
2382 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2383 tos = (fstat >> 11) & 0x7;
2384 fpreg = (mmxreg + tos) % 8;
2386 return (I387_ST0_REGNUM (tdep) + fpreg);
2390 i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2391 int regnum, gdb_byte *buf)
2393 gdb_byte raw_buf[MAX_REGISTER_SIZE];
2395 if (i386_mmx_regnum_p (gdbarch, regnum))
2397 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2399 /* Extract (always little endian). */
2400 regcache_raw_read (regcache, fpnum, raw_buf);
2401 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
2405 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2407 if (i386_ymm_regnum_p (gdbarch, regnum))
2409 regnum -= tdep->ymm0_regnum;
2411 /* Extract (always little endian). Read lower 128bits. */
2412 regcache_raw_read (regcache,
2413 I387_XMM0_REGNUM (tdep) + regnum,
2415 memcpy (buf, raw_buf, 16);
2416 /* Read upper 128bits. */
2417 regcache_raw_read (regcache,
2418 tdep->ymm0h_regnum + regnum,
2420 memcpy (buf + 16, raw_buf, 16);
2422 else if (i386_word_regnum_p (gdbarch, regnum))
2424 int gpnum = regnum - tdep->ax_regnum;
2426 /* Extract (always little endian). */
2427 regcache_raw_read (regcache, gpnum, raw_buf);
2428 memcpy (buf, raw_buf, 2);
2430 else if (i386_byte_regnum_p (gdbarch, regnum))
2432 /* Check byte pseudo registers last since this function will
2433 be called from amd64_pseudo_register_read, which handles
2434 byte pseudo registers differently. */
2435 int gpnum = regnum - tdep->al_regnum;
2437 /* Extract (always little endian). We read both lower and
2439 regcache_raw_read (regcache, gpnum % 4, raw_buf);
2441 memcpy (buf, raw_buf + 1, 1);
2443 memcpy (buf, raw_buf, 1);
2446 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2451 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2452 int regnum, const gdb_byte *buf)
2454 gdb_byte raw_buf[MAX_REGISTER_SIZE];
2456 if (i386_mmx_regnum_p (gdbarch, regnum))
2458 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2461 regcache_raw_read (regcache, fpnum, raw_buf);
2462 /* ... Modify ... (always little endian). */
2463 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
2465 regcache_raw_write (regcache, fpnum, raw_buf);
2469 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2471 if (i386_ymm_regnum_p (gdbarch, regnum))
2473 regnum -= tdep->ymm0_regnum;
2475 /* ... Write lower 128bits. */
2476 regcache_raw_write (regcache,
2477 I387_XMM0_REGNUM (tdep) + regnum,
2479 /* ... Write upper 128bits. */
2480 regcache_raw_write (regcache,
2481 tdep->ymm0h_regnum + regnum,
2484 else if (i386_word_regnum_p (gdbarch, regnum))
2486 int gpnum = regnum - tdep->ax_regnum;
2489 regcache_raw_read (regcache, gpnum, raw_buf);
2490 /* ... Modify ... (always little endian). */
2491 memcpy (raw_buf, buf, 2);
2493 regcache_raw_write (regcache, gpnum, raw_buf);
2495 else if (i386_byte_regnum_p (gdbarch, regnum))
2497 /* Check byte pseudo registers last since this function will
2498 be called from amd64_pseudo_register_read, which handles
2499 byte pseudo registers differently. */
2500 int gpnum = regnum - tdep->al_regnum;
2502 /* Read ... We read both lower and upper registers. */
2503 regcache_raw_read (regcache, gpnum % 4, raw_buf);
2504 /* ... Modify ... (always little endian). */
2506 memcpy (raw_buf + 1, buf, 1);
2508 memcpy (raw_buf, buf, 1);
2510 regcache_raw_write (regcache, gpnum % 4, raw_buf);
2513 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2518 /* Return the register number of the register allocated by GCC after
2519 REGNUM, or -1 if there is no such register. */
2522 i386_next_regnum (int regnum)
2524 /* GCC allocates the registers in the order:
2526 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2528 Since storing a variable in %esp doesn't make any sense we return
2529 -1 for %ebp and for %esp itself. */
2530 static int next_regnum[] =
2532 I386_EDX_REGNUM, /* Slot for %eax. */
2533 I386_EBX_REGNUM, /* Slot for %ecx. */
2534 I386_ECX_REGNUM, /* Slot for %edx. */
2535 I386_ESI_REGNUM, /* Slot for %ebx. */
2536 -1, -1, /* Slots for %esp and %ebp. */
2537 I386_EDI_REGNUM, /* Slot for %esi. */
2538 I386_EBP_REGNUM /* Slot for %edi. */
2541 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
2542 return next_regnum[regnum];
2547 /* Return nonzero if a value of type TYPE stored in register REGNUM
2548 needs any special handling. */
2551 i386_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type)
2553 int len = TYPE_LENGTH (type);
2555 /* Values may be spread across multiple registers. Most debugging
2556 formats aren't expressive enough to specify the locations, so
2557 some heuristics is involved. Right now we only handle types that
2558 have a length that is a multiple of the word size, since GCC
2559 doesn't seem to put any other types into registers. */
2560 if (len > 4 && len % 4 == 0)
2562 int last_regnum = regnum;
2566 last_regnum = i386_next_regnum (last_regnum);
2570 if (last_regnum != -1)
2574 return i387_convert_register_p (gdbarch, regnum, type);
2577 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2578 return its contents in TO. */
2581 i386_register_to_value (struct frame_info *frame, int regnum,
2582 struct type *type, gdb_byte *to)
2584 struct gdbarch *gdbarch = get_frame_arch (frame);
2585 int len = TYPE_LENGTH (type);
2587 /* FIXME: kettenis/20030609: What should we do if REGNUM isn't
2588 available in FRAME (i.e. if it wasn't saved)? */
2590 if (i386_fp_regnum_p (gdbarch, regnum))
2592 i387_register_to_value (frame, regnum, type, to);
2596 /* Read a value spread across multiple registers. */
2598 gdb_assert (len > 4 && len % 4 == 0);
2602 gdb_assert (regnum != -1);
2603 gdb_assert (register_size (gdbarch, regnum) == 4);
2605 get_frame_register (frame, regnum, to);
2606 regnum = i386_next_regnum (regnum);
2612 /* Write the contents FROM of a value of type TYPE into register
2613 REGNUM in frame FRAME. */
2616 i386_value_to_register (struct frame_info *frame, int regnum,
2617 struct type *type, const gdb_byte *from)
2619 int len = TYPE_LENGTH (type);
2621 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
2623 i387_value_to_register (frame, regnum, type, from);
2627 /* Write a value spread across multiple registers. */
2629 gdb_assert (len > 4 && len % 4 == 0);
2633 gdb_assert (regnum != -1);
2634 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
2636 put_frame_register (frame, regnum, from);
2637 regnum = i386_next_regnum (regnum);
2643 /* Supply register REGNUM from the buffer specified by GREGS and LEN
2644 in the general-purpose register set REGSET to register cache
2645 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2648 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
2649 int regnum, const void *gregs, size_t len)
2651 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2652 const gdb_byte *regs = gregs;
2655 gdb_assert (len == tdep->sizeof_gregset);
2657 for (i = 0; i < tdep->gregset_num_regs; i++)
2659 if ((regnum == i || regnum == -1)
2660 && tdep->gregset_reg_offset[i] != -1)
2661 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
2665 /* Collect register REGNUM from the register cache REGCACHE and store
2666 it in the buffer specified by GREGS and LEN as described by the
2667 general-purpose register set REGSET. If REGNUM is -1, do this for
2668 all registers in REGSET. */
2671 i386_collect_gregset (const struct regset *regset,
2672 const struct regcache *regcache,
2673 int regnum, void *gregs, size_t len)
2675 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2676 gdb_byte *regs = gregs;
2679 gdb_assert (len == tdep->sizeof_gregset);
2681 for (i = 0; i < tdep->gregset_num_regs; i++)
2683 if ((regnum == i || regnum == -1)
2684 && tdep->gregset_reg_offset[i] != -1)
2685 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
2689 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2690 in the floating-point register set REGSET to register cache
2691 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2694 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
2695 int regnum, const void *fpregs, size_t len)
2697 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2699 if (len == I387_SIZEOF_FXSAVE)
2701 i387_supply_fxsave (regcache, regnum, fpregs);
2705 gdb_assert (len == tdep->sizeof_fpregset);
2706 i387_supply_fsave (regcache, regnum, fpregs);
2709 /* Collect register REGNUM from the register cache REGCACHE and store
2710 it in the buffer specified by FPREGS and LEN as described by the
2711 floating-point register set REGSET. If REGNUM is -1, do this for
2712 all registers in REGSET. */
2715 i386_collect_fpregset (const struct regset *regset,
2716 const struct regcache *regcache,
2717 int regnum, void *fpregs, size_t len)
2719 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2721 if (len == I387_SIZEOF_FXSAVE)
2723 i387_collect_fxsave (regcache, regnum, fpregs);
2727 gdb_assert (len == tdep->sizeof_fpregset);
2728 i387_collect_fsave (regcache, regnum, fpregs);
2731 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
2734 i386_supply_xstateregset (const struct regset *regset,
2735 struct regcache *regcache, int regnum,
2736 const void *xstateregs, size_t len)
2738 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2739 i387_supply_xsave (regcache, regnum, xstateregs);
2742 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
2745 i386_collect_xstateregset (const struct regset *regset,
2746 const struct regcache *regcache,
2747 int regnum, void *xstateregs, size_t len)
2749 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2750 i387_collect_xsave (regcache, regnum, xstateregs, 1);
2753 /* Return the appropriate register set for the core section identified
2754 by SECT_NAME and SECT_SIZE. */
2756 const struct regset *
2757 i386_regset_from_core_section (struct gdbarch *gdbarch,
2758 const char *sect_name, size_t sect_size)
2760 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2762 if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset)
2764 if (tdep->gregset == NULL)
2765 tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset,
2766 i386_collect_gregset);
2767 return tdep->gregset;
2770 if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
2771 || (strcmp (sect_name, ".reg-xfp") == 0
2772 && sect_size == I387_SIZEOF_FXSAVE))
2774 if (tdep->fpregset == NULL)
2775 tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset,
2776 i386_collect_fpregset);
2777 return tdep->fpregset;
2780 if (strcmp (sect_name, ".reg-xstate") == 0)
2782 if (tdep->xstateregset == NULL)
2783 tdep->xstateregset = regset_alloc (gdbarch,
2784 i386_supply_xstateregset,
2785 i386_collect_xstateregset);
2787 return tdep->xstateregset;
2794 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
2797 i386_pe_skip_trampoline_code (struct frame_info *frame,
2798 CORE_ADDR pc, char *name)
2800 struct gdbarch *gdbarch = get_frame_arch (frame);
2801 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2804 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
2806 unsigned long indirect =
2807 read_memory_unsigned_integer (pc + 2, 4, byte_order);
2808 struct minimal_symbol *indsym =
2809 indirect ? lookup_minimal_symbol_by_pc (indirect) : 0;
2810 char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0;
2814 if (strncmp (symname, "__imp_", 6) == 0
2815 || strncmp (symname, "_imp_", 5) == 0)
2817 read_memory_unsigned_integer (indirect, 4, byte_order);
2820 return 0; /* Not a trampoline. */
2824 /* Return whether the THIS_FRAME corresponds to a sigtramp
2828 i386_sigtramp_p (struct frame_info *this_frame)
2830 CORE_ADDR pc = get_frame_pc (this_frame);
2833 find_pc_partial_function (pc, &name, NULL, NULL);
2834 return (name && strcmp ("_sigtramp", name) == 0);
2838 /* We have two flavours of disassembly. The machinery on this page
2839 deals with switching between those. */
2842 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
2844 gdb_assert (disassembly_flavor == att_flavor
2845 || disassembly_flavor == intel_flavor);
2847 /* FIXME: kettenis/20020915: Until disassembler_options is properly
2848 constified, cast to prevent a compiler warning. */
2849 info->disassembler_options = (char *) disassembly_flavor;
2851 return print_insn_i386 (pc, info);
2855 /* There are a few i386 architecture variants that differ only
2856 slightly from the generic i386 target. For now, we don't give them
2857 their own source file, but include them here. As a consequence,
2858 they'll always be included. */
2860 /* System V Release 4 (SVR4). */
2862 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
2866 i386_svr4_sigtramp_p (struct frame_info *this_frame)
2868 CORE_ADDR pc = get_frame_pc (this_frame);
2871 /* UnixWare uses _sigacthandler. The origin of the other symbols is
2872 currently unknown. */
2873 find_pc_partial_function (pc, &name, NULL, NULL);
2874 return (name && (strcmp ("_sigreturn", name) == 0
2875 || strcmp ("_sigacthandler", name) == 0
2876 || strcmp ("sigvechandler", name) == 0));
2879 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
2880 address of the associated sigcontext (ucontext) structure. */
2883 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
2885 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2886 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2890 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2891 sp = extract_unsigned_integer (buf, 4, byte_order);
2893 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
2900 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2902 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
2903 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
2906 /* System V Release 4 (SVR4). */
2909 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2911 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2913 /* System V Release 4 uses ELF. */
2914 i386_elf_init_abi (info, gdbarch);
2916 /* System V Release 4 has shared libraries. */
2917 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
2919 tdep->sigtramp_p = i386_svr4_sigtramp_p;
2920 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
2921 tdep->sc_pc_offset = 36 + 14 * 4;
2922 tdep->sc_sp_offset = 36 + 17 * 4;
2924 tdep->jb_pc_offset = 20;
2930 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2932 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2934 /* DJGPP doesn't have any special frames for signal handlers. */
2935 tdep->sigtramp_p = NULL;
2937 tdep->jb_pc_offset = 36;
2939 /* DJGPP does not support the SSE registers. */
2940 tdep->num_xmm_regs = 0;
2941 set_gdbarch_num_regs (gdbarch, I386_NUM_GREGS + I387_NUM_REGS);
2943 /* Native compiler is GCC, which uses the SVR4 register numbering
2944 even in COFF and STABS. See the comment in i386_gdbarch_init,
2945 before the calls to set_gdbarch_stab_reg_to_regnum and
2946 set_gdbarch_sdb_reg_to_regnum. */
2947 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
2948 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
2952 /* i386 register groups. In addition to the normal groups, add "mmx"
2955 static struct reggroup *i386_sse_reggroup;
2956 static struct reggroup *i386_mmx_reggroup;
2959 i386_init_reggroups (void)
2961 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
2962 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
2966 i386_add_reggroups (struct gdbarch *gdbarch)
2968 reggroup_add (gdbarch, i386_sse_reggroup);
2969 reggroup_add (gdbarch, i386_mmx_reggroup);
2970 reggroup_add (gdbarch, general_reggroup);
2971 reggroup_add (gdbarch, float_reggroup);
2972 reggroup_add (gdbarch, all_reggroup);
2973 reggroup_add (gdbarch, save_reggroup);
2974 reggroup_add (gdbarch, restore_reggroup);
2975 reggroup_add (gdbarch, vector_reggroup);
2976 reggroup_add (gdbarch, system_reggroup);
2980 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2981 struct reggroup *group)
2983 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2984 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
2985 ymm_regnum_p, ymmh_regnum_p;
2987 /* Don't include pseudo registers, except for MMX, in any register
2989 if (i386_byte_regnum_p (gdbarch, regnum))
2992 if (i386_word_regnum_p (gdbarch, regnum))
2995 if (i386_dword_regnum_p (gdbarch, regnum))
2998 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
2999 if (group == i386_mmx_reggroup)
3000 return mmx_regnum_p;
3002 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
3003 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
3004 if (group == i386_sse_reggroup)
3005 return xmm_regnum_p || mxcsr_regnum_p;
3007 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
3008 if (group == vector_reggroup)
3009 return (mmx_regnum_p
3013 && ((tdep->xcr0 & I386_XSTATE_AVX_MASK)
3014 == I386_XSTATE_SSE_MASK)));
3016 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
3017 || i386_fpc_regnum_p (gdbarch, regnum));
3018 if (group == float_reggroup)
3021 /* For "info reg all", don't include upper YMM registers nor XMM
3022 registers when AVX is supported. */
3023 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
3024 if (group == all_reggroup
3026 && (tdep->xcr0 & I386_XSTATE_AVX))
3030 if (group == general_reggroup)
3031 return (!fp_regnum_p
3038 return default_register_reggroup_p (gdbarch, regnum, group);
3042 /* Get the ARGIth function argument for the current function. */
3045 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
3048 struct gdbarch *gdbarch = get_frame_arch (frame);
3049 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3050 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
3051 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
3055 i386_skip_permanent_breakpoint (struct regcache *regcache)
3057 CORE_ADDR current_pc = regcache_read_pc (regcache);
3059 /* On i386, breakpoint is exactly 1 byte long, so we just
3060 adjust the PC in the regcache. */
3062 regcache_write_pc (regcache, current_pc);
3066 #define PREFIX_REPZ 0x01
3067 #define PREFIX_REPNZ 0x02
3068 #define PREFIX_LOCK 0x04
3069 #define PREFIX_DATA 0x08
3070 #define PREFIX_ADDR 0x10
3082 /* i386 arith/logic operations */
3095 struct i386_record_s
3097 struct gdbarch *gdbarch;
3098 struct regcache *regcache;
3099 CORE_ADDR orig_addr;
3105 uint8_t mod, reg, rm;
3114 /* Parse "modrm" part in current memory address that irp->addr point to
3115 Return -1 if something wrong. */
3118 i386_record_modrm (struct i386_record_s *irp)
3120 struct gdbarch *gdbarch = irp->gdbarch;
3122 if (target_read_memory (irp->addr, &irp->modrm, 1))
3125 printf_unfiltered (_("Process record: error reading memory at "
3126 "addr %s len = 1.\n"),
3127 paddress (gdbarch, irp->addr));
3131 irp->mod = (irp->modrm >> 6) & 3;
3132 irp->reg = (irp->modrm >> 3) & 7;
3133 irp->rm = irp->modrm & 7;
3138 /* Get the memory address that current instruction write to and set it to
3139 the argument "addr".
3140 Return -1 if something wrong. */
3143 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
3145 struct gdbarch *gdbarch = irp->gdbarch;
3146 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3158 uint8_t base = irp->rm;
3163 if (target_read_memory (irp->addr, &byte, 1))
3166 printf_unfiltered (_("Process record: error reading memory "
3167 "at addr %s len = 1.\n"),
3168 paddress (gdbarch, irp->addr));
3172 scale = (byte >> 6) & 3;
3173 index = ((byte >> 3) & 7) | irp->rex_x;
3181 if ((base & 7) == 5)
3184 if (target_read_memory (irp->addr, buf, 4))
3187 printf_unfiltered (_("Process record: error reading "
3188 "memory at addr %s len = 4.\n"),
3189 paddress (gdbarch, irp->addr));
3193 *addr = extract_signed_integer (buf, 4, byte_order);
3194 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
3195 *addr += irp->addr + irp->rip_offset;
3199 if (target_read_memory (irp->addr, buf, 1))
3202 printf_unfiltered (_("Process record: error reading memory "
3203 "at addr %s len = 1.\n"),
3204 paddress (gdbarch, irp->addr));
3208 *addr = (int8_t) buf[0];
3211 if (target_read_memory (irp->addr, buf, 4))
3214 printf_unfiltered (_("Process record: error reading memory "
3215 "at addr %s len = 4.\n"),
3216 paddress (gdbarch, irp->addr));
3219 *addr = extract_signed_integer (buf, 4, byte_order);
3227 if (base == 4 && irp->popl_esp_hack)
3228 *addr += irp->popl_esp_hack;
3229 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
3232 if (irp->aflag == 2)
3237 *addr = (uint32_t) (offset64 + *addr);
3239 if (havesib && (index != 4 || scale != 0))
3241 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
3243 if (irp->aflag == 2)
3244 *addr += offset64 << scale;
3246 *addr = (uint32_t) (*addr + (offset64 << scale));
3257 if (target_read_memory (irp->addr, buf, 2))
3260 printf_unfiltered (_("Process record: error reading "
3261 "memory at addr %s len = 2.\n"),
3262 paddress (gdbarch, irp->addr));
3266 *addr = extract_signed_integer (buf, 2, byte_order);
3272 if (target_read_memory (irp->addr, buf, 1))
3275 printf_unfiltered (_("Process record: error reading memory "
3276 "at addr %s len = 1.\n"),
3277 paddress (gdbarch, irp->addr));
3281 *addr = (int8_t) buf[0];
3284 if (target_read_memory (irp->addr, buf, 2))
3287 printf_unfiltered (_("Process record: error reading memory "
3288 "at addr %s len = 2.\n"),
3289 paddress (gdbarch, irp->addr));
3293 *addr = extract_signed_integer (buf, 2, byte_order);
3300 regcache_raw_read_unsigned (irp->regcache,
3301 irp->regmap[X86_RECORD_REBX_REGNUM],
3303 *addr = (uint32_t) (*addr + offset64);
3304 regcache_raw_read_unsigned (irp->regcache,
3305 irp->regmap[X86_RECORD_RESI_REGNUM],
3307 *addr = (uint32_t) (*addr + offset64);
3310 regcache_raw_read_unsigned (irp->regcache,
3311 irp->regmap[X86_RECORD_REBX_REGNUM],
3313 *addr = (uint32_t) (*addr + offset64);
3314 regcache_raw_read_unsigned (irp->regcache,
3315 irp->regmap[X86_RECORD_REDI_REGNUM],
3317 *addr = (uint32_t) (*addr + offset64);
3320 regcache_raw_read_unsigned (irp->regcache,
3321 irp->regmap[X86_RECORD_REBP_REGNUM],
3323 *addr = (uint32_t) (*addr + offset64);
3324 regcache_raw_read_unsigned (irp->regcache,
3325 irp->regmap[X86_RECORD_RESI_REGNUM],
3327 *addr = (uint32_t) (*addr + offset64);
3330 regcache_raw_read_unsigned (irp->regcache,
3331 irp->regmap[X86_RECORD_REBP_REGNUM],
3333 *addr = (uint32_t) (*addr + offset64);
3334 regcache_raw_read_unsigned (irp->regcache,
3335 irp->regmap[X86_RECORD_REDI_REGNUM],
3337 *addr = (uint32_t) (*addr + offset64);
3340 regcache_raw_read_unsigned (irp->regcache,
3341 irp->regmap[X86_RECORD_RESI_REGNUM],
3343 *addr = (uint32_t) (*addr + offset64);
3346 regcache_raw_read_unsigned (irp->regcache,
3347 irp->regmap[X86_RECORD_REDI_REGNUM],
3349 *addr = (uint32_t) (*addr + offset64);
3352 regcache_raw_read_unsigned (irp->regcache,
3353 irp->regmap[X86_RECORD_REBP_REGNUM],
3355 *addr = (uint32_t) (*addr + offset64);
3358 regcache_raw_read_unsigned (irp->regcache,
3359 irp->regmap[X86_RECORD_REBX_REGNUM],
3361 *addr = (uint32_t) (*addr + offset64);
3371 /* Record the value of the memory that willbe changed in current instruction
3372 to "record_arch_list".
3373 Return -1 if something wrong. */
3376 i386_record_lea_modrm (struct i386_record_s *irp)
3378 struct gdbarch *gdbarch = irp->gdbarch;
3381 if (irp->override >= 0)
3383 warning (_("Process record ignores the memory change "
3384 "of instruction at address %s because it "
3385 "can't get the value of the segment register."),
3386 paddress (gdbarch, irp->orig_addr));
3390 if (i386_record_lea_modrm_addr (irp, &addr))
3393 if (record_arch_list_add_mem (addr, 1 << irp->ot))
3399 /* Record the push operation to "record_arch_list".
3400 Return -1 if something wrong. */
3403 i386_record_push (struct i386_record_s *irp, int size)
3407 if (record_arch_list_add_reg (irp->regcache,
3408 irp->regmap[X86_RECORD_RESP_REGNUM]))
3410 regcache_raw_read_unsigned (irp->regcache,
3411 irp->regmap[X86_RECORD_RESP_REGNUM],
3413 if (record_arch_list_add_mem ((CORE_ADDR) addr - size, size))
3420 /* Defines contents to record. */
3421 #define I386_SAVE_FPU_REGS 0xfffd
3422 #define I386_SAVE_FPU_ENV 0xfffe
3423 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3425 /* Record the value of floating point registers which will be changed by the
3426 current instruction to "record_arch_list". Return -1 if something is wrong.
3429 static int i386_record_floats (struct gdbarch *gdbarch,
3430 struct i386_record_s *ir,
3433 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3436 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3437 happen. Currently we store st0-st7 registers, but we need not store all
3438 registers all the time, in future we use ftag register and record only
3439 those who are not marked as an empty. */
3441 if (I386_SAVE_FPU_REGS == iregnum)
3443 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
3445 if (record_arch_list_add_reg (ir->regcache, i))
3449 else if (I386_SAVE_FPU_ENV == iregnum)
3451 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3453 if (record_arch_list_add_reg (ir->regcache, i))
3457 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
3459 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3461 if (record_arch_list_add_reg (ir->regcache, i))
3465 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
3466 (iregnum <= I387_FOP_REGNUM (tdep)))
3468 if (record_arch_list_add_reg (ir->regcache,iregnum))
3473 /* Parameter error. */
3476 if(I386_SAVE_FPU_ENV != iregnum)
3478 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3480 if (record_arch_list_add_reg (ir->regcache, i))
3487 /* Parse the current instruction and record the values of the registers and
3488 memory that will be changed in current instruction to "record_arch_list".
3489 Return -1 if something wrong. */
3491 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3492 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3495 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
3496 CORE_ADDR input_addr)
3498 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3504 gdb_byte buf[MAX_REGISTER_SIZE];
3505 struct i386_record_s ir;
3506 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3511 memset (&ir, 0, sizeof (struct i386_record_s));
3512 ir.regcache = regcache;
3513 ir.addr = input_addr;
3514 ir.orig_addr = input_addr;
3518 ir.popl_esp_hack = 0;
3519 ir.regmap = tdep->record_regmap;
3520 ir.gdbarch = gdbarch;
3522 if (record_debug > 1)
3523 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
3525 paddress (gdbarch, ir.addr));
3530 if (target_read_memory (ir.addr, &opcode8, 1))
3533 printf_unfiltered (_("Process record: error reading memory at "
3534 "addr %s len = 1.\n"),
3535 paddress (gdbarch, ir.addr));
3539 switch (opcode8) /* Instruction prefixes */
3541 case REPE_PREFIX_OPCODE:
3542 prefixes |= PREFIX_REPZ;
3544 case REPNE_PREFIX_OPCODE:
3545 prefixes |= PREFIX_REPNZ;
3547 case LOCK_PREFIX_OPCODE:
3548 prefixes |= PREFIX_LOCK;
3550 case CS_PREFIX_OPCODE:
3551 ir.override = X86_RECORD_CS_REGNUM;
3553 case SS_PREFIX_OPCODE:
3554 ir.override = X86_RECORD_SS_REGNUM;
3556 case DS_PREFIX_OPCODE:
3557 ir.override = X86_RECORD_DS_REGNUM;
3559 case ES_PREFIX_OPCODE:
3560 ir.override = X86_RECORD_ES_REGNUM;
3562 case FS_PREFIX_OPCODE:
3563 ir.override = X86_RECORD_FS_REGNUM;
3565 case GS_PREFIX_OPCODE:
3566 ir.override = X86_RECORD_GS_REGNUM;
3568 case DATA_PREFIX_OPCODE:
3569 prefixes |= PREFIX_DATA;
3571 case ADDR_PREFIX_OPCODE:
3572 prefixes |= PREFIX_ADDR;
3574 case 0x40: /* i386 inc %eax */
3575 case 0x41: /* i386 inc %ecx */
3576 case 0x42: /* i386 inc %edx */
3577 case 0x43: /* i386 inc %ebx */
3578 case 0x44: /* i386 inc %esp */
3579 case 0x45: /* i386 inc %ebp */
3580 case 0x46: /* i386 inc %esi */
3581 case 0x47: /* i386 inc %edi */
3582 case 0x48: /* i386 dec %eax */
3583 case 0x49: /* i386 dec %ecx */
3584 case 0x4a: /* i386 dec %edx */
3585 case 0x4b: /* i386 dec %ebx */
3586 case 0x4c: /* i386 dec %esp */
3587 case 0x4d: /* i386 dec %ebp */
3588 case 0x4e: /* i386 dec %esi */
3589 case 0x4f: /* i386 dec %edi */
3590 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
3594 rex_w = (opcode8 >> 3) & 1;
3595 rex_r = (opcode8 & 0x4) << 1;
3596 ir.rex_x = (opcode8 & 0x2) << 2;
3597 ir.rex_b = (opcode8 & 0x1) << 3;
3599 else /* 32 bit target */
3608 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
3614 if (prefixes & PREFIX_DATA)
3617 if (prefixes & PREFIX_ADDR)
3619 else if (ir.regmap[X86_RECORD_R8_REGNUM])
3622 /* now check op code */
3623 opcode = (uint32_t) opcode8;
3628 if (target_read_memory (ir.addr, &opcode8, 1))
3631 printf_unfiltered (_("Process record: error reading memory at "
3632 "addr %s len = 1.\n"),
3633 paddress (gdbarch, ir.addr));
3637 opcode = (uint32_t) opcode8 | 0x0f00;
3641 case 0x00: /* arith & logic */
3689 if (((opcode >> 3) & 7) != OP_CMPL)
3691 if ((opcode & 1) == 0)
3694 ir.ot = ir.dflag + OT_WORD;
3696 switch ((opcode >> 1) & 3)
3698 case 0: /* OP Ev, Gv */
3699 if (i386_record_modrm (&ir))
3703 if (i386_record_lea_modrm (&ir))
3709 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3711 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
3714 case 1: /* OP Gv, Ev */
3715 if (i386_record_modrm (&ir))
3718 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3720 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
3722 case 2: /* OP A, Iv */
3723 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
3727 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3730 case 0x80: /* GRP1 */
3734 if (i386_record_modrm (&ir))
3737 if (ir.reg != OP_CMPL)
3739 if ((opcode & 1) == 0)
3742 ir.ot = ir.dflag + OT_WORD;
3749 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
3750 if (i386_record_lea_modrm (&ir))
3754 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
3756 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3759 case 0x40: /* inc */
3768 case 0x48: /* dec */
3777 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7);
3778 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3781 case 0xf6: /* GRP3 */
3783 if ((opcode & 1) == 0)
3786 ir.ot = ir.dflag + OT_WORD;
3787 if (i386_record_modrm (&ir))
3790 if (ir.mod != 3 && ir.reg == 0)
3791 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
3796 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3802 if (i386_record_lea_modrm (&ir))
3808 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3810 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
3812 if (ir.reg == 3) /* neg */
3813 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3819 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
3820 if (ir.ot != OT_BYTE)
3821 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
3822 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3826 opcode = opcode << 8 | ir.modrm;
3832 case 0xfe: /* GRP4 */
3833 case 0xff: /* GRP5 */
3834 if (i386_record_modrm (&ir))
3836 if (ir.reg >= 2 && opcode == 0xfe)
3839 opcode = opcode << 8 | ir.modrm;
3846 if ((opcode & 1) == 0)
3849 ir.ot = ir.dflag + OT_WORD;
3852 if (i386_record_lea_modrm (&ir))
3858 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3860 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
3862 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3865 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
3867 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
3869 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3872 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
3873 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
3875 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3879 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3882 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
3884 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
3889 opcode = opcode << 8 | ir.modrm;
3895 case 0x84: /* test */
3899 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3902 case 0x98: /* CWDE/CBW */
3903 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
3906 case 0x99: /* CDQ/CWD */
3907 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
3908 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
3911 case 0x0faf: /* imul */
3914 ir.ot = ir.dflag + OT_WORD;
3915 if (i386_record_modrm (&ir))
3918 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
3919 else if (opcode == 0x6b)
3922 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3924 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
3925 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3928 case 0x0fc0: /* xadd */
3930 if ((opcode & 1) == 0)
3933 ir.ot = ir.dflag + OT_WORD;
3934 if (i386_record_modrm (&ir))
3939 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3941 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
3942 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3944 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
3948 if (i386_record_lea_modrm (&ir))
3950 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3952 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
3954 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3957 case 0x0fb0: /* cmpxchg */
3959 if ((opcode & 1) == 0)
3962 ir.ot = ir.dflag + OT_WORD;
3963 if (i386_record_modrm (&ir))
3968 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
3969 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3971 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
3975 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
3976 if (i386_record_lea_modrm (&ir))
3979 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3982 case 0x0fc7: /* cmpxchg8b */
3983 if (i386_record_modrm (&ir))
3988 opcode = opcode << 8 | ir.modrm;
3991 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
3992 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
3993 if (i386_record_lea_modrm (&ir))
3995 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3998 case 0x50: /* push */
4008 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4010 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4014 case 0x06: /* push es */
4015 case 0x0e: /* push cs */
4016 case 0x16: /* push ss */
4017 case 0x1e: /* push ds */
4018 if (ir.regmap[X86_RECORD_R8_REGNUM])
4023 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4027 case 0x0fa0: /* push fs */
4028 case 0x0fa8: /* push gs */
4029 if (ir.regmap[X86_RECORD_R8_REGNUM])
4034 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4038 case 0x60: /* pusha */
4039 if (ir.regmap[X86_RECORD_R8_REGNUM])
4044 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
4048 case 0x58: /* pop */
4056 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4057 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
4060 case 0x61: /* popa */
4061 if (ir.regmap[X86_RECORD_R8_REGNUM])
4066 for (regnum = X86_RECORD_REAX_REGNUM;
4067 regnum <= X86_RECORD_REDI_REGNUM;
4069 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
4072 case 0x8f: /* pop */
4073 if (ir.regmap[X86_RECORD_R8_REGNUM])
4074 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
4076 ir.ot = ir.dflag + OT_WORD;
4077 if (i386_record_modrm (&ir))
4080 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
4083 ir.popl_esp_hack = 1 << ir.ot;
4084 if (i386_record_lea_modrm (&ir))
4087 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4090 case 0xc8: /* enter */
4091 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
4092 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4094 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4098 case 0xc9: /* leave */
4099 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4100 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
4103 case 0x07: /* pop es */
4104 if (ir.regmap[X86_RECORD_R8_REGNUM])
4109 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4110 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
4111 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4114 case 0x17: /* pop ss */
4115 if (ir.regmap[X86_RECORD_R8_REGNUM])
4120 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4121 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
4122 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4125 case 0x1f: /* pop ds */
4126 if (ir.regmap[X86_RECORD_R8_REGNUM])
4131 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4132 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
4133 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4136 case 0x0fa1: /* pop fs */
4137 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4138 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
4139 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4142 case 0x0fa9: /* pop gs */
4143 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4144 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
4145 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4148 case 0x88: /* mov */
4152 if ((opcode & 1) == 0)
4155 ir.ot = ir.dflag + OT_WORD;
4157 if (i386_record_modrm (&ir))
4162 if (opcode == 0xc6 || opcode == 0xc7)
4163 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4164 if (i386_record_lea_modrm (&ir))
4169 if (opcode == 0xc6 || opcode == 0xc7)
4171 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4173 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4177 case 0x8a: /* mov */
4179 if ((opcode & 1) == 0)
4182 ir.ot = ir.dflag + OT_WORD;
4183 if (i386_record_modrm (&ir))
4186 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4188 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4191 case 0x8c: /* mov seg */
4192 if (i386_record_modrm (&ir))
4197 opcode = opcode << 8 | ir.modrm;
4202 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4206 if (i386_record_lea_modrm (&ir))
4211 case 0x8e: /* mov seg */
4212 if (i386_record_modrm (&ir))
4217 regnum = X86_RECORD_ES_REGNUM;
4220 regnum = X86_RECORD_SS_REGNUM;
4223 regnum = X86_RECORD_DS_REGNUM;
4226 regnum = X86_RECORD_FS_REGNUM;
4229 regnum = X86_RECORD_GS_REGNUM;
4233 opcode = opcode << 8 | ir.modrm;
4237 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
4238 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4241 case 0x0fb6: /* movzbS */
4242 case 0x0fb7: /* movzwS */
4243 case 0x0fbe: /* movsbS */
4244 case 0x0fbf: /* movswS */
4245 if (i386_record_modrm (&ir))
4247 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
4250 case 0x8d: /* lea */
4251 if (i386_record_modrm (&ir))
4256 opcode = opcode << 8 | ir.modrm;
4261 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4263 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4266 case 0xa0: /* mov EAX */
4269 case 0xd7: /* xlat */
4270 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4273 case 0xa2: /* mov EAX */
4275 if (ir.override >= 0)
4277 warning (_("Process record ignores the memory change "
4278 "of instruction at address %s because "
4279 "it can't get the value of the segment "
4281 paddress (gdbarch, ir.orig_addr));
4285 if ((opcode & 1) == 0)
4288 ir.ot = ir.dflag + OT_WORD;
4291 if (target_read_memory (ir.addr, buf, 8))
4294 printf_unfiltered (_("Process record: error reading "
4295 "memory at addr 0x%s len = 8.\n"),
4296 paddress (gdbarch, ir.addr));
4300 addr = extract_unsigned_integer (buf, 8, byte_order);
4304 if (target_read_memory (ir.addr, buf, 4))
4307 printf_unfiltered (_("Process record: error reading "
4308 "memory at addr 0x%s len = 4.\n"),
4309 paddress (gdbarch, ir.addr));
4313 addr = extract_unsigned_integer (buf, 4, byte_order);
4317 if (target_read_memory (ir.addr, buf, 2))
4320 printf_unfiltered (_("Process record: error reading "
4321 "memory at addr 0x%s len = 2.\n"),
4322 paddress (gdbarch, ir.addr));
4326 addr = extract_unsigned_integer (buf, 2, byte_order);
4328 if (record_arch_list_add_mem (addr, 1 << ir.ot))
4333 case 0xb0: /* mov R, Ib */
4341 I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
4342 ? ((opcode & 0x7) | ir.rex_b)
4343 : ((opcode & 0x7) & 0x3));
4346 case 0xb8: /* mov R, Iv */
4354 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
4357 case 0x91: /* xchg R, EAX */
4364 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4365 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7);
4368 case 0x86: /* xchg Ev, Gv */
4370 if ((opcode & 1) == 0)
4373 ir.ot = ir.dflag + OT_WORD;
4374 if (i386_record_modrm (&ir))
4379 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4381 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4385 if (i386_record_lea_modrm (&ir))
4389 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4391 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4394 case 0xc4: /* les Gv */
4395 case 0xc5: /* lds Gv */
4396 if (ir.regmap[X86_RECORD_R8_REGNUM])
4401 case 0x0fb2: /* lss Gv */
4402 case 0x0fb4: /* lfs Gv */
4403 case 0x0fb5: /* lgs Gv */
4404 if (i386_record_modrm (&ir))
4412 opcode = opcode << 8 | ir.modrm;
4417 case 0xc4: /* les Gv */
4418 regnum = X86_RECORD_ES_REGNUM;
4420 case 0xc5: /* lds Gv */
4421 regnum = X86_RECORD_DS_REGNUM;
4423 case 0x0fb2: /* lss Gv */
4424 regnum = X86_RECORD_SS_REGNUM;
4426 case 0x0fb4: /* lfs Gv */
4427 regnum = X86_RECORD_FS_REGNUM;
4429 case 0x0fb5: /* lgs Gv */
4430 regnum = X86_RECORD_GS_REGNUM;
4433 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
4434 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
4435 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4438 case 0xc0: /* shifts */
4444 if ((opcode & 1) == 0)
4447 ir.ot = ir.dflag + OT_WORD;
4448 if (i386_record_modrm (&ir))
4450 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
4452 if (i386_record_lea_modrm (&ir))
4458 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4460 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4462 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4469 if (i386_record_modrm (&ir))
4473 if (record_arch_list_add_reg (ir.regcache, ir.rm))
4478 if (i386_record_lea_modrm (&ir))
4483 case 0xd8: /* Floats. */
4491 if (i386_record_modrm (&ir))
4493 ir.reg |= ((opcode & 7) << 3);
4499 if (i386_record_lea_modrm_addr (&ir, &addr64))
4507 /* For fcom, ficom nothing to do. */
4513 /* For fcomp, ficomp pop FPU stack, store all. */
4514 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4541 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
4542 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
4543 of code, always affects st(0) register. */
4544 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
4568 /* Handling fld, fild. */
4569 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4573 switch (ir.reg >> 4)
4576 if (record_arch_list_add_mem (addr64, 4))
4580 if (record_arch_list_add_mem (addr64, 8))
4586 if (record_arch_list_add_mem (addr64, 2))
4592 switch (ir.reg >> 4)
4595 if (record_arch_list_add_mem (addr64, 4))
4597 if (3 == (ir.reg & 7))
4599 /* For fstp m32fp. */
4600 if (i386_record_floats (gdbarch, &ir,
4601 I386_SAVE_FPU_REGS))
4606 if (record_arch_list_add_mem (addr64, 4))
4608 if ((3 == (ir.reg & 7))
4609 || (5 == (ir.reg & 7))
4610 || (7 == (ir.reg & 7)))
4612 /* For fstp insn. */
4613 if (i386_record_floats (gdbarch, &ir,
4614 I386_SAVE_FPU_REGS))
4619 if (record_arch_list_add_mem (addr64, 8))
4621 if (3 == (ir.reg & 7))
4623 /* For fstp m64fp. */
4624 if (i386_record_floats (gdbarch, &ir,
4625 I386_SAVE_FPU_REGS))
4630 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
4632 /* For fistp, fbld, fild, fbstp. */
4633 if (i386_record_floats (gdbarch, &ir,
4634 I386_SAVE_FPU_REGS))
4639 if (record_arch_list_add_mem (addr64, 2))
4648 if (i386_record_floats (gdbarch, &ir,
4649 I386_SAVE_FPU_ENV_REG_STACK))
4654 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
4659 if (i386_record_floats (gdbarch, &ir,
4660 I386_SAVE_FPU_ENV_REG_STACK))
4666 if (record_arch_list_add_mem (addr64, 28))
4671 if (record_arch_list_add_mem (addr64, 14))
4677 if (record_arch_list_add_mem (addr64, 2))
4679 /* Insn fstp, fbstp. */
4680 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4685 if (record_arch_list_add_mem (addr64, 10))
4691 if (record_arch_list_add_mem (addr64, 28))
4697 if (record_arch_list_add_mem (addr64, 14))
4701 if (record_arch_list_add_mem (addr64, 80))
4704 if (i386_record_floats (gdbarch, &ir,
4705 I386_SAVE_FPU_ENV_REG_STACK))
4709 if (record_arch_list_add_mem (addr64, 8))
4712 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4717 opcode = opcode << 8 | ir.modrm;
4722 /* Opcode is an extension of modR/M byte. */
4728 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
4732 if (0x0c == (ir.modrm >> 4))
4734 if ((ir.modrm & 0x0f) <= 7)
4736 if (i386_record_floats (gdbarch, &ir,
4737 I386_SAVE_FPU_REGS))
4742 if (i386_record_floats (gdbarch, &ir,
4743 I387_ST0_REGNUM (tdep)))
4745 /* If only st(0) is changing, then we have already
4747 if ((ir.modrm & 0x0f) - 0x08)
4749 if (i386_record_floats (gdbarch, &ir,
4750 I387_ST0_REGNUM (tdep) +
4751 ((ir.modrm & 0x0f) - 0x08)))
4769 if (i386_record_floats (gdbarch, &ir,
4770 I387_ST0_REGNUM (tdep)))
4788 if (i386_record_floats (gdbarch, &ir,
4789 I386_SAVE_FPU_REGS))
4793 if (i386_record_floats (gdbarch, &ir,
4794 I387_ST0_REGNUM (tdep)))
4796 if (i386_record_floats (gdbarch, &ir,
4797 I387_ST0_REGNUM (tdep) + 1))
4804 if (0xe9 == ir.modrm)
4806 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4809 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
4811 if (i386_record_floats (gdbarch, &ir,
4812 I387_ST0_REGNUM (tdep)))
4814 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
4816 if (i386_record_floats (gdbarch, &ir,
4817 I387_ST0_REGNUM (tdep) +
4821 else if ((ir.modrm & 0x0f) - 0x08)
4823 if (i386_record_floats (gdbarch, &ir,
4824 I387_ST0_REGNUM (tdep) +
4825 ((ir.modrm & 0x0f) - 0x08)))
4831 if (0xe3 == ir.modrm)
4833 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
4836 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
4838 if (i386_record_floats (gdbarch, &ir,
4839 I387_ST0_REGNUM (tdep)))
4841 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
4843 if (i386_record_floats (gdbarch, &ir,
4844 I387_ST0_REGNUM (tdep) +
4848 else if ((ir.modrm & 0x0f) - 0x08)
4850 if (i386_record_floats (gdbarch, &ir,
4851 I387_ST0_REGNUM (tdep) +
4852 ((ir.modrm & 0x0f) - 0x08)))
4858 if ((0x0c == ir.modrm >> 4)
4859 || (0x0d == ir.modrm >> 4)
4860 || (0x0f == ir.modrm >> 4))
4862 if ((ir.modrm & 0x0f) <= 7)
4864 if (i386_record_floats (gdbarch, &ir,
4865 I387_ST0_REGNUM (tdep) +
4871 if (i386_record_floats (gdbarch, &ir,
4872 I387_ST0_REGNUM (tdep) +
4873 ((ir.modrm & 0x0f) - 0x08)))
4879 if (0x0c == ir.modrm >> 4)
4881 if (i386_record_floats (gdbarch, &ir,
4882 I387_FTAG_REGNUM (tdep)))
4885 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
4887 if ((ir.modrm & 0x0f) <= 7)
4889 if (i386_record_floats (gdbarch, &ir,
4890 I387_ST0_REGNUM (tdep) +
4896 if (i386_record_floats (gdbarch, &ir,
4897 I386_SAVE_FPU_REGS))
4903 if ((0x0c == ir.modrm >> 4)
4904 || (0x0e == ir.modrm >> 4)
4905 || (0x0f == ir.modrm >> 4)
4906 || (0xd9 == ir.modrm))
4908 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4913 if (0xe0 == ir.modrm)
4915 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
4918 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
4920 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4928 case 0xa4: /* movsS */
4930 case 0xaa: /* stosS */
4932 case 0x6c: /* insS */
4934 regcache_raw_read_unsigned (ir.regcache,
4935 ir.regmap[X86_RECORD_RECX_REGNUM],
4941 if ((opcode & 1) == 0)
4944 ir.ot = ir.dflag + OT_WORD;
4945 regcache_raw_read_unsigned (ir.regcache,
4946 ir.regmap[X86_RECORD_REDI_REGNUM],
4949 regcache_raw_read_unsigned (ir.regcache,
4950 ir.regmap[X86_RECORD_ES_REGNUM],
4952 regcache_raw_read_unsigned (ir.regcache,
4953 ir.regmap[X86_RECORD_DS_REGNUM],
4955 if (ir.aflag && (es != ds))
4957 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
4958 warning (_("Process record ignores the memory "
4959 "change of instruction at address %s "
4960 "because it can't get the value of the "
4961 "ES segment register."),
4962 paddress (gdbarch, ir.orig_addr));
4966 if (record_arch_list_add_mem (addr, 1 << ir.ot))
4970 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
4971 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
4972 if (opcode == 0xa4 || opcode == 0xa5)
4973 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
4974 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
4975 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4979 case 0xa6: /* cmpsS */
4981 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
4982 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
4983 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
4984 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
4985 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4988 case 0xac: /* lodsS */
4990 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4991 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
4992 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
4993 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
4994 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4997 case 0xae: /* scasS */
4999 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5000 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5001 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5002 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5005 case 0x6e: /* outsS */
5007 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5008 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5009 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5010 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5013 case 0xe4: /* port I/O */
5017 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5018 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5028 case 0xc2: /* ret im */
5029 case 0xc3: /* ret */
5030 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5031 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5034 case 0xca: /* lret im */
5035 case 0xcb: /* lret */
5036 case 0xcf: /* iret */
5037 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5038 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5039 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5042 case 0xe8: /* call im */
5043 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5045 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5049 case 0x9a: /* lcall im */
5050 if (ir.regmap[X86_RECORD_R8_REGNUM])
5055 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5056 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5060 case 0xe9: /* jmp im */
5061 case 0xea: /* ljmp im */
5062 case 0xeb: /* jmp Jb */
5063 case 0x70: /* jcc Jb */
5079 case 0x0f80: /* jcc Jv */
5097 case 0x0f90: /* setcc Gv */
5113 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5115 if (i386_record_modrm (&ir))
5118 I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
5122 if (i386_record_lea_modrm (&ir))
5127 case 0x0f40: /* cmov Gv, Ev */
5143 if (i386_record_modrm (&ir))
5146 if (ir.dflag == OT_BYTE)
5148 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
5152 case 0x9c: /* pushf */
5153 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5154 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5156 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5160 case 0x9d: /* popf */
5161 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5162 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5165 case 0x9e: /* sahf */
5166 if (ir.regmap[X86_RECORD_R8_REGNUM])
5171 case 0xf5: /* cmc */
5172 case 0xf8: /* clc */
5173 case 0xf9: /* stc */
5174 case 0xfc: /* cld */
5175 case 0xfd: /* std */
5176 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5179 case 0x9f: /* lahf */
5180 if (ir.regmap[X86_RECORD_R8_REGNUM])
5185 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5186 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5189 /* bit operations */
5190 case 0x0fba: /* bt/bts/btr/btc Gv, im */
5191 ir.ot = ir.dflag + OT_WORD;
5192 if (i386_record_modrm (&ir))
5197 opcode = opcode << 8 | ir.modrm;
5203 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5206 if (i386_record_lea_modrm (&ir))
5210 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5213 case 0x0fa3: /* bt Gv, Ev */
5214 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5217 case 0x0fab: /* bts */
5218 case 0x0fb3: /* btr */
5219 case 0x0fbb: /* btc */
5220 ir.ot = ir.dflag + OT_WORD;
5221 if (i386_record_modrm (&ir))
5224 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5228 if (i386_record_lea_modrm_addr (&ir, &addr64))
5230 regcache_raw_read_unsigned (ir.regcache,
5231 ir.regmap[ir.reg | rex_r],
5236 addr64 += ((int16_t) addr >> 4) << 4;
5239 addr64 += ((int32_t) addr >> 5) << 5;
5242 addr64 += ((int64_t) addr >> 6) << 6;
5245 if (record_arch_list_add_mem (addr64, 1 << ir.ot))
5247 if (i386_record_lea_modrm (&ir))
5250 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5253 case 0x0fbc: /* bsf */
5254 case 0x0fbd: /* bsr */
5255 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5256 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5260 case 0x27: /* daa */
5261 case 0x2f: /* das */
5262 case 0x37: /* aaa */
5263 case 0x3f: /* aas */
5264 case 0xd4: /* aam */
5265 case 0xd5: /* aad */
5266 if (ir.regmap[X86_RECORD_R8_REGNUM])
5271 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5272 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5276 case 0x90: /* nop */
5277 if (prefixes & PREFIX_LOCK)
5284 case 0x9b: /* fwait */
5285 if (target_read_memory (ir.addr, &opcode8, 1))
5288 printf_unfiltered (_("Process record: error reading memory at "
5289 "addr 0x%s len = 1.\n"),
5290 paddress (gdbarch, ir.addr));
5293 opcode = (uint32_t) opcode8;
5299 case 0xcc: /* int3 */
5300 printf_unfiltered (_("Process record does not support instruction "
5307 case 0xcd: /* int */
5311 if (target_read_memory (ir.addr, &interrupt, 1))
5314 printf_unfiltered (_("Process record: error reading memory "
5315 "at addr %s len = 1.\n"),
5316 paddress (gdbarch, ir.addr));
5320 if (interrupt != 0x80
5321 || tdep->i386_intx80_record == NULL)
5323 printf_unfiltered (_("Process record does not support "
5324 "instruction int 0x%02x.\n"),
5329 ret = tdep->i386_intx80_record (ir.regcache);
5336 case 0xce: /* into */
5337 printf_unfiltered (_("Process record does not support "
5338 "instruction into.\n"));
5343 case 0xfa: /* cli */
5344 case 0xfb: /* sti */
5347 case 0x62: /* bound */
5348 printf_unfiltered (_("Process record does not support "
5349 "instruction bound.\n"));
5354 case 0x0fc8: /* bswap reg */
5362 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
5365 case 0xd6: /* salc */
5366 if (ir.regmap[X86_RECORD_R8_REGNUM])
5371 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5372 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5375 case 0xe0: /* loopnz */
5376 case 0xe1: /* loopz */
5377 case 0xe2: /* loop */
5378 case 0xe3: /* jecxz */
5379 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5380 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5383 case 0x0f30: /* wrmsr */
5384 printf_unfiltered (_("Process record does not support "
5385 "instruction wrmsr.\n"));
5390 case 0x0f32: /* rdmsr */
5391 printf_unfiltered (_("Process record does not support "
5392 "instruction rdmsr.\n"));
5397 case 0x0f31: /* rdtsc */
5398 printf_unfiltered (_("Process record does not support "
5399 "instruction rdtsc.\n"));
5404 case 0x0f34: /* sysenter */
5407 if (ir.regmap[X86_RECORD_R8_REGNUM])
5412 if (tdep->i386_sysenter_record == NULL)
5414 printf_unfiltered (_("Process record does not support "
5415 "instruction sysenter.\n"));
5419 ret = tdep->i386_sysenter_record (ir.regcache);
5425 case 0x0f35: /* sysexit */
5426 printf_unfiltered (_("Process record does not support "
5427 "instruction sysexit.\n"));
5432 case 0x0f05: /* syscall */
5435 if (tdep->i386_syscall_record == NULL)
5437 printf_unfiltered (_("Process record does not support "
5438 "instruction syscall.\n"));
5442 ret = tdep->i386_syscall_record (ir.regcache);
5448 case 0x0f07: /* sysret */
5449 printf_unfiltered (_("Process record does not support "
5450 "instruction sysret.\n"));
5455 case 0x0fa2: /* cpuid */
5456 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5457 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5458 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5459 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
5462 case 0xf4: /* hlt */
5463 printf_unfiltered (_("Process record does not support "
5464 "instruction hlt.\n"));
5470 if (i386_record_modrm (&ir))
5477 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5481 if (i386_record_lea_modrm (&ir))
5490 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5494 opcode = opcode << 8 | ir.modrm;
5501 if (i386_record_modrm (&ir))
5512 opcode = opcode << 8 | ir.modrm;
5515 if (ir.override >= 0)
5517 warning (_("Process record ignores the memory "
5518 "change of instruction at "
5519 "address %s because it can't get "
5520 "the value of the segment "
5522 paddress (gdbarch, ir.orig_addr));
5526 if (i386_record_lea_modrm_addr (&ir, &addr64))
5528 if (record_arch_list_add_mem (addr64, 2))
5531 if (ir.regmap[X86_RECORD_R8_REGNUM])
5533 if (record_arch_list_add_mem (addr64, 8))
5538 if (record_arch_list_add_mem (addr64, 4))
5549 case 0: /* monitor */
5552 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5556 opcode = opcode << 8 | ir.modrm;
5564 if (ir.override >= 0)
5566 warning (_("Process record ignores the memory "
5567 "change of instruction at "
5568 "address %s because it can't get "
5569 "the value of the segment "
5571 paddress (gdbarch, ir.orig_addr));
5577 if (i386_record_lea_modrm_addr (&ir, &addr64))
5579 if (record_arch_list_add_mem (addr64, 2))
5582 if (ir.regmap[X86_RECORD_R8_REGNUM])
5584 if (record_arch_list_add_mem (addr64, 8))
5589 if (record_arch_list_add_mem (addr64, 4))
5601 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5602 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5606 else if (ir.rm == 1)
5613 opcode = opcode << 8 | ir.modrm;
5620 if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
5626 if (i386_record_lea_modrm (&ir))
5629 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5632 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5634 case 7: /* invlpg */
5637 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
5638 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
5642 opcode = opcode << 8 | ir.modrm;
5647 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5651 opcode = opcode << 8 | ir.modrm;
5657 case 0x0f08: /* invd */
5658 case 0x0f09: /* wbinvd */
5661 case 0x63: /* arpl */
5662 if (i386_record_modrm (&ir))
5664 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
5666 I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
5667 ? (ir.reg | rex_r) : ir.rm);
5671 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
5672 if (i386_record_lea_modrm (&ir))
5675 if (!ir.regmap[X86_RECORD_R8_REGNUM])
5676 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5679 case 0x0f02: /* lar */
5680 case 0x0f03: /* lsl */
5681 if (i386_record_modrm (&ir))
5683 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5684 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5688 if (i386_record_modrm (&ir))
5690 if (ir.mod == 3 && ir.reg == 3)
5693 opcode = opcode << 8 | ir.modrm;
5705 /* nop (multi byte) */
5708 case 0x0f20: /* mov reg, crN */
5709 case 0x0f22: /* mov crN, reg */
5710 if (i386_record_modrm (&ir))
5712 if ((ir.modrm & 0xc0) != 0xc0)
5715 opcode = opcode << 8 | ir.modrm;
5726 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5728 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5732 opcode = opcode << 8 | ir.modrm;
5738 case 0x0f21: /* mov reg, drN */
5739 case 0x0f23: /* mov drN, reg */
5740 if (i386_record_modrm (&ir))
5742 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
5743 || ir.reg == 5 || ir.reg >= 8)
5746 opcode = opcode << 8 | ir.modrm;
5750 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5752 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5755 case 0x0f06: /* clts */
5756 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5759 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
5761 case 0x0f0d: /* 3DNow! prefetch */
5764 case 0x0f0e: /* 3DNow! femms */
5765 case 0x0f77: /* emms */
5766 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
5768 record_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
5771 case 0x0f0f: /* 3DNow! data */
5772 if (i386_record_modrm (&ir))
5774 if (target_read_memory (ir.addr, &opcode8, 1))
5776 printf_unfiltered (_("Process record: error reading memory at "
5777 "addr %s len = 1.\n"),
5778 paddress (gdbarch, ir.addr));
5784 case 0x0c: /* 3DNow! pi2fw */
5785 case 0x0d: /* 3DNow! pi2fd */
5786 case 0x1c: /* 3DNow! pf2iw */
5787 case 0x1d: /* 3DNow! pf2id */
5788 case 0x8a: /* 3DNow! pfnacc */
5789 case 0x8e: /* 3DNow! pfpnacc */
5790 case 0x90: /* 3DNow! pfcmpge */
5791 case 0x94: /* 3DNow! pfmin */
5792 case 0x96: /* 3DNow! pfrcp */
5793 case 0x97: /* 3DNow! pfrsqrt */
5794 case 0x9a: /* 3DNow! pfsub */
5795 case 0x9e: /* 3DNow! pfadd */
5796 case 0xa0: /* 3DNow! pfcmpgt */
5797 case 0xa4: /* 3DNow! pfmax */
5798 case 0xa6: /* 3DNow! pfrcpit1 */
5799 case 0xa7: /* 3DNow! pfrsqit1 */
5800 case 0xaa: /* 3DNow! pfsubr */
5801 case 0xae: /* 3DNow! pfacc */
5802 case 0xb0: /* 3DNow! pfcmpeq */
5803 case 0xb4: /* 3DNow! pfmul */
5804 case 0xb6: /* 3DNow! pfrcpit2 */
5805 case 0xb7: /* 3DNow! pmulhrw */
5806 case 0xbb: /* 3DNow! pswapd */
5807 case 0xbf: /* 3DNow! pavgusb */
5808 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
5809 goto no_support_3dnow_data;
5810 record_arch_list_add_reg (ir.regcache, ir.reg);
5814 no_support_3dnow_data:
5815 opcode = (opcode << 8) | opcode8;
5821 case 0x0faa: /* rsm */
5822 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5823 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5824 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5825 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5826 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
5827 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5828 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5829 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5830 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5834 if (i386_record_modrm (&ir))
5838 case 0: /* fxsave */
5842 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5843 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
5845 if (record_arch_list_add_mem (tmpu64, 512))
5850 case 1: /* fxrstor */
5854 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5856 for (i = I387_MM0_REGNUM (tdep);
5857 i386_mmx_regnum_p (gdbarch, i); i++)
5858 record_arch_list_add_reg (ir.regcache, i);
5860 for (i = I387_XMM0_REGNUM (tdep);
5861 i386_xmm_regnum_p (gdbarch, i); i++)
5862 record_arch_list_add_reg (ir.regcache, i);
5864 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
5865 record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
5867 for (i = I387_ST0_REGNUM (tdep);
5868 i386_fp_regnum_p (gdbarch, i); i++)
5869 record_arch_list_add_reg (ir.regcache, i);
5871 for (i = I387_FCTRL_REGNUM (tdep);
5872 i386_fpc_regnum_p (gdbarch, i); i++)
5873 record_arch_list_add_reg (ir.regcache, i);
5877 case 2: /* ldmxcsr */
5878 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
5880 record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
5883 case 3: /* stmxcsr */
5885 if (i386_record_lea_modrm (&ir))
5889 case 5: /* lfence */
5890 case 6: /* mfence */
5891 case 7: /* sfence clflush */
5895 opcode = (opcode << 8) | ir.modrm;
5901 case 0x0fc3: /* movnti */
5902 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
5903 if (i386_record_modrm (&ir))
5908 if (i386_record_lea_modrm (&ir))
5912 /* Add prefix to opcode. */
6039 reswitch_prefix_add:
6047 if (target_read_memory (ir.addr, &opcode8, 1))
6049 printf_unfiltered (_("Process record: error reading memory at "
6050 "addr %s len = 1.\n"),
6051 paddress (gdbarch, ir.addr));
6055 opcode = (uint32_t) opcode8 | opcode << 8;
6056 goto reswitch_prefix_add;
6059 case 0x0f10: /* movups */
6060 case 0x660f10: /* movupd */
6061 case 0xf30f10: /* movss */
6062 case 0xf20f10: /* movsd */
6063 case 0x0f12: /* movlps */
6064 case 0x660f12: /* movlpd */
6065 case 0xf30f12: /* movsldup */
6066 case 0xf20f12: /* movddup */
6067 case 0x0f14: /* unpcklps */
6068 case 0x660f14: /* unpcklpd */
6069 case 0x0f15: /* unpckhps */
6070 case 0x660f15: /* unpckhpd */
6071 case 0x0f16: /* movhps */
6072 case 0x660f16: /* movhpd */
6073 case 0xf30f16: /* movshdup */
6074 case 0x0f28: /* movaps */
6075 case 0x660f28: /* movapd */
6076 case 0x0f2a: /* cvtpi2ps */
6077 case 0x660f2a: /* cvtpi2pd */
6078 case 0xf30f2a: /* cvtsi2ss */
6079 case 0xf20f2a: /* cvtsi2sd */
6080 case 0x0f2c: /* cvttps2pi */
6081 case 0x660f2c: /* cvttpd2pi */
6082 case 0x0f2d: /* cvtps2pi */
6083 case 0x660f2d: /* cvtpd2pi */
6084 case 0x660f3800: /* pshufb */
6085 case 0x660f3801: /* phaddw */
6086 case 0x660f3802: /* phaddd */
6087 case 0x660f3803: /* phaddsw */
6088 case 0x660f3804: /* pmaddubsw */
6089 case 0x660f3805: /* phsubw */
6090 case 0x660f3806: /* phsubd */
6091 case 0x660f3807: /* phaddsw */
6092 case 0x660f3808: /* psignb */
6093 case 0x660f3809: /* psignw */
6094 case 0x660f380a: /* psignd */
6095 case 0x660f380b: /* pmulhrsw */
6096 case 0x660f3810: /* pblendvb */
6097 case 0x660f3814: /* blendvps */
6098 case 0x660f3815: /* blendvpd */
6099 case 0x660f381c: /* pabsb */
6100 case 0x660f381d: /* pabsw */
6101 case 0x660f381e: /* pabsd */
6102 case 0x660f3820: /* pmovsxbw */
6103 case 0x660f3821: /* pmovsxbd */
6104 case 0x660f3822: /* pmovsxbq */
6105 case 0x660f3823: /* pmovsxwd */
6106 case 0x660f3824: /* pmovsxwq */
6107 case 0x660f3825: /* pmovsxdq */
6108 case 0x660f3828: /* pmuldq */
6109 case 0x660f3829: /* pcmpeqq */
6110 case 0x660f382a: /* movntdqa */
6111 case 0x660f3a08: /* roundps */
6112 case 0x660f3a09: /* roundpd */
6113 case 0x660f3a0a: /* roundss */
6114 case 0x660f3a0b: /* roundsd */
6115 case 0x660f3a0c: /* blendps */
6116 case 0x660f3a0d: /* blendpd */
6117 case 0x660f3a0e: /* pblendw */
6118 case 0x660f3a0f: /* palignr */
6119 case 0x660f3a20: /* pinsrb */
6120 case 0x660f3a21: /* insertps */
6121 case 0x660f3a22: /* pinsrd pinsrq */
6122 case 0x660f3a40: /* dpps */
6123 case 0x660f3a41: /* dppd */
6124 case 0x660f3a42: /* mpsadbw */
6125 case 0x660f3a60: /* pcmpestrm */
6126 case 0x660f3a61: /* pcmpestri */
6127 case 0x660f3a62: /* pcmpistrm */
6128 case 0x660f3a63: /* pcmpistri */
6129 case 0x0f51: /* sqrtps */
6130 case 0x660f51: /* sqrtpd */
6131 case 0xf20f51: /* sqrtsd */
6132 case 0xf30f51: /* sqrtss */
6133 case 0x0f52: /* rsqrtps */
6134 case 0xf30f52: /* rsqrtss */
6135 case 0x0f53: /* rcpps */
6136 case 0xf30f53: /* rcpss */
6137 case 0x0f54: /* andps */
6138 case 0x660f54: /* andpd */
6139 case 0x0f55: /* andnps */
6140 case 0x660f55: /* andnpd */
6141 case 0x0f56: /* orps */
6142 case 0x660f56: /* orpd */
6143 case 0x0f57: /* xorps */
6144 case 0x660f57: /* xorpd */
6145 case 0x0f58: /* addps */
6146 case 0x660f58: /* addpd */
6147 case 0xf20f58: /* addsd */
6148 case 0xf30f58: /* addss */
6149 case 0x0f59: /* mulps */
6150 case 0x660f59: /* mulpd */
6151 case 0xf20f59: /* mulsd */
6152 case 0xf30f59: /* mulss */
6153 case 0x0f5a: /* cvtps2pd */
6154 case 0x660f5a: /* cvtpd2ps */
6155 case 0xf20f5a: /* cvtsd2ss */
6156 case 0xf30f5a: /* cvtss2sd */
6157 case 0x0f5b: /* cvtdq2ps */
6158 case 0x660f5b: /* cvtps2dq */
6159 case 0xf30f5b: /* cvttps2dq */
6160 case 0x0f5c: /* subps */
6161 case 0x660f5c: /* subpd */
6162 case 0xf20f5c: /* subsd */
6163 case 0xf30f5c: /* subss */
6164 case 0x0f5d: /* minps */
6165 case 0x660f5d: /* minpd */
6166 case 0xf20f5d: /* minsd */
6167 case 0xf30f5d: /* minss */
6168 case 0x0f5e: /* divps */
6169 case 0x660f5e: /* divpd */
6170 case 0xf20f5e: /* divsd */
6171 case 0xf30f5e: /* divss */
6172 case 0x0f5f: /* maxps */
6173 case 0x660f5f: /* maxpd */
6174 case 0xf20f5f: /* maxsd */
6175 case 0xf30f5f: /* maxss */
6176 case 0x660f60: /* punpcklbw */
6177 case 0x660f61: /* punpcklwd */
6178 case 0x660f62: /* punpckldq */
6179 case 0x660f63: /* packsswb */
6180 case 0x660f64: /* pcmpgtb */
6181 case 0x660f65: /* pcmpgtw */
6182 case 0x660f66: /* pcmpgtl */
6183 case 0x660f67: /* packuswb */
6184 case 0x660f68: /* punpckhbw */
6185 case 0x660f69: /* punpckhwd */
6186 case 0x660f6a: /* punpckhdq */
6187 case 0x660f6b: /* packssdw */
6188 case 0x660f6c: /* punpcklqdq */
6189 case 0x660f6d: /* punpckhqdq */
6190 case 0x660f6e: /* movd */
6191 case 0x660f6f: /* movdqa */
6192 case 0xf30f6f: /* movdqu */
6193 case 0x660f70: /* pshufd */
6194 case 0xf20f70: /* pshuflw */
6195 case 0xf30f70: /* pshufhw */
6196 case 0x660f74: /* pcmpeqb */
6197 case 0x660f75: /* pcmpeqw */
6198 case 0x660f76: /* pcmpeql */
6199 case 0x660f7c: /* haddpd */
6200 case 0xf20f7c: /* haddps */
6201 case 0x660f7d: /* hsubpd */
6202 case 0xf20f7d: /* hsubps */
6203 case 0xf30f7e: /* movq */
6204 case 0x0fc2: /* cmpps */
6205 case 0x660fc2: /* cmppd */
6206 case 0xf20fc2: /* cmpsd */
6207 case 0xf30fc2: /* cmpss */
6208 case 0x660fc4: /* pinsrw */
6209 case 0x0fc6: /* shufps */
6210 case 0x660fc6: /* shufpd */
6211 case 0x660fd0: /* addsubpd */
6212 case 0xf20fd0: /* addsubps */
6213 case 0x660fd1: /* psrlw */
6214 case 0x660fd2: /* psrld */
6215 case 0x660fd3: /* psrlq */
6216 case 0x660fd4: /* paddq */
6217 case 0x660fd5: /* pmullw */
6218 case 0xf30fd6: /* movq2dq */
6219 case 0x660fd8: /* psubusb */
6220 case 0x660fd9: /* psubusw */
6221 case 0x660fda: /* pminub */
6222 case 0x660fdb: /* pand */
6223 case 0x660fdc: /* paddusb */
6224 case 0x660fdd: /* paddusw */
6225 case 0x660fde: /* pmaxub */
6226 case 0x660fdf: /* pandn */
6227 case 0x660fe0: /* pavgb */
6228 case 0x660fe1: /* psraw */
6229 case 0x660fe2: /* psrad */
6230 case 0x660fe3: /* pavgw */
6231 case 0x660fe4: /* pmulhuw */
6232 case 0x660fe5: /* pmulhw */
6233 case 0x660fe6: /* cvttpd2dq */
6234 case 0xf20fe6: /* cvtpd2dq */
6235 case 0xf30fe6: /* cvtdq2pd */
6236 case 0x660fe8: /* psubsb */
6237 case 0x660fe9: /* psubsw */
6238 case 0x660fea: /* pminsw */
6239 case 0x660feb: /* por */
6240 case 0x660fec: /* paddsb */
6241 case 0x660fed: /* paddsw */
6242 case 0x660fee: /* pmaxsw */
6243 case 0x660fef: /* pxor */
6244 case 0x660ff0: /* lddqu */
6245 case 0x660ff1: /* psllw */
6246 case 0x660ff2: /* pslld */
6247 case 0x660ff3: /* psllq */
6248 case 0x660ff4: /* pmuludq */
6249 case 0x660ff5: /* pmaddwd */
6250 case 0x660ff6: /* psadbw */
6251 case 0x660ff8: /* psubb */
6252 case 0x660ff9: /* psubw */
6253 case 0x660ffa: /* psubl */
6254 case 0x660ffb: /* psubq */
6255 case 0x660ffc: /* paddb */
6256 case 0x660ffd: /* paddw */
6257 case 0x660ffe: /* paddl */
6258 if (i386_record_modrm (&ir))
6261 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
6263 record_arch_list_add_reg (ir.regcache,
6264 I387_XMM0_REGNUM (tdep) + ir.reg);
6265 if ((opcode & 0xfffffffc) == 0x660f3a60)
6266 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6269 case 0x0f11: /* movups */
6270 case 0x660f11: /* movupd */
6271 case 0xf30f11: /* movss */
6272 case 0xf20f11: /* movsd */
6273 case 0x0f13: /* movlps */
6274 case 0x660f13: /* movlpd */
6275 case 0x0f17: /* movhps */
6276 case 0x660f17: /* movhpd */
6277 case 0x0f29: /* movaps */
6278 case 0x660f29: /* movapd */
6279 case 0x660f3a14: /* pextrb */
6280 case 0x660f3a15: /* pextrw */
6281 case 0x660f3a16: /* pextrd pextrq */
6282 case 0x660f3a17: /* extractps */
6283 case 0x660f7f: /* movdqa */
6284 case 0xf30f7f: /* movdqu */
6285 if (i386_record_modrm (&ir))
6289 if (opcode == 0x0f13 || opcode == 0x660f13
6290 || opcode == 0x0f17 || opcode == 0x660f17)
6293 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
6295 record_arch_list_add_reg (ir.regcache,
6296 I387_XMM0_REGNUM (tdep) + ir.rm);
6318 if (i386_record_lea_modrm (&ir))
6323 case 0x0f2b: /* movntps */
6324 case 0x660f2b: /* movntpd */
6325 case 0x0fe7: /* movntq */
6326 case 0x660fe7: /* movntdq */
6329 if (opcode == 0x0fe7)
6333 if (i386_record_lea_modrm (&ir))
6337 case 0xf30f2c: /* cvttss2si */
6338 case 0xf20f2c: /* cvttsd2si */
6339 case 0xf30f2d: /* cvtss2si */
6340 case 0xf20f2d: /* cvtsd2si */
6341 case 0xf20f38f0: /* crc32 */
6342 case 0xf20f38f1: /* crc32 */
6343 case 0x0f50: /* movmskps */
6344 case 0x660f50: /* movmskpd */
6345 case 0x0fc5: /* pextrw */
6346 case 0x660fc5: /* pextrw */
6347 case 0x0fd7: /* pmovmskb */
6348 case 0x660fd7: /* pmovmskb */
6349 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6352 case 0x0f3800: /* pshufb */
6353 case 0x0f3801: /* phaddw */
6354 case 0x0f3802: /* phaddd */
6355 case 0x0f3803: /* phaddsw */
6356 case 0x0f3804: /* pmaddubsw */
6357 case 0x0f3805: /* phsubw */
6358 case 0x0f3806: /* phsubd */
6359 case 0x0f3807: /* phaddsw */
6360 case 0x0f3808: /* psignb */
6361 case 0x0f3809: /* psignw */
6362 case 0x0f380a: /* psignd */
6363 case 0x0f380b: /* pmulhrsw */
6364 case 0x0f381c: /* pabsb */
6365 case 0x0f381d: /* pabsw */
6366 case 0x0f381e: /* pabsd */
6367 case 0x0f382b: /* packusdw */
6368 case 0x0f3830: /* pmovzxbw */
6369 case 0x0f3831: /* pmovzxbd */
6370 case 0x0f3832: /* pmovzxbq */
6371 case 0x0f3833: /* pmovzxwd */
6372 case 0x0f3834: /* pmovzxwq */
6373 case 0x0f3835: /* pmovzxdq */
6374 case 0x0f3837: /* pcmpgtq */
6375 case 0x0f3838: /* pminsb */
6376 case 0x0f3839: /* pminsd */
6377 case 0x0f383a: /* pminuw */
6378 case 0x0f383b: /* pminud */
6379 case 0x0f383c: /* pmaxsb */
6380 case 0x0f383d: /* pmaxsd */
6381 case 0x0f383e: /* pmaxuw */
6382 case 0x0f383f: /* pmaxud */
6383 case 0x0f3840: /* pmulld */
6384 case 0x0f3841: /* phminposuw */
6385 case 0x0f3a0f: /* palignr */
6386 case 0x0f60: /* punpcklbw */
6387 case 0x0f61: /* punpcklwd */
6388 case 0x0f62: /* punpckldq */
6389 case 0x0f63: /* packsswb */
6390 case 0x0f64: /* pcmpgtb */
6391 case 0x0f65: /* pcmpgtw */
6392 case 0x0f66: /* pcmpgtl */
6393 case 0x0f67: /* packuswb */
6394 case 0x0f68: /* punpckhbw */
6395 case 0x0f69: /* punpckhwd */
6396 case 0x0f6a: /* punpckhdq */
6397 case 0x0f6b: /* packssdw */
6398 case 0x0f6e: /* movd */
6399 case 0x0f6f: /* movq */
6400 case 0x0f70: /* pshufw */
6401 case 0x0f74: /* pcmpeqb */
6402 case 0x0f75: /* pcmpeqw */
6403 case 0x0f76: /* pcmpeql */
6404 case 0x0fc4: /* pinsrw */
6405 case 0x0fd1: /* psrlw */
6406 case 0x0fd2: /* psrld */
6407 case 0x0fd3: /* psrlq */
6408 case 0x0fd4: /* paddq */
6409 case 0x0fd5: /* pmullw */
6410 case 0xf20fd6: /* movdq2q */
6411 case 0x0fd8: /* psubusb */
6412 case 0x0fd9: /* psubusw */
6413 case 0x0fda: /* pminub */
6414 case 0x0fdb: /* pand */
6415 case 0x0fdc: /* paddusb */
6416 case 0x0fdd: /* paddusw */
6417 case 0x0fde: /* pmaxub */
6418 case 0x0fdf: /* pandn */
6419 case 0x0fe0: /* pavgb */
6420 case 0x0fe1: /* psraw */
6421 case 0x0fe2: /* psrad */
6422 case 0x0fe3: /* pavgw */
6423 case 0x0fe4: /* pmulhuw */
6424 case 0x0fe5: /* pmulhw */
6425 case 0x0fe8: /* psubsb */
6426 case 0x0fe9: /* psubsw */
6427 case 0x0fea: /* pminsw */
6428 case 0x0feb: /* por */
6429 case 0x0fec: /* paddsb */
6430 case 0x0fed: /* paddsw */
6431 case 0x0fee: /* pmaxsw */
6432 case 0x0fef: /* pxor */
6433 case 0x0ff1: /* psllw */
6434 case 0x0ff2: /* pslld */
6435 case 0x0ff3: /* psllq */
6436 case 0x0ff4: /* pmuludq */
6437 case 0x0ff5: /* pmaddwd */
6438 case 0x0ff6: /* psadbw */
6439 case 0x0ff8: /* psubb */
6440 case 0x0ff9: /* psubw */
6441 case 0x0ffa: /* psubl */
6442 case 0x0ffb: /* psubq */
6443 case 0x0ffc: /* paddb */
6444 case 0x0ffd: /* paddw */
6445 case 0x0ffe: /* paddl */
6446 if (i386_record_modrm (&ir))
6448 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
6450 record_arch_list_add_reg (ir.regcache,
6451 I387_MM0_REGNUM (tdep) + ir.reg);
6454 case 0x0f71: /* psllw */
6455 case 0x0f72: /* pslld */
6456 case 0x0f73: /* psllq */
6457 if (i386_record_modrm (&ir))
6459 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
6461 record_arch_list_add_reg (ir.regcache,
6462 I387_MM0_REGNUM (tdep) + ir.rm);
6465 case 0x660f71: /* psllw */
6466 case 0x660f72: /* pslld */
6467 case 0x660f73: /* psllq */
6468 if (i386_record_modrm (&ir))
6471 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
6473 record_arch_list_add_reg (ir.regcache,
6474 I387_XMM0_REGNUM (tdep) + ir.rm);
6477 case 0x0f7e: /* movd */
6478 case 0x660f7e: /* movd */
6479 if (i386_record_modrm (&ir))
6482 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6489 if (i386_record_lea_modrm (&ir))
6494 case 0x0f7f: /* movq */
6495 if (i386_record_modrm (&ir))
6499 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
6501 record_arch_list_add_reg (ir.regcache,
6502 I387_MM0_REGNUM (tdep) + ir.rm);
6507 if (i386_record_lea_modrm (&ir))
6512 case 0xf30fb8: /* popcnt */
6513 if (i386_record_modrm (&ir))
6515 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
6516 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6519 case 0x660fd6: /* movq */
6520 if (i386_record_modrm (&ir))
6525 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
6527 record_arch_list_add_reg (ir.regcache,
6528 I387_XMM0_REGNUM (tdep) + ir.rm);
6533 if (i386_record_lea_modrm (&ir))
6538 case 0x660f3817: /* ptest */
6539 case 0x0f2e: /* ucomiss */
6540 case 0x660f2e: /* ucomisd */
6541 case 0x0f2f: /* comiss */
6542 case 0x660f2f: /* comisd */
6543 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6546 case 0x0ff7: /* maskmovq */
6547 regcache_raw_read_unsigned (ir.regcache,
6548 ir.regmap[X86_RECORD_REDI_REGNUM],
6550 if (record_arch_list_add_mem (addr, 64))
6554 case 0x660ff7: /* maskmovdqu */
6555 regcache_raw_read_unsigned (ir.regcache,
6556 ir.regmap[X86_RECORD_REDI_REGNUM],
6558 if (record_arch_list_add_mem (addr, 128))
6573 /* In the future, maybe still need to deal with need_dasm. */
6574 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
6575 if (record_arch_list_add_end ())
6581 printf_unfiltered (_("Process record does not support instruction 0x%02x "
6582 "at address %s.\n"),
6583 (unsigned int) (opcode),
6584 paddress (gdbarch, ir.orig_addr));
6588 static const int i386_record_regmap[] =
6590 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
6591 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
6592 0, 0, 0, 0, 0, 0, 0, 0,
6593 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
6594 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
6597 /* Check that the given address appears suitable for a fast
6598 tracepoint, which on x86 means that we need an instruction of at
6599 least 5 bytes, so that we can overwrite it with a 4-byte-offset
6600 jump and not have to worry about program jumps to an address in the
6601 middle of the tracepoint jump. Returns 1 if OK, and writes a size
6602 of instruction to replace, and 0 if not, plus an explanatory
6606 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch,
6607 CORE_ADDR addr, int *isize, char **msg)
6610 static struct ui_file *gdb_null = NULL;
6612 /* This is based on the target agent using a 4-byte relative jump.
6613 Alternate future possibilities include 8-byte offset for x86-84,
6614 or 3-byte jumps if the program has trampoline space close by. */
6617 /* Dummy file descriptor for the disassembler. */
6619 gdb_null = ui_file_new ();
6621 /* Check for fit. */
6622 len = gdb_print_insn (gdbarch, addr, gdb_null, NULL);
6625 /* Return a bit of target-specific detail to add to the caller's
6626 generic failure message. */
6628 *msg = xstrprintf (_("; instruction is only %d bytes long, need at least %d bytes for the jump"),
6641 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
6642 struct tdesc_arch_data *tdesc_data)
6644 const struct target_desc *tdesc = tdep->tdesc;
6645 const struct tdesc_feature *feature_core;
6646 const struct tdesc_feature *feature_sse, *feature_avx;
6647 int i, num_regs, valid_p;
6649 if (! tdesc_has_registers (tdesc))
6652 /* Get core registers. */
6653 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
6655 /* Get SSE registers. */
6656 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
6658 if (feature_core == NULL || feature_sse == NULL)
6661 /* Try AVX registers. */
6662 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
6666 /* The XCR0 bits. */
6669 tdep->xcr0 = I386_XSTATE_AVX_MASK;
6671 /* It may have been set by OSABI initialization function. */
6672 if (tdep->num_ymm_regs == 0)
6674 tdep->ymmh_register_names = i386_ymmh_names;
6675 tdep->num_ymm_regs = 8;
6676 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
6679 for (i = 0; i < tdep->num_ymm_regs; i++)
6680 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
6681 tdep->ymm0h_regnum + i,
6682 tdep->ymmh_register_names[i]);
6685 tdep->xcr0 = I386_XSTATE_SSE_MASK;
6687 num_regs = tdep->num_core_regs;
6688 for (i = 0; i < num_regs; i++)
6689 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
6690 tdep->register_names[i]);
6692 /* Need to include %mxcsr, so add one. */
6693 num_regs += tdep->num_xmm_regs + 1;
6694 for (; i < num_regs; i++)
6695 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
6696 tdep->register_names[i]);
6702 static struct gdbarch *
6703 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
6705 struct gdbarch_tdep *tdep;
6706 struct gdbarch *gdbarch;
6707 struct tdesc_arch_data *tdesc_data;
6708 const struct target_desc *tdesc;
6712 /* If there is already a candidate, use it. */
6713 arches = gdbarch_list_lookup_by_info (arches, &info);
6715 return arches->gdbarch;
6717 /* Allocate space for the new architecture. */
6718 tdep = XCALLOC (1, struct gdbarch_tdep);
6719 gdbarch = gdbarch_alloc (&info, tdep);
6721 /* General-purpose registers. */
6722 tdep->gregset = NULL;
6723 tdep->gregset_reg_offset = NULL;
6724 tdep->gregset_num_regs = I386_NUM_GREGS;
6725 tdep->sizeof_gregset = 0;
6727 /* Floating-point registers. */
6728 tdep->fpregset = NULL;
6729 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
6731 tdep->xstateregset = NULL;
6733 /* The default settings include the FPU registers, the MMX registers
6734 and the SSE registers. This can be overridden for a specific ABI
6735 by adjusting the members `st0_regnum', `mm0_regnum' and
6736 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
6737 will show up in the output of "info all-registers". Ideally we
6738 should try to autodetect whether they are available, such that we
6739 can prevent "info all-registers" from displaying registers that
6742 NOTE: kevinb/2003-07-13: ... if it's a choice between printing
6743 [the SSE registers] always (even when they don't exist) or never
6744 showing them to the user (even when they do exist), I prefer the
6745 former over the latter. */
6747 tdep->st0_regnum = I386_ST0_REGNUM;
6749 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
6750 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
6752 tdep->jb_pc_offset = -1;
6753 tdep->struct_return = pcc_struct_return;
6754 tdep->sigtramp_start = 0;
6755 tdep->sigtramp_end = 0;
6756 tdep->sigtramp_p = i386_sigtramp_p;
6757 tdep->sigcontext_addr = NULL;
6758 tdep->sc_reg_offset = NULL;
6759 tdep->sc_pc_offset = -1;
6760 tdep->sc_sp_offset = -1;
6762 tdep->xsave_xcr0_offset = -1;
6764 tdep->record_regmap = i386_record_regmap;
6766 /* The format used for `long double' on almost all i386 targets is
6767 the i387 extended floating-point format. In fact, of all targets
6768 in the GCC 2.95 tree, only OSF/1 does it different, and insists
6769 on having a `long double' that's not `long' at all. */
6770 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
6772 /* Although the i387 extended floating-point has only 80 significant
6773 bits, a `long double' actually takes up 96, probably to enforce
6775 set_gdbarch_long_double_bit (gdbarch, 96);
6777 /* Register numbers of various important registers. */
6778 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
6779 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
6780 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
6781 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
6783 /* NOTE: kettenis/20040418: GCC does have two possible register
6784 numbering schemes on the i386: dbx and SVR4. These schemes
6785 differ in how they number %ebp, %esp, %eflags, and the
6786 floating-point registers, and are implemented by the arrays
6787 dbx_register_map[] and svr4_dbx_register_map in
6788 gcc/config/i386.c. GCC also defines a third numbering scheme in
6789 gcc/config/i386.c, which it designates as the "default" register
6790 map used in 64bit mode. This last register numbering scheme is
6791 implemented in dbx64_register_map, and is used for AMD64; see
6794 Currently, each GCC i386 target always uses the same register
6795 numbering scheme across all its supported debugging formats
6796 i.e. SDB (COFF), stabs and DWARF 2. This is because
6797 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
6798 DBX_REGISTER_NUMBER macro which is defined by each target's
6799 respective config header in a manner independent of the requested
6800 output debugging format.
6802 This does not match the arrangement below, which presumes that
6803 the SDB and stabs numbering schemes differ from the DWARF and
6804 DWARF 2 ones. The reason for this arrangement is that it is
6805 likely to get the numbering scheme for the target's
6806 default/native debug format right. For targets where GCC is the
6807 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
6808 targets where the native toolchain uses a different numbering
6809 scheme for a particular debug format (stabs-in-ELF on Solaris)
6810 the defaults below will have to be overridden, like
6811 i386_elf_init_abi() does. */
6813 /* Use the dbx register numbering scheme for stabs and COFF. */
6814 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
6815 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
6817 /* Use the SVR4 register numbering scheme for DWARF 2. */
6818 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
6820 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
6821 be in use on any of the supported i386 targets. */
6823 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
6825 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
6827 /* Call dummy code. */
6828 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
6830 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
6831 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
6832 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
6834 set_gdbarch_return_value (gdbarch, i386_return_value);
6836 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
6838 /* Stack grows downward. */
6839 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
6841 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc);
6842 set_gdbarch_decr_pc_after_break (gdbarch, 1);
6843 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
6845 set_gdbarch_frame_args_skip (gdbarch, 8);
6847 set_gdbarch_print_insn (gdbarch, i386_print_insn);
6849 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
6851 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
6853 /* Add the i386 register groups. */
6854 i386_add_reggroups (gdbarch);
6855 tdep->register_reggroup_p = i386_register_reggroup_p;
6857 /* Helper for function argument information. */
6858 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
6860 /* Hook the function epilogue frame unwinder. This unwinder is
6861 appended to the list first, so that it supercedes the Dwarf
6862 unwinder in function epilogues (where the Dwarf unwinder
6863 currently fails). */
6864 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
6866 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
6867 to the list before the prologue-based unwinders, so that Dwarf
6868 CFI info will be used if it is available. */
6869 dwarf2_append_unwinders (gdbarch);
6871 frame_base_set_default (gdbarch, &i386_frame_base);
6873 /* Pseudo registers may be changed by amd64_init_abi. */
6874 set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read);
6875 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
6877 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
6878 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
6880 /* Override the normal target description method to make the AVX
6881 upper halves anonymous. */
6882 set_gdbarch_register_name (gdbarch, i386_register_name);
6884 /* Even though the default ABI only includes general-purpose registers,
6885 floating-point registers and the SSE registers, we have to leave a
6886 gap for the upper AVX registers. */
6887 set_gdbarch_num_regs (gdbarch, I386_AVX_NUM_REGS);
6889 /* Get the x86 target description from INFO. */
6890 tdesc = info.target_desc;
6891 if (! tdesc_has_registers (tdesc))
6893 tdep->tdesc = tdesc;
6895 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
6896 tdep->register_names = i386_register_names;
6898 /* No upper YMM registers. */
6899 tdep->ymmh_register_names = NULL;
6900 tdep->ymm0h_regnum = -1;
6902 tdep->num_byte_regs = 8;
6903 tdep->num_word_regs = 8;
6904 tdep->num_dword_regs = 0;
6905 tdep->num_mmx_regs = 8;
6906 tdep->num_ymm_regs = 0;
6908 tdesc_data = tdesc_data_alloc ();
6910 /* Hook in ABI-specific overrides, if they have been registered. */
6911 info.tdep_info = (void *) tdesc_data;
6912 gdbarch_init_osabi (info, gdbarch);
6914 if (!i386_validate_tdesc_p (tdep, tdesc_data))
6916 tdesc_data_cleanup (tdesc_data);
6918 gdbarch_free (gdbarch);
6922 /* Wire in pseudo registers. Number of pseudo registers may be
6924 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
6925 + tdep->num_word_regs
6926 + tdep->num_dword_regs
6927 + tdep->num_mmx_regs
6928 + tdep->num_ymm_regs));
6930 /* Target description may be changed. */
6931 tdesc = tdep->tdesc;
6933 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
6935 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
6936 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
6938 /* Make %al the first pseudo-register. */
6939 tdep->al_regnum = gdbarch_num_regs (gdbarch);
6940 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
6942 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
6943 if (tdep->num_dword_regs)
6945 /* Support dword pseudo-registesr if it hasn't been disabled, */
6946 tdep->eax_regnum = ymm0_regnum;
6947 ymm0_regnum += tdep->num_dword_regs;
6950 tdep->eax_regnum = -1;
6952 mm0_regnum = ymm0_regnum;
6953 if (tdep->num_ymm_regs)
6955 /* Support YMM pseudo-registesr if it is available, */
6956 tdep->ymm0_regnum = ymm0_regnum;
6957 mm0_regnum += tdep->num_ymm_regs;
6960 tdep->ymm0_regnum = -1;
6962 if (tdep->num_mmx_regs != 0)
6964 /* Support MMX pseudo-registesr if MMX hasn't been disabled, */
6965 tdep->mm0_regnum = mm0_regnum;
6968 tdep->mm0_regnum = -1;
6970 /* Hook in the legacy prologue-based unwinders last (fallback). */
6971 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
6972 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
6974 /* If we have a register mapping, enable the generic core file
6975 support, unless it has already been enabled. */
6976 if (tdep->gregset_reg_offset
6977 && !gdbarch_regset_from_core_section_p (gdbarch))
6978 set_gdbarch_regset_from_core_section (gdbarch,
6979 i386_regset_from_core_section);
6981 set_gdbarch_skip_permanent_breakpoint (gdbarch,
6982 i386_skip_permanent_breakpoint);
6984 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
6985 i386_fast_tracepoint_valid_at);
6990 static enum gdb_osabi
6991 i386_coff_osabi_sniffer (bfd *abfd)
6993 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
6994 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
6995 return GDB_OSABI_GO32;
6997 return GDB_OSABI_UNKNOWN;
7001 /* Provide a prototype to silence -Wmissing-prototypes. */
7002 void _initialize_i386_tdep (void);
7005 _initialize_i386_tdep (void)
7007 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
7009 /* Add the variable that controls the disassembly flavor. */
7010 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
7011 &disassembly_flavor, _("\
7012 Set the disassembly flavor."), _("\
7013 Show the disassembly flavor."), _("\
7014 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7016 NULL, /* FIXME: i18n: */
7017 &setlist, &showlist);
7019 /* Add the variable that controls the convention for returning
7021 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
7022 &struct_convention, _("\
7023 Set the convention for returning small structs."), _("\
7024 Show the convention for returning small structs."), _("\
7025 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7028 NULL, /* FIXME: i18n: */
7029 &setlist, &showlist);
7031 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
7032 i386_coff_osabi_sniffer);
7034 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
7035 i386_svr4_init_abi);
7036 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
7037 i386_go32_init_abi);
7039 /* Initialize the i386-specific register groups. */
7040 i386_init_reggroups ();
7042 /* Initialize the standard target descriptions. */
7043 initialize_tdesc_i386 ();
7044 initialize_tdesc_i386_avx ();
7046 /* Tell remote stub that we support XML target description. */
7047 register_remote_support_xml ("i386");