1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
49 #include "gdb_assert.h"
50 #include "gdb_string.h"
52 #include "i386-tdep.h"
53 #include "i387-tdep.h"
54 #include "i386-xstate.h"
59 #include "features/i386/i386.c"
60 #include "features/i386/i386-avx.c"
61 #include "features/i386/i386-mmx.c"
65 static const char *i386_register_names[] =
67 "eax", "ecx", "edx", "ebx",
68 "esp", "ebp", "esi", "edi",
69 "eip", "eflags", "cs", "ss",
70 "ds", "es", "fs", "gs",
71 "st0", "st1", "st2", "st3",
72 "st4", "st5", "st6", "st7",
73 "fctrl", "fstat", "ftag", "fiseg",
74 "fioff", "foseg", "fooff", "fop",
75 "xmm0", "xmm1", "xmm2", "xmm3",
76 "xmm4", "xmm5", "xmm6", "xmm7",
80 static const char *i386_ymm_names[] =
82 "ymm0", "ymm1", "ymm2", "ymm3",
83 "ymm4", "ymm5", "ymm6", "ymm7",
86 static const char *i386_ymmh_names[] =
88 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
89 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
92 /* Register names for MMX pseudo-registers. */
94 static const char *i386_mmx_names[] =
96 "mm0", "mm1", "mm2", "mm3",
97 "mm4", "mm5", "mm6", "mm7"
100 /* Register names for byte pseudo-registers. */
102 static const char *i386_byte_names[] =
104 "al", "cl", "dl", "bl",
105 "ah", "ch", "dh", "bh"
108 /* Register names for word pseudo-registers. */
110 static const char *i386_word_names[] =
112 "ax", "cx", "dx", "bx",
119 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
121 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
122 int mm0_regnum = tdep->mm0_regnum;
127 regnum -= mm0_regnum;
128 return regnum >= 0 && regnum < tdep->num_mmx_regs;
134 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
136 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
138 regnum -= tdep->al_regnum;
139 return regnum >= 0 && regnum < tdep->num_byte_regs;
145 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
147 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
149 regnum -= tdep->ax_regnum;
150 return regnum >= 0 && regnum < tdep->num_word_regs;
153 /* Dword register? */
156 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
158 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
159 int eax_regnum = tdep->eax_regnum;
164 regnum -= eax_regnum;
165 return regnum >= 0 && regnum < tdep->num_dword_regs;
169 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
171 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
172 int ymm0h_regnum = tdep->ymm0h_regnum;
174 if (ymm0h_regnum < 0)
177 regnum -= ymm0h_regnum;
178 return regnum >= 0 && regnum < tdep->num_ymm_regs;
184 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
186 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
187 int ymm0_regnum = tdep->ymm0_regnum;
192 regnum -= ymm0_regnum;
193 return regnum >= 0 && regnum < tdep->num_ymm_regs;
199 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
201 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
202 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
204 if (num_xmm_regs == 0)
207 regnum -= I387_XMM0_REGNUM (tdep);
208 return regnum >= 0 && regnum < num_xmm_regs;
212 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
214 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
216 if (I387_NUM_XMM_REGS (tdep) == 0)
219 return (regnum == I387_MXCSR_REGNUM (tdep));
225 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
227 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
229 if (I387_ST0_REGNUM (tdep) < 0)
232 return (I387_ST0_REGNUM (tdep) <= regnum
233 && regnum < I387_FCTRL_REGNUM (tdep));
237 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
239 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
241 if (I387_ST0_REGNUM (tdep) < 0)
244 return (I387_FCTRL_REGNUM (tdep) <= regnum
245 && regnum < I387_XMM0_REGNUM (tdep));
248 /* Return the name of register REGNUM, or the empty string if it is
249 an anonymous register. */
252 i386_register_name (struct gdbarch *gdbarch, int regnum)
254 /* Hide the upper YMM registers. */
255 if (i386_ymmh_regnum_p (gdbarch, regnum))
258 return tdesc_register_name (gdbarch, regnum);
261 /* Return the name of register REGNUM. */
264 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
266 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
267 if (i386_mmx_regnum_p (gdbarch, regnum))
268 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
269 else if (i386_ymm_regnum_p (gdbarch, regnum))
270 return i386_ymm_names[regnum - tdep->ymm0_regnum];
271 else if (i386_byte_regnum_p (gdbarch, regnum))
272 return i386_byte_names[regnum - tdep->al_regnum];
273 else if (i386_word_regnum_p (gdbarch, regnum))
274 return i386_word_names[regnum - tdep->ax_regnum];
276 internal_error (__FILE__, __LINE__, _("invalid regnum"));
279 /* Convert a dbx register number REG to the appropriate register
280 number used by GDB. */
283 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
285 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
287 /* This implements what GCC calls the "default" register map
288 (dbx_register_map[]). */
290 if (reg >= 0 && reg <= 7)
292 /* General-purpose registers. The debug info calls %ebp
293 register 4, and %esp register 5. */
300 else if (reg >= 12 && reg <= 19)
302 /* Floating-point registers. */
303 return reg - 12 + I387_ST0_REGNUM (tdep);
305 else if (reg >= 21 && reg <= 28)
308 int ymm0_regnum = tdep->ymm0_regnum;
311 && i386_xmm_regnum_p (gdbarch, reg))
312 return reg - 21 + ymm0_regnum;
314 return reg - 21 + I387_XMM0_REGNUM (tdep);
316 else if (reg >= 29 && reg <= 36)
319 return reg - 29 + I387_MM0_REGNUM (tdep);
322 /* This will hopefully provoke a warning. */
323 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
326 /* Convert SVR4 register number REG to the appropriate register number
330 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
332 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
334 /* This implements the GCC register map that tries to be compatible
335 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
337 /* The SVR4 register numbering includes %eip and %eflags, and
338 numbers the floating point registers differently. */
339 if (reg >= 0 && reg <= 9)
341 /* General-purpose registers. */
344 else if (reg >= 11 && reg <= 18)
346 /* Floating-point registers. */
347 return reg - 11 + I387_ST0_REGNUM (tdep);
349 else if (reg >= 21 && reg <= 36)
351 /* The SSE and MMX registers have the same numbers as with dbx. */
352 return i386_dbx_reg_to_regnum (gdbarch, reg);
357 case 37: return I387_FCTRL_REGNUM (tdep);
358 case 38: return I387_FSTAT_REGNUM (tdep);
359 case 39: return I387_MXCSR_REGNUM (tdep);
360 case 40: return I386_ES_REGNUM;
361 case 41: return I386_CS_REGNUM;
362 case 42: return I386_SS_REGNUM;
363 case 43: return I386_DS_REGNUM;
364 case 44: return I386_FS_REGNUM;
365 case 45: return I386_GS_REGNUM;
368 /* This will hopefully provoke a warning. */
369 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
374 /* This is the variable that is set with "set disassembly-flavor", and
375 its legitimate values. */
376 static const char att_flavor[] = "att";
377 static const char intel_flavor[] = "intel";
378 static const char *valid_flavors[] =
384 static const char *disassembly_flavor = att_flavor;
387 /* Use the program counter to determine the contents and size of a
388 breakpoint instruction. Return a pointer to a string of bytes that
389 encode a breakpoint instruction, store the length of the string in
390 *LEN and optionally adjust *PC to point to the correct memory
391 location for inserting the breakpoint.
393 On the i386 we have a single breakpoint that fits in a single byte
394 and can be inserted anywhere.
396 This function is 64-bit safe. */
398 static const gdb_byte *
399 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
401 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */
403 *len = sizeof (break_insn);
407 /* Displaced instruction handling. */
409 /* Skip the legacy instruction prefixes in INSN.
410 Not all prefixes are valid for any particular insn
411 but we needn't care, the insn will fault if it's invalid.
412 The result is a pointer to the first opcode byte,
413 or NULL if we run off the end of the buffer. */
416 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
418 gdb_byte *end = insn + max_len;
424 case DATA_PREFIX_OPCODE:
425 case ADDR_PREFIX_OPCODE:
426 case CS_PREFIX_OPCODE:
427 case DS_PREFIX_OPCODE:
428 case ES_PREFIX_OPCODE:
429 case FS_PREFIX_OPCODE:
430 case GS_PREFIX_OPCODE:
431 case SS_PREFIX_OPCODE:
432 case LOCK_PREFIX_OPCODE:
433 case REPE_PREFIX_OPCODE:
434 case REPNE_PREFIX_OPCODE:
446 i386_absolute_jmp_p (const gdb_byte *insn)
448 /* jmp far (absolute address in operand) */
454 /* jump near, absolute indirect (/4) */
455 if ((insn[1] & 0x38) == 0x20)
458 /* jump far, absolute indirect (/5) */
459 if ((insn[1] & 0x38) == 0x28)
467 i386_absolute_call_p (const gdb_byte *insn)
469 /* call far, absolute */
475 /* Call near, absolute indirect (/2) */
476 if ((insn[1] & 0x38) == 0x10)
479 /* Call far, absolute indirect (/3) */
480 if ((insn[1] & 0x38) == 0x18)
488 i386_ret_p (const gdb_byte *insn)
492 case 0xc2: /* ret near, pop N bytes */
493 case 0xc3: /* ret near */
494 case 0xca: /* ret far, pop N bytes */
495 case 0xcb: /* ret far */
496 case 0xcf: /* iret */
505 i386_call_p (const gdb_byte *insn)
507 if (i386_absolute_call_p (insn))
510 /* call near, relative */
517 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
518 length in bytes. Otherwise, return zero. */
521 i386_syscall_p (const gdb_byte *insn, int *lengthp)
532 /* Some kernels may run one past a syscall insn, so we have to cope.
533 Otherwise this is just simple_displaced_step_copy_insn. */
535 struct displaced_step_closure *
536 i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
537 CORE_ADDR from, CORE_ADDR to,
538 struct regcache *regs)
540 size_t len = gdbarch_max_insn_length (gdbarch);
541 gdb_byte *buf = xmalloc (len);
543 read_memory (from, buf, len);
545 /* GDB may get control back after the insn after the syscall.
546 Presumably this is a kernel bug.
547 If this is a syscall, make sure there's a nop afterwards. */
552 insn = i386_skip_prefixes (buf, len);
553 if (insn != NULL && i386_syscall_p (insn, &syscall_length))
554 insn[syscall_length] = NOP_OPCODE;
557 write_memory (to, buf, len);
561 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
562 paddress (gdbarch, from), paddress (gdbarch, to));
563 displaced_step_dump_bytes (gdb_stdlog, buf, len);
566 return (struct displaced_step_closure *) buf;
569 /* Fix up the state of registers and memory after having single-stepped
570 a displaced instruction. */
573 i386_displaced_step_fixup (struct gdbarch *gdbarch,
574 struct displaced_step_closure *closure,
575 CORE_ADDR from, CORE_ADDR to,
576 struct regcache *regs)
578 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
580 /* The offset we applied to the instruction's address.
581 This could well be negative (when viewed as a signed 32-bit
582 value), but ULONGEST won't reflect that, so take care when
584 ULONGEST insn_offset = to - from;
586 /* Since we use simple_displaced_step_copy_insn, our closure is a
587 copy of the instruction. */
588 gdb_byte *insn = (gdb_byte *) closure;
589 /* The start of the insn, needed in case we see some prefixes. */
590 gdb_byte *insn_start = insn;
593 fprintf_unfiltered (gdb_stdlog,
594 "displaced: fixup (%s, %s), "
595 "insn = 0x%02x 0x%02x ...\n",
596 paddress (gdbarch, from), paddress (gdbarch, to),
599 /* The list of issues to contend with here is taken from
600 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
601 Yay for Free Software! */
603 /* Relocate the %eip, if necessary. */
605 /* The instruction recognizers we use assume any leading prefixes
606 have been skipped. */
608 /* This is the size of the buffer in closure. */
609 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
610 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
611 /* If there are too many prefixes, just ignore the insn.
612 It will fault when run. */
617 /* Except in the case of absolute or indirect jump or call
618 instructions, or a return instruction, the new eip is relative to
619 the displaced instruction; make it relative. Well, signal
620 handler returns don't need relocation either, but we use the
621 value of %eip to recognize those; see below. */
622 if (! i386_absolute_jmp_p (insn)
623 && ! i386_absolute_call_p (insn)
624 && ! i386_ret_p (insn))
629 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
631 /* A signal trampoline system call changes the %eip, resuming
632 execution of the main program after the signal handler has
633 returned. That makes them like 'return' instructions; we
634 shouldn't relocate %eip.
636 But most system calls don't, and we do need to relocate %eip.
638 Our heuristic for distinguishing these cases: if stepping
639 over the system call instruction left control directly after
640 the instruction, the we relocate --- control almost certainly
641 doesn't belong in the displaced copy. Otherwise, we assume
642 the instruction has put control where it belongs, and leave
643 it unrelocated. Goodness help us if there are PC-relative
645 if (i386_syscall_p (insn, &insn_len)
646 && orig_eip != to + (insn - insn_start) + insn_len
647 /* GDB can get control back after the insn after the syscall.
648 Presumably this is a kernel bug.
649 i386_displaced_step_copy_insn ensures its a nop,
650 we add one to the length for it. */
651 && orig_eip != to + (insn - insn_start) + insn_len + 1)
654 fprintf_unfiltered (gdb_stdlog,
655 "displaced: syscall changed %%eip; "
660 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
662 /* If we just stepped over a breakpoint insn, we don't backup
663 the pc on purpose; this is to match behaviour without
666 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
669 fprintf_unfiltered (gdb_stdlog,
671 "relocated %%eip from %s to %s\n",
672 paddress (gdbarch, orig_eip),
673 paddress (gdbarch, eip));
677 /* If the instruction was PUSHFL, then the TF bit will be set in the
678 pushed value, and should be cleared. We'll leave this for later,
679 since GDB already messes up the TF flag when stepping over a
682 /* If the instruction was a call, the return address now atop the
683 stack is the address following the copied instruction. We need
684 to make it the address following the original instruction. */
685 if (i386_call_p (insn))
689 const ULONGEST retaddr_len = 4;
691 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
692 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
693 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
694 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
697 fprintf_unfiltered (gdb_stdlog,
698 "displaced: relocated return addr at %s to %s\n",
699 paddress (gdbarch, esp),
700 paddress (gdbarch, retaddr));
705 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
707 target_write_memory (*to, buf, len);
712 i386_relocate_instruction (struct gdbarch *gdbarch,
713 CORE_ADDR *to, CORE_ADDR oldloc)
715 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
716 gdb_byte buf[I386_MAX_INSN_LEN];
717 int offset = 0, rel32, newrel;
719 gdb_byte *insn = buf;
721 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
723 insn_length = gdb_buffered_insn_length (gdbarch, insn,
724 I386_MAX_INSN_LEN, oldloc);
726 /* Get past the prefixes. */
727 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
729 /* Adjust calls with 32-bit relative addresses as push/jump, with
730 the address pushed being the location where the original call in
731 the user program would return to. */
734 gdb_byte push_buf[16];
735 unsigned int ret_addr;
737 /* Where "ret" in the original code will return to. */
738 ret_addr = oldloc + insn_length;
739 push_buf[0] = 0x68; /* pushq $... */
740 memcpy (&push_buf[1], &ret_addr, 4);
742 append_insns (to, 5, push_buf);
744 /* Convert the relative call to a relative jump. */
747 /* Adjust the destination offset. */
748 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
749 newrel = (oldloc - *to) + rel32;
750 store_signed_integer (insn + 1, 4, newrel, byte_order);
752 /* Write the adjusted jump into its displaced location. */
753 append_insns (to, 5, insn);
757 /* Adjust jumps with 32-bit relative addresses. Calls are already
761 /* Adjust conditional jumps. */
762 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
767 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
768 newrel = (oldloc - *to) + rel32;
769 store_signed_integer (insn + offset, 4, newrel, byte_order);
771 fprintf_unfiltered (gdb_stdlog,
772 "Adjusted insn rel32=0x%s at 0x%s to"
773 " rel32=0x%s at 0x%s\n",
774 hex_string (rel32), paddress (gdbarch, oldloc),
775 hex_string (newrel), paddress (gdbarch, *to));
778 /* Write the adjusted instructions into their displaced
780 append_insns (to, insn_length, buf);
784 #ifdef I386_REGNO_TO_SYMMETRY
785 #error "The Sequent Symmetry is no longer supported."
788 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
789 and %esp "belong" to the calling function. Therefore these
790 registers should be saved if they're going to be modified. */
792 /* The maximum number of saved registers. This should include all
793 registers mentioned above, and %eip. */
794 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
796 struct i386_frame_cache
803 /* Saved registers. */
804 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
809 /* Stack space reserved for local variables. */
813 /* Allocate and initialize a frame cache. */
815 static struct i386_frame_cache *
816 i386_alloc_frame_cache (void)
818 struct i386_frame_cache *cache;
821 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
825 cache->sp_offset = -4;
828 /* Saved registers. We initialize these to -1 since zero is a valid
829 offset (that's where %ebp is supposed to be stored). */
830 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
831 cache->saved_regs[i] = -1;
833 cache->saved_sp_reg = -1;
834 cache->pc_in_eax = 0;
836 /* Frameless until proven otherwise. */
842 /* If the instruction at PC is a jump, return the address of its
843 target. Otherwise, return PC. */
846 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
848 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
853 target_read_memory (pc, &op, 1);
857 op = read_memory_unsigned_integer (pc + 1, 1, byte_order);
863 /* Relative jump: if data16 == 0, disp32, else disp16. */
866 delta = read_memory_integer (pc + 2, 2, byte_order);
868 /* Include the size of the jmp instruction (including the
874 delta = read_memory_integer (pc + 1, 4, byte_order);
876 /* Include the size of the jmp instruction. */
881 /* Relative jump, disp8 (ignore data16). */
882 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
891 /* Check whether PC points at a prologue for a function returning a
892 structure or union. If so, it updates CACHE and returns the
893 address of the first instruction after the code sequence that
894 removes the "hidden" argument from the stack or CURRENT_PC,
895 whichever is smaller. Otherwise, return PC. */
898 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
899 struct i386_frame_cache *cache)
901 /* Functions that return a structure or union start with:
904 xchgl %eax, (%esp) 0x87 0x04 0x24
905 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
907 (the System V compiler puts out the second `xchg' instruction,
908 and the assembler doesn't try to optimize it, so the 'sib' form
909 gets generated). This sequence is used to get the address of the
910 return buffer for a function that returns a structure. */
911 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
912 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
916 if (current_pc <= pc)
919 target_read_memory (pc, &op, 1);
921 if (op != 0x58) /* popl %eax */
924 target_read_memory (pc + 1, buf, 4);
925 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
928 if (current_pc == pc)
930 cache->sp_offset += 4;
934 if (current_pc == pc + 1)
936 cache->pc_in_eax = 1;
940 if (buf[1] == proto1[1])
947 i386_skip_probe (CORE_ADDR pc)
949 /* A function may start with
963 target_read_memory (pc, &op, 1);
965 if (op == 0x68 || op == 0x6a)
969 /* Skip past the `pushl' instruction; it has either a one-byte or a
970 four-byte operand, depending on the opcode. */
976 /* Read the following 8 bytes, which should be `call _probe' (6
977 bytes) followed by `addl $4,%esp' (2 bytes). */
978 read_memory (pc + delta, buf, sizeof (buf));
979 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
980 pc += delta + sizeof (buf);
986 /* GCC 4.1 and later, can put code in the prologue to realign the
987 stack pointer. Check whether PC points to such code, and update
988 CACHE accordingly. Return the first instruction after the code
989 sequence or CURRENT_PC, whichever is smaller. If we don't
990 recognize the code, return PC. */
993 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
994 struct i386_frame_cache *cache)
996 /* There are 2 code sequences to re-align stack before the frame
999 1. Use a caller-saved saved register:
1005 2. Use a callee-saved saved register:
1012 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1014 0x83 0xe4 0xf0 andl $-16, %esp
1015 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1020 int offset, offset_and;
1021 static int regnums[8] = {
1022 I386_EAX_REGNUM, /* %eax */
1023 I386_ECX_REGNUM, /* %ecx */
1024 I386_EDX_REGNUM, /* %edx */
1025 I386_EBX_REGNUM, /* %ebx */
1026 I386_ESP_REGNUM, /* %esp */
1027 I386_EBP_REGNUM, /* %ebp */
1028 I386_ESI_REGNUM, /* %esi */
1029 I386_EDI_REGNUM /* %edi */
1032 if (target_read_memory (pc, buf, sizeof buf))
1035 /* Check caller-saved saved register. The first instruction has
1036 to be "leal 4(%esp), %reg". */
1037 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1039 /* MOD must be binary 10 and R/M must be binary 100. */
1040 if ((buf[1] & 0xc7) != 0x44)
1043 /* REG has register number. */
1044 reg = (buf[1] >> 3) & 7;
1049 /* Check callee-saved saved register. The first instruction
1050 has to be "pushl %reg". */
1051 if ((buf[0] & 0xf8) != 0x50)
1057 /* The next instruction has to be "leal 8(%esp), %reg". */
1058 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1061 /* MOD must be binary 10 and R/M must be binary 100. */
1062 if ((buf[2] & 0xc7) != 0x44)
1065 /* REG has register number. Registers in pushl and leal have to
1067 if (reg != ((buf[2] >> 3) & 7))
1073 /* Rigister can't be %esp nor %ebp. */
1074 if (reg == 4 || reg == 5)
1077 /* The next instruction has to be "andl $-XXX, %esp". */
1078 if (buf[offset + 1] != 0xe4
1079 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1082 offset_and = offset;
1083 offset += buf[offset] == 0x81 ? 6 : 3;
1085 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1086 0xfc. REG must be binary 110 and MOD must be binary 01. */
1087 if (buf[offset] != 0xff
1088 || buf[offset + 2] != 0xfc
1089 || (buf[offset + 1] & 0xf8) != 0x70)
1092 /* R/M has register. Registers in leal and pushl have to be the
1094 if (reg != (buf[offset + 1] & 7))
1097 if (current_pc > pc + offset_and)
1098 cache->saved_sp_reg = regnums[reg];
1100 return min (pc + offset + 3, current_pc);
1103 /* Maximum instruction length we need to handle. */
1104 #define I386_MAX_MATCHED_INSN_LEN 6
1106 /* Instruction description. */
1110 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
1111 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
1114 /* Search for the instruction at PC in the list SKIP_INSNS. Return
1115 the first instruction description that matches. Otherwise, return
1118 static struct i386_insn *
1119 i386_match_insn (CORE_ADDR pc, struct i386_insn *skip_insns)
1121 struct i386_insn *insn;
1124 target_read_memory (pc, &op, 1);
1126 for (insn = skip_insns; insn->len > 0; insn++)
1128 if ((op & insn->mask[0]) == insn->insn[0])
1130 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1131 int insn_matched = 1;
1134 gdb_assert (insn->len > 1);
1135 gdb_assert (insn->len <= I386_MAX_MATCHED_INSN_LEN);
1137 target_read_memory (pc + 1, buf, insn->len - 1);
1138 for (i = 1; i < insn->len; i++)
1140 if ((buf[i - 1] & insn->mask[i]) != insn->insn[i])
1152 /* Some special instructions that might be migrated by GCC into the
1153 part of the prologue that sets up the new stack frame. Because the
1154 stack frame hasn't been setup yet, no registers have been saved
1155 yet, and only the scratch registers %eax, %ecx and %edx can be
1158 struct i386_insn i386_frame_setup_skip_insns[] =
1160 /* Check for `movb imm8, r' and `movl imm32, r'.
1162 ??? Should we handle 16-bit operand-sizes here? */
1164 /* `movb imm8, %al' and `movb imm8, %ah' */
1165 /* `movb imm8, %cl' and `movb imm8, %ch' */
1166 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1167 /* `movb imm8, %dl' and `movb imm8, %dh' */
1168 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1169 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1170 { 5, { 0xb8 }, { 0xfe } },
1171 /* `movl imm32, %edx' */
1172 { 5, { 0xba }, { 0xff } },
1174 /* Check for `mov imm32, r32'. Note that there is an alternative
1175 encoding for `mov m32, %eax'.
1177 ??? Should we handle SIB adressing here?
1178 ??? Should we handle 16-bit operand-sizes here? */
1180 /* `movl m32, %eax' */
1181 { 5, { 0xa1 }, { 0xff } },
1182 /* `movl m32, %eax' and `mov; m32, %ecx' */
1183 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1184 /* `movl m32, %edx' */
1185 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1187 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1188 Because of the symmetry, there are actually two ways to encode
1189 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1190 opcode bytes 0x31 and 0x33 for `xorl'. */
1192 /* `subl %eax, %eax' */
1193 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1194 /* `subl %ecx, %ecx' */
1195 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1196 /* `subl %edx, %edx' */
1197 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1198 /* `xorl %eax, %eax' */
1199 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1200 /* `xorl %ecx, %ecx' */
1201 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1202 /* `xorl %edx, %edx' */
1203 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1208 /* Check whether PC points to a no-op instruction. */
1210 i386_skip_noop (CORE_ADDR pc)
1215 target_read_memory (pc, &op, 1);
1220 /* Ignore `nop' instruction. */
1224 target_read_memory (pc, &op, 1);
1227 /* Ignore no-op instruction `mov %edi, %edi'.
1228 Microsoft system dlls often start with
1229 a `mov %edi,%edi' instruction.
1230 The 5 bytes before the function start are
1231 filled with `nop' instructions.
1232 This pattern can be used for hot-patching:
1233 The `mov %edi, %edi' instruction can be replaced by a
1234 near jump to the location of the 5 `nop' instructions
1235 which can be replaced by a 32-bit jump to anywhere
1236 in the 32-bit address space. */
1238 else if (op == 0x8b)
1240 target_read_memory (pc + 1, &op, 1);
1244 target_read_memory (pc, &op, 1);
1252 /* Check whether PC points at a code that sets up a new stack frame.
1253 If so, it updates CACHE and returns the address of the first
1254 instruction after the sequence that sets up the frame or LIMIT,
1255 whichever is smaller. If we don't recognize the code, return PC. */
1258 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1259 CORE_ADDR pc, CORE_ADDR limit,
1260 struct i386_frame_cache *cache)
1262 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1263 struct i386_insn *insn;
1270 target_read_memory (pc, &op, 1);
1272 if (op == 0x55) /* pushl %ebp */
1274 /* Take into account that we've executed the `pushl %ebp' that
1275 starts this instruction sequence. */
1276 cache->saved_regs[I386_EBP_REGNUM] = 0;
1277 cache->sp_offset += 4;
1280 /* If that's all, return now. */
1284 /* Check for some special instructions that might be migrated by
1285 GCC into the prologue and skip them. At this point in the
1286 prologue, code should only touch the scratch registers %eax,
1287 %ecx and %edx, so while the number of posibilities is sheer,
1290 Make sure we only skip these instructions if we later see the
1291 `movl %esp, %ebp' that actually sets up the frame. */
1292 while (pc + skip < limit)
1294 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1301 /* If that's all, return now. */
1302 if (limit <= pc + skip)
1305 target_read_memory (pc + skip, &op, 1);
1307 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1311 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1316 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1324 /* OK, we actually have a frame. We just don't know how large
1325 it is yet. Set its size to zero. We'll adjust it if
1326 necessary. We also now commit to skipping the special
1327 instructions mentioned before. */
1331 /* If that's all, return now. */
1335 /* Check for stack adjustment
1339 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1340 reg, so we don't have to worry about a data16 prefix. */
1341 target_read_memory (pc, &op, 1);
1344 /* `subl' with 8-bit immediate. */
1345 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1346 /* Some instruction starting with 0x83 other than `subl'. */
1349 /* `subl' with signed 8-bit immediate (though it wouldn't
1350 make sense to be negative). */
1351 cache->locals = read_memory_integer (pc + 2, 1, byte_order);
1354 else if (op == 0x81)
1356 /* Maybe it is `subl' with a 32-bit immediate. */
1357 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1358 /* Some instruction starting with 0x81 other than `subl'. */
1361 /* It is `subl' with a 32-bit immediate. */
1362 cache->locals = read_memory_integer (pc + 2, 4, byte_order);
1367 /* Some instruction other than `subl'. */
1371 else if (op == 0xc8) /* enter */
1373 cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order);
1380 /* Check whether PC points at code that saves registers on the stack.
1381 If so, it updates CACHE and returns the address of the first
1382 instruction after the register saves or CURRENT_PC, whichever is
1383 smaller. Otherwise, return PC. */
1386 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1387 struct i386_frame_cache *cache)
1389 CORE_ADDR offset = 0;
1393 if (cache->locals > 0)
1394 offset -= cache->locals;
1395 for (i = 0; i < 8 && pc < current_pc; i++)
1397 target_read_memory (pc, &op, 1);
1398 if (op < 0x50 || op > 0x57)
1402 cache->saved_regs[op - 0x50] = offset;
1403 cache->sp_offset += 4;
1410 /* Do a full analysis of the prologue at PC and update CACHE
1411 accordingly. Bail out early if CURRENT_PC is reached. Return the
1412 address where the analysis stopped.
1414 We handle these cases:
1416 The startup sequence can be at the start of the function, or the
1417 function can start with a branch to startup code at the end.
1419 %ebp can be set up with either the 'enter' instruction, or "pushl
1420 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1421 once used in the System V compiler).
1423 Local space is allocated just below the saved %ebp by either the
1424 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1425 16-bit unsigned argument for space to allocate, and the 'addl'
1426 instruction could have either a signed byte, or 32-bit immediate.
1428 Next, the registers used by this function are pushed. With the
1429 System V compiler they will always be in the order: %edi, %esi,
1430 %ebx (and sometimes a harmless bug causes it to also save but not
1431 restore %eax); however, the code below is willing to see the pushes
1432 in any order, and will handle up to 8 of them.
1434 If the setup sequence is at the end of the function, then the next
1435 instruction will be a branch back to the start. */
1438 i386_analyze_prologue (struct gdbarch *gdbarch,
1439 CORE_ADDR pc, CORE_ADDR current_pc,
1440 struct i386_frame_cache *cache)
1442 pc = i386_skip_noop (pc);
1443 pc = i386_follow_jump (gdbarch, pc);
1444 pc = i386_analyze_struct_return (pc, current_pc, cache);
1445 pc = i386_skip_probe (pc);
1446 pc = i386_analyze_stack_align (pc, current_pc, cache);
1447 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1448 return i386_analyze_register_saves (pc, current_pc, cache);
1451 /* Return PC of first real instruction. */
1454 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1456 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1458 static gdb_byte pic_pat[6] =
1460 0xe8, 0, 0, 0, 0, /* call 0x0 */
1461 0x5b, /* popl %ebx */
1463 struct i386_frame_cache cache;
1469 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1470 if (cache.locals < 0)
1473 /* Found valid frame setup. */
1475 /* The native cc on SVR4 in -K PIC mode inserts the following code
1476 to get the address of the global offset table (GOT) into register
1481 movl %ebx,x(%ebp) (optional)
1484 This code is with the rest of the prologue (at the end of the
1485 function), so we have to skip it to get to the first real
1486 instruction at the start of the function. */
1488 for (i = 0; i < 6; i++)
1490 target_read_memory (pc + i, &op, 1);
1491 if (pic_pat[i] != op)
1498 target_read_memory (pc + delta, &op, 1);
1500 if (op == 0x89) /* movl %ebx, x(%ebp) */
1502 op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order);
1504 if (op == 0x5d) /* One byte offset from %ebp. */
1506 else if (op == 0x9d) /* Four byte offset from %ebp. */
1508 else /* Unexpected instruction. */
1511 target_read_memory (pc + delta, &op, 1);
1515 if (delta > 0 && op == 0x81
1516 && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order)
1523 /* If the function starts with a branch (to startup code at the end)
1524 the last instruction should bring us back to the first
1525 instruction of the real code. */
1526 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1527 pc = i386_follow_jump (gdbarch, pc);
1532 /* Check that the code pointed to by PC corresponds to a call to
1533 __main, skip it if so. Return PC otherwise. */
1536 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1538 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1541 target_read_memory (pc, &op, 1);
1546 if (target_read_memory (pc + 1, buf, sizeof buf) == 0)
1548 /* Make sure address is computed correctly as a 32bit
1549 integer even if CORE_ADDR is 64 bit wide. */
1550 struct minimal_symbol *s;
1551 CORE_ADDR call_dest;
1553 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1554 call_dest = call_dest & 0xffffffffU;
1555 s = lookup_minimal_symbol_by_pc (call_dest);
1557 && SYMBOL_LINKAGE_NAME (s) != NULL
1558 && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0)
1566 /* This function is 64-bit safe. */
1569 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1573 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1574 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1578 /* Normal frames. */
1580 static struct i386_frame_cache *
1581 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
1583 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1584 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1585 struct i386_frame_cache *cache;
1592 cache = i386_alloc_frame_cache ();
1593 *this_cache = cache;
1595 /* In principle, for normal frames, %ebp holds the frame pointer,
1596 which holds the base address for the current stack frame.
1597 However, for functions that don't need it, the frame pointer is
1598 optional. For these "frameless" functions the frame pointer is
1599 actually the frame pointer of the calling frame. Signal
1600 trampolines are just a special case of a "frameless" function.
1601 They (usually) share their frame pointer with the frame that was
1602 in progress when the signal occurred. */
1604 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1605 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1606 if (cache->base == 0)
1609 /* For normal frames, %eip is stored at 4(%ebp). */
1610 cache->saved_regs[I386_EIP_REGNUM] = 4;
1612 cache->pc = get_frame_func (this_frame);
1614 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
1617 if (cache->saved_sp_reg != -1)
1619 /* Saved stack pointer has been saved. */
1620 get_frame_register (this_frame, cache->saved_sp_reg, buf);
1621 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
1624 if (cache->locals < 0)
1626 /* We didn't find a valid frame, which means that CACHE->base
1627 currently holds the frame pointer for our calling frame. If
1628 we're at the start of a function, or somewhere half-way its
1629 prologue, the function's frame probably hasn't been fully
1630 setup yet. Try to reconstruct the base address for the stack
1631 frame by looking at the stack pointer. For truly "frameless"
1632 functions this might work too. */
1634 if (cache->saved_sp_reg != -1)
1636 /* We're halfway aligning the stack. */
1637 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
1638 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
1640 /* This will be added back below. */
1641 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
1643 else if (cache->pc != 0
1644 || target_read_memory (get_frame_pc (this_frame), buf, 1))
1646 /* We're in a known function, but did not find a frame
1647 setup. Assume that the function does not use %ebp.
1648 Alternatively, we may have jumped to an invalid
1649 address; in that case there is definitely no new
1651 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1652 cache->base = extract_unsigned_integer (buf, 4, byte_order)
1656 /* We're in an unknown function. We could not find the start
1657 of the function to analyze the prologue; our best option is
1658 to assume a typical frame layout with the caller's %ebp
1660 cache->saved_regs[I386_EBP_REGNUM] = 0;
1663 /* Now that we have the base address for the stack frame we can
1664 calculate the value of %esp in the calling frame. */
1665 if (cache->saved_sp == 0)
1666 cache->saved_sp = cache->base + 8;
1668 /* Adjust all the saved registers such that they contain addresses
1669 instead of offsets. */
1670 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1671 if (cache->saved_regs[i] != -1)
1672 cache->saved_regs[i] += cache->base;
1678 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
1679 struct frame_id *this_id)
1681 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1683 /* This marks the outermost frame. */
1684 if (cache->base == 0)
1687 /* See the end of i386_push_dummy_call. */
1688 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
1691 static struct value *
1692 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
1695 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1697 gdb_assert (regnum >= 0);
1699 /* The System V ABI says that:
1701 "The flags register contains the system flags, such as the
1702 direction flag and the carry flag. The direction flag must be
1703 set to the forward (that is, zero) direction before entry and
1704 upon exit from a function. Other user flags have no specified
1705 role in the standard calling sequence and are not preserved."
1707 To guarantee the "upon exit" part of that statement we fake a
1708 saved flags register that has its direction flag cleared.
1710 Note that GCC doesn't seem to rely on the fact that the direction
1711 flag is cleared after a function return; it always explicitly
1712 clears the flag before operations where it matters.
1714 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1715 right thing to do. The way we fake the flags register here makes
1716 it impossible to change it. */
1718 if (regnum == I386_EFLAGS_REGNUM)
1722 val = get_frame_register_unsigned (this_frame, regnum);
1724 return frame_unwind_got_constant (this_frame, regnum, val);
1727 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
1728 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
1730 if (regnum == I386_ESP_REGNUM && cache->saved_sp)
1731 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
1733 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
1734 return frame_unwind_got_memory (this_frame, regnum,
1735 cache->saved_regs[regnum]);
1737 return frame_unwind_got_register (this_frame, regnum, regnum);
1740 static const struct frame_unwind i386_frame_unwind =
1744 i386_frame_prev_register,
1746 default_frame_sniffer
1749 /* Normal frames, but in a function epilogue. */
1751 /* The epilogue is defined here as the 'ret' instruction, which will
1752 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1753 the function's stack frame. */
1756 i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1760 if (target_read_memory (pc, &insn, 1))
1761 return 0; /* Can't read memory at pc. */
1763 if (insn != 0xc3) /* 'ret' instruction. */
1770 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
1771 struct frame_info *this_frame,
1772 void **this_prologue_cache)
1774 if (frame_relative_level (this_frame) == 0)
1775 return i386_in_function_epilogue_p (get_frame_arch (this_frame),
1776 get_frame_pc (this_frame));
1781 static struct i386_frame_cache *
1782 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
1784 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1785 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1786 struct i386_frame_cache *cache;
1792 cache = i386_alloc_frame_cache ();
1793 *this_cache = cache;
1795 /* Cache base will be %esp plus cache->sp_offset (-4). */
1796 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1797 cache->base = extract_unsigned_integer (buf, 4,
1798 byte_order) + cache->sp_offset;
1800 /* Cache pc will be the frame func. */
1801 cache->pc = get_frame_pc (this_frame);
1803 /* The saved %esp will be at cache->base plus 8. */
1804 cache->saved_sp = cache->base + 8;
1806 /* The saved %eip will be at cache->base plus 4. */
1807 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
1813 i386_epilogue_frame_this_id (struct frame_info *this_frame,
1815 struct frame_id *this_id)
1817 struct i386_frame_cache *cache = i386_epilogue_frame_cache (this_frame,
1820 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
1823 static const struct frame_unwind i386_epilogue_frame_unwind =
1826 i386_epilogue_frame_this_id,
1827 i386_frame_prev_register,
1829 i386_epilogue_frame_sniffer
1833 /* Signal trampolines. */
1835 static struct i386_frame_cache *
1836 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
1838 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1839 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1840 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1841 struct i386_frame_cache *cache;
1848 cache = i386_alloc_frame_cache ();
1850 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1851 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
1853 addr = tdep->sigcontext_addr (this_frame);
1854 if (tdep->sc_reg_offset)
1858 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
1860 for (i = 0; i < tdep->sc_num_regs; i++)
1861 if (tdep->sc_reg_offset[i] != -1)
1862 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
1866 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
1867 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
1870 *this_cache = cache;
1875 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
1876 struct frame_id *this_id)
1878 struct i386_frame_cache *cache =
1879 i386_sigtramp_frame_cache (this_frame, this_cache);
1881 /* See the end of i386_push_dummy_call. */
1882 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
1885 static struct value *
1886 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
1887 void **this_cache, int regnum)
1889 /* Make sure we've initialized the cache. */
1890 i386_sigtramp_frame_cache (this_frame, this_cache);
1892 return i386_frame_prev_register (this_frame, this_cache, regnum);
1896 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
1897 struct frame_info *this_frame,
1898 void **this_prologue_cache)
1900 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
1902 /* We shouldn't even bother if we don't have a sigcontext_addr
1904 if (tdep->sigcontext_addr == NULL)
1907 if (tdep->sigtramp_p != NULL)
1909 if (tdep->sigtramp_p (this_frame))
1913 if (tdep->sigtramp_start != 0)
1915 CORE_ADDR pc = get_frame_pc (this_frame);
1917 gdb_assert (tdep->sigtramp_end != 0);
1918 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
1925 static const struct frame_unwind i386_sigtramp_frame_unwind =
1928 i386_sigtramp_frame_this_id,
1929 i386_sigtramp_frame_prev_register,
1931 i386_sigtramp_frame_sniffer
1936 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
1938 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1943 static const struct frame_base i386_frame_base =
1946 i386_frame_base_address,
1947 i386_frame_base_address,
1948 i386_frame_base_address
1951 static struct frame_id
1952 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1956 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
1958 /* See the end of i386_push_dummy_call. */
1959 return frame_id_build (fp + 8, get_frame_pc (this_frame));
1963 /* Figure out where the longjmp will land. Slurp the args out of the
1964 stack. We expect the first arg to be a pointer to the jmp_buf
1965 structure from which we extract the address that we will land at.
1966 This address is copied into PC. This routine returns non-zero on
1970 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1973 CORE_ADDR sp, jb_addr;
1974 struct gdbarch *gdbarch = get_frame_arch (frame);
1975 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1976 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
1978 /* If JB_PC_OFFSET is -1, we have no way to find out where the
1979 longjmp will land. */
1980 if (jb_pc_offset == -1)
1983 get_frame_register (frame, I386_ESP_REGNUM, buf);
1984 sp = extract_unsigned_integer (buf, 4, byte_order);
1985 if (target_read_memory (sp + 4, buf, 4))
1988 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
1989 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
1992 *pc = extract_unsigned_integer (buf, 4, byte_order);
1997 /* Check whether TYPE must be 16-byte-aligned when passed as a
1998 function argument. 16-byte vectors, _Decimal128 and structures or
1999 unions containing such types must be 16-byte-aligned; other
2000 arguments are 4-byte-aligned. */
2003 i386_16_byte_align_p (struct type *type)
2005 type = check_typedef (type);
2006 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
2007 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
2008 && TYPE_LENGTH (type) == 16)
2010 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2011 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
2012 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2013 || TYPE_CODE (type) == TYPE_CODE_UNION)
2016 for (i = 0; i < TYPE_NFIELDS (type); i++)
2018 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
2026 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2027 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2028 struct value **args, CORE_ADDR sp, int struct_return,
2029 CORE_ADDR struct_addr)
2031 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2037 /* Determine the total space required for arguments and struct
2038 return address in a first pass (allowing for 16-byte-aligned
2039 arguments), then push arguments in a second pass. */
2041 for (write_pass = 0; write_pass < 2; write_pass++)
2043 int args_space_used = 0;
2044 int have_16_byte_aligned_arg = 0;
2050 /* Push value address. */
2051 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2052 write_memory (sp, buf, 4);
2053 args_space_used += 4;
2059 for (i = 0; i < nargs; i++)
2061 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2065 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2066 args_space_used = align_up (args_space_used, 16);
2068 write_memory (sp + args_space_used,
2069 value_contents_all (args[i]), len);
2070 /* The System V ABI says that:
2072 "An argument's size is increased, if necessary, to make it a
2073 multiple of [32-bit] words. This may require tail padding,
2074 depending on the size of the argument."
2076 This makes sure the stack stays word-aligned. */
2077 args_space_used += align_up (len, 4);
2081 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2083 args_space = align_up (args_space, 16);
2084 have_16_byte_aligned_arg = 1;
2086 args_space += align_up (len, 4);
2092 if (have_16_byte_aligned_arg)
2093 args_space = align_up (args_space, 16);
2098 /* Store return address. */
2100 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2101 write_memory (sp, buf, 4);
2103 /* Finally, update the stack pointer... */
2104 store_unsigned_integer (buf, 4, byte_order, sp);
2105 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
2107 /* ...and fake a frame pointer. */
2108 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
2110 /* MarkK wrote: This "+ 8" is all over the place:
2111 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2112 i386_dummy_id). It's there, since all frame unwinders for
2113 a given target have to agree (within a certain margin) on the
2114 definition of the stack address of a frame. Otherwise frame id
2115 comparison might not work correctly. Since DWARF2/GCC uses the
2116 stack address *before* the function call as a frame's CFA. On
2117 the i386, when %ebp is used as a frame pointer, the offset
2118 between the contents %ebp and the CFA as defined by GCC. */
2122 /* These registers are used for returning integers (and on some
2123 targets also for returning `struct' and `union' values when their
2124 size and alignment match an integer type). */
2125 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2126 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2128 /* Read, for architecture GDBARCH, a function return value of TYPE
2129 from REGCACHE, and copy that into VALBUF. */
2132 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2133 struct regcache *regcache, gdb_byte *valbuf)
2135 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2136 int len = TYPE_LENGTH (type);
2137 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2139 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2141 if (tdep->st0_regnum < 0)
2143 warning (_("Cannot find floating-point return value."));
2144 memset (valbuf, 0, len);
2148 /* Floating-point return values can be found in %st(0). Convert
2149 its contents to the desired type. This is probably not
2150 exactly how it would happen on the target itself, but it is
2151 the best we can do. */
2152 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2153 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
2157 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2158 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2160 if (len <= low_size)
2162 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2163 memcpy (valbuf, buf, len);
2165 else if (len <= (low_size + high_size))
2167 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2168 memcpy (valbuf, buf, low_size);
2169 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2170 memcpy (valbuf + low_size, buf, len - low_size);
2173 internal_error (__FILE__, __LINE__,
2174 _("Cannot extract return value of %d bytes long."), len);
2178 /* Write, for architecture GDBARCH, a function return value of TYPE
2179 from VALBUF into REGCACHE. */
2182 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2183 struct regcache *regcache, const gdb_byte *valbuf)
2185 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2186 int len = TYPE_LENGTH (type);
2188 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2191 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2193 if (tdep->st0_regnum < 0)
2195 warning (_("Cannot set floating-point return value."));
2199 /* Returning floating-point values is a bit tricky. Apart from
2200 storing the return value in %st(0), we have to simulate the
2201 state of the FPU at function return point. */
2203 /* Convert the value found in VALBUF to the extended
2204 floating-point format used by the FPU. This is probably
2205 not exactly how it would happen on the target itself, but
2206 it is the best we can do. */
2207 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
2208 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2210 /* Set the top of the floating-point register stack to 7. The
2211 actual value doesn't really matter, but 7 is what a normal
2212 function return would end up with if the program started out
2213 with a freshly initialized FPU. */
2214 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2216 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2218 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2219 the floating-point register stack to 7, the appropriate value
2220 for the tag word is 0x3fff. */
2221 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2225 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2226 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2228 if (len <= low_size)
2229 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2230 else if (len <= (low_size + high_size))
2232 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2233 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
2234 len - low_size, valbuf + low_size);
2237 internal_error (__FILE__, __LINE__,
2238 _("Cannot store return value of %d bytes long."), len);
2243 /* This is the variable that is set with "set struct-convention", and
2244 its legitimate values. */
2245 static const char default_struct_convention[] = "default";
2246 static const char pcc_struct_convention[] = "pcc";
2247 static const char reg_struct_convention[] = "reg";
2248 static const char *valid_conventions[] =
2250 default_struct_convention,
2251 pcc_struct_convention,
2252 reg_struct_convention,
2255 static const char *struct_convention = default_struct_convention;
2257 /* Return non-zero if TYPE, which is assumed to be a structure,
2258 a union type, or an array type, should be returned in registers
2259 for architecture GDBARCH. */
2262 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2264 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2265 enum type_code code = TYPE_CODE (type);
2266 int len = TYPE_LENGTH (type);
2268 gdb_assert (code == TYPE_CODE_STRUCT
2269 || code == TYPE_CODE_UNION
2270 || code == TYPE_CODE_ARRAY);
2272 if (struct_convention == pcc_struct_convention
2273 || (struct_convention == default_struct_convention
2274 && tdep->struct_return == pcc_struct_return))
2277 /* Structures consisting of a single `float', `double' or 'long
2278 double' member are returned in %st(0). */
2279 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2281 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2282 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2283 return (len == 4 || len == 8 || len == 12);
2286 return (len == 1 || len == 2 || len == 4 || len == 8);
2289 /* Determine, for architecture GDBARCH, how a return value of TYPE
2290 should be returned. If it is supposed to be returned in registers,
2291 and READBUF is non-zero, read the appropriate value from REGCACHE,
2292 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2293 from WRITEBUF into REGCACHE. */
2295 static enum return_value_convention
2296 i386_return_value (struct gdbarch *gdbarch, struct type *func_type,
2297 struct type *type, struct regcache *regcache,
2298 gdb_byte *readbuf, const gdb_byte *writebuf)
2300 enum type_code code = TYPE_CODE (type);
2302 if (((code == TYPE_CODE_STRUCT
2303 || code == TYPE_CODE_UNION
2304 || code == TYPE_CODE_ARRAY)
2305 && !i386_reg_struct_return_p (gdbarch, type))
2306 /* 128-bit decimal float uses the struct return convention. */
2307 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2309 /* The System V ABI says that:
2311 "A function that returns a structure or union also sets %eax
2312 to the value of the original address of the caller's area
2313 before it returns. Thus when the caller receives control
2314 again, the address of the returned object resides in register
2315 %eax and can be used to access the object."
2317 So the ABI guarantees that we can always find the return
2318 value just after the function has returned. */
2320 /* Note that the ABI doesn't mention functions returning arrays,
2321 which is something possible in certain languages such as Ada.
2322 In this case, the value is returned as if it was wrapped in
2323 a record, so the convention applied to records also applies
2330 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2331 read_memory (addr, readbuf, TYPE_LENGTH (type));
2334 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2337 /* This special case is for structures consisting of a single
2338 `float', `double' or 'long double' member. These structures are
2339 returned in %st(0). For these structures, we call ourselves
2340 recursively, changing TYPE into the type of the first member of
2341 the structure. Since that should work for all structures that
2342 have only one member, we don't bother to check the member's type
2344 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2346 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2347 return i386_return_value (gdbarch, func_type, type, regcache,
2352 i386_extract_return_value (gdbarch, type, regcache, readbuf);
2354 i386_store_return_value (gdbarch, type, regcache, writebuf);
2356 return RETURN_VALUE_REGISTER_CONVENTION;
2361 i387_ext_type (struct gdbarch *gdbarch)
2363 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2365 if (!tdep->i387_ext_type)
2367 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
2368 gdb_assert (tdep->i387_ext_type != NULL);
2371 return tdep->i387_ext_type;
2374 /* Construct vector type for pseudo YMM registers. We can't use
2375 tdesc_find_type since YMM isn't described in target description. */
2377 static struct type *
2378 i386_ymm_type (struct gdbarch *gdbarch)
2380 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2382 if (!tdep->i386_ymm_type)
2384 const struct builtin_type *bt = builtin_type (gdbarch);
2386 /* The type we're building is this: */
2388 union __gdb_builtin_type_vec256i
2390 int128_t uint128[2];
2391 int64_t v2_int64[4];
2392 int32_t v4_int32[8];
2393 int16_t v8_int16[16];
2394 int8_t v16_int8[32];
2395 double v2_double[4];
2402 t = arch_composite_type (gdbarch,
2403 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
2404 append_composite_type_field (t, "v8_float",
2405 init_vector_type (bt->builtin_float, 8));
2406 append_composite_type_field (t, "v4_double",
2407 init_vector_type (bt->builtin_double, 4));
2408 append_composite_type_field (t, "v32_int8",
2409 init_vector_type (bt->builtin_int8, 32));
2410 append_composite_type_field (t, "v16_int16",
2411 init_vector_type (bt->builtin_int16, 16));
2412 append_composite_type_field (t, "v8_int32",
2413 init_vector_type (bt->builtin_int32, 8));
2414 append_composite_type_field (t, "v4_int64",
2415 init_vector_type (bt->builtin_int64, 4));
2416 append_composite_type_field (t, "v2_int128",
2417 init_vector_type (bt->builtin_int128, 2));
2419 TYPE_VECTOR (t) = 1;
2420 TYPE_NAME (t) = "builtin_type_vec128i";
2421 tdep->i386_ymm_type = t;
2424 return tdep->i386_ymm_type;
2427 /* Construct vector type for MMX registers. */
2428 static struct type *
2429 i386_mmx_type (struct gdbarch *gdbarch)
2431 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2433 if (!tdep->i386_mmx_type)
2435 const struct builtin_type *bt = builtin_type (gdbarch);
2437 /* The type we're building is this: */
2439 union __gdb_builtin_type_vec64i
2442 int32_t v2_int32[2];
2443 int16_t v4_int16[4];
2450 t = arch_composite_type (gdbarch,
2451 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
2453 append_composite_type_field (t, "uint64", bt->builtin_int64);
2454 append_composite_type_field (t, "v2_int32",
2455 init_vector_type (bt->builtin_int32, 2));
2456 append_composite_type_field (t, "v4_int16",
2457 init_vector_type (bt->builtin_int16, 4));
2458 append_composite_type_field (t, "v8_int8",
2459 init_vector_type (bt->builtin_int8, 8));
2461 TYPE_VECTOR (t) = 1;
2462 TYPE_NAME (t) = "builtin_type_vec64i";
2463 tdep->i386_mmx_type = t;
2466 return tdep->i386_mmx_type;
2469 /* Return the GDB type object for the "standard" data type of data in
2472 static struct type *
2473 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2475 if (i386_mmx_regnum_p (gdbarch, regnum))
2476 return i386_mmx_type (gdbarch);
2477 else if (i386_ymm_regnum_p (gdbarch, regnum))
2478 return i386_ymm_type (gdbarch);
2481 const struct builtin_type *bt = builtin_type (gdbarch);
2482 if (i386_byte_regnum_p (gdbarch, regnum))
2483 return bt->builtin_int8;
2484 else if (i386_word_regnum_p (gdbarch, regnum))
2485 return bt->builtin_int16;
2486 else if (i386_dword_regnum_p (gdbarch, regnum))
2487 return bt->builtin_int32;
2490 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2493 /* Map a cooked register onto a raw register or memory. For the i386,
2494 the MMX registers need to be mapped onto floating point registers. */
2497 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
2499 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
2504 mmxreg = regnum - tdep->mm0_regnum;
2505 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2506 tos = (fstat >> 11) & 0x7;
2507 fpreg = (mmxreg + tos) % 8;
2509 return (I387_ST0_REGNUM (tdep) + fpreg);
2513 i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2514 int regnum, gdb_byte *buf)
2516 gdb_byte raw_buf[MAX_REGISTER_SIZE];
2518 if (i386_mmx_regnum_p (gdbarch, regnum))
2520 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2522 /* Extract (always little endian). */
2523 regcache_raw_read (regcache, fpnum, raw_buf);
2524 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
2528 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2530 if (i386_ymm_regnum_p (gdbarch, regnum))
2532 regnum -= tdep->ymm0_regnum;
2534 /* Extract (always little endian). Read lower 128bits. */
2535 regcache_raw_read (regcache,
2536 I387_XMM0_REGNUM (tdep) + regnum,
2538 memcpy (buf, raw_buf, 16);
2539 /* Read upper 128bits. */
2540 regcache_raw_read (regcache,
2541 tdep->ymm0h_regnum + regnum,
2543 memcpy (buf + 16, raw_buf, 16);
2545 else if (i386_word_regnum_p (gdbarch, regnum))
2547 int gpnum = regnum - tdep->ax_regnum;
2549 /* Extract (always little endian). */
2550 regcache_raw_read (regcache, gpnum, raw_buf);
2551 memcpy (buf, raw_buf, 2);
2553 else if (i386_byte_regnum_p (gdbarch, regnum))
2555 /* Check byte pseudo registers last since this function will
2556 be called from amd64_pseudo_register_read, which handles
2557 byte pseudo registers differently. */
2558 int gpnum = regnum - tdep->al_regnum;
2560 /* Extract (always little endian). We read both lower and
2562 regcache_raw_read (regcache, gpnum % 4, raw_buf);
2564 memcpy (buf, raw_buf + 1, 1);
2566 memcpy (buf, raw_buf, 1);
2569 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2574 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2575 int regnum, const gdb_byte *buf)
2577 gdb_byte raw_buf[MAX_REGISTER_SIZE];
2579 if (i386_mmx_regnum_p (gdbarch, regnum))
2581 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2584 regcache_raw_read (regcache, fpnum, raw_buf);
2585 /* ... Modify ... (always little endian). */
2586 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
2588 regcache_raw_write (regcache, fpnum, raw_buf);
2592 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2594 if (i386_ymm_regnum_p (gdbarch, regnum))
2596 regnum -= tdep->ymm0_regnum;
2598 /* ... Write lower 128bits. */
2599 regcache_raw_write (regcache,
2600 I387_XMM0_REGNUM (tdep) + regnum,
2602 /* ... Write upper 128bits. */
2603 regcache_raw_write (regcache,
2604 tdep->ymm0h_regnum + regnum,
2607 else if (i386_word_regnum_p (gdbarch, regnum))
2609 int gpnum = regnum - tdep->ax_regnum;
2612 regcache_raw_read (regcache, gpnum, raw_buf);
2613 /* ... Modify ... (always little endian). */
2614 memcpy (raw_buf, buf, 2);
2616 regcache_raw_write (regcache, gpnum, raw_buf);
2618 else if (i386_byte_regnum_p (gdbarch, regnum))
2620 /* Check byte pseudo registers last since this function will
2621 be called from amd64_pseudo_register_read, which handles
2622 byte pseudo registers differently. */
2623 int gpnum = regnum - tdep->al_regnum;
2625 /* Read ... We read both lower and upper registers. */
2626 regcache_raw_read (regcache, gpnum % 4, raw_buf);
2627 /* ... Modify ... (always little endian). */
2629 memcpy (raw_buf + 1, buf, 1);
2631 memcpy (raw_buf, buf, 1);
2633 regcache_raw_write (regcache, gpnum % 4, raw_buf);
2636 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2641 /* Return the register number of the register allocated by GCC after
2642 REGNUM, or -1 if there is no such register. */
2645 i386_next_regnum (int regnum)
2647 /* GCC allocates the registers in the order:
2649 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2651 Since storing a variable in %esp doesn't make any sense we return
2652 -1 for %ebp and for %esp itself. */
2653 static int next_regnum[] =
2655 I386_EDX_REGNUM, /* Slot for %eax. */
2656 I386_EBX_REGNUM, /* Slot for %ecx. */
2657 I386_ECX_REGNUM, /* Slot for %edx. */
2658 I386_ESI_REGNUM, /* Slot for %ebx. */
2659 -1, -1, /* Slots for %esp and %ebp. */
2660 I386_EDI_REGNUM, /* Slot for %esi. */
2661 I386_EBP_REGNUM /* Slot for %edi. */
2664 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
2665 return next_regnum[regnum];
2670 /* Return nonzero if a value of type TYPE stored in register REGNUM
2671 needs any special handling. */
2674 i386_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type)
2676 int len = TYPE_LENGTH (type);
2678 /* Values may be spread across multiple registers. Most debugging
2679 formats aren't expressive enough to specify the locations, so
2680 some heuristics is involved. Right now we only handle types that
2681 have a length that is a multiple of the word size, since GCC
2682 doesn't seem to put any other types into registers. */
2683 if (len > 4 && len % 4 == 0)
2685 int last_regnum = regnum;
2689 last_regnum = i386_next_regnum (last_regnum);
2693 if (last_regnum != -1)
2697 return i387_convert_register_p (gdbarch, regnum, type);
2700 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2701 return its contents in TO. */
2704 i386_register_to_value (struct frame_info *frame, int regnum,
2705 struct type *type, gdb_byte *to)
2707 struct gdbarch *gdbarch = get_frame_arch (frame);
2708 int len = TYPE_LENGTH (type);
2710 /* FIXME: kettenis/20030609: What should we do if REGNUM isn't
2711 available in FRAME (i.e. if it wasn't saved)? */
2713 if (i386_fp_regnum_p (gdbarch, regnum))
2715 i387_register_to_value (frame, regnum, type, to);
2719 /* Read a value spread across multiple registers. */
2721 gdb_assert (len > 4 && len % 4 == 0);
2725 gdb_assert (regnum != -1);
2726 gdb_assert (register_size (gdbarch, regnum) == 4);
2728 get_frame_register (frame, regnum, to);
2729 regnum = i386_next_regnum (regnum);
2735 /* Write the contents FROM of a value of type TYPE into register
2736 REGNUM in frame FRAME. */
2739 i386_value_to_register (struct frame_info *frame, int regnum,
2740 struct type *type, const gdb_byte *from)
2742 int len = TYPE_LENGTH (type);
2744 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
2746 i387_value_to_register (frame, regnum, type, from);
2750 /* Write a value spread across multiple registers. */
2752 gdb_assert (len > 4 && len % 4 == 0);
2756 gdb_assert (regnum != -1);
2757 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
2759 put_frame_register (frame, regnum, from);
2760 regnum = i386_next_regnum (regnum);
2766 /* Supply register REGNUM from the buffer specified by GREGS and LEN
2767 in the general-purpose register set REGSET to register cache
2768 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2771 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
2772 int regnum, const void *gregs, size_t len)
2774 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2775 const gdb_byte *regs = gregs;
2778 gdb_assert (len == tdep->sizeof_gregset);
2780 for (i = 0; i < tdep->gregset_num_regs; i++)
2782 if ((regnum == i || regnum == -1)
2783 && tdep->gregset_reg_offset[i] != -1)
2784 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
2788 /* Collect register REGNUM from the register cache REGCACHE and store
2789 it in the buffer specified by GREGS and LEN as described by the
2790 general-purpose register set REGSET. If REGNUM is -1, do this for
2791 all registers in REGSET. */
2794 i386_collect_gregset (const struct regset *regset,
2795 const struct regcache *regcache,
2796 int regnum, void *gregs, size_t len)
2798 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2799 gdb_byte *regs = gregs;
2802 gdb_assert (len == tdep->sizeof_gregset);
2804 for (i = 0; i < tdep->gregset_num_regs; i++)
2806 if ((regnum == i || regnum == -1)
2807 && tdep->gregset_reg_offset[i] != -1)
2808 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
2812 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2813 in the floating-point register set REGSET to register cache
2814 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2817 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
2818 int regnum, const void *fpregs, size_t len)
2820 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2822 if (len == I387_SIZEOF_FXSAVE)
2824 i387_supply_fxsave (regcache, regnum, fpregs);
2828 gdb_assert (len == tdep->sizeof_fpregset);
2829 i387_supply_fsave (regcache, regnum, fpregs);
2832 /* Collect register REGNUM from the register cache REGCACHE and store
2833 it in the buffer specified by FPREGS and LEN as described by the
2834 floating-point register set REGSET. If REGNUM is -1, do this for
2835 all registers in REGSET. */
2838 i386_collect_fpregset (const struct regset *regset,
2839 const struct regcache *regcache,
2840 int regnum, void *fpregs, size_t len)
2842 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2844 if (len == I387_SIZEOF_FXSAVE)
2846 i387_collect_fxsave (regcache, regnum, fpregs);
2850 gdb_assert (len == tdep->sizeof_fpregset);
2851 i387_collect_fsave (regcache, regnum, fpregs);
2854 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
2857 i386_supply_xstateregset (const struct regset *regset,
2858 struct regcache *regcache, int regnum,
2859 const void *xstateregs, size_t len)
2861 i387_supply_xsave (regcache, regnum, xstateregs);
2864 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
2867 i386_collect_xstateregset (const struct regset *regset,
2868 const struct regcache *regcache,
2869 int regnum, void *xstateregs, size_t len)
2871 i387_collect_xsave (regcache, regnum, xstateregs, 1);
2874 /* Return the appropriate register set for the core section identified
2875 by SECT_NAME and SECT_SIZE. */
2877 const struct regset *
2878 i386_regset_from_core_section (struct gdbarch *gdbarch,
2879 const char *sect_name, size_t sect_size)
2881 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2883 if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset)
2885 if (tdep->gregset == NULL)
2886 tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset,
2887 i386_collect_gregset);
2888 return tdep->gregset;
2891 if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
2892 || (strcmp (sect_name, ".reg-xfp") == 0
2893 && sect_size == I387_SIZEOF_FXSAVE))
2895 if (tdep->fpregset == NULL)
2896 tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset,
2897 i386_collect_fpregset);
2898 return tdep->fpregset;
2901 if (strcmp (sect_name, ".reg-xstate") == 0)
2903 if (tdep->xstateregset == NULL)
2904 tdep->xstateregset = regset_alloc (gdbarch,
2905 i386_supply_xstateregset,
2906 i386_collect_xstateregset);
2908 return tdep->xstateregset;
2915 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
2918 i386_pe_skip_trampoline_code (struct frame_info *frame,
2919 CORE_ADDR pc, char *name)
2921 struct gdbarch *gdbarch = get_frame_arch (frame);
2922 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2925 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
2927 unsigned long indirect =
2928 read_memory_unsigned_integer (pc + 2, 4, byte_order);
2929 struct minimal_symbol *indsym =
2930 indirect ? lookup_minimal_symbol_by_pc (indirect) : 0;
2931 char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0;
2935 if (strncmp (symname, "__imp_", 6) == 0
2936 || strncmp (symname, "_imp_", 5) == 0)
2938 read_memory_unsigned_integer (indirect, 4, byte_order);
2941 return 0; /* Not a trampoline. */
2945 /* Return whether the THIS_FRAME corresponds to a sigtramp
2949 i386_sigtramp_p (struct frame_info *this_frame)
2951 CORE_ADDR pc = get_frame_pc (this_frame);
2954 find_pc_partial_function (pc, &name, NULL, NULL);
2955 return (name && strcmp ("_sigtramp", name) == 0);
2959 /* We have two flavours of disassembly. The machinery on this page
2960 deals with switching between those. */
2963 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
2965 gdb_assert (disassembly_flavor == att_flavor
2966 || disassembly_flavor == intel_flavor);
2968 /* FIXME: kettenis/20020915: Until disassembler_options is properly
2969 constified, cast to prevent a compiler warning. */
2970 info->disassembler_options = (char *) disassembly_flavor;
2972 return print_insn_i386 (pc, info);
2976 /* There are a few i386 architecture variants that differ only
2977 slightly from the generic i386 target. For now, we don't give them
2978 their own source file, but include them here. As a consequence,
2979 they'll always be included. */
2981 /* System V Release 4 (SVR4). */
2983 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
2987 i386_svr4_sigtramp_p (struct frame_info *this_frame)
2989 CORE_ADDR pc = get_frame_pc (this_frame);
2992 /* UnixWare uses _sigacthandler. The origin of the other symbols is
2993 currently unknown. */
2994 find_pc_partial_function (pc, &name, NULL, NULL);
2995 return (name && (strcmp ("_sigreturn", name) == 0
2996 || strcmp ("_sigacthandler", name) == 0
2997 || strcmp ("sigvechandler", name) == 0));
3000 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3001 address of the associated sigcontext (ucontext) structure. */
3004 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
3006 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3007 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3011 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
3012 sp = extract_unsigned_integer (buf, 4, byte_order);
3014 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
3021 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3023 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3024 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3027 /* System V Release 4 (SVR4). */
3030 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3032 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3034 /* System V Release 4 uses ELF. */
3035 i386_elf_init_abi (info, gdbarch);
3037 /* System V Release 4 has shared libraries. */
3038 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
3040 tdep->sigtramp_p = i386_svr4_sigtramp_p;
3041 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
3042 tdep->sc_pc_offset = 36 + 14 * 4;
3043 tdep->sc_sp_offset = 36 + 17 * 4;
3045 tdep->jb_pc_offset = 20;
3051 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3053 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3055 /* DJGPP doesn't have any special frames for signal handlers. */
3056 tdep->sigtramp_p = NULL;
3058 tdep->jb_pc_offset = 36;
3060 /* DJGPP does not support the SSE registers. */
3061 if (! tdesc_has_registers (info.target_desc))
3062 tdep->tdesc = tdesc_i386_mmx;
3064 /* Native compiler is GCC, which uses the SVR4 register numbering
3065 even in COFF and STABS. See the comment in i386_gdbarch_init,
3066 before the calls to set_gdbarch_stab_reg_to_regnum and
3067 set_gdbarch_sdb_reg_to_regnum. */
3068 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3069 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3071 set_gdbarch_has_dos_based_file_system (gdbarch, 1);
3075 /* i386 register groups. In addition to the normal groups, add "mmx"
3078 static struct reggroup *i386_sse_reggroup;
3079 static struct reggroup *i386_mmx_reggroup;
3082 i386_init_reggroups (void)
3084 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
3085 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
3089 i386_add_reggroups (struct gdbarch *gdbarch)
3091 reggroup_add (gdbarch, i386_sse_reggroup);
3092 reggroup_add (gdbarch, i386_mmx_reggroup);
3093 reggroup_add (gdbarch, general_reggroup);
3094 reggroup_add (gdbarch, float_reggroup);
3095 reggroup_add (gdbarch, all_reggroup);
3096 reggroup_add (gdbarch, save_reggroup);
3097 reggroup_add (gdbarch, restore_reggroup);
3098 reggroup_add (gdbarch, vector_reggroup);
3099 reggroup_add (gdbarch, system_reggroup);
3103 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
3104 struct reggroup *group)
3106 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3107 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
3108 ymm_regnum_p, ymmh_regnum_p;
3110 /* Don't include pseudo registers, except for MMX, in any register
3112 if (i386_byte_regnum_p (gdbarch, regnum))
3115 if (i386_word_regnum_p (gdbarch, regnum))
3118 if (i386_dword_regnum_p (gdbarch, regnum))
3121 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
3122 if (group == i386_mmx_reggroup)
3123 return mmx_regnum_p;
3125 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
3126 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
3127 if (group == i386_sse_reggroup)
3128 return xmm_regnum_p || mxcsr_regnum_p;
3130 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
3131 if (group == vector_reggroup)
3132 return (mmx_regnum_p
3136 && ((tdep->xcr0 & I386_XSTATE_AVX_MASK)
3137 == I386_XSTATE_SSE_MASK)));
3139 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
3140 || i386_fpc_regnum_p (gdbarch, regnum));
3141 if (group == float_reggroup)
3144 /* For "info reg all", don't include upper YMM registers nor XMM
3145 registers when AVX is supported. */
3146 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
3147 if (group == all_reggroup
3149 && (tdep->xcr0 & I386_XSTATE_AVX))
3153 if (group == general_reggroup)
3154 return (!fp_regnum_p
3161 return default_register_reggroup_p (gdbarch, regnum, group);
3165 /* Get the ARGIth function argument for the current function. */
3168 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
3171 struct gdbarch *gdbarch = get_frame_arch (frame);
3172 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3173 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
3174 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
3178 i386_skip_permanent_breakpoint (struct regcache *regcache)
3180 CORE_ADDR current_pc = regcache_read_pc (regcache);
3182 /* On i386, breakpoint is exactly 1 byte long, so we just
3183 adjust the PC in the regcache. */
3185 regcache_write_pc (regcache, current_pc);
3189 #define PREFIX_REPZ 0x01
3190 #define PREFIX_REPNZ 0x02
3191 #define PREFIX_LOCK 0x04
3192 #define PREFIX_DATA 0x08
3193 #define PREFIX_ADDR 0x10
3205 /* i386 arith/logic operations */
3218 struct i386_record_s
3220 struct gdbarch *gdbarch;
3221 struct regcache *regcache;
3222 CORE_ADDR orig_addr;
3228 uint8_t mod, reg, rm;
3237 /* Parse "modrm" part in current memory address that irp->addr point to
3238 Return -1 if something wrong. */
3241 i386_record_modrm (struct i386_record_s *irp)
3243 struct gdbarch *gdbarch = irp->gdbarch;
3245 if (target_read_memory (irp->addr, &irp->modrm, 1))
3248 printf_unfiltered (_("Process record: error reading memory at "
3249 "addr %s len = 1.\n"),
3250 paddress (gdbarch, irp->addr));
3254 irp->mod = (irp->modrm >> 6) & 3;
3255 irp->reg = (irp->modrm >> 3) & 7;
3256 irp->rm = irp->modrm & 7;
3261 /* Get the memory address that current instruction write to and set it to
3262 the argument "addr".
3263 Return -1 if something wrong. */
3266 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
3268 struct gdbarch *gdbarch = irp->gdbarch;
3269 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3281 uint8_t base = irp->rm;
3286 if (target_read_memory (irp->addr, &byte, 1))
3289 printf_unfiltered (_("Process record: error reading memory "
3290 "at addr %s len = 1.\n"),
3291 paddress (gdbarch, irp->addr));
3295 scale = (byte >> 6) & 3;
3296 index = ((byte >> 3) & 7) | irp->rex_x;
3304 if ((base & 7) == 5)
3307 if (target_read_memory (irp->addr, buf, 4))
3310 printf_unfiltered (_("Process record: error reading "
3311 "memory at addr %s len = 4.\n"),
3312 paddress (gdbarch, irp->addr));
3316 *addr = extract_signed_integer (buf, 4, byte_order);
3317 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
3318 *addr += irp->addr + irp->rip_offset;
3322 if (target_read_memory (irp->addr, buf, 1))
3325 printf_unfiltered (_("Process record: error reading memory "
3326 "at addr %s len = 1.\n"),
3327 paddress (gdbarch, irp->addr));
3331 *addr = (int8_t) buf[0];
3334 if (target_read_memory (irp->addr, buf, 4))
3337 printf_unfiltered (_("Process record: error reading memory "
3338 "at addr %s len = 4.\n"),
3339 paddress (gdbarch, irp->addr));
3342 *addr = extract_signed_integer (buf, 4, byte_order);
3350 if (base == 4 && irp->popl_esp_hack)
3351 *addr += irp->popl_esp_hack;
3352 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
3355 if (irp->aflag == 2)
3360 *addr = (uint32_t) (offset64 + *addr);
3362 if (havesib && (index != 4 || scale != 0))
3364 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
3366 if (irp->aflag == 2)
3367 *addr += offset64 << scale;
3369 *addr = (uint32_t) (*addr + (offset64 << scale));
3380 if (target_read_memory (irp->addr, buf, 2))
3383 printf_unfiltered (_("Process record: error reading "
3384 "memory at addr %s len = 2.\n"),
3385 paddress (gdbarch, irp->addr));
3389 *addr = extract_signed_integer (buf, 2, byte_order);
3395 if (target_read_memory (irp->addr, buf, 1))
3398 printf_unfiltered (_("Process record: error reading memory "
3399 "at addr %s len = 1.\n"),
3400 paddress (gdbarch, irp->addr));
3404 *addr = (int8_t) buf[0];
3407 if (target_read_memory (irp->addr, buf, 2))
3410 printf_unfiltered (_("Process record: error reading memory "
3411 "at addr %s len = 2.\n"),
3412 paddress (gdbarch, irp->addr));
3416 *addr = extract_signed_integer (buf, 2, byte_order);
3423 regcache_raw_read_unsigned (irp->regcache,
3424 irp->regmap[X86_RECORD_REBX_REGNUM],
3426 *addr = (uint32_t) (*addr + offset64);
3427 regcache_raw_read_unsigned (irp->regcache,
3428 irp->regmap[X86_RECORD_RESI_REGNUM],
3430 *addr = (uint32_t) (*addr + offset64);
3433 regcache_raw_read_unsigned (irp->regcache,
3434 irp->regmap[X86_RECORD_REBX_REGNUM],
3436 *addr = (uint32_t) (*addr + offset64);
3437 regcache_raw_read_unsigned (irp->regcache,
3438 irp->regmap[X86_RECORD_REDI_REGNUM],
3440 *addr = (uint32_t) (*addr + offset64);
3443 regcache_raw_read_unsigned (irp->regcache,
3444 irp->regmap[X86_RECORD_REBP_REGNUM],
3446 *addr = (uint32_t) (*addr + offset64);
3447 regcache_raw_read_unsigned (irp->regcache,
3448 irp->regmap[X86_RECORD_RESI_REGNUM],
3450 *addr = (uint32_t) (*addr + offset64);
3453 regcache_raw_read_unsigned (irp->regcache,
3454 irp->regmap[X86_RECORD_REBP_REGNUM],
3456 *addr = (uint32_t) (*addr + offset64);
3457 regcache_raw_read_unsigned (irp->regcache,
3458 irp->regmap[X86_RECORD_REDI_REGNUM],
3460 *addr = (uint32_t) (*addr + offset64);
3463 regcache_raw_read_unsigned (irp->regcache,
3464 irp->regmap[X86_RECORD_RESI_REGNUM],
3466 *addr = (uint32_t) (*addr + offset64);
3469 regcache_raw_read_unsigned (irp->regcache,
3470 irp->regmap[X86_RECORD_REDI_REGNUM],
3472 *addr = (uint32_t) (*addr + offset64);
3475 regcache_raw_read_unsigned (irp->regcache,
3476 irp->regmap[X86_RECORD_REBP_REGNUM],
3478 *addr = (uint32_t) (*addr + offset64);
3481 regcache_raw_read_unsigned (irp->regcache,
3482 irp->regmap[X86_RECORD_REBX_REGNUM],
3484 *addr = (uint32_t) (*addr + offset64);
3494 /* Record the value of the memory that willbe changed in current instruction
3495 to "record_arch_list".
3496 Return -1 if something wrong. */
3499 i386_record_lea_modrm (struct i386_record_s *irp)
3501 struct gdbarch *gdbarch = irp->gdbarch;
3504 if (irp->override >= 0)
3506 warning (_("Process record ignores the memory change "
3507 "of instruction at address %s because it "
3508 "can't get the value of the segment register."),
3509 paddress (gdbarch, irp->orig_addr));
3513 if (i386_record_lea_modrm_addr (irp, &addr))
3516 if (record_arch_list_add_mem (addr, 1 << irp->ot))
3522 /* Record the push operation to "record_arch_list".
3523 Return -1 if something wrong. */
3526 i386_record_push (struct i386_record_s *irp, int size)
3530 if (record_arch_list_add_reg (irp->regcache,
3531 irp->regmap[X86_RECORD_RESP_REGNUM]))
3533 regcache_raw_read_unsigned (irp->regcache,
3534 irp->regmap[X86_RECORD_RESP_REGNUM],
3536 if (record_arch_list_add_mem ((CORE_ADDR) addr - size, size))
3543 /* Defines contents to record. */
3544 #define I386_SAVE_FPU_REGS 0xfffd
3545 #define I386_SAVE_FPU_ENV 0xfffe
3546 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3548 /* Record the value of floating point registers which will be changed by the
3549 current instruction to "record_arch_list". Return -1 if something is wrong.
3552 static int i386_record_floats (struct gdbarch *gdbarch,
3553 struct i386_record_s *ir,
3556 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3559 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3560 happen. Currently we store st0-st7 registers, but we need not store all
3561 registers all the time, in future we use ftag register and record only
3562 those who are not marked as an empty. */
3564 if (I386_SAVE_FPU_REGS == iregnum)
3566 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
3568 if (record_arch_list_add_reg (ir->regcache, i))
3572 else if (I386_SAVE_FPU_ENV == iregnum)
3574 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3576 if (record_arch_list_add_reg (ir->regcache, i))
3580 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
3582 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3584 if (record_arch_list_add_reg (ir->regcache, i))
3588 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
3589 (iregnum <= I387_FOP_REGNUM (tdep)))
3591 if (record_arch_list_add_reg (ir->regcache,iregnum))
3596 /* Parameter error. */
3599 if(I386_SAVE_FPU_ENV != iregnum)
3601 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3603 if (record_arch_list_add_reg (ir->regcache, i))
3610 /* Parse the current instruction and record the values of the registers and
3611 memory that will be changed in current instruction to "record_arch_list".
3612 Return -1 if something wrong. */
3614 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3615 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3618 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
3619 CORE_ADDR input_addr)
3621 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3627 gdb_byte buf[MAX_REGISTER_SIZE];
3628 struct i386_record_s ir;
3629 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3634 memset (&ir, 0, sizeof (struct i386_record_s));
3635 ir.regcache = regcache;
3636 ir.addr = input_addr;
3637 ir.orig_addr = input_addr;
3641 ir.popl_esp_hack = 0;
3642 ir.regmap = tdep->record_regmap;
3643 ir.gdbarch = gdbarch;
3645 if (record_debug > 1)
3646 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
3648 paddress (gdbarch, ir.addr));
3653 if (target_read_memory (ir.addr, &opcode8, 1))
3656 printf_unfiltered (_("Process record: error reading memory at "
3657 "addr %s len = 1.\n"),
3658 paddress (gdbarch, ir.addr));
3662 switch (opcode8) /* Instruction prefixes */
3664 case REPE_PREFIX_OPCODE:
3665 prefixes |= PREFIX_REPZ;
3667 case REPNE_PREFIX_OPCODE:
3668 prefixes |= PREFIX_REPNZ;
3670 case LOCK_PREFIX_OPCODE:
3671 prefixes |= PREFIX_LOCK;
3673 case CS_PREFIX_OPCODE:
3674 ir.override = X86_RECORD_CS_REGNUM;
3676 case SS_PREFIX_OPCODE:
3677 ir.override = X86_RECORD_SS_REGNUM;
3679 case DS_PREFIX_OPCODE:
3680 ir.override = X86_RECORD_DS_REGNUM;
3682 case ES_PREFIX_OPCODE:
3683 ir.override = X86_RECORD_ES_REGNUM;
3685 case FS_PREFIX_OPCODE:
3686 ir.override = X86_RECORD_FS_REGNUM;
3688 case GS_PREFIX_OPCODE:
3689 ir.override = X86_RECORD_GS_REGNUM;
3691 case DATA_PREFIX_OPCODE:
3692 prefixes |= PREFIX_DATA;
3694 case ADDR_PREFIX_OPCODE:
3695 prefixes |= PREFIX_ADDR;
3697 case 0x40: /* i386 inc %eax */
3698 case 0x41: /* i386 inc %ecx */
3699 case 0x42: /* i386 inc %edx */
3700 case 0x43: /* i386 inc %ebx */
3701 case 0x44: /* i386 inc %esp */
3702 case 0x45: /* i386 inc %ebp */
3703 case 0x46: /* i386 inc %esi */
3704 case 0x47: /* i386 inc %edi */
3705 case 0x48: /* i386 dec %eax */
3706 case 0x49: /* i386 dec %ecx */
3707 case 0x4a: /* i386 dec %edx */
3708 case 0x4b: /* i386 dec %ebx */
3709 case 0x4c: /* i386 dec %esp */
3710 case 0x4d: /* i386 dec %ebp */
3711 case 0x4e: /* i386 dec %esi */
3712 case 0x4f: /* i386 dec %edi */
3713 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
3717 rex_w = (opcode8 >> 3) & 1;
3718 rex_r = (opcode8 & 0x4) << 1;
3719 ir.rex_x = (opcode8 & 0x2) << 2;
3720 ir.rex_b = (opcode8 & 0x1) << 3;
3722 else /* 32 bit target */
3731 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
3737 if (prefixes & PREFIX_DATA)
3740 if (prefixes & PREFIX_ADDR)
3742 else if (ir.regmap[X86_RECORD_R8_REGNUM])
3745 /* now check op code */
3746 opcode = (uint32_t) opcode8;
3751 if (target_read_memory (ir.addr, &opcode8, 1))
3754 printf_unfiltered (_("Process record: error reading memory at "
3755 "addr %s len = 1.\n"),
3756 paddress (gdbarch, ir.addr));
3760 opcode = (uint32_t) opcode8 | 0x0f00;
3764 case 0x00: /* arith & logic */
3812 if (((opcode >> 3) & 7) != OP_CMPL)
3814 if ((opcode & 1) == 0)
3817 ir.ot = ir.dflag + OT_WORD;
3819 switch ((opcode >> 1) & 3)
3821 case 0: /* OP Ev, Gv */
3822 if (i386_record_modrm (&ir))
3826 if (i386_record_lea_modrm (&ir))
3832 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3834 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
3837 case 1: /* OP Gv, Ev */
3838 if (i386_record_modrm (&ir))
3841 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3843 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
3845 case 2: /* OP A, Iv */
3846 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
3850 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3853 case 0x80: /* GRP1 */
3857 if (i386_record_modrm (&ir))
3860 if (ir.reg != OP_CMPL)
3862 if ((opcode & 1) == 0)
3865 ir.ot = ir.dflag + OT_WORD;
3872 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
3873 if (i386_record_lea_modrm (&ir))
3877 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
3879 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3882 case 0x40: /* inc */
3891 case 0x48: /* dec */
3900 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7);
3901 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3904 case 0xf6: /* GRP3 */
3906 if ((opcode & 1) == 0)
3909 ir.ot = ir.dflag + OT_WORD;
3910 if (i386_record_modrm (&ir))
3913 if (ir.mod != 3 && ir.reg == 0)
3914 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
3919 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3925 if (i386_record_lea_modrm (&ir))
3931 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3933 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
3935 if (ir.reg == 3) /* neg */
3936 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3942 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
3943 if (ir.ot != OT_BYTE)
3944 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
3945 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3949 opcode = opcode << 8 | ir.modrm;
3955 case 0xfe: /* GRP4 */
3956 case 0xff: /* GRP5 */
3957 if (i386_record_modrm (&ir))
3959 if (ir.reg >= 2 && opcode == 0xfe)
3962 opcode = opcode << 8 | ir.modrm;
3969 if ((opcode & 1) == 0)
3972 ir.ot = ir.dflag + OT_WORD;
3975 if (i386_record_lea_modrm (&ir))
3981 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3983 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
3985 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3988 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
3990 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
3992 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3995 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
3996 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
3998 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4002 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4005 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4007 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4012 opcode = opcode << 8 | ir.modrm;
4018 case 0x84: /* test */
4022 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4025 case 0x98: /* CWDE/CBW */
4026 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4029 case 0x99: /* CDQ/CWD */
4030 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4031 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
4034 case 0x0faf: /* imul */
4037 ir.ot = ir.dflag + OT_WORD;
4038 if (i386_record_modrm (&ir))
4041 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4042 else if (opcode == 0x6b)
4045 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4047 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4048 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4051 case 0x0fc0: /* xadd */
4053 if ((opcode & 1) == 0)
4056 ir.ot = ir.dflag + OT_WORD;
4057 if (i386_record_modrm (&ir))
4062 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4064 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4065 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4067 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4071 if (i386_record_lea_modrm (&ir))
4073 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4075 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4077 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4080 case 0x0fb0: /* cmpxchg */
4082 if ((opcode & 1) == 0)
4085 ir.ot = ir.dflag + OT_WORD;
4086 if (i386_record_modrm (&ir))
4091 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4092 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4094 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4098 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4099 if (i386_record_lea_modrm (&ir))
4102 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4105 case 0x0fc7: /* cmpxchg8b */
4106 if (i386_record_modrm (&ir))
4111 opcode = opcode << 8 | ir.modrm;
4114 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4115 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
4116 if (i386_record_lea_modrm (&ir))
4118 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4121 case 0x50: /* push */
4131 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4133 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4137 case 0x06: /* push es */
4138 case 0x0e: /* push cs */
4139 case 0x16: /* push ss */
4140 case 0x1e: /* push ds */
4141 if (ir.regmap[X86_RECORD_R8_REGNUM])
4146 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4150 case 0x0fa0: /* push fs */
4151 case 0x0fa8: /* push gs */
4152 if (ir.regmap[X86_RECORD_R8_REGNUM])
4157 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4161 case 0x60: /* pusha */
4162 if (ir.regmap[X86_RECORD_R8_REGNUM])
4167 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
4171 case 0x58: /* pop */
4179 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4180 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
4183 case 0x61: /* popa */
4184 if (ir.regmap[X86_RECORD_R8_REGNUM])
4189 for (regnum = X86_RECORD_REAX_REGNUM;
4190 regnum <= X86_RECORD_REDI_REGNUM;
4192 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
4195 case 0x8f: /* pop */
4196 if (ir.regmap[X86_RECORD_R8_REGNUM])
4197 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
4199 ir.ot = ir.dflag + OT_WORD;
4200 if (i386_record_modrm (&ir))
4203 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
4206 ir.popl_esp_hack = 1 << ir.ot;
4207 if (i386_record_lea_modrm (&ir))
4210 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4213 case 0xc8: /* enter */
4214 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
4215 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4217 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4221 case 0xc9: /* leave */
4222 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4223 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
4226 case 0x07: /* pop es */
4227 if (ir.regmap[X86_RECORD_R8_REGNUM])
4232 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4233 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
4234 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4237 case 0x17: /* pop ss */
4238 if (ir.regmap[X86_RECORD_R8_REGNUM])
4243 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4244 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
4245 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4248 case 0x1f: /* pop ds */
4249 if (ir.regmap[X86_RECORD_R8_REGNUM])
4254 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4255 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
4256 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4259 case 0x0fa1: /* pop fs */
4260 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4261 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
4262 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4265 case 0x0fa9: /* pop gs */
4266 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4267 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
4268 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4271 case 0x88: /* mov */
4275 if ((opcode & 1) == 0)
4278 ir.ot = ir.dflag + OT_WORD;
4280 if (i386_record_modrm (&ir))
4285 if (opcode == 0xc6 || opcode == 0xc7)
4286 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4287 if (i386_record_lea_modrm (&ir))
4292 if (opcode == 0xc6 || opcode == 0xc7)
4294 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4296 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4300 case 0x8a: /* mov */
4302 if ((opcode & 1) == 0)
4305 ir.ot = ir.dflag + OT_WORD;
4306 if (i386_record_modrm (&ir))
4309 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4311 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4314 case 0x8c: /* mov seg */
4315 if (i386_record_modrm (&ir))
4320 opcode = opcode << 8 | ir.modrm;
4325 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4329 if (i386_record_lea_modrm (&ir))
4334 case 0x8e: /* mov seg */
4335 if (i386_record_modrm (&ir))
4340 regnum = X86_RECORD_ES_REGNUM;
4343 regnum = X86_RECORD_SS_REGNUM;
4346 regnum = X86_RECORD_DS_REGNUM;
4349 regnum = X86_RECORD_FS_REGNUM;
4352 regnum = X86_RECORD_GS_REGNUM;
4356 opcode = opcode << 8 | ir.modrm;
4360 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
4361 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4364 case 0x0fb6: /* movzbS */
4365 case 0x0fb7: /* movzwS */
4366 case 0x0fbe: /* movsbS */
4367 case 0x0fbf: /* movswS */
4368 if (i386_record_modrm (&ir))
4370 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
4373 case 0x8d: /* lea */
4374 if (i386_record_modrm (&ir))
4379 opcode = opcode << 8 | ir.modrm;
4384 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4386 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4389 case 0xa0: /* mov EAX */
4392 case 0xd7: /* xlat */
4393 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4396 case 0xa2: /* mov EAX */
4398 if (ir.override >= 0)
4400 warning (_("Process record ignores the memory change "
4401 "of instruction at address %s because "
4402 "it can't get the value of the segment "
4404 paddress (gdbarch, ir.orig_addr));
4408 if ((opcode & 1) == 0)
4411 ir.ot = ir.dflag + OT_WORD;
4414 if (target_read_memory (ir.addr, buf, 8))
4417 printf_unfiltered (_("Process record: error reading "
4418 "memory at addr 0x%s len = 8.\n"),
4419 paddress (gdbarch, ir.addr));
4423 addr = extract_unsigned_integer (buf, 8, byte_order);
4427 if (target_read_memory (ir.addr, buf, 4))
4430 printf_unfiltered (_("Process record: error reading "
4431 "memory at addr 0x%s len = 4.\n"),
4432 paddress (gdbarch, ir.addr));
4436 addr = extract_unsigned_integer (buf, 4, byte_order);
4440 if (target_read_memory (ir.addr, buf, 2))
4443 printf_unfiltered (_("Process record: error reading "
4444 "memory at addr 0x%s len = 2.\n"),
4445 paddress (gdbarch, ir.addr));
4449 addr = extract_unsigned_integer (buf, 2, byte_order);
4451 if (record_arch_list_add_mem (addr, 1 << ir.ot))
4456 case 0xb0: /* mov R, Ib */
4464 I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
4465 ? ((opcode & 0x7) | ir.rex_b)
4466 : ((opcode & 0x7) & 0x3));
4469 case 0xb8: /* mov R, Iv */
4477 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
4480 case 0x91: /* xchg R, EAX */
4487 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4488 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7);
4491 case 0x86: /* xchg Ev, Gv */
4493 if ((opcode & 1) == 0)
4496 ir.ot = ir.dflag + OT_WORD;
4497 if (i386_record_modrm (&ir))
4502 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4504 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4508 if (i386_record_lea_modrm (&ir))
4512 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4514 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4517 case 0xc4: /* les Gv */
4518 case 0xc5: /* lds Gv */
4519 if (ir.regmap[X86_RECORD_R8_REGNUM])
4524 case 0x0fb2: /* lss Gv */
4525 case 0x0fb4: /* lfs Gv */
4526 case 0x0fb5: /* lgs Gv */
4527 if (i386_record_modrm (&ir))
4535 opcode = opcode << 8 | ir.modrm;
4540 case 0xc4: /* les Gv */
4541 regnum = X86_RECORD_ES_REGNUM;
4543 case 0xc5: /* lds Gv */
4544 regnum = X86_RECORD_DS_REGNUM;
4546 case 0x0fb2: /* lss Gv */
4547 regnum = X86_RECORD_SS_REGNUM;
4549 case 0x0fb4: /* lfs Gv */
4550 regnum = X86_RECORD_FS_REGNUM;
4552 case 0x0fb5: /* lgs Gv */
4553 regnum = X86_RECORD_GS_REGNUM;
4556 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
4557 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
4558 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4561 case 0xc0: /* shifts */
4567 if ((opcode & 1) == 0)
4570 ir.ot = ir.dflag + OT_WORD;
4571 if (i386_record_modrm (&ir))
4573 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
4575 if (i386_record_lea_modrm (&ir))
4581 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4583 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4585 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4592 if (i386_record_modrm (&ir))
4596 if (record_arch_list_add_reg (ir.regcache, ir.rm))
4601 if (i386_record_lea_modrm (&ir))
4606 case 0xd8: /* Floats. */
4614 if (i386_record_modrm (&ir))
4616 ir.reg |= ((opcode & 7) << 3);
4622 if (i386_record_lea_modrm_addr (&ir, &addr64))
4630 /* For fcom, ficom nothing to do. */
4636 /* For fcomp, ficomp pop FPU stack, store all. */
4637 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4664 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
4665 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
4666 of code, always affects st(0) register. */
4667 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
4691 /* Handling fld, fild. */
4692 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4696 switch (ir.reg >> 4)
4699 if (record_arch_list_add_mem (addr64, 4))
4703 if (record_arch_list_add_mem (addr64, 8))
4709 if (record_arch_list_add_mem (addr64, 2))
4715 switch (ir.reg >> 4)
4718 if (record_arch_list_add_mem (addr64, 4))
4720 if (3 == (ir.reg & 7))
4722 /* For fstp m32fp. */
4723 if (i386_record_floats (gdbarch, &ir,
4724 I386_SAVE_FPU_REGS))
4729 if (record_arch_list_add_mem (addr64, 4))
4731 if ((3 == (ir.reg & 7))
4732 || (5 == (ir.reg & 7))
4733 || (7 == (ir.reg & 7)))
4735 /* For fstp insn. */
4736 if (i386_record_floats (gdbarch, &ir,
4737 I386_SAVE_FPU_REGS))
4742 if (record_arch_list_add_mem (addr64, 8))
4744 if (3 == (ir.reg & 7))
4746 /* For fstp m64fp. */
4747 if (i386_record_floats (gdbarch, &ir,
4748 I386_SAVE_FPU_REGS))
4753 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
4755 /* For fistp, fbld, fild, fbstp. */
4756 if (i386_record_floats (gdbarch, &ir,
4757 I386_SAVE_FPU_REGS))
4762 if (record_arch_list_add_mem (addr64, 2))
4771 if (i386_record_floats (gdbarch, &ir,
4772 I386_SAVE_FPU_ENV_REG_STACK))
4777 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
4782 if (i386_record_floats (gdbarch, &ir,
4783 I386_SAVE_FPU_ENV_REG_STACK))
4789 if (record_arch_list_add_mem (addr64, 28))
4794 if (record_arch_list_add_mem (addr64, 14))
4800 if (record_arch_list_add_mem (addr64, 2))
4802 /* Insn fstp, fbstp. */
4803 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4808 if (record_arch_list_add_mem (addr64, 10))
4814 if (record_arch_list_add_mem (addr64, 28))
4820 if (record_arch_list_add_mem (addr64, 14))
4824 if (record_arch_list_add_mem (addr64, 80))
4827 if (i386_record_floats (gdbarch, &ir,
4828 I386_SAVE_FPU_ENV_REG_STACK))
4832 if (record_arch_list_add_mem (addr64, 8))
4835 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4840 opcode = opcode << 8 | ir.modrm;
4845 /* Opcode is an extension of modR/M byte. */
4851 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
4855 if (0x0c == (ir.modrm >> 4))
4857 if ((ir.modrm & 0x0f) <= 7)
4859 if (i386_record_floats (gdbarch, &ir,
4860 I386_SAVE_FPU_REGS))
4865 if (i386_record_floats (gdbarch, &ir,
4866 I387_ST0_REGNUM (tdep)))
4868 /* If only st(0) is changing, then we have already
4870 if ((ir.modrm & 0x0f) - 0x08)
4872 if (i386_record_floats (gdbarch, &ir,
4873 I387_ST0_REGNUM (tdep) +
4874 ((ir.modrm & 0x0f) - 0x08)))
4892 if (i386_record_floats (gdbarch, &ir,
4893 I387_ST0_REGNUM (tdep)))
4911 if (i386_record_floats (gdbarch, &ir,
4912 I386_SAVE_FPU_REGS))
4916 if (i386_record_floats (gdbarch, &ir,
4917 I387_ST0_REGNUM (tdep)))
4919 if (i386_record_floats (gdbarch, &ir,
4920 I387_ST0_REGNUM (tdep) + 1))
4927 if (0xe9 == ir.modrm)
4929 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4932 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
4934 if (i386_record_floats (gdbarch, &ir,
4935 I387_ST0_REGNUM (tdep)))
4937 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
4939 if (i386_record_floats (gdbarch, &ir,
4940 I387_ST0_REGNUM (tdep) +
4944 else if ((ir.modrm & 0x0f) - 0x08)
4946 if (i386_record_floats (gdbarch, &ir,
4947 I387_ST0_REGNUM (tdep) +
4948 ((ir.modrm & 0x0f) - 0x08)))
4954 if (0xe3 == ir.modrm)
4956 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
4959 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
4961 if (i386_record_floats (gdbarch, &ir,
4962 I387_ST0_REGNUM (tdep)))
4964 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
4966 if (i386_record_floats (gdbarch, &ir,
4967 I387_ST0_REGNUM (tdep) +
4971 else if ((ir.modrm & 0x0f) - 0x08)
4973 if (i386_record_floats (gdbarch, &ir,
4974 I387_ST0_REGNUM (tdep) +
4975 ((ir.modrm & 0x0f) - 0x08)))
4981 if ((0x0c == ir.modrm >> 4)
4982 || (0x0d == ir.modrm >> 4)
4983 || (0x0f == ir.modrm >> 4))
4985 if ((ir.modrm & 0x0f) <= 7)
4987 if (i386_record_floats (gdbarch, &ir,
4988 I387_ST0_REGNUM (tdep) +
4994 if (i386_record_floats (gdbarch, &ir,
4995 I387_ST0_REGNUM (tdep) +
4996 ((ir.modrm & 0x0f) - 0x08)))
5002 if (0x0c == ir.modrm >> 4)
5004 if (i386_record_floats (gdbarch, &ir,
5005 I387_FTAG_REGNUM (tdep)))
5008 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
5010 if ((ir.modrm & 0x0f) <= 7)
5012 if (i386_record_floats (gdbarch, &ir,
5013 I387_ST0_REGNUM (tdep) +
5019 if (i386_record_floats (gdbarch, &ir,
5020 I386_SAVE_FPU_REGS))
5026 if ((0x0c == ir.modrm >> 4)
5027 || (0x0e == ir.modrm >> 4)
5028 || (0x0f == ir.modrm >> 4)
5029 || (0xd9 == ir.modrm))
5031 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5036 if (0xe0 == ir.modrm)
5038 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
5041 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
5043 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5051 case 0xa4: /* movsS */
5053 case 0xaa: /* stosS */
5055 case 0x6c: /* insS */
5057 regcache_raw_read_unsigned (ir.regcache,
5058 ir.regmap[X86_RECORD_RECX_REGNUM],
5064 if ((opcode & 1) == 0)
5067 ir.ot = ir.dflag + OT_WORD;
5068 regcache_raw_read_unsigned (ir.regcache,
5069 ir.regmap[X86_RECORD_REDI_REGNUM],
5072 regcache_raw_read_unsigned (ir.regcache,
5073 ir.regmap[X86_RECORD_ES_REGNUM],
5075 regcache_raw_read_unsigned (ir.regcache,
5076 ir.regmap[X86_RECORD_DS_REGNUM],
5078 if (ir.aflag && (es != ds))
5080 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5081 warning (_("Process record ignores the memory "
5082 "change of instruction at address %s "
5083 "because it can't get the value of the "
5084 "ES segment register."),
5085 paddress (gdbarch, ir.orig_addr));
5089 if (record_arch_list_add_mem (addr, 1 << ir.ot))
5093 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5094 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5095 if (opcode == 0xa4 || opcode == 0xa5)
5096 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5097 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5098 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5102 case 0xa6: /* cmpsS */
5104 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5105 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5106 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5107 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5108 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5111 case 0xac: /* lodsS */
5113 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5114 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5115 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5116 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5117 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5120 case 0xae: /* scasS */
5122 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5123 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5124 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5125 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5128 case 0x6e: /* outsS */
5130 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5131 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5132 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5133 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5136 case 0xe4: /* port I/O */
5140 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5141 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5151 case 0xc2: /* ret im */
5152 case 0xc3: /* ret */
5153 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5154 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5157 case 0xca: /* lret im */
5158 case 0xcb: /* lret */
5159 case 0xcf: /* iret */
5160 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5161 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5162 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5165 case 0xe8: /* call im */
5166 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5168 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5172 case 0x9a: /* lcall im */
5173 if (ir.regmap[X86_RECORD_R8_REGNUM])
5178 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5179 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5183 case 0xe9: /* jmp im */
5184 case 0xea: /* ljmp im */
5185 case 0xeb: /* jmp Jb */
5186 case 0x70: /* jcc Jb */
5202 case 0x0f80: /* jcc Jv */
5220 case 0x0f90: /* setcc Gv */
5236 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5238 if (i386_record_modrm (&ir))
5241 I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
5245 if (i386_record_lea_modrm (&ir))
5250 case 0x0f40: /* cmov Gv, Ev */
5266 if (i386_record_modrm (&ir))
5269 if (ir.dflag == OT_BYTE)
5271 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
5275 case 0x9c: /* pushf */
5276 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5277 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5279 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5283 case 0x9d: /* popf */
5284 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5285 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5288 case 0x9e: /* sahf */
5289 if (ir.regmap[X86_RECORD_R8_REGNUM])
5294 case 0xf5: /* cmc */
5295 case 0xf8: /* clc */
5296 case 0xf9: /* stc */
5297 case 0xfc: /* cld */
5298 case 0xfd: /* std */
5299 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5302 case 0x9f: /* lahf */
5303 if (ir.regmap[X86_RECORD_R8_REGNUM])
5308 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5309 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5312 /* bit operations */
5313 case 0x0fba: /* bt/bts/btr/btc Gv, im */
5314 ir.ot = ir.dflag + OT_WORD;
5315 if (i386_record_modrm (&ir))
5320 opcode = opcode << 8 | ir.modrm;
5326 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5329 if (i386_record_lea_modrm (&ir))
5333 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5336 case 0x0fa3: /* bt Gv, Ev */
5337 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5340 case 0x0fab: /* bts */
5341 case 0x0fb3: /* btr */
5342 case 0x0fbb: /* btc */
5343 ir.ot = ir.dflag + OT_WORD;
5344 if (i386_record_modrm (&ir))
5347 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5351 if (i386_record_lea_modrm_addr (&ir, &addr64))
5353 regcache_raw_read_unsigned (ir.regcache,
5354 ir.regmap[ir.reg | rex_r],
5359 addr64 += ((int16_t) addr >> 4) << 4;
5362 addr64 += ((int32_t) addr >> 5) << 5;
5365 addr64 += ((int64_t) addr >> 6) << 6;
5368 if (record_arch_list_add_mem (addr64, 1 << ir.ot))
5370 if (i386_record_lea_modrm (&ir))
5373 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5376 case 0x0fbc: /* bsf */
5377 case 0x0fbd: /* bsr */
5378 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5379 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5383 case 0x27: /* daa */
5384 case 0x2f: /* das */
5385 case 0x37: /* aaa */
5386 case 0x3f: /* aas */
5387 case 0xd4: /* aam */
5388 case 0xd5: /* aad */
5389 if (ir.regmap[X86_RECORD_R8_REGNUM])
5394 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5395 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5399 case 0x90: /* nop */
5400 if (prefixes & PREFIX_LOCK)
5407 case 0x9b: /* fwait */
5408 if (target_read_memory (ir.addr, &opcode8, 1))
5411 printf_unfiltered (_("Process record: error reading memory at "
5412 "addr 0x%s len = 1.\n"),
5413 paddress (gdbarch, ir.addr));
5416 opcode = (uint32_t) opcode8;
5422 case 0xcc: /* int3 */
5423 printf_unfiltered (_("Process record does not support instruction "
5430 case 0xcd: /* int */
5434 if (target_read_memory (ir.addr, &interrupt, 1))
5437 printf_unfiltered (_("Process record: error reading memory "
5438 "at addr %s len = 1.\n"),
5439 paddress (gdbarch, ir.addr));
5443 if (interrupt != 0x80
5444 || tdep->i386_intx80_record == NULL)
5446 printf_unfiltered (_("Process record does not support "
5447 "instruction int 0x%02x.\n"),
5452 ret = tdep->i386_intx80_record (ir.regcache);
5459 case 0xce: /* into */
5460 printf_unfiltered (_("Process record does not support "
5461 "instruction into.\n"));
5466 case 0xfa: /* cli */
5467 case 0xfb: /* sti */
5470 case 0x62: /* bound */
5471 printf_unfiltered (_("Process record does not support "
5472 "instruction bound.\n"));
5477 case 0x0fc8: /* bswap reg */
5485 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
5488 case 0xd6: /* salc */
5489 if (ir.regmap[X86_RECORD_R8_REGNUM])
5494 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5495 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5498 case 0xe0: /* loopnz */
5499 case 0xe1: /* loopz */
5500 case 0xe2: /* loop */
5501 case 0xe3: /* jecxz */
5502 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5503 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5506 case 0x0f30: /* wrmsr */
5507 printf_unfiltered (_("Process record does not support "
5508 "instruction wrmsr.\n"));
5513 case 0x0f32: /* rdmsr */
5514 printf_unfiltered (_("Process record does not support "
5515 "instruction rdmsr.\n"));
5520 case 0x0f31: /* rdtsc */
5521 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5522 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5525 case 0x0f34: /* sysenter */
5528 if (ir.regmap[X86_RECORD_R8_REGNUM])
5533 if (tdep->i386_sysenter_record == NULL)
5535 printf_unfiltered (_("Process record does not support "
5536 "instruction sysenter.\n"));
5540 ret = tdep->i386_sysenter_record (ir.regcache);
5546 case 0x0f35: /* sysexit */
5547 printf_unfiltered (_("Process record does not support "
5548 "instruction sysexit.\n"));
5553 case 0x0f05: /* syscall */
5556 if (tdep->i386_syscall_record == NULL)
5558 printf_unfiltered (_("Process record does not support "
5559 "instruction syscall.\n"));
5563 ret = tdep->i386_syscall_record (ir.regcache);
5569 case 0x0f07: /* sysret */
5570 printf_unfiltered (_("Process record does not support "
5571 "instruction sysret.\n"));
5576 case 0x0fa2: /* cpuid */
5577 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5578 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5579 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5580 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
5583 case 0xf4: /* hlt */
5584 printf_unfiltered (_("Process record does not support "
5585 "instruction hlt.\n"));
5591 if (i386_record_modrm (&ir))
5598 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5602 if (i386_record_lea_modrm (&ir))
5611 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5615 opcode = opcode << 8 | ir.modrm;
5622 if (i386_record_modrm (&ir))
5633 opcode = opcode << 8 | ir.modrm;
5636 if (ir.override >= 0)
5638 warning (_("Process record ignores the memory "
5639 "change of instruction at "
5640 "address %s because it can't get "
5641 "the value of the segment "
5643 paddress (gdbarch, ir.orig_addr));
5647 if (i386_record_lea_modrm_addr (&ir, &addr64))
5649 if (record_arch_list_add_mem (addr64, 2))
5652 if (ir.regmap[X86_RECORD_R8_REGNUM])
5654 if (record_arch_list_add_mem (addr64, 8))
5659 if (record_arch_list_add_mem (addr64, 4))
5670 case 0: /* monitor */
5673 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5677 opcode = opcode << 8 | ir.modrm;
5685 if (ir.override >= 0)
5687 warning (_("Process record ignores the memory "
5688 "change of instruction at "
5689 "address %s because it can't get "
5690 "the value of the segment "
5692 paddress (gdbarch, ir.orig_addr));
5698 if (i386_record_lea_modrm_addr (&ir, &addr64))
5700 if (record_arch_list_add_mem (addr64, 2))
5703 if (ir.regmap[X86_RECORD_R8_REGNUM])
5705 if (record_arch_list_add_mem (addr64, 8))
5710 if (record_arch_list_add_mem (addr64, 4))
5722 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5723 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5727 else if (ir.rm == 1)
5734 opcode = opcode << 8 | ir.modrm;
5741 if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
5747 if (i386_record_lea_modrm (&ir))
5750 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5753 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5755 case 7: /* invlpg */
5758 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
5759 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
5763 opcode = opcode << 8 | ir.modrm;
5768 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5772 opcode = opcode << 8 | ir.modrm;
5778 case 0x0f08: /* invd */
5779 case 0x0f09: /* wbinvd */
5782 case 0x63: /* arpl */
5783 if (i386_record_modrm (&ir))
5785 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
5787 I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
5788 ? (ir.reg | rex_r) : ir.rm);
5792 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
5793 if (i386_record_lea_modrm (&ir))
5796 if (!ir.regmap[X86_RECORD_R8_REGNUM])
5797 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5800 case 0x0f02: /* lar */
5801 case 0x0f03: /* lsl */
5802 if (i386_record_modrm (&ir))
5804 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5805 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5809 if (i386_record_modrm (&ir))
5811 if (ir.mod == 3 && ir.reg == 3)
5814 opcode = opcode << 8 | ir.modrm;
5826 /* nop (multi byte) */
5829 case 0x0f20: /* mov reg, crN */
5830 case 0x0f22: /* mov crN, reg */
5831 if (i386_record_modrm (&ir))
5833 if ((ir.modrm & 0xc0) != 0xc0)
5836 opcode = opcode << 8 | ir.modrm;
5847 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5849 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5853 opcode = opcode << 8 | ir.modrm;
5859 case 0x0f21: /* mov reg, drN */
5860 case 0x0f23: /* mov drN, reg */
5861 if (i386_record_modrm (&ir))
5863 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
5864 || ir.reg == 5 || ir.reg >= 8)
5867 opcode = opcode << 8 | ir.modrm;
5871 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5873 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5876 case 0x0f06: /* clts */
5877 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5880 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
5882 case 0x0f0d: /* 3DNow! prefetch */
5885 case 0x0f0e: /* 3DNow! femms */
5886 case 0x0f77: /* emms */
5887 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
5889 record_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
5892 case 0x0f0f: /* 3DNow! data */
5893 if (i386_record_modrm (&ir))
5895 if (target_read_memory (ir.addr, &opcode8, 1))
5897 printf_unfiltered (_("Process record: error reading memory at "
5898 "addr %s len = 1.\n"),
5899 paddress (gdbarch, ir.addr));
5905 case 0x0c: /* 3DNow! pi2fw */
5906 case 0x0d: /* 3DNow! pi2fd */
5907 case 0x1c: /* 3DNow! pf2iw */
5908 case 0x1d: /* 3DNow! pf2id */
5909 case 0x8a: /* 3DNow! pfnacc */
5910 case 0x8e: /* 3DNow! pfpnacc */
5911 case 0x90: /* 3DNow! pfcmpge */
5912 case 0x94: /* 3DNow! pfmin */
5913 case 0x96: /* 3DNow! pfrcp */
5914 case 0x97: /* 3DNow! pfrsqrt */
5915 case 0x9a: /* 3DNow! pfsub */
5916 case 0x9e: /* 3DNow! pfadd */
5917 case 0xa0: /* 3DNow! pfcmpgt */
5918 case 0xa4: /* 3DNow! pfmax */
5919 case 0xa6: /* 3DNow! pfrcpit1 */
5920 case 0xa7: /* 3DNow! pfrsqit1 */
5921 case 0xaa: /* 3DNow! pfsubr */
5922 case 0xae: /* 3DNow! pfacc */
5923 case 0xb0: /* 3DNow! pfcmpeq */
5924 case 0xb4: /* 3DNow! pfmul */
5925 case 0xb6: /* 3DNow! pfrcpit2 */
5926 case 0xb7: /* 3DNow! pmulhrw */
5927 case 0xbb: /* 3DNow! pswapd */
5928 case 0xbf: /* 3DNow! pavgusb */
5929 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
5930 goto no_support_3dnow_data;
5931 record_arch_list_add_reg (ir.regcache, ir.reg);
5935 no_support_3dnow_data:
5936 opcode = (opcode << 8) | opcode8;
5942 case 0x0faa: /* rsm */
5943 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5944 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5945 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5946 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5947 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
5948 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5949 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5950 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5951 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5955 if (i386_record_modrm (&ir))
5959 case 0: /* fxsave */
5963 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5964 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
5966 if (record_arch_list_add_mem (tmpu64, 512))
5971 case 1: /* fxrstor */
5975 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5977 for (i = I387_MM0_REGNUM (tdep);
5978 i386_mmx_regnum_p (gdbarch, i); i++)
5979 record_arch_list_add_reg (ir.regcache, i);
5981 for (i = I387_XMM0_REGNUM (tdep);
5982 i386_xmm_regnum_p (gdbarch, i); i++)
5983 record_arch_list_add_reg (ir.regcache, i);
5985 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
5986 record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
5988 for (i = I387_ST0_REGNUM (tdep);
5989 i386_fp_regnum_p (gdbarch, i); i++)
5990 record_arch_list_add_reg (ir.regcache, i);
5992 for (i = I387_FCTRL_REGNUM (tdep);
5993 i386_fpc_regnum_p (gdbarch, i); i++)
5994 record_arch_list_add_reg (ir.regcache, i);
5998 case 2: /* ldmxcsr */
5999 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
6001 record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
6004 case 3: /* stmxcsr */
6006 if (i386_record_lea_modrm (&ir))
6010 case 5: /* lfence */
6011 case 6: /* mfence */
6012 case 7: /* sfence clflush */
6016 opcode = (opcode << 8) | ir.modrm;
6022 case 0x0fc3: /* movnti */
6023 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
6024 if (i386_record_modrm (&ir))
6029 if (i386_record_lea_modrm (&ir))
6033 /* Add prefix to opcode. */
6160 reswitch_prefix_add:
6168 if (target_read_memory (ir.addr, &opcode8, 1))
6170 printf_unfiltered (_("Process record: error reading memory at "
6171 "addr %s len = 1.\n"),
6172 paddress (gdbarch, ir.addr));
6176 opcode = (uint32_t) opcode8 | opcode << 8;
6177 goto reswitch_prefix_add;
6180 case 0x0f10: /* movups */
6181 case 0x660f10: /* movupd */
6182 case 0xf30f10: /* movss */
6183 case 0xf20f10: /* movsd */
6184 case 0x0f12: /* movlps */
6185 case 0x660f12: /* movlpd */
6186 case 0xf30f12: /* movsldup */
6187 case 0xf20f12: /* movddup */
6188 case 0x0f14: /* unpcklps */
6189 case 0x660f14: /* unpcklpd */
6190 case 0x0f15: /* unpckhps */
6191 case 0x660f15: /* unpckhpd */
6192 case 0x0f16: /* movhps */
6193 case 0x660f16: /* movhpd */
6194 case 0xf30f16: /* movshdup */
6195 case 0x0f28: /* movaps */
6196 case 0x660f28: /* movapd */
6197 case 0x0f2a: /* cvtpi2ps */
6198 case 0x660f2a: /* cvtpi2pd */
6199 case 0xf30f2a: /* cvtsi2ss */
6200 case 0xf20f2a: /* cvtsi2sd */
6201 case 0x0f2c: /* cvttps2pi */
6202 case 0x660f2c: /* cvttpd2pi */
6203 case 0x0f2d: /* cvtps2pi */
6204 case 0x660f2d: /* cvtpd2pi */
6205 case 0x660f3800: /* pshufb */
6206 case 0x660f3801: /* phaddw */
6207 case 0x660f3802: /* phaddd */
6208 case 0x660f3803: /* phaddsw */
6209 case 0x660f3804: /* pmaddubsw */
6210 case 0x660f3805: /* phsubw */
6211 case 0x660f3806: /* phsubd */
6212 case 0x660f3807: /* phaddsw */
6213 case 0x660f3808: /* psignb */
6214 case 0x660f3809: /* psignw */
6215 case 0x660f380a: /* psignd */
6216 case 0x660f380b: /* pmulhrsw */
6217 case 0x660f3810: /* pblendvb */
6218 case 0x660f3814: /* blendvps */
6219 case 0x660f3815: /* blendvpd */
6220 case 0x660f381c: /* pabsb */
6221 case 0x660f381d: /* pabsw */
6222 case 0x660f381e: /* pabsd */
6223 case 0x660f3820: /* pmovsxbw */
6224 case 0x660f3821: /* pmovsxbd */
6225 case 0x660f3822: /* pmovsxbq */
6226 case 0x660f3823: /* pmovsxwd */
6227 case 0x660f3824: /* pmovsxwq */
6228 case 0x660f3825: /* pmovsxdq */
6229 case 0x660f3828: /* pmuldq */
6230 case 0x660f3829: /* pcmpeqq */
6231 case 0x660f382a: /* movntdqa */
6232 case 0x660f3a08: /* roundps */
6233 case 0x660f3a09: /* roundpd */
6234 case 0x660f3a0a: /* roundss */
6235 case 0x660f3a0b: /* roundsd */
6236 case 0x660f3a0c: /* blendps */
6237 case 0x660f3a0d: /* blendpd */
6238 case 0x660f3a0e: /* pblendw */
6239 case 0x660f3a0f: /* palignr */
6240 case 0x660f3a20: /* pinsrb */
6241 case 0x660f3a21: /* insertps */
6242 case 0x660f3a22: /* pinsrd pinsrq */
6243 case 0x660f3a40: /* dpps */
6244 case 0x660f3a41: /* dppd */
6245 case 0x660f3a42: /* mpsadbw */
6246 case 0x660f3a60: /* pcmpestrm */
6247 case 0x660f3a61: /* pcmpestri */
6248 case 0x660f3a62: /* pcmpistrm */
6249 case 0x660f3a63: /* pcmpistri */
6250 case 0x0f51: /* sqrtps */
6251 case 0x660f51: /* sqrtpd */
6252 case 0xf20f51: /* sqrtsd */
6253 case 0xf30f51: /* sqrtss */
6254 case 0x0f52: /* rsqrtps */
6255 case 0xf30f52: /* rsqrtss */
6256 case 0x0f53: /* rcpps */
6257 case 0xf30f53: /* rcpss */
6258 case 0x0f54: /* andps */
6259 case 0x660f54: /* andpd */
6260 case 0x0f55: /* andnps */
6261 case 0x660f55: /* andnpd */
6262 case 0x0f56: /* orps */
6263 case 0x660f56: /* orpd */
6264 case 0x0f57: /* xorps */
6265 case 0x660f57: /* xorpd */
6266 case 0x0f58: /* addps */
6267 case 0x660f58: /* addpd */
6268 case 0xf20f58: /* addsd */
6269 case 0xf30f58: /* addss */
6270 case 0x0f59: /* mulps */
6271 case 0x660f59: /* mulpd */
6272 case 0xf20f59: /* mulsd */
6273 case 0xf30f59: /* mulss */
6274 case 0x0f5a: /* cvtps2pd */
6275 case 0x660f5a: /* cvtpd2ps */
6276 case 0xf20f5a: /* cvtsd2ss */
6277 case 0xf30f5a: /* cvtss2sd */
6278 case 0x0f5b: /* cvtdq2ps */
6279 case 0x660f5b: /* cvtps2dq */
6280 case 0xf30f5b: /* cvttps2dq */
6281 case 0x0f5c: /* subps */
6282 case 0x660f5c: /* subpd */
6283 case 0xf20f5c: /* subsd */
6284 case 0xf30f5c: /* subss */
6285 case 0x0f5d: /* minps */
6286 case 0x660f5d: /* minpd */
6287 case 0xf20f5d: /* minsd */
6288 case 0xf30f5d: /* minss */
6289 case 0x0f5e: /* divps */
6290 case 0x660f5e: /* divpd */
6291 case 0xf20f5e: /* divsd */
6292 case 0xf30f5e: /* divss */
6293 case 0x0f5f: /* maxps */
6294 case 0x660f5f: /* maxpd */
6295 case 0xf20f5f: /* maxsd */
6296 case 0xf30f5f: /* maxss */
6297 case 0x660f60: /* punpcklbw */
6298 case 0x660f61: /* punpcklwd */
6299 case 0x660f62: /* punpckldq */
6300 case 0x660f63: /* packsswb */
6301 case 0x660f64: /* pcmpgtb */
6302 case 0x660f65: /* pcmpgtw */
6303 case 0x660f66: /* pcmpgtl */
6304 case 0x660f67: /* packuswb */
6305 case 0x660f68: /* punpckhbw */
6306 case 0x660f69: /* punpckhwd */
6307 case 0x660f6a: /* punpckhdq */
6308 case 0x660f6b: /* packssdw */
6309 case 0x660f6c: /* punpcklqdq */
6310 case 0x660f6d: /* punpckhqdq */
6311 case 0x660f6e: /* movd */
6312 case 0x660f6f: /* movdqa */
6313 case 0xf30f6f: /* movdqu */
6314 case 0x660f70: /* pshufd */
6315 case 0xf20f70: /* pshuflw */
6316 case 0xf30f70: /* pshufhw */
6317 case 0x660f74: /* pcmpeqb */
6318 case 0x660f75: /* pcmpeqw */
6319 case 0x660f76: /* pcmpeql */
6320 case 0x660f7c: /* haddpd */
6321 case 0xf20f7c: /* haddps */
6322 case 0x660f7d: /* hsubpd */
6323 case 0xf20f7d: /* hsubps */
6324 case 0xf30f7e: /* movq */
6325 case 0x0fc2: /* cmpps */
6326 case 0x660fc2: /* cmppd */
6327 case 0xf20fc2: /* cmpsd */
6328 case 0xf30fc2: /* cmpss */
6329 case 0x660fc4: /* pinsrw */
6330 case 0x0fc6: /* shufps */
6331 case 0x660fc6: /* shufpd */
6332 case 0x660fd0: /* addsubpd */
6333 case 0xf20fd0: /* addsubps */
6334 case 0x660fd1: /* psrlw */
6335 case 0x660fd2: /* psrld */
6336 case 0x660fd3: /* psrlq */
6337 case 0x660fd4: /* paddq */
6338 case 0x660fd5: /* pmullw */
6339 case 0xf30fd6: /* movq2dq */
6340 case 0x660fd8: /* psubusb */
6341 case 0x660fd9: /* psubusw */
6342 case 0x660fda: /* pminub */
6343 case 0x660fdb: /* pand */
6344 case 0x660fdc: /* paddusb */
6345 case 0x660fdd: /* paddusw */
6346 case 0x660fde: /* pmaxub */
6347 case 0x660fdf: /* pandn */
6348 case 0x660fe0: /* pavgb */
6349 case 0x660fe1: /* psraw */
6350 case 0x660fe2: /* psrad */
6351 case 0x660fe3: /* pavgw */
6352 case 0x660fe4: /* pmulhuw */
6353 case 0x660fe5: /* pmulhw */
6354 case 0x660fe6: /* cvttpd2dq */
6355 case 0xf20fe6: /* cvtpd2dq */
6356 case 0xf30fe6: /* cvtdq2pd */
6357 case 0x660fe8: /* psubsb */
6358 case 0x660fe9: /* psubsw */
6359 case 0x660fea: /* pminsw */
6360 case 0x660feb: /* por */
6361 case 0x660fec: /* paddsb */
6362 case 0x660fed: /* paddsw */
6363 case 0x660fee: /* pmaxsw */
6364 case 0x660fef: /* pxor */
6365 case 0x660ff0: /* lddqu */
6366 case 0x660ff1: /* psllw */
6367 case 0x660ff2: /* pslld */
6368 case 0x660ff3: /* psllq */
6369 case 0x660ff4: /* pmuludq */
6370 case 0x660ff5: /* pmaddwd */
6371 case 0x660ff6: /* psadbw */
6372 case 0x660ff8: /* psubb */
6373 case 0x660ff9: /* psubw */
6374 case 0x660ffa: /* psubl */
6375 case 0x660ffb: /* psubq */
6376 case 0x660ffc: /* paddb */
6377 case 0x660ffd: /* paddw */
6378 case 0x660ffe: /* paddl */
6379 if (i386_record_modrm (&ir))
6382 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
6384 record_arch_list_add_reg (ir.regcache,
6385 I387_XMM0_REGNUM (tdep) + ir.reg);
6386 if ((opcode & 0xfffffffc) == 0x660f3a60)
6387 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6390 case 0x0f11: /* movups */
6391 case 0x660f11: /* movupd */
6392 case 0xf30f11: /* movss */
6393 case 0xf20f11: /* movsd */
6394 case 0x0f13: /* movlps */
6395 case 0x660f13: /* movlpd */
6396 case 0x0f17: /* movhps */
6397 case 0x660f17: /* movhpd */
6398 case 0x0f29: /* movaps */
6399 case 0x660f29: /* movapd */
6400 case 0x660f3a14: /* pextrb */
6401 case 0x660f3a15: /* pextrw */
6402 case 0x660f3a16: /* pextrd pextrq */
6403 case 0x660f3a17: /* extractps */
6404 case 0x660f7f: /* movdqa */
6405 case 0xf30f7f: /* movdqu */
6406 if (i386_record_modrm (&ir))
6410 if (opcode == 0x0f13 || opcode == 0x660f13
6411 || opcode == 0x0f17 || opcode == 0x660f17)
6414 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
6416 record_arch_list_add_reg (ir.regcache,
6417 I387_XMM0_REGNUM (tdep) + ir.rm);
6439 if (i386_record_lea_modrm (&ir))
6444 case 0x0f2b: /* movntps */
6445 case 0x660f2b: /* movntpd */
6446 case 0x0fe7: /* movntq */
6447 case 0x660fe7: /* movntdq */
6450 if (opcode == 0x0fe7)
6454 if (i386_record_lea_modrm (&ir))
6458 case 0xf30f2c: /* cvttss2si */
6459 case 0xf20f2c: /* cvttsd2si */
6460 case 0xf30f2d: /* cvtss2si */
6461 case 0xf20f2d: /* cvtsd2si */
6462 case 0xf20f38f0: /* crc32 */
6463 case 0xf20f38f1: /* crc32 */
6464 case 0x0f50: /* movmskps */
6465 case 0x660f50: /* movmskpd */
6466 case 0x0fc5: /* pextrw */
6467 case 0x660fc5: /* pextrw */
6468 case 0x0fd7: /* pmovmskb */
6469 case 0x660fd7: /* pmovmskb */
6470 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6473 case 0x0f3800: /* pshufb */
6474 case 0x0f3801: /* phaddw */
6475 case 0x0f3802: /* phaddd */
6476 case 0x0f3803: /* phaddsw */
6477 case 0x0f3804: /* pmaddubsw */
6478 case 0x0f3805: /* phsubw */
6479 case 0x0f3806: /* phsubd */
6480 case 0x0f3807: /* phaddsw */
6481 case 0x0f3808: /* psignb */
6482 case 0x0f3809: /* psignw */
6483 case 0x0f380a: /* psignd */
6484 case 0x0f380b: /* pmulhrsw */
6485 case 0x0f381c: /* pabsb */
6486 case 0x0f381d: /* pabsw */
6487 case 0x0f381e: /* pabsd */
6488 case 0x0f382b: /* packusdw */
6489 case 0x0f3830: /* pmovzxbw */
6490 case 0x0f3831: /* pmovzxbd */
6491 case 0x0f3832: /* pmovzxbq */
6492 case 0x0f3833: /* pmovzxwd */
6493 case 0x0f3834: /* pmovzxwq */
6494 case 0x0f3835: /* pmovzxdq */
6495 case 0x0f3837: /* pcmpgtq */
6496 case 0x0f3838: /* pminsb */
6497 case 0x0f3839: /* pminsd */
6498 case 0x0f383a: /* pminuw */
6499 case 0x0f383b: /* pminud */
6500 case 0x0f383c: /* pmaxsb */
6501 case 0x0f383d: /* pmaxsd */
6502 case 0x0f383e: /* pmaxuw */
6503 case 0x0f383f: /* pmaxud */
6504 case 0x0f3840: /* pmulld */
6505 case 0x0f3841: /* phminposuw */
6506 case 0x0f3a0f: /* palignr */
6507 case 0x0f60: /* punpcklbw */
6508 case 0x0f61: /* punpcklwd */
6509 case 0x0f62: /* punpckldq */
6510 case 0x0f63: /* packsswb */
6511 case 0x0f64: /* pcmpgtb */
6512 case 0x0f65: /* pcmpgtw */
6513 case 0x0f66: /* pcmpgtl */
6514 case 0x0f67: /* packuswb */
6515 case 0x0f68: /* punpckhbw */
6516 case 0x0f69: /* punpckhwd */
6517 case 0x0f6a: /* punpckhdq */
6518 case 0x0f6b: /* packssdw */
6519 case 0x0f6e: /* movd */
6520 case 0x0f6f: /* movq */
6521 case 0x0f70: /* pshufw */
6522 case 0x0f74: /* pcmpeqb */
6523 case 0x0f75: /* pcmpeqw */
6524 case 0x0f76: /* pcmpeql */
6525 case 0x0fc4: /* pinsrw */
6526 case 0x0fd1: /* psrlw */
6527 case 0x0fd2: /* psrld */
6528 case 0x0fd3: /* psrlq */
6529 case 0x0fd4: /* paddq */
6530 case 0x0fd5: /* pmullw */
6531 case 0xf20fd6: /* movdq2q */
6532 case 0x0fd8: /* psubusb */
6533 case 0x0fd9: /* psubusw */
6534 case 0x0fda: /* pminub */
6535 case 0x0fdb: /* pand */
6536 case 0x0fdc: /* paddusb */
6537 case 0x0fdd: /* paddusw */
6538 case 0x0fde: /* pmaxub */
6539 case 0x0fdf: /* pandn */
6540 case 0x0fe0: /* pavgb */
6541 case 0x0fe1: /* psraw */
6542 case 0x0fe2: /* psrad */
6543 case 0x0fe3: /* pavgw */
6544 case 0x0fe4: /* pmulhuw */
6545 case 0x0fe5: /* pmulhw */
6546 case 0x0fe8: /* psubsb */
6547 case 0x0fe9: /* psubsw */
6548 case 0x0fea: /* pminsw */
6549 case 0x0feb: /* por */
6550 case 0x0fec: /* paddsb */
6551 case 0x0fed: /* paddsw */
6552 case 0x0fee: /* pmaxsw */
6553 case 0x0fef: /* pxor */
6554 case 0x0ff1: /* psllw */
6555 case 0x0ff2: /* pslld */
6556 case 0x0ff3: /* psllq */
6557 case 0x0ff4: /* pmuludq */
6558 case 0x0ff5: /* pmaddwd */
6559 case 0x0ff6: /* psadbw */
6560 case 0x0ff8: /* psubb */
6561 case 0x0ff9: /* psubw */
6562 case 0x0ffa: /* psubl */
6563 case 0x0ffb: /* psubq */
6564 case 0x0ffc: /* paddb */
6565 case 0x0ffd: /* paddw */
6566 case 0x0ffe: /* paddl */
6567 if (i386_record_modrm (&ir))
6569 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
6571 record_arch_list_add_reg (ir.regcache,
6572 I387_MM0_REGNUM (tdep) + ir.reg);
6575 case 0x0f71: /* psllw */
6576 case 0x0f72: /* pslld */
6577 case 0x0f73: /* psllq */
6578 if (i386_record_modrm (&ir))
6580 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
6582 record_arch_list_add_reg (ir.regcache,
6583 I387_MM0_REGNUM (tdep) + ir.rm);
6586 case 0x660f71: /* psllw */
6587 case 0x660f72: /* pslld */
6588 case 0x660f73: /* psllq */
6589 if (i386_record_modrm (&ir))
6592 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
6594 record_arch_list_add_reg (ir.regcache,
6595 I387_XMM0_REGNUM (tdep) + ir.rm);
6598 case 0x0f7e: /* movd */
6599 case 0x660f7e: /* movd */
6600 if (i386_record_modrm (&ir))
6603 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6610 if (i386_record_lea_modrm (&ir))
6615 case 0x0f7f: /* movq */
6616 if (i386_record_modrm (&ir))
6620 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
6622 record_arch_list_add_reg (ir.regcache,
6623 I387_MM0_REGNUM (tdep) + ir.rm);
6628 if (i386_record_lea_modrm (&ir))
6633 case 0xf30fb8: /* popcnt */
6634 if (i386_record_modrm (&ir))
6636 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
6637 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6640 case 0x660fd6: /* movq */
6641 if (i386_record_modrm (&ir))
6646 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
6648 record_arch_list_add_reg (ir.regcache,
6649 I387_XMM0_REGNUM (tdep) + ir.rm);
6654 if (i386_record_lea_modrm (&ir))
6659 case 0x660f3817: /* ptest */
6660 case 0x0f2e: /* ucomiss */
6661 case 0x660f2e: /* ucomisd */
6662 case 0x0f2f: /* comiss */
6663 case 0x660f2f: /* comisd */
6664 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6667 case 0x0ff7: /* maskmovq */
6668 regcache_raw_read_unsigned (ir.regcache,
6669 ir.regmap[X86_RECORD_REDI_REGNUM],
6671 if (record_arch_list_add_mem (addr, 64))
6675 case 0x660ff7: /* maskmovdqu */
6676 regcache_raw_read_unsigned (ir.regcache,
6677 ir.regmap[X86_RECORD_REDI_REGNUM],
6679 if (record_arch_list_add_mem (addr, 128))
6694 /* In the future, maybe still need to deal with need_dasm. */
6695 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
6696 if (record_arch_list_add_end ())
6702 printf_unfiltered (_("Process record does not support instruction 0x%02x "
6703 "at address %s.\n"),
6704 (unsigned int) (opcode),
6705 paddress (gdbarch, ir.orig_addr));
6709 static const int i386_record_regmap[] =
6711 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
6712 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
6713 0, 0, 0, 0, 0, 0, 0, 0,
6714 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
6715 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
6718 /* Check that the given address appears suitable for a fast
6719 tracepoint, which on x86 means that we need an instruction of at
6720 least 5 bytes, so that we can overwrite it with a 4-byte-offset
6721 jump and not have to worry about program jumps to an address in the
6722 middle of the tracepoint jump. Returns 1 if OK, and writes a size
6723 of instruction to replace, and 0 if not, plus an explanatory
6727 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch,
6728 CORE_ADDR addr, int *isize, char **msg)
6731 static struct ui_file *gdb_null = NULL;
6733 /* This is based on the target agent using a 4-byte relative jump.
6734 Alternate future possibilities include 8-byte offset for x86-84,
6735 or 3-byte jumps if the program has trampoline space close by. */
6738 /* Dummy file descriptor for the disassembler. */
6740 gdb_null = ui_file_new ();
6742 /* Check for fit. */
6743 len = gdb_print_insn (gdbarch, addr, gdb_null, NULL);
6746 /* Return a bit of target-specific detail to add to the caller's
6747 generic failure message. */
6749 *msg = xstrprintf (_("; instruction is only %d bytes long, need at least %d bytes for the jump"),
6762 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
6763 struct tdesc_arch_data *tdesc_data)
6765 const struct target_desc *tdesc = tdep->tdesc;
6766 const struct tdesc_feature *feature_core;
6767 const struct tdesc_feature *feature_sse, *feature_avx;
6768 int i, num_regs, valid_p;
6770 if (! tdesc_has_registers (tdesc))
6773 /* Get core registers. */
6774 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
6775 if (feature_core == NULL)
6778 /* Get SSE registers. */
6779 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
6781 /* Try AVX registers. */
6782 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
6786 /* The XCR0 bits. */
6789 /* AVX register description requires SSE register description. */
6793 tdep->xcr0 = I386_XSTATE_AVX_MASK;
6795 /* It may have been set by OSABI initialization function. */
6796 if (tdep->num_ymm_regs == 0)
6798 tdep->ymmh_register_names = i386_ymmh_names;
6799 tdep->num_ymm_regs = 8;
6800 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
6803 for (i = 0; i < tdep->num_ymm_regs; i++)
6804 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
6805 tdep->ymm0h_regnum + i,
6806 tdep->ymmh_register_names[i]);
6808 else if (feature_sse)
6809 tdep->xcr0 = I386_XSTATE_SSE_MASK;
6812 tdep->xcr0 = I386_XSTATE_X87_MASK;
6813 tdep->num_xmm_regs = 0;
6816 num_regs = tdep->num_core_regs;
6817 for (i = 0; i < num_regs; i++)
6818 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
6819 tdep->register_names[i]);
6823 /* Need to include %mxcsr, so add one. */
6824 num_regs += tdep->num_xmm_regs + 1;
6825 for (; i < num_regs; i++)
6826 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
6827 tdep->register_names[i]);
6834 static struct gdbarch *
6835 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
6837 struct gdbarch_tdep *tdep;
6838 struct gdbarch *gdbarch;
6839 struct tdesc_arch_data *tdesc_data;
6840 const struct target_desc *tdesc;
6844 /* If there is already a candidate, use it. */
6845 arches = gdbarch_list_lookup_by_info (arches, &info);
6847 return arches->gdbarch;
6849 /* Allocate space for the new architecture. */
6850 tdep = XCALLOC (1, struct gdbarch_tdep);
6851 gdbarch = gdbarch_alloc (&info, tdep);
6853 /* General-purpose registers. */
6854 tdep->gregset = NULL;
6855 tdep->gregset_reg_offset = NULL;
6856 tdep->gregset_num_regs = I386_NUM_GREGS;
6857 tdep->sizeof_gregset = 0;
6859 /* Floating-point registers. */
6860 tdep->fpregset = NULL;
6861 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
6863 tdep->xstateregset = NULL;
6865 /* The default settings include the FPU registers, the MMX registers
6866 and the SSE registers. This can be overridden for a specific ABI
6867 by adjusting the members `st0_regnum', `mm0_regnum' and
6868 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
6869 will show up in the output of "info all-registers". */
6871 tdep->st0_regnum = I386_ST0_REGNUM;
6873 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
6874 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
6876 tdep->jb_pc_offset = -1;
6877 tdep->struct_return = pcc_struct_return;
6878 tdep->sigtramp_start = 0;
6879 tdep->sigtramp_end = 0;
6880 tdep->sigtramp_p = i386_sigtramp_p;
6881 tdep->sigcontext_addr = NULL;
6882 tdep->sc_reg_offset = NULL;
6883 tdep->sc_pc_offset = -1;
6884 tdep->sc_sp_offset = -1;
6886 tdep->xsave_xcr0_offset = -1;
6888 tdep->record_regmap = i386_record_regmap;
6890 /* The format used for `long double' on almost all i386 targets is
6891 the i387 extended floating-point format. In fact, of all targets
6892 in the GCC 2.95 tree, only OSF/1 does it different, and insists
6893 on having a `long double' that's not `long' at all. */
6894 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
6896 /* Although the i387 extended floating-point has only 80 significant
6897 bits, a `long double' actually takes up 96, probably to enforce
6899 set_gdbarch_long_double_bit (gdbarch, 96);
6901 /* Register numbers of various important registers. */
6902 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
6903 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
6904 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
6905 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
6907 /* NOTE: kettenis/20040418: GCC does have two possible register
6908 numbering schemes on the i386: dbx and SVR4. These schemes
6909 differ in how they number %ebp, %esp, %eflags, and the
6910 floating-point registers, and are implemented by the arrays
6911 dbx_register_map[] and svr4_dbx_register_map in
6912 gcc/config/i386.c. GCC also defines a third numbering scheme in
6913 gcc/config/i386.c, which it designates as the "default" register
6914 map used in 64bit mode. This last register numbering scheme is
6915 implemented in dbx64_register_map, and is used for AMD64; see
6918 Currently, each GCC i386 target always uses the same register
6919 numbering scheme across all its supported debugging formats
6920 i.e. SDB (COFF), stabs and DWARF 2. This is because
6921 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
6922 DBX_REGISTER_NUMBER macro which is defined by each target's
6923 respective config header in a manner independent of the requested
6924 output debugging format.
6926 This does not match the arrangement below, which presumes that
6927 the SDB and stabs numbering schemes differ from the DWARF and
6928 DWARF 2 ones. The reason for this arrangement is that it is
6929 likely to get the numbering scheme for the target's
6930 default/native debug format right. For targets where GCC is the
6931 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
6932 targets where the native toolchain uses a different numbering
6933 scheme for a particular debug format (stabs-in-ELF on Solaris)
6934 the defaults below will have to be overridden, like
6935 i386_elf_init_abi() does. */
6937 /* Use the dbx register numbering scheme for stabs and COFF. */
6938 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
6939 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
6941 /* Use the SVR4 register numbering scheme for DWARF 2. */
6942 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
6944 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
6945 be in use on any of the supported i386 targets. */
6947 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
6949 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
6951 /* Call dummy code. */
6952 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
6954 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
6955 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
6956 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
6958 set_gdbarch_return_value (gdbarch, i386_return_value);
6960 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
6962 /* Stack grows downward. */
6963 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
6965 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc);
6966 set_gdbarch_decr_pc_after_break (gdbarch, 1);
6967 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
6969 set_gdbarch_frame_args_skip (gdbarch, 8);
6971 set_gdbarch_print_insn (gdbarch, i386_print_insn);
6973 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
6975 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
6977 /* Add the i386 register groups. */
6978 i386_add_reggroups (gdbarch);
6979 tdep->register_reggroup_p = i386_register_reggroup_p;
6981 /* Helper for function argument information. */
6982 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
6984 /* Hook the function epilogue frame unwinder. This unwinder is
6985 appended to the list first, so that it supercedes the Dwarf
6986 unwinder in function epilogues (where the Dwarf unwinder
6987 currently fails). */
6988 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
6990 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
6991 to the list before the prologue-based unwinders, so that Dwarf
6992 CFI info will be used if it is available. */
6993 dwarf2_append_unwinders (gdbarch);
6995 frame_base_set_default (gdbarch, &i386_frame_base);
6997 /* Pseudo registers may be changed by amd64_init_abi. */
6998 set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read);
6999 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
7001 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
7002 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
7004 /* Override the normal target description method to make the AVX
7005 upper halves anonymous. */
7006 set_gdbarch_register_name (gdbarch, i386_register_name);
7008 /* Even though the default ABI only includes general-purpose registers,
7009 floating-point registers and the SSE registers, we have to leave a
7010 gap for the upper AVX registers. */
7011 set_gdbarch_num_regs (gdbarch, I386_AVX_NUM_REGS);
7013 /* Get the x86 target description from INFO. */
7014 tdesc = info.target_desc;
7015 if (! tdesc_has_registers (tdesc))
7017 tdep->tdesc = tdesc;
7019 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
7020 tdep->register_names = i386_register_names;
7022 /* No upper YMM registers. */
7023 tdep->ymmh_register_names = NULL;
7024 tdep->ymm0h_regnum = -1;
7026 tdep->num_byte_regs = 8;
7027 tdep->num_word_regs = 8;
7028 tdep->num_dword_regs = 0;
7029 tdep->num_mmx_regs = 8;
7030 tdep->num_ymm_regs = 0;
7032 tdesc_data = tdesc_data_alloc ();
7034 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
7036 /* Hook in ABI-specific overrides, if they have been registered. */
7037 info.tdep_info = (void *) tdesc_data;
7038 gdbarch_init_osabi (info, gdbarch);
7040 if (!i386_validate_tdesc_p (tdep, tdesc_data))
7042 tdesc_data_cleanup (tdesc_data);
7044 gdbarch_free (gdbarch);
7048 /* Wire in pseudo registers. Number of pseudo registers may be
7050 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
7051 + tdep->num_word_regs
7052 + tdep->num_dword_regs
7053 + tdep->num_mmx_regs
7054 + tdep->num_ymm_regs));
7056 /* Target description may be changed. */
7057 tdesc = tdep->tdesc;
7059 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
7061 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7062 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
7064 /* Make %al the first pseudo-register. */
7065 tdep->al_regnum = gdbarch_num_regs (gdbarch);
7066 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
7068 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
7069 if (tdep->num_dword_regs)
7071 /* Support dword pseudo-registesr if it hasn't been disabled, */
7072 tdep->eax_regnum = ymm0_regnum;
7073 ymm0_regnum += tdep->num_dword_regs;
7076 tdep->eax_regnum = -1;
7078 mm0_regnum = ymm0_regnum;
7079 if (tdep->num_ymm_regs)
7081 /* Support YMM pseudo-registesr if it is available, */
7082 tdep->ymm0_regnum = ymm0_regnum;
7083 mm0_regnum += tdep->num_ymm_regs;
7086 tdep->ymm0_regnum = -1;
7088 if (tdep->num_mmx_regs != 0)
7090 /* Support MMX pseudo-registesr if MMX hasn't been disabled, */
7091 tdep->mm0_regnum = mm0_regnum;
7094 tdep->mm0_regnum = -1;
7096 /* Hook in the legacy prologue-based unwinders last (fallback). */
7097 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
7098 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
7100 /* If we have a register mapping, enable the generic core file
7101 support, unless it has already been enabled. */
7102 if (tdep->gregset_reg_offset
7103 && !gdbarch_regset_from_core_section_p (gdbarch))
7104 set_gdbarch_regset_from_core_section (gdbarch,
7105 i386_regset_from_core_section);
7107 set_gdbarch_skip_permanent_breakpoint (gdbarch,
7108 i386_skip_permanent_breakpoint);
7110 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
7111 i386_fast_tracepoint_valid_at);
7116 static enum gdb_osabi
7117 i386_coff_osabi_sniffer (bfd *abfd)
7119 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
7120 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
7121 return GDB_OSABI_GO32;
7123 return GDB_OSABI_UNKNOWN;
7127 /* Provide a prototype to silence -Wmissing-prototypes. */
7128 void _initialize_i386_tdep (void);
7131 _initialize_i386_tdep (void)
7133 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
7135 /* Add the variable that controls the disassembly flavor. */
7136 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
7137 &disassembly_flavor, _("\
7138 Set the disassembly flavor."), _("\
7139 Show the disassembly flavor."), _("\
7140 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7142 NULL, /* FIXME: i18n: */
7143 &setlist, &showlist);
7145 /* Add the variable that controls the convention for returning
7147 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
7148 &struct_convention, _("\
7149 Set the convention for returning small structs."), _("\
7150 Show the convention for returning small structs."), _("\
7151 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7154 NULL, /* FIXME: i18n: */
7155 &setlist, &showlist);
7157 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
7158 i386_coff_osabi_sniffer);
7160 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
7161 i386_svr4_init_abi);
7162 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
7163 i386_go32_init_abi);
7165 /* Initialize the i386-specific register groups. */
7166 i386_init_reggroups ();
7168 /* Initialize the standard target descriptions. */
7169 initialize_tdesc_i386 ();
7170 initialize_tdesc_i386_mmx ();
7171 initialize_tdesc_i386_avx ();
7173 /* Tell remote stub that we support XML target description. */
7174 register_remote_support_xml ("i386");