1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
38 #include "reggroups.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "x86-xstate.h"
52 #include "record-full.h"
53 #include "features/i386/i386.c"
54 #include "features/i386/i386-avx.c"
55 #include "features/i386/i386-mpx.c"
56 #include "features/i386/i386-avx-mpx.c"
57 #include "features/i386/i386-avx512.c"
58 #include "features/i386/i386-mmx.c"
63 #include "stap-probe.h"
64 #include "user-regs.h"
65 #include "cli/cli-utils.h"
66 #include "expression.h"
67 #include "parser-defs.h"
73 static const char *i386_register_names[] =
75 "eax", "ecx", "edx", "ebx",
76 "esp", "ebp", "esi", "edi",
77 "eip", "eflags", "cs", "ss",
78 "ds", "es", "fs", "gs",
79 "st0", "st1", "st2", "st3",
80 "st4", "st5", "st6", "st7",
81 "fctrl", "fstat", "ftag", "fiseg",
82 "fioff", "foseg", "fooff", "fop",
83 "xmm0", "xmm1", "xmm2", "xmm3",
84 "xmm4", "xmm5", "xmm6", "xmm7",
88 static const char *i386_zmm_names[] =
90 "zmm0", "zmm1", "zmm2", "zmm3",
91 "zmm4", "zmm5", "zmm6", "zmm7"
94 static const char *i386_zmmh_names[] =
96 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
97 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
100 static const char *i386_k_names[] =
102 "k0", "k1", "k2", "k3",
103 "k4", "k5", "k6", "k7"
106 static const char *i386_ymm_names[] =
108 "ymm0", "ymm1", "ymm2", "ymm3",
109 "ymm4", "ymm5", "ymm6", "ymm7",
112 static const char *i386_ymmh_names[] =
114 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
115 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
118 static const char *i386_mpx_names[] =
120 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
123 /* Register names for MPX pseudo-registers. */
125 static const char *i386_bnd_names[] =
127 "bnd0", "bnd1", "bnd2", "bnd3"
130 /* Register names for MMX pseudo-registers. */
132 static const char *i386_mmx_names[] =
134 "mm0", "mm1", "mm2", "mm3",
135 "mm4", "mm5", "mm6", "mm7"
138 /* Register names for byte pseudo-registers. */
140 static const char *i386_byte_names[] =
142 "al", "cl", "dl", "bl",
143 "ah", "ch", "dh", "bh"
146 /* Register names for word pseudo-registers. */
148 static const char *i386_word_names[] =
150 "ax", "cx", "dx", "bx",
154 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
155 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
156 we have 16 upper ZMM regs that have to be handled differently. */
158 const int num_lower_zmm_regs = 16;
163 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
165 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
166 int mm0_regnum = tdep->mm0_regnum;
171 regnum -= mm0_regnum;
172 return regnum >= 0 && regnum < tdep->num_mmx_regs;
178 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
180 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
182 regnum -= tdep->al_regnum;
183 return regnum >= 0 && regnum < tdep->num_byte_regs;
189 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
191 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
193 regnum -= tdep->ax_regnum;
194 return regnum >= 0 && regnum < tdep->num_word_regs;
197 /* Dword register? */
200 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
202 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
203 int eax_regnum = tdep->eax_regnum;
208 regnum -= eax_regnum;
209 return regnum >= 0 && regnum < tdep->num_dword_regs;
212 /* AVX512 register? */
215 i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum)
217 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
218 int zmm0h_regnum = tdep->zmm0h_regnum;
220 if (zmm0h_regnum < 0)
223 regnum -= zmm0h_regnum;
224 return regnum >= 0 && regnum < tdep->num_zmm_regs;
228 i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum)
230 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
231 int zmm0_regnum = tdep->zmm0_regnum;
236 regnum -= zmm0_regnum;
237 return regnum >= 0 && regnum < tdep->num_zmm_regs;
241 i386_k_regnum_p (struct gdbarch *gdbarch, int regnum)
243 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
244 int k0_regnum = tdep->k0_regnum;
250 return regnum >= 0 && regnum < I387_NUM_K_REGS;
254 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
256 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
257 int ymm0h_regnum = tdep->ymm0h_regnum;
259 if (ymm0h_regnum < 0)
262 regnum -= ymm0h_regnum;
263 return regnum >= 0 && regnum < tdep->num_ymm_regs;
269 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
271 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
272 int ymm0_regnum = tdep->ymm0_regnum;
277 regnum -= ymm0_regnum;
278 return regnum >= 0 && regnum < tdep->num_ymm_regs;
282 i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
284 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
285 int ymm16h_regnum = tdep->ymm16h_regnum;
287 if (ymm16h_regnum < 0)
290 regnum -= ymm16h_regnum;
291 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
295 i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
297 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
298 int ymm16_regnum = tdep->ymm16_regnum;
300 if (ymm16_regnum < 0)
303 regnum -= ymm16_regnum;
304 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
310 i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum)
312 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
313 int bnd0_regnum = tdep->bnd0_regnum;
318 regnum -= bnd0_regnum;
319 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
325 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
327 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
328 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
330 if (num_xmm_regs == 0)
333 regnum -= I387_XMM0_REGNUM (tdep);
334 return regnum >= 0 && regnum < num_xmm_regs;
337 /* XMM_512 register? */
340 i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
342 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
343 int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep);
345 if (num_xmm_avx512_regs == 0)
348 regnum -= I387_XMM16_REGNUM (tdep);
349 return regnum >= 0 && regnum < num_xmm_avx512_regs;
353 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
355 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
357 if (I387_NUM_XMM_REGS (tdep) == 0)
360 return (regnum == I387_MXCSR_REGNUM (tdep));
366 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
368 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
370 if (I387_ST0_REGNUM (tdep) < 0)
373 return (I387_ST0_REGNUM (tdep) <= regnum
374 && regnum < I387_FCTRL_REGNUM (tdep));
378 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
380 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
382 if (I387_ST0_REGNUM (tdep) < 0)
385 return (I387_FCTRL_REGNUM (tdep) <= regnum
386 && regnum < I387_XMM0_REGNUM (tdep));
389 /* BNDr (raw) register? */
392 i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum)
394 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
396 if (I387_BND0R_REGNUM (tdep) < 0)
399 regnum -= tdep->bnd0r_regnum;
400 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
403 /* BND control register? */
406 i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum)
408 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
410 if (I387_BNDCFGU_REGNUM (tdep) < 0)
413 regnum -= I387_BNDCFGU_REGNUM (tdep);
414 return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS;
417 /* Return the name of register REGNUM, or the empty string if it is
418 an anonymous register. */
421 i386_register_name (struct gdbarch *gdbarch, int regnum)
423 /* Hide the upper YMM registers. */
424 if (i386_ymmh_regnum_p (gdbarch, regnum))
427 /* Hide the upper YMM16-31 registers. */
428 if (i386_ymmh_avx512_regnum_p (gdbarch, regnum))
431 /* Hide the upper ZMM registers. */
432 if (i386_zmmh_regnum_p (gdbarch, regnum))
435 return tdesc_register_name (gdbarch, regnum);
438 /* Return the name of register REGNUM. */
441 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
443 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
444 if (i386_bnd_regnum_p (gdbarch, regnum))
445 return i386_bnd_names[regnum - tdep->bnd0_regnum];
446 if (i386_mmx_regnum_p (gdbarch, regnum))
447 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
448 else if (i386_ymm_regnum_p (gdbarch, regnum))
449 return i386_ymm_names[regnum - tdep->ymm0_regnum];
450 else if (i386_zmm_regnum_p (gdbarch, regnum))
451 return i386_zmm_names[regnum - tdep->zmm0_regnum];
452 else if (i386_byte_regnum_p (gdbarch, regnum))
453 return i386_byte_names[regnum - tdep->al_regnum];
454 else if (i386_word_regnum_p (gdbarch, regnum))
455 return i386_word_names[regnum - tdep->ax_regnum];
457 internal_error (__FILE__, __LINE__, _("invalid regnum"));
460 /* Convert a dbx register number REG to the appropriate register
461 number used by GDB. */
464 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
466 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
468 /* This implements what GCC calls the "default" register map
469 (dbx_register_map[]). */
471 if (reg >= 0 && reg <= 7)
473 /* General-purpose registers. The debug info calls %ebp
474 register 4, and %esp register 5. */
481 else if (reg >= 12 && reg <= 19)
483 /* Floating-point registers. */
484 return reg - 12 + I387_ST0_REGNUM (tdep);
486 else if (reg >= 21 && reg <= 28)
489 int ymm0_regnum = tdep->ymm0_regnum;
492 && i386_xmm_regnum_p (gdbarch, reg))
493 return reg - 21 + ymm0_regnum;
495 return reg - 21 + I387_XMM0_REGNUM (tdep);
497 else if (reg >= 29 && reg <= 36)
500 return reg - 29 + I387_MM0_REGNUM (tdep);
503 /* This will hopefully provoke a warning. */
504 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
507 /* Convert SVR4 DWARF register number REG to the appropriate register number
511 i386_svr4_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
513 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
515 /* This implements the GCC register map that tries to be compatible
516 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
518 /* The SVR4 register numbering includes %eip and %eflags, and
519 numbers the floating point registers differently. */
520 if (reg >= 0 && reg <= 9)
522 /* General-purpose registers. */
525 else if (reg >= 11 && reg <= 18)
527 /* Floating-point registers. */
528 return reg - 11 + I387_ST0_REGNUM (tdep);
530 else if (reg >= 21 && reg <= 36)
532 /* The SSE and MMX registers have the same numbers as with dbx. */
533 return i386_dbx_reg_to_regnum (gdbarch, reg);
538 case 37: return I387_FCTRL_REGNUM (tdep);
539 case 38: return I387_FSTAT_REGNUM (tdep);
540 case 39: return I387_MXCSR_REGNUM (tdep);
541 case 40: return I386_ES_REGNUM;
542 case 41: return I386_CS_REGNUM;
543 case 42: return I386_SS_REGNUM;
544 case 43: return I386_DS_REGNUM;
545 case 44: return I386_FS_REGNUM;
546 case 45: return I386_GS_REGNUM;
552 /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return
553 num_regs + num_pseudo_regs for other debug formats. */
556 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
558 int regnum = i386_svr4_dwarf_reg_to_regnum (gdbarch, reg);
561 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
567 /* This is the variable that is set with "set disassembly-flavor", and
568 its legitimate values. */
569 static const char att_flavor[] = "att";
570 static const char intel_flavor[] = "intel";
571 static const char *const valid_flavors[] =
577 static const char *disassembly_flavor = att_flavor;
580 /* Use the program counter to determine the contents and size of a
581 breakpoint instruction. Return a pointer to a string of bytes that
582 encode a breakpoint instruction, store the length of the string in
583 *LEN and optionally adjust *PC to point to the correct memory
584 location for inserting the breakpoint.
586 On the i386 we have a single breakpoint that fits in a single byte
587 and can be inserted anywhere.
589 This function is 64-bit safe. */
591 static const gdb_byte *
592 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
594 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */
596 *len = sizeof (break_insn);
600 /* Displaced instruction handling. */
602 /* Skip the legacy instruction prefixes in INSN.
603 Not all prefixes are valid for any particular insn
604 but we needn't care, the insn will fault if it's invalid.
605 The result is a pointer to the first opcode byte,
606 or NULL if we run off the end of the buffer. */
609 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
611 gdb_byte *end = insn + max_len;
617 case DATA_PREFIX_OPCODE:
618 case ADDR_PREFIX_OPCODE:
619 case CS_PREFIX_OPCODE:
620 case DS_PREFIX_OPCODE:
621 case ES_PREFIX_OPCODE:
622 case FS_PREFIX_OPCODE:
623 case GS_PREFIX_OPCODE:
624 case SS_PREFIX_OPCODE:
625 case LOCK_PREFIX_OPCODE:
626 case REPE_PREFIX_OPCODE:
627 case REPNE_PREFIX_OPCODE:
639 i386_absolute_jmp_p (const gdb_byte *insn)
641 /* jmp far (absolute address in operand). */
647 /* jump near, absolute indirect (/4). */
648 if ((insn[1] & 0x38) == 0x20)
651 /* jump far, absolute indirect (/5). */
652 if ((insn[1] & 0x38) == 0x28)
659 /* Return non-zero if INSN is a jump, zero otherwise. */
662 i386_jmp_p (const gdb_byte *insn)
664 /* jump short, relative. */
668 /* jump near, relative. */
672 return i386_absolute_jmp_p (insn);
676 i386_absolute_call_p (const gdb_byte *insn)
678 /* call far, absolute. */
684 /* Call near, absolute indirect (/2). */
685 if ((insn[1] & 0x38) == 0x10)
688 /* Call far, absolute indirect (/3). */
689 if ((insn[1] & 0x38) == 0x18)
697 i386_ret_p (const gdb_byte *insn)
701 case 0xc2: /* ret near, pop N bytes. */
702 case 0xc3: /* ret near */
703 case 0xca: /* ret far, pop N bytes. */
704 case 0xcb: /* ret far */
705 case 0xcf: /* iret */
714 i386_call_p (const gdb_byte *insn)
716 if (i386_absolute_call_p (insn))
719 /* call near, relative. */
726 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
727 length in bytes. Otherwise, return zero. */
730 i386_syscall_p (const gdb_byte *insn, int *lengthp)
732 /* Is it 'int $0x80'? */
733 if ((insn[0] == 0xcd && insn[1] == 0x80)
734 /* Or is it 'sysenter'? */
735 || (insn[0] == 0x0f && insn[1] == 0x34)
736 /* Or is it 'syscall'? */
737 || (insn[0] == 0x0f && insn[1] == 0x05))
746 /* The gdbarch insn_is_call method. */
749 i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
751 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
753 read_code (addr, buf, I386_MAX_INSN_LEN);
754 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
756 return i386_call_p (insn);
759 /* The gdbarch insn_is_ret method. */
762 i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
764 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
766 read_code (addr, buf, I386_MAX_INSN_LEN);
767 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
769 return i386_ret_p (insn);
772 /* The gdbarch insn_is_jump method. */
775 i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
777 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
779 read_code (addr, buf, I386_MAX_INSN_LEN);
780 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
782 return i386_jmp_p (insn);
785 /* Some kernels may run one past a syscall insn, so we have to cope.
786 Otherwise this is just simple_displaced_step_copy_insn. */
788 struct displaced_step_closure *
789 i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
790 CORE_ADDR from, CORE_ADDR to,
791 struct regcache *regs)
793 size_t len = gdbarch_max_insn_length (gdbarch);
794 gdb_byte *buf = (gdb_byte *) xmalloc (len);
796 read_memory (from, buf, len);
798 /* GDB may get control back after the insn after the syscall.
799 Presumably this is a kernel bug.
800 If this is a syscall, make sure there's a nop afterwards. */
805 insn = i386_skip_prefixes (buf, len);
806 if (insn != NULL && i386_syscall_p (insn, &syscall_length))
807 insn[syscall_length] = NOP_OPCODE;
810 write_memory (to, buf, len);
814 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
815 paddress (gdbarch, from), paddress (gdbarch, to));
816 displaced_step_dump_bytes (gdb_stdlog, buf, len);
819 return (struct displaced_step_closure *) buf;
822 /* Fix up the state of registers and memory after having single-stepped
823 a displaced instruction. */
826 i386_displaced_step_fixup (struct gdbarch *gdbarch,
827 struct displaced_step_closure *closure,
828 CORE_ADDR from, CORE_ADDR to,
829 struct regcache *regs)
831 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
833 /* The offset we applied to the instruction's address.
834 This could well be negative (when viewed as a signed 32-bit
835 value), but ULONGEST won't reflect that, so take care when
837 ULONGEST insn_offset = to - from;
839 /* Since we use simple_displaced_step_copy_insn, our closure is a
840 copy of the instruction. */
841 gdb_byte *insn = (gdb_byte *) closure;
842 /* The start of the insn, needed in case we see some prefixes. */
843 gdb_byte *insn_start = insn;
846 fprintf_unfiltered (gdb_stdlog,
847 "displaced: fixup (%s, %s), "
848 "insn = 0x%02x 0x%02x ...\n",
849 paddress (gdbarch, from), paddress (gdbarch, to),
852 /* The list of issues to contend with here is taken from
853 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
854 Yay for Free Software! */
856 /* Relocate the %eip, if necessary. */
858 /* The instruction recognizers we use assume any leading prefixes
859 have been skipped. */
861 /* This is the size of the buffer in closure. */
862 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
863 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
864 /* If there are too many prefixes, just ignore the insn.
865 It will fault when run. */
870 /* Except in the case of absolute or indirect jump or call
871 instructions, or a return instruction, the new eip is relative to
872 the displaced instruction; make it relative. Well, signal
873 handler returns don't need relocation either, but we use the
874 value of %eip to recognize those; see below. */
875 if (! i386_absolute_jmp_p (insn)
876 && ! i386_absolute_call_p (insn)
877 && ! i386_ret_p (insn))
882 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
884 /* A signal trampoline system call changes the %eip, resuming
885 execution of the main program after the signal handler has
886 returned. That makes them like 'return' instructions; we
887 shouldn't relocate %eip.
889 But most system calls don't, and we do need to relocate %eip.
891 Our heuristic for distinguishing these cases: if stepping
892 over the system call instruction left control directly after
893 the instruction, the we relocate --- control almost certainly
894 doesn't belong in the displaced copy. Otherwise, we assume
895 the instruction has put control where it belongs, and leave
896 it unrelocated. Goodness help us if there are PC-relative
898 if (i386_syscall_p (insn, &insn_len)
899 && orig_eip != to + (insn - insn_start) + insn_len
900 /* GDB can get control back after the insn after the syscall.
901 Presumably this is a kernel bug.
902 i386_displaced_step_copy_insn ensures its a nop,
903 we add one to the length for it. */
904 && orig_eip != to + (insn - insn_start) + insn_len + 1)
907 fprintf_unfiltered (gdb_stdlog,
908 "displaced: syscall changed %%eip; "
913 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
915 /* If we just stepped over a breakpoint insn, we don't backup
916 the pc on purpose; this is to match behaviour without
919 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
922 fprintf_unfiltered (gdb_stdlog,
924 "relocated %%eip from %s to %s\n",
925 paddress (gdbarch, orig_eip),
926 paddress (gdbarch, eip));
930 /* If the instruction was PUSHFL, then the TF bit will be set in the
931 pushed value, and should be cleared. We'll leave this for later,
932 since GDB already messes up the TF flag when stepping over a
935 /* If the instruction was a call, the return address now atop the
936 stack is the address following the copied instruction. We need
937 to make it the address following the original instruction. */
938 if (i386_call_p (insn))
942 const ULONGEST retaddr_len = 4;
944 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
945 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
946 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
947 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
950 fprintf_unfiltered (gdb_stdlog,
951 "displaced: relocated return addr at %s to %s\n",
952 paddress (gdbarch, esp),
953 paddress (gdbarch, retaddr));
958 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
960 target_write_memory (*to, buf, len);
965 i386_relocate_instruction (struct gdbarch *gdbarch,
966 CORE_ADDR *to, CORE_ADDR oldloc)
968 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
969 gdb_byte buf[I386_MAX_INSN_LEN];
970 int offset = 0, rel32, newrel;
972 gdb_byte *insn = buf;
974 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
976 insn_length = gdb_buffered_insn_length (gdbarch, insn,
977 I386_MAX_INSN_LEN, oldloc);
979 /* Get past the prefixes. */
980 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
982 /* Adjust calls with 32-bit relative addresses as push/jump, with
983 the address pushed being the location where the original call in
984 the user program would return to. */
987 gdb_byte push_buf[16];
988 unsigned int ret_addr;
990 /* Where "ret" in the original code will return to. */
991 ret_addr = oldloc + insn_length;
992 push_buf[0] = 0x68; /* pushq $... */
993 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
995 append_insns (to, 5, push_buf);
997 /* Convert the relative call to a relative jump. */
1000 /* Adjust the destination offset. */
1001 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1002 newrel = (oldloc - *to) + rel32;
1003 store_signed_integer (insn + 1, 4, byte_order, newrel);
1005 if (debug_displaced)
1006 fprintf_unfiltered (gdb_stdlog,
1007 "Adjusted insn rel32=%s at %s to"
1008 " rel32=%s at %s\n",
1009 hex_string (rel32), paddress (gdbarch, oldloc),
1010 hex_string (newrel), paddress (gdbarch, *to));
1012 /* Write the adjusted jump into its displaced location. */
1013 append_insns (to, 5, insn);
1017 /* Adjust jumps with 32-bit relative addresses. Calls are already
1019 if (insn[0] == 0xe9)
1021 /* Adjust conditional jumps. */
1022 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1027 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1028 newrel = (oldloc - *to) + rel32;
1029 store_signed_integer (insn + offset, 4, byte_order, newrel);
1030 if (debug_displaced)
1031 fprintf_unfiltered (gdb_stdlog,
1032 "Adjusted insn rel32=%s at %s to"
1033 " rel32=%s at %s\n",
1034 hex_string (rel32), paddress (gdbarch, oldloc),
1035 hex_string (newrel), paddress (gdbarch, *to));
1038 /* Write the adjusted instructions into their displaced
1040 append_insns (to, insn_length, buf);
1044 #ifdef I386_REGNO_TO_SYMMETRY
1045 #error "The Sequent Symmetry is no longer supported."
1048 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1049 and %esp "belong" to the calling function. Therefore these
1050 registers should be saved if they're going to be modified. */
1052 /* The maximum number of saved registers. This should include all
1053 registers mentioned above, and %eip. */
1054 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1056 struct i386_frame_cache
1064 /* Saved registers. */
1065 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
1070 /* Stack space reserved for local variables. */
1074 /* Allocate and initialize a frame cache. */
1076 static struct i386_frame_cache *
1077 i386_alloc_frame_cache (void)
1079 struct i386_frame_cache *cache;
1082 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
1087 cache->sp_offset = -4;
1090 /* Saved registers. We initialize these to -1 since zero is a valid
1091 offset (that's where %ebp is supposed to be stored). */
1092 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1093 cache->saved_regs[i] = -1;
1094 cache->saved_sp = 0;
1095 cache->saved_sp_reg = -1;
1096 cache->pc_in_eax = 0;
1098 /* Frameless until proven otherwise. */
1104 /* If the instruction at PC is a jump, return the address of its
1105 target. Otherwise, return PC. */
1108 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
1110 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1115 if (target_read_code (pc, &op, 1))
1122 op = read_code_unsigned_integer (pc + 1, 1, byte_order);
1128 /* Relative jump: if data16 == 0, disp32, else disp16. */
1131 delta = read_memory_integer (pc + 2, 2, byte_order);
1133 /* Include the size of the jmp instruction (including the
1139 delta = read_memory_integer (pc + 1, 4, byte_order);
1141 /* Include the size of the jmp instruction. */
1146 /* Relative jump, disp8 (ignore data16). */
1147 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
1149 delta += data16 + 2;
1156 /* Check whether PC points at a prologue for a function returning a
1157 structure or union. If so, it updates CACHE and returns the
1158 address of the first instruction after the code sequence that
1159 removes the "hidden" argument from the stack or CURRENT_PC,
1160 whichever is smaller. Otherwise, return PC. */
1163 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
1164 struct i386_frame_cache *cache)
1166 /* Functions that return a structure or union start with:
1169 xchgl %eax, (%esp) 0x87 0x04 0x24
1170 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1172 (the System V compiler puts out the second `xchg' instruction,
1173 and the assembler doesn't try to optimize it, so the 'sib' form
1174 gets generated). This sequence is used to get the address of the
1175 return buffer for a function that returns a structure. */
1176 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
1177 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
1181 if (current_pc <= pc)
1184 if (target_read_code (pc, &op, 1))
1187 if (op != 0x58) /* popl %eax */
1190 if (target_read_code (pc + 1, buf, 4))
1193 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
1196 if (current_pc == pc)
1198 cache->sp_offset += 4;
1202 if (current_pc == pc + 1)
1204 cache->pc_in_eax = 1;
1208 if (buf[1] == proto1[1])
1215 i386_skip_probe (CORE_ADDR pc)
1217 /* A function may start with
1231 if (target_read_code (pc, &op, 1))
1234 if (op == 0x68 || op == 0x6a)
1238 /* Skip past the `pushl' instruction; it has either a one-byte or a
1239 four-byte operand, depending on the opcode. */
1245 /* Read the following 8 bytes, which should be `call _probe' (6
1246 bytes) followed by `addl $4,%esp' (2 bytes). */
1247 read_memory (pc + delta, buf, sizeof (buf));
1248 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
1249 pc += delta + sizeof (buf);
1255 /* GCC 4.1 and later, can put code in the prologue to realign the
1256 stack pointer. Check whether PC points to such code, and update
1257 CACHE accordingly. Return the first instruction after the code
1258 sequence or CURRENT_PC, whichever is smaller. If we don't
1259 recognize the code, return PC. */
1262 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1263 struct i386_frame_cache *cache)
1265 /* There are 2 code sequences to re-align stack before the frame
1268 1. Use a caller-saved saved register:
1274 2. Use a callee-saved saved register:
1281 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1283 0x83 0xe4 0xf0 andl $-16, %esp
1284 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1289 int offset, offset_and;
1290 static int regnums[8] = {
1291 I386_EAX_REGNUM, /* %eax */
1292 I386_ECX_REGNUM, /* %ecx */
1293 I386_EDX_REGNUM, /* %edx */
1294 I386_EBX_REGNUM, /* %ebx */
1295 I386_ESP_REGNUM, /* %esp */
1296 I386_EBP_REGNUM, /* %ebp */
1297 I386_ESI_REGNUM, /* %esi */
1298 I386_EDI_REGNUM /* %edi */
1301 if (target_read_code (pc, buf, sizeof buf))
1304 /* Check caller-saved saved register. The first instruction has
1305 to be "leal 4(%esp), %reg". */
1306 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1308 /* MOD must be binary 10 and R/M must be binary 100. */
1309 if ((buf[1] & 0xc7) != 0x44)
1312 /* REG has register number. */
1313 reg = (buf[1] >> 3) & 7;
1318 /* Check callee-saved saved register. The first instruction
1319 has to be "pushl %reg". */
1320 if ((buf[0] & 0xf8) != 0x50)
1326 /* The next instruction has to be "leal 8(%esp), %reg". */
1327 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1330 /* MOD must be binary 10 and R/M must be binary 100. */
1331 if ((buf[2] & 0xc7) != 0x44)
1334 /* REG has register number. Registers in pushl and leal have to
1336 if (reg != ((buf[2] >> 3) & 7))
1342 /* Rigister can't be %esp nor %ebp. */
1343 if (reg == 4 || reg == 5)
1346 /* The next instruction has to be "andl $-XXX, %esp". */
1347 if (buf[offset + 1] != 0xe4
1348 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1351 offset_and = offset;
1352 offset += buf[offset] == 0x81 ? 6 : 3;
1354 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1355 0xfc. REG must be binary 110 and MOD must be binary 01. */
1356 if (buf[offset] != 0xff
1357 || buf[offset + 2] != 0xfc
1358 || (buf[offset + 1] & 0xf8) != 0x70)
1361 /* R/M has register. Registers in leal and pushl have to be the
1363 if (reg != (buf[offset + 1] & 7))
1366 if (current_pc > pc + offset_and)
1367 cache->saved_sp_reg = regnums[reg];
1369 return std::min (pc + offset + 3, current_pc);
1372 /* Maximum instruction length we need to handle. */
1373 #define I386_MAX_MATCHED_INSN_LEN 6
1375 /* Instruction description. */
1379 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
1380 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
1383 /* Return whether instruction at PC matches PATTERN. */
1386 i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern)
1390 if (target_read_code (pc, &op, 1))
1393 if ((op & pattern.mask[0]) == pattern.insn[0])
1395 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1396 int insn_matched = 1;
1399 gdb_assert (pattern.len > 1);
1400 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN);
1402 if (target_read_code (pc + 1, buf, pattern.len - 1))
1405 for (i = 1; i < pattern.len; i++)
1407 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i])
1410 return insn_matched;
1415 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1416 the first instruction description that matches. Otherwise, return
1419 static struct i386_insn *
1420 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns)
1422 struct i386_insn *pattern;
1424 for (pattern = insn_patterns; pattern->len > 0; pattern++)
1426 if (i386_match_pattern (pc, *pattern))
1433 /* Return whether PC points inside a sequence of instructions that
1434 matches INSN_PATTERNS. */
1437 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns)
1439 CORE_ADDR current_pc;
1441 struct i386_insn *insn;
1443 insn = i386_match_insn (pc, insn_patterns);
1448 ix = insn - insn_patterns;
1449 for (i = ix - 1; i >= 0; i--)
1451 current_pc -= insn_patterns[i].len;
1453 if (!i386_match_pattern (current_pc, insn_patterns[i]))
1457 current_pc = pc + insn->len;
1458 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++)
1460 if (!i386_match_pattern (current_pc, *insn))
1463 current_pc += insn->len;
1469 /* Some special instructions that might be migrated by GCC into the
1470 part of the prologue that sets up the new stack frame. Because the
1471 stack frame hasn't been setup yet, no registers have been saved
1472 yet, and only the scratch registers %eax, %ecx and %edx can be
1475 struct i386_insn i386_frame_setup_skip_insns[] =
1477 /* Check for `movb imm8, r' and `movl imm32, r'.
1479 ??? Should we handle 16-bit operand-sizes here? */
1481 /* `movb imm8, %al' and `movb imm8, %ah' */
1482 /* `movb imm8, %cl' and `movb imm8, %ch' */
1483 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1484 /* `movb imm8, %dl' and `movb imm8, %dh' */
1485 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1486 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1487 { 5, { 0xb8 }, { 0xfe } },
1488 /* `movl imm32, %edx' */
1489 { 5, { 0xba }, { 0xff } },
1491 /* Check for `mov imm32, r32'. Note that there is an alternative
1492 encoding for `mov m32, %eax'.
1494 ??? Should we handle SIB adressing here?
1495 ??? Should we handle 16-bit operand-sizes here? */
1497 /* `movl m32, %eax' */
1498 { 5, { 0xa1 }, { 0xff } },
1499 /* `movl m32, %eax' and `mov; m32, %ecx' */
1500 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1501 /* `movl m32, %edx' */
1502 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1504 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1505 Because of the symmetry, there are actually two ways to encode
1506 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1507 opcode bytes 0x31 and 0x33 for `xorl'. */
1509 /* `subl %eax, %eax' */
1510 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1511 /* `subl %ecx, %ecx' */
1512 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1513 /* `subl %edx, %edx' */
1514 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1515 /* `xorl %eax, %eax' */
1516 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1517 /* `xorl %ecx, %ecx' */
1518 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1519 /* `xorl %edx, %edx' */
1520 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1525 /* Check whether PC points to a no-op instruction. */
1527 i386_skip_noop (CORE_ADDR pc)
1532 if (target_read_code (pc, &op, 1))
1538 /* Ignore `nop' instruction. */
1542 if (target_read_code (pc, &op, 1))
1546 /* Ignore no-op instruction `mov %edi, %edi'.
1547 Microsoft system dlls often start with
1548 a `mov %edi,%edi' instruction.
1549 The 5 bytes before the function start are
1550 filled with `nop' instructions.
1551 This pattern can be used for hot-patching:
1552 The `mov %edi, %edi' instruction can be replaced by a
1553 near jump to the location of the 5 `nop' instructions
1554 which can be replaced by a 32-bit jump to anywhere
1555 in the 32-bit address space. */
1557 else if (op == 0x8b)
1559 if (target_read_code (pc + 1, &op, 1))
1565 if (target_read_code (pc, &op, 1))
1575 /* Check whether PC points at a code that sets up a new stack frame.
1576 If so, it updates CACHE and returns the address of the first
1577 instruction after the sequence that sets up the frame or LIMIT,
1578 whichever is smaller. If we don't recognize the code, return PC. */
1581 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1582 CORE_ADDR pc, CORE_ADDR limit,
1583 struct i386_frame_cache *cache)
1585 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1586 struct i386_insn *insn;
1593 if (target_read_code (pc, &op, 1))
1596 if (op == 0x55) /* pushl %ebp */
1598 /* Take into account that we've executed the `pushl %ebp' that
1599 starts this instruction sequence. */
1600 cache->saved_regs[I386_EBP_REGNUM] = 0;
1601 cache->sp_offset += 4;
1604 /* If that's all, return now. */
1608 /* Check for some special instructions that might be migrated by
1609 GCC into the prologue and skip them. At this point in the
1610 prologue, code should only touch the scratch registers %eax,
1611 %ecx and %edx, so while the number of posibilities is sheer,
1614 Make sure we only skip these instructions if we later see the
1615 `movl %esp, %ebp' that actually sets up the frame. */
1616 while (pc + skip < limit)
1618 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1625 /* If that's all, return now. */
1626 if (limit <= pc + skip)
1629 if (target_read_code (pc + skip, &op, 1))
1632 /* The i386 prologue looks like
1638 and a different prologue can be generated for atom.
1642 lea -0x10(%esp),%esp
1644 We handle both of them here. */
1648 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1650 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1656 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1661 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1662 if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order)
1671 /* OK, we actually have a frame. We just don't know how large
1672 it is yet. Set its size to zero. We'll adjust it if
1673 necessary. We also now commit to skipping the special
1674 instructions mentioned before. */
1677 /* If that's all, return now. */
1681 /* Check for stack adjustment
1687 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1688 reg, so we don't have to worry about a data16 prefix. */
1689 if (target_read_code (pc, &op, 1))
1693 /* `subl' with 8-bit immediate. */
1694 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1695 /* Some instruction starting with 0x83 other than `subl'. */
1698 /* `subl' with signed 8-bit immediate (though it wouldn't
1699 make sense to be negative). */
1700 cache->locals = read_code_integer (pc + 2, 1, byte_order);
1703 else if (op == 0x81)
1705 /* Maybe it is `subl' with a 32-bit immediate. */
1706 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1707 /* Some instruction starting with 0x81 other than `subl'. */
1710 /* It is `subl' with a 32-bit immediate. */
1711 cache->locals = read_code_integer (pc + 2, 4, byte_order);
1714 else if (op == 0x8d)
1716 /* The ModR/M byte is 0x64. */
1717 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64)
1719 /* 'lea' with 8-bit displacement. */
1720 cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order);
1725 /* Some instruction other than `subl' nor 'lea'. */
1729 else if (op == 0xc8) /* enter */
1731 cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order);
1738 /* Check whether PC points at code that saves registers on the stack.
1739 If so, it updates CACHE and returns the address of the first
1740 instruction after the register saves or CURRENT_PC, whichever is
1741 smaller. Otherwise, return PC. */
1744 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1745 struct i386_frame_cache *cache)
1747 CORE_ADDR offset = 0;
1751 if (cache->locals > 0)
1752 offset -= cache->locals;
1753 for (i = 0; i < 8 && pc < current_pc; i++)
1755 if (target_read_code (pc, &op, 1))
1757 if (op < 0x50 || op > 0x57)
1761 cache->saved_regs[op - 0x50] = offset;
1762 cache->sp_offset += 4;
1769 /* Do a full analysis of the prologue at PC and update CACHE
1770 accordingly. Bail out early if CURRENT_PC is reached. Return the
1771 address where the analysis stopped.
1773 We handle these cases:
1775 The startup sequence can be at the start of the function, or the
1776 function can start with a branch to startup code at the end.
1778 %ebp can be set up with either the 'enter' instruction, or "pushl
1779 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1780 once used in the System V compiler).
1782 Local space is allocated just below the saved %ebp by either the
1783 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1784 16-bit unsigned argument for space to allocate, and the 'addl'
1785 instruction could have either a signed byte, or 32-bit immediate.
1787 Next, the registers used by this function are pushed. With the
1788 System V compiler they will always be in the order: %edi, %esi,
1789 %ebx (and sometimes a harmless bug causes it to also save but not
1790 restore %eax); however, the code below is willing to see the pushes
1791 in any order, and will handle up to 8 of them.
1793 If the setup sequence is at the end of the function, then the next
1794 instruction will be a branch back to the start. */
1797 i386_analyze_prologue (struct gdbarch *gdbarch,
1798 CORE_ADDR pc, CORE_ADDR current_pc,
1799 struct i386_frame_cache *cache)
1801 pc = i386_skip_noop (pc);
1802 pc = i386_follow_jump (gdbarch, pc);
1803 pc = i386_analyze_struct_return (pc, current_pc, cache);
1804 pc = i386_skip_probe (pc);
1805 pc = i386_analyze_stack_align (pc, current_pc, cache);
1806 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1807 return i386_analyze_register_saves (pc, current_pc, cache);
1810 /* Return PC of first real instruction. */
1813 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1815 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1817 static gdb_byte pic_pat[6] =
1819 0xe8, 0, 0, 0, 0, /* call 0x0 */
1820 0x5b, /* popl %ebx */
1822 struct i386_frame_cache cache;
1826 CORE_ADDR func_addr;
1828 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
1830 CORE_ADDR post_prologue_pc
1831 = skip_prologue_using_sal (gdbarch, func_addr);
1832 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
1834 /* Clang always emits a line note before the prologue and another
1835 one after. We trust clang to emit usable line notes. */
1836 if (post_prologue_pc
1838 && COMPUNIT_PRODUCER (cust) != NULL
1839 && startswith (COMPUNIT_PRODUCER (cust), "clang ")))
1840 return std::max (start_pc, post_prologue_pc);
1844 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1845 if (cache.locals < 0)
1848 /* Found valid frame setup. */
1850 /* The native cc on SVR4 in -K PIC mode inserts the following code
1851 to get the address of the global offset table (GOT) into register
1856 movl %ebx,x(%ebp) (optional)
1859 This code is with the rest of the prologue (at the end of the
1860 function), so we have to skip it to get to the first real
1861 instruction at the start of the function. */
1863 for (i = 0; i < 6; i++)
1865 if (target_read_code (pc + i, &op, 1))
1868 if (pic_pat[i] != op)
1875 if (target_read_code (pc + delta, &op, 1))
1878 if (op == 0x89) /* movl %ebx, x(%ebp) */
1880 op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order);
1882 if (op == 0x5d) /* One byte offset from %ebp. */
1884 else if (op == 0x9d) /* Four byte offset from %ebp. */
1886 else /* Unexpected instruction. */
1889 if (target_read_code (pc + delta, &op, 1))
1894 if (delta > 0 && op == 0x81
1895 && read_code_unsigned_integer (pc + delta + 1, 1, byte_order)
1902 /* If the function starts with a branch (to startup code at the end)
1903 the last instruction should bring us back to the first
1904 instruction of the real code. */
1905 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1906 pc = i386_follow_jump (gdbarch, pc);
1911 /* Check that the code pointed to by PC corresponds to a call to
1912 __main, skip it if so. Return PC otherwise. */
1915 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1917 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1920 if (target_read_code (pc, &op, 1))
1926 if (target_read_code (pc + 1, buf, sizeof buf) == 0)
1928 /* Make sure address is computed correctly as a 32bit
1929 integer even if CORE_ADDR is 64 bit wide. */
1930 struct bound_minimal_symbol s;
1931 CORE_ADDR call_dest;
1933 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1934 call_dest = call_dest & 0xffffffffU;
1935 s = lookup_minimal_symbol_by_pc (call_dest);
1936 if (s.minsym != NULL
1937 && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL
1938 && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0)
1946 /* This function is 64-bit safe. */
1949 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1953 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1954 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1958 /* Normal frames. */
1961 i386_frame_cache_1 (struct frame_info *this_frame,
1962 struct i386_frame_cache *cache)
1964 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1965 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1969 cache->pc = get_frame_func (this_frame);
1971 /* In principle, for normal frames, %ebp holds the frame pointer,
1972 which holds the base address for the current stack frame.
1973 However, for functions that don't need it, the frame pointer is
1974 optional. For these "frameless" functions the frame pointer is
1975 actually the frame pointer of the calling frame. Signal
1976 trampolines are just a special case of a "frameless" function.
1977 They (usually) share their frame pointer with the frame that was
1978 in progress when the signal occurred. */
1980 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1981 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1982 if (cache->base == 0)
1988 /* For normal frames, %eip is stored at 4(%ebp). */
1989 cache->saved_regs[I386_EIP_REGNUM] = 4;
1992 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
1995 if (cache->locals < 0)
1997 /* We didn't find a valid frame, which means that CACHE->base
1998 currently holds the frame pointer for our calling frame. If
1999 we're at the start of a function, or somewhere half-way its
2000 prologue, the function's frame probably hasn't been fully
2001 setup yet. Try to reconstruct the base address for the stack
2002 frame by looking at the stack pointer. For truly "frameless"
2003 functions this might work too. */
2005 if (cache->saved_sp_reg != -1)
2007 /* Saved stack pointer has been saved. */
2008 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2009 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2011 /* We're halfway aligning the stack. */
2012 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
2013 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
2015 /* This will be added back below. */
2016 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
2018 else if (cache->pc != 0
2019 || target_read_code (get_frame_pc (this_frame), buf, 1))
2021 /* We're in a known function, but did not find a frame
2022 setup. Assume that the function does not use %ebp.
2023 Alternatively, we may have jumped to an invalid
2024 address; in that case there is definitely no new
2026 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2027 cache->base = extract_unsigned_integer (buf, 4, byte_order)
2031 /* We're in an unknown function. We could not find the start
2032 of the function to analyze the prologue; our best option is
2033 to assume a typical frame layout with the caller's %ebp
2035 cache->saved_regs[I386_EBP_REGNUM] = 0;
2038 if (cache->saved_sp_reg != -1)
2040 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2041 register may be unavailable). */
2042 if (cache->saved_sp == 0
2043 && deprecated_frame_register_read (this_frame,
2044 cache->saved_sp_reg, buf))
2045 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2047 /* Now that we have the base address for the stack frame we can
2048 calculate the value of %esp in the calling frame. */
2049 else if (cache->saved_sp == 0)
2050 cache->saved_sp = cache->base + 8;
2052 /* Adjust all the saved registers such that they contain addresses
2053 instead of offsets. */
2054 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
2055 if (cache->saved_regs[i] != -1)
2056 cache->saved_regs[i] += cache->base;
2061 static struct i386_frame_cache *
2062 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
2064 struct i386_frame_cache *cache;
2067 return (struct i386_frame_cache *) *this_cache;
2069 cache = i386_alloc_frame_cache ();
2070 *this_cache = cache;
2074 i386_frame_cache_1 (this_frame, cache);
2076 CATCH (ex, RETURN_MASK_ERROR)
2078 if (ex.error != NOT_AVAILABLE_ERROR)
2079 throw_exception (ex);
2087 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
2088 struct frame_id *this_id)
2090 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2093 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2094 else if (cache->base == 0)
2096 /* This marks the outermost frame. */
2100 /* See the end of i386_push_dummy_call. */
2101 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2105 static enum unwind_stop_reason
2106 i386_frame_unwind_stop_reason (struct frame_info *this_frame,
2109 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2112 return UNWIND_UNAVAILABLE;
2114 /* This marks the outermost frame. */
2115 if (cache->base == 0)
2116 return UNWIND_OUTERMOST;
2118 return UNWIND_NO_REASON;
2121 static struct value *
2122 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2125 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2127 gdb_assert (regnum >= 0);
2129 /* The System V ABI says that:
2131 "The flags register contains the system flags, such as the
2132 direction flag and the carry flag. The direction flag must be
2133 set to the forward (that is, zero) direction before entry and
2134 upon exit from a function. Other user flags have no specified
2135 role in the standard calling sequence and are not preserved."
2137 To guarantee the "upon exit" part of that statement we fake a
2138 saved flags register that has its direction flag cleared.
2140 Note that GCC doesn't seem to rely on the fact that the direction
2141 flag is cleared after a function return; it always explicitly
2142 clears the flag before operations where it matters.
2144 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2145 right thing to do. The way we fake the flags register here makes
2146 it impossible to change it. */
2148 if (regnum == I386_EFLAGS_REGNUM)
2152 val = get_frame_register_unsigned (this_frame, regnum);
2154 return frame_unwind_got_constant (this_frame, regnum, val);
2157 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
2158 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
2160 if (regnum == I386_ESP_REGNUM
2161 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1))
2163 /* If the SP has been saved, but we don't know where, then this
2164 means that SAVED_SP_REG register was found unavailable back
2165 when we built the cache. */
2166 if (cache->saved_sp == 0)
2167 return frame_unwind_got_register (this_frame, regnum,
2168 cache->saved_sp_reg);
2170 return frame_unwind_got_constant (this_frame, regnum,
2174 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2175 return frame_unwind_got_memory (this_frame, regnum,
2176 cache->saved_regs[regnum]);
2178 return frame_unwind_got_register (this_frame, regnum, regnum);
2181 static const struct frame_unwind i386_frame_unwind =
2184 i386_frame_unwind_stop_reason,
2186 i386_frame_prev_register,
2188 default_frame_sniffer
2191 /* Normal frames, but in a function epilogue. */
2193 /* Implement the stack_frame_destroyed_p gdbarch method.
2195 The epilogue is defined here as the 'ret' instruction, which will
2196 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2197 the function's stack frame. */
2200 i386_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2203 struct compunit_symtab *cust;
2205 cust = find_pc_compunit_symtab (pc);
2206 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
2209 if (target_read_memory (pc, &insn, 1))
2210 return 0; /* Can't read memory at pc. */
2212 if (insn != 0xc3) /* 'ret' instruction. */
2219 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
2220 struct frame_info *this_frame,
2221 void **this_prologue_cache)
2223 if (frame_relative_level (this_frame) == 0)
2224 return i386_stack_frame_destroyed_p (get_frame_arch (this_frame),
2225 get_frame_pc (this_frame));
2230 static struct i386_frame_cache *
2231 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2233 struct i386_frame_cache *cache;
2237 return (struct i386_frame_cache *) *this_cache;
2239 cache = i386_alloc_frame_cache ();
2240 *this_cache = cache;
2244 cache->pc = get_frame_func (this_frame);
2246 /* At this point the stack looks as if we just entered the
2247 function, with the return address at the top of the
2249 sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM);
2250 cache->base = sp + cache->sp_offset;
2251 cache->saved_sp = cache->base + 8;
2252 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
2256 CATCH (ex, RETURN_MASK_ERROR)
2258 if (ex.error != NOT_AVAILABLE_ERROR)
2259 throw_exception (ex);
2266 static enum unwind_stop_reason
2267 i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2270 struct i386_frame_cache *cache =
2271 i386_epilogue_frame_cache (this_frame, this_cache);
2274 return UNWIND_UNAVAILABLE;
2276 return UNWIND_NO_REASON;
2280 i386_epilogue_frame_this_id (struct frame_info *this_frame,
2282 struct frame_id *this_id)
2284 struct i386_frame_cache *cache =
2285 i386_epilogue_frame_cache (this_frame, this_cache);
2288 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2290 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2293 static struct value *
2294 i386_epilogue_frame_prev_register (struct frame_info *this_frame,
2295 void **this_cache, int regnum)
2297 /* Make sure we've initialized the cache. */
2298 i386_epilogue_frame_cache (this_frame, this_cache);
2300 return i386_frame_prev_register (this_frame, this_cache, regnum);
2303 static const struct frame_unwind i386_epilogue_frame_unwind =
2306 i386_epilogue_frame_unwind_stop_reason,
2307 i386_epilogue_frame_this_id,
2308 i386_epilogue_frame_prev_register,
2310 i386_epilogue_frame_sniffer
2314 /* Stack-based trampolines. */
2316 /* These trampolines are used on cross x86 targets, when taking the
2317 address of a nested function. When executing these trampolines,
2318 no stack frame is set up, so we are in a similar situation as in
2319 epilogues and i386_epilogue_frame_this_id can be re-used. */
2321 /* Static chain passed in register. */
2323 struct i386_insn i386_tramp_chain_in_reg_insns[] =
2325 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2326 { 5, { 0xb8 }, { 0xfe } },
2329 { 5, { 0xe9 }, { 0xff } },
2334 /* Static chain passed on stack (when regparm=3). */
2336 struct i386_insn i386_tramp_chain_on_stack_insns[] =
2339 { 5, { 0x68 }, { 0xff } },
2342 { 5, { 0xe9 }, { 0xff } },
2347 /* Return whether PC points inside a stack trampoline. */
2350 i386_in_stack_tramp_p (CORE_ADDR pc)
2355 /* A stack trampoline is detected if no name is associated
2356 to the current pc and if it points inside a trampoline
2359 find_pc_partial_function (pc, &name, NULL, NULL);
2363 if (target_read_memory (pc, &insn, 1))
2366 if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns)
2367 && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns))
2374 i386_stack_tramp_frame_sniffer (const struct frame_unwind *self,
2375 struct frame_info *this_frame,
2378 if (frame_relative_level (this_frame) == 0)
2379 return i386_in_stack_tramp_p (get_frame_pc (this_frame));
2384 static const struct frame_unwind i386_stack_tramp_frame_unwind =
2387 i386_epilogue_frame_unwind_stop_reason,
2388 i386_epilogue_frame_this_id,
2389 i386_epilogue_frame_prev_register,
2391 i386_stack_tramp_frame_sniffer
2394 /* Generate a bytecode expression to get the value of the saved PC. */
2397 i386_gen_return_address (struct gdbarch *gdbarch,
2398 struct agent_expr *ax, struct axs_value *value,
2401 /* The following sequence assumes the traditional use of the base
2403 ax_reg (ax, I386_EBP_REGNUM);
2405 ax_simple (ax, aop_add);
2406 value->type = register_type (gdbarch, I386_EIP_REGNUM);
2407 value->kind = axs_lvalue_memory;
2411 /* Signal trampolines. */
2413 static struct i386_frame_cache *
2414 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2416 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2417 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2418 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2419 struct i386_frame_cache *cache;
2424 return (struct i386_frame_cache *) *this_cache;
2426 cache = i386_alloc_frame_cache ();
2430 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2431 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
2433 addr = tdep->sigcontext_addr (this_frame);
2434 if (tdep->sc_reg_offset)
2438 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
2440 for (i = 0; i < tdep->sc_num_regs; i++)
2441 if (tdep->sc_reg_offset[i] != -1)
2442 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2446 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
2447 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
2452 CATCH (ex, RETURN_MASK_ERROR)
2454 if (ex.error != NOT_AVAILABLE_ERROR)
2455 throw_exception (ex);
2459 *this_cache = cache;
2463 static enum unwind_stop_reason
2464 i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2467 struct i386_frame_cache *cache =
2468 i386_sigtramp_frame_cache (this_frame, this_cache);
2471 return UNWIND_UNAVAILABLE;
2473 return UNWIND_NO_REASON;
2477 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
2478 struct frame_id *this_id)
2480 struct i386_frame_cache *cache =
2481 i386_sigtramp_frame_cache (this_frame, this_cache);
2484 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2487 /* See the end of i386_push_dummy_call. */
2488 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
2492 static struct value *
2493 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
2494 void **this_cache, int regnum)
2496 /* Make sure we've initialized the cache. */
2497 i386_sigtramp_frame_cache (this_frame, this_cache);
2499 return i386_frame_prev_register (this_frame, this_cache, regnum);
2503 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
2504 struct frame_info *this_frame,
2505 void **this_prologue_cache)
2507 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2509 /* We shouldn't even bother if we don't have a sigcontext_addr
2511 if (tdep->sigcontext_addr == NULL)
2514 if (tdep->sigtramp_p != NULL)
2516 if (tdep->sigtramp_p (this_frame))
2520 if (tdep->sigtramp_start != 0)
2522 CORE_ADDR pc = get_frame_pc (this_frame);
2524 gdb_assert (tdep->sigtramp_end != 0);
2525 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2532 static const struct frame_unwind i386_sigtramp_frame_unwind =
2535 i386_sigtramp_frame_unwind_stop_reason,
2536 i386_sigtramp_frame_this_id,
2537 i386_sigtramp_frame_prev_register,
2539 i386_sigtramp_frame_sniffer
2544 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
2546 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2551 static const struct frame_base i386_frame_base =
2554 i386_frame_base_address,
2555 i386_frame_base_address,
2556 i386_frame_base_address
2559 static struct frame_id
2560 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2564 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
2566 /* See the end of i386_push_dummy_call. */
2567 return frame_id_build (fp + 8, get_frame_pc (this_frame));
2570 /* _Decimal128 function return values need 16-byte alignment on the
2574 i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2576 return sp & -(CORE_ADDR)16;
2580 /* Figure out where the longjmp will land. Slurp the args out of the
2581 stack. We expect the first arg to be a pointer to the jmp_buf
2582 structure from which we extract the address that we will land at.
2583 This address is copied into PC. This routine returns non-zero on
2587 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2590 CORE_ADDR sp, jb_addr;
2591 struct gdbarch *gdbarch = get_frame_arch (frame);
2592 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2593 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2595 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2596 longjmp will land. */
2597 if (jb_pc_offset == -1)
2600 get_frame_register (frame, I386_ESP_REGNUM, buf);
2601 sp = extract_unsigned_integer (buf, 4, byte_order);
2602 if (target_read_memory (sp + 4, buf, 4))
2605 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
2606 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
2609 *pc = extract_unsigned_integer (buf, 4, byte_order);
2614 /* Check whether TYPE must be 16-byte-aligned when passed as a
2615 function argument. 16-byte vectors, _Decimal128 and structures or
2616 unions containing such types must be 16-byte-aligned; other
2617 arguments are 4-byte-aligned. */
2620 i386_16_byte_align_p (struct type *type)
2622 type = check_typedef (type);
2623 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
2624 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
2625 && TYPE_LENGTH (type) == 16)
2627 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2628 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
2629 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2630 || TYPE_CODE (type) == TYPE_CODE_UNION)
2633 for (i = 0; i < TYPE_NFIELDS (type); i++)
2635 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
2642 /* Implementation for set_gdbarch_push_dummy_code. */
2645 i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
2646 struct value **args, int nargs, struct type *value_type,
2647 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
2648 struct regcache *regcache)
2650 /* Use 0xcc breakpoint - 1 byte. */
2654 /* Keep the stack aligned. */
2659 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2660 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2661 struct value **args, CORE_ADDR sp, int struct_return,
2662 CORE_ADDR struct_addr)
2664 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2670 /* Determine the total space required for arguments and struct
2671 return address in a first pass (allowing for 16-byte-aligned
2672 arguments), then push arguments in a second pass. */
2674 for (write_pass = 0; write_pass < 2; write_pass++)
2676 int args_space_used = 0;
2682 /* Push value address. */
2683 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2684 write_memory (sp, buf, 4);
2685 args_space_used += 4;
2691 for (i = 0; i < nargs; i++)
2693 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2697 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2698 args_space_used = align_up (args_space_used, 16);
2700 write_memory (sp + args_space_used,
2701 value_contents_all (args[i]), len);
2702 /* The System V ABI says that:
2704 "An argument's size is increased, if necessary, to make it a
2705 multiple of [32-bit] words. This may require tail padding,
2706 depending on the size of the argument."
2708 This makes sure the stack stays word-aligned. */
2709 args_space_used += align_up (len, 4);
2713 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2714 args_space = align_up (args_space, 16);
2715 args_space += align_up (len, 4);
2723 /* The original System V ABI only requires word alignment,
2724 but modern incarnations need 16-byte alignment in order
2725 to support SSE. Since wasting a few bytes here isn't
2726 harmful we unconditionally enforce 16-byte alignment. */
2731 /* Store return address. */
2733 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2734 write_memory (sp, buf, 4);
2736 /* Finally, update the stack pointer... */
2737 store_unsigned_integer (buf, 4, byte_order, sp);
2738 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
2740 /* ...and fake a frame pointer. */
2741 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
2743 /* MarkK wrote: This "+ 8" is all over the place:
2744 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2745 i386_dummy_id). It's there, since all frame unwinders for
2746 a given target have to agree (within a certain margin) on the
2747 definition of the stack address of a frame. Otherwise frame id
2748 comparison might not work correctly. Since DWARF2/GCC uses the
2749 stack address *before* the function call as a frame's CFA. On
2750 the i386, when %ebp is used as a frame pointer, the offset
2751 between the contents %ebp and the CFA as defined by GCC. */
2755 /* These registers are used for returning integers (and on some
2756 targets also for returning `struct' and `union' values when their
2757 size and alignment match an integer type). */
2758 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2759 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2761 /* Read, for architecture GDBARCH, a function return value of TYPE
2762 from REGCACHE, and copy that into VALBUF. */
2765 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2766 struct regcache *regcache, gdb_byte *valbuf)
2768 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2769 int len = TYPE_LENGTH (type);
2770 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2772 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2774 if (tdep->st0_regnum < 0)
2776 warning (_("Cannot find floating-point return value."));
2777 memset (valbuf, 0, len);
2781 /* Floating-point return values can be found in %st(0). Convert
2782 its contents to the desired type. This is probably not
2783 exactly how it would happen on the target itself, but it is
2784 the best we can do. */
2785 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2786 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
2790 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2791 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2793 if (len <= low_size)
2795 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2796 memcpy (valbuf, buf, len);
2798 else if (len <= (low_size + high_size))
2800 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2801 memcpy (valbuf, buf, low_size);
2802 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2803 memcpy (valbuf + low_size, buf, len - low_size);
2806 internal_error (__FILE__, __LINE__,
2807 _("Cannot extract return value of %d bytes long."),
2812 /* Write, for architecture GDBARCH, a function return value of TYPE
2813 from VALBUF into REGCACHE. */
2816 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2817 struct regcache *regcache, const gdb_byte *valbuf)
2819 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2820 int len = TYPE_LENGTH (type);
2822 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2825 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2827 if (tdep->st0_regnum < 0)
2829 warning (_("Cannot set floating-point return value."));
2833 /* Returning floating-point values is a bit tricky. Apart from
2834 storing the return value in %st(0), we have to simulate the
2835 state of the FPU at function return point. */
2837 /* Convert the value found in VALBUF to the extended
2838 floating-point format used by the FPU. This is probably
2839 not exactly how it would happen on the target itself, but
2840 it is the best we can do. */
2841 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
2842 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2844 /* Set the top of the floating-point register stack to 7. The
2845 actual value doesn't really matter, but 7 is what a normal
2846 function return would end up with if the program started out
2847 with a freshly initialized FPU. */
2848 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2850 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2852 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2853 the floating-point register stack to 7, the appropriate value
2854 for the tag word is 0x3fff. */
2855 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2859 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2860 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2862 if (len <= low_size)
2863 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2864 else if (len <= (low_size + high_size))
2866 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2867 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
2868 len - low_size, valbuf + low_size);
2871 internal_error (__FILE__, __LINE__,
2872 _("Cannot store return value of %d bytes long."), len);
2877 /* This is the variable that is set with "set struct-convention", and
2878 its legitimate values. */
2879 static const char default_struct_convention[] = "default";
2880 static const char pcc_struct_convention[] = "pcc";
2881 static const char reg_struct_convention[] = "reg";
2882 static const char *const valid_conventions[] =
2884 default_struct_convention,
2885 pcc_struct_convention,
2886 reg_struct_convention,
2889 static const char *struct_convention = default_struct_convention;
2891 /* Return non-zero if TYPE, which is assumed to be a structure,
2892 a union type, or an array type, should be returned in registers
2893 for architecture GDBARCH. */
2896 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2898 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2899 enum type_code code = TYPE_CODE (type);
2900 int len = TYPE_LENGTH (type);
2902 gdb_assert (code == TYPE_CODE_STRUCT
2903 || code == TYPE_CODE_UNION
2904 || code == TYPE_CODE_ARRAY);
2906 if (struct_convention == pcc_struct_convention
2907 || (struct_convention == default_struct_convention
2908 && tdep->struct_return == pcc_struct_return))
2911 /* Structures consisting of a single `float', `double' or 'long
2912 double' member are returned in %st(0). */
2913 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2915 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2916 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2917 return (len == 4 || len == 8 || len == 12);
2920 return (len == 1 || len == 2 || len == 4 || len == 8);
2923 /* Determine, for architecture GDBARCH, how a return value of TYPE
2924 should be returned. If it is supposed to be returned in registers,
2925 and READBUF is non-zero, read the appropriate value from REGCACHE,
2926 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2927 from WRITEBUF into REGCACHE. */
2929 static enum return_value_convention
2930 i386_return_value (struct gdbarch *gdbarch, struct value *function,
2931 struct type *type, struct regcache *regcache,
2932 gdb_byte *readbuf, const gdb_byte *writebuf)
2934 enum type_code code = TYPE_CODE (type);
2936 if (((code == TYPE_CODE_STRUCT
2937 || code == TYPE_CODE_UNION
2938 || code == TYPE_CODE_ARRAY)
2939 && !i386_reg_struct_return_p (gdbarch, type))
2940 /* Complex double and long double uses the struct return covention. */
2941 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16)
2942 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24)
2943 /* 128-bit decimal float uses the struct return convention. */
2944 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2946 /* The System V ABI says that:
2948 "A function that returns a structure or union also sets %eax
2949 to the value of the original address of the caller's area
2950 before it returns. Thus when the caller receives control
2951 again, the address of the returned object resides in register
2952 %eax and can be used to access the object."
2954 So the ABI guarantees that we can always find the return
2955 value just after the function has returned. */
2957 /* Note that the ABI doesn't mention functions returning arrays,
2958 which is something possible in certain languages such as Ada.
2959 In this case, the value is returned as if it was wrapped in
2960 a record, so the convention applied to records also applies
2967 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2968 read_memory (addr, readbuf, TYPE_LENGTH (type));
2971 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2974 /* This special case is for structures consisting of a single
2975 `float', `double' or 'long double' member. These structures are
2976 returned in %st(0). For these structures, we call ourselves
2977 recursively, changing TYPE into the type of the first member of
2978 the structure. Since that should work for all structures that
2979 have only one member, we don't bother to check the member's type
2981 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2983 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2984 return i386_return_value (gdbarch, function, type, regcache,
2989 i386_extract_return_value (gdbarch, type, regcache, readbuf);
2991 i386_store_return_value (gdbarch, type, regcache, writebuf);
2993 return RETURN_VALUE_REGISTER_CONVENTION;
2998 i387_ext_type (struct gdbarch *gdbarch)
3000 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3002 if (!tdep->i387_ext_type)
3004 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
3005 gdb_assert (tdep->i387_ext_type != NULL);
3008 return tdep->i387_ext_type;
3011 /* Construct type for pseudo BND registers. We can't use
3012 tdesc_find_type since a complement of one value has to be used
3013 to describe the upper bound. */
3015 static struct type *
3016 i386_bnd_type (struct gdbarch *gdbarch)
3018 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3021 if (!tdep->i386_bnd_type)
3024 const struct builtin_type *bt = builtin_type (gdbarch);
3026 /* The type we're building is described bellow: */
3031 void *ubound; /* One complement of raw ubound field. */
3035 t = arch_composite_type (gdbarch,
3036 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT);
3038 append_composite_type_field (t, "lbound", bt->builtin_data_ptr);
3039 append_composite_type_field (t, "ubound", bt->builtin_data_ptr);
3041 TYPE_NAME (t) = "builtin_type_bound128";
3042 tdep->i386_bnd_type = t;
3045 return tdep->i386_bnd_type;
3048 /* Construct vector type for pseudo ZMM registers. We can't use
3049 tdesc_find_type since ZMM isn't described in target description. */
3051 static struct type *
3052 i386_zmm_type (struct gdbarch *gdbarch)
3054 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3056 if (!tdep->i386_zmm_type)
3058 const struct builtin_type *bt = builtin_type (gdbarch);
3060 /* The type we're building is this: */
3062 union __gdb_builtin_type_vec512i
3064 int128_t uint128[4];
3065 int64_t v4_int64[8];
3066 int32_t v8_int32[16];
3067 int16_t v16_int16[32];
3068 int8_t v32_int8[64];
3069 double v4_double[8];
3076 t = arch_composite_type (gdbarch,
3077 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION);
3078 append_composite_type_field (t, "v16_float",
3079 init_vector_type (bt->builtin_float, 16));
3080 append_composite_type_field (t, "v8_double",
3081 init_vector_type (bt->builtin_double, 8));
3082 append_composite_type_field (t, "v64_int8",
3083 init_vector_type (bt->builtin_int8, 64));
3084 append_composite_type_field (t, "v32_int16",
3085 init_vector_type (bt->builtin_int16, 32));
3086 append_composite_type_field (t, "v16_int32",
3087 init_vector_type (bt->builtin_int32, 16));
3088 append_composite_type_field (t, "v8_int64",
3089 init_vector_type (bt->builtin_int64, 8));
3090 append_composite_type_field (t, "v4_int128",
3091 init_vector_type (bt->builtin_int128, 4));
3093 TYPE_VECTOR (t) = 1;
3094 TYPE_NAME (t) = "builtin_type_vec512i";
3095 tdep->i386_zmm_type = t;
3098 return tdep->i386_zmm_type;
3101 /* Construct vector type for pseudo YMM registers. We can't use
3102 tdesc_find_type since YMM isn't described in target description. */
3104 static struct type *
3105 i386_ymm_type (struct gdbarch *gdbarch)
3107 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3109 if (!tdep->i386_ymm_type)
3111 const struct builtin_type *bt = builtin_type (gdbarch);
3113 /* The type we're building is this: */
3115 union __gdb_builtin_type_vec256i
3117 int128_t uint128[2];
3118 int64_t v2_int64[4];
3119 int32_t v4_int32[8];
3120 int16_t v8_int16[16];
3121 int8_t v16_int8[32];
3122 double v2_double[4];
3129 t = arch_composite_type (gdbarch,
3130 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
3131 append_composite_type_field (t, "v8_float",
3132 init_vector_type (bt->builtin_float, 8));
3133 append_composite_type_field (t, "v4_double",
3134 init_vector_type (bt->builtin_double, 4));
3135 append_composite_type_field (t, "v32_int8",
3136 init_vector_type (bt->builtin_int8, 32));
3137 append_composite_type_field (t, "v16_int16",
3138 init_vector_type (bt->builtin_int16, 16));
3139 append_composite_type_field (t, "v8_int32",
3140 init_vector_type (bt->builtin_int32, 8));
3141 append_composite_type_field (t, "v4_int64",
3142 init_vector_type (bt->builtin_int64, 4));
3143 append_composite_type_field (t, "v2_int128",
3144 init_vector_type (bt->builtin_int128, 2));
3146 TYPE_VECTOR (t) = 1;
3147 TYPE_NAME (t) = "builtin_type_vec256i";
3148 tdep->i386_ymm_type = t;
3151 return tdep->i386_ymm_type;
3154 /* Construct vector type for MMX registers. */
3155 static struct type *
3156 i386_mmx_type (struct gdbarch *gdbarch)
3158 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3160 if (!tdep->i386_mmx_type)
3162 const struct builtin_type *bt = builtin_type (gdbarch);
3164 /* The type we're building is this: */
3166 union __gdb_builtin_type_vec64i
3169 int32_t v2_int32[2];
3170 int16_t v4_int16[4];
3177 t = arch_composite_type (gdbarch,
3178 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
3180 append_composite_type_field (t, "uint64", bt->builtin_int64);
3181 append_composite_type_field (t, "v2_int32",
3182 init_vector_type (bt->builtin_int32, 2));
3183 append_composite_type_field (t, "v4_int16",
3184 init_vector_type (bt->builtin_int16, 4));
3185 append_composite_type_field (t, "v8_int8",
3186 init_vector_type (bt->builtin_int8, 8));
3188 TYPE_VECTOR (t) = 1;
3189 TYPE_NAME (t) = "builtin_type_vec64i";
3190 tdep->i386_mmx_type = t;
3193 return tdep->i386_mmx_type;
3196 /* Return the GDB type object for the "standard" data type of data in
3200 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3202 if (i386_bnd_regnum_p (gdbarch, regnum))
3203 return i386_bnd_type (gdbarch);
3204 if (i386_mmx_regnum_p (gdbarch, regnum))
3205 return i386_mmx_type (gdbarch);
3206 else if (i386_ymm_regnum_p (gdbarch, regnum))
3207 return i386_ymm_type (gdbarch);
3208 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3209 return i386_ymm_type (gdbarch);
3210 else if (i386_zmm_regnum_p (gdbarch, regnum))
3211 return i386_zmm_type (gdbarch);
3214 const struct builtin_type *bt = builtin_type (gdbarch);
3215 if (i386_byte_regnum_p (gdbarch, regnum))
3216 return bt->builtin_int8;
3217 else if (i386_word_regnum_p (gdbarch, regnum))
3218 return bt->builtin_int16;
3219 else if (i386_dword_regnum_p (gdbarch, regnum))
3220 return bt->builtin_int32;
3221 else if (i386_k_regnum_p (gdbarch, regnum))
3222 return bt->builtin_int64;
3225 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3228 /* Map a cooked register onto a raw register or memory. For the i386,
3229 the MMX registers need to be mapped onto floating point registers. */
3232 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
3234 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
3239 mmxreg = regnum - tdep->mm0_regnum;
3240 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
3241 tos = (fstat >> 11) & 0x7;
3242 fpreg = (mmxreg + tos) % 8;
3244 return (I387_ST0_REGNUM (tdep) + fpreg);
3247 /* A helper function for us by i386_pseudo_register_read_value and
3248 amd64_pseudo_register_read_value. It does all the work but reads
3249 the data into an already-allocated value. */
3252 i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
3253 struct regcache *regcache,
3255 struct value *result_value)
3257 gdb_byte raw_buf[MAX_REGISTER_SIZE];
3258 enum register_status status;
3259 gdb_byte *buf = value_contents_raw (result_value);
3261 if (i386_mmx_regnum_p (gdbarch, regnum))
3263 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3265 /* Extract (always little endian). */
3266 status = regcache_raw_read (regcache, fpnum, raw_buf);
3267 if (status != REG_VALID)
3268 mark_value_bytes_unavailable (result_value, 0,
3269 TYPE_LENGTH (value_type (result_value)));
3271 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
3275 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3276 if (i386_bnd_regnum_p (gdbarch, regnum))
3278 regnum -= tdep->bnd0_regnum;
3280 /* Extract (always little endian). Read lower 128bits. */
3281 status = regcache_raw_read (regcache,
3282 I387_BND0R_REGNUM (tdep) + regnum,
3284 if (status != REG_VALID)
3285 mark_value_bytes_unavailable (result_value, 0, 16);
3288 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3289 LONGEST upper, lower;
3290 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3292 lower = extract_unsigned_integer (raw_buf, 8, byte_order);
3293 upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order);
3296 memcpy (buf, &lower, size);
3297 memcpy (buf + size, &upper, size);
3300 else if (i386_k_regnum_p (gdbarch, regnum))
3302 regnum -= tdep->k0_regnum;
3304 /* Extract (always little endian). */
3305 status = regcache_raw_read (regcache,
3306 tdep->k0_regnum + regnum,
3308 if (status != REG_VALID)
3309 mark_value_bytes_unavailable (result_value, 0, 8);
3311 memcpy (buf, raw_buf, 8);
3313 else if (i386_zmm_regnum_p (gdbarch, regnum))
3315 regnum -= tdep->zmm0_regnum;
3317 if (regnum < num_lower_zmm_regs)
3319 /* Extract (always little endian). Read lower 128bits. */
3320 status = regcache_raw_read (regcache,
3321 I387_XMM0_REGNUM (tdep) + regnum,
3323 if (status != REG_VALID)
3324 mark_value_bytes_unavailable (result_value, 0, 16);
3326 memcpy (buf, raw_buf, 16);
3328 /* Extract (always little endian). Read upper 128bits. */
3329 status = regcache_raw_read (regcache,
3330 tdep->ymm0h_regnum + regnum,
3332 if (status != REG_VALID)
3333 mark_value_bytes_unavailable (result_value, 16, 16);
3335 memcpy (buf + 16, raw_buf, 16);
3339 /* Extract (always little endian). Read lower 128bits. */
3340 status = regcache_raw_read (regcache,
3341 I387_XMM16_REGNUM (tdep) + regnum
3342 - num_lower_zmm_regs,
3344 if (status != REG_VALID)
3345 mark_value_bytes_unavailable (result_value, 0, 16);
3347 memcpy (buf, raw_buf, 16);
3349 /* Extract (always little endian). Read upper 128bits. */
3350 status = regcache_raw_read (regcache,
3351 I387_YMM16H_REGNUM (tdep) + regnum
3352 - num_lower_zmm_regs,
3354 if (status != REG_VALID)
3355 mark_value_bytes_unavailable (result_value, 16, 16);
3357 memcpy (buf + 16, raw_buf, 16);
3360 /* Read upper 256bits. */
3361 status = regcache_raw_read (regcache,
3362 tdep->zmm0h_regnum + regnum,
3364 if (status != REG_VALID)
3365 mark_value_bytes_unavailable (result_value, 32, 32);
3367 memcpy (buf + 32, raw_buf, 32);
3369 else if (i386_ymm_regnum_p (gdbarch, regnum))
3371 regnum -= tdep->ymm0_regnum;
3373 /* Extract (always little endian). Read lower 128bits. */
3374 status = regcache_raw_read (regcache,
3375 I387_XMM0_REGNUM (tdep) + regnum,
3377 if (status != REG_VALID)
3378 mark_value_bytes_unavailable (result_value, 0, 16);
3380 memcpy (buf, raw_buf, 16);
3381 /* Read upper 128bits. */
3382 status = regcache_raw_read (regcache,
3383 tdep->ymm0h_regnum + regnum,
3385 if (status != REG_VALID)
3386 mark_value_bytes_unavailable (result_value, 16, 32);
3388 memcpy (buf + 16, raw_buf, 16);
3390 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3392 regnum -= tdep->ymm16_regnum;
3393 /* Extract (always little endian). Read lower 128bits. */
3394 status = regcache_raw_read (regcache,
3395 I387_XMM16_REGNUM (tdep) + regnum,
3397 if (status != REG_VALID)
3398 mark_value_bytes_unavailable (result_value, 0, 16);
3400 memcpy (buf, raw_buf, 16);
3401 /* Read upper 128bits. */
3402 status = regcache_raw_read (regcache,
3403 tdep->ymm16h_regnum + regnum,
3405 if (status != REG_VALID)
3406 mark_value_bytes_unavailable (result_value, 16, 16);
3408 memcpy (buf + 16, raw_buf, 16);
3410 else if (i386_word_regnum_p (gdbarch, regnum))
3412 int gpnum = regnum - tdep->ax_regnum;
3414 /* Extract (always little endian). */
3415 status = regcache_raw_read (regcache, gpnum, raw_buf);
3416 if (status != REG_VALID)
3417 mark_value_bytes_unavailable (result_value, 0,
3418 TYPE_LENGTH (value_type (result_value)));
3420 memcpy (buf, raw_buf, 2);
3422 else if (i386_byte_regnum_p (gdbarch, regnum))
3424 int gpnum = regnum - tdep->al_regnum;
3426 /* Extract (always little endian). We read both lower and
3428 status = regcache_raw_read (regcache, gpnum % 4, raw_buf);
3429 if (status != REG_VALID)
3430 mark_value_bytes_unavailable (result_value, 0,
3431 TYPE_LENGTH (value_type (result_value)));
3432 else if (gpnum >= 4)
3433 memcpy (buf, raw_buf + 1, 1);
3435 memcpy (buf, raw_buf, 1);
3438 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3442 static struct value *
3443 i386_pseudo_register_read_value (struct gdbarch *gdbarch,
3444 struct regcache *regcache,
3447 struct value *result;
3449 result = allocate_value (register_type (gdbarch, regnum));
3450 VALUE_LVAL (result) = lval_register;
3451 VALUE_REGNUM (result) = regnum;
3453 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result);
3459 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3460 int regnum, const gdb_byte *buf)
3462 gdb_byte raw_buf[MAX_REGISTER_SIZE];
3464 if (i386_mmx_regnum_p (gdbarch, regnum))
3466 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3469 regcache_raw_read (regcache, fpnum, raw_buf);
3470 /* ... Modify ... (always little endian). */
3471 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
3473 regcache_raw_write (regcache, fpnum, raw_buf);
3477 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3479 if (i386_bnd_regnum_p (gdbarch, regnum))
3481 ULONGEST upper, lower;
3482 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3483 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3485 /* New values from input value. */
3486 regnum -= tdep->bnd0_regnum;
3487 lower = extract_unsigned_integer (buf, size, byte_order);
3488 upper = extract_unsigned_integer (buf + size, size, byte_order);
3490 /* Fetching register buffer. */
3491 regcache_raw_read (regcache,
3492 I387_BND0R_REGNUM (tdep) + regnum,
3497 /* Set register bits. */
3498 memcpy (raw_buf, &lower, 8);
3499 memcpy (raw_buf + 8, &upper, 8);
3502 regcache_raw_write (regcache,
3503 I387_BND0R_REGNUM (tdep) + regnum,
3506 else if (i386_k_regnum_p (gdbarch, regnum))
3508 regnum -= tdep->k0_regnum;
3510 regcache_raw_write (regcache,
3511 tdep->k0_regnum + regnum,
3514 else if (i386_zmm_regnum_p (gdbarch, regnum))
3516 regnum -= tdep->zmm0_regnum;
3518 if (regnum < num_lower_zmm_regs)
3520 /* Write lower 128bits. */
3521 regcache_raw_write (regcache,
3522 I387_XMM0_REGNUM (tdep) + regnum,
3524 /* Write upper 128bits. */
3525 regcache_raw_write (regcache,
3526 I387_YMM0_REGNUM (tdep) + regnum,
3531 /* Write lower 128bits. */
3532 regcache_raw_write (regcache,
3533 I387_XMM16_REGNUM (tdep) + regnum
3534 - num_lower_zmm_regs,
3536 /* Write upper 128bits. */
3537 regcache_raw_write (regcache,
3538 I387_YMM16H_REGNUM (tdep) + regnum
3539 - num_lower_zmm_regs,
3542 /* Write upper 256bits. */
3543 regcache_raw_write (regcache,
3544 tdep->zmm0h_regnum + regnum,
3547 else if (i386_ymm_regnum_p (gdbarch, regnum))
3549 regnum -= tdep->ymm0_regnum;
3551 /* ... Write lower 128bits. */
3552 regcache_raw_write (regcache,
3553 I387_XMM0_REGNUM (tdep) + regnum,
3555 /* ... Write upper 128bits. */
3556 regcache_raw_write (regcache,
3557 tdep->ymm0h_regnum + regnum,
3560 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3562 regnum -= tdep->ymm16_regnum;
3564 /* ... Write lower 128bits. */
3565 regcache_raw_write (regcache,
3566 I387_XMM16_REGNUM (tdep) + regnum,
3568 /* ... Write upper 128bits. */
3569 regcache_raw_write (regcache,
3570 tdep->ymm16h_regnum + regnum,
3573 else if (i386_word_regnum_p (gdbarch, regnum))
3575 int gpnum = regnum - tdep->ax_regnum;
3578 regcache_raw_read (regcache, gpnum, raw_buf);
3579 /* ... Modify ... (always little endian). */
3580 memcpy (raw_buf, buf, 2);
3582 regcache_raw_write (regcache, gpnum, raw_buf);
3584 else if (i386_byte_regnum_p (gdbarch, regnum))
3586 int gpnum = regnum - tdep->al_regnum;
3588 /* Read ... We read both lower and upper registers. */
3589 regcache_raw_read (regcache, gpnum % 4, raw_buf);
3590 /* ... Modify ... (always little endian). */
3592 memcpy (raw_buf + 1, buf, 1);
3594 memcpy (raw_buf, buf, 1);
3596 regcache_raw_write (regcache, gpnum % 4, raw_buf);
3599 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3603 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
3606 i386_ax_pseudo_register_collect (struct gdbarch *gdbarch,
3607 struct agent_expr *ax, int regnum)
3609 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3611 if (i386_mmx_regnum_p (gdbarch, regnum))
3613 /* MMX to FPU register mapping depends on current TOS. Let's just
3614 not care and collect everything... */
3617 ax_reg_mask (ax, I387_FSTAT_REGNUM (tdep));
3618 for (i = 0; i < 8; i++)
3619 ax_reg_mask (ax, I387_ST0_REGNUM (tdep) + i);
3622 else if (i386_bnd_regnum_p (gdbarch, regnum))
3624 regnum -= tdep->bnd0_regnum;
3625 ax_reg_mask (ax, I387_BND0R_REGNUM (tdep) + regnum);
3628 else if (i386_k_regnum_p (gdbarch, regnum))
3630 regnum -= tdep->k0_regnum;
3631 ax_reg_mask (ax, tdep->k0_regnum + regnum);
3634 else if (i386_zmm_regnum_p (gdbarch, regnum))
3636 regnum -= tdep->zmm0_regnum;
3637 if (regnum < num_lower_zmm_regs)
3639 ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum);
3640 ax_reg_mask (ax, tdep->ymm0h_regnum + regnum);
3644 ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum
3645 - num_lower_zmm_regs);
3646 ax_reg_mask (ax, I387_YMM16H_REGNUM (tdep) + regnum
3647 - num_lower_zmm_regs);
3649 ax_reg_mask (ax, tdep->zmm0h_regnum + regnum);
3652 else if (i386_ymm_regnum_p (gdbarch, regnum))
3654 regnum -= tdep->ymm0_regnum;
3655 ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum);
3656 ax_reg_mask (ax, tdep->ymm0h_regnum + regnum);
3659 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3661 regnum -= tdep->ymm16_regnum;
3662 ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum);
3663 ax_reg_mask (ax, tdep->ymm16h_regnum + regnum);
3666 else if (i386_word_regnum_p (gdbarch, regnum))
3668 int gpnum = regnum - tdep->ax_regnum;
3670 ax_reg_mask (ax, gpnum);
3673 else if (i386_byte_regnum_p (gdbarch, regnum))
3675 int gpnum = regnum - tdep->al_regnum;
3677 ax_reg_mask (ax, gpnum % 4);
3681 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3686 /* Return the register number of the register allocated by GCC after
3687 REGNUM, or -1 if there is no such register. */
3690 i386_next_regnum (int regnum)
3692 /* GCC allocates the registers in the order:
3694 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3696 Since storing a variable in %esp doesn't make any sense we return
3697 -1 for %ebp and for %esp itself. */
3698 static int next_regnum[] =
3700 I386_EDX_REGNUM, /* Slot for %eax. */
3701 I386_EBX_REGNUM, /* Slot for %ecx. */
3702 I386_ECX_REGNUM, /* Slot for %edx. */
3703 I386_ESI_REGNUM, /* Slot for %ebx. */
3704 -1, -1, /* Slots for %esp and %ebp. */
3705 I386_EDI_REGNUM, /* Slot for %esi. */
3706 I386_EBP_REGNUM /* Slot for %edi. */
3709 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
3710 return next_regnum[regnum];
3715 /* Return nonzero if a value of type TYPE stored in register REGNUM
3716 needs any special handling. */
3719 i386_convert_register_p (struct gdbarch *gdbarch,
3720 int regnum, struct type *type)
3722 int len = TYPE_LENGTH (type);
3724 /* Values may be spread across multiple registers. Most debugging
3725 formats aren't expressive enough to specify the locations, so
3726 some heuristics is involved. Right now we only handle types that
3727 have a length that is a multiple of the word size, since GCC
3728 doesn't seem to put any other types into registers. */
3729 if (len > 4 && len % 4 == 0)
3731 int last_regnum = regnum;
3735 last_regnum = i386_next_regnum (last_regnum);
3739 if (last_regnum != -1)
3743 return i387_convert_register_p (gdbarch, regnum, type);
3746 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3747 return its contents in TO. */
3750 i386_register_to_value (struct frame_info *frame, int regnum,
3751 struct type *type, gdb_byte *to,
3752 int *optimizedp, int *unavailablep)
3754 struct gdbarch *gdbarch = get_frame_arch (frame);
3755 int len = TYPE_LENGTH (type);
3757 if (i386_fp_regnum_p (gdbarch, regnum))
3758 return i387_register_to_value (frame, regnum, type, to,
3759 optimizedp, unavailablep);
3761 /* Read a value spread across multiple registers. */
3763 gdb_assert (len > 4 && len % 4 == 0);
3767 gdb_assert (regnum != -1);
3768 gdb_assert (register_size (gdbarch, regnum) == 4);
3770 if (!get_frame_register_bytes (frame, regnum, 0,
3771 register_size (gdbarch, regnum),
3772 to, optimizedp, unavailablep))
3775 regnum = i386_next_regnum (regnum);
3780 *optimizedp = *unavailablep = 0;
3784 /* Write the contents FROM of a value of type TYPE into register
3785 REGNUM in frame FRAME. */
3788 i386_value_to_register (struct frame_info *frame, int regnum,
3789 struct type *type, const gdb_byte *from)
3791 int len = TYPE_LENGTH (type);
3793 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
3795 i387_value_to_register (frame, regnum, type, from);
3799 /* Write a value spread across multiple registers. */
3801 gdb_assert (len > 4 && len % 4 == 0);
3805 gdb_assert (regnum != -1);
3806 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
3808 put_frame_register (frame, regnum, from);
3809 regnum = i386_next_regnum (regnum);
3815 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3816 in the general-purpose register set REGSET to register cache
3817 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3820 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
3821 int regnum, const void *gregs, size_t len)
3823 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3824 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3825 const gdb_byte *regs = (const gdb_byte *) gregs;
3828 gdb_assert (len >= tdep->sizeof_gregset);
3830 for (i = 0; i < tdep->gregset_num_regs; i++)
3832 if ((regnum == i || regnum == -1)
3833 && tdep->gregset_reg_offset[i] != -1)
3834 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
3838 /* Collect register REGNUM from the register cache REGCACHE and store
3839 it in the buffer specified by GREGS and LEN as described by the
3840 general-purpose register set REGSET. If REGNUM is -1, do this for
3841 all registers in REGSET. */
3844 i386_collect_gregset (const struct regset *regset,
3845 const struct regcache *regcache,
3846 int regnum, void *gregs, size_t len)
3848 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3849 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3850 gdb_byte *regs = (gdb_byte *) gregs;
3853 gdb_assert (len >= tdep->sizeof_gregset);
3855 for (i = 0; i < tdep->gregset_num_regs; i++)
3857 if ((regnum == i || regnum == -1)
3858 && tdep->gregset_reg_offset[i] != -1)
3859 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
3863 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3864 in the floating-point register set REGSET to register cache
3865 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3868 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
3869 int regnum, const void *fpregs, size_t len)
3871 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3872 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3874 if (len == I387_SIZEOF_FXSAVE)
3876 i387_supply_fxsave (regcache, regnum, fpregs);
3880 gdb_assert (len >= tdep->sizeof_fpregset);
3881 i387_supply_fsave (regcache, regnum, fpregs);
3884 /* Collect register REGNUM from the register cache REGCACHE and store
3885 it in the buffer specified by FPREGS and LEN as described by the
3886 floating-point register set REGSET. If REGNUM is -1, do this for
3887 all registers in REGSET. */
3890 i386_collect_fpregset (const struct regset *regset,
3891 const struct regcache *regcache,
3892 int regnum, void *fpregs, size_t len)
3894 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3895 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3897 if (len == I387_SIZEOF_FXSAVE)
3899 i387_collect_fxsave (regcache, regnum, fpregs);
3903 gdb_assert (len >= tdep->sizeof_fpregset);
3904 i387_collect_fsave (regcache, regnum, fpregs);
3907 /* Register set definitions. */
3909 const struct regset i386_gregset =
3911 NULL, i386_supply_gregset, i386_collect_gregset
3914 const struct regset i386_fpregset =
3916 NULL, i386_supply_fpregset, i386_collect_fpregset
3919 /* Default iterator over core file register note sections. */
3922 i386_iterate_over_regset_sections (struct gdbarch *gdbarch,
3923 iterate_over_regset_sections_cb *cb,
3925 const struct regcache *regcache)
3927 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3929 cb (".reg", tdep->sizeof_gregset, &i386_gregset, NULL, cb_data);
3930 if (tdep->sizeof_fpregset)
3931 cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
3935 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3938 i386_pe_skip_trampoline_code (struct frame_info *frame,
3939 CORE_ADDR pc, char *name)
3941 struct gdbarch *gdbarch = get_frame_arch (frame);
3942 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3945 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
3947 unsigned long indirect =
3948 read_memory_unsigned_integer (pc + 2, 4, byte_order);
3949 struct minimal_symbol *indsym =
3950 indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0;
3951 const char *symname = indsym ? MSYMBOL_LINKAGE_NAME (indsym) : 0;
3955 if (startswith (symname, "__imp_")
3956 || startswith (symname, "_imp_"))
3958 read_memory_unsigned_integer (indirect, 4, byte_order);
3961 return 0; /* Not a trampoline. */
3965 /* Return whether the THIS_FRAME corresponds to a sigtramp
3969 i386_sigtramp_p (struct frame_info *this_frame)
3971 CORE_ADDR pc = get_frame_pc (this_frame);
3974 find_pc_partial_function (pc, &name, NULL, NULL);
3975 return (name && strcmp ("_sigtramp", name) == 0);
3979 /* We have two flavours of disassembly. The machinery on this page
3980 deals with switching between those. */
3983 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
3985 gdb_assert (disassembly_flavor == att_flavor
3986 || disassembly_flavor == intel_flavor);
3988 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3989 constified, cast to prevent a compiler warning. */
3990 info->disassembler_options = (char *) disassembly_flavor;
3992 return print_insn_i386 (pc, info);
3996 /* There are a few i386 architecture variants that differ only
3997 slightly from the generic i386 target. For now, we don't give them
3998 their own source file, but include them here. As a consequence,
3999 they'll always be included. */
4001 /* System V Release 4 (SVR4). */
4003 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
4007 i386_svr4_sigtramp_p (struct frame_info *this_frame)
4009 CORE_ADDR pc = get_frame_pc (this_frame);
4012 /* The origin of these symbols is currently unknown. */
4013 find_pc_partial_function (pc, &name, NULL, NULL);
4014 return (name && (strcmp ("_sigreturn", name) == 0
4015 || strcmp ("sigvechandler", name) == 0));
4018 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
4019 address of the associated sigcontext (ucontext) structure. */
4022 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
4024 struct gdbarch *gdbarch = get_frame_arch (this_frame);
4025 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4029 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
4030 sp = extract_unsigned_integer (buf, 4, byte_order);
4032 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
4037 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
4041 i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s)
4043 return (*s == '$' /* Literal number. */
4044 || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */
4045 || (*s == '(' && s[1] == '%') /* Register indirection. */
4046 || (*s == '%' && isalpha (s[1]))); /* Register access. */
4049 /* Helper function for i386_stap_parse_special_token.
4051 This function parses operands of the form `-8+3+1(%rbp)', which
4052 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
4054 Return 1 if the operand was parsed successfully, zero
4058 i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch,
4059 struct stap_parse_info *p)
4061 const char *s = p->arg;
4063 if (isdigit (*s) || *s == '-' || *s == '+')
4067 long displacements[3];
4083 if (!isdigit ((unsigned char) *s))
4086 displacements[0] = strtol (s, &endp, 10);
4089 if (*s != '+' && *s != '-')
4091 /* We are not dealing with a triplet. */
4104 if (!isdigit ((unsigned char) *s))
4107 displacements[1] = strtol (s, &endp, 10);
4110 if (*s != '+' && *s != '-')
4112 /* We are not dealing with a triplet. */
4125 if (!isdigit ((unsigned char) *s))
4128 displacements[2] = strtol (s, &endp, 10);
4131 if (*s != '(' || s[1] != '%')
4137 while (isalnum (*s))
4143 len = s - start - 1;
4144 regname = (char *) alloca (len + 1);
4146 strncpy (regname, start, len);
4147 regname[len] = '\0';
4149 if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1)
4150 error (_("Invalid register name `%s' on expression `%s'."),
4151 regname, p->saved_arg);
4153 for (i = 0; i < 3; i++)
4155 write_exp_elt_opcode (&p->pstate, OP_LONG);
4157 (&p->pstate, builtin_type (gdbarch)->builtin_long);
4158 write_exp_elt_longcst (&p->pstate, displacements[i]);
4159 write_exp_elt_opcode (&p->pstate, OP_LONG);
4161 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4164 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4167 write_exp_string (&p->pstate, str);
4168 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4170 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4171 write_exp_elt_type (&p->pstate,
4172 builtin_type (gdbarch)->builtin_data_ptr);
4173 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4175 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4176 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4177 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4179 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4180 write_exp_elt_type (&p->pstate,
4181 lookup_pointer_type (p->arg_type));
4182 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4184 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4194 /* Helper function for i386_stap_parse_special_token.
4196 This function parses operands of the form `register base +
4197 (register index * size) + offset', as represented in
4198 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4200 Return 1 if the operand was parsed successfully, zero
4204 i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch,
4205 struct stap_parse_info *p)
4207 const char *s = p->arg;
4209 if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+')
4211 int offset_minus = 0;
4220 struct stoken base_token, index_token;
4230 if (offset_minus && !isdigit (*s))
4237 offset = strtol (s, &endp, 10);
4241 if (*s != '(' || s[1] != '%')
4247 while (isalnum (*s))
4250 if (*s != ',' || s[1] != '%')
4253 len_base = s - start;
4254 base = (char *) alloca (len_base + 1);
4255 strncpy (base, start, len_base);
4256 base[len_base] = '\0';
4258 if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1)
4259 error (_("Invalid register name `%s' on expression `%s'."),
4260 base, p->saved_arg);
4265 while (isalnum (*s))
4268 len_index = s - start;
4269 index = (char *) alloca (len_index + 1);
4270 strncpy (index, start, len_index);
4271 index[len_index] = '\0';
4273 if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1)
4274 error (_("Invalid register name `%s' on expression `%s'."),
4275 index, p->saved_arg);
4277 if (*s != ',' && *s != ')')
4293 size = strtol (s, &endp, 10);
4304 write_exp_elt_opcode (&p->pstate, OP_LONG);
4305 write_exp_elt_type (&p->pstate,
4306 builtin_type (gdbarch)->builtin_long);
4307 write_exp_elt_longcst (&p->pstate, offset);
4308 write_exp_elt_opcode (&p->pstate, OP_LONG);
4310 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4313 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4314 base_token.ptr = base;
4315 base_token.length = len_base;
4316 write_exp_string (&p->pstate, base_token);
4317 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4320 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4322 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4323 index_token.ptr = index;
4324 index_token.length = len_index;
4325 write_exp_string (&p->pstate, index_token);
4326 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4330 write_exp_elt_opcode (&p->pstate, OP_LONG);
4331 write_exp_elt_type (&p->pstate,
4332 builtin_type (gdbarch)->builtin_long);
4333 write_exp_elt_longcst (&p->pstate, size);
4334 write_exp_elt_opcode (&p->pstate, OP_LONG);
4336 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4337 write_exp_elt_opcode (&p->pstate, BINOP_MUL);
4340 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4342 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4343 write_exp_elt_type (&p->pstate,
4344 lookup_pointer_type (p->arg_type));
4345 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4347 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4357 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4361 i386_stap_parse_special_token (struct gdbarch *gdbarch,
4362 struct stap_parse_info *p)
4364 /* In order to parse special tokens, we use a state-machine that go
4365 through every known token and try to get a match. */
4369 THREE_ARG_DISPLACEMENT,
4374 current_state = TRIPLET;
4376 /* The special tokens to be parsed here are:
4378 - `register base + (register index * size) + offset', as represented
4379 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4381 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4382 `*(-8 + 3 - 1 + (void *) $eax)'. */
4384 while (current_state != DONE)
4386 switch (current_state)
4389 if (i386_stap_parse_special_token_triplet (gdbarch, p))
4393 case THREE_ARG_DISPLACEMENT:
4394 if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p))
4399 /* Advancing to the next state. */
4408 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always
4409 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */
4412 i386_gnu_triplet_regexp (struct gdbarch *gdbarch)
4414 return "(x86_64|i.86)";
4422 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4424 static const char *const stap_integer_prefixes[] = { "$", NULL };
4425 static const char *const stap_register_prefixes[] = { "%", NULL };
4426 static const char *const stap_register_indirection_prefixes[] = { "(",
4428 static const char *const stap_register_indirection_suffixes[] = { ")",
4431 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4432 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4434 /* Registering SystemTap handlers. */
4435 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
4436 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
4437 set_gdbarch_stap_register_indirection_prefixes (gdbarch,
4438 stap_register_indirection_prefixes);
4439 set_gdbarch_stap_register_indirection_suffixes (gdbarch,
4440 stap_register_indirection_suffixes);
4441 set_gdbarch_stap_is_single_operand (gdbarch,
4442 i386_stap_is_single_operand);
4443 set_gdbarch_stap_parse_special_token (gdbarch,
4444 i386_stap_parse_special_token);
4446 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
4449 /* System V Release 4 (SVR4). */
4452 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4454 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4456 /* System V Release 4 uses ELF. */
4457 i386_elf_init_abi (info, gdbarch);
4459 /* System V Release 4 has shared libraries. */
4460 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
4462 tdep->sigtramp_p = i386_svr4_sigtramp_p;
4463 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
4464 tdep->sc_pc_offset = 36 + 14 * 4;
4465 tdep->sc_sp_offset = 36 + 17 * 4;
4467 tdep->jb_pc_offset = 20;
4473 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4475 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4477 /* DJGPP doesn't have any special frames for signal handlers. */
4478 tdep->sigtramp_p = NULL;
4480 tdep->jb_pc_offset = 36;
4482 /* DJGPP does not support the SSE registers. */
4483 if (! tdesc_has_registers (info.target_desc))
4484 tdep->tdesc = tdesc_i386_mmx;
4486 /* Native compiler is GCC, which uses the SVR4 register numbering
4487 even in COFF and STABS. See the comment in i386_gdbarch_init,
4488 before the calls to set_gdbarch_stab_reg_to_regnum and
4489 set_gdbarch_sdb_reg_to_regnum. */
4490 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4491 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4493 set_gdbarch_has_dos_based_file_system (gdbarch, 1);
4495 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
4499 /* i386 register groups. In addition to the normal groups, add "mmx"
4502 static struct reggroup *i386_sse_reggroup;
4503 static struct reggroup *i386_mmx_reggroup;
4506 i386_init_reggroups (void)
4508 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
4509 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
4513 i386_add_reggroups (struct gdbarch *gdbarch)
4515 reggroup_add (gdbarch, i386_sse_reggroup);
4516 reggroup_add (gdbarch, i386_mmx_reggroup);
4517 reggroup_add (gdbarch, general_reggroup);
4518 reggroup_add (gdbarch, float_reggroup);
4519 reggroup_add (gdbarch, all_reggroup);
4520 reggroup_add (gdbarch, save_reggroup);
4521 reggroup_add (gdbarch, restore_reggroup);
4522 reggroup_add (gdbarch, vector_reggroup);
4523 reggroup_add (gdbarch, system_reggroup);
4527 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
4528 struct reggroup *group)
4530 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4531 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
4532 ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p,
4533 bndr_regnum_p, bnd_regnum_p, k_regnum_p, zmm_regnum_p, zmmh_regnum_p,
4534 zmm_avx512_regnum_p, mpx_ctrl_regnum_p, xmm_avx512_regnum_p,
4535 avx512_p, avx_p, sse_p;
4537 /* Don't include pseudo registers, except for MMX, in any register
4539 if (i386_byte_regnum_p (gdbarch, regnum))
4542 if (i386_word_regnum_p (gdbarch, regnum))
4545 if (i386_dword_regnum_p (gdbarch, regnum))
4548 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
4549 if (group == i386_mmx_reggroup)
4550 return mmx_regnum_p;
4552 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
4553 xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum);
4554 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
4555 if (group == i386_sse_reggroup)
4556 return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p;
4558 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
4559 ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum);
4560 zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum);
4562 avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4563 == X86_XSTATE_AVX512_MASK);
4564 avx_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4565 == X86_XSTATE_AVX_MASK) && !avx512_p;
4566 sse_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4567 == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p;
4569 if (group == vector_reggroup)
4570 return (mmx_regnum_p
4571 || (zmm_regnum_p && avx512_p)
4572 || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p)
4573 || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p)
4576 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
4577 || i386_fpc_regnum_p (gdbarch, regnum));
4578 if (group == float_reggroup)
4581 /* For "info reg all", don't include upper YMM registers nor XMM
4582 registers when AVX is supported. */
4583 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
4584 ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum);
4585 zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum);
4586 if (group == all_reggroup
4587 && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p)
4588 || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p)
4590 || ymmh_avx512_regnum_p
4594 bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum);
4595 if (group == all_reggroup
4596 && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4597 return bnd_regnum_p;
4599 bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum);
4600 if (group == all_reggroup
4601 && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4604 mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum);
4605 if (group == all_reggroup
4606 && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4607 return mpx_ctrl_regnum_p;
4609 if (group == general_reggroup)
4610 return (!fp_regnum_p
4614 && !xmm_avx512_regnum_p
4617 && !ymm_avx512_regnum_p
4618 && !ymmh_avx512_regnum_p
4621 && !mpx_ctrl_regnum_p
4625 return default_register_reggroup_p (gdbarch, regnum, group);
4629 /* Get the ARGIth function argument for the current function. */
4632 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
4635 struct gdbarch *gdbarch = get_frame_arch (frame);
4636 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4637 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
4638 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
4641 #define PREFIX_REPZ 0x01
4642 #define PREFIX_REPNZ 0x02
4643 #define PREFIX_LOCK 0x04
4644 #define PREFIX_DATA 0x08
4645 #define PREFIX_ADDR 0x10
4657 /* i386 arith/logic operations */
4670 struct i386_record_s
4672 struct gdbarch *gdbarch;
4673 struct regcache *regcache;
4674 CORE_ADDR orig_addr;
4680 uint8_t mod, reg, rm;
4689 /* Parse the "modrm" part of the memory address irp->addr points at.
4690 Returns -1 if something goes wrong, 0 otherwise. */
4693 i386_record_modrm (struct i386_record_s *irp)
4695 struct gdbarch *gdbarch = irp->gdbarch;
4697 if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1))
4701 irp->mod = (irp->modrm >> 6) & 3;
4702 irp->reg = (irp->modrm >> 3) & 7;
4703 irp->rm = irp->modrm & 7;
4708 /* Extract the memory address that the current instruction writes to,
4709 and return it in *ADDR. Return -1 if something goes wrong. */
4712 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
4714 struct gdbarch *gdbarch = irp->gdbarch;
4715 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4720 if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM])
4727 uint8_t base = irp->rm;
4732 if (record_read_memory (gdbarch, irp->addr, &byte, 1))
4735 scale = (byte >> 6) & 3;
4736 index = ((byte >> 3) & 7) | irp->rex_x;
4744 if ((base & 7) == 5)
4747 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4750 *addr = extract_signed_integer (buf, 4, byte_order);
4751 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
4752 *addr += irp->addr + irp->rip_offset;
4756 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4759 *addr = (int8_t) buf[0];
4762 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4764 *addr = extract_signed_integer (buf, 4, byte_order);
4772 if (base == 4 && irp->popl_esp_hack)
4773 *addr += irp->popl_esp_hack;
4774 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
4777 if (irp->aflag == 2)
4782 *addr = (uint32_t) (offset64 + *addr);
4784 if (havesib && (index != 4 || scale != 0))
4786 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
4788 if (irp->aflag == 2)
4789 *addr += offset64 << scale;
4791 *addr = (uint32_t) (*addr + (offset64 << scale));
4796 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4797 address from 32-bit to 64-bit. */
4798 *addr = (uint32_t) *addr;
4809 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4812 *addr = extract_signed_integer (buf, 2, byte_order);
4818 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4821 *addr = (int8_t) buf[0];
4824 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4827 *addr = extract_signed_integer (buf, 2, byte_order);
4834 regcache_raw_read_unsigned (irp->regcache,
4835 irp->regmap[X86_RECORD_REBX_REGNUM],
4837 *addr = (uint32_t) (*addr + offset64);
4838 regcache_raw_read_unsigned (irp->regcache,
4839 irp->regmap[X86_RECORD_RESI_REGNUM],
4841 *addr = (uint32_t) (*addr + offset64);
4844 regcache_raw_read_unsigned (irp->regcache,
4845 irp->regmap[X86_RECORD_REBX_REGNUM],
4847 *addr = (uint32_t) (*addr + offset64);
4848 regcache_raw_read_unsigned (irp->regcache,
4849 irp->regmap[X86_RECORD_REDI_REGNUM],
4851 *addr = (uint32_t) (*addr + offset64);
4854 regcache_raw_read_unsigned (irp->regcache,
4855 irp->regmap[X86_RECORD_REBP_REGNUM],
4857 *addr = (uint32_t) (*addr + offset64);
4858 regcache_raw_read_unsigned (irp->regcache,
4859 irp->regmap[X86_RECORD_RESI_REGNUM],
4861 *addr = (uint32_t) (*addr + offset64);
4864 regcache_raw_read_unsigned (irp->regcache,
4865 irp->regmap[X86_RECORD_REBP_REGNUM],
4867 *addr = (uint32_t) (*addr + offset64);
4868 regcache_raw_read_unsigned (irp->regcache,
4869 irp->regmap[X86_RECORD_REDI_REGNUM],
4871 *addr = (uint32_t) (*addr + offset64);
4874 regcache_raw_read_unsigned (irp->regcache,
4875 irp->regmap[X86_RECORD_RESI_REGNUM],
4877 *addr = (uint32_t) (*addr + offset64);
4880 regcache_raw_read_unsigned (irp->regcache,
4881 irp->regmap[X86_RECORD_REDI_REGNUM],
4883 *addr = (uint32_t) (*addr + offset64);
4886 regcache_raw_read_unsigned (irp->regcache,
4887 irp->regmap[X86_RECORD_REBP_REGNUM],
4889 *addr = (uint32_t) (*addr + offset64);
4892 regcache_raw_read_unsigned (irp->regcache,
4893 irp->regmap[X86_RECORD_REBX_REGNUM],
4895 *addr = (uint32_t) (*addr + offset64);
4905 /* Record the address and contents of the memory that will be changed
4906 by the current instruction. Return -1 if something goes wrong, 0
4910 i386_record_lea_modrm (struct i386_record_s *irp)
4912 struct gdbarch *gdbarch = irp->gdbarch;
4915 if (irp->override >= 0)
4917 if (record_full_memory_query)
4920 Process record ignores the memory change of instruction at address %s\n\
4921 because it can't get the value of the segment register.\n\
4922 Do you want to stop the program?"),
4923 paddress (gdbarch, irp->orig_addr)))
4930 if (i386_record_lea_modrm_addr (irp, &addr))
4933 if (record_full_arch_list_add_mem (addr, 1 << irp->ot))
4939 /* Record the effects of a push operation. Return -1 if something
4940 goes wrong, 0 otherwise. */
4943 i386_record_push (struct i386_record_s *irp, int size)
4947 if (record_full_arch_list_add_reg (irp->regcache,
4948 irp->regmap[X86_RECORD_RESP_REGNUM]))
4950 regcache_raw_read_unsigned (irp->regcache,
4951 irp->regmap[X86_RECORD_RESP_REGNUM],
4953 if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size))
4960 /* Defines contents to record. */
4961 #define I386_SAVE_FPU_REGS 0xfffd
4962 #define I386_SAVE_FPU_ENV 0xfffe
4963 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4965 /* Record the values of the floating point registers which will be
4966 changed by the current instruction. Returns -1 if something is
4967 wrong, 0 otherwise. */
4969 static int i386_record_floats (struct gdbarch *gdbarch,
4970 struct i386_record_s *ir,
4973 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4976 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4977 happen. Currently we store st0-st7 registers, but we need not store all
4978 registers all the time, in future we use ftag register and record only
4979 those who are not marked as an empty. */
4981 if (I386_SAVE_FPU_REGS == iregnum)
4983 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
4985 if (record_full_arch_list_add_reg (ir->regcache, i))
4989 else if (I386_SAVE_FPU_ENV == iregnum)
4991 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4993 if (record_full_arch_list_add_reg (ir->regcache, i))
4997 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
4999 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
5001 if (record_full_arch_list_add_reg (ir->regcache, i))
5005 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
5006 (iregnum <= I387_FOP_REGNUM (tdep)))
5008 if (record_full_arch_list_add_reg (ir->regcache,iregnum))
5013 /* Parameter error. */
5016 if(I386_SAVE_FPU_ENV != iregnum)
5018 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
5020 if (record_full_arch_list_add_reg (ir->regcache, i))
5027 /* Parse the current instruction, and record the values of the
5028 registers and memory that will be changed by the current
5029 instruction. Returns -1 if something goes wrong, 0 otherwise. */
5031 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
5032 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
5035 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
5036 CORE_ADDR input_addr)
5038 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5044 gdb_byte buf[MAX_REGISTER_SIZE];
5045 struct i386_record_s ir;
5046 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5050 memset (&ir, 0, sizeof (struct i386_record_s));
5051 ir.regcache = regcache;
5052 ir.addr = input_addr;
5053 ir.orig_addr = input_addr;
5057 ir.popl_esp_hack = 0;
5058 ir.regmap = tdep->record_regmap;
5059 ir.gdbarch = gdbarch;
5061 if (record_debug > 1)
5062 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
5064 paddress (gdbarch, ir.addr));
5069 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5072 switch (opcode8) /* Instruction prefixes */
5074 case REPE_PREFIX_OPCODE:
5075 prefixes |= PREFIX_REPZ;
5077 case REPNE_PREFIX_OPCODE:
5078 prefixes |= PREFIX_REPNZ;
5080 case LOCK_PREFIX_OPCODE:
5081 prefixes |= PREFIX_LOCK;
5083 case CS_PREFIX_OPCODE:
5084 ir.override = X86_RECORD_CS_REGNUM;
5086 case SS_PREFIX_OPCODE:
5087 ir.override = X86_RECORD_SS_REGNUM;
5089 case DS_PREFIX_OPCODE:
5090 ir.override = X86_RECORD_DS_REGNUM;
5092 case ES_PREFIX_OPCODE:
5093 ir.override = X86_RECORD_ES_REGNUM;
5095 case FS_PREFIX_OPCODE:
5096 ir.override = X86_RECORD_FS_REGNUM;
5098 case GS_PREFIX_OPCODE:
5099 ir.override = X86_RECORD_GS_REGNUM;
5101 case DATA_PREFIX_OPCODE:
5102 prefixes |= PREFIX_DATA;
5104 case ADDR_PREFIX_OPCODE:
5105 prefixes |= PREFIX_ADDR;
5107 case 0x40: /* i386 inc %eax */
5108 case 0x41: /* i386 inc %ecx */
5109 case 0x42: /* i386 inc %edx */
5110 case 0x43: /* i386 inc %ebx */
5111 case 0x44: /* i386 inc %esp */
5112 case 0x45: /* i386 inc %ebp */
5113 case 0x46: /* i386 inc %esi */
5114 case 0x47: /* i386 inc %edi */
5115 case 0x48: /* i386 dec %eax */
5116 case 0x49: /* i386 dec %ecx */
5117 case 0x4a: /* i386 dec %edx */
5118 case 0x4b: /* i386 dec %ebx */
5119 case 0x4c: /* i386 dec %esp */
5120 case 0x4d: /* i386 dec %ebp */
5121 case 0x4e: /* i386 dec %esi */
5122 case 0x4f: /* i386 dec %edi */
5123 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
5126 rex_w = (opcode8 >> 3) & 1;
5127 rex_r = (opcode8 & 0x4) << 1;
5128 ir.rex_x = (opcode8 & 0x2) << 2;
5129 ir.rex_b = (opcode8 & 0x1) << 3;
5131 else /* 32 bit target */
5140 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
5146 if (prefixes & PREFIX_DATA)
5149 if (prefixes & PREFIX_ADDR)
5151 else if (ir.regmap[X86_RECORD_R8_REGNUM])
5154 /* Now check op code. */
5155 opcode = (uint32_t) opcode8;
5160 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5163 opcode = (uint32_t) opcode8 | 0x0f00;
5167 case 0x00: /* arith & logic */
5215 if (((opcode >> 3) & 7) != OP_CMPL)
5217 if ((opcode & 1) == 0)
5220 ir.ot = ir.dflag + OT_WORD;
5222 switch ((opcode >> 1) & 3)
5224 case 0: /* OP Ev, Gv */
5225 if (i386_record_modrm (&ir))
5229 if (i386_record_lea_modrm (&ir))
5235 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5237 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5240 case 1: /* OP Gv, Ev */
5241 if (i386_record_modrm (&ir))
5244 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5246 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5248 case 2: /* OP A, Iv */
5249 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5253 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5256 case 0x80: /* GRP1 */
5260 if (i386_record_modrm (&ir))
5263 if (ir.reg != OP_CMPL)
5265 if ((opcode & 1) == 0)
5268 ir.ot = ir.dflag + OT_WORD;
5275 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5276 if (i386_record_lea_modrm (&ir))
5280 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5282 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5285 case 0x40: /* inc */
5294 case 0x48: /* dec */
5303 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7);
5304 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5307 case 0xf6: /* GRP3 */
5309 if ((opcode & 1) == 0)
5312 ir.ot = ir.dflag + OT_WORD;
5313 if (i386_record_modrm (&ir))
5316 if (ir.mod != 3 && ir.reg == 0)
5317 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5322 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5328 if (i386_record_lea_modrm (&ir))
5334 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5336 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5338 if (ir.reg == 3) /* neg */
5339 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5345 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5346 if (ir.ot != OT_BYTE)
5347 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5348 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5352 opcode = opcode << 8 | ir.modrm;
5358 case 0xfe: /* GRP4 */
5359 case 0xff: /* GRP5 */
5360 if (i386_record_modrm (&ir))
5362 if (ir.reg >= 2 && opcode == 0xfe)
5365 opcode = opcode << 8 | ir.modrm;
5372 if ((opcode & 1) == 0)
5375 ir.ot = ir.dflag + OT_WORD;
5378 if (i386_record_lea_modrm (&ir))
5384 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5386 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5388 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5391 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5393 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5395 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5398 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5399 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5401 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5405 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5408 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5410 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5415 opcode = opcode << 8 | ir.modrm;
5421 case 0x84: /* test */
5425 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5428 case 0x98: /* CWDE/CBW */
5429 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5432 case 0x99: /* CDQ/CWD */
5433 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5434 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5437 case 0x0faf: /* imul */
5440 ir.ot = ir.dflag + OT_WORD;
5441 if (i386_record_modrm (&ir))
5444 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5445 else if (opcode == 0x6b)
5448 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5450 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5451 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5454 case 0x0fc0: /* xadd */
5456 if ((opcode & 1) == 0)
5459 ir.ot = ir.dflag + OT_WORD;
5460 if (i386_record_modrm (&ir))
5465 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5467 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5468 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5470 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5474 if (i386_record_lea_modrm (&ir))
5476 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5478 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5480 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5483 case 0x0fb0: /* cmpxchg */
5485 if ((opcode & 1) == 0)
5488 ir.ot = ir.dflag + OT_WORD;
5489 if (i386_record_modrm (&ir))
5494 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5495 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5497 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5501 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5502 if (i386_record_lea_modrm (&ir))
5505 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5508 case 0x0fc7: /* cmpxchg8b */
5509 if (i386_record_modrm (&ir))
5514 opcode = opcode << 8 | ir.modrm;
5517 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5518 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5519 if (i386_record_lea_modrm (&ir))
5521 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5524 case 0x50: /* push */
5534 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5536 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5540 case 0x06: /* push es */
5541 case 0x0e: /* push cs */
5542 case 0x16: /* push ss */
5543 case 0x1e: /* push ds */
5544 if (ir.regmap[X86_RECORD_R8_REGNUM])
5549 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5553 case 0x0fa0: /* push fs */
5554 case 0x0fa8: /* push gs */
5555 if (ir.regmap[X86_RECORD_R8_REGNUM])
5560 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5564 case 0x60: /* pusha */
5565 if (ir.regmap[X86_RECORD_R8_REGNUM])
5570 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
5574 case 0x58: /* pop */
5582 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5583 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5586 case 0x61: /* popa */
5587 if (ir.regmap[X86_RECORD_R8_REGNUM])
5592 for (regnum = X86_RECORD_REAX_REGNUM;
5593 regnum <= X86_RECORD_REDI_REGNUM;
5595 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5598 case 0x8f: /* pop */
5599 if (ir.regmap[X86_RECORD_R8_REGNUM])
5600 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
5602 ir.ot = ir.dflag + OT_WORD;
5603 if (i386_record_modrm (&ir))
5606 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5609 ir.popl_esp_hack = 1 << ir.ot;
5610 if (i386_record_lea_modrm (&ir))
5613 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5616 case 0xc8: /* enter */
5617 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5618 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5620 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5624 case 0xc9: /* leave */
5625 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5626 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5629 case 0x07: /* pop es */
5630 if (ir.regmap[X86_RECORD_R8_REGNUM])
5635 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5636 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
5637 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5640 case 0x17: /* pop ss */
5641 if (ir.regmap[X86_RECORD_R8_REGNUM])
5646 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5647 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
5648 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5651 case 0x1f: /* pop ds */
5652 if (ir.regmap[X86_RECORD_R8_REGNUM])
5657 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5658 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
5659 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5662 case 0x0fa1: /* pop fs */
5663 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5664 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
5665 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5668 case 0x0fa9: /* pop gs */
5669 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5670 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
5671 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5674 case 0x88: /* mov */
5678 if ((opcode & 1) == 0)
5681 ir.ot = ir.dflag + OT_WORD;
5683 if (i386_record_modrm (&ir))
5688 if (opcode == 0xc6 || opcode == 0xc7)
5689 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5690 if (i386_record_lea_modrm (&ir))
5695 if (opcode == 0xc6 || opcode == 0xc7)
5697 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5699 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5703 case 0x8a: /* mov */
5705 if ((opcode & 1) == 0)
5708 ir.ot = ir.dflag + OT_WORD;
5709 if (i386_record_modrm (&ir))
5712 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5714 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5717 case 0x8c: /* mov seg */
5718 if (i386_record_modrm (&ir))
5723 opcode = opcode << 8 | ir.modrm;
5728 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5732 if (i386_record_lea_modrm (&ir))
5737 case 0x8e: /* mov seg */
5738 if (i386_record_modrm (&ir))
5743 regnum = X86_RECORD_ES_REGNUM;
5746 regnum = X86_RECORD_SS_REGNUM;
5749 regnum = X86_RECORD_DS_REGNUM;
5752 regnum = X86_RECORD_FS_REGNUM;
5755 regnum = X86_RECORD_GS_REGNUM;
5759 opcode = opcode << 8 | ir.modrm;
5763 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5764 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5767 case 0x0fb6: /* movzbS */
5768 case 0x0fb7: /* movzwS */
5769 case 0x0fbe: /* movsbS */
5770 case 0x0fbf: /* movswS */
5771 if (i386_record_modrm (&ir))
5773 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5776 case 0x8d: /* lea */
5777 if (i386_record_modrm (&ir))
5782 opcode = opcode << 8 | ir.modrm;
5787 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5789 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5792 case 0xa0: /* mov EAX */
5795 case 0xd7: /* xlat */
5796 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5799 case 0xa2: /* mov EAX */
5801 if (ir.override >= 0)
5803 if (record_full_memory_query)
5806 Process record ignores the memory change of instruction at address %s\n\
5807 because it can't get the value of the segment register.\n\
5808 Do you want to stop the program?"),
5809 paddress (gdbarch, ir.orig_addr)))
5815 if ((opcode & 1) == 0)
5818 ir.ot = ir.dflag + OT_WORD;
5821 if (record_read_memory (gdbarch, ir.addr, buf, 8))
5824 addr = extract_unsigned_integer (buf, 8, byte_order);
5828 if (record_read_memory (gdbarch, ir.addr, buf, 4))
5831 addr = extract_unsigned_integer (buf, 4, byte_order);
5835 if (record_read_memory (gdbarch, ir.addr, buf, 2))
5838 addr = extract_unsigned_integer (buf, 2, byte_order);
5840 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
5845 case 0xb0: /* mov R, Ib */
5853 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
5854 ? ((opcode & 0x7) | ir.rex_b)
5855 : ((opcode & 0x7) & 0x3));
5858 case 0xb8: /* mov R, Iv */
5866 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5869 case 0x91: /* xchg R, EAX */
5876 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5877 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7);
5880 case 0x86: /* xchg Ev, Gv */
5882 if ((opcode & 1) == 0)
5885 ir.ot = ir.dflag + OT_WORD;
5886 if (i386_record_modrm (&ir))
5891 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5893 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5897 if (i386_record_lea_modrm (&ir))
5901 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5903 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5906 case 0xc4: /* les Gv */
5907 case 0xc5: /* lds Gv */
5908 if (ir.regmap[X86_RECORD_R8_REGNUM])
5914 case 0x0fb2: /* lss Gv */
5915 case 0x0fb4: /* lfs Gv */
5916 case 0x0fb5: /* lgs Gv */
5917 if (i386_record_modrm (&ir))
5925 opcode = opcode << 8 | ir.modrm;
5930 case 0xc4: /* les Gv */
5931 regnum = X86_RECORD_ES_REGNUM;
5933 case 0xc5: /* lds Gv */
5934 regnum = X86_RECORD_DS_REGNUM;
5936 case 0x0fb2: /* lss Gv */
5937 regnum = X86_RECORD_SS_REGNUM;
5939 case 0x0fb4: /* lfs Gv */
5940 regnum = X86_RECORD_FS_REGNUM;
5942 case 0x0fb5: /* lgs Gv */
5943 regnum = X86_RECORD_GS_REGNUM;
5946 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5947 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5948 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5951 case 0xc0: /* shifts */
5957 if ((opcode & 1) == 0)
5960 ir.ot = ir.dflag + OT_WORD;
5961 if (i386_record_modrm (&ir))
5963 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
5965 if (i386_record_lea_modrm (&ir))
5971 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5973 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5975 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5982 if (i386_record_modrm (&ir))
5986 if (record_full_arch_list_add_reg (ir.regcache, ir.rm))
5991 if (i386_record_lea_modrm (&ir))
5996 case 0xd8: /* Floats. */
6004 if (i386_record_modrm (&ir))
6006 ir.reg |= ((opcode & 7) << 3);
6012 if (i386_record_lea_modrm_addr (&ir, &addr64))
6020 /* For fcom, ficom nothing to do. */
6026 /* For fcomp, ficomp pop FPU stack, store all. */
6027 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6054 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
6055 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
6056 of code, always affects st(0) register. */
6057 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6081 /* Handling fld, fild. */
6082 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6086 switch (ir.reg >> 4)
6089 if (record_full_arch_list_add_mem (addr64, 4))
6093 if (record_full_arch_list_add_mem (addr64, 8))
6099 if (record_full_arch_list_add_mem (addr64, 2))
6105 switch (ir.reg >> 4)
6108 if (record_full_arch_list_add_mem (addr64, 4))
6110 if (3 == (ir.reg & 7))
6112 /* For fstp m32fp. */
6113 if (i386_record_floats (gdbarch, &ir,
6114 I386_SAVE_FPU_REGS))
6119 if (record_full_arch_list_add_mem (addr64, 4))
6121 if ((3 == (ir.reg & 7))
6122 || (5 == (ir.reg & 7))
6123 || (7 == (ir.reg & 7)))
6125 /* For fstp insn. */
6126 if (i386_record_floats (gdbarch, &ir,
6127 I386_SAVE_FPU_REGS))
6132 if (record_full_arch_list_add_mem (addr64, 8))
6134 if (3 == (ir.reg & 7))
6136 /* For fstp m64fp. */
6137 if (i386_record_floats (gdbarch, &ir,
6138 I386_SAVE_FPU_REGS))
6143 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
6145 /* For fistp, fbld, fild, fbstp. */
6146 if (i386_record_floats (gdbarch, &ir,
6147 I386_SAVE_FPU_REGS))
6152 if (record_full_arch_list_add_mem (addr64, 2))
6161 if (i386_record_floats (gdbarch, &ir,
6162 I386_SAVE_FPU_ENV_REG_STACK))
6167 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
6172 if (i386_record_floats (gdbarch, &ir,
6173 I386_SAVE_FPU_ENV_REG_STACK))
6179 if (record_full_arch_list_add_mem (addr64, 28))
6184 if (record_full_arch_list_add_mem (addr64, 14))
6190 if (record_full_arch_list_add_mem (addr64, 2))
6192 /* Insn fstp, fbstp. */
6193 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6198 if (record_full_arch_list_add_mem (addr64, 10))
6204 if (record_full_arch_list_add_mem (addr64, 28))
6210 if (record_full_arch_list_add_mem (addr64, 14))
6214 if (record_full_arch_list_add_mem (addr64, 80))
6217 if (i386_record_floats (gdbarch, &ir,
6218 I386_SAVE_FPU_ENV_REG_STACK))
6222 if (record_full_arch_list_add_mem (addr64, 8))
6225 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6230 opcode = opcode << 8 | ir.modrm;
6235 /* Opcode is an extension of modR/M byte. */
6241 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6245 if (0x0c == (ir.modrm >> 4))
6247 if ((ir.modrm & 0x0f) <= 7)
6249 if (i386_record_floats (gdbarch, &ir,
6250 I386_SAVE_FPU_REGS))
6255 if (i386_record_floats (gdbarch, &ir,
6256 I387_ST0_REGNUM (tdep)))
6258 /* If only st(0) is changing, then we have already
6260 if ((ir.modrm & 0x0f) - 0x08)
6262 if (i386_record_floats (gdbarch, &ir,
6263 I387_ST0_REGNUM (tdep) +
6264 ((ir.modrm & 0x0f) - 0x08)))
6282 if (i386_record_floats (gdbarch, &ir,
6283 I387_ST0_REGNUM (tdep)))
6301 if (i386_record_floats (gdbarch, &ir,
6302 I386_SAVE_FPU_REGS))
6306 if (i386_record_floats (gdbarch, &ir,
6307 I387_ST0_REGNUM (tdep)))
6309 if (i386_record_floats (gdbarch, &ir,
6310 I387_ST0_REGNUM (tdep) + 1))
6317 if (0xe9 == ir.modrm)
6319 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6322 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6324 if (i386_record_floats (gdbarch, &ir,
6325 I387_ST0_REGNUM (tdep)))
6327 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6329 if (i386_record_floats (gdbarch, &ir,
6330 I387_ST0_REGNUM (tdep) +
6334 else if ((ir.modrm & 0x0f) - 0x08)
6336 if (i386_record_floats (gdbarch, &ir,
6337 I387_ST0_REGNUM (tdep) +
6338 ((ir.modrm & 0x0f) - 0x08)))
6344 if (0xe3 == ir.modrm)
6346 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
6349 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6351 if (i386_record_floats (gdbarch, &ir,
6352 I387_ST0_REGNUM (tdep)))
6354 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6356 if (i386_record_floats (gdbarch, &ir,
6357 I387_ST0_REGNUM (tdep) +
6361 else if ((ir.modrm & 0x0f) - 0x08)
6363 if (i386_record_floats (gdbarch, &ir,
6364 I387_ST0_REGNUM (tdep) +
6365 ((ir.modrm & 0x0f) - 0x08)))
6371 if ((0x0c == ir.modrm >> 4)
6372 || (0x0d == ir.modrm >> 4)
6373 || (0x0f == ir.modrm >> 4))
6375 if ((ir.modrm & 0x0f) <= 7)
6377 if (i386_record_floats (gdbarch, &ir,
6378 I387_ST0_REGNUM (tdep) +
6384 if (i386_record_floats (gdbarch, &ir,
6385 I387_ST0_REGNUM (tdep) +
6386 ((ir.modrm & 0x0f) - 0x08)))
6392 if (0x0c == ir.modrm >> 4)
6394 if (i386_record_floats (gdbarch, &ir,
6395 I387_FTAG_REGNUM (tdep)))
6398 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6400 if ((ir.modrm & 0x0f) <= 7)
6402 if (i386_record_floats (gdbarch, &ir,
6403 I387_ST0_REGNUM (tdep) +
6409 if (i386_record_floats (gdbarch, &ir,
6410 I386_SAVE_FPU_REGS))
6416 if ((0x0c == ir.modrm >> 4)
6417 || (0x0e == ir.modrm >> 4)
6418 || (0x0f == ir.modrm >> 4)
6419 || (0xd9 == ir.modrm))
6421 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6426 if (0xe0 == ir.modrm)
6428 if (record_full_arch_list_add_reg (ir.regcache,
6432 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6434 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6442 case 0xa4: /* movsS */
6444 case 0xaa: /* stosS */
6446 case 0x6c: /* insS */
6448 regcache_raw_read_unsigned (ir.regcache,
6449 ir.regmap[X86_RECORD_RECX_REGNUM],
6455 if ((opcode & 1) == 0)
6458 ir.ot = ir.dflag + OT_WORD;
6459 regcache_raw_read_unsigned (ir.regcache,
6460 ir.regmap[X86_RECORD_REDI_REGNUM],
6463 regcache_raw_read_unsigned (ir.regcache,
6464 ir.regmap[X86_RECORD_ES_REGNUM],
6466 regcache_raw_read_unsigned (ir.regcache,
6467 ir.regmap[X86_RECORD_DS_REGNUM],
6469 if (ir.aflag && (es != ds))
6471 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6472 if (record_full_memory_query)
6475 Process record ignores the memory change of instruction at address %s\n\
6476 because it can't get the value of the segment register.\n\
6477 Do you want to stop the program?"),
6478 paddress (gdbarch, ir.orig_addr)))
6484 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
6488 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6489 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6490 if (opcode == 0xa4 || opcode == 0xa5)
6491 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6492 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6493 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6497 case 0xa6: /* cmpsS */
6499 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6500 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6501 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6502 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6503 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6506 case 0xac: /* lodsS */
6508 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6509 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6510 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6511 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6512 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6515 case 0xae: /* scasS */
6517 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6518 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6519 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6520 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6523 case 0x6e: /* outsS */
6525 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6526 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6527 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6528 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6531 case 0xe4: /* port I/O */
6535 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6536 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6546 case 0xc2: /* ret im */
6547 case 0xc3: /* ret */
6548 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6549 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6552 case 0xca: /* lret im */
6553 case 0xcb: /* lret */
6554 case 0xcf: /* iret */
6555 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6556 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6557 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6560 case 0xe8: /* call im */
6561 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6563 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6567 case 0x9a: /* lcall im */
6568 if (ir.regmap[X86_RECORD_R8_REGNUM])
6573 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6574 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6578 case 0xe9: /* jmp im */
6579 case 0xea: /* ljmp im */
6580 case 0xeb: /* jmp Jb */
6581 case 0x70: /* jcc Jb */
6597 case 0x0f80: /* jcc Jv */
6615 case 0x0f90: /* setcc Gv */
6631 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6633 if (i386_record_modrm (&ir))
6636 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
6640 if (i386_record_lea_modrm (&ir))
6645 case 0x0f40: /* cmov Gv, Ev */
6661 if (i386_record_modrm (&ir))
6664 if (ir.dflag == OT_BYTE)
6666 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
6670 case 0x9c: /* pushf */
6671 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6672 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6674 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6678 case 0x9d: /* popf */
6679 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6680 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6683 case 0x9e: /* sahf */
6684 if (ir.regmap[X86_RECORD_R8_REGNUM])
6690 case 0xf5: /* cmc */
6691 case 0xf8: /* clc */
6692 case 0xf9: /* stc */
6693 case 0xfc: /* cld */
6694 case 0xfd: /* std */
6695 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6698 case 0x9f: /* lahf */
6699 if (ir.regmap[X86_RECORD_R8_REGNUM])
6704 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6705 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6708 /* bit operations */
6709 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6710 ir.ot = ir.dflag + OT_WORD;
6711 if (i386_record_modrm (&ir))
6716 opcode = opcode << 8 | ir.modrm;
6722 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6725 if (i386_record_lea_modrm (&ir))
6729 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6732 case 0x0fa3: /* bt Gv, Ev */
6733 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6736 case 0x0fab: /* bts */
6737 case 0x0fb3: /* btr */
6738 case 0x0fbb: /* btc */
6739 ir.ot = ir.dflag + OT_WORD;
6740 if (i386_record_modrm (&ir))
6743 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6747 if (i386_record_lea_modrm_addr (&ir, &addr64))
6749 regcache_raw_read_unsigned (ir.regcache,
6750 ir.regmap[ir.reg | rex_r],
6755 addr64 += ((int16_t) addr >> 4) << 4;
6758 addr64 += ((int32_t) addr >> 5) << 5;
6761 addr64 += ((int64_t) addr >> 6) << 6;
6764 if (record_full_arch_list_add_mem (addr64, 1 << ir.ot))
6766 if (i386_record_lea_modrm (&ir))
6769 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6772 case 0x0fbc: /* bsf */
6773 case 0x0fbd: /* bsr */
6774 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6775 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6779 case 0x27: /* daa */
6780 case 0x2f: /* das */
6781 case 0x37: /* aaa */
6782 case 0x3f: /* aas */
6783 case 0xd4: /* aam */
6784 case 0xd5: /* aad */
6785 if (ir.regmap[X86_RECORD_R8_REGNUM])
6790 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6791 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6795 case 0x90: /* nop */
6796 if (prefixes & PREFIX_LOCK)
6803 case 0x9b: /* fwait */
6804 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
6806 opcode = (uint32_t) opcode8;
6812 case 0xcc: /* int3 */
6813 printf_unfiltered (_("Process record does not support instruction "
6820 case 0xcd: /* int */
6824 if (record_read_memory (gdbarch, ir.addr, &interrupt, 1))
6827 if (interrupt != 0x80
6828 || tdep->i386_intx80_record == NULL)
6830 printf_unfiltered (_("Process record does not support "
6831 "instruction int 0x%02x.\n"),
6836 ret = tdep->i386_intx80_record (ir.regcache);
6843 case 0xce: /* into */
6844 printf_unfiltered (_("Process record does not support "
6845 "instruction into.\n"));
6850 case 0xfa: /* cli */
6851 case 0xfb: /* sti */
6854 case 0x62: /* bound */
6855 printf_unfiltered (_("Process record does not support "
6856 "instruction bound.\n"));
6861 case 0x0fc8: /* bswap reg */
6869 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
6872 case 0xd6: /* salc */
6873 if (ir.regmap[X86_RECORD_R8_REGNUM])
6878 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6879 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6882 case 0xe0: /* loopnz */
6883 case 0xe1: /* loopz */
6884 case 0xe2: /* loop */
6885 case 0xe3: /* jecxz */
6886 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6887 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6890 case 0x0f30: /* wrmsr */
6891 printf_unfiltered (_("Process record does not support "
6892 "instruction wrmsr.\n"));
6897 case 0x0f32: /* rdmsr */
6898 printf_unfiltered (_("Process record does not support "
6899 "instruction rdmsr.\n"));
6904 case 0x0f31: /* rdtsc */
6905 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6906 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6909 case 0x0f34: /* sysenter */
6912 if (ir.regmap[X86_RECORD_R8_REGNUM])
6917 if (tdep->i386_sysenter_record == NULL)
6919 printf_unfiltered (_("Process record does not support "
6920 "instruction sysenter.\n"));
6924 ret = tdep->i386_sysenter_record (ir.regcache);
6930 case 0x0f35: /* sysexit */
6931 printf_unfiltered (_("Process record does not support "
6932 "instruction sysexit.\n"));
6937 case 0x0f05: /* syscall */
6940 if (tdep->i386_syscall_record == NULL)
6942 printf_unfiltered (_("Process record does not support "
6943 "instruction syscall.\n"));
6947 ret = tdep->i386_syscall_record (ir.regcache);
6953 case 0x0f07: /* sysret */
6954 printf_unfiltered (_("Process record does not support "
6955 "instruction sysret.\n"));
6960 case 0x0fa2: /* cpuid */
6961 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6962 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6963 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6964 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
6967 case 0xf4: /* hlt */
6968 printf_unfiltered (_("Process record does not support "
6969 "instruction hlt.\n"));
6975 if (i386_record_modrm (&ir))
6982 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6986 if (i386_record_lea_modrm (&ir))
6995 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6999 opcode = opcode << 8 | ir.modrm;
7006 if (i386_record_modrm (&ir))
7017 opcode = opcode << 8 | ir.modrm;
7020 if (ir.override >= 0)
7022 if (record_full_memory_query)
7025 Process record ignores the memory change of instruction at address %s\n\
7026 because it can't get the value of the segment register.\n\
7027 Do you want to stop the program?"),
7028 paddress (gdbarch, ir.orig_addr)))
7034 if (i386_record_lea_modrm_addr (&ir, &addr64))
7036 if (record_full_arch_list_add_mem (addr64, 2))
7039 if (ir.regmap[X86_RECORD_R8_REGNUM])
7041 if (record_full_arch_list_add_mem (addr64, 8))
7046 if (record_full_arch_list_add_mem (addr64, 4))
7057 case 0: /* monitor */
7060 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7064 opcode = opcode << 8 | ir.modrm;
7072 if (ir.override >= 0)
7074 if (record_full_memory_query)
7077 Process record ignores the memory change of instruction at address %s\n\
7078 because it can't get the value of the segment register.\n\
7079 Do you want to stop the program?"),
7080 paddress (gdbarch, ir.orig_addr)))
7088 if (i386_record_lea_modrm_addr (&ir, &addr64))
7090 if (record_full_arch_list_add_mem (addr64, 2))
7093 if (ir.regmap[X86_RECORD_R8_REGNUM])
7095 if (record_full_arch_list_add_mem (addr64, 8))
7100 if (record_full_arch_list_add_mem (addr64, 4))
7112 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7113 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7117 else if (ir.rm == 1)
7124 opcode = opcode << 8 | ir.modrm;
7131 if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
7137 if (i386_record_lea_modrm (&ir))
7140 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7143 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7145 case 7: /* invlpg */
7148 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
7149 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
7153 opcode = opcode << 8 | ir.modrm;
7158 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7162 opcode = opcode << 8 | ir.modrm;
7168 case 0x0f08: /* invd */
7169 case 0x0f09: /* wbinvd */
7172 case 0x63: /* arpl */
7173 if (i386_record_modrm (&ir))
7175 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
7177 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
7178 ? (ir.reg | rex_r) : ir.rm);
7182 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
7183 if (i386_record_lea_modrm (&ir))
7186 if (!ir.regmap[X86_RECORD_R8_REGNUM])
7187 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7190 case 0x0f02: /* lar */
7191 case 0x0f03: /* lsl */
7192 if (i386_record_modrm (&ir))
7194 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7195 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7199 if (i386_record_modrm (&ir))
7201 if (ir.mod == 3 && ir.reg == 3)
7204 opcode = opcode << 8 | ir.modrm;
7216 /* nop (multi byte) */
7219 case 0x0f20: /* mov reg, crN */
7220 case 0x0f22: /* mov crN, reg */
7221 if (i386_record_modrm (&ir))
7223 if ((ir.modrm & 0xc0) != 0xc0)
7226 opcode = opcode << 8 | ir.modrm;
7237 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7239 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7243 opcode = opcode << 8 | ir.modrm;
7249 case 0x0f21: /* mov reg, drN */
7250 case 0x0f23: /* mov drN, reg */
7251 if (i386_record_modrm (&ir))
7253 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
7254 || ir.reg == 5 || ir.reg >= 8)
7257 opcode = opcode << 8 | ir.modrm;
7261 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7263 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7266 case 0x0f06: /* clts */
7267 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7270 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7272 case 0x0f0d: /* 3DNow! prefetch */
7275 case 0x0f0e: /* 3DNow! femms */
7276 case 0x0f77: /* emms */
7277 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
7279 record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
7282 case 0x0f0f: /* 3DNow! data */
7283 if (i386_record_modrm (&ir))
7285 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7290 case 0x0c: /* 3DNow! pi2fw */
7291 case 0x0d: /* 3DNow! pi2fd */
7292 case 0x1c: /* 3DNow! pf2iw */
7293 case 0x1d: /* 3DNow! pf2id */
7294 case 0x8a: /* 3DNow! pfnacc */
7295 case 0x8e: /* 3DNow! pfpnacc */
7296 case 0x90: /* 3DNow! pfcmpge */
7297 case 0x94: /* 3DNow! pfmin */
7298 case 0x96: /* 3DNow! pfrcp */
7299 case 0x97: /* 3DNow! pfrsqrt */
7300 case 0x9a: /* 3DNow! pfsub */
7301 case 0x9e: /* 3DNow! pfadd */
7302 case 0xa0: /* 3DNow! pfcmpgt */
7303 case 0xa4: /* 3DNow! pfmax */
7304 case 0xa6: /* 3DNow! pfrcpit1 */
7305 case 0xa7: /* 3DNow! pfrsqit1 */
7306 case 0xaa: /* 3DNow! pfsubr */
7307 case 0xae: /* 3DNow! pfacc */
7308 case 0xb0: /* 3DNow! pfcmpeq */
7309 case 0xb4: /* 3DNow! pfmul */
7310 case 0xb6: /* 3DNow! pfrcpit2 */
7311 case 0xb7: /* 3DNow! pmulhrw */
7312 case 0xbb: /* 3DNow! pswapd */
7313 case 0xbf: /* 3DNow! pavgusb */
7314 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7315 goto no_support_3dnow_data;
7316 record_full_arch_list_add_reg (ir.regcache, ir.reg);
7320 no_support_3dnow_data:
7321 opcode = (opcode << 8) | opcode8;
7327 case 0x0faa: /* rsm */
7328 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7329 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7330 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
7331 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7332 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
7333 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
7334 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
7335 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
7336 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
7340 if (i386_record_modrm (&ir))
7344 case 0: /* fxsave */
7348 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7349 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
7351 if (record_full_arch_list_add_mem (tmpu64, 512))
7356 case 1: /* fxrstor */
7360 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7362 for (i = I387_MM0_REGNUM (tdep);
7363 i386_mmx_regnum_p (gdbarch, i); i++)
7364 record_full_arch_list_add_reg (ir.regcache, i);
7366 for (i = I387_XMM0_REGNUM (tdep);
7367 i386_xmm_regnum_p (gdbarch, i); i++)
7368 record_full_arch_list_add_reg (ir.regcache, i);
7370 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7371 record_full_arch_list_add_reg (ir.regcache,
7372 I387_MXCSR_REGNUM(tdep));
7374 for (i = I387_ST0_REGNUM (tdep);
7375 i386_fp_regnum_p (gdbarch, i); i++)
7376 record_full_arch_list_add_reg (ir.regcache, i);
7378 for (i = I387_FCTRL_REGNUM (tdep);
7379 i386_fpc_regnum_p (gdbarch, i); i++)
7380 record_full_arch_list_add_reg (ir.regcache, i);
7384 case 2: /* ldmxcsr */
7385 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7387 record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
7390 case 3: /* stmxcsr */
7392 if (i386_record_lea_modrm (&ir))
7396 case 5: /* lfence */
7397 case 6: /* mfence */
7398 case 7: /* sfence clflush */
7402 opcode = (opcode << 8) | ir.modrm;
7408 case 0x0fc3: /* movnti */
7409 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
7410 if (i386_record_modrm (&ir))
7415 if (i386_record_lea_modrm (&ir))
7419 /* Add prefix to opcode. */
7534 /* Mask out PREFIX_ADDR. */
7535 switch ((prefixes & ~PREFIX_ADDR))
7547 reswitch_prefix_add:
7555 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7558 opcode = (uint32_t) opcode8 | opcode << 8;
7559 goto reswitch_prefix_add;
7562 case 0x0f10: /* movups */
7563 case 0x660f10: /* movupd */
7564 case 0xf30f10: /* movss */
7565 case 0xf20f10: /* movsd */
7566 case 0x0f12: /* movlps */
7567 case 0x660f12: /* movlpd */
7568 case 0xf30f12: /* movsldup */
7569 case 0xf20f12: /* movddup */
7570 case 0x0f14: /* unpcklps */
7571 case 0x660f14: /* unpcklpd */
7572 case 0x0f15: /* unpckhps */
7573 case 0x660f15: /* unpckhpd */
7574 case 0x0f16: /* movhps */
7575 case 0x660f16: /* movhpd */
7576 case 0xf30f16: /* movshdup */
7577 case 0x0f28: /* movaps */
7578 case 0x660f28: /* movapd */
7579 case 0x0f2a: /* cvtpi2ps */
7580 case 0x660f2a: /* cvtpi2pd */
7581 case 0xf30f2a: /* cvtsi2ss */
7582 case 0xf20f2a: /* cvtsi2sd */
7583 case 0x0f2c: /* cvttps2pi */
7584 case 0x660f2c: /* cvttpd2pi */
7585 case 0x0f2d: /* cvtps2pi */
7586 case 0x660f2d: /* cvtpd2pi */
7587 case 0x660f3800: /* pshufb */
7588 case 0x660f3801: /* phaddw */
7589 case 0x660f3802: /* phaddd */
7590 case 0x660f3803: /* phaddsw */
7591 case 0x660f3804: /* pmaddubsw */
7592 case 0x660f3805: /* phsubw */
7593 case 0x660f3806: /* phsubd */
7594 case 0x660f3807: /* phsubsw */
7595 case 0x660f3808: /* psignb */
7596 case 0x660f3809: /* psignw */
7597 case 0x660f380a: /* psignd */
7598 case 0x660f380b: /* pmulhrsw */
7599 case 0x660f3810: /* pblendvb */
7600 case 0x660f3814: /* blendvps */
7601 case 0x660f3815: /* blendvpd */
7602 case 0x660f381c: /* pabsb */
7603 case 0x660f381d: /* pabsw */
7604 case 0x660f381e: /* pabsd */
7605 case 0x660f3820: /* pmovsxbw */
7606 case 0x660f3821: /* pmovsxbd */
7607 case 0x660f3822: /* pmovsxbq */
7608 case 0x660f3823: /* pmovsxwd */
7609 case 0x660f3824: /* pmovsxwq */
7610 case 0x660f3825: /* pmovsxdq */
7611 case 0x660f3828: /* pmuldq */
7612 case 0x660f3829: /* pcmpeqq */
7613 case 0x660f382a: /* movntdqa */
7614 case 0x660f3a08: /* roundps */
7615 case 0x660f3a09: /* roundpd */
7616 case 0x660f3a0a: /* roundss */
7617 case 0x660f3a0b: /* roundsd */
7618 case 0x660f3a0c: /* blendps */
7619 case 0x660f3a0d: /* blendpd */
7620 case 0x660f3a0e: /* pblendw */
7621 case 0x660f3a0f: /* palignr */
7622 case 0x660f3a20: /* pinsrb */
7623 case 0x660f3a21: /* insertps */
7624 case 0x660f3a22: /* pinsrd pinsrq */
7625 case 0x660f3a40: /* dpps */
7626 case 0x660f3a41: /* dppd */
7627 case 0x660f3a42: /* mpsadbw */
7628 case 0x660f3a60: /* pcmpestrm */
7629 case 0x660f3a61: /* pcmpestri */
7630 case 0x660f3a62: /* pcmpistrm */
7631 case 0x660f3a63: /* pcmpistri */
7632 case 0x0f51: /* sqrtps */
7633 case 0x660f51: /* sqrtpd */
7634 case 0xf20f51: /* sqrtsd */
7635 case 0xf30f51: /* sqrtss */
7636 case 0x0f52: /* rsqrtps */
7637 case 0xf30f52: /* rsqrtss */
7638 case 0x0f53: /* rcpps */
7639 case 0xf30f53: /* rcpss */
7640 case 0x0f54: /* andps */
7641 case 0x660f54: /* andpd */
7642 case 0x0f55: /* andnps */
7643 case 0x660f55: /* andnpd */
7644 case 0x0f56: /* orps */
7645 case 0x660f56: /* orpd */
7646 case 0x0f57: /* xorps */
7647 case 0x660f57: /* xorpd */
7648 case 0x0f58: /* addps */
7649 case 0x660f58: /* addpd */
7650 case 0xf20f58: /* addsd */
7651 case 0xf30f58: /* addss */
7652 case 0x0f59: /* mulps */
7653 case 0x660f59: /* mulpd */
7654 case 0xf20f59: /* mulsd */
7655 case 0xf30f59: /* mulss */
7656 case 0x0f5a: /* cvtps2pd */
7657 case 0x660f5a: /* cvtpd2ps */
7658 case 0xf20f5a: /* cvtsd2ss */
7659 case 0xf30f5a: /* cvtss2sd */
7660 case 0x0f5b: /* cvtdq2ps */
7661 case 0x660f5b: /* cvtps2dq */
7662 case 0xf30f5b: /* cvttps2dq */
7663 case 0x0f5c: /* subps */
7664 case 0x660f5c: /* subpd */
7665 case 0xf20f5c: /* subsd */
7666 case 0xf30f5c: /* subss */
7667 case 0x0f5d: /* minps */
7668 case 0x660f5d: /* minpd */
7669 case 0xf20f5d: /* minsd */
7670 case 0xf30f5d: /* minss */
7671 case 0x0f5e: /* divps */
7672 case 0x660f5e: /* divpd */
7673 case 0xf20f5e: /* divsd */
7674 case 0xf30f5e: /* divss */
7675 case 0x0f5f: /* maxps */
7676 case 0x660f5f: /* maxpd */
7677 case 0xf20f5f: /* maxsd */
7678 case 0xf30f5f: /* maxss */
7679 case 0x660f60: /* punpcklbw */
7680 case 0x660f61: /* punpcklwd */
7681 case 0x660f62: /* punpckldq */
7682 case 0x660f63: /* packsswb */
7683 case 0x660f64: /* pcmpgtb */
7684 case 0x660f65: /* pcmpgtw */
7685 case 0x660f66: /* pcmpgtd */
7686 case 0x660f67: /* packuswb */
7687 case 0x660f68: /* punpckhbw */
7688 case 0x660f69: /* punpckhwd */
7689 case 0x660f6a: /* punpckhdq */
7690 case 0x660f6b: /* packssdw */
7691 case 0x660f6c: /* punpcklqdq */
7692 case 0x660f6d: /* punpckhqdq */
7693 case 0x660f6e: /* movd */
7694 case 0x660f6f: /* movdqa */
7695 case 0xf30f6f: /* movdqu */
7696 case 0x660f70: /* pshufd */
7697 case 0xf20f70: /* pshuflw */
7698 case 0xf30f70: /* pshufhw */
7699 case 0x660f74: /* pcmpeqb */
7700 case 0x660f75: /* pcmpeqw */
7701 case 0x660f76: /* pcmpeqd */
7702 case 0x660f7c: /* haddpd */
7703 case 0xf20f7c: /* haddps */
7704 case 0x660f7d: /* hsubpd */
7705 case 0xf20f7d: /* hsubps */
7706 case 0xf30f7e: /* movq */
7707 case 0x0fc2: /* cmpps */
7708 case 0x660fc2: /* cmppd */
7709 case 0xf20fc2: /* cmpsd */
7710 case 0xf30fc2: /* cmpss */
7711 case 0x660fc4: /* pinsrw */
7712 case 0x0fc6: /* shufps */
7713 case 0x660fc6: /* shufpd */
7714 case 0x660fd0: /* addsubpd */
7715 case 0xf20fd0: /* addsubps */
7716 case 0x660fd1: /* psrlw */
7717 case 0x660fd2: /* psrld */
7718 case 0x660fd3: /* psrlq */
7719 case 0x660fd4: /* paddq */
7720 case 0x660fd5: /* pmullw */
7721 case 0xf30fd6: /* movq2dq */
7722 case 0x660fd8: /* psubusb */
7723 case 0x660fd9: /* psubusw */
7724 case 0x660fda: /* pminub */
7725 case 0x660fdb: /* pand */
7726 case 0x660fdc: /* paddusb */
7727 case 0x660fdd: /* paddusw */
7728 case 0x660fde: /* pmaxub */
7729 case 0x660fdf: /* pandn */
7730 case 0x660fe0: /* pavgb */
7731 case 0x660fe1: /* psraw */
7732 case 0x660fe2: /* psrad */
7733 case 0x660fe3: /* pavgw */
7734 case 0x660fe4: /* pmulhuw */
7735 case 0x660fe5: /* pmulhw */
7736 case 0x660fe6: /* cvttpd2dq */
7737 case 0xf20fe6: /* cvtpd2dq */
7738 case 0xf30fe6: /* cvtdq2pd */
7739 case 0x660fe8: /* psubsb */
7740 case 0x660fe9: /* psubsw */
7741 case 0x660fea: /* pminsw */
7742 case 0x660feb: /* por */
7743 case 0x660fec: /* paddsb */
7744 case 0x660fed: /* paddsw */
7745 case 0x660fee: /* pmaxsw */
7746 case 0x660fef: /* pxor */
7747 case 0xf20ff0: /* lddqu */
7748 case 0x660ff1: /* psllw */
7749 case 0x660ff2: /* pslld */
7750 case 0x660ff3: /* psllq */
7751 case 0x660ff4: /* pmuludq */
7752 case 0x660ff5: /* pmaddwd */
7753 case 0x660ff6: /* psadbw */
7754 case 0x660ff8: /* psubb */
7755 case 0x660ff9: /* psubw */
7756 case 0x660ffa: /* psubd */
7757 case 0x660ffb: /* psubq */
7758 case 0x660ffc: /* paddb */
7759 case 0x660ffd: /* paddw */
7760 case 0x660ffe: /* paddd */
7761 if (i386_record_modrm (&ir))
7764 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
7766 record_full_arch_list_add_reg (ir.regcache,
7767 I387_XMM0_REGNUM (tdep) + ir.reg);
7768 if ((opcode & 0xfffffffc) == 0x660f3a60)
7769 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7772 case 0x0f11: /* movups */
7773 case 0x660f11: /* movupd */
7774 case 0xf30f11: /* movss */
7775 case 0xf20f11: /* movsd */
7776 case 0x0f13: /* movlps */
7777 case 0x660f13: /* movlpd */
7778 case 0x0f17: /* movhps */
7779 case 0x660f17: /* movhpd */
7780 case 0x0f29: /* movaps */
7781 case 0x660f29: /* movapd */
7782 case 0x660f3a14: /* pextrb */
7783 case 0x660f3a15: /* pextrw */
7784 case 0x660f3a16: /* pextrd pextrq */
7785 case 0x660f3a17: /* extractps */
7786 case 0x660f7f: /* movdqa */
7787 case 0xf30f7f: /* movdqu */
7788 if (i386_record_modrm (&ir))
7792 if (opcode == 0x0f13 || opcode == 0x660f13
7793 || opcode == 0x0f17 || opcode == 0x660f17)
7796 if (!i386_xmm_regnum_p (gdbarch,
7797 I387_XMM0_REGNUM (tdep) + ir.rm))
7799 record_full_arch_list_add_reg (ir.regcache,
7800 I387_XMM0_REGNUM (tdep) + ir.rm);
7822 if (i386_record_lea_modrm (&ir))
7827 case 0x0f2b: /* movntps */
7828 case 0x660f2b: /* movntpd */
7829 case 0x0fe7: /* movntq */
7830 case 0x660fe7: /* movntdq */
7833 if (opcode == 0x0fe7)
7837 if (i386_record_lea_modrm (&ir))
7841 case 0xf30f2c: /* cvttss2si */
7842 case 0xf20f2c: /* cvttsd2si */
7843 case 0xf30f2d: /* cvtss2si */
7844 case 0xf20f2d: /* cvtsd2si */
7845 case 0xf20f38f0: /* crc32 */
7846 case 0xf20f38f1: /* crc32 */
7847 case 0x0f50: /* movmskps */
7848 case 0x660f50: /* movmskpd */
7849 case 0x0fc5: /* pextrw */
7850 case 0x660fc5: /* pextrw */
7851 case 0x0fd7: /* pmovmskb */
7852 case 0x660fd7: /* pmovmskb */
7853 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7856 case 0x0f3800: /* pshufb */
7857 case 0x0f3801: /* phaddw */
7858 case 0x0f3802: /* phaddd */
7859 case 0x0f3803: /* phaddsw */
7860 case 0x0f3804: /* pmaddubsw */
7861 case 0x0f3805: /* phsubw */
7862 case 0x0f3806: /* phsubd */
7863 case 0x0f3807: /* phsubsw */
7864 case 0x0f3808: /* psignb */
7865 case 0x0f3809: /* psignw */
7866 case 0x0f380a: /* psignd */
7867 case 0x0f380b: /* pmulhrsw */
7868 case 0x0f381c: /* pabsb */
7869 case 0x0f381d: /* pabsw */
7870 case 0x0f381e: /* pabsd */
7871 case 0x0f382b: /* packusdw */
7872 case 0x0f3830: /* pmovzxbw */
7873 case 0x0f3831: /* pmovzxbd */
7874 case 0x0f3832: /* pmovzxbq */
7875 case 0x0f3833: /* pmovzxwd */
7876 case 0x0f3834: /* pmovzxwq */
7877 case 0x0f3835: /* pmovzxdq */
7878 case 0x0f3837: /* pcmpgtq */
7879 case 0x0f3838: /* pminsb */
7880 case 0x0f3839: /* pminsd */
7881 case 0x0f383a: /* pminuw */
7882 case 0x0f383b: /* pminud */
7883 case 0x0f383c: /* pmaxsb */
7884 case 0x0f383d: /* pmaxsd */
7885 case 0x0f383e: /* pmaxuw */
7886 case 0x0f383f: /* pmaxud */
7887 case 0x0f3840: /* pmulld */
7888 case 0x0f3841: /* phminposuw */
7889 case 0x0f3a0f: /* palignr */
7890 case 0x0f60: /* punpcklbw */
7891 case 0x0f61: /* punpcklwd */
7892 case 0x0f62: /* punpckldq */
7893 case 0x0f63: /* packsswb */
7894 case 0x0f64: /* pcmpgtb */
7895 case 0x0f65: /* pcmpgtw */
7896 case 0x0f66: /* pcmpgtd */
7897 case 0x0f67: /* packuswb */
7898 case 0x0f68: /* punpckhbw */
7899 case 0x0f69: /* punpckhwd */
7900 case 0x0f6a: /* punpckhdq */
7901 case 0x0f6b: /* packssdw */
7902 case 0x0f6e: /* movd */
7903 case 0x0f6f: /* movq */
7904 case 0x0f70: /* pshufw */
7905 case 0x0f74: /* pcmpeqb */
7906 case 0x0f75: /* pcmpeqw */
7907 case 0x0f76: /* pcmpeqd */
7908 case 0x0fc4: /* pinsrw */
7909 case 0x0fd1: /* psrlw */
7910 case 0x0fd2: /* psrld */
7911 case 0x0fd3: /* psrlq */
7912 case 0x0fd4: /* paddq */
7913 case 0x0fd5: /* pmullw */
7914 case 0xf20fd6: /* movdq2q */
7915 case 0x0fd8: /* psubusb */
7916 case 0x0fd9: /* psubusw */
7917 case 0x0fda: /* pminub */
7918 case 0x0fdb: /* pand */
7919 case 0x0fdc: /* paddusb */
7920 case 0x0fdd: /* paddusw */
7921 case 0x0fde: /* pmaxub */
7922 case 0x0fdf: /* pandn */
7923 case 0x0fe0: /* pavgb */
7924 case 0x0fe1: /* psraw */
7925 case 0x0fe2: /* psrad */
7926 case 0x0fe3: /* pavgw */
7927 case 0x0fe4: /* pmulhuw */
7928 case 0x0fe5: /* pmulhw */
7929 case 0x0fe8: /* psubsb */
7930 case 0x0fe9: /* psubsw */
7931 case 0x0fea: /* pminsw */
7932 case 0x0feb: /* por */
7933 case 0x0fec: /* paddsb */
7934 case 0x0fed: /* paddsw */
7935 case 0x0fee: /* pmaxsw */
7936 case 0x0fef: /* pxor */
7937 case 0x0ff1: /* psllw */
7938 case 0x0ff2: /* pslld */
7939 case 0x0ff3: /* psllq */
7940 case 0x0ff4: /* pmuludq */
7941 case 0x0ff5: /* pmaddwd */
7942 case 0x0ff6: /* psadbw */
7943 case 0x0ff8: /* psubb */
7944 case 0x0ff9: /* psubw */
7945 case 0x0ffa: /* psubd */
7946 case 0x0ffb: /* psubq */
7947 case 0x0ffc: /* paddb */
7948 case 0x0ffd: /* paddw */
7949 case 0x0ffe: /* paddd */
7950 if (i386_record_modrm (&ir))
7952 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7954 record_full_arch_list_add_reg (ir.regcache,
7955 I387_MM0_REGNUM (tdep) + ir.reg);
7958 case 0x0f71: /* psllw */
7959 case 0x0f72: /* pslld */
7960 case 0x0f73: /* psllq */
7961 if (i386_record_modrm (&ir))
7963 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7965 record_full_arch_list_add_reg (ir.regcache,
7966 I387_MM0_REGNUM (tdep) + ir.rm);
7969 case 0x660f71: /* psllw */
7970 case 0x660f72: /* pslld */
7971 case 0x660f73: /* psllq */
7972 if (i386_record_modrm (&ir))
7975 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
7977 record_full_arch_list_add_reg (ir.regcache,
7978 I387_XMM0_REGNUM (tdep) + ir.rm);
7981 case 0x0f7e: /* movd */
7982 case 0x660f7e: /* movd */
7983 if (i386_record_modrm (&ir))
7986 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7993 if (i386_record_lea_modrm (&ir))
7998 case 0x0f7f: /* movq */
7999 if (i386_record_modrm (&ir))
8003 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
8005 record_full_arch_list_add_reg (ir.regcache,
8006 I387_MM0_REGNUM (tdep) + ir.rm);
8011 if (i386_record_lea_modrm (&ir))
8016 case 0xf30fb8: /* popcnt */
8017 if (i386_record_modrm (&ir))
8019 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
8020 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
8023 case 0x660fd6: /* movq */
8024 if (i386_record_modrm (&ir))
8029 if (!i386_xmm_regnum_p (gdbarch,
8030 I387_XMM0_REGNUM (tdep) + ir.rm))
8032 record_full_arch_list_add_reg (ir.regcache,
8033 I387_XMM0_REGNUM (tdep) + ir.rm);
8038 if (i386_record_lea_modrm (&ir))
8043 case 0x660f3817: /* ptest */
8044 case 0x0f2e: /* ucomiss */
8045 case 0x660f2e: /* ucomisd */
8046 case 0x0f2f: /* comiss */
8047 case 0x660f2f: /* comisd */
8048 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
8051 case 0x0ff7: /* maskmovq */
8052 regcache_raw_read_unsigned (ir.regcache,
8053 ir.regmap[X86_RECORD_REDI_REGNUM],
8055 if (record_full_arch_list_add_mem (addr, 64))
8059 case 0x660ff7: /* maskmovdqu */
8060 regcache_raw_read_unsigned (ir.regcache,
8061 ir.regmap[X86_RECORD_REDI_REGNUM],
8063 if (record_full_arch_list_add_mem (addr, 128))
8078 /* In the future, maybe still need to deal with need_dasm. */
8079 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
8080 if (record_full_arch_list_add_end ())
8086 printf_unfiltered (_("Process record does not support instruction 0x%02x "
8087 "at address %s.\n"),
8088 (unsigned int) (opcode),
8089 paddress (gdbarch, ir.orig_addr));
8093 static const int i386_record_regmap[] =
8095 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
8096 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
8097 0, 0, 0, 0, 0, 0, 0, 0,
8098 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
8099 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
8102 /* Check that the given address appears suitable for a fast
8103 tracepoint, which on x86-64 means that we need an instruction of at
8104 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8105 jump and not have to worry about program jumps to an address in the
8106 middle of the tracepoint jump. On x86, it may be possible to use
8107 4-byte jumps with a 2-byte offset to a trampoline located in the
8108 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8109 of instruction to replace, and 0 if not, plus an explanatory
8113 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, CORE_ADDR addr,
8117 static struct ui_file *gdb_null = NULL;
8119 /* Ask the target for the minimum instruction length supported. */
8120 jumplen = target_get_min_fast_tracepoint_insn_len ();
8124 /* If the target does not support the get_min_fast_tracepoint_insn_len
8125 operation, assume that fast tracepoints will always be implemented
8126 using 4-byte relative jumps on both x86 and x86-64. */
8129 else if (jumplen == 0)
8131 /* If the target does support get_min_fast_tracepoint_insn_len but
8132 returns zero, then the IPA has not loaded yet. In this case,
8133 we optimistically assume that truncated 2-byte relative jumps
8134 will be available on x86, and compensate later if this assumption
8135 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8136 jumps will always be used. */
8137 jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4;
8140 /* Dummy file descriptor for the disassembler. */
8142 gdb_null = ui_file_new ();
8144 /* Check for fit. */
8145 len = gdb_print_insn (gdbarch, addr, gdb_null, NULL);
8149 /* Return a bit of target-specific detail to add to the caller's
8150 generic failure message. */
8152 *msg = xstrprintf (_("; instruction is only %d bytes long, "
8153 "need at least %d bytes for the jump"),
8165 /* Return a floating-point format for a floating-point variable of
8166 length LEN in bits. If non-NULL, NAME is the name of its type.
8167 If no suitable type is found, return NULL. */
8169 const struct floatformat **
8170 i386_floatformat_for_type (struct gdbarch *gdbarch,
8171 const char *name, int len)
8173 if (len == 128 && name)
8174 if (strcmp (name, "__float128") == 0
8175 || strcmp (name, "_Float128") == 0
8176 || strcmp (name, "complex _Float128") == 0)
8177 return floatformats_ia64_quad;
8179 return default_floatformat_for_type (gdbarch, name, len);
8183 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
8184 struct tdesc_arch_data *tdesc_data)
8186 const struct target_desc *tdesc = tdep->tdesc;
8187 const struct tdesc_feature *feature_core;
8189 const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx,
8191 int i, num_regs, valid_p;
8193 if (! tdesc_has_registers (tdesc))
8196 /* Get core registers. */
8197 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
8198 if (feature_core == NULL)
8201 /* Get SSE registers. */
8202 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
8204 /* Try AVX registers. */
8205 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
8207 /* Try MPX registers. */
8208 feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx");
8210 /* Try AVX512 registers. */
8211 feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512");
8215 /* The XCR0 bits. */
8218 /* AVX512 register description requires AVX register description. */
8222 tdep->xcr0 = X86_XSTATE_MPX_AVX512_MASK;
8224 /* It may have been set by OSABI initialization function. */
8225 if (tdep->k0_regnum < 0)
8227 tdep->k_register_names = i386_k_names;
8228 tdep->k0_regnum = I386_K0_REGNUM;
8231 for (i = 0; i < I387_NUM_K_REGS; i++)
8232 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8233 tdep->k0_regnum + i,
8236 if (tdep->num_zmm_regs == 0)
8238 tdep->zmmh_register_names = i386_zmmh_names;
8239 tdep->num_zmm_regs = 8;
8240 tdep->zmm0h_regnum = I386_ZMM0H_REGNUM;
8243 for (i = 0; i < tdep->num_zmm_regs; i++)
8244 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8245 tdep->zmm0h_regnum + i,
8246 tdep->zmmh_register_names[i]);
8248 for (i = 0; i < tdep->num_xmm_avx512_regs; i++)
8249 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8250 tdep->xmm16_regnum + i,
8251 tdep->xmm_avx512_register_names[i]);
8253 for (i = 0; i < tdep->num_ymm_avx512_regs; i++)
8254 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8255 tdep->ymm16h_regnum + i,
8256 tdep->ymm16h_register_names[i]);
8260 /* AVX register description requires SSE register description. */
8264 if (!feature_avx512)
8265 tdep->xcr0 = X86_XSTATE_AVX_MASK;
8267 /* It may have been set by OSABI initialization function. */
8268 if (tdep->num_ymm_regs == 0)
8270 tdep->ymmh_register_names = i386_ymmh_names;
8271 tdep->num_ymm_regs = 8;
8272 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
8275 for (i = 0; i < tdep->num_ymm_regs; i++)
8276 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
8277 tdep->ymm0h_regnum + i,
8278 tdep->ymmh_register_names[i]);
8280 else if (feature_sse)
8281 tdep->xcr0 = X86_XSTATE_SSE_MASK;
8284 tdep->xcr0 = X86_XSTATE_X87_MASK;
8285 tdep->num_xmm_regs = 0;
8288 num_regs = tdep->num_core_regs;
8289 for (i = 0; i < num_regs; i++)
8290 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
8291 tdep->register_names[i]);
8295 /* Need to include %mxcsr, so add one. */
8296 num_regs += tdep->num_xmm_regs + 1;
8297 for (; i < num_regs; i++)
8298 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
8299 tdep->register_names[i]);
8304 tdep->xcr0 |= X86_XSTATE_MPX_MASK;
8306 if (tdep->bnd0r_regnum < 0)
8308 tdep->mpx_register_names = i386_mpx_names;
8309 tdep->bnd0r_regnum = I386_BND0R_REGNUM;
8310 tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM;
8313 for (i = 0; i < I387_NUM_MPX_REGS; i++)
8314 valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data,
8315 I387_BND0R_REGNUM (tdep) + i,
8316 tdep->mpx_register_names[i]);
8323 static struct gdbarch *
8324 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8326 struct gdbarch_tdep *tdep;
8327 struct gdbarch *gdbarch;
8328 struct tdesc_arch_data *tdesc_data;
8329 const struct target_desc *tdesc;
8335 /* If there is already a candidate, use it. */
8336 arches = gdbarch_list_lookup_by_info (arches, &info);
8338 return arches->gdbarch;
8340 /* Allocate space for the new architecture. */
8341 tdep = XCNEW (struct gdbarch_tdep);
8342 gdbarch = gdbarch_alloc (&info, tdep);
8344 /* General-purpose registers. */
8345 tdep->gregset_reg_offset = NULL;
8346 tdep->gregset_num_regs = I386_NUM_GREGS;
8347 tdep->sizeof_gregset = 0;
8349 /* Floating-point registers. */
8350 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
8351 tdep->fpregset = &i386_fpregset;
8353 /* The default settings include the FPU registers, the MMX registers
8354 and the SSE registers. This can be overridden for a specific ABI
8355 by adjusting the members `st0_regnum', `mm0_regnum' and
8356 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8357 will show up in the output of "info all-registers". */
8359 tdep->st0_regnum = I386_ST0_REGNUM;
8361 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8362 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
8364 tdep->jb_pc_offset = -1;
8365 tdep->struct_return = pcc_struct_return;
8366 tdep->sigtramp_start = 0;
8367 tdep->sigtramp_end = 0;
8368 tdep->sigtramp_p = i386_sigtramp_p;
8369 tdep->sigcontext_addr = NULL;
8370 tdep->sc_reg_offset = NULL;
8371 tdep->sc_pc_offset = -1;
8372 tdep->sc_sp_offset = -1;
8374 tdep->xsave_xcr0_offset = -1;
8376 tdep->record_regmap = i386_record_regmap;
8378 set_gdbarch_long_long_align_bit (gdbarch, 32);
8380 /* The format used for `long double' on almost all i386 targets is
8381 the i387 extended floating-point format. In fact, of all targets
8382 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8383 on having a `long double' that's not `long' at all. */
8384 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
8386 /* Although the i387 extended floating-point has only 80 significant
8387 bits, a `long double' actually takes up 96, probably to enforce
8389 set_gdbarch_long_double_bit (gdbarch, 96);
8391 /* Support for floating-point data type variants. */
8392 set_gdbarch_floatformat_for_type (gdbarch, i386_floatformat_for_type);
8394 /* Register numbers of various important registers. */
8395 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
8396 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
8397 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
8398 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
8400 /* NOTE: kettenis/20040418: GCC does have two possible register
8401 numbering schemes on the i386: dbx and SVR4. These schemes
8402 differ in how they number %ebp, %esp, %eflags, and the
8403 floating-point registers, and are implemented by the arrays
8404 dbx_register_map[] and svr4_dbx_register_map in
8405 gcc/config/i386.c. GCC also defines a third numbering scheme in
8406 gcc/config/i386.c, which it designates as the "default" register
8407 map used in 64bit mode. This last register numbering scheme is
8408 implemented in dbx64_register_map, and is used for AMD64; see
8411 Currently, each GCC i386 target always uses the same register
8412 numbering scheme across all its supported debugging formats
8413 i.e. SDB (COFF), stabs and DWARF 2. This is because
8414 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8415 DBX_REGISTER_NUMBER macro which is defined by each target's
8416 respective config header in a manner independent of the requested
8417 output debugging format.
8419 This does not match the arrangement below, which presumes that
8420 the SDB and stabs numbering schemes differ from the DWARF and
8421 DWARF 2 ones. The reason for this arrangement is that it is
8422 likely to get the numbering scheme for the target's
8423 default/native debug format right. For targets where GCC is the
8424 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8425 targets where the native toolchain uses a different numbering
8426 scheme for a particular debug format (stabs-in-ELF on Solaris)
8427 the defaults below will have to be overridden, like
8428 i386_elf_init_abi() does. */
8430 /* Use the dbx register numbering scheme for stabs and COFF. */
8431 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8432 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8434 /* Use the SVR4 register numbering scheme for DWARF 2. */
8435 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_dwarf_reg_to_regnum);
8437 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8438 be in use on any of the supported i386 targets. */
8440 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
8442 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
8444 /* Call dummy code. */
8445 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
8446 set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code);
8447 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
8448 set_gdbarch_frame_align (gdbarch, i386_frame_align);
8450 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
8451 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
8452 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
8454 set_gdbarch_return_value (gdbarch, i386_return_value);
8456 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
8458 /* Stack grows downward. */
8459 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8461 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc);
8462 set_gdbarch_decr_pc_after_break (gdbarch, 1);
8463 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
8465 set_gdbarch_frame_args_skip (gdbarch, 8);
8467 set_gdbarch_print_insn (gdbarch, i386_print_insn);
8469 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
8471 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
8473 /* Add the i386 register groups. */
8474 i386_add_reggroups (gdbarch);
8475 tdep->register_reggroup_p = i386_register_reggroup_p;
8477 /* Helper for function argument information. */
8478 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
8480 /* Hook the function epilogue frame unwinder. This unwinder is
8481 appended to the list first, so that it supercedes the DWARF
8482 unwinder in function epilogues (where the DWARF unwinder
8483 currently fails). */
8484 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
8486 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8487 to the list before the prologue-based unwinders, so that DWARF
8488 CFI info will be used if it is available. */
8489 dwarf2_append_unwinders (gdbarch);
8491 frame_base_set_default (gdbarch, &i386_frame_base);
8493 /* Pseudo registers may be changed by amd64_init_abi. */
8494 set_gdbarch_pseudo_register_read_value (gdbarch,
8495 i386_pseudo_register_read_value);
8496 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
8497 set_gdbarch_ax_pseudo_register_collect (gdbarch,
8498 i386_ax_pseudo_register_collect);
8500 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
8501 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
8503 /* Override the normal target description method to make the AVX
8504 upper halves anonymous. */
8505 set_gdbarch_register_name (gdbarch, i386_register_name);
8507 /* Even though the default ABI only includes general-purpose registers,
8508 floating-point registers and the SSE registers, we have to leave a
8509 gap for the upper AVX, MPX and AVX512 registers. */
8510 set_gdbarch_num_regs (gdbarch, I386_AVX512_NUM_REGS);
8512 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
8514 /* Get the x86 target description from INFO. */
8515 tdesc = info.target_desc;
8516 if (! tdesc_has_registers (tdesc))
8518 tdep->tdesc = tdesc;
8520 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
8521 tdep->register_names = i386_register_names;
8523 /* No upper YMM registers. */
8524 tdep->ymmh_register_names = NULL;
8525 tdep->ymm0h_regnum = -1;
8527 /* No upper ZMM registers. */
8528 tdep->zmmh_register_names = NULL;
8529 tdep->zmm0h_regnum = -1;
8531 /* No high XMM registers. */
8532 tdep->xmm_avx512_register_names = NULL;
8533 tdep->xmm16_regnum = -1;
8535 /* No upper YMM16-31 registers. */
8536 tdep->ymm16h_register_names = NULL;
8537 tdep->ymm16h_regnum = -1;
8539 tdep->num_byte_regs = 8;
8540 tdep->num_word_regs = 8;
8541 tdep->num_dword_regs = 0;
8542 tdep->num_mmx_regs = 8;
8543 tdep->num_ymm_regs = 0;
8545 /* No MPX registers. */
8546 tdep->bnd0r_regnum = -1;
8547 tdep->bndcfgu_regnum = -1;
8549 /* No AVX512 registers. */
8550 tdep->k0_regnum = -1;
8551 tdep->num_zmm_regs = 0;
8552 tdep->num_ymm_avx512_regs = 0;
8553 tdep->num_xmm_avx512_regs = 0;
8555 tdesc_data = tdesc_data_alloc ();
8557 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
8559 set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address);
8561 set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call);
8562 set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret);
8563 set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump);
8565 /* Hook in ABI-specific overrides, if they have been registered. */
8566 info.tdep_info = tdesc_data;
8567 gdbarch_init_osabi (info, gdbarch);
8569 if (!i386_validate_tdesc_p (tdep, tdesc_data))
8571 tdesc_data_cleanup (tdesc_data);
8573 gdbarch_free (gdbarch);
8577 num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0);
8579 /* Wire in pseudo registers. Number of pseudo registers may be
8581 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
8582 + tdep->num_word_regs
8583 + tdep->num_dword_regs
8584 + tdep->num_mmx_regs
8585 + tdep->num_ymm_regs
8587 + tdep->num_ymm_avx512_regs
8588 + tdep->num_zmm_regs));
8590 /* Target description may be changed. */
8591 tdesc = tdep->tdesc;
8593 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
8595 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8596 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
8598 /* Make %al the first pseudo-register. */
8599 tdep->al_regnum = gdbarch_num_regs (gdbarch);
8600 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
8602 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
8603 if (tdep->num_dword_regs)
8605 /* Support dword pseudo-register if it hasn't been disabled. */
8606 tdep->eax_regnum = ymm0_regnum;
8607 ymm0_regnum += tdep->num_dword_regs;
8610 tdep->eax_regnum = -1;
8612 mm0_regnum = ymm0_regnum;
8613 if (tdep->num_ymm_regs)
8615 /* Support YMM pseudo-register if it is available. */
8616 tdep->ymm0_regnum = ymm0_regnum;
8617 mm0_regnum += tdep->num_ymm_regs;
8620 tdep->ymm0_regnum = -1;
8622 if (tdep->num_ymm_avx512_regs)
8624 /* Support YMM16-31 pseudo registers if available. */
8625 tdep->ymm16_regnum = mm0_regnum;
8626 mm0_regnum += tdep->num_ymm_avx512_regs;
8629 tdep->ymm16_regnum = -1;
8631 if (tdep->num_zmm_regs)
8633 /* Support ZMM pseudo-register if it is available. */
8634 tdep->zmm0_regnum = mm0_regnum;
8635 mm0_regnum += tdep->num_zmm_regs;
8638 tdep->zmm0_regnum = -1;
8640 bnd0_regnum = mm0_regnum;
8641 if (tdep->num_mmx_regs != 0)
8643 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8644 tdep->mm0_regnum = mm0_regnum;
8645 bnd0_regnum += tdep->num_mmx_regs;
8648 tdep->mm0_regnum = -1;
8650 if (tdep->bnd0r_regnum > 0)
8651 tdep->bnd0_regnum = bnd0_regnum;
8653 tdep-> bnd0_regnum = -1;
8655 /* Hook in the legacy prologue-based unwinders last (fallback). */
8656 frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind);
8657 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
8658 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
8660 /* If we have a register mapping, enable the generic core file
8661 support, unless it has already been enabled. */
8662 if (tdep->gregset_reg_offset
8663 && !gdbarch_iterate_over_regset_sections_p (gdbarch))
8664 set_gdbarch_iterate_over_regset_sections
8665 (gdbarch, i386_iterate_over_regset_sections);
8667 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
8668 i386_fast_tracepoint_valid_at);
8673 static enum gdb_osabi
8674 i386_coff_osabi_sniffer (bfd *abfd)
8676 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
8677 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
8678 return GDB_OSABI_GO32;
8680 return GDB_OSABI_UNKNOWN;
8684 /* Return the target description for a specified XSAVE feature mask. */
8686 const struct target_desc *
8687 i386_target_description (uint64_t xcr0)
8689 switch (xcr0 & X86_XSTATE_ALL_MASK)
8691 case X86_XSTATE_MPX_AVX512_MASK:
8692 case X86_XSTATE_AVX512_MASK:
8693 return tdesc_i386_avx512;
8694 case X86_XSTATE_AVX_MPX_MASK:
8695 return tdesc_i386_avx_mpx;
8696 case X86_XSTATE_MPX_MASK:
8697 return tdesc_i386_mpx;
8698 case X86_XSTATE_AVX_MASK:
8699 return tdesc_i386_avx;
8705 #define MPX_BASE_MASK (~(ULONGEST) 0xfff)
8707 /* Find the bound directory base address. */
8709 static unsigned long
8710 i386_mpx_bd_base (void)
8712 struct regcache *rcache;
8713 struct gdbarch_tdep *tdep;
8715 enum register_status regstatus;
8717 rcache = get_current_regcache ();
8718 tdep = gdbarch_tdep (get_regcache_arch (rcache));
8720 regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret);
8722 if (regstatus != REG_VALID)
8723 error (_("BNDCFGU register invalid, read status %d."), regstatus);
8725 return ret & MPX_BASE_MASK;
8729 i386_mpx_enabled (void)
8731 const struct gdbarch_tdep *tdep = gdbarch_tdep (get_current_arch ());
8732 const struct target_desc *tdesc = tdep->tdesc;
8734 return (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL);
8737 #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */
8738 #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */
8739 #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */
8740 #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */
8742 /* Find the bound table entry given the pointer location and the base
8743 address of the table. */
8746 i386_mpx_get_bt_entry (CORE_ADDR ptr, CORE_ADDR bd_base)
8750 CORE_ADDR mpx_bd_mask, bd_ptr_r_shift, bd_ptr_l_shift;
8751 CORE_ADDR bt_mask, bt_select_r_shift, bt_select_l_shift;
8752 CORE_ADDR bd_entry_addr;
8755 struct gdbarch *gdbarch = get_current_arch ();
8756 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8759 if (gdbarch_ptr_bit (gdbarch) == 64)
8761 mpx_bd_mask = (CORE_ADDR) MPX_BD_MASK;
8762 bd_ptr_r_shift = 20;
8764 bt_select_r_shift = 3;
8765 bt_select_l_shift = 5;
8766 bt_mask = (CORE_ADDR) MPX_BT_MASK;
8768 if ( sizeof (CORE_ADDR) == 4)
8769 error (_("bound table examination not supported\
8770 for 64-bit process with 32-bit GDB"));
8774 mpx_bd_mask = MPX_BD_MASK_32;
8775 bd_ptr_r_shift = 12;
8777 bt_select_r_shift = 2;
8778 bt_select_l_shift = 4;
8779 bt_mask = MPX_BT_MASK_32;
8782 offset1 = ((ptr & mpx_bd_mask) >> bd_ptr_r_shift) << bd_ptr_l_shift;
8783 bd_entry_addr = bd_base + offset1;
8784 bd_entry = read_memory_typed_address (bd_entry_addr, data_ptr_type);
8786 if ((bd_entry & 0x1) == 0)
8787 error (_("Invalid bounds directory entry at %s."),
8788 paddress (get_current_arch (), bd_entry_addr));
8790 /* Clearing status bit. */
8792 bt_addr = bd_entry & ~bt_select_r_shift;
8793 offset2 = ((ptr & bt_mask) >> bt_select_r_shift) << bt_select_l_shift;
8795 return bt_addr + offset2;
8798 /* Print routine for the mpx bounds. */
8801 i386_mpx_print_bounds (const CORE_ADDR bt_entry[4])
8803 struct ui_out *uiout = current_uiout;
8805 struct gdbarch *gdbarch = get_current_arch ();
8806 CORE_ADDR onecompl = ~((CORE_ADDR) 0);
8807 int bounds_in_map = ((~bt_entry[1] == 0 && bt_entry[0] == onecompl) ? 1 : 0);
8809 if (bounds_in_map == 1)
8811 ui_out_text (uiout, "Null bounds on map:");
8812 ui_out_text (uiout, " pointer value = ");
8813 ui_out_field_core_addr (uiout, "pointer-value", gdbarch, bt_entry[2]);
8814 ui_out_text (uiout, ".");
8815 ui_out_text (uiout, "\n");
8819 ui_out_text (uiout, "{lbound = ");
8820 ui_out_field_core_addr (uiout, "lower-bound", gdbarch, bt_entry[0]);
8821 ui_out_text (uiout, ", ubound = ");
8823 /* The upper bound is stored in 1's complement. */
8824 ui_out_field_core_addr (uiout, "upper-bound", gdbarch, ~bt_entry[1]);
8825 ui_out_text (uiout, "}: pointer value = ");
8826 ui_out_field_core_addr (uiout, "pointer-value", gdbarch, bt_entry[2]);
8828 if (gdbarch_ptr_bit (gdbarch) == 64)
8829 size = ( (~(int64_t) bt_entry[1]) - (int64_t) bt_entry[0]);
8831 size = ( ~((int32_t) bt_entry[1]) - (int32_t) bt_entry[0]);
8833 /* In case the bounds are 0x0 and 0xffff... the difference will be -1.
8834 -1 represents in this sense full memory access, and there is no need
8837 size = (size > -1 ? size + 1 : size);
8838 ui_out_text (uiout, ", size = ");
8839 ui_out_field_fmt (uiout, "size", "%s", plongest (size));
8841 ui_out_text (uiout, ", metadata = ");
8842 ui_out_field_core_addr (uiout, "metadata", gdbarch, bt_entry[3]);
8843 ui_out_text (uiout, "\n");
8847 /* Implement the command "show mpx bound". */
8850 i386_mpx_info_bounds (char *args, int from_tty)
8852 CORE_ADDR bd_base = 0;
8854 CORE_ADDR bt_entry_addr = 0;
8855 CORE_ADDR bt_entry[4];
8857 struct gdbarch *gdbarch = get_current_arch ();
8858 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8860 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386
8861 || !i386_mpx_enabled ())
8863 printf_unfiltered (_("Intel Memory Protection Extensions not "
8864 "supported on this target.\n"));
8870 printf_unfiltered (_("Address of pointer variable expected.\n"));
8874 addr = parse_and_eval_address (args);
8876 bd_base = i386_mpx_bd_base ();
8877 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8879 memset (bt_entry, 0, sizeof (bt_entry));
8881 for (i = 0; i < 4; i++)
8882 bt_entry[i] = read_memory_typed_address (bt_entry_addr
8883 + i * TYPE_LENGTH (data_ptr_type),
8886 i386_mpx_print_bounds (bt_entry);
8889 /* Implement the command "set mpx bound". */
8892 i386_mpx_set_bounds (char *args, int from_tty)
8894 CORE_ADDR bd_base = 0;
8895 CORE_ADDR addr, lower, upper;
8896 CORE_ADDR bt_entry_addr = 0;
8897 CORE_ADDR bt_entry[2];
8898 const char *input = args;
8900 struct gdbarch *gdbarch = get_current_arch ();
8901 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8902 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8904 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386
8905 || !i386_mpx_enabled ())
8906 error (_("Intel Memory Protection Extensions not supported\
8910 error (_("Pointer value expected."));
8912 addr = value_as_address (parse_to_comma_and_eval (&input));
8914 if (input[0] == ',')
8916 if (input[0] == '\0')
8917 error (_("wrong number of arguments: missing lower and upper bound."));
8918 lower = value_as_address (parse_to_comma_and_eval (&input));
8920 if (input[0] == ',')
8922 if (input[0] == '\0')
8923 error (_("Wrong number of arguments; Missing upper bound."));
8924 upper = value_as_address (parse_to_comma_and_eval (&input));
8926 bd_base = i386_mpx_bd_base ();
8927 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8928 for (i = 0; i < 2; i++)
8929 bt_entry[i] = read_memory_typed_address (bt_entry_addr
8930 + i * TYPE_LENGTH (data_ptr_type),
8932 bt_entry[0] = (uint64_t) lower;
8933 bt_entry[1] = ~(uint64_t) upper;
8935 for (i = 0; i < 2; i++)
8936 write_memory_unsigned_integer (bt_entry_addr
8937 + i * TYPE_LENGTH (data_ptr_type),
8938 TYPE_LENGTH (data_ptr_type), byte_order,
8942 static struct cmd_list_element *mpx_set_cmdlist, *mpx_show_cmdlist;
8944 /* Helper function for the CLI commands. */
8947 set_mpx_cmd (char *args, int from_tty)
8949 help_list (mpx_set_cmdlist, "set mpx ", all_commands, gdb_stdout);
8952 /* Helper function for the CLI commands. */
8955 show_mpx_cmd (char *args, int from_tty)
8957 cmd_show_list (mpx_show_cmdlist, from_tty, "");
8960 /* Provide a prototype to silence -Wmissing-prototypes. */
8961 void _initialize_i386_tdep (void);
8964 _initialize_i386_tdep (void)
8966 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
8968 /* Add the variable that controls the disassembly flavor. */
8969 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
8970 &disassembly_flavor, _("\
8971 Set the disassembly flavor."), _("\
8972 Show the disassembly flavor."), _("\
8973 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
8975 NULL, /* FIXME: i18n: */
8976 &setlist, &showlist);
8978 /* Add the variable that controls the convention for returning
8980 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
8981 &struct_convention, _("\
8982 Set the convention for returning small structs."), _("\
8983 Show the convention for returning small structs."), _("\
8984 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
8987 NULL, /* FIXME: i18n: */
8988 &setlist, &showlist);
8990 /* Add "mpx" prefix for the set commands. */
8992 add_prefix_cmd ("mpx", class_support, set_mpx_cmd, _("\
8993 Set Intel Memory Protection Extensions specific variables."),
8994 &mpx_set_cmdlist, "set mpx ",
8995 0 /* allow-unknown */, &setlist);
8997 /* Add "mpx" prefix for the show commands. */
8999 add_prefix_cmd ("mpx", class_support, show_mpx_cmd, _("\
9000 Show Intel Memory Protection Extensions specific variables."),
9001 &mpx_show_cmdlist, "show mpx ",
9002 0 /* allow-unknown */, &showlist);
9004 /* Add "bound" command for the show mpx commands list. */
9006 add_cmd ("bound", no_class, i386_mpx_info_bounds,
9007 "Show the memory bounds for a given array/pointer storage\
9008 in the bound table.",
9011 /* Add "bound" command for the set mpx commands list. */
9013 add_cmd ("bound", no_class, i386_mpx_set_bounds,
9014 "Set the memory bounds for a given array/pointer storage\
9015 in the bound table.",
9018 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
9019 i386_coff_osabi_sniffer);
9021 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
9022 i386_svr4_init_abi);
9023 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
9024 i386_go32_init_abi);
9026 /* Initialize the i386-specific register groups. */
9027 i386_init_reggroups ();
9029 /* Initialize the standard target descriptions. */
9030 initialize_tdesc_i386 ();
9031 initialize_tdesc_i386_mmx ();
9032 initialize_tdesc_i386_avx ();
9033 initialize_tdesc_i386_mpx ();
9034 initialize_tdesc_i386_avx_mpx ();
9035 initialize_tdesc_i386_avx512 ();
9037 /* Tell remote stub that we support XML target description. */
9038 register_remote_support_xml ("i386");