1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
38 #include "reggroups.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "x86-xstate.h"
52 #include "record-full.h"
53 #include "features/i386/i386.c"
54 #include "features/i386/i386-avx.c"
55 #include "features/i386/i386-mpx.c"
56 #include "features/i386/i386-avx-mpx.c"
57 #include "features/i386/i386-avx-avx512.c"
58 #include "features/i386/i386-avx-mpx-avx512.c"
59 #include "features/i386/i386-mmx.c"
64 #include "stap-probe.h"
65 #include "user-regs.h"
66 #include "cli/cli-utils.h"
67 #include "expression.h"
68 #include "parser-defs.h"
74 static const char *i386_register_names[] =
76 "eax", "ecx", "edx", "ebx",
77 "esp", "ebp", "esi", "edi",
78 "eip", "eflags", "cs", "ss",
79 "ds", "es", "fs", "gs",
80 "st0", "st1", "st2", "st3",
81 "st4", "st5", "st6", "st7",
82 "fctrl", "fstat", "ftag", "fiseg",
83 "fioff", "foseg", "fooff", "fop",
84 "xmm0", "xmm1", "xmm2", "xmm3",
85 "xmm4", "xmm5", "xmm6", "xmm7",
89 static const char *i386_zmm_names[] =
91 "zmm0", "zmm1", "zmm2", "zmm3",
92 "zmm4", "zmm5", "zmm6", "zmm7"
95 static const char *i386_zmmh_names[] =
97 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
98 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
101 static const char *i386_k_names[] =
103 "k0", "k1", "k2", "k3",
104 "k4", "k5", "k6", "k7"
107 static const char *i386_ymm_names[] =
109 "ymm0", "ymm1", "ymm2", "ymm3",
110 "ymm4", "ymm5", "ymm6", "ymm7",
113 static const char *i386_ymmh_names[] =
115 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
116 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
119 static const char *i386_mpx_names[] =
121 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
124 /* Register names for MPX pseudo-registers. */
126 static const char *i386_bnd_names[] =
128 "bnd0", "bnd1", "bnd2", "bnd3"
131 /* Register names for MMX pseudo-registers. */
133 static const char *i386_mmx_names[] =
135 "mm0", "mm1", "mm2", "mm3",
136 "mm4", "mm5", "mm6", "mm7"
139 /* Register names for byte pseudo-registers. */
141 static const char *i386_byte_names[] =
143 "al", "cl", "dl", "bl",
144 "ah", "ch", "dh", "bh"
147 /* Register names for word pseudo-registers. */
149 static const char *i386_word_names[] =
151 "ax", "cx", "dx", "bx",
155 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
156 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
157 we have 16 upper ZMM regs that have to be handled differently. */
159 const int num_lower_zmm_regs = 16;
164 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
166 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
167 int mm0_regnum = tdep->mm0_regnum;
172 regnum -= mm0_regnum;
173 return regnum >= 0 && regnum < tdep->num_mmx_regs;
179 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
181 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
183 regnum -= tdep->al_regnum;
184 return regnum >= 0 && regnum < tdep->num_byte_regs;
190 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
192 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
194 regnum -= tdep->ax_regnum;
195 return regnum >= 0 && regnum < tdep->num_word_regs;
198 /* Dword register? */
201 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
203 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
204 int eax_regnum = tdep->eax_regnum;
209 regnum -= eax_regnum;
210 return regnum >= 0 && regnum < tdep->num_dword_regs;
213 /* AVX512 register? */
216 i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum)
218 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
219 int zmm0h_regnum = tdep->zmm0h_regnum;
221 if (zmm0h_regnum < 0)
224 regnum -= zmm0h_regnum;
225 return regnum >= 0 && regnum < tdep->num_zmm_regs;
229 i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum)
231 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
232 int zmm0_regnum = tdep->zmm0_regnum;
237 regnum -= zmm0_regnum;
238 return regnum >= 0 && regnum < tdep->num_zmm_regs;
242 i386_k_regnum_p (struct gdbarch *gdbarch, int regnum)
244 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
245 int k0_regnum = tdep->k0_regnum;
251 return regnum >= 0 && regnum < I387_NUM_K_REGS;
255 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
257 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
258 int ymm0h_regnum = tdep->ymm0h_regnum;
260 if (ymm0h_regnum < 0)
263 regnum -= ymm0h_regnum;
264 return regnum >= 0 && regnum < tdep->num_ymm_regs;
270 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
272 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
273 int ymm0_regnum = tdep->ymm0_regnum;
278 regnum -= ymm0_regnum;
279 return regnum >= 0 && regnum < tdep->num_ymm_regs;
283 i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
285 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
286 int ymm16h_regnum = tdep->ymm16h_regnum;
288 if (ymm16h_regnum < 0)
291 regnum -= ymm16h_regnum;
292 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
296 i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
298 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
299 int ymm16_regnum = tdep->ymm16_regnum;
301 if (ymm16_regnum < 0)
304 regnum -= ymm16_regnum;
305 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
311 i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum)
313 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
314 int bnd0_regnum = tdep->bnd0_regnum;
319 regnum -= bnd0_regnum;
320 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
326 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
328 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
329 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
331 if (num_xmm_regs == 0)
334 regnum -= I387_XMM0_REGNUM (tdep);
335 return regnum >= 0 && regnum < num_xmm_regs;
338 /* XMM_512 register? */
341 i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
343 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
344 int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep);
346 if (num_xmm_avx512_regs == 0)
349 regnum -= I387_XMM16_REGNUM (tdep);
350 return regnum >= 0 && regnum < num_xmm_avx512_regs;
354 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
356 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
358 if (I387_NUM_XMM_REGS (tdep) == 0)
361 return (regnum == I387_MXCSR_REGNUM (tdep));
367 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
369 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
371 if (I387_ST0_REGNUM (tdep) < 0)
374 return (I387_ST0_REGNUM (tdep) <= regnum
375 && regnum < I387_FCTRL_REGNUM (tdep));
379 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
381 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
383 if (I387_ST0_REGNUM (tdep) < 0)
386 return (I387_FCTRL_REGNUM (tdep) <= regnum
387 && regnum < I387_XMM0_REGNUM (tdep));
390 /* BNDr (raw) register? */
393 i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum)
395 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
397 if (I387_BND0R_REGNUM (tdep) < 0)
400 regnum -= tdep->bnd0r_regnum;
401 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
404 /* BND control register? */
407 i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum)
409 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
411 if (I387_BNDCFGU_REGNUM (tdep) < 0)
414 regnum -= I387_BNDCFGU_REGNUM (tdep);
415 return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS;
418 /* Return the name of register REGNUM, or the empty string if it is
419 an anonymous register. */
422 i386_register_name (struct gdbarch *gdbarch, int regnum)
424 /* Hide the upper YMM registers. */
425 if (i386_ymmh_regnum_p (gdbarch, regnum))
428 /* Hide the upper YMM16-31 registers. */
429 if (i386_ymmh_avx512_regnum_p (gdbarch, regnum))
432 /* Hide the upper ZMM registers. */
433 if (i386_zmmh_regnum_p (gdbarch, regnum))
436 return tdesc_register_name (gdbarch, regnum);
439 /* Return the name of register REGNUM. */
442 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
444 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
445 if (i386_bnd_regnum_p (gdbarch, regnum))
446 return i386_bnd_names[regnum - tdep->bnd0_regnum];
447 if (i386_mmx_regnum_p (gdbarch, regnum))
448 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
449 else if (i386_ymm_regnum_p (gdbarch, regnum))
450 return i386_ymm_names[regnum - tdep->ymm0_regnum];
451 else if (i386_zmm_regnum_p (gdbarch, regnum))
452 return i386_zmm_names[regnum - tdep->zmm0_regnum];
453 else if (i386_byte_regnum_p (gdbarch, regnum))
454 return i386_byte_names[regnum - tdep->al_regnum];
455 else if (i386_word_regnum_p (gdbarch, regnum))
456 return i386_word_names[regnum - tdep->ax_regnum];
458 internal_error (__FILE__, __LINE__, _("invalid regnum"));
461 /* Convert a dbx register number REG to the appropriate register
462 number used by GDB. */
465 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
467 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
469 /* This implements what GCC calls the "default" register map
470 (dbx_register_map[]). */
472 if (reg >= 0 && reg <= 7)
474 /* General-purpose registers. The debug info calls %ebp
475 register 4, and %esp register 5. */
482 else if (reg >= 12 && reg <= 19)
484 /* Floating-point registers. */
485 return reg - 12 + I387_ST0_REGNUM (tdep);
487 else if (reg >= 21 && reg <= 28)
490 int ymm0_regnum = tdep->ymm0_regnum;
493 && i386_xmm_regnum_p (gdbarch, reg))
494 return reg - 21 + ymm0_regnum;
496 return reg - 21 + I387_XMM0_REGNUM (tdep);
498 else if (reg >= 29 && reg <= 36)
501 return reg - 29 + I387_MM0_REGNUM (tdep);
504 /* This will hopefully provoke a warning. */
505 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
508 /* Convert SVR4 DWARF register number REG to the appropriate register number
512 i386_svr4_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
514 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
516 /* This implements the GCC register map that tries to be compatible
517 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
519 /* The SVR4 register numbering includes %eip and %eflags, and
520 numbers the floating point registers differently. */
521 if (reg >= 0 && reg <= 9)
523 /* General-purpose registers. */
526 else if (reg >= 11 && reg <= 18)
528 /* Floating-point registers. */
529 return reg - 11 + I387_ST0_REGNUM (tdep);
531 else if (reg >= 21 && reg <= 36)
533 /* The SSE and MMX registers have the same numbers as with dbx. */
534 return i386_dbx_reg_to_regnum (gdbarch, reg);
539 case 37: return I387_FCTRL_REGNUM (tdep);
540 case 38: return I387_FSTAT_REGNUM (tdep);
541 case 39: return I387_MXCSR_REGNUM (tdep);
542 case 40: return I386_ES_REGNUM;
543 case 41: return I386_CS_REGNUM;
544 case 42: return I386_SS_REGNUM;
545 case 43: return I386_DS_REGNUM;
546 case 44: return I386_FS_REGNUM;
547 case 45: return I386_GS_REGNUM;
553 /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return
554 num_regs + num_pseudo_regs for other debug formats. */
557 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
559 int regnum = i386_svr4_dwarf_reg_to_regnum (gdbarch, reg);
562 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
568 /* This is the variable that is set with "set disassembly-flavor", and
569 its legitimate values. */
570 static const char att_flavor[] = "att";
571 static const char intel_flavor[] = "intel";
572 static const char *const valid_flavors[] =
578 static const char *disassembly_flavor = att_flavor;
581 /* Use the program counter to determine the contents and size of a
582 breakpoint instruction. Return a pointer to a string of bytes that
583 encode a breakpoint instruction, store the length of the string in
584 *LEN and optionally adjust *PC to point to the correct memory
585 location for inserting the breakpoint.
587 On the i386 we have a single breakpoint that fits in a single byte
588 and can be inserted anywhere.
590 This function is 64-bit safe. */
592 constexpr gdb_byte i386_break_insn[] = { 0xcc }; /* int 3 */
594 typedef BP_MANIPULATION (i386_break_insn) i386_breakpoint;
597 /* Displaced instruction handling. */
599 /* Skip the legacy instruction prefixes in INSN.
600 Not all prefixes are valid for any particular insn
601 but we needn't care, the insn will fault if it's invalid.
602 The result is a pointer to the first opcode byte,
603 or NULL if we run off the end of the buffer. */
606 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
608 gdb_byte *end = insn + max_len;
614 case DATA_PREFIX_OPCODE:
615 case ADDR_PREFIX_OPCODE:
616 case CS_PREFIX_OPCODE:
617 case DS_PREFIX_OPCODE:
618 case ES_PREFIX_OPCODE:
619 case FS_PREFIX_OPCODE:
620 case GS_PREFIX_OPCODE:
621 case SS_PREFIX_OPCODE:
622 case LOCK_PREFIX_OPCODE:
623 case REPE_PREFIX_OPCODE:
624 case REPNE_PREFIX_OPCODE:
636 i386_absolute_jmp_p (const gdb_byte *insn)
638 /* jmp far (absolute address in operand). */
644 /* jump near, absolute indirect (/4). */
645 if ((insn[1] & 0x38) == 0x20)
648 /* jump far, absolute indirect (/5). */
649 if ((insn[1] & 0x38) == 0x28)
656 /* Return non-zero if INSN is a jump, zero otherwise. */
659 i386_jmp_p (const gdb_byte *insn)
661 /* jump short, relative. */
665 /* jump near, relative. */
669 return i386_absolute_jmp_p (insn);
673 i386_absolute_call_p (const gdb_byte *insn)
675 /* call far, absolute. */
681 /* Call near, absolute indirect (/2). */
682 if ((insn[1] & 0x38) == 0x10)
685 /* Call far, absolute indirect (/3). */
686 if ((insn[1] & 0x38) == 0x18)
694 i386_ret_p (const gdb_byte *insn)
698 case 0xc2: /* ret near, pop N bytes. */
699 case 0xc3: /* ret near */
700 case 0xca: /* ret far, pop N bytes. */
701 case 0xcb: /* ret far */
702 case 0xcf: /* iret */
711 i386_call_p (const gdb_byte *insn)
713 if (i386_absolute_call_p (insn))
716 /* call near, relative. */
723 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
724 length in bytes. Otherwise, return zero. */
727 i386_syscall_p (const gdb_byte *insn, int *lengthp)
729 /* Is it 'int $0x80'? */
730 if ((insn[0] == 0xcd && insn[1] == 0x80)
731 /* Or is it 'sysenter'? */
732 || (insn[0] == 0x0f && insn[1] == 0x34)
733 /* Or is it 'syscall'? */
734 || (insn[0] == 0x0f && insn[1] == 0x05))
743 /* The gdbarch insn_is_call method. */
746 i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
748 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
750 read_code (addr, buf, I386_MAX_INSN_LEN);
751 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
753 return i386_call_p (insn);
756 /* The gdbarch insn_is_ret method. */
759 i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
761 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
763 read_code (addr, buf, I386_MAX_INSN_LEN);
764 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
766 return i386_ret_p (insn);
769 /* The gdbarch insn_is_jump method. */
772 i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
774 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
776 read_code (addr, buf, I386_MAX_INSN_LEN);
777 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
779 return i386_jmp_p (insn);
782 /* Some kernels may run one past a syscall insn, so we have to cope.
783 Otherwise this is just simple_displaced_step_copy_insn. */
785 struct displaced_step_closure *
786 i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
787 CORE_ADDR from, CORE_ADDR to,
788 struct regcache *regs)
790 size_t len = gdbarch_max_insn_length (gdbarch);
791 gdb_byte *buf = (gdb_byte *) xmalloc (len);
793 read_memory (from, buf, len);
795 /* GDB may get control back after the insn after the syscall.
796 Presumably this is a kernel bug.
797 If this is a syscall, make sure there's a nop afterwards. */
802 insn = i386_skip_prefixes (buf, len);
803 if (insn != NULL && i386_syscall_p (insn, &syscall_length))
804 insn[syscall_length] = NOP_OPCODE;
807 write_memory (to, buf, len);
811 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
812 paddress (gdbarch, from), paddress (gdbarch, to));
813 displaced_step_dump_bytes (gdb_stdlog, buf, len);
816 return (struct displaced_step_closure *) buf;
819 /* Fix up the state of registers and memory after having single-stepped
820 a displaced instruction. */
823 i386_displaced_step_fixup (struct gdbarch *gdbarch,
824 struct displaced_step_closure *closure,
825 CORE_ADDR from, CORE_ADDR to,
826 struct regcache *regs)
828 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
830 /* The offset we applied to the instruction's address.
831 This could well be negative (when viewed as a signed 32-bit
832 value), but ULONGEST won't reflect that, so take care when
834 ULONGEST insn_offset = to - from;
836 /* Since we use simple_displaced_step_copy_insn, our closure is a
837 copy of the instruction. */
838 gdb_byte *insn = (gdb_byte *) closure;
839 /* The start of the insn, needed in case we see some prefixes. */
840 gdb_byte *insn_start = insn;
843 fprintf_unfiltered (gdb_stdlog,
844 "displaced: fixup (%s, %s), "
845 "insn = 0x%02x 0x%02x ...\n",
846 paddress (gdbarch, from), paddress (gdbarch, to),
849 /* The list of issues to contend with here is taken from
850 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
851 Yay for Free Software! */
853 /* Relocate the %eip, if necessary. */
855 /* The instruction recognizers we use assume any leading prefixes
856 have been skipped. */
858 /* This is the size of the buffer in closure. */
859 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
860 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
861 /* If there are too many prefixes, just ignore the insn.
862 It will fault when run. */
867 /* Except in the case of absolute or indirect jump or call
868 instructions, or a return instruction, the new eip is relative to
869 the displaced instruction; make it relative. Well, signal
870 handler returns don't need relocation either, but we use the
871 value of %eip to recognize those; see below. */
872 if (! i386_absolute_jmp_p (insn)
873 && ! i386_absolute_call_p (insn)
874 && ! i386_ret_p (insn))
879 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
881 /* A signal trampoline system call changes the %eip, resuming
882 execution of the main program after the signal handler has
883 returned. That makes them like 'return' instructions; we
884 shouldn't relocate %eip.
886 But most system calls don't, and we do need to relocate %eip.
888 Our heuristic for distinguishing these cases: if stepping
889 over the system call instruction left control directly after
890 the instruction, the we relocate --- control almost certainly
891 doesn't belong in the displaced copy. Otherwise, we assume
892 the instruction has put control where it belongs, and leave
893 it unrelocated. Goodness help us if there are PC-relative
895 if (i386_syscall_p (insn, &insn_len)
896 && orig_eip != to + (insn - insn_start) + insn_len
897 /* GDB can get control back after the insn after the syscall.
898 Presumably this is a kernel bug.
899 i386_displaced_step_copy_insn ensures its a nop,
900 we add one to the length for it. */
901 && orig_eip != to + (insn - insn_start) + insn_len + 1)
904 fprintf_unfiltered (gdb_stdlog,
905 "displaced: syscall changed %%eip; "
910 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
912 /* If we just stepped over a breakpoint insn, we don't backup
913 the pc on purpose; this is to match behaviour without
916 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
919 fprintf_unfiltered (gdb_stdlog,
921 "relocated %%eip from %s to %s\n",
922 paddress (gdbarch, orig_eip),
923 paddress (gdbarch, eip));
927 /* If the instruction was PUSHFL, then the TF bit will be set in the
928 pushed value, and should be cleared. We'll leave this for later,
929 since GDB already messes up the TF flag when stepping over a
932 /* If the instruction was a call, the return address now atop the
933 stack is the address following the copied instruction. We need
934 to make it the address following the original instruction. */
935 if (i386_call_p (insn))
939 const ULONGEST retaddr_len = 4;
941 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
942 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
943 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
944 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
947 fprintf_unfiltered (gdb_stdlog,
948 "displaced: relocated return addr at %s to %s\n",
949 paddress (gdbarch, esp),
950 paddress (gdbarch, retaddr));
955 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
957 target_write_memory (*to, buf, len);
962 i386_relocate_instruction (struct gdbarch *gdbarch,
963 CORE_ADDR *to, CORE_ADDR oldloc)
965 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
966 gdb_byte buf[I386_MAX_INSN_LEN];
967 int offset = 0, rel32, newrel;
969 gdb_byte *insn = buf;
971 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
973 insn_length = gdb_buffered_insn_length (gdbarch, insn,
974 I386_MAX_INSN_LEN, oldloc);
976 /* Get past the prefixes. */
977 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
979 /* Adjust calls with 32-bit relative addresses as push/jump, with
980 the address pushed being the location where the original call in
981 the user program would return to. */
984 gdb_byte push_buf[16];
985 unsigned int ret_addr;
987 /* Where "ret" in the original code will return to. */
988 ret_addr = oldloc + insn_length;
989 push_buf[0] = 0x68; /* pushq $... */
990 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
992 append_insns (to, 5, push_buf);
994 /* Convert the relative call to a relative jump. */
997 /* Adjust the destination offset. */
998 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
999 newrel = (oldloc - *to) + rel32;
1000 store_signed_integer (insn + 1, 4, byte_order, newrel);
1002 if (debug_displaced)
1003 fprintf_unfiltered (gdb_stdlog,
1004 "Adjusted insn rel32=%s at %s to"
1005 " rel32=%s at %s\n",
1006 hex_string (rel32), paddress (gdbarch, oldloc),
1007 hex_string (newrel), paddress (gdbarch, *to));
1009 /* Write the adjusted jump into its displaced location. */
1010 append_insns (to, 5, insn);
1014 /* Adjust jumps with 32-bit relative addresses. Calls are already
1016 if (insn[0] == 0xe9)
1018 /* Adjust conditional jumps. */
1019 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1024 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1025 newrel = (oldloc - *to) + rel32;
1026 store_signed_integer (insn + offset, 4, byte_order, newrel);
1027 if (debug_displaced)
1028 fprintf_unfiltered (gdb_stdlog,
1029 "Adjusted insn rel32=%s at %s to"
1030 " rel32=%s at %s\n",
1031 hex_string (rel32), paddress (gdbarch, oldloc),
1032 hex_string (newrel), paddress (gdbarch, *to));
1035 /* Write the adjusted instructions into their displaced
1037 append_insns (to, insn_length, buf);
1041 #ifdef I386_REGNO_TO_SYMMETRY
1042 #error "The Sequent Symmetry is no longer supported."
1045 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1046 and %esp "belong" to the calling function. Therefore these
1047 registers should be saved if they're going to be modified. */
1049 /* The maximum number of saved registers. This should include all
1050 registers mentioned above, and %eip. */
1051 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1053 struct i386_frame_cache
1061 /* Saved registers. */
1062 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
1067 /* Stack space reserved for local variables. */
1071 /* Allocate and initialize a frame cache. */
1073 static struct i386_frame_cache *
1074 i386_alloc_frame_cache (void)
1076 struct i386_frame_cache *cache;
1079 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
1084 cache->sp_offset = -4;
1087 /* Saved registers. We initialize these to -1 since zero is a valid
1088 offset (that's where %ebp is supposed to be stored). */
1089 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1090 cache->saved_regs[i] = -1;
1091 cache->saved_sp = 0;
1092 cache->saved_sp_reg = -1;
1093 cache->pc_in_eax = 0;
1095 /* Frameless until proven otherwise. */
1101 /* If the instruction at PC is a jump, return the address of its
1102 target. Otherwise, return PC. */
1105 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
1107 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1112 if (target_read_code (pc, &op, 1))
1119 op = read_code_unsigned_integer (pc + 1, 1, byte_order);
1125 /* Relative jump: if data16 == 0, disp32, else disp16. */
1128 delta = read_memory_integer (pc + 2, 2, byte_order);
1130 /* Include the size of the jmp instruction (including the
1136 delta = read_memory_integer (pc + 1, 4, byte_order);
1138 /* Include the size of the jmp instruction. */
1143 /* Relative jump, disp8 (ignore data16). */
1144 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
1146 delta += data16 + 2;
1153 /* Check whether PC points at a prologue for a function returning a
1154 structure or union. If so, it updates CACHE and returns the
1155 address of the first instruction after the code sequence that
1156 removes the "hidden" argument from the stack or CURRENT_PC,
1157 whichever is smaller. Otherwise, return PC. */
1160 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
1161 struct i386_frame_cache *cache)
1163 /* Functions that return a structure or union start with:
1166 xchgl %eax, (%esp) 0x87 0x04 0x24
1167 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1169 (the System V compiler puts out the second `xchg' instruction,
1170 and the assembler doesn't try to optimize it, so the 'sib' form
1171 gets generated). This sequence is used to get the address of the
1172 return buffer for a function that returns a structure. */
1173 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
1174 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
1178 if (current_pc <= pc)
1181 if (target_read_code (pc, &op, 1))
1184 if (op != 0x58) /* popl %eax */
1187 if (target_read_code (pc + 1, buf, 4))
1190 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
1193 if (current_pc == pc)
1195 cache->sp_offset += 4;
1199 if (current_pc == pc + 1)
1201 cache->pc_in_eax = 1;
1205 if (buf[1] == proto1[1])
1212 i386_skip_probe (CORE_ADDR pc)
1214 /* A function may start with
1228 if (target_read_code (pc, &op, 1))
1231 if (op == 0x68 || op == 0x6a)
1235 /* Skip past the `pushl' instruction; it has either a one-byte or a
1236 four-byte operand, depending on the opcode. */
1242 /* Read the following 8 bytes, which should be `call _probe' (6
1243 bytes) followed by `addl $4,%esp' (2 bytes). */
1244 read_memory (pc + delta, buf, sizeof (buf));
1245 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
1246 pc += delta + sizeof (buf);
1252 /* GCC 4.1 and later, can put code in the prologue to realign the
1253 stack pointer. Check whether PC points to such code, and update
1254 CACHE accordingly. Return the first instruction after the code
1255 sequence or CURRENT_PC, whichever is smaller. If we don't
1256 recognize the code, return PC. */
1259 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1260 struct i386_frame_cache *cache)
1262 /* There are 2 code sequences to re-align stack before the frame
1265 1. Use a caller-saved saved register:
1271 2. Use a callee-saved saved register:
1278 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1280 0x83 0xe4 0xf0 andl $-16, %esp
1281 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1286 int offset, offset_and;
1287 static int regnums[8] = {
1288 I386_EAX_REGNUM, /* %eax */
1289 I386_ECX_REGNUM, /* %ecx */
1290 I386_EDX_REGNUM, /* %edx */
1291 I386_EBX_REGNUM, /* %ebx */
1292 I386_ESP_REGNUM, /* %esp */
1293 I386_EBP_REGNUM, /* %ebp */
1294 I386_ESI_REGNUM, /* %esi */
1295 I386_EDI_REGNUM /* %edi */
1298 if (target_read_code (pc, buf, sizeof buf))
1301 /* Check caller-saved saved register. The first instruction has
1302 to be "leal 4(%esp), %reg". */
1303 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1305 /* MOD must be binary 10 and R/M must be binary 100. */
1306 if ((buf[1] & 0xc7) != 0x44)
1309 /* REG has register number. */
1310 reg = (buf[1] >> 3) & 7;
1315 /* Check callee-saved saved register. The first instruction
1316 has to be "pushl %reg". */
1317 if ((buf[0] & 0xf8) != 0x50)
1323 /* The next instruction has to be "leal 8(%esp), %reg". */
1324 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1327 /* MOD must be binary 10 and R/M must be binary 100. */
1328 if ((buf[2] & 0xc7) != 0x44)
1331 /* REG has register number. Registers in pushl and leal have to
1333 if (reg != ((buf[2] >> 3) & 7))
1339 /* Rigister can't be %esp nor %ebp. */
1340 if (reg == 4 || reg == 5)
1343 /* The next instruction has to be "andl $-XXX, %esp". */
1344 if (buf[offset + 1] != 0xe4
1345 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1348 offset_and = offset;
1349 offset += buf[offset] == 0x81 ? 6 : 3;
1351 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1352 0xfc. REG must be binary 110 and MOD must be binary 01. */
1353 if (buf[offset] != 0xff
1354 || buf[offset + 2] != 0xfc
1355 || (buf[offset + 1] & 0xf8) != 0x70)
1358 /* R/M has register. Registers in leal and pushl have to be the
1360 if (reg != (buf[offset + 1] & 7))
1363 if (current_pc > pc + offset_and)
1364 cache->saved_sp_reg = regnums[reg];
1366 return std::min (pc + offset + 3, current_pc);
1369 /* Maximum instruction length we need to handle. */
1370 #define I386_MAX_MATCHED_INSN_LEN 6
1372 /* Instruction description. */
1376 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
1377 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
1380 /* Return whether instruction at PC matches PATTERN. */
1383 i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern)
1387 if (target_read_code (pc, &op, 1))
1390 if ((op & pattern.mask[0]) == pattern.insn[0])
1392 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1393 int insn_matched = 1;
1396 gdb_assert (pattern.len > 1);
1397 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN);
1399 if (target_read_code (pc + 1, buf, pattern.len - 1))
1402 for (i = 1; i < pattern.len; i++)
1404 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i])
1407 return insn_matched;
1412 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1413 the first instruction description that matches. Otherwise, return
1416 static struct i386_insn *
1417 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns)
1419 struct i386_insn *pattern;
1421 for (pattern = insn_patterns; pattern->len > 0; pattern++)
1423 if (i386_match_pattern (pc, *pattern))
1430 /* Return whether PC points inside a sequence of instructions that
1431 matches INSN_PATTERNS. */
1434 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns)
1436 CORE_ADDR current_pc;
1438 struct i386_insn *insn;
1440 insn = i386_match_insn (pc, insn_patterns);
1445 ix = insn - insn_patterns;
1446 for (i = ix - 1; i >= 0; i--)
1448 current_pc -= insn_patterns[i].len;
1450 if (!i386_match_pattern (current_pc, insn_patterns[i]))
1454 current_pc = pc + insn->len;
1455 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++)
1457 if (!i386_match_pattern (current_pc, *insn))
1460 current_pc += insn->len;
1466 /* Some special instructions that might be migrated by GCC into the
1467 part of the prologue that sets up the new stack frame. Because the
1468 stack frame hasn't been setup yet, no registers have been saved
1469 yet, and only the scratch registers %eax, %ecx and %edx can be
1472 struct i386_insn i386_frame_setup_skip_insns[] =
1474 /* Check for `movb imm8, r' and `movl imm32, r'.
1476 ??? Should we handle 16-bit operand-sizes here? */
1478 /* `movb imm8, %al' and `movb imm8, %ah' */
1479 /* `movb imm8, %cl' and `movb imm8, %ch' */
1480 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1481 /* `movb imm8, %dl' and `movb imm8, %dh' */
1482 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1483 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1484 { 5, { 0xb8 }, { 0xfe } },
1485 /* `movl imm32, %edx' */
1486 { 5, { 0xba }, { 0xff } },
1488 /* Check for `mov imm32, r32'. Note that there is an alternative
1489 encoding for `mov m32, %eax'.
1491 ??? Should we handle SIB adressing here?
1492 ??? Should we handle 16-bit operand-sizes here? */
1494 /* `movl m32, %eax' */
1495 { 5, { 0xa1 }, { 0xff } },
1496 /* `movl m32, %eax' and `mov; m32, %ecx' */
1497 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1498 /* `movl m32, %edx' */
1499 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1501 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1502 Because of the symmetry, there are actually two ways to encode
1503 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1504 opcode bytes 0x31 and 0x33 for `xorl'. */
1506 /* `subl %eax, %eax' */
1507 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1508 /* `subl %ecx, %ecx' */
1509 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1510 /* `subl %edx, %edx' */
1511 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1512 /* `xorl %eax, %eax' */
1513 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1514 /* `xorl %ecx, %ecx' */
1515 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1516 /* `xorl %edx, %edx' */
1517 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1522 /* Check whether PC points to a no-op instruction. */
1524 i386_skip_noop (CORE_ADDR pc)
1529 if (target_read_code (pc, &op, 1))
1535 /* Ignore `nop' instruction. */
1539 if (target_read_code (pc, &op, 1))
1543 /* Ignore no-op instruction `mov %edi, %edi'.
1544 Microsoft system dlls often start with
1545 a `mov %edi,%edi' instruction.
1546 The 5 bytes before the function start are
1547 filled with `nop' instructions.
1548 This pattern can be used for hot-patching:
1549 The `mov %edi, %edi' instruction can be replaced by a
1550 near jump to the location of the 5 `nop' instructions
1551 which can be replaced by a 32-bit jump to anywhere
1552 in the 32-bit address space. */
1554 else if (op == 0x8b)
1556 if (target_read_code (pc + 1, &op, 1))
1562 if (target_read_code (pc, &op, 1))
1572 /* Check whether PC points at a code that sets up a new stack frame.
1573 If so, it updates CACHE and returns the address of the first
1574 instruction after the sequence that sets up the frame or LIMIT,
1575 whichever is smaller. If we don't recognize the code, return PC. */
1578 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1579 CORE_ADDR pc, CORE_ADDR limit,
1580 struct i386_frame_cache *cache)
1582 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1583 struct i386_insn *insn;
1590 if (target_read_code (pc, &op, 1))
1593 if (op == 0x55) /* pushl %ebp */
1595 /* Take into account that we've executed the `pushl %ebp' that
1596 starts this instruction sequence. */
1597 cache->saved_regs[I386_EBP_REGNUM] = 0;
1598 cache->sp_offset += 4;
1601 /* If that's all, return now. */
1605 /* Check for some special instructions that might be migrated by
1606 GCC into the prologue and skip them. At this point in the
1607 prologue, code should only touch the scratch registers %eax,
1608 %ecx and %edx, so while the number of posibilities is sheer,
1611 Make sure we only skip these instructions if we later see the
1612 `movl %esp, %ebp' that actually sets up the frame. */
1613 while (pc + skip < limit)
1615 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1622 /* If that's all, return now. */
1623 if (limit <= pc + skip)
1626 if (target_read_code (pc + skip, &op, 1))
1629 /* The i386 prologue looks like
1635 and a different prologue can be generated for atom.
1639 lea -0x10(%esp),%esp
1641 We handle both of them here. */
1645 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1647 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1653 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1658 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1659 if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order)
1668 /* OK, we actually have a frame. We just don't know how large
1669 it is yet. Set its size to zero. We'll adjust it if
1670 necessary. We also now commit to skipping the special
1671 instructions mentioned before. */
1674 /* If that's all, return now. */
1678 /* Check for stack adjustment
1684 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1685 reg, so we don't have to worry about a data16 prefix. */
1686 if (target_read_code (pc, &op, 1))
1690 /* `subl' with 8-bit immediate. */
1691 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1692 /* Some instruction starting with 0x83 other than `subl'. */
1695 /* `subl' with signed 8-bit immediate (though it wouldn't
1696 make sense to be negative). */
1697 cache->locals = read_code_integer (pc + 2, 1, byte_order);
1700 else if (op == 0x81)
1702 /* Maybe it is `subl' with a 32-bit immediate. */
1703 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1704 /* Some instruction starting with 0x81 other than `subl'. */
1707 /* It is `subl' with a 32-bit immediate. */
1708 cache->locals = read_code_integer (pc + 2, 4, byte_order);
1711 else if (op == 0x8d)
1713 /* The ModR/M byte is 0x64. */
1714 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64)
1716 /* 'lea' with 8-bit displacement. */
1717 cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order);
1722 /* Some instruction other than `subl' nor 'lea'. */
1726 else if (op == 0xc8) /* enter */
1728 cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order);
1735 /* Check whether PC points at code that saves registers on the stack.
1736 If so, it updates CACHE and returns the address of the first
1737 instruction after the register saves or CURRENT_PC, whichever is
1738 smaller. Otherwise, return PC. */
1741 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1742 struct i386_frame_cache *cache)
1744 CORE_ADDR offset = 0;
1748 if (cache->locals > 0)
1749 offset -= cache->locals;
1750 for (i = 0; i < 8 && pc < current_pc; i++)
1752 if (target_read_code (pc, &op, 1))
1754 if (op < 0x50 || op > 0x57)
1758 cache->saved_regs[op - 0x50] = offset;
1759 cache->sp_offset += 4;
1766 /* Do a full analysis of the prologue at PC and update CACHE
1767 accordingly. Bail out early if CURRENT_PC is reached. Return the
1768 address where the analysis stopped.
1770 We handle these cases:
1772 The startup sequence can be at the start of the function, or the
1773 function can start with a branch to startup code at the end.
1775 %ebp can be set up with either the 'enter' instruction, or "pushl
1776 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1777 once used in the System V compiler).
1779 Local space is allocated just below the saved %ebp by either the
1780 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1781 16-bit unsigned argument for space to allocate, and the 'addl'
1782 instruction could have either a signed byte, or 32-bit immediate.
1784 Next, the registers used by this function are pushed. With the
1785 System V compiler they will always be in the order: %edi, %esi,
1786 %ebx (and sometimes a harmless bug causes it to also save but not
1787 restore %eax); however, the code below is willing to see the pushes
1788 in any order, and will handle up to 8 of them.
1790 If the setup sequence is at the end of the function, then the next
1791 instruction will be a branch back to the start. */
1794 i386_analyze_prologue (struct gdbarch *gdbarch,
1795 CORE_ADDR pc, CORE_ADDR current_pc,
1796 struct i386_frame_cache *cache)
1798 pc = i386_skip_noop (pc);
1799 pc = i386_follow_jump (gdbarch, pc);
1800 pc = i386_analyze_struct_return (pc, current_pc, cache);
1801 pc = i386_skip_probe (pc);
1802 pc = i386_analyze_stack_align (pc, current_pc, cache);
1803 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1804 return i386_analyze_register_saves (pc, current_pc, cache);
1807 /* Return PC of first real instruction. */
1810 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1812 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1814 static gdb_byte pic_pat[6] =
1816 0xe8, 0, 0, 0, 0, /* call 0x0 */
1817 0x5b, /* popl %ebx */
1819 struct i386_frame_cache cache;
1823 CORE_ADDR func_addr;
1825 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
1827 CORE_ADDR post_prologue_pc
1828 = skip_prologue_using_sal (gdbarch, func_addr);
1829 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
1831 /* Clang always emits a line note before the prologue and another
1832 one after. We trust clang to emit usable line notes. */
1833 if (post_prologue_pc
1835 && COMPUNIT_PRODUCER (cust) != NULL
1836 && startswith (COMPUNIT_PRODUCER (cust), "clang ")))
1837 return std::max (start_pc, post_prologue_pc);
1841 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1842 if (cache.locals < 0)
1845 /* Found valid frame setup. */
1847 /* The native cc on SVR4 in -K PIC mode inserts the following code
1848 to get the address of the global offset table (GOT) into register
1853 movl %ebx,x(%ebp) (optional)
1856 This code is with the rest of the prologue (at the end of the
1857 function), so we have to skip it to get to the first real
1858 instruction at the start of the function. */
1860 for (i = 0; i < 6; i++)
1862 if (target_read_code (pc + i, &op, 1))
1865 if (pic_pat[i] != op)
1872 if (target_read_code (pc + delta, &op, 1))
1875 if (op == 0x89) /* movl %ebx, x(%ebp) */
1877 op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order);
1879 if (op == 0x5d) /* One byte offset from %ebp. */
1881 else if (op == 0x9d) /* Four byte offset from %ebp. */
1883 else /* Unexpected instruction. */
1886 if (target_read_code (pc + delta, &op, 1))
1891 if (delta > 0 && op == 0x81
1892 && read_code_unsigned_integer (pc + delta + 1, 1, byte_order)
1899 /* If the function starts with a branch (to startup code at the end)
1900 the last instruction should bring us back to the first
1901 instruction of the real code. */
1902 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1903 pc = i386_follow_jump (gdbarch, pc);
1908 /* Check that the code pointed to by PC corresponds to a call to
1909 __main, skip it if so. Return PC otherwise. */
1912 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1914 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1917 if (target_read_code (pc, &op, 1))
1923 if (target_read_code (pc + 1, buf, sizeof buf) == 0)
1925 /* Make sure address is computed correctly as a 32bit
1926 integer even if CORE_ADDR is 64 bit wide. */
1927 struct bound_minimal_symbol s;
1928 CORE_ADDR call_dest;
1930 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1931 call_dest = call_dest & 0xffffffffU;
1932 s = lookup_minimal_symbol_by_pc (call_dest);
1933 if (s.minsym != NULL
1934 && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL
1935 && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0)
1943 /* This function is 64-bit safe. */
1946 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1950 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1951 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1955 /* Normal frames. */
1958 i386_frame_cache_1 (struct frame_info *this_frame,
1959 struct i386_frame_cache *cache)
1961 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1962 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1966 cache->pc = get_frame_func (this_frame);
1968 /* In principle, for normal frames, %ebp holds the frame pointer,
1969 which holds the base address for the current stack frame.
1970 However, for functions that don't need it, the frame pointer is
1971 optional. For these "frameless" functions the frame pointer is
1972 actually the frame pointer of the calling frame. Signal
1973 trampolines are just a special case of a "frameless" function.
1974 They (usually) share their frame pointer with the frame that was
1975 in progress when the signal occurred. */
1977 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1978 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1979 if (cache->base == 0)
1985 /* For normal frames, %eip is stored at 4(%ebp). */
1986 cache->saved_regs[I386_EIP_REGNUM] = 4;
1989 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
1992 if (cache->locals < 0)
1994 /* We didn't find a valid frame, which means that CACHE->base
1995 currently holds the frame pointer for our calling frame. If
1996 we're at the start of a function, or somewhere half-way its
1997 prologue, the function's frame probably hasn't been fully
1998 setup yet. Try to reconstruct the base address for the stack
1999 frame by looking at the stack pointer. For truly "frameless"
2000 functions this might work too. */
2002 if (cache->saved_sp_reg != -1)
2004 /* Saved stack pointer has been saved. */
2005 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2006 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2008 /* We're halfway aligning the stack. */
2009 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
2010 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
2012 /* This will be added back below. */
2013 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
2015 else if (cache->pc != 0
2016 || target_read_code (get_frame_pc (this_frame), buf, 1))
2018 /* We're in a known function, but did not find a frame
2019 setup. Assume that the function does not use %ebp.
2020 Alternatively, we may have jumped to an invalid
2021 address; in that case there is definitely no new
2023 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2024 cache->base = extract_unsigned_integer (buf, 4, byte_order)
2028 /* We're in an unknown function. We could not find the start
2029 of the function to analyze the prologue; our best option is
2030 to assume a typical frame layout with the caller's %ebp
2032 cache->saved_regs[I386_EBP_REGNUM] = 0;
2035 if (cache->saved_sp_reg != -1)
2037 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2038 register may be unavailable). */
2039 if (cache->saved_sp == 0
2040 && deprecated_frame_register_read (this_frame,
2041 cache->saved_sp_reg, buf))
2042 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2044 /* Now that we have the base address for the stack frame we can
2045 calculate the value of %esp in the calling frame. */
2046 else if (cache->saved_sp == 0)
2047 cache->saved_sp = cache->base + 8;
2049 /* Adjust all the saved registers such that they contain addresses
2050 instead of offsets. */
2051 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
2052 if (cache->saved_regs[i] != -1)
2053 cache->saved_regs[i] += cache->base;
2058 static struct i386_frame_cache *
2059 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
2061 struct i386_frame_cache *cache;
2064 return (struct i386_frame_cache *) *this_cache;
2066 cache = i386_alloc_frame_cache ();
2067 *this_cache = cache;
2071 i386_frame_cache_1 (this_frame, cache);
2073 CATCH (ex, RETURN_MASK_ERROR)
2075 if (ex.error != NOT_AVAILABLE_ERROR)
2076 throw_exception (ex);
2084 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
2085 struct frame_id *this_id)
2087 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2090 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2091 else if (cache->base == 0)
2093 /* This marks the outermost frame. */
2097 /* See the end of i386_push_dummy_call. */
2098 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2102 static enum unwind_stop_reason
2103 i386_frame_unwind_stop_reason (struct frame_info *this_frame,
2106 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2109 return UNWIND_UNAVAILABLE;
2111 /* This marks the outermost frame. */
2112 if (cache->base == 0)
2113 return UNWIND_OUTERMOST;
2115 return UNWIND_NO_REASON;
2118 static struct value *
2119 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2122 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2124 gdb_assert (regnum >= 0);
2126 /* The System V ABI says that:
2128 "The flags register contains the system flags, such as the
2129 direction flag and the carry flag. The direction flag must be
2130 set to the forward (that is, zero) direction before entry and
2131 upon exit from a function. Other user flags have no specified
2132 role in the standard calling sequence and are not preserved."
2134 To guarantee the "upon exit" part of that statement we fake a
2135 saved flags register that has its direction flag cleared.
2137 Note that GCC doesn't seem to rely on the fact that the direction
2138 flag is cleared after a function return; it always explicitly
2139 clears the flag before operations where it matters.
2141 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2142 right thing to do. The way we fake the flags register here makes
2143 it impossible to change it. */
2145 if (regnum == I386_EFLAGS_REGNUM)
2149 val = get_frame_register_unsigned (this_frame, regnum);
2151 return frame_unwind_got_constant (this_frame, regnum, val);
2154 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
2155 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
2157 if (regnum == I386_ESP_REGNUM
2158 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1))
2160 /* If the SP has been saved, but we don't know where, then this
2161 means that SAVED_SP_REG register was found unavailable back
2162 when we built the cache. */
2163 if (cache->saved_sp == 0)
2164 return frame_unwind_got_register (this_frame, regnum,
2165 cache->saved_sp_reg);
2167 return frame_unwind_got_constant (this_frame, regnum,
2171 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2172 return frame_unwind_got_memory (this_frame, regnum,
2173 cache->saved_regs[regnum]);
2175 return frame_unwind_got_register (this_frame, regnum, regnum);
2178 static const struct frame_unwind i386_frame_unwind =
2181 i386_frame_unwind_stop_reason,
2183 i386_frame_prev_register,
2185 default_frame_sniffer
2188 /* Normal frames, but in a function epilogue. */
2190 /* Implement the stack_frame_destroyed_p gdbarch method.
2192 The epilogue is defined here as the 'ret' instruction, which will
2193 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2194 the function's stack frame. */
2197 i386_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2200 struct compunit_symtab *cust;
2202 cust = find_pc_compunit_symtab (pc);
2203 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
2206 if (target_read_memory (pc, &insn, 1))
2207 return 0; /* Can't read memory at pc. */
2209 if (insn != 0xc3) /* 'ret' instruction. */
2216 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
2217 struct frame_info *this_frame,
2218 void **this_prologue_cache)
2220 if (frame_relative_level (this_frame) == 0)
2221 return i386_stack_frame_destroyed_p (get_frame_arch (this_frame),
2222 get_frame_pc (this_frame));
2227 static struct i386_frame_cache *
2228 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2230 struct i386_frame_cache *cache;
2234 return (struct i386_frame_cache *) *this_cache;
2236 cache = i386_alloc_frame_cache ();
2237 *this_cache = cache;
2241 cache->pc = get_frame_func (this_frame);
2243 /* At this point the stack looks as if we just entered the
2244 function, with the return address at the top of the
2246 sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM);
2247 cache->base = sp + cache->sp_offset;
2248 cache->saved_sp = cache->base + 8;
2249 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
2253 CATCH (ex, RETURN_MASK_ERROR)
2255 if (ex.error != NOT_AVAILABLE_ERROR)
2256 throw_exception (ex);
2263 static enum unwind_stop_reason
2264 i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2267 struct i386_frame_cache *cache =
2268 i386_epilogue_frame_cache (this_frame, this_cache);
2271 return UNWIND_UNAVAILABLE;
2273 return UNWIND_NO_REASON;
2277 i386_epilogue_frame_this_id (struct frame_info *this_frame,
2279 struct frame_id *this_id)
2281 struct i386_frame_cache *cache =
2282 i386_epilogue_frame_cache (this_frame, this_cache);
2285 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2287 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2290 static struct value *
2291 i386_epilogue_frame_prev_register (struct frame_info *this_frame,
2292 void **this_cache, int regnum)
2294 /* Make sure we've initialized the cache. */
2295 i386_epilogue_frame_cache (this_frame, this_cache);
2297 return i386_frame_prev_register (this_frame, this_cache, regnum);
2300 static const struct frame_unwind i386_epilogue_frame_unwind =
2303 i386_epilogue_frame_unwind_stop_reason,
2304 i386_epilogue_frame_this_id,
2305 i386_epilogue_frame_prev_register,
2307 i386_epilogue_frame_sniffer
2311 /* Stack-based trampolines. */
2313 /* These trampolines are used on cross x86 targets, when taking the
2314 address of a nested function. When executing these trampolines,
2315 no stack frame is set up, so we are in a similar situation as in
2316 epilogues and i386_epilogue_frame_this_id can be re-used. */
2318 /* Static chain passed in register. */
2320 struct i386_insn i386_tramp_chain_in_reg_insns[] =
2322 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2323 { 5, { 0xb8 }, { 0xfe } },
2326 { 5, { 0xe9 }, { 0xff } },
2331 /* Static chain passed on stack (when regparm=3). */
2333 struct i386_insn i386_tramp_chain_on_stack_insns[] =
2336 { 5, { 0x68 }, { 0xff } },
2339 { 5, { 0xe9 }, { 0xff } },
2344 /* Return whether PC points inside a stack trampoline. */
2347 i386_in_stack_tramp_p (CORE_ADDR pc)
2352 /* A stack trampoline is detected if no name is associated
2353 to the current pc and if it points inside a trampoline
2356 find_pc_partial_function (pc, &name, NULL, NULL);
2360 if (target_read_memory (pc, &insn, 1))
2363 if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns)
2364 && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns))
2371 i386_stack_tramp_frame_sniffer (const struct frame_unwind *self,
2372 struct frame_info *this_frame,
2375 if (frame_relative_level (this_frame) == 0)
2376 return i386_in_stack_tramp_p (get_frame_pc (this_frame));
2381 static const struct frame_unwind i386_stack_tramp_frame_unwind =
2384 i386_epilogue_frame_unwind_stop_reason,
2385 i386_epilogue_frame_this_id,
2386 i386_epilogue_frame_prev_register,
2388 i386_stack_tramp_frame_sniffer
2391 /* Generate a bytecode expression to get the value of the saved PC. */
2394 i386_gen_return_address (struct gdbarch *gdbarch,
2395 struct agent_expr *ax, struct axs_value *value,
2398 /* The following sequence assumes the traditional use of the base
2400 ax_reg (ax, I386_EBP_REGNUM);
2402 ax_simple (ax, aop_add);
2403 value->type = register_type (gdbarch, I386_EIP_REGNUM);
2404 value->kind = axs_lvalue_memory;
2408 /* Signal trampolines. */
2410 static struct i386_frame_cache *
2411 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2413 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2414 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2415 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2416 struct i386_frame_cache *cache;
2421 return (struct i386_frame_cache *) *this_cache;
2423 cache = i386_alloc_frame_cache ();
2427 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2428 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
2430 addr = tdep->sigcontext_addr (this_frame);
2431 if (tdep->sc_reg_offset)
2435 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
2437 for (i = 0; i < tdep->sc_num_regs; i++)
2438 if (tdep->sc_reg_offset[i] != -1)
2439 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2443 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
2444 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
2449 CATCH (ex, RETURN_MASK_ERROR)
2451 if (ex.error != NOT_AVAILABLE_ERROR)
2452 throw_exception (ex);
2456 *this_cache = cache;
2460 static enum unwind_stop_reason
2461 i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2464 struct i386_frame_cache *cache =
2465 i386_sigtramp_frame_cache (this_frame, this_cache);
2468 return UNWIND_UNAVAILABLE;
2470 return UNWIND_NO_REASON;
2474 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
2475 struct frame_id *this_id)
2477 struct i386_frame_cache *cache =
2478 i386_sigtramp_frame_cache (this_frame, this_cache);
2481 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2484 /* See the end of i386_push_dummy_call. */
2485 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
2489 static struct value *
2490 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
2491 void **this_cache, int regnum)
2493 /* Make sure we've initialized the cache. */
2494 i386_sigtramp_frame_cache (this_frame, this_cache);
2496 return i386_frame_prev_register (this_frame, this_cache, regnum);
2500 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
2501 struct frame_info *this_frame,
2502 void **this_prologue_cache)
2504 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2506 /* We shouldn't even bother if we don't have a sigcontext_addr
2508 if (tdep->sigcontext_addr == NULL)
2511 if (tdep->sigtramp_p != NULL)
2513 if (tdep->sigtramp_p (this_frame))
2517 if (tdep->sigtramp_start != 0)
2519 CORE_ADDR pc = get_frame_pc (this_frame);
2521 gdb_assert (tdep->sigtramp_end != 0);
2522 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2529 static const struct frame_unwind i386_sigtramp_frame_unwind =
2532 i386_sigtramp_frame_unwind_stop_reason,
2533 i386_sigtramp_frame_this_id,
2534 i386_sigtramp_frame_prev_register,
2536 i386_sigtramp_frame_sniffer
2541 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
2543 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2548 static const struct frame_base i386_frame_base =
2551 i386_frame_base_address,
2552 i386_frame_base_address,
2553 i386_frame_base_address
2556 static struct frame_id
2557 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2561 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
2563 /* See the end of i386_push_dummy_call. */
2564 return frame_id_build (fp + 8, get_frame_pc (this_frame));
2567 /* _Decimal128 function return values need 16-byte alignment on the
2571 i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2573 return sp & -(CORE_ADDR)16;
2577 /* Figure out where the longjmp will land. Slurp the args out of the
2578 stack. We expect the first arg to be a pointer to the jmp_buf
2579 structure from which we extract the address that we will land at.
2580 This address is copied into PC. This routine returns non-zero on
2584 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2587 CORE_ADDR sp, jb_addr;
2588 struct gdbarch *gdbarch = get_frame_arch (frame);
2589 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2590 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2592 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2593 longjmp will land. */
2594 if (jb_pc_offset == -1)
2597 get_frame_register (frame, I386_ESP_REGNUM, buf);
2598 sp = extract_unsigned_integer (buf, 4, byte_order);
2599 if (target_read_memory (sp + 4, buf, 4))
2602 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
2603 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
2606 *pc = extract_unsigned_integer (buf, 4, byte_order);
2611 /* Check whether TYPE must be 16-byte-aligned when passed as a
2612 function argument. 16-byte vectors, _Decimal128 and structures or
2613 unions containing such types must be 16-byte-aligned; other
2614 arguments are 4-byte-aligned. */
2617 i386_16_byte_align_p (struct type *type)
2619 type = check_typedef (type);
2620 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
2621 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
2622 && TYPE_LENGTH (type) == 16)
2624 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2625 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
2626 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2627 || TYPE_CODE (type) == TYPE_CODE_UNION)
2630 for (i = 0; i < TYPE_NFIELDS (type); i++)
2632 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
2639 /* Implementation for set_gdbarch_push_dummy_code. */
2642 i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
2643 struct value **args, int nargs, struct type *value_type,
2644 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
2645 struct regcache *regcache)
2647 /* Use 0xcc breakpoint - 1 byte. */
2651 /* Keep the stack aligned. */
2656 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2657 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2658 struct value **args, CORE_ADDR sp, int struct_return,
2659 CORE_ADDR struct_addr)
2661 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2667 /* Determine the total space required for arguments and struct
2668 return address in a first pass (allowing for 16-byte-aligned
2669 arguments), then push arguments in a second pass. */
2671 for (write_pass = 0; write_pass < 2; write_pass++)
2673 int args_space_used = 0;
2679 /* Push value address. */
2680 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2681 write_memory (sp, buf, 4);
2682 args_space_used += 4;
2688 for (i = 0; i < nargs; i++)
2690 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2694 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2695 args_space_used = align_up (args_space_used, 16);
2697 write_memory (sp + args_space_used,
2698 value_contents_all (args[i]), len);
2699 /* The System V ABI says that:
2701 "An argument's size is increased, if necessary, to make it a
2702 multiple of [32-bit] words. This may require tail padding,
2703 depending on the size of the argument."
2705 This makes sure the stack stays word-aligned. */
2706 args_space_used += align_up (len, 4);
2710 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2711 args_space = align_up (args_space, 16);
2712 args_space += align_up (len, 4);
2720 /* The original System V ABI only requires word alignment,
2721 but modern incarnations need 16-byte alignment in order
2722 to support SSE. Since wasting a few bytes here isn't
2723 harmful we unconditionally enforce 16-byte alignment. */
2728 /* Store return address. */
2730 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2731 write_memory (sp, buf, 4);
2733 /* Finally, update the stack pointer... */
2734 store_unsigned_integer (buf, 4, byte_order, sp);
2735 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
2737 /* ...and fake a frame pointer. */
2738 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
2740 /* MarkK wrote: This "+ 8" is all over the place:
2741 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2742 i386_dummy_id). It's there, since all frame unwinders for
2743 a given target have to agree (within a certain margin) on the
2744 definition of the stack address of a frame. Otherwise frame id
2745 comparison might not work correctly. Since DWARF2/GCC uses the
2746 stack address *before* the function call as a frame's CFA. On
2747 the i386, when %ebp is used as a frame pointer, the offset
2748 between the contents %ebp and the CFA as defined by GCC. */
2752 /* These registers are used for returning integers (and on some
2753 targets also for returning `struct' and `union' values when their
2754 size and alignment match an integer type). */
2755 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2756 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2758 /* Read, for architecture GDBARCH, a function return value of TYPE
2759 from REGCACHE, and copy that into VALBUF. */
2762 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2763 struct regcache *regcache, gdb_byte *valbuf)
2765 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2766 int len = TYPE_LENGTH (type);
2767 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2769 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2771 if (tdep->st0_regnum < 0)
2773 warning (_("Cannot find floating-point return value."));
2774 memset (valbuf, 0, len);
2778 /* Floating-point return values can be found in %st(0). Convert
2779 its contents to the desired type. This is probably not
2780 exactly how it would happen on the target itself, but it is
2781 the best we can do. */
2782 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2783 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
2787 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2788 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2790 if (len <= low_size)
2792 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2793 memcpy (valbuf, buf, len);
2795 else if (len <= (low_size + high_size))
2797 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2798 memcpy (valbuf, buf, low_size);
2799 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2800 memcpy (valbuf + low_size, buf, len - low_size);
2803 internal_error (__FILE__, __LINE__,
2804 _("Cannot extract return value of %d bytes long."),
2809 /* Write, for architecture GDBARCH, a function return value of TYPE
2810 from VALBUF into REGCACHE. */
2813 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2814 struct regcache *regcache, const gdb_byte *valbuf)
2816 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2817 int len = TYPE_LENGTH (type);
2819 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2822 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2824 if (tdep->st0_regnum < 0)
2826 warning (_("Cannot set floating-point return value."));
2830 /* Returning floating-point values is a bit tricky. Apart from
2831 storing the return value in %st(0), we have to simulate the
2832 state of the FPU at function return point. */
2834 /* Convert the value found in VALBUF to the extended
2835 floating-point format used by the FPU. This is probably
2836 not exactly how it would happen on the target itself, but
2837 it is the best we can do. */
2838 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
2839 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2841 /* Set the top of the floating-point register stack to 7. The
2842 actual value doesn't really matter, but 7 is what a normal
2843 function return would end up with if the program started out
2844 with a freshly initialized FPU. */
2845 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2847 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2849 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2850 the floating-point register stack to 7, the appropriate value
2851 for the tag word is 0x3fff. */
2852 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2856 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2857 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2859 if (len <= low_size)
2860 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2861 else if (len <= (low_size + high_size))
2863 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2864 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
2865 len - low_size, valbuf + low_size);
2868 internal_error (__FILE__, __LINE__,
2869 _("Cannot store return value of %d bytes long."), len);
2874 /* This is the variable that is set with "set struct-convention", and
2875 its legitimate values. */
2876 static const char default_struct_convention[] = "default";
2877 static const char pcc_struct_convention[] = "pcc";
2878 static const char reg_struct_convention[] = "reg";
2879 static const char *const valid_conventions[] =
2881 default_struct_convention,
2882 pcc_struct_convention,
2883 reg_struct_convention,
2886 static const char *struct_convention = default_struct_convention;
2888 /* Return non-zero if TYPE, which is assumed to be a structure,
2889 a union type, or an array type, should be returned in registers
2890 for architecture GDBARCH. */
2893 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2895 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2896 enum type_code code = TYPE_CODE (type);
2897 int len = TYPE_LENGTH (type);
2899 gdb_assert (code == TYPE_CODE_STRUCT
2900 || code == TYPE_CODE_UNION
2901 || code == TYPE_CODE_ARRAY);
2903 if (struct_convention == pcc_struct_convention
2904 || (struct_convention == default_struct_convention
2905 && tdep->struct_return == pcc_struct_return))
2908 /* Structures consisting of a single `float', `double' or 'long
2909 double' member are returned in %st(0). */
2910 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2912 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2913 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2914 return (len == 4 || len == 8 || len == 12);
2917 return (len == 1 || len == 2 || len == 4 || len == 8);
2920 /* Determine, for architecture GDBARCH, how a return value of TYPE
2921 should be returned. If it is supposed to be returned in registers,
2922 and READBUF is non-zero, read the appropriate value from REGCACHE,
2923 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2924 from WRITEBUF into REGCACHE. */
2926 static enum return_value_convention
2927 i386_return_value (struct gdbarch *gdbarch, struct value *function,
2928 struct type *type, struct regcache *regcache,
2929 gdb_byte *readbuf, const gdb_byte *writebuf)
2931 enum type_code code = TYPE_CODE (type);
2933 if (((code == TYPE_CODE_STRUCT
2934 || code == TYPE_CODE_UNION
2935 || code == TYPE_CODE_ARRAY)
2936 && !i386_reg_struct_return_p (gdbarch, type))
2937 /* Complex double and long double uses the struct return covention. */
2938 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16)
2939 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24)
2940 /* 128-bit decimal float uses the struct return convention. */
2941 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2943 /* The System V ABI says that:
2945 "A function that returns a structure or union also sets %eax
2946 to the value of the original address of the caller's area
2947 before it returns. Thus when the caller receives control
2948 again, the address of the returned object resides in register
2949 %eax and can be used to access the object."
2951 So the ABI guarantees that we can always find the return
2952 value just after the function has returned. */
2954 /* Note that the ABI doesn't mention functions returning arrays,
2955 which is something possible in certain languages such as Ada.
2956 In this case, the value is returned as if it was wrapped in
2957 a record, so the convention applied to records also applies
2964 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2965 read_memory (addr, readbuf, TYPE_LENGTH (type));
2968 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2971 /* This special case is for structures consisting of a single
2972 `float', `double' or 'long double' member. These structures are
2973 returned in %st(0). For these structures, we call ourselves
2974 recursively, changing TYPE into the type of the first member of
2975 the structure. Since that should work for all structures that
2976 have only one member, we don't bother to check the member's type
2978 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2980 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2981 return i386_return_value (gdbarch, function, type, regcache,
2986 i386_extract_return_value (gdbarch, type, regcache, readbuf);
2988 i386_store_return_value (gdbarch, type, regcache, writebuf);
2990 return RETURN_VALUE_REGISTER_CONVENTION;
2995 i387_ext_type (struct gdbarch *gdbarch)
2997 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2999 if (!tdep->i387_ext_type)
3001 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
3002 gdb_assert (tdep->i387_ext_type != NULL);
3005 return tdep->i387_ext_type;
3008 /* Construct type for pseudo BND registers. We can't use
3009 tdesc_find_type since a complement of one value has to be used
3010 to describe the upper bound. */
3012 static struct type *
3013 i386_bnd_type (struct gdbarch *gdbarch)
3015 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3018 if (!tdep->i386_bnd_type)
3021 const struct builtin_type *bt = builtin_type (gdbarch);
3023 /* The type we're building is described bellow: */
3028 void *ubound; /* One complement of raw ubound field. */
3032 t = arch_composite_type (gdbarch,
3033 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT);
3035 append_composite_type_field (t, "lbound", bt->builtin_data_ptr);
3036 append_composite_type_field (t, "ubound", bt->builtin_data_ptr);
3038 TYPE_NAME (t) = "builtin_type_bound128";
3039 tdep->i386_bnd_type = t;
3042 return tdep->i386_bnd_type;
3045 /* Construct vector type for pseudo ZMM registers. We can't use
3046 tdesc_find_type since ZMM isn't described in target description. */
3048 static struct type *
3049 i386_zmm_type (struct gdbarch *gdbarch)
3051 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3053 if (!tdep->i386_zmm_type)
3055 const struct builtin_type *bt = builtin_type (gdbarch);
3057 /* The type we're building is this: */
3059 union __gdb_builtin_type_vec512i
3061 int128_t uint128[4];
3062 int64_t v4_int64[8];
3063 int32_t v8_int32[16];
3064 int16_t v16_int16[32];
3065 int8_t v32_int8[64];
3066 double v4_double[8];
3073 t = arch_composite_type (gdbarch,
3074 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION);
3075 append_composite_type_field (t, "v16_float",
3076 init_vector_type (bt->builtin_float, 16));
3077 append_composite_type_field (t, "v8_double",
3078 init_vector_type (bt->builtin_double, 8));
3079 append_composite_type_field (t, "v64_int8",
3080 init_vector_type (bt->builtin_int8, 64));
3081 append_composite_type_field (t, "v32_int16",
3082 init_vector_type (bt->builtin_int16, 32));
3083 append_composite_type_field (t, "v16_int32",
3084 init_vector_type (bt->builtin_int32, 16));
3085 append_composite_type_field (t, "v8_int64",
3086 init_vector_type (bt->builtin_int64, 8));
3087 append_composite_type_field (t, "v4_int128",
3088 init_vector_type (bt->builtin_int128, 4));
3090 TYPE_VECTOR (t) = 1;
3091 TYPE_NAME (t) = "builtin_type_vec512i";
3092 tdep->i386_zmm_type = t;
3095 return tdep->i386_zmm_type;
3098 /* Construct vector type for pseudo YMM registers. We can't use
3099 tdesc_find_type since YMM isn't described in target description. */
3101 static struct type *
3102 i386_ymm_type (struct gdbarch *gdbarch)
3104 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3106 if (!tdep->i386_ymm_type)
3108 const struct builtin_type *bt = builtin_type (gdbarch);
3110 /* The type we're building is this: */
3112 union __gdb_builtin_type_vec256i
3114 int128_t uint128[2];
3115 int64_t v2_int64[4];
3116 int32_t v4_int32[8];
3117 int16_t v8_int16[16];
3118 int8_t v16_int8[32];
3119 double v2_double[4];
3126 t = arch_composite_type (gdbarch,
3127 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
3128 append_composite_type_field (t, "v8_float",
3129 init_vector_type (bt->builtin_float, 8));
3130 append_composite_type_field (t, "v4_double",
3131 init_vector_type (bt->builtin_double, 4));
3132 append_composite_type_field (t, "v32_int8",
3133 init_vector_type (bt->builtin_int8, 32));
3134 append_composite_type_field (t, "v16_int16",
3135 init_vector_type (bt->builtin_int16, 16));
3136 append_composite_type_field (t, "v8_int32",
3137 init_vector_type (bt->builtin_int32, 8));
3138 append_composite_type_field (t, "v4_int64",
3139 init_vector_type (bt->builtin_int64, 4));
3140 append_composite_type_field (t, "v2_int128",
3141 init_vector_type (bt->builtin_int128, 2));
3143 TYPE_VECTOR (t) = 1;
3144 TYPE_NAME (t) = "builtin_type_vec256i";
3145 tdep->i386_ymm_type = t;
3148 return tdep->i386_ymm_type;
3151 /* Construct vector type for MMX registers. */
3152 static struct type *
3153 i386_mmx_type (struct gdbarch *gdbarch)
3155 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3157 if (!tdep->i386_mmx_type)
3159 const struct builtin_type *bt = builtin_type (gdbarch);
3161 /* The type we're building is this: */
3163 union __gdb_builtin_type_vec64i
3166 int32_t v2_int32[2];
3167 int16_t v4_int16[4];
3174 t = arch_composite_type (gdbarch,
3175 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
3177 append_composite_type_field (t, "uint64", bt->builtin_int64);
3178 append_composite_type_field (t, "v2_int32",
3179 init_vector_type (bt->builtin_int32, 2));
3180 append_composite_type_field (t, "v4_int16",
3181 init_vector_type (bt->builtin_int16, 4));
3182 append_composite_type_field (t, "v8_int8",
3183 init_vector_type (bt->builtin_int8, 8));
3185 TYPE_VECTOR (t) = 1;
3186 TYPE_NAME (t) = "builtin_type_vec64i";
3187 tdep->i386_mmx_type = t;
3190 return tdep->i386_mmx_type;
3193 /* Return the GDB type object for the "standard" data type of data in
3197 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3199 if (i386_bnd_regnum_p (gdbarch, regnum))
3200 return i386_bnd_type (gdbarch);
3201 if (i386_mmx_regnum_p (gdbarch, regnum))
3202 return i386_mmx_type (gdbarch);
3203 else if (i386_ymm_regnum_p (gdbarch, regnum))
3204 return i386_ymm_type (gdbarch);
3205 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3206 return i386_ymm_type (gdbarch);
3207 else if (i386_zmm_regnum_p (gdbarch, regnum))
3208 return i386_zmm_type (gdbarch);
3211 const struct builtin_type *bt = builtin_type (gdbarch);
3212 if (i386_byte_regnum_p (gdbarch, regnum))
3213 return bt->builtin_int8;
3214 else if (i386_word_regnum_p (gdbarch, regnum))
3215 return bt->builtin_int16;
3216 else if (i386_dword_regnum_p (gdbarch, regnum))
3217 return bt->builtin_int32;
3218 else if (i386_k_regnum_p (gdbarch, regnum))
3219 return bt->builtin_int64;
3222 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3225 /* Map a cooked register onto a raw register or memory. For the i386,
3226 the MMX registers need to be mapped onto floating point registers. */
3229 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
3231 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
3236 mmxreg = regnum - tdep->mm0_regnum;
3237 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
3238 tos = (fstat >> 11) & 0x7;
3239 fpreg = (mmxreg + tos) % 8;
3241 return (I387_ST0_REGNUM (tdep) + fpreg);
3244 /* A helper function for us by i386_pseudo_register_read_value and
3245 amd64_pseudo_register_read_value. It does all the work but reads
3246 the data into an already-allocated value. */
3249 i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
3250 struct regcache *regcache,
3252 struct value *result_value)
3254 gdb_byte raw_buf[MAX_REGISTER_SIZE];
3255 enum register_status status;
3256 gdb_byte *buf = value_contents_raw (result_value);
3258 if (i386_mmx_regnum_p (gdbarch, regnum))
3260 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3262 /* Extract (always little endian). */
3263 status = regcache_raw_read (regcache, fpnum, raw_buf);
3264 if (status != REG_VALID)
3265 mark_value_bytes_unavailable (result_value, 0,
3266 TYPE_LENGTH (value_type (result_value)));
3268 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
3272 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3273 if (i386_bnd_regnum_p (gdbarch, regnum))
3275 regnum -= tdep->bnd0_regnum;
3277 /* Extract (always little endian). Read lower 128bits. */
3278 status = regcache_raw_read (regcache,
3279 I387_BND0R_REGNUM (tdep) + regnum,
3281 if (status != REG_VALID)
3282 mark_value_bytes_unavailable (result_value, 0, 16);
3285 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3286 LONGEST upper, lower;
3287 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3289 lower = extract_unsigned_integer (raw_buf, 8, byte_order);
3290 upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order);
3293 memcpy (buf, &lower, size);
3294 memcpy (buf + size, &upper, size);
3297 else if (i386_k_regnum_p (gdbarch, regnum))
3299 regnum -= tdep->k0_regnum;
3301 /* Extract (always little endian). */
3302 status = regcache_raw_read (regcache,
3303 tdep->k0_regnum + regnum,
3305 if (status != REG_VALID)
3306 mark_value_bytes_unavailable (result_value, 0, 8);
3308 memcpy (buf, raw_buf, 8);
3310 else if (i386_zmm_regnum_p (gdbarch, regnum))
3312 regnum -= tdep->zmm0_regnum;
3314 if (regnum < num_lower_zmm_regs)
3316 /* Extract (always little endian). Read lower 128bits. */
3317 status = regcache_raw_read (regcache,
3318 I387_XMM0_REGNUM (tdep) + regnum,
3320 if (status != REG_VALID)
3321 mark_value_bytes_unavailable (result_value, 0, 16);
3323 memcpy (buf, raw_buf, 16);
3325 /* Extract (always little endian). Read upper 128bits. */
3326 status = regcache_raw_read (regcache,
3327 tdep->ymm0h_regnum + regnum,
3329 if (status != REG_VALID)
3330 mark_value_bytes_unavailable (result_value, 16, 16);
3332 memcpy (buf + 16, raw_buf, 16);
3336 /* Extract (always little endian). Read lower 128bits. */
3337 status = regcache_raw_read (regcache,
3338 I387_XMM16_REGNUM (tdep) + regnum
3339 - num_lower_zmm_regs,
3341 if (status != REG_VALID)
3342 mark_value_bytes_unavailable (result_value, 0, 16);
3344 memcpy (buf, raw_buf, 16);
3346 /* Extract (always little endian). Read upper 128bits. */
3347 status = regcache_raw_read (regcache,
3348 I387_YMM16H_REGNUM (tdep) + regnum
3349 - num_lower_zmm_regs,
3351 if (status != REG_VALID)
3352 mark_value_bytes_unavailable (result_value, 16, 16);
3354 memcpy (buf + 16, raw_buf, 16);
3357 /* Read upper 256bits. */
3358 status = regcache_raw_read (regcache,
3359 tdep->zmm0h_regnum + regnum,
3361 if (status != REG_VALID)
3362 mark_value_bytes_unavailable (result_value, 32, 32);
3364 memcpy (buf + 32, raw_buf, 32);
3366 else if (i386_ymm_regnum_p (gdbarch, regnum))
3368 regnum -= tdep->ymm0_regnum;
3370 /* Extract (always little endian). Read lower 128bits. */
3371 status = regcache_raw_read (regcache,
3372 I387_XMM0_REGNUM (tdep) + regnum,
3374 if (status != REG_VALID)
3375 mark_value_bytes_unavailable (result_value, 0, 16);
3377 memcpy (buf, raw_buf, 16);
3378 /* Read upper 128bits. */
3379 status = regcache_raw_read (regcache,
3380 tdep->ymm0h_regnum + regnum,
3382 if (status != REG_VALID)
3383 mark_value_bytes_unavailable (result_value, 16, 32);
3385 memcpy (buf + 16, raw_buf, 16);
3387 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3389 regnum -= tdep->ymm16_regnum;
3390 /* Extract (always little endian). Read lower 128bits. */
3391 status = regcache_raw_read (regcache,
3392 I387_XMM16_REGNUM (tdep) + regnum,
3394 if (status != REG_VALID)
3395 mark_value_bytes_unavailable (result_value, 0, 16);
3397 memcpy (buf, raw_buf, 16);
3398 /* Read upper 128bits. */
3399 status = regcache_raw_read (regcache,
3400 tdep->ymm16h_regnum + regnum,
3402 if (status != REG_VALID)
3403 mark_value_bytes_unavailable (result_value, 16, 16);
3405 memcpy (buf + 16, raw_buf, 16);
3407 else if (i386_word_regnum_p (gdbarch, regnum))
3409 int gpnum = regnum - tdep->ax_regnum;
3411 /* Extract (always little endian). */
3412 status = regcache_raw_read (regcache, gpnum, raw_buf);
3413 if (status != REG_VALID)
3414 mark_value_bytes_unavailable (result_value, 0,
3415 TYPE_LENGTH (value_type (result_value)));
3417 memcpy (buf, raw_buf, 2);
3419 else if (i386_byte_regnum_p (gdbarch, regnum))
3421 int gpnum = regnum - tdep->al_regnum;
3423 /* Extract (always little endian). We read both lower and
3425 status = regcache_raw_read (regcache, gpnum % 4, raw_buf);
3426 if (status != REG_VALID)
3427 mark_value_bytes_unavailable (result_value, 0,
3428 TYPE_LENGTH (value_type (result_value)));
3429 else if (gpnum >= 4)
3430 memcpy (buf, raw_buf + 1, 1);
3432 memcpy (buf, raw_buf, 1);
3435 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3439 static struct value *
3440 i386_pseudo_register_read_value (struct gdbarch *gdbarch,
3441 struct regcache *regcache,
3444 struct value *result;
3446 result = allocate_value (register_type (gdbarch, regnum));
3447 VALUE_LVAL (result) = lval_register;
3448 VALUE_REGNUM (result) = regnum;
3450 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result);
3456 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3457 int regnum, const gdb_byte *buf)
3459 gdb_byte raw_buf[MAX_REGISTER_SIZE];
3461 if (i386_mmx_regnum_p (gdbarch, regnum))
3463 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3466 regcache_raw_read (regcache, fpnum, raw_buf);
3467 /* ... Modify ... (always little endian). */
3468 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
3470 regcache_raw_write (regcache, fpnum, raw_buf);
3474 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3476 if (i386_bnd_regnum_p (gdbarch, regnum))
3478 ULONGEST upper, lower;
3479 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3480 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3482 /* New values from input value. */
3483 regnum -= tdep->bnd0_regnum;
3484 lower = extract_unsigned_integer (buf, size, byte_order);
3485 upper = extract_unsigned_integer (buf + size, size, byte_order);
3487 /* Fetching register buffer. */
3488 regcache_raw_read (regcache,
3489 I387_BND0R_REGNUM (tdep) + regnum,
3494 /* Set register bits. */
3495 memcpy (raw_buf, &lower, 8);
3496 memcpy (raw_buf + 8, &upper, 8);
3499 regcache_raw_write (regcache,
3500 I387_BND0R_REGNUM (tdep) + regnum,
3503 else if (i386_k_regnum_p (gdbarch, regnum))
3505 regnum -= tdep->k0_regnum;
3507 regcache_raw_write (regcache,
3508 tdep->k0_regnum + regnum,
3511 else if (i386_zmm_regnum_p (gdbarch, regnum))
3513 regnum -= tdep->zmm0_regnum;
3515 if (regnum < num_lower_zmm_regs)
3517 /* Write lower 128bits. */
3518 regcache_raw_write (regcache,
3519 I387_XMM0_REGNUM (tdep) + regnum,
3521 /* Write upper 128bits. */
3522 regcache_raw_write (regcache,
3523 I387_YMM0_REGNUM (tdep) + regnum,
3528 /* Write lower 128bits. */
3529 regcache_raw_write (regcache,
3530 I387_XMM16_REGNUM (tdep) + regnum
3531 - num_lower_zmm_regs,
3533 /* Write upper 128bits. */
3534 regcache_raw_write (regcache,
3535 I387_YMM16H_REGNUM (tdep) + regnum
3536 - num_lower_zmm_regs,
3539 /* Write upper 256bits. */
3540 regcache_raw_write (regcache,
3541 tdep->zmm0h_regnum + regnum,
3544 else if (i386_ymm_regnum_p (gdbarch, regnum))
3546 regnum -= tdep->ymm0_regnum;
3548 /* ... Write lower 128bits. */
3549 regcache_raw_write (regcache,
3550 I387_XMM0_REGNUM (tdep) + regnum,
3552 /* ... Write upper 128bits. */
3553 regcache_raw_write (regcache,
3554 tdep->ymm0h_regnum + regnum,
3557 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3559 regnum -= tdep->ymm16_regnum;
3561 /* ... Write lower 128bits. */
3562 regcache_raw_write (regcache,
3563 I387_XMM16_REGNUM (tdep) + regnum,
3565 /* ... Write upper 128bits. */
3566 regcache_raw_write (regcache,
3567 tdep->ymm16h_regnum + regnum,
3570 else if (i386_word_regnum_p (gdbarch, regnum))
3572 int gpnum = regnum - tdep->ax_regnum;
3575 regcache_raw_read (regcache, gpnum, raw_buf);
3576 /* ... Modify ... (always little endian). */
3577 memcpy (raw_buf, buf, 2);
3579 regcache_raw_write (regcache, gpnum, raw_buf);
3581 else if (i386_byte_regnum_p (gdbarch, regnum))
3583 int gpnum = regnum - tdep->al_regnum;
3585 /* Read ... We read both lower and upper registers. */
3586 regcache_raw_read (regcache, gpnum % 4, raw_buf);
3587 /* ... Modify ... (always little endian). */
3589 memcpy (raw_buf + 1, buf, 1);
3591 memcpy (raw_buf, buf, 1);
3593 regcache_raw_write (regcache, gpnum % 4, raw_buf);
3596 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3600 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
3603 i386_ax_pseudo_register_collect (struct gdbarch *gdbarch,
3604 struct agent_expr *ax, int regnum)
3606 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3608 if (i386_mmx_regnum_p (gdbarch, regnum))
3610 /* MMX to FPU register mapping depends on current TOS. Let's just
3611 not care and collect everything... */
3614 ax_reg_mask (ax, I387_FSTAT_REGNUM (tdep));
3615 for (i = 0; i < 8; i++)
3616 ax_reg_mask (ax, I387_ST0_REGNUM (tdep) + i);
3619 else if (i386_bnd_regnum_p (gdbarch, regnum))
3621 regnum -= tdep->bnd0_regnum;
3622 ax_reg_mask (ax, I387_BND0R_REGNUM (tdep) + regnum);
3625 else if (i386_k_regnum_p (gdbarch, regnum))
3627 regnum -= tdep->k0_regnum;
3628 ax_reg_mask (ax, tdep->k0_regnum + regnum);
3631 else if (i386_zmm_regnum_p (gdbarch, regnum))
3633 regnum -= tdep->zmm0_regnum;
3634 if (regnum < num_lower_zmm_regs)
3636 ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum);
3637 ax_reg_mask (ax, tdep->ymm0h_regnum + regnum);
3641 ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum
3642 - num_lower_zmm_regs);
3643 ax_reg_mask (ax, I387_YMM16H_REGNUM (tdep) + regnum
3644 - num_lower_zmm_regs);
3646 ax_reg_mask (ax, tdep->zmm0h_regnum + regnum);
3649 else if (i386_ymm_regnum_p (gdbarch, regnum))
3651 regnum -= tdep->ymm0_regnum;
3652 ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum);
3653 ax_reg_mask (ax, tdep->ymm0h_regnum + regnum);
3656 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3658 regnum -= tdep->ymm16_regnum;
3659 ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum);
3660 ax_reg_mask (ax, tdep->ymm16h_regnum + regnum);
3663 else if (i386_word_regnum_p (gdbarch, regnum))
3665 int gpnum = regnum - tdep->ax_regnum;
3667 ax_reg_mask (ax, gpnum);
3670 else if (i386_byte_regnum_p (gdbarch, regnum))
3672 int gpnum = regnum - tdep->al_regnum;
3674 ax_reg_mask (ax, gpnum % 4);
3678 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3683 /* Return the register number of the register allocated by GCC after
3684 REGNUM, or -1 if there is no such register. */
3687 i386_next_regnum (int regnum)
3689 /* GCC allocates the registers in the order:
3691 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3693 Since storing a variable in %esp doesn't make any sense we return
3694 -1 for %ebp and for %esp itself. */
3695 static int next_regnum[] =
3697 I386_EDX_REGNUM, /* Slot for %eax. */
3698 I386_EBX_REGNUM, /* Slot for %ecx. */
3699 I386_ECX_REGNUM, /* Slot for %edx. */
3700 I386_ESI_REGNUM, /* Slot for %ebx. */
3701 -1, -1, /* Slots for %esp and %ebp. */
3702 I386_EDI_REGNUM, /* Slot for %esi. */
3703 I386_EBP_REGNUM /* Slot for %edi. */
3706 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
3707 return next_regnum[regnum];
3712 /* Return nonzero if a value of type TYPE stored in register REGNUM
3713 needs any special handling. */
3716 i386_convert_register_p (struct gdbarch *gdbarch,
3717 int regnum, struct type *type)
3719 int len = TYPE_LENGTH (type);
3721 /* Values may be spread across multiple registers. Most debugging
3722 formats aren't expressive enough to specify the locations, so
3723 some heuristics is involved. Right now we only handle types that
3724 have a length that is a multiple of the word size, since GCC
3725 doesn't seem to put any other types into registers. */
3726 if (len > 4 && len % 4 == 0)
3728 int last_regnum = regnum;
3732 last_regnum = i386_next_regnum (last_regnum);
3736 if (last_regnum != -1)
3740 return i387_convert_register_p (gdbarch, regnum, type);
3743 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3744 return its contents in TO. */
3747 i386_register_to_value (struct frame_info *frame, int regnum,
3748 struct type *type, gdb_byte *to,
3749 int *optimizedp, int *unavailablep)
3751 struct gdbarch *gdbarch = get_frame_arch (frame);
3752 int len = TYPE_LENGTH (type);
3754 if (i386_fp_regnum_p (gdbarch, regnum))
3755 return i387_register_to_value (frame, regnum, type, to,
3756 optimizedp, unavailablep);
3758 /* Read a value spread across multiple registers. */
3760 gdb_assert (len > 4 && len % 4 == 0);
3764 gdb_assert (regnum != -1);
3765 gdb_assert (register_size (gdbarch, regnum) == 4);
3767 if (!get_frame_register_bytes (frame, regnum, 0,
3768 register_size (gdbarch, regnum),
3769 to, optimizedp, unavailablep))
3772 regnum = i386_next_regnum (regnum);
3777 *optimizedp = *unavailablep = 0;
3781 /* Write the contents FROM of a value of type TYPE into register
3782 REGNUM in frame FRAME. */
3785 i386_value_to_register (struct frame_info *frame, int regnum,
3786 struct type *type, const gdb_byte *from)
3788 int len = TYPE_LENGTH (type);
3790 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
3792 i387_value_to_register (frame, regnum, type, from);
3796 /* Write a value spread across multiple registers. */
3798 gdb_assert (len > 4 && len % 4 == 0);
3802 gdb_assert (regnum != -1);
3803 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
3805 put_frame_register (frame, regnum, from);
3806 regnum = i386_next_regnum (regnum);
3812 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3813 in the general-purpose register set REGSET to register cache
3814 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3817 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
3818 int regnum, const void *gregs, size_t len)
3820 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3821 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3822 const gdb_byte *regs = (const gdb_byte *) gregs;
3825 gdb_assert (len >= tdep->sizeof_gregset);
3827 for (i = 0; i < tdep->gregset_num_regs; i++)
3829 if ((regnum == i || regnum == -1)
3830 && tdep->gregset_reg_offset[i] != -1)
3831 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
3835 /* Collect register REGNUM from the register cache REGCACHE and store
3836 it in the buffer specified by GREGS and LEN as described by the
3837 general-purpose register set REGSET. If REGNUM is -1, do this for
3838 all registers in REGSET. */
3841 i386_collect_gregset (const struct regset *regset,
3842 const struct regcache *regcache,
3843 int regnum, void *gregs, size_t len)
3845 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3846 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3847 gdb_byte *regs = (gdb_byte *) gregs;
3850 gdb_assert (len >= tdep->sizeof_gregset);
3852 for (i = 0; i < tdep->gregset_num_regs; i++)
3854 if ((regnum == i || regnum == -1)
3855 && tdep->gregset_reg_offset[i] != -1)
3856 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
3860 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3861 in the floating-point register set REGSET to register cache
3862 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3865 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
3866 int regnum, const void *fpregs, size_t len)
3868 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3869 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3871 if (len == I387_SIZEOF_FXSAVE)
3873 i387_supply_fxsave (regcache, regnum, fpregs);
3877 gdb_assert (len >= tdep->sizeof_fpregset);
3878 i387_supply_fsave (regcache, regnum, fpregs);
3881 /* Collect register REGNUM from the register cache REGCACHE and store
3882 it in the buffer specified by FPREGS and LEN as described by the
3883 floating-point register set REGSET. If REGNUM is -1, do this for
3884 all registers in REGSET. */
3887 i386_collect_fpregset (const struct regset *regset,
3888 const struct regcache *regcache,
3889 int regnum, void *fpregs, size_t len)
3891 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3892 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3894 if (len == I387_SIZEOF_FXSAVE)
3896 i387_collect_fxsave (regcache, regnum, fpregs);
3900 gdb_assert (len >= tdep->sizeof_fpregset);
3901 i387_collect_fsave (regcache, regnum, fpregs);
3904 /* Register set definitions. */
3906 const struct regset i386_gregset =
3908 NULL, i386_supply_gregset, i386_collect_gregset
3911 const struct regset i386_fpregset =
3913 NULL, i386_supply_fpregset, i386_collect_fpregset
3916 /* Default iterator over core file register note sections. */
3919 i386_iterate_over_regset_sections (struct gdbarch *gdbarch,
3920 iterate_over_regset_sections_cb *cb,
3922 const struct regcache *regcache)
3924 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3926 cb (".reg", tdep->sizeof_gregset, &i386_gregset, NULL, cb_data);
3927 if (tdep->sizeof_fpregset)
3928 cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
3932 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3935 i386_pe_skip_trampoline_code (struct frame_info *frame,
3936 CORE_ADDR pc, char *name)
3938 struct gdbarch *gdbarch = get_frame_arch (frame);
3939 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3942 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
3944 unsigned long indirect =
3945 read_memory_unsigned_integer (pc + 2, 4, byte_order);
3946 struct minimal_symbol *indsym =
3947 indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0;
3948 const char *symname = indsym ? MSYMBOL_LINKAGE_NAME (indsym) : 0;
3952 if (startswith (symname, "__imp_")
3953 || startswith (symname, "_imp_"))
3955 read_memory_unsigned_integer (indirect, 4, byte_order);
3958 return 0; /* Not a trampoline. */
3962 /* Return whether the THIS_FRAME corresponds to a sigtramp
3966 i386_sigtramp_p (struct frame_info *this_frame)
3968 CORE_ADDR pc = get_frame_pc (this_frame);
3971 find_pc_partial_function (pc, &name, NULL, NULL);
3972 return (name && strcmp ("_sigtramp", name) == 0);
3976 /* We have two flavours of disassembly. The machinery on this page
3977 deals with switching between those. */
3980 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
3982 gdb_assert (disassembly_flavor == att_flavor
3983 || disassembly_flavor == intel_flavor);
3985 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3986 constified, cast to prevent a compiler warning. */
3987 info->disassembler_options = (char *) disassembly_flavor;
3989 return print_insn_i386 (pc, info);
3993 /* There are a few i386 architecture variants that differ only
3994 slightly from the generic i386 target. For now, we don't give them
3995 their own source file, but include them here. As a consequence,
3996 they'll always be included. */
3998 /* System V Release 4 (SVR4). */
4000 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
4004 i386_svr4_sigtramp_p (struct frame_info *this_frame)
4006 CORE_ADDR pc = get_frame_pc (this_frame);
4009 /* The origin of these symbols is currently unknown. */
4010 find_pc_partial_function (pc, &name, NULL, NULL);
4011 return (name && (strcmp ("_sigreturn", name) == 0
4012 || strcmp ("sigvechandler", name) == 0));
4015 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
4016 address of the associated sigcontext (ucontext) structure. */
4019 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
4021 struct gdbarch *gdbarch = get_frame_arch (this_frame);
4022 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4026 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
4027 sp = extract_unsigned_integer (buf, 4, byte_order);
4029 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
4034 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
4038 i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s)
4040 return (*s == '$' /* Literal number. */
4041 || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */
4042 || (*s == '(' && s[1] == '%') /* Register indirection. */
4043 || (*s == '%' && isalpha (s[1]))); /* Register access. */
4046 /* Helper function for i386_stap_parse_special_token.
4048 This function parses operands of the form `-8+3+1(%rbp)', which
4049 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
4051 Return 1 if the operand was parsed successfully, zero
4055 i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch,
4056 struct stap_parse_info *p)
4058 const char *s = p->arg;
4060 if (isdigit (*s) || *s == '-' || *s == '+')
4064 long displacements[3];
4080 if (!isdigit ((unsigned char) *s))
4083 displacements[0] = strtol (s, &endp, 10);
4086 if (*s != '+' && *s != '-')
4088 /* We are not dealing with a triplet. */
4101 if (!isdigit ((unsigned char) *s))
4104 displacements[1] = strtol (s, &endp, 10);
4107 if (*s != '+' && *s != '-')
4109 /* We are not dealing with a triplet. */
4122 if (!isdigit ((unsigned char) *s))
4125 displacements[2] = strtol (s, &endp, 10);
4128 if (*s != '(' || s[1] != '%')
4134 while (isalnum (*s))
4140 len = s - start - 1;
4141 regname = (char *) alloca (len + 1);
4143 strncpy (regname, start, len);
4144 regname[len] = '\0';
4146 if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1)
4147 error (_("Invalid register name `%s' on expression `%s'."),
4148 regname, p->saved_arg);
4150 for (i = 0; i < 3; i++)
4152 write_exp_elt_opcode (&p->pstate, OP_LONG);
4154 (&p->pstate, builtin_type (gdbarch)->builtin_long);
4155 write_exp_elt_longcst (&p->pstate, displacements[i]);
4156 write_exp_elt_opcode (&p->pstate, OP_LONG);
4158 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4161 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4164 write_exp_string (&p->pstate, str);
4165 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4167 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4168 write_exp_elt_type (&p->pstate,
4169 builtin_type (gdbarch)->builtin_data_ptr);
4170 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4172 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4173 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4174 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4176 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4177 write_exp_elt_type (&p->pstate,
4178 lookup_pointer_type (p->arg_type));
4179 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4181 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4191 /* Helper function for i386_stap_parse_special_token.
4193 This function parses operands of the form `register base +
4194 (register index * size) + offset', as represented in
4195 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4197 Return 1 if the operand was parsed successfully, zero
4201 i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch,
4202 struct stap_parse_info *p)
4204 const char *s = p->arg;
4206 if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+')
4208 int offset_minus = 0;
4217 struct stoken base_token, index_token;
4227 if (offset_minus && !isdigit (*s))
4234 offset = strtol (s, &endp, 10);
4238 if (*s != '(' || s[1] != '%')
4244 while (isalnum (*s))
4247 if (*s != ',' || s[1] != '%')
4250 len_base = s - start;
4251 base = (char *) alloca (len_base + 1);
4252 strncpy (base, start, len_base);
4253 base[len_base] = '\0';
4255 if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1)
4256 error (_("Invalid register name `%s' on expression `%s'."),
4257 base, p->saved_arg);
4262 while (isalnum (*s))
4265 len_index = s - start;
4266 index = (char *) alloca (len_index + 1);
4267 strncpy (index, start, len_index);
4268 index[len_index] = '\0';
4270 if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1)
4271 error (_("Invalid register name `%s' on expression `%s'."),
4272 index, p->saved_arg);
4274 if (*s != ',' && *s != ')')
4290 size = strtol (s, &endp, 10);
4301 write_exp_elt_opcode (&p->pstate, OP_LONG);
4302 write_exp_elt_type (&p->pstate,
4303 builtin_type (gdbarch)->builtin_long);
4304 write_exp_elt_longcst (&p->pstate, offset);
4305 write_exp_elt_opcode (&p->pstate, OP_LONG);
4307 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4310 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4311 base_token.ptr = base;
4312 base_token.length = len_base;
4313 write_exp_string (&p->pstate, base_token);
4314 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4317 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4319 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4320 index_token.ptr = index;
4321 index_token.length = len_index;
4322 write_exp_string (&p->pstate, index_token);
4323 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4327 write_exp_elt_opcode (&p->pstate, OP_LONG);
4328 write_exp_elt_type (&p->pstate,
4329 builtin_type (gdbarch)->builtin_long);
4330 write_exp_elt_longcst (&p->pstate, size);
4331 write_exp_elt_opcode (&p->pstate, OP_LONG);
4333 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4334 write_exp_elt_opcode (&p->pstate, BINOP_MUL);
4337 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4339 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4340 write_exp_elt_type (&p->pstate,
4341 lookup_pointer_type (p->arg_type));
4342 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4344 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4354 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4358 i386_stap_parse_special_token (struct gdbarch *gdbarch,
4359 struct stap_parse_info *p)
4361 /* In order to parse special tokens, we use a state-machine that go
4362 through every known token and try to get a match. */
4366 THREE_ARG_DISPLACEMENT,
4371 current_state = TRIPLET;
4373 /* The special tokens to be parsed here are:
4375 - `register base + (register index * size) + offset', as represented
4376 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4378 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4379 `*(-8 + 3 - 1 + (void *) $eax)'. */
4381 while (current_state != DONE)
4383 switch (current_state)
4386 if (i386_stap_parse_special_token_triplet (gdbarch, p))
4390 case THREE_ARG_DISPLACEMENT:
4391 if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p))
4396 /* Advancing to the next state. */
4405 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always
4406 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */
4409 i386_gnu_triplet_regexp (struct gdbarch *gdbarch)
4411 return "(x86_64|i.86)";
4419 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4421 static const char *const stap_integer_prefixes[] = { "$", NULL };
4422 static const char *const stap_register_prefixes[] = { "%", NULL };
4423 static const char *const stap_register_indirection_prefixes[] = { "(",
4425 static const char *const stap_register_indirection_suffixes[] = { ")",
4428 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4429 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4431 /* Registering SystemTap handlers. */
4432 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
4433 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
4434 set_gdbarch_stap_register_indirection_prefixes (gdbarch,
4435 stap_register_indirection_prefixes);
4436 set_gdbarch_stap_register_indirection_suffixes (gdbarch,
4437 stap_register_indirection_suffixes);
4438 set_gdbarch_stap_is_single_operand (gdbarch,
4439 i386_stap_is_single_operand);
4440 set_gdbarch_stap_parse_special_token (gdbarch,
4441 i386_stap_parse_special_token);
4443 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
4446 /* System V Release 4 (SVR4). */
4449 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4451 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4453 /* System V Release 4 uses ELF. */
4454 i386_elf_init_abi (info, gdbarch);
4456 /* System V Release 4 has shared libraries. */
4457 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
4459 tdep->sigtramp_p = i386_svr4_sigtramp_p;
4460 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
4461 tdep->sc_pc_offset = 36 + 14 * 4;
4462 tdep->sc_sp_offset = 36 + 17 * 4;
4464 tdep->jb_pc_offset = 20;
4470 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4472 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4474 /* DJGPP doesn't have any special frames for signal handlers. */
4475 tdep->sigtramp_p = NULL;
4477 tdep->jb_pc_offset = 36;
4479 /* DJGPP does not support the SSE registers. */
4480 if (! tdesc_has_registers (info.target_desc))
4481 tdep->tdesc = tdesc_i386_mmx;
4483 /* Native compiler is GCC, which uses the SVR4 register numbering
4484 even in COFF and STABS. See the comment in i386_gdbarch_init,
4485 before the calls to set_gdbarch_stab_reg_to_regnum and
4486 set_gdbarch_sdb_reg_to_regnum. */
4487 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4488 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4490 set_gdbarch_has_dos_based_file_system (gdbarch, 1);
4492 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
4496 /* i386 register groups. In addition to the normal groups, add "mmx"
4499 static struct reggroup *i386_sse_reggroup;
4500 static struct reggroup *i386_mmx_reggroup;
4503 i386_init_reggroups (void)
4505 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
4506 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
4510 i386_add_reggroups (struct gdbarch *gdbarch)
4512 reggroup_add (gdbarch, i386_sse_reggroup);
4513 reggroup_add (gdbarch, i386_mmx_reggroup);
4514 reggroup_add (gdbarch, general_reggroup);
4515 reggroup_add (gdbarch, float_reggroup);
4516 reggroup_add (gdbarch, all_reggroup);
4517 reggroup_add (gdbarch, save_reggroup);
4518 reggroup_add (gdbarch, restore_reggroup);
4519 reggroup_add (gdbarch, vector_reggroup);
4520 reggroup_add (gdbarch, system_reggroup);
4524 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
4525 struct reggroup *group)
4527 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4528 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
4529 ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p,
4530 bndr_regnum_p, bnd_regnum_p, k_regnum_p, zmm_regnum_p, zmmh_regnum_p,
4531 zmm_avx512_regnum_p, mpx_ctrl_regnum_p, xmm_avx512_regnum_p,
4532 avx512_p, avx_p, sse_p;
4534 /* Don't include pseudo registers, except for MMX, in any register
4536 if (i386_byte_regnum_p (gdbarch, regnum))
4539 if (i386_word_regnum_p (gdbarch, regnum))
4542 if (i386_dword_regnum_p (gdbarch, regnum))
4545 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
4546 if (group == i386_mmx_reggroup)
4547 return mmx_regnum_p;
4549 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
4550 xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum);
4551 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
4552 if (group == i386_sse_reggroup)
4553 return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p;
4555 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
4556 ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum);
4557 zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum);
4559 avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK)
4560 == X86_XSTATE_AVX_AVX512_MASK);
4561 avx_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK)
4562 == X86_XSTATE_AVX_MASK) && !avx512_p;
4563 sse_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK)
4564 == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p;
4566 if (group == vector_reggroup)
4567 return (mmx_regnum_p
4568 || (zmm_regnum_p && avx512_p)
4569 || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p)
4570 || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p)
4573 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
4574 || i386_fpc_regnum_p (gdbarch, regnum));
4575 if (group == float_reggroup)
4578 /* For "info reg all", don't include upper YMM registers nor XMM
4579 registers when AVX is supported. */
4580 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
4581 ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum);
4582 zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum);
4583 if (group == all_reggroup
4584 && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p)
4585 || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p)
4587 || ymmh_avx512_regnum_p
4591 bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum);
4592 if (group == all_reggroup
4593 && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4594 return bnd_regnum_p;
4596 bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum);
4597 if (group == all_reggroup
4598 && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4601 mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum);
4602 if (group == all_reggroup
4603 && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4604 return mpx_ctrl_regnum_p;
4606 if (group == general_reggroup)
4607 return (!fp_regnum_p
4611 && !xmm_avx512_regnum_p
4614 && !ymm_avx512_regnum_p
4615 && !ymmh_avx512_regnum_p
4618 && !mpx_ctrl_regnum_p
4622 return default_register_reggroup_p (gdbarch, regnum, group);
4626 /* Get the ARGIth function argument for the current function. */
4629 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
4632 struct gdbarch *gdbarch = get_frame_arch (frame);
4633 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4634 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
4635 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
4638 #define PREFIX_REPZ 0x01
4639 #define PREFIX_REPNZ 0x02
4640 #define PREFIX_LOCK 0x04
4641 #define PREFIX_DATA 0x08
4642 #define PREFIX_ADDR 0x10
4654 /* i386 arith/logic operations */
4667 struct i386_record_s
4669 struct gdbarch *gdbarch;
4670 struct regcache *regcache;
4671 CORE_ADDR orig_addr;
4677 uint8_t mod, reg, rm;
4686 /* Parse the "modrm" part of the memory address irp->addr points at.
4687 Returns -1 if something goes wrong, 0 otherwise. */
4690 i386_record_modrm (struct i386_record_s *irp)
4692 struct gdbarch *gdbarch = irp->gdbarch;
4694 if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1))
4698 irp->mod = (irp->modrm >> 6) & 3;
4699 irp->reg = (irp->modrm >> 3) & 7;
4700 irp->rm = irp->modrm & 7;
4705 /* Extract the memory address that the current instruction writes to,
4706 and return it in *ADDR. Return -1 if something goes wrong. */
4709 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
4711 struct gdbarch *gdbarch = irp->gdbarch;
4712 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4717 if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM])
4724 uint8_t base = irp->rm;
4729 if (record_read_memory (gdbarch, irp->addr, &byte, 1))
4732 scale = (byte >> 6) & 3;
4733 index = ((byte >> 3) & 7) | irp->rex_x;
4741 if ((base & 7) == 5)
4744 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4747 *addr = extract_signed_integer (buf, 4, byte_order);
4748 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
4749 *addr += irp->addr + irp->rip_offset;
4753 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4756 *addr = (int8_t) buf[0];
4759 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4761 *addr = extract_signed_integer (buf, 4, byte_order);
4769 if (base == 4 && irp->popl_esp_hack)
4770 *addr += irp->popl_esp_hack;
4771 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
4774 if (irp->aflag == 2)
4779 *addr = (uint32_t) (offset64 + *addr);
4781 if (havesib && (index != 4 || scale != 0))
4783 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
4785 if (irp->aflag == 2)
4786 *addr += offset64 << scale;
4788 *addr = (uint32_t) (*addr + (offset64 << scale));
4793 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4794 address from 32-bit to 64-bit. */
4795 *addr = (uint32_t) *addr;
4806 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4809 *addr = extract_signed_integer (buf, 2, byte_order);
4815 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4818 *addr = (int8_t) buf[0];
4821 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4824 *addr = extract_signed_integer (buf, 2, byte_order);
4831 regcache_raw_read_unsigned (irp->regcache,
4832 irp->regmap[X86_RECORD_REBX_REGNUM],
4834 *addr = (uint32_t) (*addr + offset64);
4835 regcache_raw_read_unsigned (irp->regcache,
4836 irp->regmap[X86_RECORD_RESI_REGNUM],
4838 *addr = (uint32_t) (*addr + offset64);
4841 regcache_raw_read_unsigned (irp->regcache,
4842 irp->regmap[X86_RECORD_REBX_REGNUM],
4844 *addr = (uint32_t) (*addr + offset64);
4845 regcache_raw_read_unsigned (irp->regcache,
4846 irp->regmap[X86_RECORD_REDI_REGNUM],
4848 *addr = (uint32_t) (*addr + offset64);
4851 regcache_raw_read_unsigned (irp->regcache,
4852 irp->regmap[X86_RECORD_REBP_REGNUM],
4854 *addr = (uint32_t) (*addr + offset64);
4855 regcache_raw_read_unsigned (irp->regcache,
4856 irp->regmap[X86_RECORD_RESI_REGNUM],
4858 *addr = (uint32_t) (*addr + offset64);
4861 regcache_raw_read_unsigned (irp->regcache,
4862 irp->regmap[X86_RECORD_REBP_REGNUM],
4864 *addr = (uint32_t) (*addr + offset64);
4865 regcache_raw_read_unsigned (irp->regcache,
4866 irp->regmap[X86_RECORD_REDI_REGNUM],
4868 *addr = (uint32_t) (*addr + offset64);
4871 regcache_raw_read_unsigned (irp->regcache,
4872 irp->regmap[X86_RECORD_RESI_REGNUM],
4874 *addr = (uint32_t) (*addr + offset64);
4877 regcache_raw_read_unsigned (irp->regcache,
4878 irp->regmap[X86_RECORD_REDI_REGNUM],
4880 *addr = (uint32_t) (*addr + offset64);
4883 regcache_raw_read_unsigned (irp->regcache,
4884 irp->regmap[X86_RECORD_REBP_REGNUM],
4886 *addr = (uint32_t) (*addr + offset64);
4889 regcache_raw_read_unsigned (irp->regcache,
4890 irp->regmap[X86_RECORD_REBX_REGNUM],
4892 *addr = (uint32_t) (*addr + offset64);
4902 /* Record the address and contents of the memory that will be changed
4903 by the current instruction. Return -1 if something goes wrong, 0
4907 i386_record_lea_modrm (struct i386_record_s *irp)
4909 struct gdbarch *gdbarch = irp->gdbarch;
4912 if (irp->override >= 0)
4914 if (record_full_memory_query)
4917 Process record ignores the memory change of instruction at address %s\n\
4918 because it can't get the value of the segment register.\n\
4919 Do you want to stop the program?"),
4920 paddress (gdbarch, irp->orig_addr)))
4927 if (i386_record_lea_modrm_addr (irp, &addr))
4930 if (record_full_arch_list_add_mem (addr, 1 << irp->ot))
4936 /* Record the effects of a push operation. Return -1 if something
4937 goes wrong, 0 otherwise. */
4940 i386_record_push (struct i386_record_s *irp, int size)
4944 if (record_full_arch_list_add_reg (irp->regcache,
4945 irp->regmap[X86_RECORD_RESP_REGNUM]))
4947 regcache_raw_read_unsigned (irp->regcache,
4948 irp->regmap[X86_RECORD_RESP_REGNUM],
4950 if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size))
4957 /* Defines contents to record. */
4958 #define I386_SAVE_FPU_REGS 0xfffd
4959 #define I386_SAVE_FPU_ENV 0xfffe
4960 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4962 /* Record the values of the floating point registers which will be
4963 changed by the current instruction. Returns -1 if something is
4964 wrong, 0 otherwise. */
4966 static int i386_record_floats (struct gdbarch *gdbarch,
4967 struct i386_record_s *ir,
4970 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4973 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4974 happen. Currently we store st0-st7 registers, but we need not store all
4975 registers all the time, in future we use ftag register and record only
4976 those who are not marked as an empty. */
4978 if (I386_SAVE_FPU_REGS == iregnum)
4980 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
4982 if (record_full_arch_list_add_reg (ir->regcache, i))
4986 else if (I386_SAVE_FPU_ENV == iregnum)
4988 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4990 if (record_full_arch_list_add_reg (ir->regcache, i))
4994 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
4996 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4998 if (record_full_arch_list_add_reg (ir->regcache, i))
5002 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
5003 (iregnum <= I387_FOP_REGNUM (tdep)))
5005 if (record_full_arch_list_add_reg (ir->regcache,iregnum))
5010 /* Parameter error. */
5013 if(I386_SAVE_FPU_ENV != iregnum)
5015 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
5017 if (record_full_arch_list_add_reg (ir->regcache, i))
5024 /* Parse the current instruction, and record the values of the
5025 registers and memory that will be changed by the current
5026 instruction. Returns -1 if something goes wrong, 0 otherwise. */
5028 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
5029 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
5032 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
5033 CORE_ADDR input_addr)
5035 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5041 gdb_byte buf[MAX_REGISTER_SIZE];
5042 struct i386_record_s ir;
5043 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5047 memset (&ir, 0, sizeof (struct i386_record_s));
5048 ir.regcache = regcache;
5049 ir.addr = input_addr;
5050 ir.orig_addr = input_addr;
5054 ir.popl_esp_hack = 0;
5055 ir.regmap = tdep->record_regmap;
5056 ir.gdbarch = gdbarch;
5058 if (record_debug > 1)
5059 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
5061 paddress (gdbarch, ir.addr));
5066 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5069 switch (opcode8) /* Instruction prefixes */
5071 case REPE_PREFIX_OPCODE:
5072 prefixes |= PREFIX_REPZ;
5074 case REPNE_PREFIX_OPCODE:
5075 prefixes |= PREFIX_REPNZ;
5077 case LOCK_PREFIX_OPCODE:
5078 prefixes |= PREFIX_LOCK;
5080 case CS_PREFIX_OPCODE:
5081 ir.override = X86_RECORD_CS_REGNUM;
5083 case SS_PREFIX_OPCODE:
5084 ir.override = X86_RECORD_SS_REGNUM;
5086 case DS_PREFIX_OPCODE:
5087 ir.override = X86_RECORD_DS_REGNUM;
5089 case ES_PREFIX_OPCODE:
5090 ir.override = X86_RECORD_ES_REGNUM;
5092 case FS_PREFIX_OPCODE:
5093 ir.override = X86_RECORD_FS_REGNUM;
5095 case GS_PREFIX_OPCODE:
5096 ir.override = X86_RECORD_GS_REGNUM;
5098 case DATA_PREFIX_OPCODE:
5099 prefixes |= PREFIX_DATA;
5101 case ADDR_PREFIX_OPCODE:
5102 prefixes |= PREFIX_ADDR;
5104 case 0x40: /* i386 inc %eax */
5105 case 0x41: /* i386 inc %ecx */
5106 case 0x42: /* i386 inc %edx */
5107 case 0x43: /* i386 inc %ebx */
5108 case 0x44: /* i386 inc %esp */
5109 case 0x45: /* i386 inc %ebp */
5110 case 0x46: /* i386 inc %esi */
5111 case 0x47: /* i386 inc %edi */
5112 case 0x48: /* i386 dec %eax */
5113 case 0x49: /* i386 dec %ecx */
5114 case 0x4a: /* i386 dec %edx */
5115 case 0x4b: /* i386 dec %ebx */
5116 case 0x4c: /* i386 dec %esp */
5117 case 0x4d: /* i386 dec %ebp */
5118 case 0x4e: /* i386 dec %esi */
5119 case 0x4f: /* i386 dec %edi */
5120 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
5123 rex_w = (opcode8 >> 3) & 1;
5124 rex_r = (opcode8 & 0x4) << 1;
5125 ir.rex_x = (opcode8 & 0x2) << 2;
5126 ir.rex_b = (opcode8 & 0x1) << 3;
5128 else /* 32 bit target */
5137 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
5143 if (prefixes & PREFIX_DATA)
5146 if (prefixes & PREFIX_ADDR)
5148 else if (ir.regmap[X86_RECORD_R8_REGNUM])
5151 /* Now check op code. */
5152 opcode = (uint32_t) opcode8;
5157 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5160 opcode = (uint32_t) opcode8 | 0x0f00;
5164 case 0x00: /* arith & logic */
5212 if (((opcode >> 3) & 7) != OP_CMPL)
5214 if ((opcode & 1) == 0)
5217 ir.ot = ir.dflag + OT_WORD;
5219 switch ((opcode >> 1) & 3)
5221 case 0: /* OP Ev, Gv */
5222 if (i386_record_modrm (&ir))
5226 if (i386_record_lea_modrm (&ir))
5232 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5234 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5237 case 1: /* OP Gv, Ev */
5238 if (i386_record_modrm (&ir))
5241 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5243 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5245 case 2: /* OP A, Iv */
5246 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5250 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5253 case 0x80: /* GRP1 */
5257 if (i386_record_modrm (&ir))
5260 if (ir.reg != OP_CMPL)
5262 if ((opcode & 1) == 0)
5265 ir.ot = ir.dflag + OT_WORD;
5272 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5273 if (i386_record_lea_modrm (&ir))
5277 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5279 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5282 case 0x40: /* inc */
5291 case 0x48: /* dec */
5300 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7);
5301 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5304 case 0xf6: /* GRP3 */
5306 if ((opcode & 1) == 0)
5309 ir.ot = ir.dflag + OT_WORD;
5310 if (i386_record_modrm (&ir))
5313 if (ir.mod != 3 && ir.reg == 0)
5314 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5319 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5325 if (i386_record_lea_modrm (&ir))
5331 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5333 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5335 if (ir.reg == 3) /* neg */
5336 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5342 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5343 if (ir.ot != OT_BYTE)
5344 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5345 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5349 opcode = opcode << 8 | ir.modrm;
5355 case 0xfe: /* GRP4 */
5356 case 0xff: /* GRP5 */
5357 if (i386_record_modrm (&ir))
5359 if (ir.reg >= 2 && opcode == 0xfe)
5362 opcode = opcode << 8 | ir.modrm;
5369 if ((opcode & 1) == 0)
5372 ir.ot = ir.dflag + OT_WORD;
5375 if (i386_record_lea_modrm (&ir))
5381 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5383 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5385 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5388 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5390 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5392 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5395 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5396 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5398 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5402 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5405 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5407 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5412 opcode = opcode << 8 | ir.modrm;
5418 case 0x84: /* test */
5422 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5425 case 0x98: /* CWDE/CBW */
5426 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5429 case 0x99: /* CDQ/CWD */
5430 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5431 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5434 case 0x0faf: /* imul */
5437 ir.ot = ir.dflag + OT_WORD;
5438 if (i386_record_modrm (&ir))
5441 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5442 else if (opcode == 0x6b)
5445 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5447 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5448 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5451 case 0x0fc0: /* xadd */
5453 if ((opcode & 1) == 0)
5456 ir.ot = ir.dflag + OT_WORD;
5457 if (i386_record_modrm (&ir))
5462 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5464 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5465 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5467 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5471 if (i386_record_lea_modrm (&ir))
5473 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5475 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5477 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5480 case 0x0fb0: /* cmpxchg */
5482 if ((opcode & 1) == 0)
5485 ir.ot = ir.dflag + OT_WORD;
5486 if (i386_record_modrm (&ir))
5491 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5492 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5494 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5498 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5499 if (i386_record_lea_modrm (&ir))
5502 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5505 case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */
5506 if (i386_record_modrm (&ir))
5510 /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as
5511 an extended opcode. rdrand has bits 110 (/6) and rdseed
5512 has bits 111 (/7). */
5513 if (ir.reg == 6 || ir.reg == 7)
5515 /* The storage register is described by the 3 R/M bits, but the
5516 REX.B prefix may be used to give access to registers
5517 R8~R15. In this case ir.rex_b + R/M will give us the register
5518 in the range R8~R15.
5520 REX.W may also be used to access 64-bit registers, but we
5521 already record entire registers and not just partial bits
5523 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b + ir.rm);
5524 /* These instructions also set conditional bits. */
5525 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5530 /* We don't handle this particular instruction yet. */
5532 opcode = opcode << 8 | ir.modrm;
5536 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5537 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5538 if (i386_record_lea_modrm (&ir))
5540 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5543 case 0x50: /* push */
5553 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5555 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5559 case 0x06: /* push es */
5560 case 0x0e: /* push cs */
5561 case 0x16: /* push ss */
5562 case 0x1e: /* push ds */
5563 if (ir.regmap[X86_RECORD_R8_REGNUM])
5568 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5572 case 0x0fa0: /* push fs */
5573 case 0x0fa8: /* push gs */
5574 if (ir.regmap[X86_RECORD_R8_REGNUM])
5579 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5583 case 0x60: /* pusha */
5584 if (ir.regmap[X86_RECORD_R8_REGNUM])
5589 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
5593 case 0x58: /* pop */
5601 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5602 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5605 case 0x61: /* popa */
5606 if (ir.regmap[X86_RECORD_R8_REGNUM])
5611 for (regnum = X86_RECORD_REAX_REGNUM;
5612 regnum <= X86_RECORD_REDI_REGNUM;
5614 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5617 case 0x8f: /* pop */
5618 if (ir.regmap[X86_RECORD_R8_REGNUM])
5619 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
5621 ir.ot = ir.dflag + OT_WORD;
5622 if (i386_record_modrm (&ir))
5625 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5628 ir.popl_esp_hack = 1 << ir.ot;
5629 if (i386_record_lea_modrm (&ir))
5632 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5635 case 0xc8: /* enter */
5636 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5637 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5639 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5643 case 0xc9: /* leave */
5644 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5645 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5648 case 0x07: /* pop es */
5649 if (ir.regmap[X86_RECORD_R8_REGNUM])
5654 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5655 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
5656 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5659 case 0x17: /* pop ss */
5660 if (ir.regmap[X86_RECORD_R8_REGNUM])
5665 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5666 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
5667 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5670 case 0x1f: /* pop ds */
5671 if (ir.regmap[X86_RECORD_R8_REGNUM])
5676 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5677 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
5678 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5681 case 0x0fa1: /* pop fs */
5682 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5683 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
5684 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5687 case 0x0fa9: /* pop gs */
5688 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5689 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
5690 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5693 case 0x88: /* mov */
5697 if ((opcode & 1) == 0)
5700 ir.ot = ir.dflag + OT_WORD;
5702 if (i386_record_modrm (&ir))
5707 if (opcode == 0xc6 || opcode == 0xc7)
5708 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5709 if (i386_record_lea_modrm (&ir))
5714 if (opcode == 0xc6 || opcode == 0xc7)
5716 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5718 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5722 case 0x8a: /* mov */
5724 if ((opcode & 1) == 0)
5727 ir.ot = ir.dflag + OT_WORD;
5728 if (i386_record_modrm (&ir))
5731 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5733 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5736 case 0x8c: /* mov seg */
5737 if (i386_record_modrm (&ir))
5742 opcode = opcode << 8 | ir.modrm;
5747 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5751 if (i386_record_lea_modrm (&ir))
5756 case 0x8e: /* mov seg */
5757 if (i386_record_modrm (&ir))
5762 regnum = X86_RECORD_ES_REGNUM;
5765 regnum = X86_RECORD_SS_REGNUM;
5768 regnum = X86_RECORD_DS_REGNUM;
5771 regnum = X86_RECORD_FS_REGNUM;
5774 regnum = X86_RECORD_GS_REGNUM;
5778 opcode = opcode << 8 | ir.modrm;
5782 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5783 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5786 case 0x0fb6: /* movzbS */
5787 case 0x0fb7: /* movzwS */
5788 case 0x0fbe: /* movsbS */
5789 case 0x0fbf: /* movswS */
5790 if (i386_record_modrm (&ir))
5792 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5795 case 0x8d: /* lea */
5796 if (i386_record_modrm (&ir))
5801 opcode = opcode << 8 | ir.modrm;
5806 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5808 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5811 case 0xa0: /* mov EAX */
5814 case 0xd7: /* xlat */
5815 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5818 case 0xa2: /* mov EAX */
5820 if (ir.override >= 0)
5822 if (record_full_memory_query)
5825 Process record ignores the memory change of instruction at address %s\n\
5826 because it can't get the value of the segment register.\n\
5827 Do you want to stop the program?"),
5828 paddress (gdbarch, ir.orig_addr)))
5834 if ((opcode & 1) == 0)
5837 ir.ot = ir.dflag + OT_WORD;
5840 if (record_read_memory (gdbarch, ir.addr, buf, 8))
5843 addr = extract_unsigned_integer (buf, 8, byte_order);
5847 if (record_read_memory (gdbarch, ir.addr, buf, 4))
5850 addr = extract_unsigned_integer (buf, 4, byte_order);
5854 if (record_read_memory (gdbarch, ir.addr, buf, 2))
5857 addr = extract_unsigned_integer (buf, 2, byte_order);
5859 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
5864 case 0xb0: /* mov R, Ib */
5872 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
5873 ? ((opcode & 0x7) | ir.rex_b)
5874 : ((opcode & 0x7) & 0x3));
5877 case 0xb8: /* mov R, Iv */
5885 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5888 case 0x91: /* xchg R, EAX */
5895 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5896 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7);
5899 case 0x86: /* xchg Ev, Gv */
5901 if ((opcode & 1) == 0)
5904 ir.ot = ir.dflag + OT_WORD;
5905 if (i386_record_modrm (&ir))
5910 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5912 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5916 if (i386_record_lea_modrm (&ir))
5920 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5922 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5925 case 0xc4: /* les Gv */
5926 case 0xc5: /* lds Gv */
5927 if (ir.regmap[X86_RECORD_R8_REGNUM])
5933 case 0x0fb2: /* lss Gv */
5934 case 0x0fb4: /* lfs Gv */
5935 case 0x0fb5: /* lgs Gv */
5936 if (i386_record_modrm (&ir))
5944 opcode = opcode << 8 | ir.modrm;
5949 case 0xc4: /* les Gv */
5950 regnum = X86_RECORD_ES_REGNUM;
5952 case 0xc5: /* lds Gv */
5953 regnum = X86_RECORD_DS_REGNUM;
5955 case 0x0fb2: /* lss Gv */
5956 regnum = X86_RECORD_SS_REGNUM;
5958 case 0x0fb4: /* lfs Gv */
5959 regnum = X86_RECORD_FS_REGNUM;
5961 case 0x0fb5: /* lgs Gv */
5962 regnum = X86_RECORD_GS_REGNUM;
5965 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5966 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5967 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5970 case 0xc0: /* shifts */
5976 if ((opcode & 1) == 0)
5979 ir.ot = ir.dflag + OT_WORD;
5980 if (i386_record_modrm (&ir))
5982 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
5984 if (i386_record_lea_modrm (&ir))
5990 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5992 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5994 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6001 if (i386_record_modrm (&ir))
6005 if (record_full_arch_list_add_reg (ir.regcache, ir.rm))
6010 if (i386_record_lea_modrm (&ir))
6015 case 0xd8: /* Floats. */
6023 if (i386_record_modrm (&ir))
6025 ir.reg |= ((opcode & 7) << 3);
6031 if (i386_record_lea_modrm_addr (&ir, &addr64))
6039 /* For fcom, ficom nothing to do. */
6045 /* For fcomp, ficomp pop FPU stack, store all. */
6046 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6073 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
6074 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
6075 of code, always affects st(0) register. */
6076 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6100 /* Handling fld, fild. */
6101 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6105 switch (ir.reg >> 4)
6108 if (record_full_arch_list_add_mem (addr64, 4))
6112 if (record_full_arch_list_add_mem (addr64, 8))
6118 if (record_full_arch_list_add_mem (addr64, 2))
6124 switch (ir.reg >> 4)
6127 if (record_full_arch_list_add_mem (addr64, 4))
6129 if (3 == (ir.reg & 7))
6131 /* For fstp m32fp. */
6132 if (i386_record_floats (gdbarch, &ir,
6133 I386_SAVE_FPU_REGS))
6138 if (record_full_arch_list_add_mem (addr64, 4))
6140 if ((3 == (ir.reg & 7))
6141 || (5 == (ir.reg & 7))
6142 || (7 == (ir.reg & 7)))
6144 /* For fstp insn. */
6145 if (i386_record_floats (gdbarch, &ir,
6146 I386_SAVE_FPU_REGS))
6151 if (record_full_arch_list_add_mem (addr64, 8))
6153 if (3 == (ir.reg & 7))
6155 /* For fstp m64fp. */
6156 if (i386_record_floats (gdbarch, &ir,
6157 I386_SAVE_FPU_REGS))
6162 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
6164 /* For fistp, fbld, fild, fbstp. */
6165 if (i386_record_floats (gdbarch, &ir,
6166 I386_SAVE_FPU_REGS))
6171 if (record_full_arch_list_add_mem (addr64, 2))
6180 if (i386_record_floats (gdbarch, &ir,
6181 I386_SAVE_FPU_ENV_REG_STACK))
6186 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
6191 if (i386_record_floats (gdbarch, &ir,
6192 I386_SAVE_FPU_ENV_REG_STACK))
6198 if (record_full_arch_list_add_mem (addr64, 28))
6203 if (record_full_arch_list_add_mem (addr64, 14))
6209 if (record_full_arch_list_add_mem (addr64, 2))
6211 /* Insn fstp, fbstp. */
6212 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6217 if (record_full_arch_list_add_mem (addr64, 10))
6223 if (record_full_arch_list_add_mem (addr64, 28))
6229 if (record_full_arch_list_add_mem (addr64, 14))
6233 if (record_full_arch_list_add_mem (addr64, 80))
6236 if (i386_record_floats (gdbarch, &ir,
6237 I386_SAVE_FPU_ENV_REG_STACK))
6241 if (record_full_arch_list_add_mem (addr64, 8))
6244 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6249 opcode = opcode << 8 | ir.modrm;
6254 /* Opcode is an extension of modR/M byte. */
6260 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6264 if (0x0c == (ir.modrm >> 4))
6266 if ((ir.modrm & 0x0f) <= 7)
6268 if (i386_record_floats (gdbarch, &ir,
6269 I386_SAVE_FPU_REGS))
6274 if (i386_record_floats (gdbarch, &ir,
6275 I387_ST0_REGNUM (tdep)))
6277 /* If only st(0) is changing, then we have already
6279 if ((ir.modrm & 0x0f) - 0x08)
6281 if (i386_record_floats (gdbarch, &ir,
6282 I387_ST0_REGNUM (tdep) +
6283 ((ir.modrm & 0x0f) - 0x08)))
6301 if (i386_record_floats (gdbarch, &ir,
6302 I387_ST0_REGNUM (tdep)))
6320 if (i386_record_floats (gdbarch, &ir,
6321 I386_SAVE_FPU_REGS))
6325 if (i386_record_floats (gdbarch, &ir,
6326 I387_ST0_REGNUM (tdep)))
6328 if (i386_record_floats (gdbarch, &ir,
6329 I387_ST0_REGNUM (tdep) + 1))
6336 if (0xe9 == ir.modrm)
6338 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6341 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6343 if (i386_record_floats (gdbarch, &ir,
6344 I387_ST0_REGNUM (tdep)))
6346 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6348 if (i386_record_floats (gdbarch, &ir,
6349 I387_ST0_REGNUM (tdep) +
6353 else if ((ir.modrm & 0x0f) - 0x08)
6355 if (i386_record_floats (gdbarch, &ir,
6356 I387_ST0_REGNUM (tdep) +
6357 ((ir.modrm & 0x0f) - 0x08)))
6363 if (0xe3 == ir.modrm)
6365 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
6368 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6370 if (i386_record_floats (gdbarch, &ir,
6371 I387_ST0_REGNUM (tdep)))
6373 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6375 if (i386_record_floats (gdbarch, &ir,
6376 I387_ST0_REGNUM (tdep) +
6380 else if ((ir.modrm & 0x0f) - 0x08)
6382 if (i386_record_floats (gdbarch, &ir,
6383 I387_ST0_REGNUM (tdep) +
6384 ((ir.modrm & 0x0f) - 0x08)))
6390 if ((0x0c == ir.modrm >> 4)
6391 || (0x0d == ir.modrm >> 4)
6392 || (0x0f == ir.modrm >> 4))
6394 if ((ir.modrm & 0x0f) <= 7)
6396 if (i386_record_floats (gdbarch, &ir,
6397 I387_ST0_REGNUM (tdep) +
6403 if (i386_record_floats (gdbarch, &ir,
6404 I387_ST0_REGNUM (tdep) +
6405 ((ir.modrm & 0x0f) - 0x08)))
6411 if (0x0c == ir.modrm >> 4)
6413 if (i386_record_floats (gdbarch, &ir,
6414 I387_FTAG_REGNUM (tdep)))
6417 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6419 if ((ir.modrm & 0x0f) <= 7)
6421 if (i386_record_floats (gdbarch, &ir,
6422 I387_ST0_REGNUM (tdep) +
6428 if (i386_record_floats (gdbarch, &ir,
6429 I386_SAVE_FPU_REGS))
6435 if ((0x0c == ir.modrm >> 4)
6436 || (0x0e == ir.modrm >> 4)
6437 || (0x0f == ir.modrm >> 4)
6438 || (0xd9 == ir.modrm))
6440 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6445 if (0xe0 == ir.modrm)
6447 if (record_full_arch_list_add_reg (ir.regcache,
6451 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6453 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6461 case 0xa4: /* movsS */
6463 case 0xaa: /* stosS */
6465 case 0x6c: /* insS */
6467 regcache_raw_read_unsigned (ir.regcache,
6468 ir.regmap[X86_RECORD_RECX_REGNUM],
6474 if ((opcode & 1) == 0)
6477 ir.ot = ir.dflag + OT_WORD;
6478 regcache_raw_read_unsigned (ir.regcache,
6479 ir.regmap[X86_RECORD_REDI_REGNUM],
6482 regcache_raw_read_unsigned (ir.regcache,
6483 ir.regmap[X86_RECORD_ES_REGNUM],
6485 regcache_raw_read_unsigned (ir.regcache,
6486 ir.regmap[X86_RECORD_DS_REGNUM],
6488 if (ir.aflag && (es != ds))
6490 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6491 if (record_full_memory_query)
6494 Process record ignores the memory change of instruction at address %s\n\
6495 because it can't get the value of the segment register.\n\
6496 Do you want to stop the program?"),
6497 paddress (gdbarch, ir.orig_addr)))
6503 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
6507 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6508 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6509 if (opcode == 0xa4 || opcode == 0xa5)
6510 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6511 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6512 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6516 case 0xa6: /* cmpsS */
6518 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6519 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6520 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6521 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6522 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6525 case 0xac: /* lodsS */
6527 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6528 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6529 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6530 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6531 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6534 case 0xae: /* scasS */
6536 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6537 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6538 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6539 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6542 case 0x6e: /* outsS */
6544 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6545 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6546 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6547 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6550 case 0xe4: /* port I/O */
6554 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6555 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6565 case 0xc2: /* ret im */
6566 case 0xc3: /* ret */
6567 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6568 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6571 case 0xca: /* lret im */
6572 case 0xcb: /* lret */
6573 case 0xcf: /* iret */
6574 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6575 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6576 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6579 case 0xe8: /* call im */
6580 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6582 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6586 case 0x9a: /* lcall im */
6587 if (ir.regmap[X86_RECORD_R8_REGNUM])
6592 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6593 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6597 case 0xe9: /* jmp im */
6598 case 0xea: /* ljmp im */
6599 case 0xeb: /* jmp Jb */
6600 case 0x70: /* jcc Jb */
6616 case 0x0f80: /* jcc Jv */
6634 case 0x0f90: /* setcc Gv */
6650 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6652 if (i386_record_modrm (&ir))
6655 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
6659 if (i386_record_lea_modrm (&ir))
6664 case 0x0f40: /* cmov Gv, Ev */
6680 if (i386_record_modrm (&ir))
6683 if (ir.dflag == OT_BYTE)
6685 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
6689 case 0x9c: /* pushf */
6690 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6691 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6693 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6697 case 0x9d: /* popf */
6698 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6699 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6702 case 0x9e: /* sahf */
6703 if (ir.regmap[X86_RECORD_R8_REGNUM])
6709 case 0xf5: /* cmc */
6710 case 0xf8: /* clc */
6711 case 0xf9: /* stc */
6712 case 0xfc: /* cld */
6713 case 0xfd: /* std */
6714 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6717 case 0x9f: /* lahf */
6718 if (ir.regmap[X86_RECORD_R8_REGNUM])
6723 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6724 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6727 /* bit operations */
6728 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6729 ir.ot = ir.dflag + OT_WORD;
6730 if (i386_record_modrm (&ir))
6735 opcode = opcode << 8 | ir.modrm;
6741 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6744 if (i386_record_lea_modrm (&ir))
6748 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6751 case 0x0fa3: /* bt Gv, Ev */
6752 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6755 case 0x0fab: /* bts */
6756 case 0x0fb3: /* btr */
6757 case 0x0fbb: /* btc */
6758 ir.ot = ir.dflag + OT_WORD;
6759 if (i386_record_modrm (&ir))
6762 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6766 if (i386_record_lea_modrm_addr (&ir, &addr64))
6768 regcache_raw_read_unsigned (ir.regcache,
6769 ir.regmap[ir.reg | rex_r],
6774 addr64 += ((int16_t) addr >> 4) << 4;
6777 addr64 += ((int32_t) addr >> 5) << 5;
6780 addr64 += ((int64_t) addr >> 6) << 6;
6783 if (record_full_arch_list_add_mem (addr64, 1 << ir.ot))
6785 if (i386_record_lea_modrm (&ir))
6788 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6791 case 0x0fbc: /* bsf */
6792 case 0x0fbd: /* bsr */
6793 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6794 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6798 case 0x27: /* daa */
6799 case 0x2f: /* das */
6800 case 0x37: /* aaa */
6801 case 0x3f: /* aas */
6802 case 0xd4: /* aam */
6803 case 0xd5: /* aad */
6804 if (ir.regmap[X86_RECORD_R8_REGNUM])
6809 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6810 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6814 case 0x90: /* nop */
6815 if (prefixes & PREFIX_LOCK)
6822 case 0x9b: /* fwait */
6823 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
6825 opcode = (uint32_t) opcode8;
6831 case 0xcc: /* int3 */
6832 printf_unfiltered (_("Process record does not support instruction "
6839 case 0xcd: /* int */
6843 if (record_read_memory (gdbarch, ir.addr, &interrupt, 1))
6846 if (interrupt != 0x80
6847 || tdep->i386_intx80_record == NULL)
6849 printf_unfiltered (_("Process record does not support "
6850 "instruction int 0x%02x.\n"),
6855 ret = tdep->i386_intx80_record (ir.regcache);
6862 case 0xce: /* into */
6863 printf_unfiltered (_("Process record does not support "
6864 "instruction into.\n"));
6869 case 0xfa: /* cli */
6870 case 0xfb: /* sti */
6873 case 0x62: /* bound */
6874 printf_unfiltered (_("Process record does not support "
6875 "instruction bound.\n"));
6880 case 0x0fc8: /* bswap reg */
6888 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
6891 case 0xd6: /* salc */
6892 if (ir.regmap[X86_RECORD_R8_REGNUM])
6897 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6898 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6901 case 0xe0: /* loopnz */
6902 case 0xe1: /* loopz */
6903 case 0xe2: /* loop */
6904 case 0xe3: /* jecxz */
6905 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6906 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6909 case 0x0f30: /* wrmsr */
6910 printf_unfiltered (_("Process record does not support "
6911 "instruction wrmsr.\n"));
6916 case 0x0f32: /* rdmsr */
6917 printf_unfiltered (_("Process record does not support "
6918 "instruction rdmsr.\n"));
6923 case 0x0f31: /* rdtsc */
6924 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6925 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6928 case 0x0f34: /* sysenter */
6931 if (ir.regmap[X86_RECORD_R8_REGNUM])
6936 if (tdep->i386_sysenter_record == NULL)
6938 printf_unfiltered (_("Process record does not support "
6939 "instruction sysenter.\n"));
6943 ret = tdep->i386_sysenter_record (ir.regcache);
6949 case 0x0f35: /* sysexit */
6950 printf_unfiltered (_("Process record does not support "
6951 "instruction sysexit.\n"));
6956 case 0x0f05: /* syscall */
6959 if (tdep->i386_syscall_record == NULL)
6961 printf_unfiltered (_("Process record does not support "
6962 "instruction syscall.\n"));
6966 ret = tdep->i386_syscall_record (ir.regcache);
6972 case 0x0f07: /* sysret */
6973 printf_unfiltered (_("Process record does not support "
6974 "instruction sysret.\n"));
6979 case 0x0fa2: /* cpuid */
6980 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6981 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6982 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6983 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
6986 case 0xf4: /* hlt */
6987 printf_unfiltered (_("Process record does not support "
6988 "instruction hlt.\n"));
6994 if (i386_record_modrm (&ir))
7001 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7005 if (i386_record_lea_modrm (&ir))
7014 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7018 opcode = opcode << 8 | ir.modrm;
7025 if (i386_record_modrm (&ir))
7036 opcode = opcode << 8 | ir.modrm;
7039 if (ir.override >= 0)
7041 if (record_full_memory_query)
7044 Process record ignores the memory change of instruction at address %s\n\
7045 because it can't get the value of the segment register.\n\
7046 Do you want to stop the program?"),
7047 paddress (gdbarch, ir.orig_addr)))
7053 if (i386_record_lea_modrm_addr (&ir, &addr64))
7055 if (record_full_arch_list_add_mem (addr64, 2))
7058 if (ir.regmap[X86_RECORD_R8_REGNUM])
7060 if (record_full_arch_list_add_mem (addr64, 8))
7065 if (record_full_arch_list_add_mem (addr64, 4))
7076 case 0: /* monitor */
7079 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7083 opcode = opcode << 8 | ir.modrm;
7091 if (ir.override >= 0)
7093 if (record_full_memory_query)
7096 Process record ignores the memory change of instruction at address %s\n\
7097 because it can't get the value of the segment register.\n\
7098 Do you want to stop the program?"),
7099 paddress (gdbarch, ir.orig_addr)))
7107 if (i386_record_lea_modrm_addr (&ir, &addr64))
7109 if (record_full_arch_list_add_mem (addr64, 2))
7112 if (ir.regmap[X86_RECORD_R8_REGNUM])
7114 if (record_full_arch_list_add_mem (addr64, 8))
7119 if (record_full_arch_list_add_mem (addr64, 4))
7131 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7132 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7136 else if (ir.rm == 1)
7143 opcode = opcode << 8 | ir.modrm;
7150 if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
7156 if (i386_record_lea_modrm (&ir))
7159 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7162 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7164 case 7: /* invlpg */
7167 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
7168 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
7172 opcode = opcode << 8 | ir.modrm;
7177 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7181 opcode = opcode << 8 | ir.modrm;
7187 case 0x0f08: /* invd */
7188 case 0x0f09: /* wbinvd */
7191 case 0x63: /* arpl */
7192 if (i386_record_modrm (&ir))
7194 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
7196 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
7197 ? (ir.reg | rex_r) : ir.rm);
7201 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
7202 if (i386_record_lea_modrm (&ir))
7205 if (!ir.regmap[X86_RECORD_R8_REGNUM])
7206 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7209 case 0x0f02: /* lar */
7210 case 0x0f03: /* lsl */
7211 if (i386_record_modrm (&ir))
7213 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7214 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7218 if (i386_record_modrm (&ir))
7220 if (ir.mod == 3 && ir.reg == 3)
7223 opcode = opcode << 8 | ir.modrm;
7235 /* nop (multi byte) */
7238 case 0x0f20: /* mov reg, crN */
7239 case 0x0f22: /* mov crN, reg */
7240 if (i386_record_modrm (&ir))
7242 if ((ir.modrm & 0xc0) != 0xc0)
7245 opcode = opcode << 8 | ir.modrm;
7256 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7258 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7262 opcode = opcode << 8 | ir.modrm;
7268 case 0x0f21: /* mov reg, drN */
7269 case 0x0f23: /* mov drN, reg */
7270 if (i386_record_modrm (&ir))
7272 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
7273 || ir.reg == 5 || ir.reg >= 8)
7276 opcode = opcode << 8 | ir.modrm;
7280 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7282 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7285 case 0x0f06: /* clts */
7286 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7289 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7291 case 0x0f0d: /* 3DNow! prefetch */
7294 case 0x0f0e: /* 3DNow! femms */
7295 case 0x0f77: /* emms */
7296 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
7298 record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
7301 case 0x0f0f: /* 3DNow! data */
7302 if (i386_record_modrm (&ir))
7304 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7309 case 0x0c: /* 3DNow! pi2fw */
7310 case 0x0d: /* 3DNow! pi2fd */
7311 case 0x1c: /* 3DNow! pf2iw */
7312 case 0x1d: /* 3DNow! pf2id */
7313 case 0x8a: /* 3DNow! pfnacc */
7314 case 0x8e: /* 3DNow! pfpnacc */
7315 case 0x90: /* 3DNow! pfcmpge */
7316 case 0x94: /* 3DNow! pfmin */
7317 case 0x96: /* 3DNow! pfrcp */
7318 case 0x97: /* 3DNow! pfrsqrt */
7319 case 0x9a: /* 3DNow! pfsub */
7320 case 0x9e: /* 3DNow! pfadd */
7321 case 0xa0: /* 3DNow! pfcmpgt */
7322 case 0xa4: /* 3DNow! pfmax */
7323 case 0xa6: /* 3DNow! pfrcpit1 */
7324 case 0xa7: /* 3DNow! pfrsqit1 */
7325 case 0xaa: /* 3DNow! pfsubr */
7326 case 0xae: /* 3DNow! pfacc */
7327 case 0xb0: /* 3DNow! pfcmpeq */
7328 case 0xb4: /* 3DNow! pfmul */
7329 case 0xb6: /* 3DNow! pfrcpit2 */
7330 case 0xb7: /* 3DNow! pmulhrw */
7331 case 0xbb: /* 3DNow! pswapd */
7332 case 0xbf: /* 3DNow! pavgusb */
7333 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7334 goto no_support_3dnow_data;
7335 record_full_arch_list_add_reg (ir.regcache, ir.reg);
7339 no_support_3dnow_data:
7340 opcode = (opcode << 8) | opcode8;
7346 case 0x0faa: /* rsm */
7347 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7348 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7349 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
7350 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7351 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
7352 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
7353 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
7354 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
7355 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
7359 if (i386_record_modrm (&ir))
7363 case 0: /* fxsave */
7367 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7368 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
7370 if (record_full_arch_list_add_mem (tmpu64, 512))
7375 case 1: /* fxrstor */
7379 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7381 for (i = I387_MM0_REGNUM (tdep);
7382 i386_mmx_regnum_p (gdbarch, i); i++)
7383 record_full_arch_list_add_reg (ir.regcache, i);
7385 for (i = I387_XMM0_REGNUM (tdep);
7386 i386_xmm_regnum_p (gdbarch, i); i++)
7387 record_full_arch_list_add_reg (ir.regcache, i);
7389 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7390 record_full_arch_list_add_reg (ir.regcache,
7391 I387_MXCSR_REGNUM(tdep));
7393 for (i = I387_ST0_REGNUM (tdep);
7394 i386_fp_regnum_p (gdbarch, i); i++)
7395 record_full_arch_list_add_reg (ir.regcache, i);
7397 for (i = I387_FCTRL_REGNUM (tdep);
7398 i386_fpc_regnum_p (gdbarch, i); i++)
7399 record_full_arch_list_add_reg (ir.regcache, i);
7403 case 2: /* ldmxcsr */
7404 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7406 record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
7409 case 3: /* stmxcsr */
7411 if (i386_record_lea_modrm (&ir))
7415 case 5: /* lfence */
7416 case 6: /* mfence */
7417 case 7: /* sfence clflush */
7421 opcode = (opcode << 8) | ir.modrm;
7427 case 0x0fc3: /* movnti */
7428 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
7429 if (i386_record_modrm (&ir))
7434 if (i386_record_lea_modrm (&ir))
7438 /* Add prefix to opcode. */
7553 /* Mask out PREFIX_ADDR. */
7554 switch ((prefixes & ~PREFIX_ADDR))
7566 reswitch_prefix_add:
7574 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7577 opcode = (uint32_t) opcode8 | opcode << 8;
7578 goto reswitch_prefix_add;
7581 case 0x0f10: /* movups */
7582 case 0x660f10: /* movupd */
7583 case 0xf30f10: /* movss */
7584 case 0xf20f10: /* movsd */
7585 case 0x0f12: /* movlps */
7586 case 0x660f12: /* movlpd */
7587 case 0xf30f12: /* movsldup */
7588 case 0xf20f12: /* movddup */
7589 case 0x0f14: /* unpcklps */
7590 case 0x660f14: /* unpcklpd */
7591 case 0x0f15: /* unpckhps */
7592 case 0x660f15: /* unpckhpd */
7593 case 0x0f16: /* movhps */
7594 case 0x660f16: /* movhpd */
7595 case 0xf30f16: /* movshdup */
7596 case 0x0f28: /* movaps */
7597 case 0x660f28: /* movapd */
7598 case 0x0f2a: /* cvtpi2ps */
7599 case 0x660f2a: /* cvtpi2pd */
7600 case 0xf30f2a: /* cvtsi2ss */
7601 case 0xf20f2a: /* cvtsi2sd */
7602 case 0x0f2c: /* cvttps2pi */
7603 case 0x660f2c: /* cvttpd2pi */
7604 case 0x0f2d: /* cvtps2pi */
7605 case 0x660f2d: /* cvtpd2pi */
7606 case 0x660f3800: /* pshufb */
7607 case 0x660f3801: /* phaddw */
7608 case 0x660f3802: /* phaddd */
7609 case 0x660f3803: /* phaddsw */
7610 case 0x660f3804: /* pmaddubsw */
7611 case 0x660f3805: /* phsubw */
7612 case 0x660f3806: /* phsubd */
7613 case 0x660f3807: /* phsubsw */
7614 case 0x660f3808: /* psignb */
7615 case 0x660f3809: /* psignw */
7616 case 0x660f380a: /* psignd */
7617 case 0x660f380b: /* pmulhrsw */
7618 case 0x660f3810: /* pblendvb */
7619 case 0x660f3814: /* blendvps */
7620 case 0x660f3815: /* blendvpd */
7621 case 0x660f381c: /* pabsb */
7622 case 0x660f381d: /* pabsw */
7623 case 0x660f381e: /* pabsd */
7624 case 0x660f3820: /* pmovsxbw */
7625 case 0x660f3821: /* pmovsxbd */
7626 case 0x660f3822: /* pmovsxbq */
7627 case 0x660f3823: /* pmovsxwd */
7628 case 0x660f3824: /* pmovsxwq */
7629 case 0x660f3825: /* pmovsxdq */
7630 case 0x660f3828: /* pmuldq */
7631 case 0x660f3829: /* pcmpeqq */
7632 case 0x660f382a: /* movntdqa */
7633 case 0x660f3a08: /* roundps */
7634 case 0x660f3a09: /* roundpd */
7635 case 0x660f3a0a: /* roundss */
7636 case 0x660f3a0b: /* roundsd */
7637 case 0x660f3a0c: /* blendps */
7638 case 0x660f3a0d: /* blendpd */
7639 case 0x660f3a0e: /* pblendw */
7640 case 0x660f3a0f: /* palignr */
7641 case 0x660f3a20: /* pinsrb */
7642 case 0x660f3a21: /* insertps */
7643 case 0x660f3a22: /* pinsrd pinsrq */
7644 case 0x660f3a40: /* dpps */
7645 case 0x660f3a41: /* dppd */
7646 case 0x660f3a42: /* mpsadbw */
7647 case 0x660f3a60: /* pcmpestrm */
7648 case 0x660f3a61: /* pcmpestri */
7649 case 0x660f3a62: /* pcmpistrm */
7650 case 0x660f3a63: /* pcmpistri */
7651 case 0x0f51: /* sqrtps */
7652 case 0x660f51: /* sqrtpd */
7653 case 0xf20f51: /* sqrtsd */
7654 case 0xf30f51: /* sqrtss */
7655 case 0x0f52: /* rsqrtps */
7656 case 0xf30f52: /* rsqrtss */
7657 case 0x0f53: /* rcpps */
7658 case 0xf30f53: /* rcpss */
7659 case 0x0f54: /* andps */
7660 case 0x660f54: /* andpd */
7661 case 0x0f55: /* andnps */
7662 case 0x660f55: /* andnpd */
7663 case 0x0f56: /* orps */
7664 case 0x660f56: /* orpd */
7665 case 0x0f57: /* xorps */
7666 case 0x660f57: /* xorpd */
7667 case 0x0f58: /* addps */
7668 case 0x660f58: /* addpd */
7669 case 0xf20f58: /* addsd */
7670 case 0xf30f58: /* addss */
7671 case 0x0f59: /* mulps */
7672 case 0x660f59: /* mulpd */
7673 case 0xf20f59: /* mulsd */
7674 case 0xf30f59: /* mulss */
7675 case 0x0f5a: /* cvtps2pd */
7676 case 0x660f5a: /* cvtpd2ps */
7677 case 0xf20f5a: /* cvtsd2ss */
7678 case 0xf30f5a: /* cvtss2sd */
7679 case 0x0f5b: /* cvtdq2ps */
7680 case 0x660f5b: /* cvtps2dq */
7681 case 0xf30f5b: /* cvttps2dq */
7682 case 0x0f5c: /* subps */
7683 case 0x660f5c: /* subpd */
7684 case 0xf20f5c: /* subsd */
7685 case 0xf30f5c: /* subss */
7686 case 0x0f5d: /* minps */
7687 case 0x660f5d: /* minpd */
7688 case 0xf20f5d: /* minsd */
7689 case 0xf30f5d: /* minss */
7690 case 0x0f5e: /* divps */
7691 case 0x660f5e: /* divpd */
7692 case 0xf20f5e: /* divsd */
7693 case 0xf30f5e: /* divss */
7694 case 0x0f5f: /* maxps */
7695 case 0x660f5f: /* maxpd */
7696 case 0xf20f5f: /* maxsd */
7697 case 0xf30f5f: /* maxss */
7698 case 0x660f60: /* punpcklbw */
7699 case 0x660f61: /* punpcklwd */
7700 case 0x660f62: /* punpckldq */
7701 case 0x660f63: /* packsswb */
7702 case 0x660f64: /* pcmpgtb */
7703 case 0x660f65: /* pcmpgtw */
7704 case 0x660f66: /* pcmpgtd */
7705 case 0x660f67: /* packuswb */
7706 case 0x660f68: /* punpckhbw */
7707 case 0x660f69: /* punpckhwd */
7708 case 0x660f6a: /* punpckhdq */
7709 case 0x660f6b: /* packssdw */
7710 case 0x660f6c: /* punpcklqdq */
7711 case 0x660f6d: /* punpckhqdq */
7712 case 0x660f6e: /* movd */
7713 case 0x660f6f: /* movdqa */
7714 case 0xf30f6f: /* movdqu */
7715 case 0x660f70: /* pshufd */
7716 case 0xf20f70: /* pshuflw */
7717 case 0xf30f70: /* pshufhw */
7718 case 0x660f74: /* pcmpeqb */
7719 case 0x660f75: /* pcmpeqw */
7720 case 0x660f76: /* pcmpeqd */
7721 case 0x660f7c: /* haddpd */
7722 case 0xf20f7c: /* haddps */
7723 case 0x660f7d: /* hsubpd */
7724 case 0xf20f7d: /* hsubps */
7725 case 0xf30f7e: /* movq */
7726 case 0x0fc2: /* cmpps */
7727 case 0x660fc2: /* cmppd */
7728 case 0xf20fc2: /* cmpsd */
7729 case 0xf30fc2: /* cmpss */
7730 case 0x660fc4: /* pinsrw */
7731 case 0x0fc6: /* shufps */
7732 case 0x660fc6: /* shufpd */
7733 case 0x660fd0: /* addsubpd */
7734 case 0xf20fd0: /* addsubps */
7735 case 0x660fd1: /* psrlw */
7736 case 0x660fd2: /* psrld */
7737 case 0x660fd3: /* psrlq */
7738 case 0x660fd4: /* paddq */
7739 case 0x660fd5: /* pmullw */
7740 case 0xf30fd6: /* movq2dq */
7741 case 0x660fd8: /* psubusb */
7742 case 0x660fd9: /* psubusw */
7743 case 0x660fda: /* pminub */
7744 case 0x660fdb: /* pand */
7745 case 0x660fdc: /* paddusb */
7746 case 0x660fdd: /* paddusw */
7747 case 0x660fde: /* pmaxub */
7748 case 0x660fdf: /* pandn */
7749 case 0x660fe0: /* pavgb */
7750 case 0x660fe1: /* psraw */
7751 case 0x660fe2: /* psrad */
7752 case 0x660fe3: /* pavgw */
7753 case 0x660fe4: /* pmulhuw */
7754 case 0x660fe5: /* pmulhw */
7755 case 0x660fe6: /* cvttpd2dq */
7756 case 0xf20fe6: /* cvtpd2dq */
7757 case 0xf30fe6: /* cvtdq2pd */
7758 case 0x660fe8: /* psubsb */
7759 case 0x660fe9: /* psubsw */
7760 case 0x660fea: /* pminsw */
7761 case 0x660feb: /* por */
7762 case 0x660fec: /* paddsb */
7763 case 0x660fed: /* paddsw */
7764 case 0x660fee: /* pmaxsw */
7765 case 0x660fef: /* pxor */
7766 case 0xf20ff0: /* lddqu */
7767 case 0x660ff1: /* psllw */
7768 case 0x660ff2: /* pslld */
7769 case 0x660ff3: /* psllq */
7770 case 0x660ff4: /* pmuludq */
7771 case 0x660ff5: /* pmaddwd */
7772 case 0x660ff6: /* psadbw */
7773 case 0x660ff8: /* psubb */
7774 case 0x660ff9: /* psubw */
7775 case 0x660ffa: /* psubd */
7776 case 0x660ffb: /* psubq */
7777 case 0x660ffc: /* paddb */
7778 case 0x660ffd: /* paddw */
7779 case 0x660ffe: /* paddd */
7780 if (i386_record_modrm (&ir))
7783 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
7785 record_full_arch_list_add_reg (ir.regcache,
7786 I387_XMM0_REGNUM (tdep) + ir.reg);
7787 if ((opcode & 0xfffffffc) == 0x660f3a60)
7788 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7791 case 0x0f11: /* movups */
7792 case 0x660f11: /* movupd */
7793 case 0xf30f11: /* movss */
7794 case 0xf20f11: /* movsd */
7795 case 0x0f13: /* movlps */
7796 case 0x660f13: /* movlpd */
7797 case 0x0f17: /* movhps */
7798 case 0x660f17: /* movhpd */
7799 case 0x0f29: /* movaps */
7800 case 0x660f29: /* movapd */
7801 case 0x660f3a14: /* pextrb */
7802 case 0x660f3a15: /* pextrw */
7803 case 0x660f3a16: /* pextrd pextrq */
7804 case 0x660f3a17: /* extractps */
7805 case 0x660f7f: /* movdqa */
7806 case 0xf30f7f: /* movdqu */
7807 if (i386_record_modrm (&ir))
7811 if (opcode == 0x0f13 || opcode == 0x660f13
7812 || opcode == 0x0f17 || opcode == 0x660f17)
7815 if (!i386_xmm_regnum_p (gdbarch,
7816 I387_XMM0_REGNUM (tdep) + ir.rm))
7818 record_full_arch_list_add_reg (ir.regcache,
7819 I387_XMM0_REGNUM (tdep) + ir.rm);
7841 if (i386_record_lea_modrm (&ir))
7846 case 0x0f2b: /* movntps */
7847 case 0x660f2b: /* movntpd */
7848 case 0x0fe7: /* movntq */
7849 case 0x660fe7: /* movntdq */
7852 if (opcode == 0x0fe7)
7856 if (i386_record_lea_modrm (&ir))
7860 case 0xf30f2c: /* cvttss2si */
7861 case 0xf20f2c: /* cvttsd2si */
7862 case 0xf30f2d: /* cvtss2si */
7863 case 0xf20f2d: /* cvtsd2si */
7864 case 0xf20f38f0: /* crc32 */
7865 case 0xf20f38f1: /* crc32 */
7866 case 0x0f50: /* movmskps */
7867 case 0x660f50: /* movmskpd */
7868 case 0x0fc5: /* pextrw */
7869 case 0x660fc5: /* pextrw */
7870 case 0x0fd7: /* pmovmskb */
7871 case 0x660fd7: /* pmovmskb */
7872 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7875 case 0x0f3800: /* pshufb */
7876 case 0x0f3801: /* phaddw */
7877 case 0x0f3802: /* phaddd */
7878 case 0x0f3803: /* phaddsw */
7879 case 0x0f3804: /* pmaddubsw */
7880 case 0x0f3805: /* phsubw */
7881 case 0x0f3806: /* phsubd */
7882 case 0x0f3807: /* phsubsw */
7883 case 0x0f3808: /* psignb */
7884 case 0x0f3809: /* psignw */
7885 case 0x0f380a: /* psignd */
7886 case 0x0f380b: /* pmulhrsw */
7887 case 0x0f381c: /* pabsb */
7888 case 0x0f381d: /* pabsw */
7889 case 0x0f381e: /* pabsd */
7890 case 0x0f382b: /* packusdw */
7891 case 0x0f3830: /* pmovzxbw */
7892 case 0x0f3831: /* pmovzxbd */
7893 case 0x0f3832: /* pmovzxbq */
7894 case 0x0f3833: /* pmovzxwd */
7895 case 0x0f3834: /* pmovzxwq */
7896 case 0x0f3835: /* pmovzxdq */
7897 case 0x0f3837: /* pcmpgtq */
7898 case 0x0f3838: /* pminsb */
7899 case 0x0f3839: /* pminsd */
7900 case 0x0f383a: /* pminuw */
7901 case 0x0f383b: /* pminud */
7902 case 0x0f383c: /* pmaxsb */
7903 case 0x0f383d: /* pmaxsd */
7904 case 0x0f383e: /* pmaxuw */
7905 case 0x0f383f: /* pmaxud */
7906 case 0x0f3840: /* pmulld */
7907 case 0x0f3841: /* phminposuw */
7908 case 0x0f3a0f: /* palignr */
7909 case 0x0f60: /* punpcklbw */
7910 case 0x0f61: /* punpcklwd */
7911 case 0x0f62: /* punpckldq */
7912 case 0x0f63: /* packsswb */
7913 case 0x0f64: /* pcmpgtb */
7914 case 0x0f65: /* pcmpgtw */
7915 case 0x0f66: /* pcmpgtd */
7916 case 0x0f67: /* packuswb */
7917 case 0x0f68: /* punpckhbw */
7918 case 0x0f69: /* punpckhwd */
7919 case 0x0f6a: /* punpckhdq */
7920 case 0x0f6b: /* packssdw */
7921 case 0x0f6e: /* movd */
7922 case 0x0f6f: /* movq */
7923 case 0x0f70: /* pshufw */
7924 case 0x0f74: /* pcmpeqb */
7925 case 0x0f75: /* pcmpeqw */
7926 case 0x0f76: /* pcmpeqd */
7927 case 0x0fc4: /* pinsrw */
7928 case 0x0fd1: /* psrlw */
7929 case 0x0fd2: /* psrld */
7930 case 0x0fd3: /* psrlq */
7931 case 0x0fd4: /* paddq */
7932 case 0x0fd5: /* pmullw */
7933 case 0xf20fd6: /* movdq2q */
7934 case 0x0fd8: /* psubusb */
7935 case 0x0fd9: /* psubusw */
7936 case 0x0fda: /* pminub */
7937 case 0x0fdb: /* pand */
7938 case 0x0fdc: /* paddusb */
7939 case 0x0fdd: /* paddusw */
7940 case 0x0fde: /* pmaxub */
7941 case 0x0fdf: /* pandn */
7942 case 0x0fe0: /* pavgb */
7943 case 0x0fe1: /* psraw */
7944 case 0x0fe2: /* psrad */
7945 case 0x0fe3: /* pavgw */
7946 case 0x0fe4: /* pmulhuw */
7947 case 0x0fe5: /* pmulhw */
7948 case 0x0fe8: /* psubsb */
7949 case 0x0fe9: /* psubsw */
7950 case 0x0fea: /* pminsw */
7951 case 0x0feb: /* por */
7952 case 0x0fec: /* paddsb */
7953 case 0x0fed: /* paddsw */
7954 case 0x0fee: /* pmaxsw */
7955 case 0x0fef: /* pxor */
7956 case 0x0ff1: /* psllw */
7957 case 0x0ff2: /* pslld */
7958 case 0x0ff3: /* psllq */
7959 case 0x0ff4: /* pmuludq */
7960 case 0x0ff5: /* pmaddwd */
7961 case 0x0ff6: /* psadbw */
7962 case 0x0ff8: /* psubb */
7963 case 0x0ff9: /* psubw */
7964 case 0x0ffa: /* psubd */
7965 case 0x0ffb: /* psubq */
7966 case 0x0ffc: /* paddb */
7967 case 0x0ffd: /* paddw */
7968 case 0x0ffe: /* paddd */
7969 if (i386_record_modrm (&ir))
7971 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7973 record_full_arch_list_add_reg (ir.regcache,
7974 I387_MM0_REGNUM (tdep) + ir.reg);
7977 case 0x0f71: /* psllw */
7978 case 0x0f72: /* pslld */
7979 case 0x0f73: /* psllq */
7980 if (i386_record_modrm (&ir))
7982 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7984 record_full_arch_list_add_reg (ir.regcache,
7985 I387_MM0_REGNUM (tdep) + ir.rm);
7988 case 0x660f71: /* psllw */
7989 case 0x660f72: /* pslld */
7990 case 0x660f73: /* psllq */
7991 if (i386_record_modrm (&ir))
7994 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
7996 record_full_arch_list_add_reg (ir.regcache,
7997 I387_XMM0_REGNUM (tdep) + ir.rm);
8000 case 0x0f7e: /* movd */
8001 case 0x660f7e: /* movd */
8002 if (i386_record_modrm (&ir))
8005 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
8012 if (i386_record_lea_modrm (&ir))
8017 case 0x0f7f: /* movq */
8018 if (i386_record_modrm (&ir))
8022 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
8024 record_full_arch_list_add_reg (ir.regcache,
8025 I387_MM0_REGNUM (tdep) + ir.rm);
8030 if (i386_record_lea_modrm (&ir))
8035 case 0xf30fb8: /* popcnt */
8036 if (i386_record_modrm (&ir))
8038 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
8039 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
8042 case 0x660fd6: /* movq */
8043 if (i386_record_modrm (&ir))
8048 if (!i386_xmm_regnum_p (gdbarch,
8049 I387_XMM0_REGNUM (tdep) + ir.rm))
8051 record_full_arch_list_add_reg (ir.regcache,
8052 I387_XMM0_REGNUM (tdep) + ir.rm);
8057 if (i386_record_lea_modrm (&ir))
8062 case 0x660f3817: /* ptest */
8063 case 0x0f2e: /* ucomiss */
8064 case 0x660f2e: /* ucomisd */
8065 case 0x0f2f: /* comiss */
8066 case 0x660f2f: /* comisd */
8067 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
8070 case 0x0ff7: /* maskmovq */
8071 regcache_raw_read_unsigned (ir.regcache,
8072 ir.regmap[X86_RECORD_REDI_REGNUM],
8074 if (record_full_arch_list_add_mem (addr, 64))
8078 case 0x660ff7: /* maskmovdqu */
8079 regcache_raw_read_unsigned (ir.regcache,
8080 ir.regmap[X86_RECORD_REDI_REGNUM],
8082 if (record_full_arch_list_add_mem (addr, 128))
8097 /* In the future, maybe still need to deal with need_dasm. */
8098 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
8099 if (record_full_arch_list_add_end ())
8105 printf_unfiltered (_("Process record does not support instruction 0x%02x "
8106 "at address %s.\n"),
8107 (unsigned int) (opcode),
8108 paddress (gdbarch, ir.orig_addr));
8112 static const int i386_record_regmap[] =
8114 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
8115 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
8116 0, 0, 0, 0, 0, 0, 0, 0,
8117 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
8118 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
8121 /* Check that the given address appears suitable for a fast
8122 tracepoint, which on x86-64 means that we need an instruction of at
8123 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8124 jump and not have to worry about program jumps to an address in the
8125 middle of the tracepoint jump. On x86, it may be possible to use
8126 4-byte jumps with a 2-byte offset to a trampoline located in the
8127 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8128 of instruction to replace, and 0 if not, plus an explanatory
8132 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, CORE_ADDR addr,
8137 /* Ask the target for the minimum instruction length supported. */
8138 jumplen = target_get_min_fast_tracepoint_insn_len ();
8142 /* If the target does not support the get_min_fast_tracepoint_insn_len
8143 operation, assume that fast tracepoints will always be implemented
8144 using 4-byte relative jumps on both x86 and x86-64. */
8147 else if (jumplen == 0)
8149 /* If the target does support get_min_fast_tracepoint_insn_len but
8150 returns zero, then the IPA has not loaded yet. In this case,
8151 we optimistically assume that truncated 2-byte relative jumps
8152 will be available on x86, and compensate later if this assumption
8153 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8154 jumps will always be used. */
8155 jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4;
8158 /* Check for fit. */
8159 len = gdb_insn_length (gdbarch, addr);
8163 /* Return a bit of target-specific detail to add to the caller's
8164 generic failure message. */
8166 *msg = xstrprintf (_("; instruction is only %d bytes long, "
8167 "need at least %d bytes for the jump"),
8179 /* Return a floating-point format for a floating-point variable of
8180 length LEN in bits. If non-NULL, NAME is the name of its type.
8181 If no suitable type is found, return NULL. */
8183 const struct floatformat **
8184 i386_floatformat_for_type (struct gdbarch *gdbarch,
8185 const char *name, int len)
8187 if (len == 128 && name)
8188 if (strcmp (name, "__float128") == 0
8189 || strcmp (name, "_Float128") == 0
8190 || strcmp (name, "complex _Float128") == 0)
8191 return floatformats_ia64_quad;
8193 return default_floatformat_for_type (gdbarch, name, len);
8197 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
8198 struct tdesc_arch_data *tdesc_data)
8200 const struct target_desc *tdesc = tdep->tdesc;
8201 const struct tdesc_feature *feature_core;
8203 const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx,
8205 int i, num_regs, valid_p;
8207 if (! tdesc_has_registers (tdesc))
8210 /* Get core registers. */
8211 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
8212 if (feature_core == NULL)
8215 /* Get SSE registers. */
8216 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
8218 /* Try AVX registers. */
8219 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
8221 /* Try MPX registers. */
8222 feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx");
8224 /* Try AVX512 registers. */
8225 feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512");
8229 /* The XCR0 bits. */
8232 /* AVX512 register description requires AVX register description. */
8236 tdep->xcr0 = X86_XSTATE_AVX_AVX512_MASK;
8238 /* It may have been set by OSABI initialization function. */
8239 if (tdep->k0_regnum < 0)
8241 tdep->k_register_names = i386_k_names;
8242 tdep->k0_regnum = I386_K0_REGNUM;
8245 for (i = 0; i < I387_NUM_K_REGS; i++)
8246 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8247 tdep->k0_regnum + i,
8250 if (tdep->num_zmm_regs == 0)
8252 tdep->zmmh_register_names = i386_zmmh_names;
8253 tdep->num_zmm_regs = 8;
8254 tdep->zmm0h_regnum = I386_ZMM0H_REGNUM;
8257 for (i = 0; i < tdep->num_zmm_regs; i++)
8258 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8259 tdep->zmm0h_regnum + i,
8260 tdep->zmmh_register_names[i]);
8262 for (i = 0; i < tdep->num_xmm_avx512_regs; i++)
8263 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8264 tdep->xmm16_regnum + i,
8265 tdep->xmm_avx512_register_names[i]);
8267 for (i = 0; i < tdep->num_ymm_avx512_regs; i++)
8268 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8269 tdep->ymm16h_regnum + i,
8270 tdep->ymm16h_register_names[i]);
8274 /* AVX register description requires SSE register description. */
8278 if (!feature_avx512)
8279 tdep->xcr0 = X86_XSTATE_AVX_MASK;
8281 /* It may have been set by OSABI initialization function. */
8282 if (tdep->num_ymm_regs == 0)
8284 tdep->ymmh_register_names = i386_ymmh_names;
8285 tdep->num_ymm_regs = 8;
8286 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
8289 for (i = 0; i < tdep->num_ymm_regs; i++)
8290 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
8291 tdep->ymm0h_regnum + i,
8292 tdep->ymmh_register_names[i]);
8294 else if (feature_sse)
8295 tdep->xcr0 = X86_XSTATE_SSE_MASK;
8298 tdep->xcr0 = X86_XSTATE_X87_MASK;
8299 tdep->num_xmm_regs = 0;
8302 num_regs = tdep->num_core_regs;
8303 for (i = 0; i < num_regs; i++)
8304 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
8305 tdep->register_names[i]);
8309 /* Need to include %mxcsr, so add one. */
8310 num_regs += tdep->num_xmm_regs + 1;
8311 for (; i < num_regs; i++)
8312 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
8313 tdep->register_names[i]);
8318 tdep->xcr0 |= X86_XSTATE_MPX_MASK;
8320 if (tdep->bnd0r_regnum < 0)
8322 tdep->mpx_register_names = i386_mpx_names;
8323 tdep->bnd0r_regnum = I386_BND0R_REGNUM;
8324 tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM;
8327 for (i = 0; i < I387_NUM_MPX_REGS; i++)
8328 valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data,
8329 I387_BND0R_REGNUM (tdep) + i,
8330 tdep->mpx_register_names[i]);
8337 /* Note: This is called for both i386 and amd64. */
8339 static struct gdbarch *
8340 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8342 struct gdbarch_tdep *tdep;
8343 struct gdbarch *gdbarch;
8344 struct tdesc_arch_data *tdesc_data;
8345 const struct target_desc *tdesc;
8351 /* If there is already a candidate, use it. */
8352 arches = gdbarch_list_lookup_by_info (arches, &info);
8354 return arches->gdbarch;
8356 /* Allocate space for the new architecture. Assume i386 for now. */
8357 tdep = XCNEW (struct gdbarch_tdep);
8358 gdbarch = gdbarch_alloc (&info, tdep);
8360 /* General-purpose registers. */
8361 tdep->gregset_reg_offset = NULL;
8362 tdep->gregset_num_regs = I386_NUM_GREGS;
8363 tdep->sizeof_gregset = 0;
8365 /* Floating-point registers. */
8366 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
8367 tdep->fpregset = &i386_fpregset;
8369 /* The default settings include the FPU registers, the MMX registers
8370 and the SSE registers. This can be overridden for a specific ABI
8371 by adjusting the members `st0_regnum', `mm0_regnum' and
8372 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8373 will show up in the output of "info all-registers". */
8375 tdep->st0_regnum = I386_ST0_REGNUM;
8377 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8378 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
8380 tdep->jb_pc_offset = -1;
8381 tdep->struct_return = pcc_struct_return;
8382 tdep->sigtramp_start = 0;
8383 tdep->sigtramp_end = 0;
8384 tdep->sigtramp_p = i386_sigtramp_p;
8385 tdep->sigcontext_addr = NULL;
8386 tdep->sc_reg_offset = NULL;
8387 tdep->sc_pc_offset = -1;
8388 tdep->sc_sp_offset = -1;
8390 tdep->xsave_xcr0_offset = -1;
8392 tdep->record_regmap = i386_record_regmap;
8394 set_gdbarch_long_long_align_bit (gdbarch, 32);
8396 /* The format used for `long double' on almost all i386 targets is
8397 the i387 extended floating-point format. In fact, of all targets
8398 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8399 on having a `long double' that's not `long' at all. */
8400 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
8402 /* Although the i387 extended floating-point has only 80 significant
8403 bits, a `long double' actually takes up 96, probably to enforce
8405 set_gdbarch_long_double_bit (gdbarch, 96);
8407 /* Support for floating-point data type variants. */
8408 set_gdbarch_floatformat_for_type (gdbarch, i386_floatformat_for_type);
8410 /* Register numbers of various important registers. */
8411 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
8412 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
8413 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
8414 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
8416 /* NOTE: kettenis/20040418: GCC does have two possible register
8417 numbering schemes on the i386: dbx and SVR4. These schemes
8418 differ in how they number %ebp, %esp, %eflags, and the
8419 floating-point registers, and are implemented by the arrays
8420 dbx_register_map[] and svr4_dbx_register_map in
8421 gcc/config/i386.c. GCC also defines a third numbering scheme in
8422 gcc/config/i386.c, which it designates as the "default" register
8423 map used in 64bit mode. This last register numbering scheme is
8424 implemented in dbx64_register_map, and is used for AMD64; see
8427 Currently, each GCC i386 target always uses the same register
8428 numbering scheme across all its supported debugging formats
8429 i.e. SDB (COFF), stabs and DWARF 2. This is because
8430 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8431 DBX_REGISTER_NUMBER macro which is defined by each target's
8432 respective config header in a manner independent of the requested
8433 output debugging format.
8435 This does not match the arrangement below, which presumes that
8436 the SDB and stabs numbering schemes differ from the DWARF and
8437 DWARF 2 ones. The reason for this arrangement is that it is
8438 likely to get the numbering scheme for the target's
8439 default/native debug format right. For targets where GCC is the
8440 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8441 targets where the native toolchain uses a different numbering
8442 scheme for a particular debug format (stabs-in-ELF on Solaris)
8443 the defaults below will have to be overridden, like
8444 i386_elf_init_abi() does. */
8446 /* Use the dbx register numbering scheme for stabs and COFF. */
8447 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8448 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8450 /* Use the SVR4 register numbering scheme for DWARF 2. */
8451 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_dwarf_reg_to_regnum);
8453 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8454 be in use on any of the supported i386 targets. */
8456 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
8458 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
8460 /* Call dummy code. */
8461 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
8462 set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code);
8463 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
8464 set_gdbarch_frame_align (gdbarch, i386_frame_align);
8466 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
8467 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
8468 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
8470 set_gdbarch_return_value (gdbarch, i386_return_value);
8472 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
8474 /* Stack grows downward. */
8475 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8477 set_gdbarch_breakpoint_kind_from_pc (gdbarch, i386_breakpoint::kind_from_pc);
8478 set_gdbarch_sw_breakpoint_from_kind (gdbarch, i386_breakpoint::bp_from_kind);
8480 set_gdbarch_decr_pc_after_break (gdbarch, 1);
8481 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
8483 set_gdbarch_frame_args_skip (gdbarch, 8);
8485 set_gdbarch_print_insn (gdbarch, i386_print_insn);
8487 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
8489 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
8491 /* Add the i386 register groups. */
8492 i386_add_reggroups (gdbarch);
8493 tdep->register_reggroup_p = i386_register_reggroup_p;
8495 /* Helper for function argument information. */
8496 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
8498 /* Hook the function epilogue frame unwinder. This unwinder is
8499 appended to the list first, so that it supercedes the DWARF
8500 unwinder in function epilogues (where the DWARF unwinder
8501 currently fails). */
8502 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
8504 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8505 to the list before the prologue-based unwinders, so that DWARF
8506 CFI info will be used if it is available. */
8507 dwarf2_append_unwinders (gdbarch);
8509 frame_base_set_default (gdbarch, &i386_frame_base);
8511 /* Pseudo registers may be changed by amd64_init_abi. */
8512 set_gdbarch_pseudo_register_read_value (gdbarch,
8513 i386_pseudo_register_read_value);
8514 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
8515 set_gdbarch_ax_pseudo_register_collect (gdbarch,
8516 i386_ax_pseudo_register_collect);
8518 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
8519 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
8521 /* Override the normal target description method to make the AVX
8522 upper halves anonymous. */
8523 set_gdbarch_register_name (gdbarch, i386_register_name);
8525 /* Even though the default ABI only includes general-purpose registers,
8526 floating-point registers and the SSE registers, we have to leave a
8527 gap for the upper AVX, MPX and AVX512 registers. */
8528 set_gdbarch_num_regs (gdbarch, I386_AVX512_NUM_REGS);
8530 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
8532 /* Get the x86 target description from INFO. */
8533 tdesc = info.target_desc;
8534 if (! tdesc_has_registers (tdesc))
8536 tdep->tdesc = tdesc;
8538 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
8539 tdep->register_names = i386_register_names;
8541 /* No upper YMM registers. */
8542 tdep->ymmh_register_names = NULL;
8543 tdep->ymm0h_regnum = -1;
8545 /* No upper ZMM registers. */
8546 tdep->zmmh_register_names = NULL;
8547 tdep->zmm0h_regnum = -1;
8549 /* No high XMM registers. */
8550 tdep->xmm_avx512_register_names = NULL;
8551 tdep->xmm16_regnum = -1;
8553 /* No upper YMM16-31 registers. */
8554 tdep->ymm16h_register_names = NULL;
8555 tdep->ymm16h_regnum = -1;
8557 tdep->num_byte_regs = 8;
8558 tdep->num_word_regs = 8;
8559 tdep->num_dword_regs = 0;
8560 tdep->num_mmx_regs = 8;
8561 tdep->num_ymm_regs = 0;
8563 /* No MPX registers. */
8564 tdep->bnd0r_regnum = -1;
8565 tdep->bndcfgu_regnum = -1;
8567 /* No AVX512 registers. */
8568 tdep->k0_regnum = -1;
8569 tdep->num_zmm_regs = 0;
8570 tdep->num_ymm_avx512_regs = 0;
8571 tdep->num_xmm_avx512_regs = 0;
8573 tdesc_data = tdesc_data_alloc ();
8575 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
8577 set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address);
8579 set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call);
8580 set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret);
8581 set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump);
8583 /* Hook in ABI-specific overrides, if they have been registered.
8584 Note: If INFO specifies a 64 bit arch, this is where we turn
8585 a 32-bit i386 into a 64-bit amd64. */
8586 info.tdep_info = tdesc_data;
8587 gdbarch_init_osabi (info, gdbarch);
8589 if (!i386_validate_tdesc_p (tdep, tdesc_data))
8591 tdesc_data_cleanup (tdesc_data);
8593 gdbarch_free (gdbarch);
8597 num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0);
8599 /* Wire in pseudo registers. Number of pseudo registers may be
8601 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
8602 + tdep->num_word_regs
8603 + tdep->num_dword_regs
8604 + tdep->num_mmx_regs
8605 + tdep->num_ymm_regs
8607 + tdep->num_ymm_avx512_regs
8608 + tdep->num_zmm_regs));
8610 /* Target description may be changed. */
8611 tdesc = tdep->tdesc;
8613 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
8615 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8616 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
8618 /* Make %al the first pseudo-register. */
8619 tdep->al_regnum = gdbarch_num_regs (gdbarch);
8620 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
8622 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
8623 if (tdep->num_dword_regs)
8625 /* Support dword pseudo-register if it hasn't been disabled. */
8626 tdep->eax_regnum = ymm0_regnum;
8627 ymm0_regnum += tdep->num_dword_regs;
8630 tdep->eax_regnum = -1;
8632 mm0_regnum = ymm0_regnum;
8633 if (tdep->num_ymm_regs)
8635 /* Support YMM pseudo-register if it is available. */
8636 tdep->ymm0_regnum = ymm0_regnum;
8637 mm0_regnum += tdep->num_ymm_regs;
8640 tdep->ymm0_regnum = -1;
8642 if (tdep->num_ymm_avx512_regs)
8644 /* Support YMM16-31 pseudo registers if available. */
8645 tdep->ymm16_regnum = mm0_regnum;
8646 mm0_regnum += tdep->num_ymm_avx512_regs;
8649 tdep->ymm16_regnum = -1;
8651 if (tdep->num_zmm_regs)
8653 /* Support ZMM pseudo-register if it is available. */
8654 tdep->zmm0_regnum = mm0_regnum;
8655 mm0_regnum += tdep->num_zmm_regs;
8658 tdep->zmm0_regnum = -1;
8660 bnd0_regnum = mm0_regnum;
8661 if (tdep->num_mmx_regs != 0)
8663 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8664 tdep->mm0_regnum = mm0_regnum;
8665 bnd0_regnum += tdep->num_mmx_regs;
8668 tdep->mm0_regnum = -1;
8670 if (tdep->bnd0r_regnum > 0)
8671 tdep->bnd0_regnum = bnd0_regnum;
8673 tdep-> bnd0_regnum = -1;
8675 /* Hook in the legacy prologue-based unwinders last (fallback). */
8676 frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind);
8677 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
8678 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
8680 /* If we have a register mapping, enable the generic core file
8681 support, unless it has already been enabled. */
8682 if (tdep->gregset_reg_offset
8683 && !gdbarch_iterate_over_regset_sections_p (gdbarch))
8684 set_gdbarch_iterate_over_regset_sections
8685 (gdbarch, i386_iterate_over_regset_sections);
8687 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
8688 i386_fast_tracepoint_valid_at);
8693 static enum gdb_osabi
8694 i386_coff_osabi_sniffer (bfd *abfd)
8696 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
8697 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
8698 return GDB_OSABI_GO32;
8700 return GDB_OSABI_UNKNOWN;
8704 /* Return the target description for a specified XSAVE feature mask. */
8706 const struct target_desc *
8707 i386_target_description (uint64_t xcr0)
8709 switch (xcr0 & X86_XSTATE_ALL_MASK)
8711 case X86_XSTATE_AVX_MPX_AVX512_MASK:
8712 return tdesc_i386_avx_mpx_avx512;
8713 case X86_XSTATE_AVX_AVX512_MASK:
8714 return tdesc_i386_avx_avx512;
8715 case X86_XSTATE_AVX_MPX_MASK:
8716 return tdesc_i386_avx_mpx;
8717 case X86_XSTATE_MPX_MASK:
8718 return tdesc_i386_mpx;
8719 case X86_XSTATE_AVX_MASK:
8720 return tdesc_i386_avx;
8726 #define MPX_BASE_MASK (~(ULONGEST) 0xfff)
8728 /* Find the bound directory base address. */
8730 static unsigned long
8731 i386_mpx_bd_base (void)
8733 struct regcache *rcache;
8734 struct gdbarch_tdep *tdep;
8736 enum register_status regstatus;
8738 rcache = get_current_regcache ();
8739 tdep = gdbarch_tdep (get_regcache_arch (rcache));
8741 regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret);
8743 if (regstatus != REG_VALID)
8744 error (_("BNDCFGU register invalid, read status %d."), regstatus);
8746 return ret & MPX_BASE_MASK;
8750 i386_mpx_enabled (void)
8752 const struct gdbarch_tdep *tdep = gdbarch_tdep (get_current_arch ());
8753 const struct target_desc *tdesc = tdep->tdesc;
8755 return (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL);
8758 #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */
8759 #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */
8760 #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */
8761 #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */
8763 /* Find the bound table entry given the pointer location and the base
8764 address of the table. */
8767 i386_mpx_get_bt_entry (CORE_ADDR ptr, CORE_ADDR bd_base)
8771 CORE_ADDR mpx_bd_mask, bd_ptr_r_shift, bd_ptr_l_shift;
8772 CORE_ADDR bt_mask, bt_select_r_shift, bt_select_l_shift;
8773 CORE_ADDR bd_entry_addr;
8776 struct gdbarch *gdbarch = get_current_arch ();
8777 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8780 if (gdbarch_ptr_bit (gdbarch) == 64)
8782 mpx_bd_mask = (CORE_ADDR) MPX_BD_MASK;
8783 bd_ptr_r_shift = 20;
8785 bt_select_r_shift = 3;
8786 bt_select_l_shift = 5;
8787 bt_mask = (CORE_ADDR) MPX_BT_MASK;
8789 if ( sizeof (CORE_ADDR) == 4)
8790 error (_("bound table examination not supported\
8791 for 64-bit process with 32-bit GDB"));
8795 mpx_bd_mask = MPX_BD_MASK_32;
8796 bd_ptr_r_shift = 12;
8798 bt_select_r_shift = 2;
8799 bt_select_l_shift = 4;
8800 bt_mask = MPX_BT_MASK_32;
8803 offset1 = ((ptr & mpx_bd_mask) >> bd_ptr_r_shift) << bd_ptr_l_shift;
8804 bd_entry_addr = bd_base + offset1;
8805 bd_entry = read_memory_typed_address (bd_entry_addr, data_ptr_type);
8807 if ((bd_entry & 0x1) == 0)
8808 error (_("Invalid bounds directory entry at %s."),
8809 paddress (get_current_arch (), bd_entry_addr));
8811 /* Clearing status bit. */
8813 bt_addr = bd_entry & ~bt_select_r_shift;
8814 offset2 = ((ptr & bt_mask) >> bt_select_r_shift) << bt_select_l_shift;
8816 return bt_addr + offset2;
8819 /* Print routine for the mpx bounds. */
8822 i386_mpx_print_bounds (const CORE_ADDR bt_entry[4])
8824 struct ui_out *uiout = current_uiout;
8826 struct gdbarch *gdbarch = get_current_arch ();
8827 CORE_ADDR onecompl = ~((CORE_ADDR) 0);
8828 int bounds_in_map = ((~bt_entry[1] == 0 && bt_entry[0] == onecompl) ? 1 : 0);
8830 if (bounds_in_map == 1)
8832 uiout->text ("Null bounds on map:");
8833 uiout->text (" pointer value = ");
8834 uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]);
8840 uiout->text ("{lbound = ");
8841 uiout->field_core_addr ("lower-bound", gdbarch, bt_entry[0]);
8842 uiout->text (", ubound = ");
8844 /* The upper bound is stored in 1's complement. */
8845 uiout->field_core_addr ("upper-bound", gdbarch, ~bt_entry[1]);
8846 uiout->text ("}: pointer value = ");
8847 uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]);
8849 if (gdbarch_ptr_bit (gdbarch) == 64)
8850 size = ( (~(int64_t) bt_entry[1]) - (int64_t) bt_entry[0]);
8852 size = ( ~((int32_t) bt_entry[1]) - (int32_t) bt_entry[0]);
8854 /* In case the bounds are 0x0 and 0xffff... the difference will be -1.
8855 -1 represents in this sense full memory access, and there is no need
8858 size = (size > -1 ? size + 1 : size);
8859 uiout->text (", size = ");
8860 uiout->field_fmt ("size", "%s", plongest (size));
8862 uiout->text (", metadata = ");
8863 uiout->field_core_addr ("metadata", gdbarch, bt_entry[3]);
8868 /* Implement the command "show mpx bound". */
8871 i386_mpx_info_bounds (char *args, int from_tty)
8873 CORE_ADDR bd_base = 0;
8875 CORE_ADDR bt_entry_addr = 0;
8876 CORE_ADDR bt_entry[4];
8878 struct gdbarch *gdbarch = get_current_arch ();
8879 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8881 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386
8882 || !i386_mpx_enabled ())
8884 printf_unfiltered (_("Intel Memory Protection Extensions not "
8885 "supported on this target.\n"));
8891 printf_unfiltered (_("Address of pointer variable expected.\n"));
8895 addr = parse_and_eval_address (args);
8897 bd_base = i386_mpx_bd_base ();
8898 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8900 memset (bt_entry, 0, sizeof (bt_entry));
8902 for (i = 0; i < 4; i++)
8903 bt_entry[i] = read_memory_typed_address (bt_entry_addr
8904 + i * TYPE_LENGTH (data_ptr_type),
8907 i386_mpx_print_bounds (bt_entry);
8910 /* Implement the command "set mpx bound". */
8913 i386_mpx_set_bounds (char *args, int from_tty)
8915 CORE_ADDR bd_base = 0;
8916 CORE_ADDR addr, lower, upper;
8917 CORE_ADDR bt_entry_addr = 0;
8918 CORE_ADDR bt_entry[2];
8919 const char *input = args;
8921 struct gdbarch *gdbarch = get_current_arch ();
8922 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8923 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8925 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386
8926 || !i386_mpx_enabled ())
8927 error (_("Intel Memory Protection Extensions not supported\
8931 error (_("Pointer value expected."));
8933 addr = value_as_address (parse_to_comma_and_eval (&input));
8935 if (input[0] == ',')
8937 if (input[0] == '\0')
8938 error (_("wrong number of arguments: missing lower and upper bound."));
8939 lower = value_as_address (parse_to_comma_and_eval (&input));
8941 if (input[0] == ',')
8943 if (input[0] == '\0')
8944 error (_("Wrong number of arguments; Missing upper bound."));
8945 upper = value_as_address (parse_to_comma_and_eval (&input));
8947 bd_base = i386_mpx_bd_base ();
8948 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8949 for (i = 0; i < 2; i++)
8950 bt_entry[i] = read_memory_typed_address (bt_entry_addr
8951 + i * TYPE_LENGTH (data_ptr_type),
8953 bt_entry[0] = (uint64_t) lower;
8954 bt_entry[1] = ~(uint64_t) upper;
8956 for (i = 0; i < 2; i++)
8957 write_memory_unsigned_integer (bt_entry_addr
8958 + i * TYPE_LENGTH (data_ptr_type),
8959 TYPE_LENGTH (data_ptr_type), byte_order,
8963 static struct cmd_list_element *mpx_set_cmdlist, *mpx_show_cmdlist;
8965 /* Helper function for the CLI commands. */
8968 set_mpx_cmd (char *args, int from_tty)
8970 help_list (mpx_set_cmdlist, "set mpx ", all_commands, gdb_stdout);
8973 /* Helper function for the CLI commands. */
8976 show_mpx_cmd (char *args, int from_tty)
8978 cmd_show_list (mpx_show_cmdlist, from_tty, "");
8981 /* Provide a prototype to silence -Wmissing-prototypes. */
8982 void _initialize_i386_tdep (void);
8985 _initialize_i386_tdep (void)
8987 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
8989 /* Add the variable that controls the disassembly flavor. */
8990 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
8991 &disassembly_flavor, _("\
8992 Set the disassembly flavor."), _("\
8993 Show the disassembly flavor."), _("\
8994 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
8996 NULL, /* FIXME: i18n: */
8997 &setlist, &showlist);
8999 /* Add the variable that controls the convention for returning
9001 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
9002 &struct_convention, _("\
9003 Set the convention for returning small structs."), _("\
9004 Show the convention for returning small structs."), _("\
9005 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
9008 NULL, /* FIXME: i18n: */
9009 &setlist, &showlist);
9011 /* Add "mpx" prefix for the set commands. */
9013 add_prefix_cmd ("mpx", class_support, set_mpx_cmd, _("\
9014 Set Intel Memory Protection Extensions specific variables."),
9015 &mpx_set_cmdlist, "set mpx ",
9016 0 /* allow-unknown */, &setlist);
9018 /* Add "mpx" prefix for the show commands. */
9020 add_prefix_cmd ("mpx", class_support, show_mpx_cmd, _("\
9021 Show Intel Memory Protection Extensions specific variables."),
9022 &mpx_show_cmdlist, "show mpx ",
9023 0 /* allow-unknown */, &showlist);
9025 /* Add "bound" command for the show mpx commands list. */
9027 add_cmd ("bound", no_class, i386_mpx_info_bounds,
9028 "Show the memory bounds for a given array/pointer storage\
9029 in the bound table.",
9032 /* Add "bound" command for the set mpx commands list. */
9034 add_cmd ("bound", no_class, i386_mpx_set_bounds,
9035 "Set the memory bounds for a given array/pointer storage\
9036 in the bound table.",
9039 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
9040 i386_coff_osabi_sniffer);
9042 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
9043 i386_svr4_init_abi);
9044 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
9045 i386_go32_init_abi);
9047 /* Initialize the i386-specific register groups. */
9048 i386_init_reggroups ();
9050 /* Initialize the standard target descriptions. */
9051 initialize_tdesc_i386 ();
9052 initialize_tdesc_i386_mmx ();
9053 initialize_tdesc_i386_avx ();
9054 initialize_tdesc_i386_mpx ();
9055 initialize_tdesc_i386_avx_mpx ();
9056 initialize_tdesc_i386_avx_avx512 ();
9057 initialize_tdesc_i386_avx_mpx_avx512 ();
9059 /* Tell remote stub that we support XML target description. */
9060 register_remote_support_xml ("i386");