1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2015 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
38 #include "reggroups.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "x86-xstate.h"
52 #include "record-full.h"
55 #include "features/i386/i386.c"
56 #include "features/i386/i386-avx.c"
57 #include "features/i386/i386-mpx.c"
58 #include "features/i386/i386-avx512.c"
59 #include "features/i386/i386-mmx.c"
64 #include "stap-probe.h"
65 #include "user-regs.h"
66 #include "cli/cli-utils.h"
67 #include "expression.h"
68 #include "parser-defs.h"
73 static const char *i386_register_names[] =
75 "eax", "ecx", "edx", "ebx",
76 "esp", "ebp", "esi", "edi",
77 "eip", "eflags", "cs", "ss",
78 "ds", "es", "fs", "gs",
79 "st0", "st1", "st2", "st3",
80 "st4", "st5", "st6", "st7",
81 "fctrl", "fstat", "ftag", "fiseg",
82 "fioff", "foseg", "fooff", "fop",
83 "xmm0", "xmm1", "xmm2", "xmm3",
84 "xmm4", "xmm5", "xmm6", "xmm7",
88 static const char *i386_zmm_names[] =
90 "zmm0", "zmm1", "zmm2", "zmm3",
91 "zmm4", "zmm5", "zmm6", "zmm7"
94 static const char *i386_zmmh_names[] =
96 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
97 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
100 static const char *i386_k_names[] =
102 "k0", "k1", "k2", "k3",
103 "k4", "k5", "k6", "k7"
106 static const char *i386_ymm_names[] =
108 "ymm0", "ymm1", "ymm2", "ymm3",
109 "ymm4", "ymm5", "ymm6", "ymm7",
112 static const char *i386_ymmh_names[] =
114 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
115 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
118 static const char *i386_mpx_names[] =
120 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
123 /* Register names for MPX pseudo-registers. */
125 static const char *i386_bnd_names[] =
127 "bnd0", "bnd1", "bnd2", "bnd3"
130 /* Register names for MMX pseudo-registers. */
132 static const char *i386_mmx_names[] =
134 "mm0", "mm1", "mm2", "mm3",
135 "mm4", "mm5", "mm6", "mm7"
138 /* Register names for byte pseudo-registers. */
140 static const char *i386_byte_names[] =
142 "al", "cl", "dl", "bl",
143 "ah", "ch", "dh", "bh"
146 /* Register names for word pseudo-registers. */
148 static const char *i386_word_names[] =
150 "ax", "cx", "dx", "bx",
154 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
155 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
156 we have 16 upper ZMM regs that have to be handled differently. */
158 const int num_lower_zmm_regs = 16;
163 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
165 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
166 int mm0_regnum = tdep->mm0_regnum;
171 regnum -= mm0_regnum;
172 return regnum >= 0 && regnum < tdep->num_mmx_regs;
178 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
180 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
182 regnum -= tdep->al_regnum;
183 return regnum >= 0 && regnum < tdep->num_byte_regs;
189 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
191 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
193 regnum -= tdep->ax_regnum;
194 return regnum >= 0 && regnum < tdep->num_word_regs;
197 /* Dword register? */
200 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
202 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
203 int eax_regnum = tdep->eax_regnum;
208 regnum -= eax_regnum;
209 return regnum >= 0 && regnum < tdep->num_dword_regs;
212 /* AVX512 register? */
215 i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum)
217 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
218 int zmm0h_regnum = tdep->zmm0h_regnum;
220 if (zmm0h_regnum < 0)
223 regnum -= zmm0h_regnum;
224 return regnum >= 0 && regnum < tdep->num_zmm_regs;
228 i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum)
230 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
231 int zmm0_regnum = tdep->zmm0_regnum;
236 regnum -= zmm0_regnum;
237 return regnum >= 0 && regnum < tdep->num_zmm_regs;
241 i386_k_regnum_p (struct gdbarch *gdbarch, int regnum)
243 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
244 int k0_regnum = tdep->k0_regnum;
250 return regnum >= 0 && regnum < I387_NUM_K_REGS;
254 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
256 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
257 int ymm0h_regnum = tdep->ymm0h_regnum;
259 if (ymm0h_regnum < 0)
262 regnum -= ymm0h_regnum;
263 return regnum >= 0 && regnum < tdep->num_ymm_regs;
269 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
271 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
272 int ymm0_regnum = tdep->ymm0_regnum;
277 regnum -= ymm0_regnum;
278 return regnum >= 0 && regnum < tdep->num_ymm_regs;
282 i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
284 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
285 int ymm16h_regnum = tdep->ymm16h_regnum;
287 if (ymm16h_regnum < 0)
290 regnum -= ymm16h_regnum;
291 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
295 i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
297 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
298 int ymm16_regnum = tdep->ymm16_regnum;
300 if (ymm16_regnum < 0)
303 regnum -= ymm16_regnum;
304 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
310 i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum)
312 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
313 int bnd0_regnum = tdep->bnd0_regnum;
318 regnum -= bnd0_regnum;
319 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
325 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
327 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
328 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
330 if (num_xmm_regs == 0)
333 regnum -= I387_XMM0_REGNUM (tdep);
334 return regnum >= 0 && regnum < num_xmm_regs;
337 /* XMM_512 register? */
340 i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
342 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
343 int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep);
345 if (num_xmm_avx512_regs == 0)
348 regnum -= I387_XMM16_REGNUM (tdep);
349 return regnum >= 0 && regnum < num_xmm_avx512_regs;
353 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
355 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
357 if (I387_NUM_XMM_REGS (tdep) == 0)
360 return (regnum == I387_MXCSR_REGNUM (tdep));
366 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
368 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
370 if (I387_ST0_REGNUM (tdep) < 0)
373 return (I387_ST0_REGNUM (tdep) <= regnum
374 && regnum < I387_FCTRL_REGNUM (tdep));
378 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
380 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
382 if (I387_ST0_REGNUM (tdep) < 0)
385 return (I387_FCTRL_REGNUM (tdep) <= regnum
386 && regnum < I387_XMM0_REGNUM (tdep));
389 /* BNDr (raw) register? */
392 i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum)
394 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
396 if (I387_BND0R_REGNUM (tdep) < 0)
399 regnum -= tdep->bnd0r_regnum;
400 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
403 /* BND control register? */
406 i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum)
408 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
410 if (I387_BNDCFGU_REGNUM (tdep) < 0)
413 regnum -= I387_BNDCFGU_REGNUM (tdep);
414 return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS;
417 /* Return the name of register REGNUM, or the empty string if it is
418 an anonymous register. */
421 i386_register_name (struct gdbarch *gdbarch, int regnum)
423 /* Hide the upper YMM registers. */
424 if (i386_ymmh_regnum_p (gdbarch, regnum))
427 /* Hide the upper YMM16-31 registers. */
428 if (i386_ymmh_avx512_regnum_p (gdbarch, regnum))
431 /* Hide the upper ZMM registers. */
432 if (i386_zmmh_regnum_p (gdbarch, regnum))
435 return tdesc_register_name (gdbarch, regnum);
438 /* Return the name of register REGNUM. */
441 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
443 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
444 if (i386_bnd_regnum_p (gdbarch, regnum))
445 return i386_bnd_names[regnum - tdep->bnd0_regnum];
446 if (i386_mmx_regnum_p (gdbarch, regnum))
447 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
448 else if (i386_ymm_regnum_p (gdbarch, regnum))
449 return i386_ymm_names[regnum - tdep->ymm0_regnum];
450 else if (i386_zmm_regnum_p (gdbarch, regnum))
451 return i386_zmm_names[regnum - tdep->zmm0_regnum];
452 else if (i386_byte_regnum_p (gdbarch, regnum))
453 return i386_byte_names[regnum - tdep->al_regnum];
454 else if (i386_word_regnum_p (gdbarch, regnum))
455 return i386_word_names[regnum - tdep->ax_regnum];
457 internal_error (__FILE__, __LINE__, _("invalid regnum"));
460 /* Convert a dbx register number REG to the appropriate register
461 number used by GDB. */
464 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
466 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
468 /* This implements what GCC calls the "default" register map
469 (dbx_register_map[]). */
471 if (reg >= 0 && reg <= 7)
473 /* General-purpose registers. The debug info calls %ebp
474 register 4, and %esp register 5. */
481 else if (reg >= 12 && reg <= 19)
483 /* Floating-point registers. */
484 return reg - 12 + I387_ST0_REGNUM (tdep);
486 else if (reg >= 21 && reg <= 28)
489 int ymm0_regnum = tdep->ymm0_regnum;
492 && i386_xmm_regnum_p (gdbarch, reg))
493 return reg - 21 + ymm0_regnum;
495 return reg - 21 + I387_XMM0_REGNUM (tdep);
497 else if (reg >= 29 && reg <= 36)
500 return reg - 29 + I387_MM0_REGNUM (tdep);
503 /* This will hopefully provoke a warning. */
504 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
507 /* Convert SVR4 register number REG to the appropriate register number
511 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
513 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
515 /* This implements the GCC register map that tries to be compatible
516 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
518 /* The SVR4 register numbering includes %eip and %eflags, and
519 numbers the floating point registers differently. */
520 if (reg >= 0 && reg <= 9)
522 /* General-purpose registers. */
525 else if (reg >= 11 && reg <= 18)
527 /* Floating-point registers. */
528 return reg - 11 + I387_ST0_REGNUM (tdep);
530 else if (reg >= 21 && reg <= 36)
532 /* The SSE and MMX registers have the same numbers as with dbx. */
533 return i386_dbx_reg_to_regnum (gdbarch, reg);
538 case 37: return I387_FCTRL_REGNUM (tdep);
539 case 38: return I387_FSTAT_REGNUM (tdep);
540 case 39: return I387_MXCSR_REGNUM (tdep);
541 case 40: return I386_ES_REGNUM;
542 case 41: return I386_CS_REGNUM;
543 case 42: return I386_SS_REGNUM;
544 case 43: return I386_DS_REGNUM;
545 case 44: return I386_FS_REGNUM;
546 case 45: return I386_GS_REGNUM;
549 /* This will hopefully provoke a warning. */
550 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
555 /* This is the variable that is set with "set disassembly-flavor", and
556 its legitimate values. */
557 static const char att_flavor[] = "att";
558 static const char intel_flavor[] = "intel";
559 static const char *const valid_flavors[] =
565 static const char *disassembly_flavor = att_flavor;
568 /* Use the program counter to determine the contents and size of a
569 breakpoint instruction. Return a pointer to a string of bytes that
570 encode a breakpoint instruction, store the length of the string in
571 *LEN and optionally adjust *PC to point to the correct memory
572 location for inserting the breakpoint.
574 On the i386 we have a single breakpoint that fits in a single byte
575 and can be inserted anywhere.
577 This function is 64-bit safe. */
579 static const gdb_byte *
580 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
582 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */
584 *len = sizeof (break_insn);
588 /* Displaced instruction handling. */
590 /* Skip the legacy instruction prefixes in INSN.
591 Not all prefixes are valid for any particular insn
592 but we needn't care, the insn will fault if it's invalid.
593 The result is a pointer to the first opcode byte,
594 or NULL if we run off the end of the buffer. */
597 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
599 gdb_byte *end = insn + max_len;
605 case DATA_PREFIX_OPCODE:
606 case ADDR_PREFIX_OPCODE:
607 case CS_PREFIX_OPCODE:
608 case DS_PREFIX_OPCODE:
609 case ES_PREFIX_OPCODE:
610 case FS_PREFIX_OPCODE:
611 case GS_PREFIX_OPCODE:
612 case SS_PREFIX_OPCODE:
613 case LOCK_PREFIX_OPCODE:
614 case REPE_PREFIX_OPCODE:
615 case REPNE_PREFIX_OPCODE:
627 i386_absolute_jmp_p (const gdb_byte *insn)
629 /* jmp far (absolute address in operand). */
635 /* jump near, absolute indirect (/4). */
636 if ((insn[1] & 0x38) == 0x20)
639 /* jump far, absolute indirect (/5). */
640 if ((insn[1] & 0x38) == 0x28)
647 /* Return non-zero if INSN is a jump, zero otherwise. */
650 i386_jmp_p (const gdb_byte *insn)
652 /* jump short, relative. */
656 /* jump near, relative. */
660 return i386_absolute_jmp_p (insn);
664 i386_absolute_call_p (const gdb_byte *insn)
666 /* call far, absolute. */
672 /* Call near, absolute indirect (/2). */
673 if ((insn[1] & 0x38) == 0x10)
676 /* Call far, absolute indirect (/3). */
677 if ((insn[1] & 0x38) == 0x18)
685 i386_ret_p (const gdb_byte *insn)
689 case 0xc2: /* ret near, pop N bytes. */
690 case 0xc3: /* ret near */
691 case 0xca: /* ret far, pop N bytes. */
692 case 0xcb: /* ret far */
693 case 0xcf: /* iret */
702 i386_call_p (const gdb_byte *insn)
704 if (i386_absolute_call_p (insn))
707 /* call near, relative. */
714 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
715 length in bytes. Otherwise, return zero. */
718 i386_syscall_p (const gdb_byte *insn, int *lengthp)
720 /* Is it 'int $0x80'? */
721 if ((insn[0] == 0xcd && insn[1] == 0x80)
722 /* Or is it 'sysenter'? */
723 || (insn[0] == 0x0f && insn[1] == 0x34)
724 /* Or is it 'syscall'? */
725 || (insn[0] == 0x0f && insn[1] == 0x05))
734 /* The gdbarch insn_is_call method. */
737 i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
739 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
741 read_code (addr, buf, I386_MAX_INSN_LEN);
742 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
744 return i386_call_p (insn);
747 /* The gdbarch insn_is_ret method. */
750 i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
752 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
754 read_code (addr, buf, I386_MAX_INSN_LEN);
755 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
757 return i386_ret_p (insn);
760 /* The gdbarch insn_is_jump method. */
763 i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
765 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
767 read_code (addr, buf, I386_MAX_INSN_LEN);
768 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
770 return i386_jmp_p (insn);
773 /* Some kernels may run one past a syscall insn, so we have to cope.
774 Otherwise this is just simple_displaced_step_copy_insn. */
776 struct displaced_step_closure *
777 i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
778 CORE_ADDR from, CORE_ADDR to,
779 struct regcache *regs)
781 size_t len = gdbarch_max_insn_length (gdbarch);
782 gdb_byte *buf = xmalloc (len);
784 read_memory (from, buf, len);
786 /* GDB may get control back after the insn after the syscall.
787 Presumably this is a kernel bug.
788 If this is a syscall, make sure there's a nop afterwards. */
793 insn = i386_skip_prefixes (buf, len);
794 if (insn != NULL && i386_syscall_p (insn, &syscall_length))
795 insn[syscall_length] = NOP_OPCODE;
798 write_memory (to, buf, len);
802 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
803 paddress (gdbarch, from), paddress (gdbarch, to));
804 displaced_step_dump_bytes (gdb_stdlog, buf, len);
807 return (struct displaced_step_closure *) buf;
810 /* Fix up the state of registers and memory after having single-stepped
811 a displaced instruction. */
814 i386_displaced_step_fixup (struct gdbarch *gdbarch,
815 struct displaced_step_closure *closure,
816 CORE_ADDR from, CORE_ADDR to,
817 struct regcache *regs)
819 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
821 /* The offset we applied to the instruction's address.
822 This could well be negative (when viewed as a signed 32-bit
823 value), but ULONGEST won't reflect that, so take care when
825 ULONGEST insn_offset = to - from;
827 /* Since we use simple_displaced_step_copy_insn, our closure is a
828 copy of the instruction. */
829 gdb_byte *insn = (gdb_byte *) closure;
830 /* The start of the insn, needed in case we see some prefixes. */
831 gdb_byte *insn_start = insn;
834 fprintf_unfiltered (gdb_stdlog,
835 "displaced: fixup (%s, %s), "
836 "insn = 0x%02x 0x%02x ...\n",
837 paddress (gdbarch, from), paddress (gdbarch, to),
840 /* The list of issues to contend with here is taken from
841 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
842 Yay for Free Software! */
844 /* Relocate the %eip, if necessary. */
846 /* The instruction recognizers we use assume any leading prefixes
847 have been skipped. */
849 /* This is the size of the buffer in closure. */
850 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
851 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
852 /* If there are too many prefixes, just ignore the insn.
853 It will fault when run. */
858 /* Except in the case of absolute or indirect jump or call
859 instructions, or a return instruction, the new eip is relative to
860 the displaced instruction; make it relative. Well, signal
861 handler returns don't need relocation either, but we use the
862 value of %eip to recognize those; see below. */
863 if (! i386_absolute_jmp_p (insn)
864 && ! i386_absolute_call_p (insn)
865 && ! i386_ret_p (insn))
870 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
872 /* A signal trampoline system call changes the %eip, resuming
873 execution of the main program after the signal handler has
874 returned. That makes them like 'return' instructions; we
875 shouldn't relocate %eip.
877 But most system calls don't, and we do need to relocate %eip.
879 Our heuristic for distinguishing these cases: if stepping
880 over the system call instruction left control directly after
881 the instruction, the we relocate --- control almost certainly
882 doesn't belong in the displaced copy. Otherwise, we assume
883 the instruction has put control where it belongs, and leave
884 it unrelocated. Goodness help us if there are PC-relative
886 if (i386_syscall_p (insn, &insn_len)
887 && orig_eip != to + (insn - insn_start) + insn_len
888 /* GDB can get control back after the insn after the syscall.
889 Presumably this is a kernel bug.
890 i386_displaced_step_copy_insn ensures its a nop,
891 we add one to the length for it. */
892 && orig_eip != to + (insn - insn_start) + insn_len + 1)
895 fprintf_unfiltered (gdb_stdlog,
896 "displaced: syscall changed %%eip; "
901 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
903 /* If we just stepped over a breakpoint insn, we don't backup
904 the pc on purpose; this is to match behaviour without
907 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
910 fprintf_unfiltered (gdb_stdlog,
912 "relocated %%eip from %s to %s\n",
913 paddress (gdbarch, orig_eip),
914 paddress (gdbarch, eip));
918 /* If the instruction was PUSHFL, then the TF bit will be set in the
919 pushed value, and should be cleared. We'll leave this for later,
920 since GDB already messes up the TF flag when stepping over a
923 /* If the instruction was a call, the return address now atop the
924 stack is the address following the copied instruction. We need
925 to make it the address following the original instruction. */
926 if (i386_call_p (insn))
930 const ULONGEST retaddr_len = 4;
932 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
933 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
934 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
935 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
938 fprintf_unfiltered (gdb_stdlog,
939 "displaced: relocated return addr at %s to %s\n",
940 paddress (gdbarch, esp),
941 paddress (gdbarch, retaddr));
946 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
948 target_write_memory (*to, buf, len);
953 i386_relocate_instruction (struct gdbarch *gdbarch,
954 CORE_ADDR *to, CORE_ADDR oldloc)
956 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
957 gdb_byte buf[I386_MAX_INSN_LEN];
958 int offset = 0, rel32, newrel;
960 gdb_byte *insn = buf;
962 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
964 insn_length = gdb_buffered_insn_length (gdbarch, insn,
965 I386_MAX_INSN_LEN, oldloc);
967 /* Get past the prefixes. */
968 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
970 /* Adjust calls with 32-bit relative addresses as push/jump, with
971 the address pushed being the location where the original call in
972 the user program would return to. */
975 gdb_byte push_buf[16];
976 unsigned int ret_addr;
978 /* Where "ret" in the original code will return to. */
979 ret_addr = oldloc + insn_length;
980 push_buf[0] = 0x68; /* pushq $... */
981 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
983 append_insns (to, 5, push_buf);
985 /* Convert the relative call to a relative jump. */
988 /* Adjust the destination offset. */
989 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
990 newrel = (oldloc - *to) + rel32;
991 store_signed_integer (insn + 1, 4, byte_order, newrel);
994 fprintf_unfiltered (gdb_stdlog,
995 "Adjusted insn rel32=%s at %s to"
997 hex_string (rel32), paddress (gdbarch, oldloc),
998 hex_string (newrel), paddress (gdbarch, *to));
1000 /* Write the adjusted jump into its displaced location. */
1001 append_insns (to, 5, insn);
1005 /* Adjust jumps with 32-bit relative addresses. Calls are already
1007 if (insn[0] == 0xe9)
1009 /* Adjust conditional jumps. */
1010 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1015 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1016 newrel = (oldloc - *to) + rel32;
1017 store_signed_integer (insn + offset, 4, byte_order, newrel);
1018 if (debug_displaced)
1019 fprintf_unfiltered (gdb_stdlog,
1020 "Adjusted insn rel32=%s at %s to"
1021 " rel32=%s at %s\n",
1022 hex_string (rel32), paddress (gdbarch, oldloc),
1023 hex_string (newrel), paddress (gdbarch, *to));
1026 /* Write the adjusted instructions into their displaced
1028 append_insns (to, insn_length, buf);
1032 #ifdef I386_REGNO_TO_SYMMETRY
1033 #error "The Sequent Symmetry is no longer supported."
1036 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1037 and %esp "belong" to the calling function. Therefore these
1038 registers should be saved if they're going to be modified. */
1040 /* The maximum number of saved registers. This should include all
1041 registers mentioned above, and %eip. */
1042 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1044 struct i386_frame_cache
1052 /* Saved registers. */
1053 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
1058 /* Stack space reserved for local variables. */
1062 /* Allocate and initialize a frame cache. */
1064 static struct i386_frame_cache *
1065 i386_alloc_frame_cache (void)
1067 struct i386_frame_cache *cache;
1070 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
1075 cache->sp_offset = -4;
1078 /* Saved registers. We initialize these to -1 since zero is a valid
1079 offset (that's where %ebp is supposed to be stored). */
1080 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1081 cache->saved_regs[i] = -1;
1082 cache->saved_sp = 0;
1083 cache->saved_sp_reg = -1;
1084 cache->pc_in_eax = 0;
1086 /* Frameless until proven otherwise. */
1092 /* If the instruction at PC is a jump, return the address of its
1093 target. Otherwise, return PC. */
1096 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
1098 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1103 if (target_read_code (pc, &op, 1))
1110 op = read_code_unsigned_integer (pc + 1, 1, byte_order);
1116 /* Relative jump: if data16 == 0, disp32, else disp16. */
1119 delta = read_memory_integer (pc + 2, 2, byte_order);
1121 /* Include the size of the jmp instruction (including the
1127 delta = read_memory_integer (pc + 1, 4, byte_order);
1129 /* Include the size of the jmp instruction. */
1134 /* Relative jump, disp8 (ignore data16). */
1135 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
1137 delta += data16 + 2;
1144 /* Check whether PC points at a prologue for a function returning a
1145 structure or union. If so, it updates CACHE and returns the
1146 address of the first instruction after the code sequence that
1147 removes the "hidden" argument from the stack or CURRENT_PC,
1148 whichever is smaller. Otherwise, return PC. */
1151 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
1152 struct i386_frame_cache *cache)
1154 /* Functions that return a structure or union start with:
1157 xchgl %eax, (%esp) 0x87 0x04 0x24
1158 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1160 (the System V compiler puts out the second `xchg' instruction,
1161 and the assembler doesn't try to optimize it, so the 'sib' form
1162 gets generated). This sequence is used to get the address of the
1163 return buffer for a function that returns a structure. */
1164 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
1165 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
1169 if (current_pc <= pc)
1172 if (target_read_code (pc, &op, 1))
1175 if (op != 0x58) /* popl %eax */
1178 if (target_read_code (pc + 1, buf, 4))
1181 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
1184 if (current_pc == pc)
1186 cache->sp_offset += 4;
1190 if (current_pc == pc + 1)
1192 cache->pc_in_eax = 1;
1196 if (buf[1] == proto1[1])
1203 i386_skip_probe (CORE_ADDR pc)
1205 /* A function may start with
1219 if (target_read_code (pc, &op, 1))
1222 if (op == 0x68 || op == 0x6a)
1226 /* Skip past the `pushl' instruction; it has either a one-byte or a
1227 four-byte operand, depending on the opcode. */
1233 /* Read the following 8 bytes, which should be `call _probe' (6
1234 bytes) followed by `addl $4,%esp' (2 bytes). */
1235 read_memory (pc + delta, buf, sizeof (buf));
1236 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
1237 pc += delta + sizeof (buf);
1243 /* GCC 4.1 and later, can put code in the prologue to realign the
1244 stack pointer. Check whether PC points to such code, and update
1245 CACHE accordingly. Return the first instruction after the code
1246 sequence or CURRENT_PC, whichever is smaller. If we don't
1247 recognize the code, return PC. */
1250 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1251 struct i386_frame_cache *cache)
1253 /* There are 2 code sequences to re-align stack before the frame
1256 1. Use a caller-saved saved register:
1262 2. Use a callee-saved saved register:
1269 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1271 0x83 0xe4 0xf0 andl $-16, %esp
1272 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1277 int offset, offset_and;
1278 static int regnums[8] = {
1279 I386_EAX_REGNUM, /* %eax */
1280 I386_ECX_REGNUM, /* %ecx */
1281 I386_EDX_REGNUM, /* %edx */
1282 I386_EBX_REGNUM, /* %ebx */
1283 I386_ESP_REGNUM, /* %esp */
1284 I386_EBP_REGNUM, /* %ebp */
1285 I386_ESI_REGNUM, /* %esi */
1286 I386_EDI_REGNUM /* %edi */
1289 if (target_read_code (pc, buf, sizeof buf))
1292 /* Check caller-saved saved register. The first instruction has
1293 to be "leal 4(%esp), %reg". */
1294 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1296 /* MOD must be binary 10 and R/M must be binary 100. */
1297 if ((buf[1] & 0xc7) != 0x44)
1300 /* REG has register number. */
1301 reg = (buf[1] >> 3) & 7;
1306 /* Check callee-saved saved register. The first instruction
1307 has to be "pushl %reg". */
1308 if ((buf[0] & 0xf8) != 0x50)
1314 /* The next instruction has to be "leal 8(%esp), %reg". */
1315 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1318 /* MOD must be binary 10 and R/M must be binary 100. */
1319 if ((buf[2] & 0xc7) != 0x44)
1322 /* REG has register number. Registers in pushl and leal have to
1324 if (reg != ((buf[2] >> 3) & 7))
1330 /* Rigister can't be %esp nor %ebp. */
1331 if (reg == 4 || reg == 5)
1334 /* The next instruction has to be "andl $-XXX, %esp". */
1335 if (buf[offset + 1] != 0xe4
1336 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1339 offset_and = offset;
1340 offset += buf[offset] == 0x81 ? 6 : 3;
1342 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1343 0xfc. REG must be binary 110 and MOD must be binary 01. */
1344 if (buf[offset] != 0xff
1345 || buf[offset + 2] != 0xfc
1346 || (buf[offset + 1] & 0xf8) != 0x70)
1349 /* R/M has register. Registers in leal and pushl have to be the
1351 if (reg != (buf[offset + 1] & 7))
1354 if (current_pc > pc + offset_and)
1355 cache->saved_sp_reg = regnums[reg];
1357 return min (pc + offset + 3, current_pc);
1360 /* Maximum instruction length we need to handle. */
1361 #define I386_MAX_MATCHED_INSN_LEN 6
1363 /* Instruction description. */
1367 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
1368 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
1371 /* Return whether instruction at PC matches PATTERN. */
1374 i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern)
1378 if (target_read_code (pc, &op, 1))
1381 if ((op & pattern.mask[0]) == pattern.insn[0])
1383 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1384 int insn_matched = 1;
1387 gdb_assert (pattern.len > 1);
1388 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN);
1390 if (target_read_code (pc + 1, buf, pattern.len - 1))
1393 for (i = 1; i < pattern.len; i++)
1395 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i])
1398 return insn_matched;
1403 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1404 the first instruction description that matches. Otherwise, return
1407 static struct i386_insn *
1408 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns)
1410 struct i386_insn *pattern;
1412 for (pattern = insn_patterns; pattern->len > 0; pattern++)
1414 if (i386_match_pattern (pc, *pattern))
1421 /* Return whether PC points inside a sequence of instructions that
1422 matches INSN_PATTERNS. */
1425 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns)
1427 CORE_ADDR current_pc;
1429 struct i386_insn *insn;
1431 insn = i386_match_insn (pc, insn_patterns);
1436 ix = insn - insn_patterns;
1437 for (i = ix - 1; i >= 0; i--)
1439 current_pc -= insn_patterns[i].len;
1441 if (!i386_match_pattern (current_pc, insn_patterns[i]))
1445 current_pc = pc + insn->len;
1446 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++)
1448 if (!i386_match_pattern (current_pc, *insn))
1451 current_pc += insn->len;
1457 /* Some special instructions that might be migrated by GCC into the
1458 part of the prologue that sets up the new stack frame. Because the
1459 stack frame hasn't been setup yet, no registers have been saved
1460 yet, and only the scratch registers %eax, %ecx and %edx can be
1463 struct i386_insn i386_frame_setup_skip_insns[] =
1465 /* Check for `movb imm8, r' and `movl imm32, r'.
1467 ??? Should we handle 16-bit operand-sizes here? */
1469 /* `movb imm8, %al' and `movb imm8, %ah' */
1470 /* `movb imm8, %cl' and `movb imm8, %ch' */
1471 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1472 /* `movb imm8, %dl' and `movb imm8, %dh' */
1473 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1474 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1475 { 5, { 0xb8 }, { 0xfe } },
1476 /* `movl imm32, %edx' */
1477 { 5, { 0xba }, { 0xff } },
1479 /* Check for `mov imm32, r32'. Note that there is an alternative
1480 encoding for `mov m32, %eax'.
1482 ??? Should we handle SIB adressing here?
1483 ??? Should we handle 16-bit operand-sizes here? */
1485 /* `movl m32, %eax' */
1486 { 5, { 0xa1 }, { 0xff } },
1487 /* `movl m32, %eax' and `mov; m32, %ecx' */
1488 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1489 /* `movl m32, %edx' */
1490 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1492 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1493 Because of the symmetry, there are actually two ways to encode
1494 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1495 opcode bytes 0x31 and 0x33 for `xorl'. */
1497 /* `subl %eax, %eax' */
1498 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1499 /* `subl %ecx, %ecx' */
1500 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1501 /* `subl %edx, %edx' */
1502 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1503 /* `xorl %eax, %eax' */
1504 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1505 /* `xorl %ecx, %ecx' */
1506 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1507 /* `xorl %edx, %edx' */
1508 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1513 /* Check whether PC points to a no-op instruction. */
1515 i386_skip_noop (CORE_ADDR pc)
1520 if (target_read_code (pc, &op, 1))
1526 /* Ignore `nop' instruction. */
1530 if (target_read_code (pc, &op, 1))
1534 /* Ignore no-op instruction `mov %edi, %edi'.
1535 Microsoft system dlls often start with
1536 a `mov %edi,%edi' instruction.
1537 The 5 bytes before the function start are
1538 filled with `nop' instructions.
1539 This pattern can be used for hot-patching:
1540 The `mov %edi, %edi' instruction can be replaced by a
1541 near jump to the location of the 5 `nop' instructions
1542 which can be replaced by a 32-bit jump to anywhere
1543 in the 32-bit address space. */
1545 else if (op == 0x8b)
1547 if (target_read_code (pc + 1, &op, 1))
1553 if (target_read_code (pc, &op, 1))
1563 /* Check whether PC points at a code that sets up a new stack frame.
1564 If so, it updates CACHE and returns the address of the first
1565 instruction after the sequence that sets up the frame or LIMIT,
1566 whichever is smaller. If we don't recognize the code, return PC. */
1569 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1570 CORE_ADDR pc, CORE_ADDR limit,
1571 struct i386_frame_cache *cache)
1573 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1574 struct i386_insn *insn;
1581 if (target_read_code (pc, &op, 1))
1584 if (op == 0x55) /* pushl %ebp */
1586 /* Take into account that we've executed the `pushl %ebp' that
1587 starts this instruction sequence. */
1588 cache->saved_regs[I386_EBP_REGNUM] = 0;
1589 cache->sp_offset += 4;
1592 /* If that's all, return now. */
1596 /* Check for some special instructions that might be migrated by
1597 GCC into the prologue and skip them. At this point in the
1598 prologue, code should only touch the scratch registers %eax,
1599 %ecx and %edx, so while the number of posibilities is sheer,
1602 Make sure we only skip these instructions if we later see the
1603 `movl %esp, %ebp' that actually sets up the frame. */
1604 while (pc + skip < limit)
1606 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1613 /* If that's all, return now. */
1614 if (limit <= pc + skip)
1617 if (target_read_code (pc + skip, &op, 1))
1620 /* The i386 prologue looks like
1626 and a different prologue can be generated for atom.
1630 lea -0x10(%esp),%esp
1632 We handle both of them here. */
1636 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1638 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1644 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1649 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1650 if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order)
1659 /* OK, we actually have a frame. We just don't know how large
1660 it is yet. Set its size to zero. We'll adjust it if
1661 necessary. We also now commit to skipping the special
1662 instructions mentioned before. */
1665 /* If that's all, return now. */
1669 /* Check for stack adjustment
1675 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1676 reg, so we don't have to worry about a data16 prefix. */
1677 if (target_read_code (pc, &op, 1))
1681 /* `subl' with 8-bit immediate. */
1682 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1683 /* Some instruction starting with 0x83 other than `subl'. */
1686 /* `subl' with signed 8-bit immediate (though it wouldn't
1687 make sense to be negative). */
1688 cache->locals = read_code_integer (pc + 2, 1, byte_order);
1691 else if (op == 0x81)
1693 /* Maybe it is `subl' with a 32-bit immediate. */
1694 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1695 /* Some instruction starting with 0x81 other than `subl'. */
1698 /* It is `subl' with a 32-bit immediate. */
1699 cache->locals = read_code_integer (pc + 2, 4, byte_order);
1702 else if (op == 0x8d)
1704 /* The ModR/M byte is 0x64. */
1705 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64)
1707 /* 'lea' with 8-bit displacement. */
1708 cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order);
1713 /* Some instruction other than `subl' nor 'lea'. */
1717 else if (op == 0xc8) /* enter */
1719 cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order);
1726 /* Check whether PC points at code that saves registers on the stack.
1727 If so, it updates CACHE and returns the address of the first
1728 instruction after the register saves or CURRENT_PC, whichever is
1729 smaller. Otherwise, return PC. */
1732 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1733 struct i386_frame_cache *cache)
1735 CORE_ADDR offset = 0;
1739 if (cache->locals > 0)
1740 offset -= cache->locals;
1741 for (i = 0; i < 8 && pc < current_pc; i++)
1743 if (target_read_code (pc, &op, 1))
1745 if (op < 0x50 || op > 0x57)
1749 cache->saved_regs[op - 0x50] = offset;
1750 cache->sp_offset += 4;
1757 /* Do a full analysis of the prologue at PC and update CACHE
1758 accordingly. Bail out early if CURRENT_PC is reached. Return the
1759 address where the analysis stopped.
1761 We handle these cases:
1763 The startup sequence can be at the start of the function, or the
1764 function can start with a branch to startup code at the end.
1766 %ebp can be set up with either the 'enter' instruction, or "pushl
1767 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1768 once used in the System V compiler).
1770 Local space is allocated just below the saved %ebp by either the
1771 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1772 16-bit unsigned argument for space to allocate, and the 'addl'
1773 instruction could have either a signed byte, or 32-bit immediate.
1775 Next, the registers used by this function are pushed. With the
1776 System V compiler they will always be in the order: %edi, %esi,
1777 %ebx (and sometimes a harmless bug causes it to also save but not
1778 restore %eax); however, the code below is willing to see the pushes
1779 in any order, and will handle up to 8 of them.
1781 If the setup sequence is at the end of the function, then the next
1782 instruction will be a branch back to the start. */
1785 i386_analyze_prologue (struct gdbarch *gdbarch,
1786 CORE_ADDR pc, CORE_ADDR current_pc,
1787 struct i386_frame_cache *cache)
1789 pc = i386_skip_noop (pc);
1790 pc = i386_follow_jump (gdbarch, pc);
1791 pc = i386_analyze_struct_return (pc, current_pc, cache);
1792 pc = i386_skip_probe (pc);
1793 pc = i386_analyze_stack_align (pc, current_pc, cache);
1794 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1795 return i386_analyze_register_saves (pc, current_pc, cache);
1798 /* Return PC of first real instruction. */
1801 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1803 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1805 static gdb_byte pic_pat[6] =
1807 0xe8, 0, 0, 0, 0, /* call 0x0 */
1808 0x5b, /* popl %ebx */
1810 struct i386_frame_cache cache;
1814 CORE_ADDR func_addr;
1816 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
1818 CORE_ADDR post_prologue_pc
1819 = skip_prologue_using_sal (gdbarch, func_addr);
1820 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
1822 /* Clang always emits a line note before the prologue and another
1823 one after. We trust clang to emit usable line notes. */
1824 if (post_prologue_pc
1826 && COMPUNIT_PRODUCER (cust) != NULL
1827 && startswith (COMPUNIT_PRODUCER (cust), "clang ")))
1828 return max (start_pc, post_prologue_pc);
1832 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1833 if (cache.locals < 0)
1836 /* Found valid frame setup. */
1838 /* The native cc on SVR4 in -K PIC mode inserts the following code
1839 to get the address of the global offset table (GOT) into register
1844 movl %ebx,x(%ebp) (optional)
1847 This code is with the rest of the prologue (at the end of the
1848 function), so we have to skip it to get to the first real
1849 instruction at the start of the function. */
1851 for (i = 0; i < 6; i++)
1853 if (target_read_code (pc + i, &op, 1))
1856 if (pic_pat[i] != op)
1863 if (target_read_code (pc + delta, &op, 1))
1866 if (op == 0x89) /* movl %ebx, x(%ebp) */
1868 op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order);
1870 if (op == 0x5d) /* One byte offset from %ebp. */
1872 else if (op == 0x9d) /* Four byte offset from %ebp. */
1874 else /* Unexpected instruction. */
1877 if (target_read_code (pc + delta, &op, 1))
1882 if (delta > 0 && op == 0x81
1883 && read_code_unsigned_integer (pc + delta + 1, 1, byte_order)
1890 /* If the function starts with a branch (to startup code at the end)
1891 the last instruction should bring us back to the first
1892 instruction of the real code. */
1893 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1894 pc = i386_follow_jump (gdbarch, pc);
1899 /* Check that the code pointed to by PC corresponds to a call to
1900 __main, skip it if so. Return PC otherwise. */
1903 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1905 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1908 if (target_read_code (pc, &op, 1))
1914 if (target_read_code (pc + 1, buf, sizeof buf) == 0)
1916 /* Make sure address is computed correctly as a 32bit
1917 integer even if CORE_ADDR is 64 bit wide. */
1918 struct bound_minimal_symbol s;
1919 CORE_ADDR call_dest;
1921 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1922 call_dest = call_dest & 0xffffffffU;
1923 s = lookup_minimal_symbol_by_pc (call_dest);
1924 if (s.minsym != NULL
1925 && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL
1926 && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0)
1934 /* This function is 64-bit safe. */
1937 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1941 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1942 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1946 /* Normal frames. */
1949 i386_frame_cache_1 (struct frame_info *this_frame,
1950 struct i386_frame_cache *cache)
1952 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1953 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1957 cache->pc = get_frame_func (this_frame);
1959 /* In principle, for normal frames, %ebp holds the frame pointer,
1960 which holds the base address for the current stack frame.
1961 However, for functions that don't need it, the frame pointer is
1962 optional. For these "frameless" functions the frame pointer is
1963 actually the frame pointer of the calling frame. Signal
1964 trampolines are just a special case of a "frameless" function.
1965 They (usually) share their frame pointer with the frame that was
1966 in progress when the signal occurred. */
1968 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1969 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1970 if (cache->base == 0)
1976 /* For normal frames, %eip is stored at 4(%ebp). */
1977 cache->saved_regs[I386_EIP_REGNUM] = 4;
1980 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
1983 if (cache->locals < 0)
1985 /* We didn't find a valid frame, which means that CACHE->base
1986 currently holds the frame pointer for our calling frame. If
1987 we're at the start of a function, or somewhere half-way its
1988 prologue, the function's frame probably hasn't been fully
1989 setup yet. Try to reconstruct the base address for the stack
1990 frame by looking at the stack pointer. For truly "frameless"
1991 functions this might work too. */
1993 if (cache->saved_sp_reg != -1)
1995 /* Saved stack pointer has been saved. */
1996 get_frame_register (this_frame, cache->saved_sp_reg, buf);
1997 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
1999 /* We're halfway aligning the stack. */
2000 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
2001 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
2003 /* This will be added back below. */
2004 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
2006 else if (cache->pc != 0
2007 || target_read_code (get_frame_pc (this_frame), buf, 1))
2009 /* We're in a known function, but did not find a frame
2010 setup. Assume that the function does not use %ebp.
2011 Alternatively, we may have jumped to an invalid
2012 address; in that case there is definitely no new
2014 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2015 cache->base = extract_unsigned_integer (buf, 4, byte_order)
2019 /* We're in an unknown function. We could not find the start
2020 of the function to analyze the prologue; our best option is
2021 to assume a typical frame layout with the caller's %ebp
2023 cache->saved_regs[I386_EBP_REGNUM] = 0;
2026 if (cache->saved_sp_reg != -1)
2028 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2029 register may be unavailable). */
2030 if (cache->saved_sp == 0
2031 && deprecated_frame_register_read (this_frame,
2032 cache->saved_sp_reg, buf))
2033 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2035 /* Now that we have the base address for the stack frame we can
2036 calculate the value of %esp in the calling frame. */
2037 else if (cache->saved_sp == 0)
2038 cache->saved_sp = cache->base + 8;
2040 /* Adjust all the saved registers such that they contain addresses
2041 instead of offsets. */
2042 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
2043 if (cache->saved_regs[i] != -1)
2044 cache->saved_regs[i] += cache->base;
2049 static struct i386_frame_cache *
2050 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
2052 struct i386_frame_cache *cache;
2057 cache = i386_alloc_frame_cache ();
2058 *this_cache = cache;
2062 i386_frame_cache_1 (this_frame, cache);
2064 CATCH (ex, RETURN_MASK_ERROR)
2066 if (ex.error != NOT_AVAILABLE_ERROR)
2067 throw_exception (ex);
2075 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
2076 struct frame_id *this_id)
2078 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2081 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2082 else if (cache->base == 0)
2084 /* This marks the outermost frame. */
2088 /* See the end of i386_push_dummy_call. */
2089 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2093 static enum unwind_stop_reason
2094 i386_frame_unwind_stop_reason (struct frame_info *this_frame,
2097 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2100 return UNWIND_UNAVAILABLE;
2102 /* This marks the outermost frame. */
2103 if (cache->base == 0)
2104 return UNWIND_OUTERMOST;
2106 return UNWIND_NO_REASON;
2109 static struct value *
2110 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2113 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2115 gdb_assert (regnum >= 0);
2117 /* The System V ABI says that:
2119 "The flags register contains the system flags, such as the
2120 direction flag and the carry flag. The direction flag must be
2121 set to the forward (that is, zero) direction before entry and
2122 upon exit from a function. Other user flags have no specified
2123 role in the standard calling sequence and are not preserved."
2125 To guarantee the "upon exit" part of that statement we fake a
2126 saved flags register that has its direction flag cleared.
2128 Note that GCC doesn't seem to rely on the fact that the direction
2129 flag is cleared after a function return; it always explicitly
2130 clears the flag before operations where it matters.
2132 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2133 right thing to do. The way we fake the flags register here makes
2134 it impossible to change it. */
2136 if (regnum == I386_EFLAGS_REGNUM)
2140 val = get_frame_register_unsigned (this_frame, regnum);
2142 return frame_unwind_got_constant (this_frame, regnum, val);
2145 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
2146 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
2148 if (regnum == I386_ESP_REGNUM
2149 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1))
2151 /* If the SP has been saved, but we don't know where, then this
2152 means that SAVED_SP_REG register was found unavailable back
2153 when we built the cache. */
2154 if (cache->saved_sp == 0)
2155 return frame_unwind_got_register (this_frame, regnum,
2156 cache->saved_sp_reg);
2158 return frame_unwind_got_constant (this_frame, regnum,
2162 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2163 return frame_unwind_got_memory (this_frame, regnum,
2164 cache->saved_regs[regnum]);
2166 return frame_unwind_got_register (this_frame, regnum, regnum);
2169 static const struct frame_unwind i386_frame_unwind =
2172 i386_frame_unwind_stop_reason,
2174 i386_frame_prev_register,
2176 default_frame_sniffer
2179 /* Normal frames, but in a function epilogue. */
2181 /* Implement the stack_frame_destroyed_p gdbarch method.
2183 The epilogue is defined here as the 'ret' instruction, which will
2184 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2185 the function's stack frame. */
2188 i386_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2191 struct compunit_symtab *cust;
2193 cust = find_pc_compunit_symtab (pc);
2194 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
2197 if (target_read_memory (pc, &insn, 1))
2198 return 0; /* Can't read memory at pc. */
2200 if (insn != 0xc3) /* 'ret' instruction. */
2207 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
2208 struct frame_info *this_frame,
2209 void **this_prologue_cache)
2211 if (frame_relative_level (this_frame) == 0)
2212 return i386_stack_frame_destroyed_p (get_frame_arch (this_frame),
2213 get_frame_pc (this_frame));
2218 static struct i386_frame_cache *
2219 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2221 struct i386_frame_cache *cache;
2227 cache = i386_alloc_frame_cache ();
2228 *this_cache = cache;
2232 cache->pc = get_frame_func (this_frame);
2234 /* At this point the stack looks as if we just entered the
2235 function, with the return address at the top of the
2237 sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM);
2238 cache->base = sp + cache->sp_offset;
2239 cache->saved_sp = cache->base + 8;
2240 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
2244 CATCH (ex, RETURN_MASK_ERROR)
2246 if (ex.error != NOT_AVAILABLE_ERROR)
2247 throw_exception (ex);
2254 static enum unwind_stop_reason
2255 i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2258 struct i386_frame_cache *cache =
2259 i386_epilogue_frame_cache (this_frame, this_cache);
2262 return UNWIND_UNAVAILABLE;
2264 return UNWIND_NO_REASON;
2268 i386_epilogue_frame_this_id (struct frame_info *this_frame,
2270 struct frame_id *this_id)
2272 struct i386_frame_cache *cache =
2273 i386_epilogue_frame_cache (this_frame, this_cache);
2276 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2278 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2281 static struct value *
2282 i386_epilogue_frame_prev_register (struct frame_info *this_frame,
2283 void **this_cache, int regnum)
2285 /* Make sure we've initialized the cache. */
2286 i386_epilogue_frame_cache (this_frame, this_cache);
2288 return i386_frame_prev_register (this_frame, this_cache, regnum);
2291 static const struct frame_unwind i386_epilogue_frame_unwind =
2294 i386_epilogue_frame_unwind_stop_reason,
2295 i386_epilogue_frame_this_id,
2296 i386_epilogue_frame_prev_register,
2298 i386_epilogue_frame_sniffer
2302 /* Stack-based trampolines. */
2304 /* These trampolines are used on cross x86 targets, when taking the
2305 address of a nested function. When executing these trampolines,
2306 no stack frame is set up, so we are in a similar situation as in
2307 epilogues and i386_epilogue_frame_this_id can be re-used. */
2309 /* Static chain passed in register. */
2311 struct i386_insn i386_tramp_chain_in_reg_insns[] =
2313 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2314 { 5, { 0xb8 }, { 0xfe } },
2317 { 5, { 0xe9 }, { 0xff } },
2322 /* Static chain passed on stack (when regparm=3). */
2324 struct i386_insn i386_tramp_chain_on_stack_insns[] =
2327 { 5, { 0x68 }, { 0xff } },
2330 { 5, { 0xe9 }, { 0xff } },
2335 /* Return whether PC points inside a stack trampoline. */
2338 i386_in_stack_tramp_p (CORE_ADDR pc)
2343 /* A stack trampoline is detected if no name is associated
2344 to the current pc and if it points inside a trampoline
2347 find_pc_partial_function (pc, &name, NULL, NULL);
2351 if (target_read_memory (pc, &insn, 1))
2354 if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns)
2355 && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns))
2362 i386_stack_tramp_frame_sniffer (const struct frame_unwind *self,
2363 struct frame_info *this_frame,
2366 if (frame_relative_level (this_frame) == 0)
2367 return i386_in_stack_tramp_p (get_frame_pc (this_frame));
2372 static const struct frame_unwind i386_stack_tramp_frame_unwind =
2375 i386_epilogue_frame_unwind_stop_reason,
2376 i386_epilogue_frame_this_id,
2377 i386_epilogue_frame_prev_register,
2379 i386_stack_tramp_frame_sniffer
2382 /* Generate a bytecode expression to get the value of the saved PC. */
2385 i386_gen_return_address (struct gdbarch *gdbarch,
2386 struct agent_expr *ax, struct axs_value *value,
2389 /* The following sequence assumes the traditional use of the base
2391 ax_reg (ax, I386_EBP_REGNUM);
2393 ax_simple (ax, aop_add);
2394 value->type = register_type (gdbarch, I386_EIP_REGNUM);
2395 value->kind = axs_lvalue_memory;
2399 /* Signal trampolines. */
2401 static struct i386_frame_cache *
2402 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2404 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2405 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2406 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2407 struct i386_frame_cache *cache;
2414 cache = i386_alloc_frame_cache ();
2418 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2419 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
2421 addr = tdep->sigcontext_addr (this_frame);
2422 if (tdep->sc_reg_offset)
2426 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
2428 for (i = 0; i < tdep->sc_num_regs; i++)
2429 if (tdep->sc_reg_offset[i] != -1)
2430 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2434 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
2435 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
2440 CATCH (ex, RETURN_MASK_ERROR)
2442 if (ex.error != NOT_AVAILABLE_ERROR)
2443 throw_exception (ex);
2447 *this_cache = cache;
2451 static enum unwind_stop_reason
2452 i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2455 struct i386_frame_cache *cache =
2456 i386_sigtramp_frame_cache (this_frame, this_cache);
2459 return UNWIND_UNAVAILABLE;
2461 return UNWIND_NO_REASON;
2465 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
2466 struct frame_id *this_id)
2468 struct i386_frame_cache *cache =
2469 i386_sigtramp_frame_cache (this_frame, this_cache);
2472 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2475 /* See the end of i386_push_dummy_call. */
2476 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
2480 static struct value *
2481 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
2482 void **this_cache, int regnum)
2484 /* Make sure we've initialized the cache. */
2485 i386_sigtramp_frame_cache (this_frame, this_cache);
2487 return i386_frame_prev_register (this_frame, this_cache, regnum);
2491 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
2492 struct frame_info *this_frame,
2493 void **this_prologue_cache)
2495 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2497 /* We shouldn't even bother if we don't have a sigcontext_addr
2499 if (tdep->sigcontext_addr == NULL)
2502 if (tdep->sigtramp_p != NULL)
2504 if (tdep->sigtramp_p (this_frame))
2508 if (tdep->sigtramp_start != 0)
2510 CORE_ADDR pc = get_frame_pc (this_frame);
2512 gdb_assert (tdep->sigtramp_end != 0);
2513 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2520 static const struct frame_unwind i386_sigtramp_frame_unwind =
2523 i386_sigtramp_frame_unwind_stop_reason,
2524 i386_sigtramp_frame_this_id,
2525 i386_sigtramp_frame_prev_register,
2527 i386_sigtramp_frame_sniffer
2532 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
2534 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2539 static const struct frame_base i386_frame_base =
2542 i386_frame_base_address,
2543 i386_frame_base_address,
2544 i386_frame_base_address
2547 static struct frame_id
2548 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2552 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
2554 /* See the end of i386_push_dummy_call. */
2555 return frame_id_build (fp + 8, get_frame_pc (this_frame));
2558 /* _Decimal128 function return values need 16-byte alignment on the
2562 i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2564 return sp & -(CORE_ADDR)16;
2568 /* Figure out where the longjmp will land. Slurp the args out of the
2569 stack. We expect the first arg to be a pointer to the jmp_buf
2570 structure from which we extract the address that we will land at.
2571 This address is copied into PC. This routine returns non-zero on
2575 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2578 CORE_ADDR sp, jb_addr;
2579 struct gdbarch *gdbarch = get_frame_arch (frame);
2580 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2581 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2583 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2584 longjmp will land. */
2585 if (jb_pc_offset == -1)
2588 get_frame_register (frame, I386_ESP_REGNUM, buf);
2589 sp = extract_unsigned_integer (buf, 4, byte_order);
2590 if (target_read_memory (sp + 4, buf, 4))
2593 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
2594 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
2597 *pc = extract_unsigned_integer (buf, 4, byte_order);
2602 /* Check whether TYPE must be 16-byte-aligned when passed as a
2603 function argument. 16-byte vectors, _Decimal128 and structures or
2604 unions containing such types must be 16-byte-aligned; other
2605 arguments are 4-byte-aligned. */
2608 i386_16_byte_align_p (struct type *type)
2610 type = check_typedef (type);
2611 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
2612 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
2613 && TYPE_LENGTH (type) == 16)
2615 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2616 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
2617 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2618 || TYPE_CODE (type) == TYPE_CODE_UNION)
2621 for (i = 0; i < TYPE_NFIELDS (type); i++)
2623 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
2630 /* Implementation for set_gdbarch_push_dummy_code. */
2633 i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
2634 struct value **args, int nargs, struct type *value_type,
2635 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
2636 struct regcache *regcache)
2638 /* Use 0xcc breakpoint - 1 byte. */
2642 /* Keep the stack aligned. */
2647 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2648 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2649 struct value **args, CORE_ADDR sp, int struct_return,
2650 CORE_ADDR struct_addr)
2652 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2658 /* Determine the total space required for arguments and struct
2659 return address in a first pass (allowing for 16-byte-aligned
2660 arguments), then push arguments in a second pass. */
2662 for (write_pass = 0; write_pass < 2; write_pass++)
2664 int args_space_used = 0;
2670 /* Push value address. */
2671 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2672 write_memory (sp, buf, 4);
2673 args_space_used += 4;
2679 for (i = 0; i < nargs; i++)
2681 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2685 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2686 args_space_used = align_up (args_space_used, 16);
2688 write_memory (sp + args_space_used,
2689 value_contents_all (args[i]), len);
2690 /* The System V ABI says that:
2692 "An argument's size is increased, if necessary, to make it a
2693 multiple of [32-bit] words. This may require tail padding,
2694 depending on the size of the argument."
2696 This makes sure the stack stays word-aligned. */
2697 args_space_used += align_up (len, 4);
2701 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2702 args_space = align_up (args_space, 16);
2703 args_space += align_up (len, 4);
2711 /* The original System V ABI only requires word alignment,
2712 but modern incarnations need 16-byte alignment in order
2713 to support SSE. Since wasting a few bytes here isn't
2714 harmful we unconditionally enforce 16-byte alignment. */
2719 /* Store return address. */
2721 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2722 write_memory (sp, buf, 4);
2724 /* Finally, update the stack pointer... */
2725 store_unsigned_integer (buf, 4, byte_order, sp);
2726 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
2728 /* ...and fake a frame pointer. */
2729 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
2731 /* MarkK wrote: This "+ 8" is all over the place:
2732 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2733 i386_dummy_id). It's there, since all frame unwinders for
2734 a given target have to agree (within a certain margin) on the
2735 definition of the stack address of a frame. Otherwise frame id
2736 comparison might not work correctly. Since DWARF2/GCC uses the
2737 stack address *before* the function call as a frame's CFA. On
2738 the i386, when %ebp is used as a frame pointer, the offset
2739 between the contents %ebp and the CFA as defined by GCC. */
2743 /* These registers are used for returning integers (and on some
2744 targets also for returning `struct' and `union' values when their
2745 size and alignment match an integer type). */
2746 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2747 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2749 /* Read, for architecture GDBARCH, a function return value of TYPE
2750 from REGCACHE, and copy that into VALBUF. */
2753 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2754 struct regcache *regcache, gdb_byte *valbuf)
2756 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2757 int len = TYPE_LENGTH (type);
2758 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2760 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2762 if (tdep->st0_regnum < 0)
2764 warning (_("Cannot find floating-point return value."));
2765 memset (valbuf, 0, len);
2769 /* Floating-point return values can be found in %st(0). Convert
2770 its contents to the desired type. This is probably not
2771 exactly how it would happen on the target itself, but it is
2772 the best we can do. */
2773 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2774 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
2778 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2779 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2781 if (len <= low_size)
2783 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2784 memcpy (valbuf, buf, len);
2786 else if (len <= (low_size + high_size))
2788 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2789 memcpy (valbuf, buf, low_size);
2790 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2791 memcpy (valbuf + low_size, buf, len - low_size);
2794 internal_error (__FILE__, __LINE__,
2795 _("Cannot extract return value of %d bytes long."),
2800 /* Write, for architecture GDBARCH, a function return value of TYPE
2801 from VALBUF into REGCACHE. */
2804 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2805 struct regcache *regcache, const gdb_byte *valbuf)
2807 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2808 int len = TYPE_LENGTH (type);
2810 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2813 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2815 if (tdep->st0_regnum < 0)
2817 warning (_("Cannot set floating-point return value."));
2821 /* Returning floating-point values is a bit tricky. Apart from
2822 storing the return value in %st(0), we have to simulate the
2823 state of the FPU at function return point. */
2825 /* Convert the value found in VALBUF to the extended
2826 floating-point format used by the FPU. This is probably
2827 not exactly how it would happen on the target itself, but
2828 it is the best we can do. */
2829 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
2830 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2832 /* Set the top of the floating-point register stack to 7. The
2833 actual value doesn't really matter, but 7 is what a normal
2834 function return would end up with if the program started out
2835 with a freshly initialized FPU. */
2836 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2838 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2840 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2841 the floating-point register stack to 7, the appropriate value
2842 for the tag word is 0x3fff. */
2843 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2847 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2848 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2850 if (len <= low_size)
2851 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2852 else if (len <= (low_size + high_size))
2854 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2855 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
2856 len - low_size, valbuf + low_size);
2859 internal_error (__FILE__, __LINE__,
2860 _("Cannot store return value of %d bytes long."), len);
2865 /* This is the variable that is set with "set struct-convention", and
2866 its legitimate values. */
2867 static const char default_struct_convention[] = "default";
2868 static const char pcc_struct_convention[] = "pcc";
2869 static const char reg_struct_convention[] = "reg";
2870 static const char *const valid_conventions[] =
2872 default_struct_convention,
2873 pcc_struct_convention,
2874 reg_struct_convention,
2877 static const char *struct_convention = default_struct_convention;
2879 /* Return non-zero if TYPE, which is assumed to be a structure,
2880 a union type, or an array type, should be returned in registers
2881 for architecture GDBARCH. */
2884 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2886 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2887 enum type_code code = TYPE_CODE (type);
2888 int len = TYPE_LENGTH (type);
2890 gdb_assert (code == TYPE_CODE_STRUCT
2891 || code == TYPE_CODE_UNION
2892 || code == TYPE_CODE_ARRAY);
2894 if (struct_convention == pcc_struct_convention
2895 || (struct_convention == default_struct_convention
2896 && tdep->struct_return == pcc_struct_return))
2899 /* Structures consisting of a single `float', `double' or 'long
2900 double' member are returned in %st(0). */
2901 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2903 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2904 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2905 return (len == 4 || len == 8 || len == 12);
2908 return (len == 1 || len == 2 || len == 4 || len == 8);
2911 /* Determine, for architecture GDBARCH, how a return value of TYPE
2912 should be returned. If it is supposed to be returned in registers,
2913 and READBUF is non-zero, read the appropriate value from REGCACHE,
2914 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2915 from WRITEBUF into REGCACHE. */
2917 static enum return_value_convention
2918 i386_return_value (struct gdbarch *gdbarch, struct value *function,
2919 struct type *type, struct regcache *regcache,
2920 gdb_byte *readbuf, const gdb_byte *writebuf)
2922 enum type_code code = TYPE_CODE (type);
2924 if (((code == TYPE_CODE_STRUCT
2925 || code == TYPE_CODE_UNION
2926 || code == TYPE_CODE_ARRAY)
2927 && !i386_reg_struct_return_p (gdbarch, type))
2928 /* Complex double and long double uses the struct return covention. */
2929 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16)
2930 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24)
2931 /* 128-bit decimal float uses the struct return convention. */
2932 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2934 /* The System V ABI says that:
2936 "A function that returns a structure or union also sets %eax
2937 to the value of the original address of the caller's area
2938 before it returns. Thus when the caller receives control
2939 again, the address of the returned object resides in register
2940 %eax and can be used to access the object."
2942 So the ABI guarantees that we can always find the return
2943 value just after the function has returned. */
2945 /* Note that the ABI doesn't mention functions returning arrays,
2946 which is something possible in certain languages such as Ada.
2947 In this case, the value is returned as if it was wrapped in
2948 a record, so the convention applied to records also applies
2955 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2956 read_memory (addr, readbuf, TYPE_LENGTH (type));
2959 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2962 /* This special case is for structures consisting of a single
2963 `float', `double' or 'long double' member. These structures are
2964 returned in %st(0). For these structures, we call ourselves
2965 recursively, changing TYPE into the type of the first member of
2966 the structure. Since that should work for all structures that
2967 have only one member, we don't bother to check the member's type
2969 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2971 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2972 return i386_return_value (gdbarch, function, type, regcache,
2977 i386_extract_return_value (gdbarch, type, regcache, readbuf);
2979 i386_store_return_value (gdbarch, type, regcache, writebuf);
2981 return RETURN_VALUE_REGISTER_CONVENTION;
2986 i387_ext_type (struct gdbarch *gdbarch)
2988 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2990 if (!tdep->i387_ext_type)
2992 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
2993 gdb_assert (tdep->i387_ext_type != NULL);
2996 return tdep->i387_ext_type;
2999 /* Construct type for pseudo BND registers. We can't use
3000 tdesc_find_type since a complement of one value has to be used
3001 to describe the upper bound. */
3003 static struct type *
3004 i386_bnd_type (struct gdbarch *gdbarch)
3006 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3009 if (!tdep->i386_bnd_type)
3011 struct type *t, *bound_t;
3012 const struct builtin_type *bt = builtin_type (gdbarch);
3014 /* The type we're building is described bellow: */
3019 void *ubound; /* One complement of raw ubound field. */
3023 t = arch_composite_type (gdbarch,
3024 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT);
3026 append_composite_type_field (t, "lbound", bt->builtin_data_ptr);
3027 append_composite_type_field (t, "ubound", bt->builtin_data_ptr);
3029 TYPE_NAME (t) = "builtin_type_bound128";
3030 tdep->i386_bnd_type = t;
3033 return tdep->i386_bnd_type;
3036 /* Construct vector type for pseudo ZMM registers. We can't use
3037 tdesc_find_type since ZMM isn't described in target description. */
3039 static struct type *
3040 i386_zmm_type (struct gdbarch *gdbarch)
3042 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3044 if (!tdep->i386_zmm_type)
3046 const struct builtin_type *bt = builtin_type (gdbarch);
3048 /* The type we're building is this: */
3050 union __gdb_builtin_type_vec512i
3052 int128_t uint128[4];
3053 int64_t v4_int64[8];
3054 int32_t v8_int32[16];
3055 int16_t v16_int16[32];
3056 int8_t v32_int8[64];
3057 double v4_double[8];
3064 t = arch_composite_type (gdbarch,
3065 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION);
3066 append_composite_type_field (t, "v16_float",
3067 init_vector_type (bt->builtin_float, 16));
3068 append_composite_type_field (t, "v8_double",
3069 init_vector_type (bt->builtin_double, 8));
3070 append_composite_type_field (t, "v64_int8",
3071 init_vector_type (bt->builtin_int8, 64));
3072 append_composite_type_field (t, "v32_int16",
3073 init_vector_type (bt->builtin_int16, 32));
3074 append_composite_type_field (t, "v16_int32",
3075 init_vector_type (bt->builtin_int32, 16));
3076 append_composite_type_field (t, "v8_int64",
3077 init_vector_type (bt->builtin_int64, 8));
3078 append_composite_type_field (t, "v4_int128",
3079 init_vector_type (bt->builtin_int128, 4));
3081 TYPE_VECTOR (t) = 1;
3082 TYPE_NAME (t) = "builtin_type_vec512i";
3083 tdep->i386_zmm_type = t;
3086 return tdep->i386_zmm_type;
3089 /* Construct vector type for pseudo YMM registers. We can't use
3090 tdesc_find_type since YMM isn't described in target description. */
3092 static struct type *
3093 i386_ymm_type (struct gdbarch *gdbarch)
3095 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3097 if (!tdep->i386_ymm_type)
3099 const struct builtin_type *bt = builtin_type (gdbarch);
3101 /* The type we're building is this: */
3103 union __gdb_builtin_type_vec256i
3105 int128_t uint128[2];
3106 int64_t v2_int64[4];
3107 int32_t v4_int32[8];
3108 int16_t v8_int16[16];
3109 int8_t v16_int8[32];
3110 double v2_double[4];
3117 t = arch_composite_type (gdbarch,
3118 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
3119 append_composite_type_field (t, "v8_float",
3120 init_vector_type (bt->builtin_float, 8));
3121 append_composite_type_field (t, "v4_double",
3122 init_vector_type (bt->builtin_double, 4));
3123 append_composite_type_field (t, "v32_int8",
3124 init_vector_type (bt->builtin_int8, 32));
3125 append_composite_type_field (t, "v16_int16",
3126 init_vector_type (bt->builtin_int16, 16));
3127 append_composite_type_field (t, "v8_int32",
3128 init_vector_type (bt->builtin_int32, 8));
3129 append_composite_type_field (t, "v4_int64",
3130 init_vector_type (bt->builtin_int64, 4));
3131 append_composite_type_field (t, "v2_int128",
3132 init_vector_type (bt->builtin_int128, 2));
3134 TYPE_VECTOR (t) = 1;
3135 TYPE_NAME (t) = "builtin_type_vec256i";
3136 tdep->i386_ymm_type = t;
3139 return tdep->i386_ymm_type;
3142 /* Construct vector type for MMX registers. */
3143 static struct type *
3144 i386_mmx_type (struct gdbarch *gdbarch)
3146 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3148 if (!tdep->i386_mmx_type)
3150 const struct builtin_type *bt = builtin_type (gdbarch);
3152 /* The type we're building is this: */
3154 union __gdb_builtin_type_vec64i
3157 int32_t v2_int32[2];
3158 int16_t v4_int16[4];
3165 t = arch_composite_type (gdbarch,
3166 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
3168 append_composite_type_field (t, "uint64", bt->builtin_int64);
3169 append_composite_type_field (t, "v2_int32",
3170 init_vector_type (bt->builtin_int32, 2));
3171 append_composite_type_field (t, "v4_int16",
3172 init_vector_type (bt->builtin_int16, 4));
3173 append_composite_type_field (t, "v8_int8",
3174 init_vector_type (bt->builtin_int8, 8));
3176 TYPE_VECTOR (t) = 1;
3177 TYPE_NAME (t) = "builtin_type_vec64i";
3178 tdep->i386_mmx_type = t;
3181 return tdep->i386_mmx_type;
3184 /* Return the GDB type object for the "standard" data type of data in
3188 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3190 if (i386_bnd_regnum_p (gdbarch, regnum))
3191 return i386_bnd_type (gdbarch);
3192 if (i386_mmx_regnum_p (gdbarch, regnum))
3193 return i386_mmx_type (gdbarch);
3194 else if (i386_ymm_regnum_p (gdbarch, regnum))
3195 return i386_ymm_type (gdbarch);
3196 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3197 return i386_ymm_type (gdbarch);
3198 else if (i386_zmm_regnum_p (gdbarch, regnum))
3199 return i386_zmm_type (gdbarch);
3202 const struct builtin_type *bt = builtin_type (gdbarch);
3203 if (i386_byte_regnum_p (gdbarch, regnum))
3204 return bt->builtin_int8;
3205 else if (i386_word_regnum_p (gdbarch, regnum))
3206 return bt->builtin_int16;
3207 else if (i386_dword_regnum_p (gdbarch, regnum))
3208 return bt->builtin_int32;
3209 else if (i386_k_regnum_p (gdbarch, regnum))
3210 return bt->builtin_int64;
3213 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3216 /* Map a cooked register onto a raw register or memory. For the i386,
3217 the MMX registers need to be mapped onto floating point registers. */
3220 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
3222 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
3227 mmxreg = regnum - tdep->mm0_regnum;
3228 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
3229 tos = (fstat >> 11) & 0x7;
3230 fpreg = (mmxreg + tos) % 8;
3232 return (I387_ST0_REGNUM (tdep) + fpreg);
3235 /* A helper function for us by i386_pseudo_register_read_value and
3236 amd64_pseudo_register_read_value. It does all the work but reads
3237 the data into an already-allocated value. */
3240 i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
3241 struct regcache *regcache,
3243 struct value *result_value)
3245 gdb_byte raw_buf[MAX_REGISTER_SIZE];
3246 enum register_status status;
3247 gdb_byte *buf = value_contents_raw (result_value);
3249 if (i386_mmx_regnum_p (gdbarch, regnum))
3251 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3253 /* Extract (always little endian). */
3254 status = regcache_raw_read (regcache, fpnum, raw_buf);
3255 if (status != REG_VALID)
3256 mark_value_bytes_unavailable (result_value, 0,
3257 TYPE_LENGTH (value_type (result_value)));
3259 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
3263 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3264 if (i386_bnd_regnum_p (gdbarch, regnum))
3266 regnum -= tdep->bnd0_regnum;
3268 /* Extract (always little endian). Read lower 128bits. */
3269 status = regcache_raw_read (regcache,
3270 I387_BND0R_REGNUM (tdep) + regnum,
3272 if (status != REG_VALID)
3273 mark_value_bytes_unavailable (result_value, 0, 16);
3276 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3277 LONGEST upper, lower;
3278 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3280 lower = extract_unsigned_integer (raw_buf, 8, byte_order);
3281 upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order);
3284 memcpy (buf, &lower, size);
3285 memcpy (buf + size, &upper, size);
3288 else if (i386_k_regnum_p (gdbarch, regnum))
3290 regnum -= tdep->k0_regnum;
3292 /* Extract (always little endian). */
3293 status = regcache_raw_read (regcache,
3294 tdep->k0_regnum + regnum,
3296 if (status != REG_VALID)
3297 mark_value_bytes_unavailable (result_value, 0, 8);
3299 memcpy (buf, raw_buf, 8);
3301 else if (i386_zmm_regnum_p (gdbarch, regnum))
3303 regnum -= tdep->zmm0_regnum;
3305 if (regnum < num_lower_zmm_regs)
3307 /* Extract (always little endian). Read lower 128bits. */
3308 status = regcache_raw_read (regcache,
3309 I387_XMM0_REGNUM (tdep) + regnum,
3311 if (status != REG_VALID)
3312 mark_value_bytes_unavailable (result_value, 0, 16);
3314 memcpy (buf, raw_buf, 16);
3316 /* Extract (always little endian). Read upper 128bits. */
3317 status = regcache_raw_read (regcache,
3318 tdep->ymm0h_regnum + regnum,
3320 if (status != REG_VALID)
3321 mark_value_bytes_unavailable (result_value, 16, 16);
3323 memcpy (buf + 16, raw_buf, 16);
3327 /* Extract (always little endian). Read lower 128bits. */
3328 status = regcache_raw_read (regcache,
3329 I387_XMM16_REGNUM (tdep) + regnum
3330 - num_lower_zmm_regs,
3332 if (status != REG_VALID)
3333 mark_value_bytes_unavailable (result_value, 0, 16);
3335 memcpy (buf, raw_buf, 16);
3337 /* Extract (always little endian). Read upper 128bits. */
3338 status = regcache_raw_read (regcache,
3339 I387_YMM16H_REGNUM (tdep) + regnum
3340 - num_lower_zmm_regs,
3342 if (status != REG_VALID)
3343 mark_value_bytes_unavailable (result_value, 16, 16);
3345 memcpy (buf + 16, raw_buf, 16);
3348 /* Read upper 256bits. */
3349 status = regcache_raw_read (regcache,
3350 tdep->zmm0h_regnum + regnum,
3352 if (status != REG_VALID)
3353 mark_value_bytes_unavailable (result_value, 32, 32);
3355 memcpy (buf + 32, raw_buf, 32);
3357 else if (i386_ymm_regnum_p (gdbarch, regnum))
3359 regnum -= tdep->ymm0_regnum;
3361 /* Extract (always little endian). Read lower 128bits. */
3362 status = regcache_raw_read (regcache,
3363 I387_XMM0_REGNUM (tdep) + regnum,
3365 if (status != REG_VALID)
3366 mark_value_bytes_unavailable (result_value, 0, 16);
3368 memcpy (buf, raw_buf, 16);
3369 /* Read upper 128bits. */
3370 status = regcache_raw_read (regcache,
3371 tdep->ymm0h_regnum + regnum,
3373 if (status != REG_VALID)
3374 mark_value_bytes_unavailable (result_value, 16, 32);
3376 memcpy (buf + 16, raw_buf, 16);
3378 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3380 regnum -= tdep->ymm16_regnum;
3381 /* Extract (always little endian). Read lower 128bits. */
3382 status = regcache_raw_read (regcache,
3383 I387_XMM16_REGNUM (tdep) + regnum,
3385 if (status != REG_VALID)
3386 mark_value_bytes_unavailable (result_value, 0, 16);
3388 memcpy (buf, raw_buf, 16);
3389 /* Read upper 128bits. */
3390 status = regcache_raw_read (regcache,
3391 tdep->ymm16h_regnum + regnum,
3393 if (status != REG_VALID)
3394 mark_value_bytes_unavailable (result_value, 16, 16);
3396 memcpy (buf + 16, raw_buf, 16);
3398 else if (i386_word_regnum_p (gdbarch, regnum))
3400 int gpnum = regnum - tdep->ax_regnum;
3402 /* Extract (always little endian). */
3403 status = regcache_raw_read (regcache, gpnum, raw_buf);
3404 if (status != REG_VALID)
3405 mark_value_bytes_unavailable (result_value, 0,
3406 TYPE_LENGTH (value_type (result_value)));
3408 memcpy (buf, raw_buf, 2);
3410 else if (i386_byte_regnum_p (gdbarch, regnum))
3412 /* Check byte pseudo registers last since this function will
3413 be called from amd64_pseudo_register_read, which handles
3414 byte pseudo registers differently. */
3415 int gpnum = regnum - tdep->al_regnum;
3417 /* Extract (always little endian). We read both lower and
3419 status = regcache_raw_read (regcache, gpnum % 4, raw_buf);
3420 if (status != REG_VALID)
3421 mark_value_bytes_unavailable (result_value, 0,
3422 TYPE_LENGTH (value_type (result_value)));
3423 else if (gpnum >= 4)
3424 memcpy (buf, raw_buf + 1, 1);
3426 memcpy (buf, raw_buf, 1);
3429 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3433 static struct value *
3434 i386_pseudo_register_read_value (struct gdbarch *gdbarch,
3435 struct regcache *regcache,
3438 struct value *result;
3440 result = allocate_value (register_type (gdbarch, regnum));
3441 VALUE_LVAL (result) = lval_register;
3442 VALUE_REGNUM (result) = regnum;
3444 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result);
3450 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3451 int regnum, const gdb_byte *buf)
3453 gdb_byte raw_buf[MAX_REGISTER_SIZE];
3455 if (i386_mmx_regnum_p (gdbarch, regnum))
3457 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3460 regcache_raw_read (regcache, fpnum, raw_buf);
3461 /* ... Modify ... (always little endian). */
3462 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
3464 regcache_raw_write (regcache, fpnum, raw_buf);
3468 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3470 if (i386_bnd_regnum_p (gdbarch, regnum))
3472 ULONGEST upper, lower;
3473 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3474 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3476 /* New values from input value. */
3477 regnum -= tdep->bnd0_regnum;
3478 lower = extract_unsigned_integer (buf, size, byte_order);
3479 upper = extract_unsigned_integer (buf + size, size, byte_order);
3481 /* Fetching register buffer. */
3482 regcache_raw_read (regcache,
3483 I387_BND0R_REGNUM (tdep) + regnum,
3488 /* Set register bits. */
3489 memcpy (raw_buf, &lower, 8);
3490 memcpy (raw_buf + 8, &upper, 8);
3493 regcache_raw_write (regcache,
3494 I387_BND0R_REGNUM (tdep) + regnum,
3497 else if (i386_k_regnum_p (gdbarch, regnum))
3499 regnum -= tdep->k0_regnum;
3501 regcache_raw_write (regcache,
3502 tdep->k0_regnum + regnum,
3505 else if (i386_zmm_regnum_p (gdbarch, regnum))
3507 regnum -= tdep->zmm0_regnum;
3509 if (regnum < num_lower_zmm_regs)
3511 /* Write lower 128bits. */
3512 regcache_raw_write (regcache,
3513 I387_XMM0_REGNUM (tdep) + regnum,
3515 /* Write upper 128bits. */
3516 regcache_raw_write (regcache,
3517 I387_YMM0_REGNUM (tdep) + regnum,
3522 /* Write lower 128bits. */
3523 regcache_raw_write (regcache,
3524 I387_XMM16_REGNUM (tdep) + regnum
3525 - num_lower_zmm_regs,
3527 /* Write upper 128bits. */
3528 regcache_raw_write (regcache,
3529 I387_YMM16H_REGNUM (tdep) + regnum
3530 - num_lower_zmm_regs,
3533 /* Write upper 256bits. */
3534 regcache_raw_write (regcache,
3535 tdep->zmm0h_regnum + regnum,
3538 else if (i386_ymm_regnum_p (gdbarch, regnum))
3540 regnum -= tdep->ymm0_regnum;
3542 /* ... Write lower 128bits. */
3543 regcache_raw_write (regcache,
3544 I387_XMM0_REGNUM (tdep) + regnum,
3546 /* ... Write upper 128bits. */
3547 regcache_raw_write (regcache,
3548 tdep->ymm0h_regnum + regnum,
3551 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3553 regnum -= tdep->ymm16_regnum;
3555 /* ... Write lower 128bits. */
3556 regcache_raw_write (regcache,
3557 I387_XMM16_REGNUM (tdep) + regnum,
3559 /* ... Write upper 128bits. */
3560 regcache_raw_write (regcache,
3561 tdep->ymm16h_regnum + regnum,
3564 else if (i386_word_regnum_p (gdbarch, regnum))
3566 int gpnum = regnum - tdep->ax_regnum;
3569 regcache_raw_read (regcache, gpnum, raw_buf);
3570 /* ... Modify ... (always little endian). */
3571 memcpy (raw_buf, buf, 2);
3573 regcache_raw_write (regcache, gpnum, raw_buf);
3575 else if (i386_byte_regnum_p (gdbarch, regnum))
3577 /* Check byte pseudo registers last since this function will
3578 be called from amd64_pseudo_register_read, which handles
3579 byte pseudo registers differently. */
3580 int gpnum = regnum - tdep->al_regnum;
3582 /* Read ... We read both lower and upper registers. */
3583 regcache_raw_read (regcache, gpnum % 4, raw_buf);
3584 /* ... Modify ... (always little endian). */
3586 memcpy (raw_buf + 1, buf, 1);
3588 memcpy (raw_buf, buf, 1);
3590 regcache_raw_write (regcache, gpnum % 4, raw_buf);
3593 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3598 /* Return the register number of the register allocated by GCC after
3599 REGNUM, or -1 if there is no such register. */
3602 i386_next_regnum (int regnum)
3604 /* GCC allocates the registers in the order:
3606 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3608 Since storing a variable in %esp doesn't make any sense we return
3609 -1 for %ebp and for %esp itself. */
3610 static int next_regnum[] =
3612 I386_EDX_REGNUM, /* Slot for %eax. */
3613 I386_EBX_REGNUM, /* Slot for %ecx. */
3614 I386_ECX_REGNUM, /* Slot for %edx. */
3615 I386_ESI_REGNUM, /* Slot for %ebx. */
3616 -1, -1, /* Slots for %esp and %ebp. */
3617 I386_EDI_REGNUM, /* Slot for %esi. */
3618 I386_EBP_REGNUM /* Slot for %edi. */
3621 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
3622 return next_regnum[regnum];
3627 /* Return nonzero if a value of type TYPE stored in register REGNUM
3628 needs any special handling. */
3631 i386_convert_register_p (struct gdbarch *gdbarch,
3632 int regnum, struct type *type)
3634 int len = TYPE_LENGTH (type);
3636 /* Values may be spread across multiple registers. Most debugging
3637 formats aren't expressive enough to specify the locations, so
3638 some heuristics is involved. Right now we only handle types that
3639 have a length that is a multiple of the word size, since GCC
3640 doesn't seem to put any other types into registers. */
3641 if (len > 4 && len % 4 == 0)
3643 int last_regnum = regnum;
3647 last_regnum = i386_next_regnum (last_regnum);
3651 if (last_regnum != -1)
3655 return i387_convert_register_p (gdbarch, regnum, type);
3658 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3659 return its contents in TO. */
3662 i386_register_to_value (struct frame_info *frame, int regnum,
3663 struct type *type, gdb_byte *to,
3664 int *optimizedp, int *unavailablep)
3666 struct gdbarch *gdbarch = get_frame_arch (frame);
3667 int len = TYPE_LENGTH (type);
3669 if (i386_fp_regnum_p (gdbarch, regnum))
3670 return i387_register_to_value (frame, regnum, type, to,
3671 optimizedp, unavailablep);
3673 /* Read a value spread across multiple registers. */
3675 gdb_assert (len > 4 && len % 4 == 0);
3679 gdb_assert (regnum != -1);
3680 gdb_assert (register_size (gdbarch, regnum) == 4);
3682 if (!get_frame_register_bytes (frame, regnum, 0,
3683 register_size (gdbarch, regnum),
3684 to, optimizedp, unavailablep))
3687 regnum = i386_next_regnum (regnum);
3692 *optimizedp = *unavailablep = 0;
3696 /* Write the contents FROM of a value of type TYPE into register
3697 REGNUM in frame FRAME. */
3700 i386_value_to_register (struct frame_info *frame, int regnum,
3701 struct type *type, const gdb_byte *from)
3703 int len = TYPE_LENGTH (type);
3705 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
3707 i387_value_to_register (frame, regnum, type, from);
3711 /* Write a value spread across multiple registers. */
3713 gdb_assert (len > 4 && len % 4 == 0);
3717 gdb_assert (regnum != -1);
3718 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
3720 put_frame_register (frame, regnum, from);
3721 regnum = i386_next_regnum (regnum);
3727 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3728 in the general-purpose register set REGSET to register cache
3729 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3732 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
3733 int regnum, const void *gregs, size_t len)
3735 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3736 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3737 const gdb_byte *regs = gregs;
3740 gdb_assert (len >= tdep->sizeof_gregset);
3742 for (i = 0; i < tdep->gregset_num_regs; i++)
3744 if ((regnum == i || regnum == -1)
3745 && tdep->gregset_reg_offset[i] != -1)
3746 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
3750 /* Collect register REGNUM from the register cache REGCACHE and store
3751 it in the buffer specified by GREGS and LEN as described by the
3752 general-purpose register set REGSET. If REGNUM is -1, do this for
3753 all registers in REGSET. */
3756 i386_collect_gregset (const struct regset *regset,
3757 const struct regcache *regcache,
3758 int regnum, void *gregs, size_t len)
3760 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3761 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3762 gdb_byte *regs = gregs;
3765 gdb_assert (len >= tdep->sizeof_gregset);
3767 for (i = 0; i < tdep->gregset_num_regs; i++)
3769 if ((regnum == i || regnum == -1)
3770 && tdep->gregset_reg_offset[i] != -1)
3771 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
3775 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3776 in the floating-point register set REGSET to register cache
3777 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3780 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
3781 int regnum, const void *fpregs, size_t len)
3783 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3784 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3786 if (len == I387_SIZEOF_FXSAVE)
3788 i387_supply_fxsave (regcache, regnum, fpregs);
3792 gdb_assert (len >= tdep->sizeof_fpregset);
3793 i387_supply_fsave (regcache, regnum, fpregs);
3796 /* Collect register REGNUM from the register cache REGCACHE and store
3797 it in the buffer specified by FPREGS and LEN as described by the
3798 floating-point register set REGSET. If REGNUM is -1, do this for
3799 all registers in REGSET. */
3802 i386_collect_fpregset (const struct regset *regset,
3803 const struct regcache *regcache,
3804 int regnum, void *fpregs, size_t len)
3806 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3807 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3809 if (len == I387_SIZEOF_FXSAVE)
3811 i387_collect_fxsave (regcache, regnum, fpregs);
3815 gdb_assert (len >= tdep->sizeof_fpregset);
3816 i387_collect_fsave (regcache, regnum, fpregs);
3819 /* Register set definitions. */
3821 const struct regset i386_gregset =
3823 NULL, i386_supply_gregset, i386_collect_gregset
3826 const struct regset i386_fpregset =
3828 NULL, i386_supply_fpregset, i386_collect_fpregset
3831 /* Default iterator over core file register note sections. */
3834 i386_iterate_over_regset_sections (struct gdbarch *gdbarch,
3835 iterate_over_regset_sections_cb *cb,
3837 const struct regcache *regcache)
3839 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3841 cb (".reg", tdep->sizeof_gregset, &i386_gregset, NULL, cb_data);
3842 if (tdep->sizeof_fpregset)
3843 cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
3847 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3850 i386_pe_skip_trampoline_code (struct frame_info *frame,
3851 CORE_ADDR pc, char *name)
3853 struct gdbarch *gdbarch = get_frame_arch (frame);
3854 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3857 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
3859 unsigned long indirect =
3860 read_memory_unsigned_integer (pc + 2, 4, byte_order);
3861 struct minimal_symbol *indsym =
3862 indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0;
3863 const char *symname = indsym ? MSYMBOL_LINKAGE_NAME (indsym) : 0;
3867 if (startswith (symname, "__imp_")
3868 || startswith (symname, "_imp_"))
3870 read_memory_unsigned_integer (indirect, 4, byte_order);
3873 return 0; /* Not a trampoline. */
3877 /* Return whether the THIS_FRAME corresponds to a sigtramp
3881 i386_sigtramp_p (struct frame_info *this_frame)
3883 CORE_ADDR pc = get_frame_pc (this_frame);
3886 find_pc_partial_function (pc, &name, NULL, NULL);
3887 return (name && strcmp ("_sigtramp", name) == 0);
3891 /* We have two flavours of disassembly. The machinery on this page
3892 deals with switching between those. */
3895 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
3897 gdb_assert (disassembly_flavor == att_flavor
3898 || disassembly_flavor == intel_flavor);
3900 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3901 constified, cast to prevent a compiler warning. */
3902 info->disassembler_options = (char *) disassembly_flavor;
3904 return print_insn_i386 (pc, info);
3908 /* There are a few i386 architecture variants that differ only
3909 slightly from the generic i386 target. For now, we don't give them
3910 their own source file, but include them here. As a consequence,
3911 they'll always be included. */
3913 /* System V Release 4 (SVR4). */
3915 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3919 i386_svr4_sigtramp_p (struct frame_info *this_frame)
3921 CORE_ADDR pc = get_frame_pc (this_frame);
3924 /* The origin of these symbols is currently unknown. */
3925 find_pc_partial_function (pc, &name, NULL, NULL);
3926 return (name && (strcmp ("_sigreturn", name) == 0
3927 || strcmp ("sigvechandler", name) == 0));
3930 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3931 address of the associated sigcontext (ucontext) structure. */
3934 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
3936 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3937 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3941 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
3942 sp = extract_unsigned_integer (buf, 4, byte_order);
3944 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
3949 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
3953 i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s)
3955 return (*s == '$' /* Literal number. */
3956 || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */
3957 || (*s == '(' && s[1] == '%') /* Register indirection. */
3958 || (*s == '%' && isalpha (s[1]))); /* Register access. */
3961 /* Helper function for i386_stap_parse_special_token.
3963 This function parses operands of the form `-8+3+1(%rbp)', which
3964 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
3966 Return 1 if the operand was parsed successfully, zero
3970 i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch,
3971 struct stap_parse_info *p)
3973 const char *s = p->arg;
3975 if (isdigit (*s) || *s == '-' || *s == '+')
3979 long displacements[3];
3995 if (!isdigit ((unsigned char) *s))
3998 displacements[0] = strtol (s, &endp, 10);
4001 if (*s != '+' && *s != '-')
4003 /* We are not dealing with a triplet. */
4016 if (!isdigit ((unsigned char) *s))
4019 displacements[1] = strtol (s, &endp, 10);
4022 if (*s != '+' && *s != '-')
4024 /* We are not dealing with a triplet. */
4037 if (!isdigit ((unsigned char) *s))
4040 displacements[2] = strtol (s, &endp, 10);
4043 if (*s != '(' || s[1] != '%')
4049 while (isalnum (*s))
4055 len = s - start - 1;
4056 regname = alloca (len + 1);
4058 strncpy (regname, start, len);
4059 regname[len] = '\0';
4061 if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1)
4062 error (_("Invalid register name `%s' on expression `%s'."),
4063 regname, p->saved_arg);
4065 for (i = 0; i < 3; i++)
4067 write_exp_elt_opcode (&p->pstate, OP_LONG);
4069 (&p->pstate, builtin_type (gdbarch)->builtin_long);
4070 write_exp_elt_longcst (&p->pstate, displacements[i]);
4071 write_exp_elt_opcode (&p->pstate, OP_LONG);
4073 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4076 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4079 write_exp_string (&p->pstate, str);
4080 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4082 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4083 write_exp_elt_type (&p->pstate,
4084 builtin_type (gdbarch)->builtin_data_ptr);
4085 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4087 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4088 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4089 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4091 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4092 write_exp_elt_type (&p->pstate,
4093 lookup_pointer_type (p->arg_type));
4094 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4096 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4106 /* Helper function for i386_stap_parse_special_token.
4108 This function parses operands of the form `register base +
4109 (register index * size) + offset', as represented in
4110 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4112 Return 1 if the operand was parsed successfully, zero
4116 i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch,
4117 struct stap_parse_info *p)
4119 const char *s = p->arg;
4121 if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+')
4123 int offset_minus = 0;
4132 struct stoken base_token, index_token;
4142 if (offset_minus && !isdigit (*s))
4149 offset = strtol (s, &endp, 10);
4153 if (*s != '(' || s[1] != '%')
4159 while (isalnum (*s))
4162 if (*s != ',' || s[1] != '%')
4165 len_base = s - start;
4166 base = alloca (len_base + 1);
4167 strncpy (base, start, len_base);
4168 base[len_base] = '\0';
4170 if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1)
4171 error (_("Invalid register name `%s' on expression `%s'."),
4172 base, p->saved_arg);
4177 while (isalnum (*s))
4180 len_index = s - start;
4181 index = alloca (len_index + 1);
4182 strncpy (index, start, len_index);
4183 index[len_index] = '\0';
4185 if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1)
4186 error (_("Invalid register name `%s' on expression `%s'."),
4187 index, p->saved_arg);
4189 if (*s != ',' && *s != ')')
4205 size = strtol (s, &endp, 10);
4216 write_exp_elt_opcode (&p->pstate, OP_LONG);
4217 write_exp_elt_type (&p->pstate,
4218 builtin_type (gdbarch)->builtin_long);
4219 write_exp_elt_longcst (&p->pstate, offset);
4220 write_exp_elt_opcode (&p->pstate, OP_LONG);
4222 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4225 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4226 base_token.ptr = base;
4227 base_token.length = len_base;
4228 write_exp_string (&p->pstate, base_token);
4229 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4232 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4234 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4235 index_token.ptr = index;
4236 index_token.length = len_index;
4237 write_exp_string (&p->pstate, index_token);
4238 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4242 write_exp_elt_opcode (&p->pstate, OP_LONG);
4243 write_exp_elt_type (&p->pstate,
4244 builtin_type (gdbarch)->builtin_long);
4245 write_exp_elt_longcst (&p->pstate, size);
4246 write_exp_elt_opcode (&p->pstate, OP_LONG);
4248 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4249 write_exp_elt_opcode (&p->pstate, BINOP_MUL);
4252 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4254 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4255 write_exp_elt_type (&p->pstate,
4256 lookup_pointer_type (p->arg_type));
4257 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4259 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4269 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4273 i386_stap_parse_special_token (struct gdbarch *gdbarch,
4274 struct stap_parse_info *p)
4276 /* In order to parse special tokens, we use a state-machine that go
4277 through every known token and try to get a match. */
4281 THREE_ARG_DISPLACEMENT,
4286 current_state = TRIPLET;
4288 /* The special tokens to be parsed here are:
4290 - `register base + (register index * size) + offset', as represented
4291 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4293 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4294 `*(-8 + 3 - 1 + (void *) $eax)'. */
4296 while (current_state != DONE)
4298 switch (current_state)
4301 if (i386_stap_parse_special_token_triplet (gdbarch, p))
4305 case THREE_ARG_DISPLACEMENT:
4306 if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p))
4311 /* Advancing to the next state. */
4320 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always
4321 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */
4324 i386_gnu_triplet_regexp (struct gdbarch *gdbarch)
4326 return "(x86_64|i.86)";
4334 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4336 static const char *const stap_integer_prefixes[] = { "$", NULL };
4337 static const char *const stap_register_prefixes[] = { "%", NULL };
4338 static const char *const stap_register_indirection_prefixes[] = { "(",
4340 static const char *const stap_register_indirection_suffixes[] = { ")",
4343 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4344 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4346 /* Registering SystemTap handlers. */
4347 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
4348 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
4349 set_gdbarch_stap_register_indirection_prefixes (gdbarch,
4350 stap_register_indirection_prefixes);
4351 set_gdbarch_stap_register_indirection_suffixes (gdbarch,
4352 stap_register_indirection_suffixes);
4353 set_gdbarch_stap_is_single_operand (gdbarch,
4354 i386_stap_is_single_operand);
4355 set_gdbarch_stap_parse_special_token (gdbarch,
4356 i386_stap_parse_special_token);
4358 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
4361 /* System V Release 4 (SVR4). */
4364 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4366 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4368 /* System V Release 4 uses ELF. */
4369 i386_elf_init_abi (info, gdbarch);
4371 /* System V Release 4 has shared libraries. */
4372 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
4374 tdep->sigtramp_p = i386_svr4_sigtramp_p;
4375 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
4376 tdep->sc_pc_offset = 36 + 14 * 4;
4377 tdep->sc_sp_offset = 36 + 17 * 4;
4379 tdep->jb_pc_offset = 20;
4385 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4387 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4389 /* DJGPP doesn't have any special frames for signal handlers. */
4390 tdep->sigtramp_p = NULL;
4392 tdep->jb_pc_offset = 36;
4394 /* DJGPP does not support the SSE registers. */
4395 if (! tdesc_has_registers (info.target_desc))
4396 tdep->tdesc = tdesc_i386_mmx;
4398 /* Native compiler is GCC, which uses the SVR4 register numbering
4399 even in COFF and STABS. See the comment in i386_gdbarch_init,
4400 before the calls to set_gdbarch_stab_reg_to_regnum and
4401 set_gdbarch_sdb_reg_to_regnum. */
4402 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4403 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4405 set_gdbarch_has_dos_based_file_system (gdbarch, 1);
4407 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
4411 /* i386 register groups. In addition to the normal groups, add "mmx"
4414 static struct reggroup *i386_sse_reggroup;
4415 static struct reggroup *i386_mmx_reggroup;
4418 i386_init_reggroups (void)
4420 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
4421 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
4425 i386_add_reggroups (struct gdbarch *gdbarch)
4427 reggroup_add (gdbarch, i386_sse_reggroup);
4428 reggroup_add (gdbarch, i386_mmx_reggroup);
4429 reggroup_add (gdbarch, general_reggroup);
4430 reggroup_add (gdbarch, float_reggroup);
4431 reggroup_add (gdbarch, all_reggroup);
4432 reggroup_add (gdbarch, save_reggroup);
4433 reggroup_add (gdbarch, restore_reggroup);
4434 reggroup_add (gdbarch, vector_reggroup);
4435 reggroup_add (gdbarch, system_reggroup);
4439 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
4440 struct reggroup *group)
4442 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4443 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
4444 ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p,
4445 bndr_regnum_p, bnd_regnum_p, k_regnum_p, zmm_regnum_p, zmmh_regnum_p,
4446 zmm_avx512_regnum_p, mpx_ctrl_regnum_p, xmm_avx512_regnum_p,
4447 avx512_p, avx_p, sse_p;
4449 /* Don't include pseudo registers, except for MMX, in any register
4451 if (i386_byte_regnum_p (gdbarch, regnum))
4454 if (i386_word_regnum_p (gdbarch, regnum))
4457 if (i386_dword_regnum_p (gdbarch, regnum))
4460 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
4461 if (group == i386_mmx_reggroup)
4462 return mmx_regnum_p;
4464 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
4465 xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum);
4466 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
4467 if (group == i386_sse_reggroup)
4468 return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p;
4470 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
4471 ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum);
4472 zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum);
4474 avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4475 == X86_XSTATE_AVX512_MASK);
4476 avx_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4477 == X86_XSTATE_AVX_MASK) && !avx512_p;
4478 sse_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4479 == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p;
4481 if (group == vector_reggroup)
4482 return (mmx_regnum_p
4483 || (zmm_regnum_p && avx512_p)
4484 || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p)
4485 || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p)
4488 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
4489 || i386_fpc_regnum_p (gdbarch, regnum));
4490 if (group == float_reggroup)
4493 /* For "info reg all", don't include upper YMM registers nor XMM
4494 registers when AVX is supported. */
4495 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
4496 ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum);
4497 zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum);
4498 if (group == all_reggroup
4499 && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p)
4500 || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p)
4502 || ymmh_avx512_regnum_p
4506 bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum);
4507 if (group == all_reggroup
4508 && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4509 return bnd_regnum_p;
4511 bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum);
4512 if (group == all_reggroup
4513 && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4516 mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum);
4517 if (group == all_reggroup
4518 && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4519 return mpx_ctrl_regnum_p;
4521 if (group == general_reggroup)
4522 return (!fp_regnum_p
4526 && !xmm_avx512_regnum_p
4529 && !ymm_avx512_regnum_p
4530 && !ymmh_avx512_regnum_p
4533 && !mpx_ctrl_regnum_p
4537 return default_register_reggroup_p (gdbarch, regnum, group);
4541 /* Get the ARGIth function argument for the current function. */
4544 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
4547 struct gdbarch *gdbarch = get_frame_arch (frame);
4548 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4549 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
4550 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
4553 #define PREFIX_REPZ 0x01
4554 #define PREFIX_REPNZ 0x02
4555 #define PREFIX_LOCK 0x04
4556 #define PREFIX_DATA 0x08
4557 #define PREFIX_ADDR 0x10
4569 /* i386 arith/logic operations */
4582 struct i386_record_s
4584 struct gdbarch *gdbarch;
4585 struct regcache *regcache;
4586 CORE_ADDR orig_addr;
4592 uint8_t mod, reg, rm;
4601 /* Parse the "modrm" part of the memory address irp->addr points at.
4602 Returns -1 if something goes wrong, 0 otherwise. */
4605 i386_record_modrm (struct i386_record_s *irp)
4607 struct gdbarch *gdbarch = irp->gdbarch;
4609 if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1))
4613 irp->mod = (irp->modrm >> 6) & 3;
4614 irp->reg = (irp->modrm >> 3) & 7;
4615 irp->rm = irp->modrm & 7;
4620 /* Extract the memory address that the current instruction writes to,
4621 and return it in *ADDR. Return -1 if something goes wrong. */
4624 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
4626 struct gdbarch *gdbarch = irp->gdbarch;
4627 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4632 if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM])
4639 uint8_t base = irp->rm;
4644 if (record_read_memory (gdbarch, irp->addr, &byte, 1))
4647 scale = (byte >> 6) & 3;
4648 index = ((byte >> 3) & 7) | irp->rex_x;
4656 if ((base & 7) == 5)
4659 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4662 *addr = extract_signed_integer (buf, 4, byte_order);
4663 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
4664 *addr += irp->addr + irp->rip_offset;
4668 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4671 *addr = (int8_t) buf[0];
4674 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4676 *addr = extract_signed_integer (buf, 4, byte_order);
4684 if (base == 4 && irp->popl_esp_hack)
4685 *addr += irp->popl_esp_hack;
4686 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
4689 if (irp->aflag == 2)
4694 *addr = (uint32_t) (offset64 + *addr);
4696 if (havesib && (index != 4 || scale != 0))
4698 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
4700 if (irp->aflag == 2)
4701 *addr += offset64 << scale;
4703 *addr = (uint32_t) (*addr + (offset64 << scale));
4708 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4709 address from 32-bit to 64-bit. */
4710 *addr = (uint32_t) *addr;
4721 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4724 *addr = extract_signed_integer (buf, 2, byte_order);
4730 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4733 *addr = (int8_t) buf[0];
4736 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4739 *addr = extract_signed_integer (buf, 2, byte_order);
4746 regcache_raw_read_unsigned (irp->regcache,
4747 irp->regmap[X86_RECORD_REBX_REGNUM],
4749 *addr = (uint32_t) (*addr + offset64);
4750 regcache_raw_read_unsigned (irp->regcache,
4751 irp->regmap[X86_RECORD_RESI_REGNUM],
4753 *addr = (uint32_t) (*addr + offset64);
4756 regcache_raw_read_unsigned (irp->regcache,
4757 irp->regmap[X86_RECORD_REBX_REGNUM],
4759 *addr = (uint32_t) (*addr + offset64);
4760 regcache_raw_read_unsigned (irp->regcache,
4761 irp->regmap[X86_RECORD_REDI_REGNUM],
4763 *addr = (uint32_t) (*addr + offset64);
4766 regcache_raw_read_unsigned (irp->regcache,
4767 irp->regmap[X86_RECORD_REBP_REGNUM],
4769 *addr = (uint32_t) (*addr + offset64);
4770 regcache_raw_read_unsigned (irp->regcache,
4771 irp->regmap[X86_RECORD_RESI_REGNUM],
4773 *addr = (uint32_t) (*addr + offset64);
4776 regcache_raw_read_unsigned (irp->regcache,
4777 irp->regmap[X86_RECORD_REBP_REGNUM],
4779 *addr = (uint32_t) (*addr + offset64);
4780 regcache_raw_read_unsigned (irp->regcache,
4781 irp->regmap[X86_RECORD_REDI_REGNUM],
4783 *addr = (uint32_t) (*addr + offset64);
4786 regcache_raw_read_unsigned (irp->regcache,
4787 irp->regmap[X86_RECORD_RESI_REGNUM],
4789 *addr = (uint32_t) (*addr + offset64);
4792 regcache_raw_read_unsigned (irp->regcache,
4793 irp->regmap[X86_RECORD_REDI_REGNUM],
4795 *addr = (uint32_t) (*addr + offset64);
4798 regcache_raw_read_unsigned (irp->regcache,
4799 irp->regmap[X86_RECORD_REBP_REGNUM],
4801 *addr = (uint32_t) (*addr + offset64);
4804 regcache_raw_read_unsigned (irp->regcache,
4805 irp->regmap[X86_RECORD_REBX_REGNUM],
4807 *addr = (uint32_t) (*addr + offset64);
4817 /* Record the address and contents of the memory that will be changed
4818 by the current instruction. Return -1 if something goes wrong, 0
4822 i386_record_lea_modrm (struct i386_record_s *irp)
4824 struct gdbarch *gdbarch = irp->gdbarch;
4827 if (irp->override >= 0)
4829 if (record_full_memory_query)
4833 target_terminal_ours ();
4835 Process record ignores the memory change of instruction at address %s\n\
4836 because it can't get the value of the segment register.\n\
4837 Do you want to stop the program?"),
4838 paddress (gdbarch, irp->orig_addr));
4839 target_terminal_inferior ();
4847 if (i386_record_lea_modrm_addr (irp, &addr))
4850 if (record_full_arch_list_add_mem (addr, 1 << irp->ot))
4856 /* Record the effects of a push operation. Return -1 if something
4857 goes wrong, 0 otherwise. */
4860 i386_record_push (struct i386_record_s *irp, int size)
4864 if (record_full_arch_list_add_reg (irp->regcache,
4865 irp->regmap[X86_RECORD_RESP_REGNUM]))
4867 regcache_raw_read_unsigned (irp->regcache,
4868 irp->regmap[X86_RECORD_RESP_REGNUM],
4870 if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size))
4877 /* Defines contents to record. */
4878 #define I386_SAVE_FPU_REGS 0xfffd
4879 #define I386_SAVE_FPU_ENV 0xfffe
4880 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4882 /* Record the values of the floating point registers which will be
4883 changed by the current instruction. Returns -1 if something is
4884 wrong, 0 otherwise. */
4886 static int i386_record_floats (struct gdbarch *gdbarch,
4887 struct i386_record_s *ir,
4890 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4893 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4894 happen. Currently we store st0-st7 registers, but we need not store all
4895 registers all the time, in future we use ftag register and record only
4896 those who are not marked as an empty. */
4898 if (I386_SAVE_FPU_REGS == iregnum)
4900 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
4902 if (record_full_arch_list_add_reg (ir->regcache, i))
4906 else if (I386_SAVE_FPU_ENV == iregnum)
4908 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4910 if (record_full_arch_list_add_reg (ir->regcache, i))
4914 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
4916 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4918 if (record_full_arch_list_add_reg (ir->regcache, i))
4922 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
4923 (iregnum <= I387_FOP_REGNUM (tdep)))
4925 if (record_full_arch_list_add_reg (ir->regcache,iregnum))
4930 /* Parameter error. */
4933 if(I386_SAVE_FPU_ENV != iregnum)
4935 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4937 if (record_full_arch_list_add_reg (ir->regcache, i))
4944 /* Parse the current instruction, and record the values of the
4945 registers and memory that will be changed by the current
4946 instruction. Returns -1 if something goes wrong, 0 otherwise. */
4948 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
4949 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
4952 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
4953 CORE_ADDR input_addr)
4955 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4961 gdb_byte buf[MAX_REGISTER_SIZE];
4962 struct i386_record_s ir;
4963 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4967 memset (&ir, 0, sizeof (struct i386_record_s));
4968 ir.regcache = regcache;
4969 ir.addr = input_addr;
4970 ir.orig_addr = input_addr;
4974 ir.popl_esp_hack = 0;
4975 ir.regmap = tdep->record_regmap;
4976 ir.gdbarch = gdbarch;
4978 if (record_debug > 1)
4979 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
4981 paddress (gdbarch, ir.addr));
4986 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
4989 switch (opcode8) /* Instruction prefixes */
4991 case REPE_PREFIX_OPCODE:
4992 prefixes |= PREFIX_REPZ;
4994 case REPNE_PREFIX_OPCODE:
4995 prefixes |= PREFIX_REPNZ;
4997 case LOCK_PREFIX_OPCODE:
4998 prefixes |= PREFIX_LOCK;
5000 case CS_PREFIX_OPCODE:
5001 ir.override = X86_RECORD_CS_REGNUM;
5003 case SS_PREFIX_OPCODE:
5004 ir.override = X86_RECORD_SS_REGNUM;
5006 case DS_PREFIX_OPCODE:
5007 ir.override = X86_RECORD_DS_REGNUM;
5009 case ES_PREFIX_OPCODE:
5010 ir.override = X86_RECORD_ES_REGNUM;
5012 case FS_PREFIX_OPCODE:
5013 ir.override = X86_RECORD_FS_REGNUM;
5015 case GS_PREFIX_OPCODE:
5016 ir.override = X86_RECORD_GS_REGNUM;
5018 case DATA_PREFIX_OPCODE:
5019 prefixes |= PREFIX_DATA;
5021 case ADDR_PREFIX_OPCODE:
5022 prefixes |= PREFIX_ADDR;
5024 case 0x40: /* i386 inc %eax */
5025 case 0x41: /* i386 inc %ecx */
5026 case 0x42: /* i386 inc %edx */
5027 case 0x43: /* i386 inc %ebx */
5028 case 0x44: /* i386 inc %esp */
5029 case 0x45: /* i386 inc %ebp */
5030 case 0x46: /* i386 inc %esi */
5031 case 0x47: /* i386 inc %edi */
5032 case 0x48: /* i386 dec %eax */
5033 case 0x49: /* i386 dec %ecx */
5034 case 0x4a: /* i386 dec %edx */
5035 case 0x4b: /* i386 dec %ebx */
5036 case 0x4c: /* i386 dec %esp */
5037 case 0x4d: /* i386 dec %ebp */
5038 case 0x4e: /* i386 dec %esi */
5039 case 0x4f: /* i386 dec %edi */
5040 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
5043 rex_w = (opcode8 >> 3) & 1;
5044 rex_r = (opcode8 & 0x4) << 1;
5045 ir.rex_x = (opcode8 & 0x2) << 2;
5046 ir.rex_b = (opcode8 & 0x1) << 3;
5048 else /* 32 bit target */
5057 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
5063 if (prefixes & PREFIX_DATA)
5066 if (prefixes & PREFIX_ADDR)
5068 else if (ir.regmap[X86_RECORD_R8_REGNUM])
5071 /* Now check op code. */
5072 opcode = (uint32_t) opcode8;
5077 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5080 opcode = (uint32_t) opcode8 | 0x0f00;
5084 case 0x00: /* arith & logic */
5132 if (((opcode >> 3) & 7) != OP_CMPL)
5134 if ((opcode & 1) == 0)
5137 ir.ot = ir.dflag + OT_WORD;
5139 switch ((opcode >> 1) & 3)
5141 case 0: /* OP Ev, Gv */
5142 if (i386_record_modrm (&ir))
5146 if (i386_record_lea_modrm (&ir))
5152 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5154 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5157 case 1: /* OP Gv, Ev */
5158 if (i386_record_modrm (&ir))
5161 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5163 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5165 case 2: /* OP A, Iv */
5166 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5170 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5173 case 0x80: /* GRP1 */
5177 if (i386_record_modrm (&ir))
5180 if (ir.reg != OP_CMPL)
5182 if ((opcode & 1) == 0)
5185 ir.ot = ir.dflag + OT_WORD;
5192 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5193 if (i386_record_lea_modrm (&ir))
5197 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5199 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5202 case 0x40: /* inc */
5211 case 0x48: /* dec */
5220 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7);
5221 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5224 case 0xf6: /* GRP3 */
5226 if ((opcode & 1) == 0)
5229 ir.ot = ir.dflag + OT_WORD;
5230 if (i386_record_modrm (&ir))
5233 if (ir.mod != 3 && ir.reg == 0)
5234 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5239 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5245 if (i386_record_lea_modrm (&ir))
5251 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5253 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5255 if (ir.reg == 3) /* neg */
5256 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5262 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5263 if (ir.ot != OT_BYTE)
5264 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5265 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5269 opcode = opcode << 8 | ir.modrm;
5275 case 0xfe: /* GRP4 */
5276 case 0xff: /* GRP5 */
5277 if (i386_record_modrm (&ir))
5279 if (ir.reg >= 2 && opcode == 0xfe)
5282 opcode = opcode << 8 | ir.modrm;
5289 if ((opcode & 1) == 0)
5292 ir.ot = ir.dflag + OT_WORD;
5295 if (i386_record_lea_modrm (&ir))
5301 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5303 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5305 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5308 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5310 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5312 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5315 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5316 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5318 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5322 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5325 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5327 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5332 opcode = opcode << 8 | ir.modrm;
5338 case 0x84: /* test */
5342 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5345 case 0x98: /* CWDE/CBW */
5346 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5349 case 0x99: /* CDQ/CWD */
5350 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5351 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5354 case 0x0faf: /* imul */
5357 ir.ot = ir.dflag + OT_WORD;
5358 if (i386_record_modrm (&ir))
5361 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5362 else if (opcode == 0x6b)
5365 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5367 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5368 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5371 case 0x0fc0: /* xadd */
5373 if ((opcode & 1) == 0)
5376 ir.ot = ir.dflag + OT_WORD;
5377 if (i386_record_modrm (&ir))
5382 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5384 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5385 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5387 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5391 if (i386_record_lea_modrm (&ir))
5393 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5395 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5397 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5400 case 0x0fb0: /* cmpxchg */
5402 if ((opcode & 1) == 0)
5405 ir.ot = ir.dflag + OT_WORD;
5406 if (i386_record_modrm (&ir))
5411 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5412 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5414 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5418 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5419 if (i386_record_lea_modrm (&ir))
5422 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5425 case 0x0fc7: /* cmpxchg8b */
5426 if (i386_record_modrm (&ir))
5431 opcode = opcode << 8 | ir.modrm;
5434 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5435 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5436 if (i386_record_lea_modrm (&ir))
5438 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5441 case 0x50: /* push */
5451 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5453 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5457 case 0x06: /* push es */
5458 case 0x0e: /* push cs */
5459 case 0x16: /* push ss */
5460 case 0x1e: /* push ds */
5461 if (ir.regmap[X86_RECORD_R8_REGNUM])
5466 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5470 case 0x0fa0: /* push fs */
5471 case 0x0fa8: /* push gs */
5472 if (ir.regmap[X86_RECORD_R8_REGNUM])
5477 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5481 case 0x60: /* pusha */
5482 if (ir.regmap[X86_RECORD_R8_REGNUM])
5487 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
5491 case 0x58: /* pop */
5499 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5500 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5503 case 0x61: /* popa */
5504 if (ir.regmap[X86_RECORD_R8_REGNUM])
5509 for (regnum = X86_RECORD_REAX_REGNUM;
5510 regnum <= X86_RECORD_REDI_REGNUM;
5512 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5515 case 0x8f: /* pop */
5516 if (ir.regmap[X86_RECORD_R8_REGNUM])
5517 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
5519 ir.ot = ir.dflag + OT_WORD;
5520 if (i386_record_modrm (&ir))
5523 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5526 ir.popl_esp_hack = 1 << ir.ot;
5527 if (i386_record_lea_modrm (&ir))
5530 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5533 case 0xc8: /* enter */
5534 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5535 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5537 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5541 case 0xc9: /* leave */
5542 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5543 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5546 case 0x07: /* pop es */
5547 if (ir.regmap[X86_RECORD_R8_REGNUM])
5552 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5553 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
5554 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5557 case 0x17: /* pop ss */
5558 if (ir.regmap[X86_RECORD_R8_REGNUM])
5563 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5564 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
5565 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5568 case 0x1f: /* pop ds */
5569 if (ir.regmap[X86_RECORD_R8_REGNUM])
5574 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5575 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
5576 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5579 case 0x0fa1: /* pop fs */
5580 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5581 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
5582 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5585 case 0x0fa9: /* pop gs */
5586 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5587 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
5588 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5591 case 0x88: /* mov */
5595 if ((opcode & 1) == 0)
5598 ir.ot = ir.dflag + OT_WORD;
5600 if (i386_record_modrm (&ir))
5605 if (opcode == 0xc6 || opcode == 0xc7)
5606 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5607 if (i386_record_lea_modrm (&ir))
5612 if (opcode == 0xc6 || opcode == 0xc7)
5614 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5616 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5620 case 0x8a: /* mov */
5622 if ((opcode & 1) == 0)
5625 ir.ot = ir.dflag + OT_WORD;
5626 if (i386_record_modrm (&ir))
5629 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5631 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5634 case 0x8c: /* mov seg */
5635 if (i386_record_modrm (&ir))
5640 opcode = opcode << 8 | ir.modrm;
5645 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5649 if (i386_record_lea_modrm (&ir))
5654 case 0x8e: /* mov seg */
5655 if (i386_record_modrm (&ir))
5660 regnum = X86_RECORD_ES_REGNUM;
5663 regnum = X86_RECORD_SS_REGNUM;
5666 regnum = X86_RECORD_DS_REGNUM;
5669 regnum = X86_RECORD_FS_REGNUM;
5672 regnum = X86_RECORD_GS_REGNUM;
5676 opcode = opcode << 8 | ir.modrm;
5680 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5681 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5684 case 0x0fb6: /* movzbS */
5685 case 0x0fb7: /* movzwS */
5686 case 0x0fbe: /* movsbS */
5687 case 0x0fbf: /* movswS */
5688 if (i386_record_modrm (&ir))
5690 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5693 case 0x8d: /* lea */
5694 if (i386_record_modrm (&ir))
5699 opcode = opcode << 8 | ir.modrm;
5704 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5706 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5709 case 0xa0: /* mov EAX */
5712 case 0xd7: /* xlat */
5713 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5716 case 0xa2: /* mov EAX */
5718 if (ir.override >= 0)
5720 if (record_full_memory_query)
5724 target_terminal_ours ();
5726 Process record ignores the memory change of instruction at address %s\n\
5727 because it can't get the value of the segment register.\n\
5728 Do you want to stop the program?"),
5729 paddress (gdbarch, ir.orig_addr));
5730 target_terminal_inferior ();
5737 if ((opcode & 1) == 0)
5740 ir.ot = ir.dflag + OT_WORD;
5743 if (record_read_memory (gdbarch, ir.addr, buf, 8))
5746 addr = extract_unsigned_integer (buf, 8, byte_order);
5750 if (record_read_memory (gdbarch, ir.addr, buf, 4))
5753 addr = extract_unsigned_integer (buf, 4, byte_order);
5757 if (record_read_memory (gdbarch, ir.addr, buf, 2))
5760 addr = extract_unsigned_integer (buf, 2, byte_order);
5762 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
5767 case 0xb0: /* mov R, Ib */
5775 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
5776 ? ((opcode & 0x7) | ir.rex_b)
5777 : ((opcode & 0x7) & 0x3));
5780 case 0xb8: /* mov R, Iv */
5788 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5791 case 0x91: /* xchg R, EAX */
5798 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5799 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7);
5802 case 0x86: /* xchg Ev, Gv */
5804 if ((opcode & 1) == 0)
5807 ir.ot = ir.dflag + OT_WORD;
5808 if (i386_record_modrm (&ir))
5813 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5815 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5819 if (i386_record_lea_modrm (&ir))
5823 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5825 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5828 case 0xc4: /* les Gv */
5829 case 0xc5: /* lds Gv */
5830 if (ir.regmap[X86_RECORD_R8_REGNUM])
5836 case 0x0fb2: /* lss Gv */
5837 case 0x0fb4: /* lfs Gv */
5838 case 0x0fb5: /* lgs Gv */
5839 if (i386_record_modrm (&ir))
5847 opcode = opcode << 8 | ir.modrm;
5852 case 0xc4: /* les Gv */
5853 regnum = X86_RECORD_ES_REGNUM;
5855 case 0xc5: /* lds Gv */
5856 regnum = X86_RECORD_DS_REGNUM;
5858 case 0x0fb2: /* lss Gv */
5859 regnum = X86_RECORD_SS_REGNUM;
5861 case 0x0fb4: /* lfs Gv */
5862 regnum = X86_RECORD_FS_REGNUM;
5864 case 0x0fb5: /* lgs Gv */
5865 regnum = X86_RECORD_GS_REGNUM;
5868 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5869 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5870 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5873 case 0xc0: /* shifts */
5879 if ((opcode & 1) == 0)
5882 ir.ot = ir.dflag + OT_WORD;
5883 if (i386_record_modrm (&ir))
5885 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
5887 if (i386_record_lea_modrm (&ir))
5893 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5895 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5897 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5904 if (i386_record_modrm (&ir))
5908 if (record_full_arch_list_add_reg (ir.regcache, ir.rm))
5913 if (i386_record_lea_modrm (&ir))
5918 case 0xd8: /* Floats. */
5926 if (i386_record_modrm (&ir))
5928 ir.reg |= ((opcode & 7) << 3);
5934 if (i386_record_lea_modrm_addr (&ir, &addr64))
5942 /* For fcom, ficom nothing to do. */
5948 /* For fcomp, ficomp pop FPU stack, store all. */
5949 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5976 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5977 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5978 of code, always affects st(0) register. */
5979 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6003 /* Handling fld, fild. */
6004 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6008 switch (ir.reg >> 4)
6011 if (record_full_arch_list_add_mem (addr64, 4))
6015 if (record_full_arch_list_add_mem (addr64, 8))
6021 if (record_full_arch_list_add_mem (addr64, 2))
6027 switch (ir.reg >> 4)
6030 if (record_full_arch_list_add_mem (addr64, 4))
6032 if (3 == (ir.reg & 7))
6034 /* For fstp m32fp. */
6035 if (i386_record_floats (gdbarch, &ir,
6036 I386_SAVE_FPU_REGS))
6041 if (record_full_arch_list_add_mem (addr64, 4))
6043 if ((3 == (ir.reg & 7))
6044 || (5 == (ir.reg & 7))
6045 || (7 == (ir.reg & 7)))
6047 /* For fstp insn. */
6048 if (i386_record_floats (gdbarch, &ir,
6049 I386_SAVE_FPU_REGS))
6054 if (record_full_arch_list_add_mem (addr64, 8))
6056 if (3 == (ir.reg & 7))
6058 /* For fstp m64fp. */
6059 if (i386_record_floats (gdbarch, &ir,
6060 I386_SAVE_FPU_REGS))
6065 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
6067 /* For fistp, fbld, fild, fbstp. */
6068 if (i386_record_floats (gdbarch, &ir,
6069 I386_SAVE_FPU_REGS))
6074 if (record_full_arch_list_add_mem (addr64, 2))
6083 if (i386_record_floats (gdbarch, &ir,
6084 I386_SAVE_FPU_ENV_REG_STACK))
6089 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
6094 if (i386_record_floats (gdbarch, &ir,
6095 I386_SAVE_FPU_ENV_REG_STACK))
6101 if (record_full_arch_list_add_mem (addr64, 28))
6106 if (record_full_arch_list_add_mem (addr64, 14))
6112 if (record_full_arch_list_add_mem (addr64, 2))
6114 /* Insn fstp, fbstp. */
6115 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6120 if (record_full_arch_list_add_mem (addr64, 10))
6126 if (record_full_arch_list_add_mem (addr64, 28))
6132 if (record_full_arch_list_add_mem (addr64, 14))
6136 if (record_full_arch_list_add_mem (addr64, 80))
6139 if (i386_record_floats (gdbarch, &ir,
6140 I386_SAVE_FPU_ENV_REG_STACK))
6144 if (record_full_arch_list_add_mem (addr64, 8))
6147 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6152 opcode = opcode << 8 | ir.modrm;
6157 /* Opcode is an extension of modR/M byte. */
6163 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6167 if (0x0c == (ir.modrm >> 4))
6169 if ((ir.modrm & 0x0f) <= 7)
6171 if (i386_record_floats (gdbarch, &ir,
6172 I386_SAVE_FPU_REGS))
6177 if (i386_record_floats (gdbarch, &ir,
6178 I387_ST0_REGNUM (tdep)))
6180 /* If only st(0) is changing, then we have already
6182 if ((ir.modrm & 0x0f) - 0x08)
6184 if (i386_record_floats (gdbarch, &ir,
6185 I387_ST0_REGNUM (tdep) +
6186 ((ir.modrm & 0x0f) - 0x08)))
6204 if (i386_record_floats (gdbarch, &ir,
6205 I387_ST0_REGNUM (tdep)))
6223 if (i386_record_floats (gdbarch, &ir,
6224 I386_SAVE_FPU_REGS))
6228 if (i386_record_floats (gdbarch, &ir,
6229 I387_ST0_REGNUM (tdep)))
6231 if (i386_record_floats (gdbarch, &ir,
6232 I387_ST0_REGNUM (tdep) + 1))
6239 if (0xe9 == ir.modrm)
6241 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6244 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6246 if (i386_record_floats (gdbarch, &ir,
6247 I387_ST0_REGNUM (tdep)))
6249 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6251 if (i386_record_floats (gdbarch, &ir,
6252 I387_ST0_REGNUM (tdep) +
6256 else if ((ir.modrm & 0x0f) - 0x08)
6258 if (i386_record_floats (gdbarch, &ir,
6259 I387_ST0_REGNUM (tdep) +
6260 ((ir.modrm & 0x0f) - 0x08)))
6266 if (0xe3 == ir.modrm)
6268 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
6271 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6273 if (i386_record_floats (gdbarch, &ir,
6274 I387_ST0_REGNUM (tdep)))
6276 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6278 if (i386_record_floats (gdbarch, &ir,
6279 I387_ST0_REGNUM (tdep) +
6283 else if ((ir.modrm & 0x0f) - 0x08)
6285 if (i386_record_floats (gdbarch, &ir,
6286 I387_ST0_REGNUM (tdep) +
6287 ((ir.modrm & 0x0f) - 0x08)))
6293 if ((0x0c == ir.modrm >> 4)
6294 || (0x0d == ir.modrm >> 4)
6295 || (0x0f == ir.modrm >> 4))
6297 if ((ir.modrm & 0x0f) <= 7)
6299 if (i386_record_floats (gdbarch, &ir,
6300 I387_ST0_REGNUM (tdep) +
6306 if (i386_record_floats (gdbarch, &ir,
6307 I387_ST0_REGNUM (tdep) +
6308 ((ir.modrm & 0x0f) - 0x08)))
6314 if (0x0c == ir.modrm >> 4)
6316 if (i386_record_floats (gdbarch, &ir,
6317 I387_FTAG_REGNUM (tdep)))
6320 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6322 if ((ir.modrm & 0x0f) <= 7)
6324 if (i386_record_floats (gdbarch, &ir,
6325 I387_ST0_REGNUM (tdep) +
6331 if (i386_record_floats (gdbarch, &ir,
6332 I386_SAVE_FPU_REGS))
6338 if ((0x0c == ir.modrm >> 4)
6339 || (0x0e == ir.modrm >> 4)
6340 || (0x0f == ir.modrm >> 4)
6341 || (0xd9 == ir.modrm))
6343 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6348 if (0xe0 == ir.modrm)
6350 if (record_full_arch_list_add_reg (ir.regcache,
6354 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6356 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6364 case 0xa4: /* movsS */
6366 case 0xaa: /* stosS */
6368 case 0x6c: /* insS */
6370 regcache_raw_read_unsigned (ir.regcache,
6371 ir.regmap[X86_RECORD_RECX_REGNUM],
6377 if ((opcode & 1) == 0)
6380 ir.ot = ir.dflag + OT_WORD;
6381 regcache_raw_read_unsigned (ir.regcache,
6382 ir.regmap[X86_RECORD_REDI_REGNUM],
6385 regcache_raw_read_unsigned (ir.regcache,
6386 ir.regmap[X86_RECORD_ES_REGNUM],
6388 regcache_raw_read_unsigned (ir.regcache,
6389 ir.regmap[X86_RECORD_DS_REGNUM],
6391 if (ir.aflag && (es != ds))
6393 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6394 if (record_full_memory_query)
6398 target_terminal_ours ();
6400 Process record ignores the memory change of instruction at address %s\n\
6401 because it can't get the value of the segment register.\n\
6402 Do you want to stop the program?"),
6403 paddress (gdbarch, ir.orig_addr));
6404 target_terminal_inferior ();
6411 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
6415 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6416 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6417 if (opcode == 0xa4 || opcode == 0xa5)
6418 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6419 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6420 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6424 case 0xa6: /* cmpsS */
6426 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6427 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6428 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6429 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6430 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6433 case 0xac: /* lodsS */
6435 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6436 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6437 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6438 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6439 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6442 case 0xae: /* scasS */
6444 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6445 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6446 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6447 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6450 case 0x6e: /* outsS */
6452 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6453 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6454 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6455 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6458 case 0xe4: /* port I/O */
6462 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6463 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6473 case 0xc2: /* ret im */
6474 case 0xc3: /* ret */
6475 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6476 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6479 case 0xca: /* lret im */
6480 case 0xcb: /* lret */
6481 case 0xcf: /* iret */
6482 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6483 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6484 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6487 case 0xe8: /* call im */
6488 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6490 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6494 case 0x9a: /* lcall im */
6495 if (ir.regmap[X86_RECORD_R8_REGNUM])
6500 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6501 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6505 case 0xe9: /* jmp im */
6506 case 0xea: /* ljmp im */
6507 case 0xeb: /* jmp Jb */
6508 case 0x70: /* jcc Jb */
6524 case 0x0f80: /* jcc Jv */
6542 case 0x0f90: /* setcc Gv */
6558 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6560 if (i386_record_modrm (&ir))
6563 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
6567 if (i386_record_lea_modrm (&ir))
6572 case 0x0f40: /* cmov Gv, Ev */
6588 if (i386_record_modrm (&ir))
6591 if (ir.dflag == OT_BYTE)
6593 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
6597 case 0x9c: /* pushf */
6598 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6599 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6601 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6605 case 0x9d: /* popf */
6606 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6607 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6610 case 0x9e: /* sahf */
6611 if (ir.regmap[X86_RECORD_R8_REGNUM])
6617 case 0xf5: /* cmc */
6618 case 0xf8: /* clc */
6619 case 0xf9: /* stc */
6620 case 0xfc: /* cld */
6621 case 0xfd: /* std */
6622 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6625 case 0x9f: /* lahf */
6626 if (ir.regmap[X86_RECORD_R8_REGNUM])
6631 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6632 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6635 /* bit operations */
6636 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6637 ir.ot = ir.dflag + OT_WORD;
6638 if (i386_record_modrm (&ir))
6643 opcode = opcode << 8 | ir.modrm;
6649 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6652 if (i386_record_lea_modrm (&ir))
6656 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6659 case 0x0fa3: /* bt Gv, Ev */
6660 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6663 case 0x0fab: /* bts */
6664 case 0x0fb3: /* btr */
6665 case 0x0fbb: /* btc */
6666 ir.ot = ir.dflag + OT_WORD;
6667 if (i386_record_modrm (&ir))
6670 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6674 if (i386_record_lea_modrm_addr (&ir, &addr64))
6676 regcache_raw_read_unsigned (ir.regcache,
6677 ir.regmap[ir.reg | rex_r],
6682 addr64 += ((int16_t) addr >> 4) << 4;
6685 addr64 += ((int32_t) addr >> 5) << 5;
6688 addr64 += ((int64_t) addr >> 6) << 6;
6691 if (record_full_arch_list_add_mem (addr64, 1 << ir.ot))
6693 if (i386_record_lea_modrm (&ir))
6696 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6699 case 0x0fbc: /* bsf */
6700 case 0x0fbd: /* bsr */
6701 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6702 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6706 case 0x27: /* daa */
6707 case 0x2f: /* das */
6708 case 0x37: /* aaa */
6709 case 0x3f: /* aas */
6710 case 0xd4: /* aam */
6711 case 0xd5: /* aad */
6712 if (ir.regmap[X86_RECORD_R8_REGNUM])
6717 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6718 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6722 case 0x90: /* nop */
6723 if (prefixes & PREFIX_LOCK)
6730 case 0x9b: /* fwait */
6731 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
6733 opcode = (uint32_t) opcode8;
6739 case 0xcc: /* int3 */
6740 printf_unfiltered (_("Process record does not support instruction "
6747 case 0xcd: /* int */
6751 if (record_read_memory (gdbarch, ir.addr, &interrupt, 1))
6754 if (interrupt != 0x80
6755 || tdep->i386_intx80_record == NULL)
6757 printf_unfiltered (_("Process record does not support "
6758 "instruction int 0x%02x.\n"),
6763 ret = tdep->i386_intx80_record (ir.regcache);
6770 case 0xce: /* into */
6771 printf_unfiltered (_("Process record does not support "
6772 "instruction into.\n"));
6777 case 0xfa: /* cli */
6778 case 0xfb: /* sti */
6781 case 0x62: /* bound */
6782 printf_unfiltered (_("Process record does not support "
6783 "instruction bound.\n"));
6788 case 0x0fc8: /* bswap reg */
6796 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
6799 case 0xd6: /* salc */
6800 if (ir.regmap[X86_RECORD_R8_REGNUM])
6805 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6806 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6809 case 0xe0: /* loopnz */
6810 case 0xe1: /* loopz */
6811 case 0xe2: /* loop */
6812 case 0xe3: /* jecxz */
6813 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6814 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6817 case 0x0f30: /* wrmsr */
6818 printf_unfiltered (_("Process record does not support "
6819 "instruction wrmsr.\n"));
6824 case 0x0f32: /* rdmsr */
6825 printf_unfiltered (_("Process record does not support "
6826 "instruction rdmsr.\n"));
6831 case 0x0f31: /* rdtsc */
6832 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6833 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6836 case 0x0f34: /* sysenter */
6839 if (ir.regmap[X86_RECORD_R8_REGNUM])
6844 if (tdep->i386_sysenter_record == NULL)
6846 printf_unfiltered (_("Process record does not support "
6847 "instruction sysenter.\n"));
6851 ret = tdep->i386_sysenter_record (ir.regcache);
6857 case 0x0f35: /* sysexit */
6858 printf_unfiltered (_("Process record does not support "
6859 "instruction sysexit.\n"));
6864 case 0x0f05: /* syscall */
6867 if (tdep->i386_syscall_record == NULL)
6869 printf_unfiltered (_("Process record does not support "
6870 "instruction syscall.\n"));
6874 ret = tdep->i386_syscall_record (ir.regcache);
6880 case 0x0f07: /* sysret */
6881 printf_unfiltered (_("Process record does not support "
6882 "instruction sysret.\n"));
6887 case 0x0fa2: /* cpuid */
6888 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6889 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6890 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6891 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
6894 case 0xf4: /* hlt */
6895 printf_unfiltered (_("Process record does not support "
6896 "instruction hlt.\n"));
6902 if (i386_record_modrm (&ir))
6909 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6913 if (i386_record_lea_modrm (&ir))
6922 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6926 opcode = opcode << 8 | ir.modrm;
6933 if (i386_record_modrm (&ir))
6944 opcode = opcode << 8 | ir.modrm;
6947 if (ir.override >= 0)
6949 if (record_full_memory_query)
6953 target_terminal_ours ();
6955 Process record ignores the memory change of instruction at address %s\n\
6956 because it can't get the value of the segment register.\n\
6957 Do you want to stop the program?"),
6958 paddress (gdbarch, ir.orig_addr));
6959 target_terminal_inferior ();
6966 if (i386_record_lea_modrm_addr (&ir, &addr64))
6968 if (record_full_arch_list_add_mem (addr64, 2))
6971 if (ir.regmap[X86_RECORD_R8_REGNUM])
6973 if (record_full_arch_list_add_mem (addr64, 8))
6978 if (record_full_arch_list_add_mem (addr64, 4))
6989 case 0: /* monitor */
6992 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6996 opcode = opcode << 8 | ir.modrm;
7004 if (ir.override >= 0)
7006 if (record_full_memory_query)
7010 target_terminal_ours ();
7012 Process record ignores the memory change of instruction at address %s\n\
7013 because it can't get the value of the segment register.\n\
7014 Do you want to stop the program?"),
7015 paddress (gdbarch, ir.orig_addr));
7016 target_terminal_inferior ();
7025 if (i386_record_lea_modrm_addr (&ir, &addr64))
7027 if (record_full_arch_list_add_mem (addr64, 2))
7030 if (ir.regmap[X86_RECORD_R8_REGNUM])
7032 if (record_full_arch_list_add_mem (addr64, 8))
7037 if (record_full_arch_list_add_mem (addr64, 4))
7049 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7050 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7054 else if (ir.rm == 1)
7061 opcode = opcode << 8 | ir.modrm;
7068 if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
7074 if (i386_record_lea_modrm (&ir))
7077 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7080 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7082 case 7: /* invlpg */
7085 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
7086 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
7090 opcode = opcode << 8 | ir.modrm;
7095 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7099 opcode = opcode << 8 | ir.modrm;
7105 case 0x0f08: /* invd */
7106 case 0x0f09: /* wbinvd */
7109 case 0x63: /* arpl */
7110 if (i386_record_modrm (&ir))
7112 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
7114 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
7115 ? (ir.reg | rex_r) : ir.rm);
7119 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
7120 if (i386_record_lea_modrm (&ir))
7123 if (!ir.regmap[X86_RECORD_R8_REGNUM])
7124 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7127 case 0x0f02: /* lar */
7128 case 0x0f03: /* lsl */
7129 if (i386_record_modrm (&ir))
7131 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7132 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7136 if (i386_record_modrm (&ir))
7138 if (ir.mod == 3 && ir.reg == 3)
7141 opcode = opcode << 8 | ir.modrm;
7153 /* nop (multi byte) */
7156 case 0x0f20: /* mov reg, crN */
7157 case 0x0f22: /* mov crN, reg */
7158 if (i386_record_modrm (&ir))
7160 if ((ir.modrm & 0xc0) != 0xc0)
7163 opcode = opcode << 8 | ir.modrm;
7174 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7176 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7180 opcode = opcode << 8 | ir.modrm;
7186 case 0x0f21: /* mov reg, drN */
7187 case 0x0f23: /* mov drN, reg */
7188 if (i386_record_modrm (&ir))
7190 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
7191 || ir.reg == 5 || ir.reg >= 8)
7194 opcode = opcode << 8 | ir.modrm;
7198 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7200 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7203 case 0x0f06: /* clts */
7204 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7207 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7209 case 0x0f0d: /* 3DNow! prefetch */
7212 case 0x0f0e: /* 3DNow! femms */
7213 case 0x0f77: /* emms */
7214 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
7216 record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
7219 case 0x0f0f: /* 3DNow! data */
7220 if (i386_record_modrm (&ir))
7222 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7227 case 0x0c: /* 3DNow! pi2fw */
7228 case 0x0d: /* 3DNow! pi2fd */
7229 case 0x1c: /* 3DNow! pf2iw */
7230 case 0x1d: /* 3DNow! pf2id */
7231 case 0x8a: /* 3DNow! pfnacc */
7232 case 0x8e: /* 3DNow! pfpnacc */
7233 case 0x90: /* 3DNow! pfcmpge */
7234 case 0x94: /* 3DNow! pfmin */
7235 case 0x96: /* 3DNow! pfrcp */
7236 case 0x97: /* 3DNow! pfrsqrt */
7237 case 0x9a: /* 3DNow! pfsub */
7238 case 0x9e: /* 3DNow! pfadd */
7239 case 0xa0: /* 3DNow! pfcmpgt */
7240 case 0xa4: /* 3DNow! pfmax */
7241 case 0xa6: /* 3DNow! pfrcpit1 */
7242 case 0xa7: /* 3DNow! pfrsqit1 */
7243 case 0xaa: /* 3DNow! pfsubr */
7244 case 0xae: /* 3DNow! pfacc */
7245 case 0xb0: /* 3DNow! pfcmpeq */
7246 case 0xb4: /* 3DNow! pfmul */
7247 case 0xb6: /* 3DNow! pfrcpit2 */
7248 case 0xb7: /* 3DNow! pmulhrw */
7249 case 0xbb: /* 3DNow! pswapd */
7250 case 0xbf: /* 3DNow! pavgusb */
7251 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7252 goto no_support_3dnow_data;
7253 record_full_arch_list_add_reg (ir.regcache, ir.reg);
7257 no_support_3dnow_data:
7258 opcode = (opcode << 8) | opcode8;
7264 case 0x0faa: /* rsm */
7265 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7266 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7267 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
7268 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7269 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
7270 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
7271 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
7272 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
7273 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
7277 if (i386_record_modrm (&ir))
7281 case 0: /* fxsave */
7285 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7286 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
7288 if (record_full_arch_list_add_mem (tmpu64, 512))
7293 case 1: /* fxrstor */
7297 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7299 for (i = I387_MM0_REGNUM (tdep);
7300 i386_mmx_regnum_p (gdbarch, i); i++)
7301 record_full_arch_list_add_reg (ir.regcache, i);
7303 for (i = I387_XMM0_REGNUM (tdep);
7304 i386_xmm_regnum_p (gdbarch, i); i++)
7305 record_full_arch_list_add_reg (ir.regcache, i);
7307 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7308 record_full_arch_list_add_reg (ir.regcache,
7309 I387_MXCSR_REGNUM(tdep));
7311 for (i = I387_ST0_REGNUM (tdep);
7312 i386_fp_regnum_p (gdbarch, i); i++)
7313 record_full_arch_list_add_reg (ir.regcache, i);
7315 for (i = I387_FCTRL_REGNUM (tdep);
7316 i386_fpc_regnum_p (gdbarch, i); i++)
7317 record_full_arch_list_add_reg (ir.regcache, i);
7321 case 2: /* ldmxcsr */
7322 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7324 record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
7327 case 3: /* stmxcsr */
7329 if (i386_record_lea_modrm (&ir))
7333 case 5: /* lfence */
7334 case 6: /* mfence */
7335 case 7: /* sfence clflush */
7339 opcode = (opcode << 8) | ir.modrm;
7345 case 0x0fc3: /* movnti */
7346 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
7347 if (i386_record_modrm (&ir))
7352 if (i386_record_lea_modrm (&ir))
7356 /* Add prefix to opcode. */
7471 /* Mask out PREFIX_ADDR. */
7472 switch ((prefixes & ~PREFIX_ADDR))
7484 reswitch_prefix_add:
7492 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7495 opcode = (uint32_t) opcode8 | opcode << 8;
7496 goto reswitch_prefix_add;
7499 case 0x0f10: /* movups */
7500 case 0x660f10: /* movupd */
7501 case 0xf30f10: /* movss */
7502 case 0xf20f10: /* movsd */
7503 case 0x0f12: /* movlps */
7504 case 0x660f12: /* movlpd */
7505 case 0xf30f12: /* movsldup */
7506 case 0xf20f12: /* movddup */
7507 case 0x0f14: /* unpcklps */
7508 case 0x660f14: /* unpcklpd */
7509 case 0x0f15: /* unpckhps */
7510 case 0x660f15: /* unpckhpd */
7511 case 0x0f16: /* movhps */
7512 case 0x660f16: /* movhpd */
7513 case 0xf30f16: /* movshdup */
7514 case 0x0f28: /* movaps */
7515 case 0x660f28: /* movapd */
7516 case 0x0f2a: /* cvtpi2ps */
7517 case 0x660f2a: /* cvtpi2pd */
7518 case 0xf30f2a: /* cvtsi2ss */
7519 case 0xf20f2a: /* cvtsi2sd */
7520 case 0x0f2c: /* cvttps2pi */
7521 case 0x660f2c: /* cvttpd2pi */
7522 case 0x0f2d: /* cvtps2pi */
7523 case 0x660f2d: /* cvtpd2pi */
7524 case 0x660f3800: /* pshufb */
7525 case 0x660f3801: /* phaddw */
7526 case 0x660f3802: /* phaddd */
7527 case 0x660f3803: /* phaddsw */
7528 case 0x660f3804: /* pmaddubsw */
7529 case 0x660f3805: /* phsubw */
7530 case 0x660f3806: /* phsubd */
7531 case 0x660f3807: /* phsubsw */
7532 case 0x660f3808: /* psignb */
7533 case 0x660f3809: /* psignw */
7534 case 0x660f380a: /* psignd */
7535 case 0x660f380b: /* pmulhrsw */
7536 case 0x660f3810: /* pblendvb */
7537 case 0x660f3814: /* blendvps */
7538 case 0x660f3815: /* blendvpd */
7539 case 0x660f381c: /* pabsb */
7540 case 0x660f381d: /* pabsw */
7541 case 0x660f381e: /* pabsd */
7542 case 0x660f3820: /* pmovsxbw */
7543 case 0x660f3821: /* pmovsxbd */
7544 case 0x660f3822: /* pmovsxbq */
7545 case 0x660f3823: /* pmovsxwd */
7546 case 0x660f3824: /* pmovsxwq */
7547 case 0x660f3825: /* pmovsxdq */
7548 case 0x660f3828: /* pmuldq */
7549 case 0x660f3829: /* pcmpeqq */
7550 case 0x660f382a: /* movntdqa */
7551 case 0x660f3a08: /* roundps */
7552 case 0x660f3a09: /* roundpd */
7553 case 0x660f3a0a: /* roundss */
7554 case 0x660f3a0b: /* roundsd */
7555 case 0x660f3a0c: /* blendps */
7556 case 0x660f3a0d: /* blendpd */
7557 case 0x660f3a0e: /* pblendw */
7558 case 0x660f3a0f: /* palignr */
7559 case 0x660f3a20: /* pinsrb */
7560 case 0x660f3a21: /* insertps */
7561 case 0x660f3a22: /* pinsrd pinsrq */
7562 case 0x660f3a40: /* dpps */
7563 case 0x660f3a41: /* dppd */
7564 case 0x660f3a42: /* mpsadbw */
7565 case 0x660f3a60: /* pcmpestrm */
7566 case 0x660f3a61: /* pcmpestri */
7567 case 0x660f3a62: /* pcmpistrm */
7568 case 0x660f3a63: /* pcmpistri */
7569 case 0x0f51: /* sqrtps */
7570 case 0x660f51: /* sqrtpd */
7571 case 0xf20f51: /* sqrtsd */
7572 case 0xf30f51: /* sqrtss */
7573 case 0x0f52: /* rsqrtps */
7574 case 0xf30f52: /* rsqrtss */
7575 case 0x0f53: /* rcpps */
7576 case 0xf30f53: /* rcpss */
7577 case 0x0f54: /* andps */
7578 case 0x660f54: /* andpd */
7579 case 0x0f55: /* andnps */
7580 case 0x660f55: /* andnpd */
7581 case 0x0f56: /* orps */
7582 case 0x660f56: /* orpd */
7583 case 0x0f57: /* xorps */
7584 case 0x660f57: /* xorpd */
7585 case 0x0f58: /* addps */
7586 case 0x660f58: /* addpd */
7587 case 0xf20f58: /* addsd */
7588 case 0xf30f58: /* addss */
7589 case 0x0f59: /* mulps */
7590 case 0x660f59: /* mulpd */
7591 case 0xf20f59: /* mulsd */
7592 case 0xf30f59: /* mulss */
7593 case 0x0f5a: /* cvtps2pd */
7594 case 0x660f5a: /* cvtpd2ps */
7595 case 0xf20f5a: /* cvtsd2ss */
7596 case 0xf30f5a: /* cvtss2sd */
7597 case 0x0f5b: /* cvtdq2ps */
7598 case 0x660f5b: /* cvtps2dq */
7599 case 0xf30f5b: /* cvttps2dq */
7600 case 0x0f5c: /* subps */
7601 case 0x660f5c: /* subpd */
7602 case 0xf20f5c: /* subsd */
7603 case 0xf30f5c: /* subss */
7604 case 0x0f5d: /* minps */
7605 case 0x660f5d: /* minpd */
7606 case 0xf20f5d: /* minsd */
7607 case 0xf30f5d: /* minss */
7608 case 0x0f5e: /* divps */
7609 case 0x660f5e: /* divpd */
7610 case 0xf20f5e: /* divsd */
7611 case 0xf30f5e: /* divss */
7612 case 0x0f5f: /* maxps */
7613 case 0x660f5f: /* maxpd */
7614 case 0xf20f5f: /* maxsd */
7615 case 0xf30f5f: /* maxss */
7616 case 0x660f60: /* punpcklbw */
7617 case 0x660f61: /* punpcklwd */
7618 case 0x660f62: /* punpckldq */
7619 case 0x660f63: /* packsswb */
7620 case 0x660f64: /* pcmpgtb */
7621 case 0x660f65: /* pcmpgtw */
7622 case 0x660f66: /* pcmpgtd */
7623 case 0x660f67: /* packuswb */
7624 case 0x660f68: /* punpckhbw */
7625 case 0x660f69: /* punpckhwd */
7626 case 0x660f6a: /* punpckhdq */
7627 case 0x660f6b: /* packssdw */
7628 case 0x660f6c: /* punpcklqdq */
7629 case 0x660f6d: /* punpckhqdq */
7630 case 0x660f6e: /* movd */
7631 case 0x660f6f: /* movdqa */
7632 case 0xf30f6f: /* movdqu */
7633 case 0x660f70: /* pshufd */
7634 case 0xf20f70: /* pshuflw */
7635 case 0xf30f70: /* pshufhw */
7636 case 0x660f74: /* pcmpeqb */
7637 case 0x660f75: /* pcmpeqw */
7638 case 0x660f76: /* pcmpeqd */
7639 case 0x660f7c: /* haddpd */
7640 case 0xf20f7c: /* haddps */
7641 case 0x660f7d: /* hsubpd */
7642 case 0xf20f7d: /* hsubps */
7643 case 0xf30f7e: /* movq */
7644 case 0x0fc2: /* cmpps */
7645 case 0x660fc2: /* cmppd */
7646 case 0xf20fc2: /* cmpsd */
7647 case 0xf30fc2: /* cmpss */
7648 case 0x660fc4: /* pinsrw */
7649 case 0x0fc6: /* shufps */
7650 case 0x660fc6: /* shufpd */
7651 case 0x660fd0: /* addsubpd */
7652 case 0xf20fd0: /* addsubps */
7653 case 0x660fd1: /* psrlw */
7654 case 0x660fd2: /* psrld */
7655 case 0x660fd3: /* psrlq */
7656 case 0x660fd4: /* paddq */
7657 case 0x660fd5: /* pmullw */
7658 case 0xf30fd6: /* movq2dq */
7659 case 0x660fd8: /* psubusb */
7660 case 0x660fd9: /* psubusw */
7661 case 0x660fda: /* pminub */
7662 case 0x660fdb: /* pand */
7663 case 0x660fdc: /* paddusb */
7664 case 0x660fdd: /* paddusw */
7665 case 0x660fde: /* pmaxub */
7666 case 0x660fdf: /* pandn */
7667 case 0x660fe0: /* pavgb */
7668 case 0x660fe1: /* psraw */
7669 case 0x660fe2: /* psrad */
7670 case 0x660fe3: /* pavgw */
7671 case 0x660fe4: /* pmulhuw */
7672 case 0x660fe5: /* pmulhw */
7673 case 0x660fe6: /* cvttpd2dq */
7674 case 0xf20fe6: /* cvtpd2dq */
7675 case 0xf30fe6: /* cvtdq2pd */
7676 case 0x660fe8: /* psubsb */
7677 case 0x660fe9: /* psubsw */
7678 case 0x660fea: /* pminsw */
7679 case 0x660feb: /* por */
7680 case 0x660fec: /* paddsb */
7681 case 0x660fed: /* paddsw */
7682 case 0x660fee: /* pmaxsw */
7683 case 0x660fef: /* pxor */
7684 case 0xf20ff0: /* lddqu */
7685 case 0x660ff1: /* psllw */
7686 case 0x660ff2: /* pslld */
7687 case 0x660ff3: /* psllq */
7688 case 0x660ff4: /* pmuludq */
7689 case 0x660ff5: /* pmaddwd */
7690 case 0x660ff6: /* psadbw */
7691 case 0x660ff8: /* psubb */
7692 case 0x660ff9: /* psubw */
7693 case 0x660ffa: /* psubd */
7694 case 0x660ffb: /* psubq */
7695 case 0x660ffc: /* paddb */
7696 case 0x660ffd: /* paddw */
7697 case 0x660ffe: /* paddd */
7698 if (i386_record_modrm (&ir))
7701 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
7703 record_full_arch_list_add_reg (ir.regcache,
7704 I387_XMM0_REGNUM (tdep) + ir.reg);
7705 if ((opcode & 0xfffffffc) == 0x660f3a60)
7706 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7709 case 0x0f11: /* movups */
7710 case 0x660f11: /* movupd */
7711 case 0xf30f11: /* movss */
7712 case 0xf20f11: /* movsd */
7713 case 0x0f13: /* movlps */
7714 case 0x660f13: /* movlpd */
7715 case 0x0f17: /* movhps */
7716 case 0x660f17: /* movhpd */
7717 case 0x0f29: /* movaps */
7718 case 0x660f29: /* movapd */
7719 case 0x660f3a14: /* pextrb */
7720 case 0x660f3a15: /* pextrw */
7721 case 0x660f3a16: /* pextrd pextrq */
7722 case 0x660f3a17: /* extractps */
7723 case 0x660f7f: /* movdqa */
7724 case 0xf30f7f: /* movdqu */
7725 if (i386_record_modrm (&ir))
7729 if (opcode == 0x0f13 || opcode == 0x660f13
7730 || opcode == 0x0f17 || opcode == 0x660f17)
7733 if (!i386_xmm_regnum_p (gdbarch,
7734 I387_XMM0_REGNUM (tdep) + ir.rm))
7736 record_full_arch_list_add_reg (ir.regcache,
7737 I387_XMM0_REGNUM (tdep) + ir.rm);
7759 if (i386_record_lea_modrm (&ir))
7764 case 0x0f2b: /* movntps */
7765 case 0x660f2b: /* movntpd */
7766 case 0x0fe7: /* movntq */
7767 case 0x660fe7: /* movntdq */
7770 if (opcode == 0x0fe7)
7774 if (i386_record_lea_modrm (&ir))
7778 case 0xf30f2c: /* cvttss2si */
7779 case 0xf20f2c: /* cvttsd2si */
7780 case 0xf30f2d: /* cvtss2si */
7781 case 0xf20f2d: /* cvtsd2si */
7782 case 0xf20f38f0: /* crc32 */
7783 case 0xf20f38f1: /* crc32 */
7784 case 0x0f50: /* movmskps */
7785 case 0x660f50: /* movmskpd */
7786 case 0x0fc5: /* pextrw */
7787 case 0x660fc5: /* pextrw */
7788 case 0x0fd7: /* pmovmskb */
7789 case 0x660fd7: /* pmovmskb */
7790 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7793 case 0x0f3800: /* pshufb */
7794 case 0x0f3801: /* phaddw */
7795 case 0x0f3802: /* phaddd */
7796 case 0x0f3803: /* phaddsw */
7797 case 0x0f3804: /* pmaddubsw */
7798 case 0x0f3805: /* phsubw */
7799 case 0x0f3806: /* phsubd */
7800 case 0x0f3807: /* phsubsw */
7801 case 0x0f3808: /* psignb */
7802 case 0x0f3809: /* psignw */
7803 case 0x0f380a: /* psignd */
7804 case 0x0f380b: /* pmulhrsw */
7805 case 0x0f381c: /* pabsb */
7806 case 0x0f381d: /* pabsw */
7807 case 0x0f381e: /* pabsd */
7808 case 0x0f382b: /* packusdw */
7809 case 0x0f3830: /* pmovzxbw */
7810 case 0x0f3831: /* pmovzxbd */
7811 case 0x0f3832: /* pmovzxbq */
7812 case 0x0f3833: /* pmovzxwd */
7813 case 0x0f3834: /* pmovzxwq */
7814 case 0x0f3835: /* pmovzxdq */
7815 case 0x0f3837: /* pcmpgtq */
7816 case 0x0f3838: /* pminsb */
7817 case 0x0f3839: /* pminsd */
7818 case 0x0f383a: /* pminuw */
7819 case 0x0f383b: /* pminud */
7820 case 0x0f383c: /* pmaxsb */
7821 case 0x0f383d: /* pmaxsd */
7822 case 0x0f383e: /* pmaxuw */
7823 case 0x0f383f: /* pmaxud */
7824 case 0x0f3840: /* pmulld */
7825 case 0x0f3841: /* phminposuw */
7826 case 0x0f3a0f: /* palignr */
7827 case 0x0f60: /* punpcklbw */
7828 case 0x0f61: /* punpcklwd */
7829 case 0x0f62: /* punpckldq */
7830 case 0x0f63: /* packsswb */
7831 case 0x0f64: /* pcmpgtb */
7832 case 0x0f65: /* pcmpgtw */
7833 case 0x0f66: /* pcmpgtd */
7834 case 0x0f67: /* packuswb */
7835 case 0x0f68: /* punpckhbw */
7836 case 0x0f69: /* punpckhwd */
7837 case 0x0f6a: /* punpckhdq */
7838 case 0x0f6b: /* packssdw */
7839 case 0x0f6e: /* movd */
7840 case 0x0f6f: /* movq */
7841 case 0x0f70: /* pshufw */
7842 case 0x0f74: /* pcmpeqb */
7843 case 0x0f75: /* pcmpeqw */
7844 case 0x0f76: /* pcmpeqd */
7845 case 0x0fc4: /* pinsrw */
7846 case 0x0fd1: /* psrlw */
7847 case 0x0fd2: /* psrld */
7848 case 0x0fd3: /* psrlq */
7849 case 0x0fd4: /* paddq */
7850 case 0x0fd5: /* pmullw */
7851 case 0xf20fd6: /* movdq2q */
7852 case 0x0fd8: /* psubusb */
7853 case 0x0fd9: /* psubusw */
7854 case 0x0fda: /* pminub */
7855 case 0x0fdb: /* pand */
7856 case 0x0fdc: /* paddusb */
7857 case 0x0fdd: /* paddusw */
7858 case 0x0fde: /* pmaxub */
7859 case 0x0fdf: /* pandn */
7860 case 0x0fe0: /* pavgb */
7861 case 0x0fe1: /* psraw */
7862 case 0x0fe2: /* psrad */
7863 case 0x0fe3: /* pavgw */
7864 case 0x0fe4: /* pmulhuw */
7865 case 0x0fe5: /* pmulhw */
7866 case 0x0fe8: /* psubsb */
7867 case 0x0fe9: /* psubsw */
7868 case 0x0fea: /* pminsw */
7869 case 0x0feb: /* por */
7870 case 0x0fec: /* paddsb */
7871 case 0x0fed: /* paddsw */
7872 case 0x0fee: /* pmaxsw */
7873 case 0x0fef: /* pxor */
7874 case 0x0ff1: /* psllw */
7875 case 0x0ff2: /* pslld */
7876 case 0x0ff3: /* psllq */
7877 case 0x0ff4: /* pmuludq */
7878 case 0x0ff5: /* pmaddwd */
7879 case 0x0ff6: /* psadbw */
7880 case 0x0ff8: /* psubb */
7881 case 0x0ff9: /* psubw */
7882 case 0x0ffa: /* psubd */
7883 case 0x0ffb: /* psubq */
7884 case 0x0ffc: /* paddb */
7885 case 0x0ffd: /* paddw */
7886 case 0x0ffe: /* paddd */
7887 if (i386_record_modrm (&ir))
7889 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7891 record_full_arch_list_add_reg (ir.regcache,
7892 I387_MM0_REGNUM (tdep) + ir.reg);
7895 case 0x0f71: /* psllw */
7896 case 0x0f72: /* pslld */
7897 case 0x0f73: /* psllq */
7898 if (i386_record_modrm (&ir))
7900 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7902 record_full_arch_list_add_reg (ir.regcache,
7903 I387_MM0_REGNUM (tdep) + ir.rm);
7906 case 0x660f71: /* psllw */
7907 case 0x660f72: /* pslld */
7908 case 0x660f73: /* psllq */
7909 if (i386_record_modrm (&ir))
7912 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
7914 record_full_arch_list_add_reg (ir.regcache,
7915 I387_XMM0_REGNUM (tdep) + ir.rm);
7918 case 0x0f7e: /* movd */
7919 case 0x660f7e: /* movd */
7920 if (i386_record_modrm (&ir))
7923 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7930 if (i386_record_lea_modrm (&ir))
7935 case 0x0f7f: /* movq */
7936 if (i386_record_modrm (&ir))
7940 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7942 record_full_arch_list_add_reg (ir.regcache,
7943 I387_MM0_REGNUM (tdep) + ir.rm);
7948 if (i386_record_lea_modrm (&ir))
7953 case 0xf30fb8: /* popcnt */
7954 if (i386_record_modrm (&ir))
7956 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
7957 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7960 case 0x660fd6: /* movq */
7961 if (i386_record_modrm (&ir))
7966 if (!i386_xmm_regnum_p (gdbarch,
7967 I387_XMM0_REGNUM (tdep) + ir.rm))
7969 record_full_arch_list_add_reg (ir.regcache,
7970 I387_XMM0_REGNUM (tdep) + ir.rm);
7975 if (i386_record_lea_modrm (&ir))
7980 case 0x660f3817: /* ptest */
7981 case 0x0f2e: /* ucomiss */
7982 case 0x660f2e: /* ucomisd */
7983 case 0x0f2f: /* comiss */
7984 case 0x660f2f: /* comisd */
7985 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7988 case 0x0ff7: /* maskmovq */
7989 regcache_raw_read_unsigned (ir.regcache,
7990 ir.regmap[X86_RECORD_REDI_REGNUM],
7992 if (record_full_arch_list_add_mem (addr, 64))
7996 case 0x660ff7: /* maskmovdqu */
7997 regcache_raw_read_unsigned (ir.regcache,
7998 ir.regmap[X86_RECORD_REDI_REGNUM],
8000 if (record_full_arch_list_add_mem (addr, 128))
8015 /* In the future, maybe still need to deal with need_dasm. */
8016 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
8017 if (record_full_arch_list_add_end ())
8023 printf_unfiltered (_("Process record does not support instruction 0x%02x "
8024 "at address %s.\n"),
8025 (unsigned int) (opcode),
8026 paddress (gdbarch, ir.orig_addr));
8030 static const int i386_record_regmap[] =
8032 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
8033 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
8034 0, 0, 0, 0, 0, 0, 0, 0,
8035 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
8036 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
8039 /* Check that the given address appears suitable for a fast
8040 tracepoint, which on x86-64 means that we need an instruction of at
8041 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8042 jump and not have to worry about program jumps to an address in the
8043 middle of the tracepoint jump. On x86, it may be possible to use
8044 4-byte jumps with a 2-byte offset to a trampoline located in the
8045 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8046 of instruction to replace, and 0 if not, plus an explanatory
8050 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch,
8051 CORE_ADDR addr, int *isize, char **msg)
8054 static struct ui_file *gdb_null = NULL;
8056 /* Ask the target for the minimum instruction length supported. */
8057 jumplen = target_get_min_fast_tracepoint_insn_len ();
8061 /* If the target does not support the get_min_fast_tracepoint_insn_len
8062 operation, assume that fast tracepoints will always be implemented
8063 using 4-byte relative jumps on both x86 and x86-64. */
8066 else if (jumplen == 0)
8068 /* If the target does support get_min_fast_tracepoint_insn_len but
8069 returns zero, then the IPA has not loaded yet. In this case,
8070 we optimistically assume that truncated 2-byte relative jumps
8071 will be available on x86, and compensate later if this assumption
8072 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8073 jumps will always be used. */
8074 jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4;
8077 /* Dummy file descriptor for the disassembler. */
8079 gdb_null = ui_file_new ();
8081 /* Check for fit. */
8082 len = gdb_print_insn (gdbarch, addr, gdb_null, NULL);
8088 /* Return a bit of target-specific detail to add to the caller's
8089 generic failure message. */
8091 *msg = xstrprintf (_("; instruction is only %d bytes long, "
8092 "need at least %d bytes for the jump"),
8105 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
8106 struct tdesc_arch_data *tdesc_data)
8108 const struct target_desc *tdesc = tdep->tdesc;
8109 const struct tdesc_feature *feature_core;
8111 const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx,
8113 int i, num_regs, valid_p;
8115 if (! tdesc_has_registers (tdesc))
8118 /* Get core registers. */
8119 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
8120 if (feature_core == NULL)
8123 /* Get SSE registers. */
8124 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
8126 /* Try AVX registers. */
8127 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
8129 /* Try MPX registers. */
8130 feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx");
8132 /* Try AVX512 registers. */
8133 feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512");
8137 /* The XCR0 bits. */
8140 /* AVX512 register description requires AVX register description. */
8144 tdep->xcr0 = X86_XSTATE_MPX_AVX512_MASK;
8146 /* It may have been set by OSABI initialization function. */
8147 if (tdep->k0_regnum < 0)
8149 tdep->k_register_names = i386_k_names;
8150 tdep->k0_regnum = I386_K0_REGNUM;
8153 for (i = 0; i < I387_NUM_K_REGS; i++)
8154 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8155 tdep->k0_regnum + i,
8158 if (tdep->num_zmm_regs == 0)
8160 tdep->zmmh_register_names = i386_zmmh_names;
8161 tdep->num_zmm_regs = 8;
8162 tdep->zmm0h_regnum = I386_ZMM0H_REGNUM;
8165 for (i = 0; i < tdep->num_zmm_regs; i++)
8166 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8167 tdep->zmm0h_regnum + i,
8168 tdep->zmmh_register_names[i]);
8170 for (i = 0; i < tdep->num_xmm_avx512_regs; i++)
8171 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8172 tdep->xmm16_regnum + i,
8173 tdep->xmm_avx512_register_names[i]);
8175 for (i = 0; i < tdep->num_ymm_avx512_regs; i++)
8176 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8177 tdep->ymm16h_regnum + i,
8178 tdep->ymm16h_register_names[i]);
8182 /* AVX register description requires SSE register description. */
8186 if (!feature_avx512)
8187 tdep->xcr0 = X86_XSTATE_AVX_MASK;
8189 /* It may have been set by OSABI initialization function. */
8190 if (tdep->num_ymm_regs == 0)
8192 tdep->ymmh_register_names = i386_ymmh_names;
8193 tdep->num_ymm_regs = 8;
8194 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
8197 for (i = 0; i < tdep->num_ymm_regs; i++)
8198 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
8199 tdep->ymm0h_regnum + i,
8200 tdep->ymmh_register_names[i]);
8202 else if (feature_sse)
8203 tdep->xcr0 = X86_XSTATE_SSE_MASK;
8206 tdep->xcr0 = X86_XSTATE_X87_MASK;
8207 tdep->num_xmm_regs = 0;
8210 num_regs = tdep->num_core_regs;
8211 for (i = 0; i < num_regs; i++)
8212 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
8213 tdep->register_names[i]);
8217 /* Need to include %mxcsr, so add one. */
8218 num_regs += tdep->num_xmm_regs + 1;
8219 for (; i < num_regs; i++)
8220 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
8221 tdep->register_names[i]);
8226 tdep->xcr0 |= X86_XSTATE_MPX_MASK;
8228 if (tdep->bnd0r_regnum < 0)
8230 tdep->mpx_register_names = i386_mpx_names;
8231 tdep->bnd0r_regnum = I386_BND0R_REGNUM;
8232 tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM;
8235 for (i = 0; i < I387_NUM_MPX_REGS; i++)
8236 valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data,
8237 I387_BND0R_REGNUM (tdep) + i,
8238 tdep->mpx_register_names[i]);
8245 static struct gdbarch *
8246 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8248 struct gdbarch_tdep *tdep;
8249 struct gdbarch *gdbarch;
8250 struct tdesc_arch_data *tdesc_data;
8251 const struct target_desc *tdesc;
8259 /* If there is already a candidate, use it. */
8260 arches = gdbarch_list_lookup_by_info (arches, &info);
8262 return arches->gdbarch;
8264 /* Allocate space for the new architecture. */
8265 tdep = XCNEW (struct gdbarch_tdep);
8266 gdbarch = gdbarch_alloc (&info, tdep);
8268 /* General-purpose registers. */
8269 tdep->gregset_reg_offset = NULL;
8270 tdep->gregset_num_regs = I386_NUM_GREGS;
8271 tdep->sizeof_gregset = 0;
8273 /* Floating-point registers. */
8274 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
8275 tdep->fpregset = &i386_fpregset;
8277 /* The default settings include the FPU registers, the MMX registers
8278 and the SSE registers. This can be overridden for a specific ABI
8279 by adjusting the members `st0_regnum', `mm0_regnum' and
8280 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8281 will show up in the output of "info all-registers". */
8283 tdep->st0_regnum = I386_ST0_REGNUM;
8285 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8286 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
8288 tdep->jb_pc_offset = -1;
8289 tdep->struct_return = pcc_struct_return;
8290 tdep->sigtramp_start = 0;
8291 tdep->sigtramp_end = 0;
8292 tdep->sigtramp_p = i386_sigtramp_p;
8293 tdep->sigcontext_addr = NULL;
8294 tdep->sc_reg_offset = NULL;
8295 tdep->sc_pc_offset = -1;
8296 tdep->sc_sp_offset = -1;
8298 tdep->xsave_xcr0_offset = -1;
8300 tdep->record_regmap = i386_record_regmap;
8302 set_gdbarch_long_long_align_bit (gdbarch, 32);
8304 /* The format used for `long double' on almost all i386 targets is
8305 the i387 extended floating-point format. In fact, of all targets
8306 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8307 on having a `long double' that's not `long' at all. */
8308 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
8310 /* Although the i387 extended floating-point has only 80 significant
8311 bits, a `long double' actually takes up 96, probably to enforce
8313 set_gdbarch_long_double_bit (gdbarch, 96);
8315 /* Register numbers of various important registers. */
8316 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
8317 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
8318 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
8319 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
8321 /* NOTE: kettenis/20040418: GCC does have two possible register
8322 numbering schemes on the i386: dbx and SVR4. These schemes
8323 differ in how they number %ebp, %esp, %eflags, and the
8324 floating-point registers, and are implemented by the arrays
8325 dbx_register_map[] and svr4_dbx_register_map in
8326 gcc/config/i386.c. GCC also defines a third numbering scheme in
8327 gcc/config/i386.c, which it designates as the "default" register
8328 map used in 64bit mode. This last register numbering scheme is
8329 implemented in dbx64_register_map, and is used for AMD64; see
8332 Currently, each GCC i386 target always uses the same register
8333 numbering scheme across all its supported debugging formats
8334 i.e. SDB (COFF), stabs and DWARF 2. This is because
8335 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8336 DBX_REGISTER_NUMBER macro which is defined by each target's
8337 respective config header in a manner independent of the requested
8338 output debugging format.
8340 This does not match the arrangement below, which presumes that
8341 the SDB and stabs numbering schemes differ from the DWARF and
8342 DWARF 2 ones. The reason for this arrangement is that it is
8343 likely to get the numbering scheme for the target's
8344 default/native debug format right. For targets where GCC is the
8345 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8346 targets where the native toolchain uses a different numbering
8347 scheme for a particular debug format (stabs-in-ELF on Solaris)
8348 the defaults below will have to be overridden, like
8349 i386_elf_init_abi() does. */
8351 /* Use the dbx register numbering scheme for stabs and COFF. */
8352 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8353 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8355 /* Use the SVR4 register numbering scheme for DWARF 2. */
8356 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
8358 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8359 be in use on any of the supported i386 targets. */
8361 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
8363 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
8365 /* Call dummy code. */
8366 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
8367 set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code);
8368 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
8369 set_gdbarch_frame_align (gdbarch, i386_frame_align);
8371 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
8372 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
8373 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
8375 set_gdbarch_return_value (gdbarch, i386_return_value);
8377 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
8379 /* Stack grows downward. */
8380 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8382 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc);
8383 set_gdbarch_decr_pc_after_break (gdbarch, 1);
8384 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
8386 set_gdbarch_frame_args_skip (gdbarch, 8);
8388 set_gdbarch_print_insn (gdbarch, i386_print_insn);
8390 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
8392 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
8394 /* Add the i386 register groups. */
8395 i386_add_reggroups (gdbarch);
8396 tdep->register_reggroup_p = i386_register_reggroup_p;
8398 /* Helper for function argument information. */
8399 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
8401 /* Hook the function epilogue frame unwinder. This unwinder is
8402 appended to the list first, so that it supercedes the DWARF
8403 unwinder in function epilogues (where the DWARF unwinder
8404 currently fails). */
8405 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
8407 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8408 to the list before the prologue-based unwinders, so that DWARF
8409 CFI info will be used if it is available. */
8410 dwarf2_append_unwinders (gdbarch);
8412 frame_base_set_default (gdbarch, &i386_frame_base);
8414 /* Pseudo registers may be changed by amd64_init_abi. */
8415 set_gdbarch_pseudo_register_read_value (gdbarch,
8416 i386_pseudo_register_read_value);
8417 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
8419 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
8420 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
8422 /* Override the normal target description method to make the AVX
8423 upper halves anonymous. */
8424 set_gdbarch_register_name (gdbarch, i386_register_name);
8426 /* Even though the default ABI only includes general-purpose registers,
8427 floating-point registers and the SSE registers, we have to leave a
8428 gap for the upper AVX, MPX and AVX512 registers. */
8429 set_gdbarch_num_regs (gdbarch, I386_AVX512_NUM_REGS);
8431 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
8433 /* Get the x86 target description from INFO. */
8434 tdesc = info.target_desc;
8435 if (! tdesc_has_registers (tdesc))
8437 tdep->tdesc = tdesc;
8439 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
8440 tdep->register_names = i386_register_names;
8442 /* No upper YMM registers. */
8443 tdep->ymmh_register_names = NULL;
8444 tdep->ymm0h_regnum = -1;
8446 /* No upper ZMM registers. */
8447 tdep->zmmh_register_names = NULL;
8448 tdep->zmm0h_regnum = -1;
8450 /* No high XMM registers. */
8451 tdep->xmm_avx512_register_names = NULL;
8452 tdep->xmm16_regnum = -1;
8454 /* No upper YMM16-31 registers. */
8455 tdep->ymm16h_register_names = NULL;
8456 tdep->ymm16h_regnum = -1;
8458 tdep->num_byte_regs = 8;
8459 tdep->num_word_regs = 8;
8460 tdep->num_dword_regs = 0;
8461 tdep->num_mmx_regs = 8;
8462 tdep->num_ymm_regs = 0;
8464 /* No MPX registers. */
8465 tdep->bnd0r_regnum = -1;
8466 tdep->bndcfgu_regnum = -1;
8468 /* No AVX512 registers. */
8469 tdep->k0_regnum = -1;
8470 tdep->num_zmm_regs = 0;
8471 tdep->num_ymm_avx512_regs = 0;
8472 tdep->num_xmm_avx512_regs = 0;
8474 tdesc_data = tdesc_data_alloc ();
8476 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
8478 set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address);
8480 set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call);
8481 set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret);
8482 set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump);
8484 /* Hook in ABI-specific overrides, if they have been registered. */
8485 info.tdep_info = (void *) tdesc_data;
8486 gdbarch_init_osabi (info, gdbarch);
8488 if (!i386_validate_tdesc_p (tdep, tdesc_data))
8490 tdesc_data_cleanup (tdesc_data);
8492 gdbarch_free (gdbarch);
8496 num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0);
8498 /* Wire in pseudo registers. Number of pseudo registers may be
8500 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
8501 + tdep->num_word_regs
8502 + tdep->num_dword_regs
8503 + tdep->num_mmx_regs
8504 + tdep->num_ymm_regs
8506 + tdep->num_ymm_avx512_regs
8507 + tdep->num_zmm_regs));
8509 /* Target description may be changed. */
8510 tdesc = tdep->tdesc;
8512 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
8514 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8515 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
8517 /* Make %al the first pseudo-register. */
8518 tdep->al_regnum = gdbarch_num_regs (gdbarch);
8519 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
8521 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
8522 if (tdep->num_dword_regs)
8524 /* Support dword pseudo-register if it hasn't been disabled. */
8525 tdep->eax_regnum = ymm0_regnum;
8526 ymm0_regnum += tdep->num_dword_regs;
8529 tdep->eax_regnum = -1;
8531 mm0_regnum = ymm0_regnum;
8532 if (tdep->num_ymm_regs)
8534 /* Support YMM pseudo-register if it is available. */
8535 tdep->ymm0_regnum = ymm0_regnum;
8536 mm0_regnum += tdep->num_ymm_regs;
8539 tdep->ymm0_regnum = -1;
8541 if (tdep->num_ymm_avx512_regs)
8543 /* Support YMM16-31 pseudo registers if available. */
8544 tdep->ymm16_regnum = mm0_regnum;
8545 mm0_regnum += tdep->num_ymm_avx512_regs;
8548 tdep->ymm16_regnum = -1;
8550 if (tdep->num_zmm_regs)
8552 /* Support ZMM pseudo-register if it is available. */
8553 tdep->zmm0_regnum = mm0_regnum;
8554 mm0_regnum += tdep->num_zmm_regs;
8557 tdep->zmm0_regnum = -1;
8559 bnd0_regnum = mm0_regnum;
8560 if (tdep->num_mmx_regs != 0)
8562 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8563 tdep->mm0_regnum = mm0_regnum;
8564 bnd0_regnum += tdep->num_mmx_regs;
8567 tdep->mm0_regnum = -1;
8569 if (tdep->bnd0r_regnum > 0)
8570 tdep->bnd0_regnum = bnd0_regnum;
8572 tdep-> bnd0_regnum = -1;
8574 /* Hook in the legacy prologue-based unwinders last (fallback). */
8575 frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind);
8576 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
8577 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
8579 /* If we have a register mapping, enable the generic core file
8580 support, unless it has already been enabled. */
8581 if (tdep->gregset_reg_offset
8582 && !gdbarch_iterate_over_regset_sections_p (gdbarch))
8583 set_gdbarch_iterate_over_regset_sections
8584 (gdbarch, i386_iterate_over_regset_sections);
8586 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
8587 i386_fast_tracepoint_valid_at);
8592 static enum gdb_osabi
8593 i386_coff_osabi_sniffer (bfd *abfd)
8595 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
8596 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
8597 return GDB_OSABI_GO32;
8599 return GDB_OSABI_UNKNOWN;
8603 /* Return the target description for a specified XSAVE feature mask. */
8605 const struct target_desc *
8606 i386_target_description (uint64_t xcr0)
8608 switch (xcr0 & X86_XSTATE_ALL_MASK)
8610 case X86_XSTATE_MPX_AVX512_MASK:
8611 case X86_XSTATE_AVX512_MASK:
8612 return tdesc_i386_avx512;
8613 case X86_XSTATE_MPX_MASK:
8614 return tdesc_i386_mpx;
8615 case X86_XSTATE_AVX_MASK:
8616 return tdesc_i386_avx;
8622 #define MPX_BASE_MASK (~(ULONGEST) 0xfff)
8624 /* Find the bound directory base address. */
8626 static unsigned long
8627 i386_mpx_bd_base (void)
8629 struct regcache *rcache;
8630 struct gdbarch_tdep *tdep;
8632 enum register_status regstatus;
8633 struct gdb_exception except;
8635 rcache = get_current_regcache ();
8636 tdep = gdbarch_tdep (get_regcache_arch (rcache));
8638 regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret);
8640 if (regstatus != REG_VALID)
8641 error (_("BNDCFGU register invalid, read status %d."), regstatus);
8643 return ret & MPX_BASE_MASK;
8646 /* Check if the current target is MPX enabled. */
8649 i386_mpx_enabled (void)
8651 const struct gdbarch_tdep *tdep = gdbarch_tdep (get_current_arch ());
8652 const struct target_desc *tdesc = tdep->tdesc;
8654 return (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL);
8657 #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */
8658 #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */
8659 #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */
8660 #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */
8662 /* Find the bound table entry given the pointer location and the base
8663 address of the table. */
8666 i386_mpx_get_bt_entry (CORE_ADDR ptr, CORE_ADDR bd_base)
8670 CORE_ADDR mpx_bd_mask, bd_ptr_r_shift, bd_ptr_l_shift;
8671 CORE_ADDR bt_mask, bt_select_r_shift, bt_select_l_shift;
8672 CORE_ADDR bd_entry_addr;
8675 struct gdbarch *gdbarch = get_current_arch ();
8676 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8679 if (gdbarch_ptr_bit (gdbarch) == 64)
8681 mpx_bd_mask = (CORE_ADDR) MPX_BD_MASK;
8682 bd_ptr_r_shift = 20;
8684 bt_select_r_shift = 3;
8685 bt_select_l_shift = 5;
8686 bt_mask = (CORE_ADDR) MPX_BT_MASK;
8688 if ( sizeof (CORE_ADDR) == 4)
8689 error (_("operation not supported"));
8693 mpx_bd_mask = MPX_BD_MASK_32;
8694 bd_ptr_r_shift = 12;
8696 bt_select_r_shift = 2;
8697 bt_select_l_shift = 4;
8698 bt_mask = MPX_BT_MASK_32;
8701 offset1 = ((ptr & mpx_bd_mask) >> bd_ptr_r_shift) << bd_ptr_l_shift;
8702 bd_entry_addr = bd_base + offset1;
8703 bd_entry = read_memory_typed_address (bd_entry_addr, data_ptr_type);
8705 if ((bd_entry & 0x1) == 0)
8706 error (_("Invalid bounds directory entry at %s."),
8707 paddress (get_current_arch (), bd_entry_addr));
8709 /* Clearing status bit. */
8711 bt_addr = bd_entry & ~bt_select_r_shift;
8712 offset2 = ((ptr & bt_mask) >> bt_select_r_shift) << bt_select_l_shift;
8714 return bt_addr + offset2;
8717 /* Print routine for the mpx bounds. */
8720 i386_mpx_print_bounds (const CORE_ADDR bt_entry[4])
8722 struct ui_out *uiout = current_uiout;
8724 struct gdbarch *gdbarch = get_current_arch ();
8725 CORE_ADDR onecompl = ~((CORE_ADDR) 0);
8726 int bounds_in_map = ((~bt_entry[1] == 0 && bt_entry[0] == onecompl) ? 1 : 0);
8728 if (bounds_in_map == 1)
8730 ui_out_text (uiout, "Null bounds on map:");
8731 ui_out_text (uiout, " pointer value = ");
8732 ui_out_field_core_addr (uiout, "pointer-value", gdbarch, bt_entry[2]);
8733 ui_out_text (uiout, ".");
8734 ui_out_text (uiout, "\n");
8738 ui_out_text (uiout, "{lbound = ");
8739 ui_out_field_core_addr (uiout, "lower-bound", gdbarch, bt_entry[0]);
8740 ui_out_text (uiout, ", ubound = ");
8742 /* The upper bound is stored in 1's complement. */
8743 ui_out_field_core_addr (uiout, "upper-bound", gdbarch, ~bt_entry[1]);
8744 ui_out_text (uiout, "}: pointer value = ");
8745 ui_out_field_core_addr (uiout, "pointer-value", gdbarch, bt_entry[2]);
8747 if (gdbarch_ptr_bit (gdbarch) == 64)
8748 size = ( (~(int64_t) bt_entry[1]) - (int64_t) bt_entry[0]);
8750 size = ( ~((int32_t) bt_entry[1]) - (int32_t) bt_entry[0]);
8752 /* In case the bounds are 0x0 and 0xffff... the difference will be -1.
8753 -1 represents in this sense full memory access, and there is no need
8756 size = (size > -1 ? size + 1 : size);
8757 ui_out_text (uiout, ", size = ");
8758 ui_out_field_fmt (uiout, "size", "%s", plongest (size));
8760 ui_out_text (uiout, ", metadata = ");
8761 ui_out_field_core_addr (uiout, "metadata", gdbarch, bt_entry[3]);
8762 ui_out_text (uiout, "\n");
8766 /* Implement the command "show mpx bound". */
8769 i386_mpx_info_bounds (char *args, int from_tty)
8771 CORE_ADDR bd_base = 0;
8773 CORE_ADDR bt_entry_addr = 0;
8774 CORE_ADDR bt_entry[4];
8776 struct gdbarch *gdbarch = get_current_arch ();
8777 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8779 if (!i386_mpx_enabled ())
8780 error (_("Intel(R) Memory Protection Extensions not\
8781 supported on this target."));
8784 error (_("Address of pointer variable expected."));
8786 addr = parse_and_eval_address (args);
8788 bd_base = i386_mpx_bd_base ();
8789 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8791 memset (bt_entry, 0, sizeof (bt_entry));
8793 for (i = 0; i < 4; i++)
8794 bt_entry[i] = read_memory_typed_address (bt_entry_addr
8795 + i * data_ptr_type->length,
8798 i386_mpx_print_bounds (bt_entry);
8801 /* Implement the command "set mpx bound". */
8804 i386_mpx_set_bounds (char *args, int from_tty)
8806 CORE_ADDR bd_base = 0;
8807 CORE_ADDR addr, lower, upper;
8808 CORE_ADDR bt_entry_addr = 0;
8809 CORE_ADDR bt_entry[2];
8810 const char *input = args;
8812 struct gdbarch *gdbarch = get_current_arch ();
8813 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8814 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8816 if (!i386_mpx_enabled ())
8817 error (_("Intel(R) Memory Protection Extensions not supported\
8821 error (_("Pointer value expected."));
8823 addr = value_as_address (parse_to_comma_and_eval (&input));
8825 if (input[0] == ',')
8827 if (input[0] == '\0')
8828 error (_("wrong number of arguments: missing lower and upper bound."));
8829 lower = value_as_address (parse_to_comma_and_eval (&input));
8831 if (input[0] == ',')
8833 if (input[0] == '\0')
8834 error (_("Wrong number of arguments; Missing upper bound."));
8835 upper = value_as_address (parse_to_comma_and_eval (&input));
8837 bd_base = i386_mpx_bd_base ();
8838 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8839 for (i = 0; i < 2; i++)
8840 bt_entry[i] = read_memory_typed_address (bt_entry_addr
8841 + i * data_ptr_type->length,
8843 bt_entry[0] = (uint64_t) lower;
8844 bt_entry[1] = ~(uint64_t) upper;
8846 for (i = 0; i < 2; i++)
8847 write_memory_unsigned_integer (bt_entry_addr + i * data_ptr_type->length,
8848 data_ptr_type->length, byte_order,
8852 static struct cmd_list_element *mpx_set_cmdlist, *mpx_show_cmdlist;
8854 /* Helper function for the CLI commands. */
8857 set_mpx_cmd (char *args, int from_tty)
8859 help_list (mpx_set_cmdlist, "set mpx", all_commands, gdb_stdout);
8862 /* Helper function for the CLI commands. */
8865 show_mpx_cmd (char *args, int from_tty)
8867 cmd_show_list (mpx_show_cmdlist, from_tty, "");
8870 /* Provide a prototype to silence -Wmissing-prototypes. */
8871 void _initialize_i386_tdep (void);
8874 _initialize_i386_tdep (void)
8876 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
8878 /* Add the variable that controls the disassembly flavor. */
8879 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
8880 &disassembly_flavor, _("\
8881 Set the disassembly flavor."), _("\
8882 Show the disassembly flavor."), _("\
8883 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
8885 NULL, /* FIXME: i18n: */
8886 &setlist, &showlist);
8888 /* Add the variable that controls the convention for returning
8890 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
8891 &struct_convention, _("\
8892 Set the convention for returning small structs."), _("\
8893 Show the convention for returning small structs."), _("\
8894 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
8897 NULL, /* FIXME: i18n: */
8898 &setlist, &showlist);
8900 /* Add "mpx" prefix for the set commands. */
8902 add_prefix_cmd ("mpx", class_support, set_mpx_cmd, _("\
8903 Set Intel(R) Memory Protection Extensions specific variables."),
8904 &mpx_set_cmdlist, "set tdesc ",
8905 0 /* allow-unknown */, &setlist);
8907 /* Add "mpx" prefix for the show commands. */
8909 add_prefix_cmd ("mpx", class_support, show_mpx_cmd, _("\
8910 Show Intel(R) Memory Protection Extensions specific variables."),
8911 &mpx_show_cmdlist, "show mpx ",
8912 0 /* allow-unknown */, &showlist);
8914 /* Add "bound" command for the show mpx commands list. */
8916 add_cmd ("bound", no_class, i386_mpx_info_bounds,
8917 "Show the memory bounds for a given array/pointer storage\
8918 in the bound table.",
8921 /* Add "bound" command for the set mpx commands list. */
8923 add_cmd ("bound", no_class, i386_mpx_set_bounds,
8924 "Set the memory bounds for a given array/pointer storage\
8925 in the bound table.",
8928 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
8929 i386_coff_osabi_sniffer);
8931 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
8932 i386_svr4_init_abi);
8933 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
8934 i386_go32_init_abi);
8936 /* Initialize the i386-specific register groups. */
8937 i386_init_reggroups ();
8939 /* Initialize the standard target descriptions. */
8940 initialize_tdesc_i386 ();
8941 initialize_tdesc_i386_mmx ();
8942 initialize_tdesc_i386_avx ();
8943 initialize_tdesc_i386_mpx ();
8944 initialize_tdesc_i386_avx512 ();
8946 /* Tell remote stub that we support XML target description. */
8947 register_remote_support_xml ("i386");