1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
48 #include "gdb_assert.h"
49 #include "gdb_string.h"
51 #include "i386-tdep.h"
52 #include "i387-tdep.h"
57 #include "features/i386/i386.c"
61 static const char *i386_register_names[] =
63 "eax", "ecx", "edx", "ebx",
64 "esp", "ebp", "esi", "edi",
65 "eip", "eflags", "cs", "ss",
66 "ds", "es", "fs", "gs",
67 "st0", "st1", "st2", "st3",
68 "st4", "st5", "st6", "st7",
69 "fctrl", "fstat", "ftag", "fiseg",
70 "fioff", "foseg", "fooff", "fop",
71 "xmm0", "xmm1", "xmm2", "xmm3",
72 "xmm4", "xmm5", "xmm6", "xmm7",
76 /* Register names for MMX pseudo-registers. */
78 static const char *i386_mmx_names[] =
80 "mm0", "mm1", "mm2", "mm3",
81 "mm4", "mm5", "mm6", "mm7"
84 static const int i386_num_mmx_regs = ARRAY_SIZE (i386_mmx_names);
87 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
89 int mm0_regnum = gdbarch_tdep (gdbarch)->mm0_regnum;
94 return (regnum >= mm0_regnum && regnum < mm0_regnum + i386_num_mmx_regs);
100 i386_sse_regnum_p (struct gdbarch *gdbarch, int regnum)
102 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
104 if (I387_NUM_XMM_REGS (tdep) == 0)
107 return (I387_XMM0_REGNUM (tdep) <= regnum
108 && regnum < I387_MXCSR_REGNUM (tdep));
112 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
114 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
116 if (I387_NUM_XMM_REGS (tdep) == 0)
119 return (regnum == I387_MXCSR_REGNUM (tdep));
125 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
127 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
129 if (I387_ST0_REGNUM (tdep) < 0)
132 return (I387_ST0_REGNUM (tdep) <= regnum
133 && regnum < I387_FCTRL_REGNUM (tdep));
137 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
139 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
141 if (I387_ST0_REGNUM (tdep) < 0)
144 return (I387_FCTRL_REGNUM (tdep) <= regnum
145 && regnum < I387_XMM0_REGNUM (tdep));
148 /* Return the name of register REGNUM. */
151 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
153 gdb_assert (i386_mmx_regnum_p (gdbarch, regnum));
154 return i386_mmx_names[regnum - I387_MM0_REGNUM (gdbarch_tdep (gdbarch))];
157 /* Convert a dbx register number REG to the appropriate register
158 number used by GDB. */
161 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
163 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
165 /* This implements what GCC calls the "default" register map
166 (dbx_register_map[]). */
168 if (reg >= 0 && reg <= 7)
170 /* General-purpose registers. The debug info calls %ebp
171 register 4, and %esp register 5. */
178 else if (reg >= 12 && reg <= 19)
180 /* Floating-point registers. */
181 return reg - 12 + I387_ST0_REGNUM (tdep);
183 else if (reg >= 21 && reg <= 28)
186 return reg - 21 + I387_XMM0_REGNUM (tdep);
188 else if (reg >= 29 && reg <= 36)
191 return reg - 29 + I387_MM0_REGNUM (tdep);
194 /* This will hopefully provoke a warning. */
195 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
198 /* Convert SVR4 register number REG to the appropriate register number
202 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
204 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
206 /* This implements the GCC register map that tries to be compatible
207 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
209 /* The SVR4 register numbering includes %eip and %eflags, and
210 numbers the floating point registers differently. */
211 if (reg >= 0 && reg <= 9)
213 /* General-purpose registers. */
216 else if (reg >= 11 && reg <= 18)
218 /* Floating-point registers. */
219 return reg - 11 + I387_ST0_REGNUM (tdep);
221 else if (reg >= 21 && reg <= 36)
223 /* The SSE and MMX registers have the same numbers as with dbx. */
224 return i386_dbx_reg_to_regnum (gdbarch, reg);
229 case 37: return I387_FCTRL_REGNUM (tdep);
230 case 38: return I387_FSTAT_REGNUM (tdep);
231 case 39: return I387_MXCSR_REGNUM (tdep);
232 case 40: return I386_ES_REGNUM;
233 case 41: return I386_CS_REGNUM;
234 case 42: return I386_SS_REGNUM;
235 case 43: return I386_DS_REGNUM;
236 case 44: return I386_FS_REGNUM;
237 case 45: return I386_GS_REGNUM;
240 /* This will hopefully provoke a warning. */
241 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
246 /* This is the variable that is set with "set disassembly-flavor", and
247 its legitimate values. */
248 static const char att_flavor[] = "att";
249 static const char intel_flavor[] = "intel";
250 static const char *valid_flavors[] =
256 static const char *disassembly_flavor = att_flavor;
259 /* Use the program counter to determine the contents and size of a
260 breakpoint instruction. Return a pointer to a string of bytes that
261 encode a breakpoint instruction, store the length of the string in
262 *LEN and optionally adjust *PC to point to the correct memory
263 location for inserting the breakpoint.
265 On the i386 we have a single breakpoint that fits in a single byte
266 and can be inserted anywhere.
268 This function is 64-bit safe. */
270 static const gdb_byte *
271 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
273 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */
275 *len = sizeof (break_insn);
279 /* Displaced instruction handling. */
281 /* Skip the legacy instruction prefixes in INSN.
282 Not all prefixes are valid for any particular insn
283 but we needn't care, the insn will fault if it's invalid.
284 The result is a pointer to the first opcode byte,
285 or NULL if we run off the end of the buffer. */
288 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
290 gdb_byte *end = insn + max_len;
296 case DATA_PREFIX_OPCODE:
297 case ADDR_PREFIX_OPCODE:
298 case CS_PREFIX_OPCODE:
299 case DS_PREFIX_OPCODE:
300 case ES_PREFIX_OPCODE:
301 case FS_PREFIX_OPCODE:
302 case GS_PREFIX_OPCODE:
303 case SS_PREFIX_OPCODE:
304 case LOCK_PREFIX_OPCODE:
305 case REPE_PREFIX_OPCODE:
306 case REPNE_PREFIX_OPCODE:
318 i386_absolute_jmp_p (const gdb_byte *insn)
320 /* jmp far (absolute address in operand) */
326 /* jump near, absolute indirect (/4) */
327 if ((insn[1] & 0x38) == 0x20)
330 /* jump far, absolute indirect (/5) */
331 if ((insn[1] & 0x38) == 0x28)
339 i386_absolute_call_p (const gdb_byte *insn)
341 /* call far, absolute */
347 /* Call near, absolute indirect (/2) */
348 if ((insn[1] & 0x38) == 0x10)
351 /* Call far, absolute indirect (/3) */
352 if ((insn[1] & 0x38) == 0x18)
360 i386_ret_p (const gdb_byte *insn)
364 case 0xc2: /* ret near, pop N bytes */
365 case 0xc3: /* ret near */
366 case 0xca: /* ret far, pop N bytes */
367 case 0xcb: /* ret far */
368 case 0xcf: /* iret */
377 i386_call_p (const gdb_byte *insn)
379 if (i386_absolute_call_p (insn))
382 /* call near, relative */
389 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
390 length in bytes. Otherwise, return zero. */
393 i386_syscall_p (const gdb_byte *insn, ULONGEST *lengthp)
404 /* Fix up the state of registers and memory after having single-stepped
405 a displaced instruction. */
408 i386_displaced_step_fixup (struct gdbarch *gdbarch,
409 struct displaced_step_closure *closure,
410 CORE_ADDR from, CORE_ADDR to,
411 struct regcache *regs)
413 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
415 /* The offset we applied to the instruction's address.
416 This could well be negative (when viewed as a signed 32-bit
417 value), but ULONGEST won't reflect that, so take care when
419 ULONGEST insn_offset = to - from;
421 /* Since we use simple_displaced_step_copy_insn, our closure is a
422 copy of the instruction. */
423 gdb_byte *insn = (gdb_byte *) closure;
424 /* The start of the insn, needed in case we see some prefixes. */
425 gdb_byte *insn_start = insn;
428 fprintf_unfiltered (gdb_stdlog,
429 "displaced: fixup (%s, %s), "
430 "insn = 0x%02x 0x%02x ...\n",
431 paddress (gdbarch, from), paddress (gdbarch, to),
434 /* The list of issues to contend with here is taken from
435 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
436 Yay for Free Software! */
438 /* Relocate the %eip, if necessary. */
440 /* The instruction recognizers we use assume any leading prefixes
441 have been skipped. */
443 /* This is the size of the buffer in closure. */
444 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
445 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
446 /* If there are too many prefixes, just ignore the insn.
447 It will fault when run. */
452 /* Except in the case of absolute or indirect jump or call
453 instructions, or a return instruction, the new eip is relative to
454 the displaced instruction; make it relative. Well, signal
455 handler returns don't need relocation either, but we use the
456 value of %eip to recognize those; see below. */
457 if (! i386_absolute_jmp_p (insn)
458 && ! i386_absolute_call_p (insn)
459 && ! i386_ret_p (insn))
464 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
466 /* A signal trampoline system call changes the %eip, resuming
467 execution of the main program after the signal handler has
468 returned. That makes them like 'return' instructions; we
469 shouldn't relocate %eip.
471 But most system calls don't, and we do need to relocate %eip.
473 Our heuristic for distinguishing these cases: if stepping
474 over the system call instruction left control directly after
475 the instruction, the we relocate --- control almost certainly
476 doesn't belong in the displaced copy. Otherwise, we assume
477 the instruction has put control where it belongs, and leave
478 it unrelocated. Goodness help us if there are PC-relative
480 if (i386_syscall_p (insn, &insn_len)
481 && orig_eip != to + (insn - insn_start) + insn_len)
484 fprintf_unfiltered (gdb_stdlog,
485 "displaced: syscall changed %%eip; "
490 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
492 /* If we just stepped over a breakpoint insn, we don't backup
493 the pc on purpose; this is to match behaviour without
496 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
499 fprintf_unfiltered (gdb_stdlog,
501 "relocated %%eip from %s to %s\n",
502 paddress (gdbarch, orig_eip),
503 paddress (gdbarch, eip));
507 /* If the instruction was PUSHFL, then the TF bit will be set in the
508 pushed value, and should be cleared. We'll leave this for later,
509 since GDB already messes up the TF flag when stepping over a
512 /* If the instruction was a call, the return address now atop the
513 stack is the address following the copied instruction. We need
514 to make it the address following the original instruction. */
515 if (i386_call_p (insn))
519 const ULONGEST retaddr_len = 4;
521 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
522 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
523 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
524 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
527 fprintf_unfiltered (gdb_stdlog,
528 "displaced: relocated return addr at %s to %s\n",
529 paddress (gdbarch, esp),
530 paddress (gdbarch, retaddr));
534 #ifdef I386_REGNO_TO_SYMMETRY
535 #error "The Sequent Symmetry is no longer supported."
538 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
539 and %esp "belong" to the calling function. Therefore these
540 registers should be saved if they're going to be modified. */
542 /* The maximum number of saved registers. This should include all
543 registers mentioned above, and %eip. */
544 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
546 struct i386_frame_cache
553 /* Saved registers. */
554 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
559 /* Stack space reserved for local variables. */
563 /* Allocate and initialize a frame cache. */
565 static struct i386_frame_cache *
566 i386_alloc_frame_cache (void)
568 struct i386_frame_cache *cache;
571 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
575 cache->sp_offset = -4;
578 /* Saved registers. We initialize these to -1 since zero is a valid
579 offset (that's where %ebp is supposed to be stored). */
580 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
581 cache->saved_regs[i] = -1;
583 cache->saved_sp_reg = -1;
584 cache->pc_in_eax = 0;
586 /* Frameless until proven otherwise. */
592 /* If the instruction at PC is a jump, return the address of its
593 target. Otherwise, return PC. */
596 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
598 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
603 target_read_memory (pc, &op, 1);
607 op = read_memory_unsigned_integer (pc + 1, 1, byte_order);
613 /* Relative jump: if data16 == 0, disp32, else disp16. */
616 delta = read_memory_integer (pc + 2, 2, byte_order);
618 /* Include the size of the jmp instruction (including the
624 delta = read_memory_integer (pc + 1, 4, byte_order);
626 /* Include the size of the jmp instruction. */
631 /* Relative jump, disp8 (ignore data16). */
632 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
641 /* Check whether PC points at a prologue for a function returning a
642 structure or union. If so, it updates CACHE and returns the
643 address of the first instruction after the code sequence that
644 removes the "hidden" argument from the stack or CURRENT_PC,
645 whichever is smaller. Otherwise, return PC. */
648 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
649 struct i386_frame_cache *cache)
651 /* Functions that return a structure or union start with:
654 xchgl %eax, (%esp) 0x87 0x04 0x24
655 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
657 (the System V compiler puts out the second `xchg' instruction,
658 and the assembler doesn't try to optimize it, so the 'sib' form
659 gets generated). This sequence is used to get the address of the
660 return buffer for a function that returns a structure. */
661 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
662 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
666 if (current_pc <= pc)
669 target_read_memory (pc, &op, 1);
671 if (op != 0x58) /* popl %eax */
674 target_read_memory (pc + 1, buf, 4);
675 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
678 if (current_pc == pc)
680 cache->sp_offset += 4;
684 if (current_pc == pc + 1)
686 cache->pc_in_eax = 1;
690 if (buf[1] == proto1[1])
697 i386_skip_probe (CORE_ADDR pc)
699 /* A function may start with
713 target_read_memory (pc, &op, 1);
715 if (op == 0x68 || op == 0x6a)
719 /* Skip past the `pushl' instruction; it has either a one-byte or a
720 four-byte operand, depending on the opcode. */
726 /* Read the following 8 bytes, which should be `call _probe' (6
727 bytes) followed by `addl $4,%esp' (2 bytes). */
728 read_memory (pc + delta, buf, sizeof (buf));
729 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
730 pc += delta + sizeof (buf);
736 /* GCC 4.1 and later, can put code in the prologue to realign the
737 stack pointer. Check whether PC points to such code, and update
738 CACHE accordingly. Return the first instruction after the code
739 sequence or CURRENT_PC, whichever is smaller. If we don't
740 recognize the code, return PC. */
743 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
744 struct i386_frame_cache *cache)
746 /* There are 2 code sequences to re-align stack before the frame
749 1. Use a caller-saved saved register:
755 2. Use a callee-saved saved register:
762 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
764 0x83 0xe4 0xf0 andl $-16, %esp
765 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
770 int offset, offset_and;
771 static int regnums[8] = {
772 I386_EAX_REGNUM, /* %eax */
773 I386_ECX_REGNUM, /* %ecx */
774 I386_EDX_REGNUM, /* %edx */
775 I386_EBX_REGNUM, /* %ebx */
776 I386_ESP_REGNUM, /* %esp */
777 I386_EBP_REGNUM, /* %ebp */
778 I386_ESI_REGNUM, /* %esi */
779 I386_EDI_REGNUM /* %edi */
782 if (target_read_memory (pc, buf, sizeof buf))
785 /* Check caller-saved saved register. The first instruction has
786 to be "leal 4(%esp), %reg". */
787 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
789 /* MOD must be binary 10 and R/M must be binary 100. */
790 if ((buf[1] & 0xc7) != 0x44)
793 /* REG has register number. */
794 reg = (buf[1] >> 3) & 7;
799 /* Check callee-saved saved register. The first instruction
800 has to be "pushl %reg". */
801 if ((buf[0] & 0xf8) != 0x50)
807 /* The next instruction has to be "leal 8(%esp), %reg". */
808 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
811 /* MOD must be binary 10 and R/M must be binary 100. */
812 if ((buf[2] & 0xc7) != 0x44)
815 /* REG has register number. Registers in pushl and leal have to
817 if (reg != ((buf[2] >> 3) & 7))
823 /* Rigister can't be %esp nor %ebp. */
824 if (reg == 4 || reg == 5)
827 /* The next instruction has to be "andl $-XXX, %esp". */
828 if (buf[offset + 1] != 0xe4
829 || (buf[offset] != 0x81 && buf[offset] != 0x83))
833 offset += buf[offset] == 0x81 ? 6 : 3;
835 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
836 0xfc. REG must be binary 110 and MOD must be binary 01. */
837 if (buf[offset] != 0xff
838 || buf[offset + 2] != 0xfc
839 || (buf[offset + 1] & 0xf8) != 0x70)
842 /* R/M has register. Registers in leal and pushl have to be the
844 if (reg != (buf[offset + 1] & 7))
847 if (current_pc > pc + offset_and)
848 cache->saved_sp_reg = regnums[reg];
850 return min (pc + offset + 3, current_pc);
853 /* Maximum instruction length we need to handle. */
854 #define I386_MAX_MATCHED_INSN_LEN 6
856 /* Instruction description. */
860 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
861 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
864 /* Search for the instruction at PC in the list SKIP_INSNS. Return
865 the first instruction description that matches. Otherwise, return
868 static struct i386_insn *
869 i386_match_insn (CORE_ADDR pc, struct i386_insn *skip_insns)
871 struct i386_insn *insn;
874 target_read_memory (pc, &op, 1);
876 for (insn = skip_insns; insn->len > 0; insn++)
878 if ((op & insn->mask[0]) == insn->insn[0])
880 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
881 int insn_matched = 1;
884 gdb_assert (insn->len > 1);
885 gdb_assert (insn->len <= I386_MAX_MATCHED_INSN_LEN);
887 target_read_memory (pc + 1, buf, insn->len - 1);
888 for (i = 1; i < insn->len; i++)
890 if ((buf[i - 1] & insn->mask[i]) != insn->insn[i])
902 /* Some special instructions that might be migrated by GCC into the
903 part of the prologue that sets up the new stack frame. Because the
904 stack frame hasn't been setup yet, no registers have been saved
905 yet, and only the scratch registers %eax, %ecx and %edx can be
908 struct i386_insn i386_frame_setup_skip_insns[] =
910 /* Check for `movb imm8, r' and `movl imm32, r'.
912 ??? Should we handle 16-bit operand-sizes here? */
914 /* `movb imm8, %al' and `movb imm8, %ah' */
915 /* `movb imm8, %cl' and `movb imm8, %ch' */
916 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
917 /* `movb imm8, %dl' and `movb imm8, %dh' */
918 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
919 /* `movl imm32, %eax' and `movl imm32, %ecx' */
920 { 5, { 0xb8 }, { 0xfe } },
921 /* `movl imm32, %edx' */
922 { 5, { 0xba }, { 0xff } },
924 /* Check for `mov imm32, r32'. Note that there is an alternative
925 encoding for `mov m32, %eax'.
927 ??? Should we handle SIB adressing here?
928 ??? Should we handle 16-bit operand-sizes here? */
930 /* `movl m32, %eax' */
931 { 5, { 0xa1 }, { 0xff } },
932 /* `movl m32, %eax' and `mov; m32, %ecx' */
933 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
934 /* `movl m32, %edx' */
935 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
937 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
938 Because of the symmetry, there are actually two ways to encode
939 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
940 opcode bytes 0x31 and 0x33 for `xorl'. */
942 /* `subl %eax, %eax' */
943 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
944 /* `subl %ecx, %ecx' */
945 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
946 /* `subl %edx, %edx' */
947 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
948 /* `xorl %eax, %eax' */
949 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
950 /* `xorl %ecx, %ecx' */
951 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
952 /* `xorl %edx, %edx' */
953 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
958 /* Check whether PC points to a no-op instruction. */
960 i386_skip_noop (CORE_ADDR pc)
965 target_read_memory (pc, &op, 1);
970 /* Ignore `nop' instruction. */
974 target_read_memory (pc, &op, 1);
977 /* Ignore no-op instruction `mov %edi, %edi'.
978 Microsoft system dlls often start with
979 a `mov %edi,%edi' instruction.
980 The 5 bytes before the function start are
981 filled with `nop' instructions.
982 This pattern can be used for hot-patching:
983 The `mov %edi, %edi' instruction can be replaced by a
984 near jump to the location of the 5 `nop' instructions
985 which can be replaced by a 32-bit jump to anywhere
986 in the 32-bit address space. */
990 target_read_memory (pc + 1, &op, 1);
994 target_read_memory (pc, &op, 1);
1002 /* Check whether PC points at a code that sets up a new stack frame.
1003 If so, it updates CACHE and returns the address of the first
1004 instruction after the sequence that sets up the frame or LIMIT,
1005 whichever is smaller. If we don't recognize the code, return PC. */
1008 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1009 CORE_ADDR pc, CORE_ADDR limit,
1010 struct i386_frame_cache *cache)
1012 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1013 struct i386_insn *insn;
1020 target_read_memory (pc, &op, 1);
1022 if (op == 0x55) /* pushl %ebp */
1024 /* Take into account that we've executed the `pushl %ebp' that
1025 starts this instruction sequence. */
1026 cache->saved_regs[I386_EBP_REGNUM] = 0;
1027 cache->sp_offset += 4;
1030 /* If that's all, return now. */
1034 /* Check for some special instructions that might be migrated by
1035 GCC into the prologue and skip them. At this point in the
1036 prologue, code should only touch the scratch registers %eax,
1037 %ecx and %edx, so while the number of posibilities is sheer,
1040 Make sure we only skip these instructions if we later see the
1041 `movl %esp, %ebp' that actually sets up the frame. */
1042 while (pc + skip < limit)
1044 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1051 /* If that's all, return now. */
1052 if (limit <= pc + skip)
1055 target_read_memory (pc + skip, &op, 1);
1057 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1061 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1066 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1074 /* OK, we actually have a frame. We just don't know how large
1075 it is yet. Set its size to zero. We'll adjust it if
1076 necessary. We also now commit to skipping the special
1077 instructions mentioned before. */
1081 /* If that's all, return now. */
1085 /* Check for stack adjustment
1089 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1090 reg, so we don't have to worry about a data16 prefix. */
1091 target_read_memory (pc, &op, 1);
1094 /* `subl' with 8-bit immediate. */
1095 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1096 /* Some instruction starting with 0x83 other than `subl'. */
1099 /* `subl' with signed 8-bit immediate (though it wouldn't
1100 make sense to be negative). */
1101 cache->locals = read_memory_integer (pc + 2, 1, byte_order);
1104 else if (op == 0x81)
1106 /* Maybe it is `subl' with a 32-bit immediate. */
1107 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1108 /* Some instruction starting with 0x81 other than `subl'. */
1111 /* It is `subl' with a 32-bit immediate. */
1112 cache->locals = read_memory_integer (pc + 2, 4, byte_order);
1117 /* Some instruction other than `subl'. */
1121 else if (op == 0xc8) /* enter */
1123 cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order);
1130 /* Check whether PC points at code that saves registers on the stack.
1131 If so, it updates CACHE and returns the address of the first
1132 instruction after the register saves or CURRENT_PC, whichever is
1133 smaller. Otherwise, return PC. */
1136 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1137 struct i386_frame_cache *cache)
1139 CORE_ADDR offset = 0;
1143 if (cache->locals > 0)
1144 offset -= cache->locals;
1145 for (i = 0; i < 8 && pc < current_pc; i++)
1147 target_read_memory (pc, &op, 1);
1148 if (op < 0x50 || op > 0x57)
1152 cache->saved_regs[op - 0x50] = offset;
1153 cache->sp_offset += 4;
1160 /* Do a full analysis of the prologue at PC and update CACHE
1161 accordingly. Bail out early if CURRENT_PC is reached. Return the
1162 address where the analysis stopped.
1164 We handle these cases:
1166 The startup sequence can be at the start of the function, or the
1167 function can start with a branch to startup code at the end.
1169 %ebp can be set up with either the 'enter' instruction, or "pushl
1170 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1171 once used in the System V compiler).
1173 Local space is allocated just below the saved %ebp by either the
1174 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1175 16-bit unsigned argument for space to allocate, and the 'addl'
1176 instruction could have either a signed byte, or 32-bit immediate.
1178 Next, the registers used by this function are pushed. With the
1179 System V compiler they will always be in the order: %edi, %esi,
1180 %ebx (and sometimes a harmless bug causes it to also save but not
1181 restore %eax); however, the code below is willing to see the pushes
1182 in any order, and will handle up to 8 of them.
1184 If the setup sequence is at the end of the function, then the next
1185 instruction will be a branch back to the start. */
1188 i386_analyze_prologue (struct gdbarch *gdbarch,
1189 CORE_ADDR pc, CORE_ADDR current_pc,
1190 struct i386_frame_cache *cache)
1192 pc = i386_skip_noop (pc);
1193 pc = i386_follow_jump (gdbarch, pc);
1194 pc = i386_analyze_struct_return (pc, current_pc, cache);
1195 pc = i386_skip_probe (pc);
1196 pc = i386_analyze_stack_align (pc, current_pc, cache);
1197 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1198 return i386_analyze_register_saves (pc, current_pc, cache);
1201 /* Return PC of first real instruction. */
1204 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1206 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1208 static gdb_byte pic_pat[6] =
1210 0xe8, 0, 0, 0, 0, /* call 0x0 */
1211 0x5b, /* popl %ebx */
1213 struct i386_frame_cache cache;
1219 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1220 if (cache.locals < 0)
1223 /* Found valid frame setup. */
1225 /* The native cc on SVR4 in -K PIC mode inserts the following code
1226 to get the address of the global offset table (GOT) into register
1231 movl %ebx,x(%ebp) (optional)
1234 This code is with the rest of the prologue (at the end of the
1235 function), so we have to skip it to get to the first real
1236 instruction at the start of the function. */
1238 for (i = 0; i < 6; i++)
1240 target_read_memory (pc + i, &op, 1);
1241 if (pic_pat[i] != op)
1248 target_read_memory (pc + delta, &op, 1);
1250 if (op == 0x89) /* movl %ebx, x(%ebp) */
1252 op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order);
1254 if (op == 0x5d) /* One byte offset from %ebp. */
1256 else if (op == 0x9d) /* Four byte offset from %ebp. */
1258 else /* Unexpected instruction. */
1261 target_read_memory (pc + delta, &op, 1);
1265 if (delta > 0 && op == 0x81
1266 && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order)
1273 /* If the function starts with a branch (to startup code at the end)
1274 the last instruction should bring us back to the first
1275 instruction of the real code. */
1276 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1277 pc = i386_follow_jump (gdbarch, pc);
1282 /* Check that the code pointed to by PC corresponds to a call to
1283 __main, skip it if so. Return PC otherwise. */
1286 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1288 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1291 target_read_memory (pc, &op, 1);
1296 if (target_read_memory (pc + 1, buf, sizeof buf) == 0)
1298 /* Make sure address is computed correctly as a 32bit
1299 integer even if CORE_ADDR is 64 bit wide. */
1300 struct minimal_symbol *s;
1301 CORE_ADDR call_dest;
1303 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1304 call_dest = call_dest & 0xffffffffU;
1305 s = lookup_minimal_symbol_by_pc (call_dest);
1307 && SYMBOL_LINKAGE_NAME (s) != NULL
1308 && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0)
1316 /* This function is 64-bit safe. */
1319 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1323 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1324 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1328 /* Normal frames. */
1330 static struct i386_frame_cache *
1331 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
1333 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1334 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1335 struct i386_frame_cache *cache;
1342 cache = i386_alloc_frame_cache ();
1343 *this_cache = cache;
1345 /* In principle, for normal frames, %ebp holds the frame pointer,
1346 which holds the base address for the current stack frame.
1347 However, for functions that don't need it, the frame pointer is
1348 optional. For these "frameless" functions the frame pointer is
1349 actually the frame pointer of the calling frame. Signal
1350 trampolines are just a special case of a "frameless" function.
1351 They (usually) share their frame pointer with the frame that was
1352 in progress when the signal occurred. */
1354 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1355 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1356 if (cache->base == 0)
1359 /* For normal frames, %eip is stored at 4(%ebp). */
1360 cache->saved_regs[I386_EIP_REGNUM] = 4;
1362 cache->pc = get_frame_func (this_frame);
1364 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
1367 if (cache->saved_sp_reg != -1)
1369 /* Saved stack pointer has been saved. */
1370 get_frame_register (this_frame, cache->saved_sp_reg, buf);
1371 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
1374 if (cache->locals < 0)
1376 /* We didn't find a valid frame, which means that CACHE->base
1377 currently holds the frame pointer for our calling frame. If
1378 we're at the start of a function, or somewhere half-way its
1379 prologue, the function's frame probably hasn't been fully
1380 setup yet. Try to reconstruct the base address for the stack
1381 frame by looking at the stack pointer. For truly "frameless"
1382 functions this might work too. */
1384 if (cache->saved_sp_reg != -1)
1386 /* We're halfway aligning the stack. */
1387 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
1388 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
1390 /* This will be added back below. */
1391 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
1393 else if (cache->pc != 0
1394 || target_read_memory (get_frame_pc (this_frame), buf, 1))
1396 /* We're in a known function, but did not find a frame
1397 setup. Assume that the function does not use %ebp.
1398 Alternatively, we may have jumped to an invalid
1399 address; in that case there is definitely no new
1401 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1402 cache->base = extract_unsigned_integer (buf, 4, byte_order)
1406 /* We're in an unknown function. We could not find the start
1407 of the function to analyze the prologue; our best option is
1408 to assume a typical frame layout with the caller's %ebp
1410 cache->saved_regs[I386_EBP_REGNUM] = 0;
1413 /* Now that we have the base address for the stack frame we can
1414 calculate the value of %esp in the calling frame. */
1415 if (cache->saved_sp == 0)
1416 cache->saved_sp = cache->base + 8;
1418 /* Adjust all the saved registers such that they contain addresses
1419 instead of offsets. */
1420 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1421 if (cache->saved_regs[i] != -1)
1422 cache->saved_regs[i] += cache->base;
1428 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
1429 struct frame_id *this_id)
1431 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1433 /* This marks the outermost frame. */
1434 if (cache->base == 0)
1437 /* See the end of i386_push_dummy_call. */
1438 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
1441 static struct value *
1442 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
1445 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1447 gdb_assert (regnum >= 0);
1449 /* The System V ABI says that:
1451 "The flags register contains the system flags, such as the
1452 direction flag and the carry flag. The direction flag must be
1453 set to the forward (that is, zero) direction before entry and
1454 upon exit from a function. Other user flags have no specified
1455 role in the standard calling sequence and are not preserved."
1457 To guarantee the "upon exit" part of that statement we fake a
1458 saved flags register that has its direction flag cleared.
1460 Note that GCC doesn't seem to rely on the fact that the direction
1461 flag is cleared after a function return; it always explicitly
1462 clears the flag before operations where it matters.
1464 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1465 right thing to do. The way we fake the flags register here makes
1466 it impossible to change it. */
1468 if (regnum == I386_EFLAGS_REGNUM)
1472 val = get_frame_register_unsigned (this_frame, regnum);
1474 return frame_unwind_got_constant (this_frame, regnum, val);
1477 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
1478 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
1480 if (regnum == I386_ESP_REGNUM && cache->saved_sp)
1481 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
1483 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
1484 return frame_unwind_got_memory (this_frame, regnum,
1485 cache->saved_regs[regnum]);
1487 return frame_unwind_got_register (this_frame, regnum, regnum);
1490 static const struct frame_unwind i386_frame_unwind =
1494 i386_frame_prev_register,
1496 default_frame_sniffer
1499 /* Normal frames, but in a function epilogue. */
1501 /* The epilogue is defined here as the 'ret' instruction, which will
1502 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1503 the function's stack frame. */
1506 i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1510 if (target_read_memory (pc, &insn, 1))
1511 return 0; /* Can't read memory at pc. */
1513 if (insn != 0xc3) /* 'ret' instruction. */
1520 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
1521 struct frame_info *this_frame,
1522 void **this_prologue_cache)
1524 if (frame_relative_level (this_frame) == 0)
1525 return i386_in_function_epilogue_p (get_frame_arch (this_frame),
1526 get_frame_pc (this_frame));
1531 static struct i386_frame_cache *
1532 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
1534 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1535 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1536 struct i386_frame_cache *cache;
1542 cache = i386_alloc_frame_cache ();
1543 *this_cache = cache;
1545 /* Cache base will be %esp plus cache->sp_offset (-4). */
1546 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1547 cache->base = extract_unsigned_integer (buf, 4,
1548 byte_order) + cache->sp_offset;
1550 /* Cache pc will be the frame func. */
1551 cache->pc = get_frame_pc (this_frame);
1553 /* The saved %esp will be at cache->base plus 8. */
1554 cache->saved_sp = cache->base + 8;
1556 /* The saved %eip will be at cache->base plus 4. */
1557 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
1563 i386_epilogue_frame_this_id (struct frame_info *this_frame,
1565 struct frame_id *this_id)
1567 struct i386_frame_cache *cache = i386_epilogue_frame_cache (this_frame,
1570 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
1573 static const struct frame_unwind i386_epilogue_frame_unwind =
1576 i386_epilogue_frame_this_id,
1577 i386_frame_prev_register,
1579 i386_epilogue_frame_sniffer
1583 /* Signal trampolines. */
1585 static struct i386_frame_cache *
1586 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
1588 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1589 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1590 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1591 struct i386_frame_cache *cache;
1598 cache = i386_alloc_frame_cache ();
1600 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1601 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
1603 addr = tdep->sigcontext_addr (this_frame);
1604 if (tdep->sc_reg_offset)
1608 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
1610 for (i = 0; i < tdep->sc_num_regs; i++)
1611 if (tdep->sc_reg_offset[i] != -1)
1612 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
1616 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
1617 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
1620 *this_cache = cache;
1625 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
1626 struct frame_id *this_id)
1628 struct i386_frame_cache *cache =
1629 i386_sigtramp_frame_cache (this_frame, this_cache);
1631 /* See the end of i386_push_dummy_call. */
1632 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
1635 static struct value *
1636 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
1637 void **this_cache, int regnum)
1639 /* Make sure we've initialized the cache. */
1640 i386_sigtramp_frame_cache (this_frame, this_cache);
1642 return i386_frame_prev_register (this_frame, this_cache, regnum);
1646 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
1647 struct frame_info *this_frame,
1648 void **this_prologue_cache)
1650 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
1652 /* We shouldn't even bother if we don't have a sigcontext_addr
1654 if (tdep->sigcontext_addr == NULL)
1657 if (tdep->sigtramp_p != NULL)
1659 if (tdep->sigtramp_p (this_frame))
1663 if (tdep->sigtramp_start != 0)
1665 CORE_ADDR pc = get_frame_pc (this_frame);
1667 gdb_assert (tdep->sigtramp_end != 0);
1668 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
1675 static const struct frame_unwind i386_sigtramp_frame_unwind =
1678 i386_sigtramp_frame_this_id,
1679 i386_sigtramp_frame_prev_register,
1681 i386_sigtramp_frame_sniffer
1686 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
1688 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1693 static const struct frame_base i386_frame_base =
1696 i386_frame_base_address,
1697 i386_frame_base_address,
1698 i386_frame_base_address
1701 static struct frame_id
1702 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1706 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
1708 /* See the end of i386_push_dummy_call. */
1709 return frame_id_build (fp + 8, get_frame_pc (this_frame));
1713 /* Figure out where the longjmp will land. Slurp the args out of the
1714 stack. We expect the first arg to be a pointer to the jmp_buf
1715 structure from which we extract the address that we will land at.
1716 This address is copied into PC. This routine returns non-zero on
1720 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1723 CORE_ADDR sp, jb_addr;
1724 struct gdbarch *gdbarch = get_frame_arch (frame);
1725 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1726 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
1728 /* If JB_PC_OFFSET is -1, we have no way to find out where the
1729 longjmp will land. */
1730 if (jb_pc_offset == -1)
1733 get_frame_register (frame, I386_ESP_REGNUM, buf);
1734 sp = extract_unsigned_integer (buf, 4, byte_order);
1735 if (target_read_memory (sp + 4, buf, 4))
1738 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
1739 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
1742 *pc = extract_unsigned_integer (buf, 4, byte_order);
1747 /* Check whether TYPE must be 16-byte-aligned when passed as a
1748 function argument. 16-byte vectors, _Decimal128 and structures or
1749 unions containing such types must be 16-byte-aligned; other
1750 arguments are 4-byte-aligned. */
1753 i386_16_byte_align_p (struct type *type)
1755 type = check_typedef (type);
1756 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
1757 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
1758 && TYPE_LENGTH (type) == 16)
1760 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
1761 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
1762 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1763 || TYPE_CODE (type) == TYPE_CODE_UNION)
1766 for (i = 0; i < TYPE_NFIELDS (type); i++)
1768 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
1776 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1777 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
1778 struct value **args, CORE_ADDR sp, int struct_return,
1779 CORE_ADDR struct_addr)
1781 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1787 /* Determine the total space required for arguments and struct
1788 return address in a first pass (allowing for 16-byte-aligned
1789 arguments), then push arguments in a second pass. */
1791 for (write_pass = 0; write_pass < 2; write_pass++)
1793 int args_space_used = 0;
1794 int have_16_byte_aligned_arg = 0;
1800 /* Push value address. */
1801 store_unsigned_integer (buf, 4, byte_order, struct_addr);
1802 write_memory (sp, buf, 4);
1803 args_space_used += 4;
1809 for (i = 0; i < nargs; i++)
1811 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
1815 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
1816 args_space_used = align_up (args_space_used, 16);
1818 write_memory (sp + args_space_used,
1819 value_contents_all (args[i]), len);
1820 /* The System V ABI says that:
1822 "An argument's size is increased, if necessary, to make it a
1823 multiple of [32-bit] words. This may require tail padding,
1824 depending on the size of the argument."
1826 This makes sure the stack stays word-aligned. */
1827 args_space_used += align_up (len, 4);
1831 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
1833 args_space = align_up (args_space, 16);
1834 have_16_byte_aligned_arg = 1;
1836 args_space += align_up (len, 4);
1842 if (have_16_byte_aligned_arg)
1843 args_space = align_up (args_space, 16);
1848 /* Store return address. */
1850 store_unsigned_integer (buf, 4, byte_order, bp_addr);
1851 write_memory (sp, buf, 4);
1853 /* Finally, update the stack pointer... */
1854 store_unsigned_integer (buf, 4, byte_order, sp);
1855 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
1857 /* ...and fake a frame pointer. */
1858 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
1860 /* MarkK wrote: This "+ 8" is all over the place:
1861 (i386_frame_this_id, i386_sigtramp_frame_this_id,
1862 i386_dummy_id). It's there, since all frame unwinders for
1863 a given target have to agree (within a certain margin) on the
1864 definition of the stack address of a frame. Otherwise frame id
1865 comparison might not work correctly. Since DWARF2/GCC uses the
1866 stack address *before* the function call as a frame's CFA. On
1867 the i386, when %ebp is used as a frame pointer, the offset
1868 between the contents %ebp and the CFA as defined by GCC. */
1872 /* These registers are used for returning integers (and on some
1873 targets also for returning `struct' and `union' values when their
1874 size and alignment match an integer type). */
1875 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
1876 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
1878 /* Read, for architecture GDBARCH, a function return value of TYPE
1879 from REGCACHE, and copy that into VALBUF. */
1882 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
1883 struct regcache *regcache, gdb_byte *valbuf)
1885 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1886 int len = TYPE_LENGTH (type);
1887 gdb_byte buf[I386_MAX_REGISTER_SIZE];
1889 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1891 if (tdep->st0_regnum < 0)
1893 warning (_("Cannot find floating-point return value."));
1894 memset (valbuf, 0, len);
1898 /* Floating-point return values can be found in %st(0). Convert
1899 its contents to the desired type. This is probably not
1900 exactly how it would happen on the target itself, but it is
1901 the best we can do. */
1902 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
1903 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
1907 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
1908 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
1910 if (len <= low_size)
1912 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
1913 memcpy (valbuf, buf, len);
1915 else if (len <= (low_size + high_size))
1917 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
1918 memcpy (valbuf, buf, low_size);
1919 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
1920 memcpy (valbuf + low_size, buf, len - low_size);
1923 internal_error (__FILE__, __LINE__,
1924 _("Cannot extract return value of %d bytes long."), len);
1928 /* Write, for architecture GDBARCH, a function return value of TYPE
1929 from VALBUF into REGCACHE. */
1932 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
1933 struct regcache *regcache, const gdb_byte *valbuf)
1935 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1936 int len = TYPE_LENGTH (type);
1938 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1941 gdb_byte buf[I386_MAX_REGISTER_SIZE];
1943 if (tdep->st0_regnum < 0)
1945 warning (_("Cannot set floating-point return value."));
1949 /* Returning floating-point values is a bit tricky. Apart from
1950 storing the return value in %st(0), we have to simulate the
1951 state of the FPU at function return point. */
1953 /* Convert the value found in VALBUF to the extended
1954 floating-point format used by the FPU. This is probably
1955 not exactly how it would happen on the target itself, but
1956 it is the best we can do. */
1957 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
1958 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
1960 /* Set the top of the floating-point register stack to 7. The
1961 actual value doesn't really matter, but 7 is what a normal
1962 function return would end up with if the program started out
1963 with a freshly initialized FPU. */
1964 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
1966 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
1968 /* Mark %st(1) through %st(7) as empty. Since we set the top of
1969 the floating-point register stack to 7, the appropriate value
1970 for the tag word is 0x3fff. */
1971 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
1975 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
1976 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
1978 if (len <= low_size)
1979 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
1980 else if (len <= (low_size + high_size))
1982 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
1983 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
1984 len - low_size, valbuf + low_size);
1987 internal_error (__FILE__, __LINE__,
1988 _("Cannot store return value of %d bytes long."), len);
1993 /* This is the variable that is set with "set struct-convention", and
1994 its legitimate values. */
1995 static const char default_struct_convention[] = "default";
1996 static const char pcc_struct_convention[] = "pcc";
1997 static const char reg_struct_convention[] = "reg";
1998 static const char *valid_conventions[] =
2000 default_struct_convention,
2001 pcc_struct_convention,
2002 reg_struct_convention,
2005 static const char *struct_convention = default_struct_convention;
2007 /* Return non-zero if TYPE, which is assumed to be a structure,
2008 a union type, or an array type, should be returned in registers
2009 for architecture GDBARCH. */
2012 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2014 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2015 enum type_code code = TYPE_CODE (type);
2016 int len = TYPE_LENGTH (type);
2018 gdb_assert (code == TYPE_CODE_STRUCT
2019 || code == TYPE_CODE_UNION
2020 || code == TYPE_CODE_ARRAY);
2022 if (struct_convention == pcc_struct_convention
2023 || (struct_convention == default_struct_convention
2024 && tdep->struct_return == pcc_struct_return))
2027 /* Structures consisting of a single `float', `double' or 'long
2028 double' member are returned in %st(0). */
2029 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2031 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2032 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2033 return (len == 4 || len == 8 || len == 12);
2036 return (len == 1 || len == 2 || len == 4 || len == 8);
2039 /* Determine, for architecture GDBARCH, how a return value of TYPE
2040 should be returned. If it is supposed to be returned in registers,
2041 and READBUF is non-zero, read the appropriate value from REGCACHE,
2042 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2043 from WRITEBUF into REGCACHE. */
2045 static enum return_value_convention
2046 i386_return_value (struct gdbarch *gdbarch, struct type *func_type,
2047 struct type *type, struct regcache *regcache,
2048 gdb_byte *readbuf, const gdb_byte *writebuf)
2050 enum type_code code = TYPE_CODE (type);
2052 if (((code == TYPE_CODE_STRUCT
2053 || code == TYPE_CODE_UNION
2054 || code == TYPE_CODE_ARRAY)
2055 && !i386_reg_struct_return_p (gdbarch, type))
2056 /* 128-bit decimal float uses the struct return convention. */
2057 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2059 /* The System V ABI says that:
2061 "A function that returns a structure or union also sets %eax
2062 to the value of the original address of the caller's area
2063 before it returns. Thus when the caller receives control
2064 again, the address of the returned object resides in register
2065 %eax and can be used to access the object."
2067 So the ABI guarantees that we can always find the return
2068 value just after the function has returned. */
2070 /* Note that the ABI doesn't mention functions returning arrays,
2071 which is something possible in certain languages such as Ada.
2072 In this case, the value is returned as if it was wrapped in
2073 a record, so the convention applied to records also applies
2080 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2081 read_memory (addr, readbuf, TYPE_LENGTH (type));
2084 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2087 /* This special case is for structures consisting of a single
2088 `float', `double' or 'long double' member. These structures are
2089 returned in %st(0). For these structures, we call ourselves
2090 recursively, changing TYPE into the type of the first member of
2091 the structure. Since that should work for all structures that
2092 have only one member, we don't bother to check the member's type
2094 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2096 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2097 return i386_return_value (gdbarch, func_type, type, regcache,
2102 i386_extract_return_value (gdbarch, type, regcache, readbuf);
2104 i386_store_return_value (gdbarch, type, regcache, writebuf);
2106 return RETURN_VALUE_REGISTER_CONVENTION;
2111 i387_ext_type (struct gdbarch *gdbarch)
2113 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2115 if (!tdep->i387_ext_type)
2117 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
2118 gdb_assert (tdep->i387_ext_type != NULL);
2121 return tdep->i387_ext_type;
2124 /* Construct vector type for MMX registers. */
2125 static struct type *
2126 i386_mmx_type (struct gdbarch *gdbarch)
2128 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2130 if (!tdep->i386_mmx_type)
2132 const struct builtin_type *bt = builtin_type (gdbarch);
2134 /* The type we're building is this: */
2136 union __gdb_builtin_type_vec64i
2139 int32_t v2_int32[2];
2140 int16_t v4_int16[4];
2147 t = arch_composite_type (gdbarch,
2148 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
2150 append_composite_type_field (t, "uint64", bt->builtin_int64);
2151 append_composite_type_field (t, "v2_int32",
2152 init_vector_type (bt->builtin_int32, 2));
2153 append_composite_type_field (t, "v4_int16",
2154 init_vector_type (bt->builtin_int16, 4));
2155 append_composite_type_field (t, "v8_int8",
2156 init_vector_type (bt->builtin_int8, 8));
2158 TYPE_VECTOR (t) = 1;
2159 TYPE_NAME (t) = "builtin_type_vec64i";
2160 tdep->i386_mmx_type = t;
2163 return tdep->i386_mmx_type;
2166 /* Return the GDB type object for the "standard" data type of data in
2169 static struct type *
2170 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2172 gdb_assert (i386_mmx_regnum_p (gdbarch, regnum));
2173 return i386_mmx_type (gdbarch);
2176 /* Map a cooked register onto a raw register or memory. For the i386,
2177 the MMX registers need to be mapped onto floating point registers. */
2180 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
2182 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
2187 mmxreg = regnum - tdep->mm0_regnum;
2188 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2189 tos = (fstat >> 11) & 0x7;
2190 fpreg = (mmxreg + tos) % 8;
2192 return (I387_ST0_REGNUM (tdep) + fpreg);
2196 i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2197 int regnum, gdb_byte *buf)
2199 if (i386_mmx_regnum_p (gdbarch, regnum))
2201 gdb_byte mmx_buf[MAX_REGISTER_SIZE];
2202 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2204 /* Extract (always little endian). */
2205 regcache_raw_read (regcache, fpnum, mmx_buf);
2206 memcpy (buf, mmx_buf, register_size (gdbarch, regnum));
2209 regcache_raw_read (regcache, regnum, buf);
2213 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2214 int regnum, const gdb_byte *buf)
2216 if (i386_mmx_regnum_p (gdbarch, regnum))
2218 gdb_byte mmx_buf[MAX_REGISTER_SIZE];
2219 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2222 regcache_raw_read (regcache, fpnum, mmx_buf);
2223 /* ... Modify ... (always little endian). */
2224 memcpy (mmx_buf, buf, register_size (gdbarch, regnum));
2226 regcache_raw_write (regcache, fpnum, mmx_buf);
2229 regcache_raw_write (regcache, regnum, buf);
2233 /* Return the register number of the register allocated by GCC after
2234 REGNUM, or -1 if there is no such register. */
2237 i386_next_regnum (int regnum)
2239 /* GCC allocates the registers in the order:
2241 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2243 Since storing a variable in %esp doesn't make any sense we return
2244 -1 for %ebp and for %esp itself. */
2245 static int next_regnum[] =
2247 I386_EDX_REGNUM, /* Slot for %eax. */
2248 I386_EBX_REGNUM, /* Slot for %ecx. */
2249 I386_ECX_REGNUM, /* Slot for %edx. */
2250 I386_ESI_REGNUM, /* Slot for %ebx. */
2251 -1, -1, /* Slots for %esp and %ebp. */
2252 I386_EDI_REGNUM, /* Slot for %esi. */
2253 I386_EBP_REGNUM /* Slot for %edi. */
2256 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
2257 return next_regnum[regnum];
2262 /* Return nonzero if a value of type TYPE stored in register REGNUM
2263 needs any special handling. */
2266 i386_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type)
2268 int len = TYPE_LENGTH (type);
2270 /* Values may be spread across multiple registers. Most debugging
2271 formats aren't expressive enough to specify the locations, so
2272 some heuristics is involved. Right now we only handle types that
2273 have a length that is a multiple of the word size, since GCC
2274 doesn't seem to put any other types into registers. */
2275 if (len > 4 && len % 4 == 0)
2277 int last_regnum = regnum;
2281 last_regnum = i386_next_regnum (last_regnum);
2285 if (last_regnum != -1)
2289 return i387_convert_register_p (gdbarch, regnum, type);
2292 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2293 return its contents in TO. */
2296 i386_register_to_value (struct frame_info *frame, int regnum,
2297 struct type *type, gdb_byte *to)
2299 struct gdbarch *gdbarch = get_frame_arch (frame);
2300 int len = TYPE_LENGTH (type);
2302 /* FIXME: kettenis/20030609: What should we do if REGNUM isn't
2303 available in FRAME (i.e. if it wasn't saved)? */
2305 if (i386_fp_regnum_p (gdbarch, regnum))
2307 i387_register_to_value (frame, regnum, type, to);
2311 /* Read a value spread across multiple registers. */
2313 gdb_assert (len > 4 && len % 4 == 0);
2317 gdb_assert (regnum != -1);
2318 gdb_assert (register_size (gdbarch, regnum) == 4);
2320 get_frame_register (frame, regnum, to);
2321 regnum = i386_next_regnum (regnum);
2327 /* Write the contents FROM of a value of type TYPE into register
2328 REGNUM in frame FRAME. */
2331 i386_value_to_register (struct frame_info *frame, int regnum,
2332 struct type *type, const gdb_byte *from)
2334 int len = TYPE_LENGTH (type);
2336 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
2338 i387_value_to_register (frame, regnum, type, from);
2342 /* Write a value spread across multiple registers. */
2344 gdb_assert (len > 4 && len % 4 == 0);
2348 gdb_assert (regnum != -1);
2349 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
2351 put_frame_register (frame, regnum, from);
2352 regnum = i386_next_regnum (regnum);
2358 /* Supply register REGNUM from the buffer specified by GREGS and LEN
2359 in the general-purpose register set REGSET to register cache
2360 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2363 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
2364 int regnum, const void *gregs, size_t len)
2366 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2367 const gdb_byte *regs = gregs;
2370 gdb_assert (len == tdep->sizeof_gregset);
2372 for (i = 0; i < tdep->gregset_num_regs; i++)
2374 if ((regnum == i || regnum == -1)
2375 && tdep->gregset_reg_offset[i] != -1)
2376 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
2380 /* Collect register REGNUM from the register cache REGCACHE and store
2381 it in the buffer specified by GREGS and LEN as described by the
2382 general-purpose register set REGSET. If REGNUM is -1, do this for
2383 all registers in REGSET. */
2386 i386_collect_gregset (const struct regset *regset,
2387 const struct regcache *regcache,
2388 int regnum, void *gregs, size_t len)
2390 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2391 gdb_byte *regs = gregs;
2394 gdb_assert (len == tdep->sizeof_gregset);
2396 for (i = 0; i < tdep->gregset_num_regs; i++)
2398 if ((regnum == i || regnum == -1)
2399 && tdep->gregset_reg_offset[i] != -1)
2400 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
2404 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2405 in the floating-point register set REGSET to register cache
2406 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2409 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
2410 int regnum, const void *fpregs, size_t len)
2412 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2414 if (len == I387_SIZEOF_FXSAVE)
2416 i387_supply_fxsave (regcache, regnum, fpregs);
2420 gdb_assert (len == tdep->sizeof_fpregset);
2421 i387_supply_fsave (regcache, regnum, fpregs);
2424 /* Collect register REGNUM from the register cache REGCACHE and store
2425 it in the buffer specified by FPREGS and LEN as described by the
2426 floating-point register set REGSET. If REGNUM is -1, do this for
2427 all registers in REGSET. */
2430 i386_collect_fpregset (const struct regset *regset,
2431 const struct regcache *regcache,
2432 int regnum, void *fpregs, size_t len)
2434 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2436 if (len == I387_SIZEOF_FXSAVE)
2438 i387_collect_fxsave (regcache, regnum, fpregs);
2442 gdb_assert (len == tdep->sizeof_fpregset);
2443 i387_collect_fsave (regcache, regnum, fpregs);
2446 /* Return the appropriate register set for the core section identified
2447 by SECT_NAME and SECT_SIZE. */
2449 const struct regset *
2450 i386_regset_from_core_section (struct gdbarch *gdbarch,
2451 const char *sect_name, size_t sect_size)
2453 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2455 if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset)
2457 if (tdep->gregset == NULL)
2458 tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset,
2459 i386_collect_gregset);
2460 return tdep->gregset;
2463 if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
2464 || (strcmp (sect_name, ".reg-xfp") == 0
2465 && sect_size == I387_SIZEOF_FXSAVE))
2467 if (tdep->fpregset == NULL)
2468 tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset,
2469 i386_collect_fpregset);
2470 return tdep->fpregset;
2477 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
2480 i386_pe_skip_trampoline_code (struct frame_info *frame,
2481 CORE_ADDR pc, char *name)
2483 struct gdbarch *gdbarch = get_frame_arch (frame);
2484 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2487 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
2489 unsigned long indirect =
2490 read_memory_unsigned_integer (pc + 2, 4, byte_order);
2491 struct minimal_symbol *indsym =
2492 indirect ? lookup_minimal_symbol_by_pc (indirect) : 0;
2493 char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0;
2497 if (strncmp (symname, "__imp_", 6) == 0
2498 || strncmp (symname, "_imp_", 5) == 0)
2500 read_memory_unsigned_integer (indirect, 4, byte_order);
2503 return 0; /* Not a trampoline. */
2507 /* Return whether the THIS_FRAME corresponds to a sigtramp
2511 i386_sigtramp_p (struct frame_info *this_frame)
2513 CORE_ADDR pc = get_frame_pc (this_frame);
2516 find_pc_partial_function (pc, &name, NULL, NULL);
2517 return (name && strcmp ("_sigtramp", name) == 0);
2521 /* We have two flavours of disassembly. The machinery on this page
2522 deals with switching between those. */
2525 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
2527 gdb_assert (disassembly_flavor == att_flavor
2528 || disassembly_flavor == intel_flavor);
2530 /* FIXME: kettenis/20020915: Until disassembler_options is properly
2531 constified, cast to prevent a compiler warning. */
2532 info->disassembler_options = (char *) disassembly_flavor;
2534 return print_insn_i386 (pc, info);
2538 /* There are a few i386 architecture variants that differ only
2539 slightly from the generic i386 target. For now, we don't give them
2540 their own source file, but include them here. As a consequence,
2541 they'll always be included. */
2543 /* System V Release 4 (SVR4). */
2545 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
2549 i386_svr4_sigtramp_p (struct frame_info *this_frame)
2551 CORE_ADDR pc = get_frame_pc (this_frame);
2554 /* UnixWare uses _sigacthandler. The origin of the other symbols is
2555 currently unknown. */
2556 find_pc_partial_function (pc, &name, NULL, NULL);
2557 return (name && (strcmp ("_sigreturn", name) == 0
2558 || strcmp ("_sigacthandler", name) == 0
2559 || strcmp ("sigvechandler", name) == 0));
2562 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
2563 address of the associated sigcontext (ucontext) structure. */
2566 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
2568 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2569 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2573 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2574 sp = extract_unsigned_integer (buf, 4, byte_order);
2576 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
2583 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2585 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
2586 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
2589 /* System V Release 4 (SVR4). */
2592 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2594 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2596 /* System V Release 4 uses ELF. */
2597 i386_elf_init_abi (info, gdbarch);
2599 /* System V Release 4 has shared libraries. */
2600 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
2602 tdep->sigtramp_p = i386_svr4_sigtramp_p;
2603 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
2604 tdep->sc_pc_offset = 36 + 14 * 4;
2605 tdep->sc_sp_offset = 36 + 17 * 4;
2607 tdep->jb_pc_offset = 20;
2613 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2615 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2617 /* DJGPP doesn't have any special frames for signal handlers. */
2618 tdep->sigtramp_p = NULL;
2620 tdep->jb_pc_offset = 36;
2622 /* DJGPP does not support the SSE registers. */
2623 tdep->num_xmm_regs = 0;
2624 set_gdbarch_num_regs (gdbarch, I386_NUM_GREGS + I387_NUM_REGS);
2626 /* Native compiler is GCC, which uses the SVR4 register numbering
2627 even in COFF and STABS. See the comment in i386_gdbarch_init,
2628 before the calls to set_gdbarch_stab_reg_to_regnum and
2629 set_gdbarch_sdb_reg_to_regnum. */
2630 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
2631 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
2635 /* i386 register groups. In addition to the normal groups, add "mmx"
2638 static struct reggroup *i386_sse_reggroup;
2639 static struct reggroup *i386_mmx_reggroup;
2642 i386_init_reggroups (void)
2644 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
2645 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
2649 i386_add_reggroups (struct gdbarch *gdbarch)
2651 reggroup_add (gdbarch, i386_sse_reggroup);
2652 reggroup_add (gdbarch, i386_mmx_reggroup);
2653 reggroup_add (gdbarch, general_reggroup);
2654 reggroup_add (gdbarch, float_reggroup);
2655 reggroup_add (gdbarch, all_reggroup);
2656 reggroup_add (gdbarch, save_reggroup);
2657 reggroup_add (gdbarch, restore_reggroup);
2658 reggroup_add (gdbarch, vector_reggroup);
2659 reggroup_add (gdbarch, system_reggroup);
2663 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2664 struct reggroup *group)
2666 int sse_regnum_p = (i386_sse_regnum_p (gdbarch, regnum)
2667 || i386_mxcsr_regnum_p (gdbarch, regnum));
2668 int fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
2669 || i386_fpc_regnum_p (gdbarch, regnum));
2670 int mmx_regnum_p = (i386_mmx_regnum_p (gdbarch, regnum));
2672 if (group == i386_mmx_reggroup)
2673 return mmx_regnum_p;
2674 if (group == i386_sse_reggroup)
2675 return sse_regnum_p;
2676 if (group == vector_reggroup)
2677 return (mmx_regnum_p || sse_regnum_p);
2678 if (group == float_reggroup)
2680 if (group == general_reggroup)
2681 return (!fp_regnum_p && !mmx_regnum_p && !sse_regnum_p);
2683 return default_register_reggroup_p (gdbarch, regnum, group);
2687 /* Get the ARGIth function argument for the current function. */
2690 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
2693 struct gdbarch *gdbarch = get_frame_arch (frame);
2694 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2695 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
2696 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
2700 i386_skip_permanent_breakpoint (struct regcache *regcache)
2702 CORE_ADDR current_pc = regcache_read_pc (regcache);
2704 /* On i386, breakpoint is exactly 1 byte long, so we just
2705 adjust the PC in the regcache. */
2707 regcache_write_pc (regcache, current_pc);
2711 #define PREFIX_REPZ 0x01
2712 #define PREFIX_REPNZ 0x02
2713 #define PREFIX_LOCK 0x04
2714 #define PREFIX_DATA 0x08
2715 #define PREFIX_ADDR 0x10
2726 /* i386 arith/logic operations */
2739 struct i386_record_s
2741 struct gdbarch *gdbarch;
2742 struct regcache *regcache;
2743 CORE_ADDR orig_addr;
2749 uint8_t mod, reg, rm;
2758 /* Parse "modrm" part in current memory address that irp->addr point to
2759 Return -1 if something wrong. */
2762 i386_record_modrm (struct i386_record_s *irp)
2764 struct gdbarch *gdbarch = irp->gdbarch;
2766 if (target_read_memory (irp->addr, &irp->modrm, 1))
2769 printf_unfiltered (_("Process record: error reading memory at "
2770 "addr %s len = 1.\n"),
2771 paddress (gdbarch, irp->addr));
2775 irp->mod = (irp->modrm >> 6) & 3;
2776 irp->reg = (irp->modrm >> 3) & 7;
2777 irp->rm = irp->modrm & 7;
2782 /* Get the memory address that current instruction write to and set it to
2783 the argument "addr".
2784 Return -1 if something wrong. */
2787 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
2789 struct gdbarch *gdbarch = irp->gdbarch;
2793 ULONGEST tmpulongest;
2802 uint8_t base = irp->rm;
2807 if (target_read_memory (irp->addr, &tmpu8, 1))
2810 printf_unfiltered (_("Process record: error reading memory "
2811 "at addr %s len = 1.\n"),
2812 paddress (gdbarch, irp->addr));
2816 scale = (tmpu8 >> 6) & 3;
2817 index = ((tmpu8 >> 3) & 7) | irp->rex_x;
2825 if ((base & 7) == 5)
2828 if (target_read_memory (irp->addr, (gdb_byte *) &tmpi32, 4))
2831 printf_unfiltered (_("Process record: error reading "
2832 "memory at addr %s len = 4.\n"),
2833 paddress (gdbarch, irp->addr));
2838 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
2839 *addr += irp->addr + irp->rip_offset;
2847 if (target_read_memory (irp->addr, &tmpu8, 1))
2850 printf_unfiltered (_("Process record: error reading memory "
2851 "at addr %s len = 1.\n"),
2852 paddress (gdbarch, irp->addr));
2856 *addr = (int8_t) tmpu8;
2859 if (target_read_memory (irp->addr, (gdb_byte *) &tmpi32, 4))
2862 printf_unfiltered (_("Process record: error reading memory "
2863 "at addr %s len = 4.\n"),
2864 paddress (gdbarch, irp->addr));
2875 if (base == 4 && irp->popl_esp_hack)
2876 *addr += irp->popl_esp_hack;
2877 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
2880 if (irp->aflag == 2)
2882 *addr += tmpulongest;
2885 *addr = (uint32_t) (tmpulongest + *addr);
2887 if (havesib && (index != 4 || scale != 0))
2889 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
2891 if (irp->aflag == 2)
2892 *addr += tmpulongest << scale;
2894 *addr = (uint32_t) (*addr + (tmpulongest << scale));
2905 if (target_read_memory
2906 (irp->addr, (gdb_byte *) &tmpi16, 2))
2909 printf_unfiltered (_("Process record: error reading "
2910 "memory at addr %s len = 2.\n"),
2911 paddress (gdbarch, irp->addr));
2925 if (target_read_memory (irp->addr, &tmpu8, 1))
2928 printf_unfiltered (_("Process record: error reading memory "
2929 "at addr %s len = 1.\n"),
2930 paddress (gdbarch, irp->addr));
2934 *addr = (int8_t) tmpu8;
2937 if (target_read_memory (irp->addr, (gdb_byte *) &tmpi16, 2))
2940 printf_unfiltered (_("Process record: error reading memory "
2941 "at addr %s len = 2.\n"),
2942 paddress (gdbarch, irp->addr));
2953 regcache_raw_read_unsigned (irp->regcache,
2954 irp->regmap[X86_RECORD_REBX_REGNUM],
2956 *addr = (uint32_t) (*addr + tmpulongest);
2957 regcache_raw_read_unsigned (irp->regcache,
2958 irp->regmap[X86_RECORD_RESI_REGNUM],
2960 *addr = (uint32_t) (*addr + tmpulongest);
2963 regcache_raw_read_unsigned (irp->regcache,
2964 irp->regmap[X86_RECORD_REBX_REGNUM],
2966 *addr = (uint32_t) (*addr + tmpulongest);
2967 regcache_raw_read_unsigned (irp->regcache,
2968 irp->regmap[X86_RECORD_REDI_REGNUM],
2970 *addr = (uint32_t) (*addr + tmpulongest);
2973 regcache_raw_read_unsigned (irp->regcache,
2974 irp->regmap[X86_RECORD_REBP_REGNUM],
2976 *addr = (uint32_t) (*addr + tmpulongest);
2977 regcache_raw_read_unsigned (irp->regcache,
2978 irp->regmap[X86_RECORD_RESI_REGNUM],
2980 *addr = (uint32_t) (*addr + tmpulongest);
2983 regcache_raw_read_unsigned (irp->regcache,
2984 irp->regmap[X86_RECORD_REBP_REGNUM],
2986 *addr = (uint32_t) (*addr + tmpulongest);
2987 regcache_raw_read_unsigned (irp->regcache,
2988 irp->regmap[X86_RECORD_REDI_REGNUM],
2990 *addr = (uint32_t) (*addr + tmpulongest);
2993 regcache_raw_read_unsigned (irp->regcache,
2994 irp->regmap[X86_RECORD_RESI_REGNUM],
2996 *addr = (uint32_t) (*addr + tmpulongest);
2999 regcache_raw_read_unsigned (irp->regcache,
3000 irp->regmap[X86_RECORD_REDI_REGNUM],
3002 *addr = (uint32_t) (*addr + tmpulongest);
3005 regcache_raw_read_unsigned (irp->regcache,
3006 irp->regmap[X86_RECORD_REBP_REGNUM],
3008 *addr = (uint32_t) (*addr + tmpulongest);
3011 regcache_raw_read_unsigned (irp->regcache,
3012 irp->regmap[X86_RECORD_REBX_REGNUM],
3014 *addr = (uint32_t) (*addr + tmpulongest);
3024 /* Record the value of the memory that willbe changed in current instruction
3025 to "record_arch_list".
3026 Return -1 if something wrong. */
3029 i386_record_lea_modrm (struct i386_record_s *irp)
3031 struct gdbarch *gdbarch = irp->gdbarch;
3034 if (irp->override >= 0)
3036 warning (_("Process record ignores the memory change "
3037 "of instruction at address %s because it "
3038 "can't get the value of the segment register."),
3039 paddress (gdbarch, irp->orig_addr));
3043 if (i386_record_lea_modrm_addr (irp, &addr))
3046 if (record_arch_list_add_mem (addr, 1 << irp->ot))
3052 /* Record the push operation to "record_arch_list".
3053 Return -1 if something wrong. */
3056 i386_record_push (struct i386_record_s *irp, int size)
3058 ULONGEST tmpulongest;
3060 if (record_arch_list_add_reg (irp->regcache,
3061 irp->regmap[X86_RECORD_RESP_REGNUM]))
3063 regcache_raw_read_unsigned (irp->regcache,
3064 irp->regmap[X86_RECORD_RESP_REGNUM],
3066 if (record_arch_list_add_mem ((CORE_ADDR) tmpulongest - size, size))
3073 /* Defines contents to record. */
3074 #define I386_SAVE_FPU_REGS 0xfffd
3075 #define I386_SAVE_FPU_ENV 0xfffe
3076 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3078 /* Record the value of floating point registers which will be changed by the
3079 current instruction to "record_arch_list". Return -1 if something is wrong.
3082 static int i386_record_floats (struct gdbarch *gdbarch,
3083 struct i386_record_s *ir,
3086 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3089 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3090 happen. Currently we store st0-st7 registers, but we need not store all
3091 registers all the time, in future we use ftag register and record only
3092 those who are not marked as an empty. */
3094 if (I386_SAVE_FPU_REGS == iregnum)
3096 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
3098 if (record_arch_list_add_reg (ir->regcache, i))
3102 else if (I386_SAVE_FPU_ENV == iregnum)
3104 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3106 if (record_arch_list_add_reg (ir->regcache, i))
3110 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
3112 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3114 if (record_arch_list_add_reg (ir->regcache, i))
3118 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
3119 (iregnum <= I387_FOP_REGNUM (tdep)))
3121 if (record_arch_list_add_reg (ir->regcache,iregnum))
3126 /* Parameter error. */
3129 if(I386_SAVE_FPU_ENV != iregnum)
3131 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3133 if (record_arch_list_add_reg (ir->regcache, i))
3140 /* Parse the current instruction and record the values of the registers and
3141 memory that will be changed in current instruction to "record_arch_list".
3142 Return -1 if something wrong. */
3144 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3145 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3148 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
3155 ULONGEST tmpulongest;
3157 struct i386_record_s ir;
3158 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3163 memset (&ir, 0, sizeof (struct i386_record_s));
3164 ir.regcache = regcache;
3166 ir.orig_addr = addr;
3170 ir.popl_esp_hack = 0;
3171 ir.regmap = gdbarch_tdep (gdbarch)->record_regmap;
3172 ir.gdbarch = gdbarch;
3174 if (record_debug > 1)
3175 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
3177 paddress (gdbarch, ir.addr));
3182 if (target_read_memory (ir.addr, &tmpu8, 1))
3185 printf_unfiltered (_("Process record: error reading memory at "
3186 "addr %s len = 1.\n"),
3187 paddress (gdbarch, ir.addr));
3191 switch (tmpu8) /* Instruction prefixes */
3193 case REPE_PREFIX_OPCODE:
3194 prefixes |= PREFIX_REPZ;
3196 case REPNE_PREFIX_OPCODE:
3197 prefixes |= PREFIX_REPNZ;
3199 case LOCK_PREFIX_OPCODE:
3200 prefixes |= PREFIX_LOCK;
3202 case CS_PREFIX_OPCODE:
3203 ir.override = X86_RECORD_CS_REGNUM;
3205 case SS_PREFIX_OPCODE:
3206 ir.override = X86_RECORD_SS_REGNUM;
3208 case DS_PREFIX_OPCODE:
3209 ir.override = X86_RECORD_DS_REGNUM;
3211 case ES_PREFIX_OPCODE:
3212 ir.override = X86_RECORD_ES_REGNUM;
3214 case FS_PREFIX_OPCODE:
3215 ir.override = X86_RECORD_FS_REGNUM;
3217 case GS_PREFIX_OPCODE:
3218 ir.override = X86_RECORD_GS_REGNUM;
3220 case DATA_PREFIX_OPCODE:
3221 prefixes |= PREFIX_DATA;
3223 case ADDR_PREFIX_OPCODE:
3224 prefixes |= PREFIX_ADDR;
3226 case 0x40: /* i386 inc %eax */
3227 case 0x41: /* i386 inc %ecx */
3228 case 0x42: /* i386 inc %edx */
3229 case 0x43: /* i386 inc %ebx */
3230 case 0x44: /* i386 inc %esp */
3231 case 0x45: /* i386 inc %ebp */
3232 case 0x46: /* i386 inc %esi */
3233 case 0x47: /* i386 inc %edi */
3234 case 0x48: /* i386 dec %eax */
3235 case 0x49: /* i386 dec %ecx */
3236 case 0x4a: /* i386 dec %edx */
3237 case 0x4b: /* i386 dec %ebx */
3238 case 0x4c: /* i386 dec %esp */
3239 case 0x4d: /* i386 dec %ebp */
3240 case 0x4e: /* i386 dec %esi */
3241 case 0x4f: /* i386 dec %edi */
3242 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
3246 rex_w = (tmpu8 >> 3) & 1;
3247 rex_r = (tmpu8 & 0x4) << 1;
3248 ir.rex_x = (tmpu8 & 0x2) << 2;
3249 ir.rex_b = (tmpu8 & 0x1) << 3;
3251 else /* 32 bit target */
3260 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
3266 if (prefixes & PREFIX_DATA)
3269 if (prefixes & PREFIX_ADDR)
3271 else if (ir.regmap[X86_RECORD_R8_REGNUM])
3274 /* now check op code */
3275 opcode = (uint32_t) tmpu8;
3280 if (target_read_memory (ir.addr, &tmpu8, 1))
3283 printf_unfiltered (_("Process record: error reading memory at "
3284 "addr %s len = 1.\n"),
3285 paddress (gdbarch, ir.addr));
3289 opcode = (uint16_t) tmpu8 | 0x0f00;
3293 case 0x00: /* arith & logic */
3341 if (((opcode >> 3) & 7) != OP_CMPL)
3343 if ((opcode & 1) == 0)
3346 ir.ot = ir.dflag + OT_WORD;
3348 switch ((opcode >> 1) & 3)
3350 case 0: /* OP Ev, Gv */
3351 if (i386_record_modrm (&ir))
3355 if (i386_record_lea_modrm (&ir))
3361 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3363 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
3366 case 1: /* OP Gv, Ev */
3367 if (i386_record_modrm (&ir))
3370 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3372 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
3374 case 2: /* OP A, Iv */
3375 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
3379 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3382 case 0x80: /* GRP1 */
3386 if (i386_record_modrm (&ir))
3389 if (ir.reg != OP_CMPL)
3391 if ((opcode & 1) == 0)
3394 ir.ot = ir.dflag + OT_WORD;
3401 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
3402 if (i386_record_lea_modrm (&ir))
3406 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
3408 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3411 case 0x40: /* inc */
3420 case 0x48: /* dec */
3429 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7);
3430 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3433 case 0xf6: /* GRP3 */
3435 if ((opcode & 1) == 0)
3438 ir.ot = ir.dflag + OT_WORD;
3439 if (i386_record_modrm (&ir))
3442 if (ir.mod != 3 && ir.reg == 0)
3443 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
3448 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3454 if (i386_record_lea_modrm (&ir))
3460 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3462 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
3464 if (ir.reg == 3) /* neg */
3465 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3471 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
3472 if (ir.ot != OT_BYTE)
3473 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
3474 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3478 opcode = opcode << 8 | ir.modrm;
3484 case 0xfe: /* GRP4 */
3485 case 0xff: /* GRP5 */
3486 if (i386_record_modrm (&ir))
3488 if (ir.reg >= 2 && opcode == 0xfe)
3491 opcode = opcode << 8 | ir.modrm;
3498 if ((opcode & 1) == 0)
3501 ir.ot = ir.dflag + OT_WORD;
3504 if (i386_record_lea_modrm (&ir))
3510 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3512 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
3514 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3517 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
3519 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
3521 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3524 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
3525 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
3527 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3531 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3534 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
3536 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
3541 opcode = opcode << 8 | ir.modrm;
3547 case 0x84: /* test */
3551 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3554 case 0x98: /* CWDE/CBW */
3555 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
3558 case 0x99: /* CDQ/CWD */
3559 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
3560 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
3563 case 0x0faf: /* imul */
3566 ir.ot = ir.dflag + OT_WORD;
3567 if (i386_record_modrm (&ir))
3570 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
3571 else if (opcode == 0x6b)
3574 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3576 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
3577 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3580 case 0x0fc0: /* xadd */
3582 if ((opcode & 1) == 0)
3585 ir.ot = ir.dflag + OT_WORD;
3586 if (i386_record_modrm (&ir))
3591 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3593 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
3594 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3596 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
3600 if (i386_record_lea_modrm (&ir))
3602 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3604 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
3606 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3609 case 0x0fb0: /* cmpxchg */
3611 if ((opcode & 1) == 0)
3614 ir.ot = ir.dflag + OT_WORD;
3615 if (i386_record_modrm (&ir))
3620 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
3621 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3623 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
3627 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
3628 if (i386_record_lea_modrm (&ir))
3631 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3634 case 0x0fc7: /* cmpxchg8b */
3635 if (i386_record_modrm (&ir))
3640 opcode = opcode << 8 | ir.modrm;
3643 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
3644 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
3645 if (i386_record_lea_modrm (&ir))
3647 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3650 case 0x50: /* push */
3660 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
3662 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
3666 case 0x06: /* push es */
3667 case 0x0e: /* push cs */
3668 case 0x16: /* push ss */
3669 case 0x1e: /* push ds */
3670 if (ir.regmap[X86_RECORD_R8_REGNUM])
3675 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
3679 case 0x0fa0: /* push fs */
3680 case 0x0fa8: /* push gs */
3681 if (ir.regmap[X86_RECORD_R8_REGNUM])
3686 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
3690 case 0x60: /* pusha */
3691 if (ir.regmap[X86_RECORD_R8_REGNUM])
3696 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
3700 case 0x58: /* pop */
3708 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
3709 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
3712 case 0x61: /* popa */
3713 if (ir.regmap[X86_RECORD_R8_REGNUM])
3718 for (tmpu8 = X86_RECORD_REAX_REGNUM; tmpu8 <= X86_RECORD_REDI_REGNUM;
3720 I386_RECORD_ARCH_LIST_ADD_REG (tmpu8);
3723 case 0x8f: /* pop */
3724 if (ir.regmap[X86_RECORD_R8_REGNUM])
3725 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
3727 ir.ot = ir.dflag + OT_WORD;
3728 if (i386_record_modrm (&ir))
3731 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
3734 ir.popl_esp_hack = 1 << ir.ot;
3735 if (i386_record_lea_modrm (&ir))
3738 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
3741 case 0xc8: /* enter */
3742 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
3743 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
3745 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
3749 case 0xc9: /* leave */
3750 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
3751 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
3754 case 0x07: /* pop es */
3755 if (ir.regmap[X86_RECORD_R8_REGNUM])
3760 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
3761 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
3762 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3765 case 0x17: /* pop ss */
3766 if (ir.regmap[X86_RECORD_R8_REGNUM])
3771 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
3772 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
3773 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3776 case 0x1f: /* pop ds */
3777 if (ir.regmap[X86_RECORD_R8_REGNUM])
3782 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
3783 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
3784 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3787 case 0x0fa1: /* pop fs */
3788 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
3789 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
3790 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3793 case 0x0fa9: /* pop gs */
3794 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
3795 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
3796 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3799 case 0x88: /* mov */
3803 if ((opcode & 1) == 0)
3806 ir.ot = ir.dflag + OT_WORD;
3808 if (i386_record_modrm (&ir))
3813 if (opcode == 0xc6 || opcode == 0xc7)
3814 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
3815 if (i386_record_lea_modrm (&ir))
3820 if (opcode == 0xc6 || opcode == 0xc7)
3822 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3824 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
3828 case 0x8a: /* mov */
3830 if ((opcode & 1) == 0)
3833 ir.ot = ir.dflag + OT_WORD;
3834 if (i386_record_modrm (&ir))
3837 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3839 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
3842 case 0x8c: /* mov seg */
3843 if (i386_record_modrm (&ir))
3848 opcode = opcode << 8 | ir.modrm;
3853 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
3857 if (i386_record_lea_modrm (&ir))
3862 case 0x8e: /* mov seg */
3863 if (i386_record_modrm (&ir))
3868 tmpu8 = X86_RECORD_ES_REGNUM;
3871 tmpu8 = X86_RECORD_SS_REGNUM;
3874 tmpu8 = X86_RECORD_DS_REGNUM;
3877 tmpu8 = X86_RECORD_FS_REGNUM;
3880 tmpu8 = X86_RECORD_GS_REGNUM;
3884 opcode = opcode << 8 | ir.modrm;
3888 I386_RECORD_ARCH_LIST_ADD_REG (tmpu8);
3889 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3892 case 0x0fb6: /* movzbS */
3893 case 0x0fb7: /* movzwS */
3894 case 0x0fbe: /* movsbS */
3895 case 0x0fbf: /* movswS */
3896 if (i386_record_modrm (&ir))
3898 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
3901 case 0x8d: /* lea */
3902 if (i386_record_modrm (&ir))
3907 opcode = opcode << 8 | ir.modrm;
3912 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3914 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
3917 case 0xa0: /* mov EAX */
3920 case 0xd7: /* xlat */
3921 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
3924 case 0xa2: /* mov EAX */
3926 if (ir.override >= 0)
3928 warning (_("Process record ignores the memory change "
3929 "of instruction at address %s because "
3930 "it can't get the value of the segment "
3932 paddress (gdbarch, ir.orig_addr));
3936 if ((opcode & 1) == 0)
3939 ir.ot = ir.dflag + OT_WORD;
3942 if (target_read_memory (ir.addr, (gdb_byte *) &addr, 8))
3945 printf_unfiltered (_("Process record: error reading "
3946 "memory at addr 0x%s len = 8.\n"),
3947 paddress (gdbarch, ir.addr));
3954 if (target_read_memory (ir.addr, (gdb_byte *) &tmpu32, 4))
3957 printf_unfiltered (_("Process record: error reading "
3958 "memory at addr 0x%s len = 4.\n"),
3959 paddress (gdbarch, ir.addr));
3967 if (target_read_memory (ir.addr, (gdb_byte *) &tmpu16, 2))
3970 printf_unfiltered (_("Process record: error reading "
3971 "memory at addr 0x%s len = 2.\n"),
3972 paddress (gdbarch, ir.addr));
3978 if (record_arch_list_add_mem (addr, 1 << ir.ot))
3983 case 0xb0: /* mov R, Ib */
3991 I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
3992 ? ((opcode & 0x7) | ir.rex_b)
3993 : ((opcode & 0x7) & 0x3));
3996 case 0xb8: /* mov R, Iv */
4004 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
4007 case 0x91: /* xchg R, EAX */
4014 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4015 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7);
4018 case 0x86: /* xchg Ev, Gv */
4020 if ((opcode & 1) == 0)
4023 ir.ot = ir.dflag + OT_WORD;
4024 if (i386_record_modrm (&ir))
4029 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4031 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4035 if (i386_record_lea_modrm (&ir))
4039 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4041 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4044 case 0xc4: /* les Gv */
4045 case 0xc5: /* lds Gv */
4046 if (ir.regmap[X86_RECORD_R8_REGNUM])
4051 case 0x0fb2: /* lss Gv */
4052 case 0x0fb4: /* lfs Gv */
4053 case 0x0fb5: /* lgs Gv */
4054 if (i386_record_modrm (&ir))
4062 opcode = opcode << 8 | ir.modrm;
4067 case 0xc4: /* les Gv */
4068 tmpu8 = X86_RECORD_ES_REGNUM;
4070 case 0xc5: /* lds Gv */
4071 tmpu8 = X86_RECORD_DS_REGNUM;
4073 case 0x0fb2: /* lss Gv */
4074 tmpu8 = X86_RECORD_SS_REGNUM;
4076 case 0x0fb4: /* lfs Gv */
4077 tmpu8 = X86_RECORD_FS_REGNUM;
4079 case 0x0fb5: /* lgs Gv */
4080 tmpu8 = X86_RECORD_GS_REGNUM;
4083 I386_RECORD_ARCH_LIST_ADD_REG (tmpu8);
4084 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
4085 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4088 case 0xc0: /* shifts */
4094 if ((opcode & 1) == 0)
4097 ir.ot = ir.dflag + OT_WORD;
4098 if (i386_record_modrm (&ir))
4100 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
4102 if (i386_record_lea_modrm (&ir))
4108 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4110 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4112 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4119 if (i386_record_modrm (&ir))
4123 if (record_arch_list_add_reg (ir.regcache, ir.rm))
4128 if (i386_record_lea_modrm (&ir))
4133 case 0xd8: /* Floats. */
4141 if (i386_record_modrm (&ir))
4143 ir.reg |= ((opcode & 7) << 3);
4149 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
4157 /* For fcom, ficom nothing to do. */
4163 /* For fcomp, ficomp pop FPU stack, store all. */
4164 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4191 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
4192 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
4193 of code, always affects st(0) register. */
4194 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
4218 /* Handling fld, fild. */
4219 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4223 switch (ir.reg >> 4)
4226 if (record_arch_list_add_mem (tmpu64, 4))
4230 if (record_arch_list_add_mem (tmpu64, 8))
4236 if (record_arch_list_add_mem (tmpu64, 2))
4242 switch (ir.reg >> 4)
4245 if (record_arch_list_add_mem (tmpu64, 4))
4247 if (3 == (ir.reg & 7))
4249 /* For fstp m32fp. */
4250 if (i386_record_floats (gdbarch, &ir,
4251 I386_SAVE_FPU_REGS))
4256 if (record_arch_list_add_mem (tmpu64, 4))
4258 if ((3 == (ir.reg & 7))
4259 || (5 == (ir.reg & 7))
4260 || (7 == (ir.reg & 7)))
4262 /* For fstp insn. */
4263 if (i386_record_floats (gdbarch, &ir,
4264 I386_SAVE_FPU_REGS))
4269 if (record_arch_list_add_mem (tmpu64, 8))
4271 if (3 == (ir.reg & 7))
4273 /* For fstp m64fp. */
4274 if (i386_record_floats (gdbarch, &ir,
4275 I386_SAVE_FPU_REGS))
4280 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
4282 /* For fistp, fbld, fild, fbstp. */
4283 if (i386_record_floats (gdbarch, &ir,
4284 I386_SAVE_FPU_REGS))
4289 if (record_arch_list_add_mem (tmpu64, 2))
4298 if (i386_record_floats (gdbarch, &ir,
4299 I386_SAVE_FPU_ENV_REG_STACK))
4304 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
4309 if (i386_record_floats (gdbarch, &ir,
4310 I386_SAVE_FPU_ENV_REG_STACK))
4316 if (record_arch_list_add_mem (tmpu64, 28))
4321 if (record_arch_list_add_mem (tmpu64, 14))
4327 if (record_arch_list_add_mem (tmpu64, 2))
4329 /* Insn fstp, fbstp. */
4330 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4335 if (record_arch_list_add_mem (tmpu64, 10))
4341 if (record_arch_list_add_mem (tmpu64, 28))
4347 if (record_arch_list_add_mem (tmpu64, 14))
4351 if (record_arch_list_add_mem (tmpu64, 80))
4354 if (i386_record_floats (gdbarch, &ir,
4355 I386_SAVE_FPU_ENV_REG_STACK))
4359 if (record_arch_list_add_mem (tmpu64, 8))
4362 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4367 opcode = opcode << 8 | ir.modrm;
4372 /* Opcode is an extension of modR/M byte. */
4378 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
4382 if (0x0c == (ir.modrm >> 4))
4384 if ((ir.modrm & 0x0f) <= 7)
4386 if (i386_record_floats (gdbarch, &ir,
4387 I386_SAVE_FPU_REGS))
4392 if (i386_record_floats (gdbarch, &ir,
4393 I387_ST0_REGNUM (tdep)))
4395 /* If only st(0) is changing, then we have already
4397 if ((ir.modrm & 0x0f) - 0x08)
4399 if (i386_record_floats (gdbarch, &ir,
4400 I387_ST0_REGNUM (tdep) +
4401 ((ir.modrm & 0x0f) - 0x08)))
4419 if (i386_record_floats (gdbarch, &ir,
4420 I387_ST0_REGNUM (tdep)))
4438 if (i386_record_floats (gdbarch, &ir,
4439 I386_SAVE_FPU_REGS))
4443 if (i386_record_floats (gdbarch, &ir,
4444 I387_ST0_REGNUM (tdep)))
4446 if (i386_record_floats (gdbarch, &ir,
4447 I387_ST0_REGNUM (tdep) + 1))
4454 if (0xe9 == ir.modrm)
4456 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4459 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
4461 if (i386_record_floats (gdbarch, &ir,
4462 I387_ST0_REGNUM (tdep)))
4464 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
4466 if (i386_record_floats (gdbarch, &ir,
4467 I387_ST0_REGNUM (tdep) +
4471 else if ((ir.modrm & 0x0f) - 0x08)
4473 if (i386_record_floats (gdbarch, &ir,
4474 I387_ST0_REGNUM (tdep) +
4475 ((ir.modrm & 0x0f) - 0x08)))
4481 if (0xe3 == ir.modrm)
4483 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
4486 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
4488 if (i386_record_floats (gdbarch, &ir,
4489 I387_ST0_REGNUM (tdep)))
4491 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
4493 if (i386_record_floats (gdbarch, &ir,
4494 I387_ST0_REGNUM (tdep) +
4498 else if ((ir.modrm & 0x0f) - 0x08)
4500 if (i386_record_floats (gdbarch, &ir,
4501 I387_ST0_REGNUM (tdep) +
4502 ((ir.modrm & 0x0f) - 0x08)))
4508 if ((0x0c == ir.modrm >> 4)
4509 || (0x0d == ir.modrm >> 4)
4510 || (0x0f == ir.modrm >> 4))
4512 if ((ir.modrm & 0x0f) <= 7)
4514 if (i386_record_floats (gdbarch, &ir,
4515 I387_ST0_REGNUM (tdep) +
4521 if (i386_record_floats (gdbarch, &ir,
4522 I387_ST0_REGNUM (tdep) +
4523 ((ir.modrm & 0x0f) - 0x08)))
4529 if (0x0c == ir.modrm >> 4)
4531 if (i386_record_floats (gdbarch, &ir,
4532 I387_FTAG_REGNUM (tdep)))
4535 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
4537 if ((ir.modrm & 0x0f) <= 7)
4539 if (i386_record_floats (gdbarch, &ir,
4540 I387_ST0_REGNUM (tdep) +
4546 if (i386_record_floats (gdbarch, &ir,
4547 I386_SAVE_FPU_REGS))
4553 if ((0x0c == ir.modrm >> 4)
4554 || (0x0e == ir.modrm >> 4)
4555 || (0x0f == ir.modrm >> 4)
4556 || (0xd9 == ir.modrm))
4558 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4563 if (0xe0 == ir.modrm)
4565 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
4568 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
4570 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4578 case 0xa4: /* movsS */
4580 case 0xaa: /* stosS */
4582 case 0x6c: /* insS */
4584 regcache_raw_read_unsigned (ir.regcache,
4585 ir.regmap[X86_RECORD_RECX_REGNUM],
4591 if ((opcode & 1) == 0)
4594 ir.ot = ir.dflag + OT_WORD;
4595 regcache_raw_read_unsigned (ir.regcache,
4596 ir.regmap[X86_RECORD_REDI_REGNUM],
4599 regcache_raw_read_unsigned (ir.regcache,
4600 ir.regmap[X86_RECORD_ES_REGNUM],
4602 regcache_raw_read_unsigned (ir.regcache,
4603 ir.regmap[X86_RECORD_DS_REGNUM],
4605 if (ir.aflag && (es != ds))
4607 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
4608 warning (_("Process record ignores the memory "
4609 "change of instruction at address %s "
4610 "because it can't get the value of the "
4611 "ES segment register."),
4612 paddress (gdbarch, ir.orig_addr));
4616 if (record_arch_list_add_mem (tmpulongest, 1 << ir.ot))
4620 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
4621 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
4622 if (opcode == 0xa4 || opcode == 0xa5)
4623 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
4624 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
4625 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4629 case 0xa6: /* cmpsS */
4631 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
4632 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
4633 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
4634 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
4635 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4638 case 0xac: /* lodsS */
4640 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4641 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
4642 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
4643 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
4644 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4647 case 0xae: /* scasS */
4649 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
4650 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
4651 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
4652 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4655 case 0x6e: /* outsS */
4657 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
4658 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
4659 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
4660 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4663 case 0xe4: /* port I/O */
4667 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4668 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4678 case 0xc2: /* ret im */
4679 case 0xc3: /* ret */
4680 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4681 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4684 case 0xca: /* lret im */
4685 case 0xcb: /* lret */
4686 case 0xcf: /* iret */
4687 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
4688 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4689 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4692 case 0xe8: /* call im */
4693 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4695 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4699 case 0x9a: /* lcall im */
4700 if (ir.regmap[X86_RECORD_R8_REGNUM])
4705 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
4706 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4710 case 0xe9: /* jmp im */
4711 case 0xea: /* ljmp im */
4712 case 0xeb: /* jmp Jb */
4713 case 0x70: /* jcc Jb */
4729 case 0x0f80: /* jcc Jv */
4747 case 0x0f90: /* setcc Gv */
4763 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4765 if (i386_record_modrm (&ir))
4768 I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
4772 if (i386_record_lea_modrm (&ir))
4777 case 0x0f40: /* cmov Gv, Ev */
4793 if (i386_record_modrm (&ir))
4796 if (ir.dflag == OT_BYTE)
4798 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4802 case 0x9c: /* pushf */
4803 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4804 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4806 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4810 case 0x9d: /* popf */
4811 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4812 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4815 case 0x9e: /* sahf */
4816 if (ir.regmap[X86_RECORD_R8_REGNUM])
4821 case 0xf5: /* cmc */
4822 case 0xf8: /* clc */
4823 case 0xf9: /* stc */
4824 case 0xfc: /* cld */
4825 case 0xfd: /* std */
4826 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4829 case 0x9f: /* lahf */
4830 if (ir.regmap[X86_RECORD_R8_REGNUM])
4835 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4836 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4839 /* bit operations */
4840 case 0x0fba: /* bt/bts/btr/btc Gv, im */
4841 ir.ot = ir.dflag + OT_WORD;
4842 if (i386_record_modrm (&ir))
4847 opcode = opcode << 8 | ir.modrm;
4853 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
4856 if (i386_record_lea_modrm (&ir))
4860 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4863 case 0x0fa3: /* bt Gv, Ev */
4864 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4867 case 0x0fab: /* bts */
4868 case 0x0fb3: /* btr */
4869 case 0x0fbb: /* btc */
4870 ir.ot = ir.dflag + OT_WORD;
4871 if (i386_record_modrm (&ir))
4874 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
4878 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
4880 regcache_raw_read_unsigned (ir.regcache,
4881 ir.regmap[ir.reg | rex_r],
4886 tmpu64 += ((int16_t) tmpulongest >> 4) << 4;
4889 tmpu64 += ((int32_t) tmpulongest >> 5) << 5;
4892 tmpu64 += ((int64_t) tmpulongest >> 6) << 6;
4895 if (record_arch_list_add_mem (tmpu64, 1 << ir.ot))
4897 if (i386_record_lea_modrm (&ir))
4900 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4903 case 0x0fbc: /* bsf */
4904 case 0x0fbd: /* bsr */
4905 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
4906 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4910 case 0x27: /* daa */
4911 case 0x2f: /* das */
4912 case 0x37: /* aaa */
4913 case 0x3f: /* aas */
4914 case 0xd4: /* aam */
4915 case 0xd5: /* aad */
4916 if (ir.regmap[X86_RECORD_R8_REGNUM])
4921 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4922 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4926 case 0x90: /* nop */
4927 if (prefixes & PREFIX_LOCK)
4934 case 0x9b: /* fwait */
4935 if (target_read_memory (ir.addr, &tmpu8, 1))
4938 printf_unfiltered (_("Process record: error reading memory at "
4939 "addr 0x%s len = 1.\n"),
4940 paddress (gdbarch, ir.addr));
4943 opcode = (uint32_t) tmpu8;
4949 case 0xcc: /* int3 */
4950 printf_unfiltered (_("Process record doesn't support instruction "
4957 case 0xcd: /* int */
4960 if (target_read_memory (ir.addr, &tmpu8, 1))
4963 printf_unfiltered (_("Process record: error reading memory "
4964 "at addr %s len = 1.\n"),
4965 paddress (gdbarch, ir.addr));
4970 || gdbarch_tdep (gdbarch)->i386_intx80_record == NULL)
4972 printf_unfiltered (_("Process record doesn't support "
4973 "instruction int 0x%02x.\n"),
4978 ret = gdbarch_tdep (gdbarch)->i386_intx80_record (ir.regcache);
4985 case 0xce: /* into */
4986 printf_unfiltered (_("Process record doesn't support "
4987 "instruction into.\n"));
4992 case 0xfa: /* cli */
4993 case 0xfb: /* sti */
4996 case 0x62: /* bound */
4997 printf_unfiltered (_("Process record doesn't support "
4998 "instruction bound.\n"));
5003 case 0x0fc8: /* bswap reg */
5011 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
5014 case 0xd6: /* salc */
5015 if (ir.regmap[X86_RECORD_R8_REGNUM])
5020 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5021 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5024 case 0xe0: /* loopnz */
5025 case 0xe1: /* loopz */
5026 case 0xe2: /* loop */
5027 case 0xe3: /* jecxz */
5028 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5029 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5032 case 0x0f30: /* wrmsr */
5033 printf_unfiltered (_("Process record doesn't support "
5034 "instruction wrmsr.\n"));
5039 case 0x0f32: /* rdmsr */
5040 printf_unfiltered (_("Process record doesn't support "
5041 "instruction rdmsr.\n"));
5046 case 0x0f31: /* rdtsc */
5047 printf_unfiltered (_("Process record doesn't support "
5048 "instruction rdtsc.\n"));
5053 case 0x0f34: /* sysenter */
5056 if (ir.regmap[X86_RECORD_R8_REGNUM])
5061 if (gdbarch_tdep (gdbarch)->i386_sysenter_record == NULL)
5063 printf_unfiltered (_("Process record doesn't support "
5064 "instruction sysenter.\n"));
5068 ret = gdbarch_tdep (gdbarch)->i386_sysenter_record (ir.regcache);
5074 case 0x0f35: /* sysexit */
5075 printf_unfiltered (_("Process record doesn't support "
5076 "instruction sysexit.\n"));
5081 case 0x0f05: /* syscall */
5084 if (gdbarch_tdep (gdbarch)->i386_syscall_record == NULL)
5086 printf_unfiltered (_("Process record doesn't support "
5087 "instruction syscall.\n"));
5091 ret = gdbarch_tdep (gdbarch)->i386_syscall_record (ir.regcache);
5097 case 0x0f07: /* sysret */
5098 printf_unfiltered (_("Process record doesn't support "
5099 "instruction sysret.\n"));
5104 case 0x0fa2: /* cpuid */
5105 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5106 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5107 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5108 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
5111 case 0xf4: /* hlt */
5112 printf_unfiltered (_("Process record doesn't support "
5113 "instruction hlt.\n"));
5119 if (i386_record_modrm (&ir))
5126 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5130 if (i386_record_lea_modrm (&ir))
5139 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5143 opcode = opcode << 8 | ir.modrm;
5150 if (i386_record_modrm (&ir))
5161 opcode = opcode << 8 | ir.modrm;
5164 if (ir.override >= 0)
5166 warning (_("Process record ignores the memory "
5167 "change of instruction at "
5168 "address %s because it can't get "
5169 "the value of the segment "
5171 paddress (gdbarch, ir.orig_addr));
5175 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
5177 if (record_arch_list_add_mem (tmpu64, 2))
5180 if (ir.regmap[X86_RECORD_R8_REGNUM])
5182 if (record_arch_list_add_mem (tmpu64, 8))
5187 if (record_arch_list_add_mem (tmpu64, 4))
5198 case 0: /* monitor */
5201 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5205 opcode = opcode << 8 | ir.modrm;
5213 if (ir.override >= 0)
5215 warning (_("Process record ignores the memory "
5216 "change of instruction at "
5217 "address %s because it can't get "
5218 "the value of the segment "
5220 paddress (gdbarch, ir.orig_addr));
5226 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
5228 if (record_arch_list_add_mem (tmpu64, 2))
5231 if (ir.regmap[X86_RECORD_R8_REGNUM])
5233 if (record_arch_list_add_mem (tmpu64, 8))
5238 if (record_arch_list_add_mem (tmpu64, 4))
5250 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5251 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5255 else if (ir.rm == 1)
5262 opcode = opcode << 8 | ir.modrm;
5269 if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
5275 if (i386_record_lea_modrm (&ir))
5278 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5281 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5283 case 7: /* invlpg */
5286 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
5287 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
5291 opcode = opcode << 8 | ir.modrm;
5296 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5300 opcode = opcode << 8 | ir.modrm;
5306 case 0x0f08: /* invd */
5307 case 0x0f09: /* wbinvd */
5310 case 0x63: /* arpl */
5311 if (i386_record_modrm (&ir))
5313 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
5315 I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
5316 ? (ir.reg | rex_r) : ir.rm);
5320 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
5321 if (i386_record_lea_modrm (&ir))
5324 if (!ir.regmap[X86_RECORD_R8_REGNUM])
5325 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5328 case 0x0f02: /* lar */
5329 case 0x0f03: /* lsl */
5330 if (i386_record_modrm (&ir))
5332 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5333 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5337 if (i386_record_modrm (&ir))
5339 if (ir.mod == 3 && ir.reg == 3)
5342 opcode = opcode << 8 | ir.modrm;
5354 /* nop (multi byte) */
5357 case 0x0f20: /* mov reg, crN */
5358 case 0x0f22: /* mov crN, reg */
5359 if (i386_record_modrm (&ir))
5361 if ((ir.modrm & 0xc0) != 0xc0)
5364 opcode = opcode << 8 | ir.modrm;
5375 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5377 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5381 opcode = opcode << 8 | ir.modrm;
5387 case 0x0f21: /* mov reg, drN */
5388 case 0x0f23: /* mov drN, reg */
5389 if (i386_record_modrm (&ir))
5391 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
5392 || ir.reg == 5 || ir.reg >= 8)
5395 opcode = opcode << 8 | ir.modrm;
5399 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5401 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5404 case 0x0f06: /* clts */
5405 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5408 /* MMX/SSE/SSE2/PNI support */
5420 /* In the future, maybe still need to deal with need_dasm. */
5421 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
5422 if (record_arch_list_add_end ())
5428 printf_unfiltered (_("Process record doesn't support instruction 0x%02x "
5429 "at address %s.\n"),
5430 (unsigned int) (opcode), paddress (gdbarch, ir.addr));
5434 static const int i386_record_regmap[] =
5436 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
5437 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
5438 0, 0, 0, 0, 0, 0, 0, 0,
5439 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
5440 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
5443 /* Check that the given address appears suitable for a fast
5444 tracepoint, which on x86 means that we need an instruction of at
5445 least 5 bytes, so that we can overwrite it with a 4-byte-offset
5446 jump and not have to worry about program jumps to an address in the
5447 middle of the tracepoint jump. Returns 1 if OK, and writes a size
5448 of instruction to replace, and 0 if not, plus an explanatory
5452 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch,
5453 CORE_ADDR addr, int *isize, char **msg)
5456 static struct ui_file *gdb_null = NULL;
5458 /* This is based on the target agent using a 4-byte relative jump.
5459 Alternate future possibilities include 8-byte offset for x86-84,
5460 or 3-byte jumps if the program has trampoline space close by. */
5463 /* Dummy file descriptor for the disassembler. */
5465 gdb_null = ui_file_new ();
5467 /* Check for fit. */
5468 len = gdb_print_insn (gdbarch, addr, gdb_null, NULL);
5471 /* Return a bit of target-specific detail to add to the caller's
5472 generic failure message. */
5474 *msg = xstrprintf (_("; instruction is only %d bytes long, need at least %d bytes for the jump"),
5487 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
5488 struct tdesc_arch_data *tdesc_data)
5490 const struct target_desc *tdesc = tdep->tdesc;
5491 const struct tdesc_feature *feature_core, *feature_vector;
5492 int i, num_regs, valid_p;
5494 if (! tdesc_has_registers (tdesc))
5497 /* Get core registers. */
5498 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
5500 /* Get SSE registers. */
5501 feature_vector = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
5503 if (feature_core == NULL || feature_vector == NULL)
5508 num_regs = tdep->num_core_regs;
5509 for (i = 0; i < num_regs; i++)
5510 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
5511 tdep->register_names[i]);
5513 /* Need to include %mxcsr, so add one. */
5514 num_regs += tdep->num_xmm_regs + 1;
5515 for (; i < num_regs; i++)
5516 valid_p &= tdesc_numbered_register (feature_vector, tdesc_data, i,
5517 tdep->register_names[i]);
5523 static struct gdbarch *
5524 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
5526 struct gdbarch_tdep *tdep;
5527 struct gdbarch *gdbarch;
5528 struct tdesc_arch_data *tdesc_data;
5529 const struct target_desc *tdesc;
5531 /* If there is already a candidate, use it. */
5532 arches = gdbarch_list_lookup_by_info (arches, &info);
5534 return arches->gdbarch;
5536 /* Allocate space for the new architecture. */
5537 tdep = XCALLOC (1, struct gdbarch_tdep);
5538 gdbarch = gdbarch_alloc (&info, tdep);
5540 /* General-purpose registers. */
5541 tdep->gregset = NULL;
5542 tdep->gregset_reg_offset = NULL;
5543 tdep->gregset_num_regs = I386_NUM_GREGS;
5544 tdep->sizeof_gregset = 0;
5546 /* Floating-point registers. */
5547 tdep->fpregset = NULL;
5548 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
5550 /* The default settings include the FPU registers, the MMX registers
5551 and the SSE registers. This can be overridden for a specific ABI
5552 by adjusting the members `st0_regnum', `mm0_regnum' and
5553 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
5554 will show up in the output of "info all-registers". Ideally we
5555 should try to autodetect whether they are available, such that we
5556 can prevent "info all-registers" from displaying registers that
5559 NOTE: kevinb/2003-07-13: ... if it's a choice between printing
5560 [the SSE registers] always (even when they don't exist) or never
5561 showing them to the user (even when they do exist), I prefer the
5562 former over the latter. */
5564 tdep->st0_regnum = I386_ST0_REGNUM;
5566 /* The MMX registers are implemented as pseudo-registers. Put off
5567 calculating the register number for %mm0 until we know the number
5568 of raw registers. */
5569 tdep->mm0_regnum = 0;
5571 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
5572 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
5574 tdep->jb_pc_offset = -1;
5575 tdep->struct_return = pcc_struct_return;
5576 tdep->sigtramp_start = 0;
5577 tdep->sigtramp_end = 0;
5578 tdep->sigtramp_p = i386_sigtramp_p;
5579 tdep->sigcontext_addr = NULL;
5580 tdep->sc_reg_offset = NULL;
5581 tdep->sc_pc_offset = -1;
5582 tdep->sc_sp_offset = -1;
5584 tdep->record_regmap = i386_record_regmap;
5586 /* The format used for `long double' on almost all i386 targets is
5587 the i387 extended floating-point format. In fact, of all targets
5588 in the GCC 2.95 tree, only OSF/1 does it different, and insists
5589 on having a `long double' that's not `long' at all. */
5590 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
5592 /* Although the i387 extended floating-point has only 80 significant
5593 bits, a `long double' actually takes up 96, probably to enforce
5595 set_gdbarch_long_double_bit (gdbarch, 96);
5597 /* Register numbers of various important registers. */
5598 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
5599 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
5600 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
5601 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
5603 /* NOTE: kettenis/20040418: GCC does have two possible register
5604 numbering schemes on the i386: dbx and SVR4. These schemes
5605 differ in how they number %ebp, %esp, %eflags, and the
5606 floating-point registers, and are implemented by the arrays
5607 dbx_register_map[] and svr4_dbx_register_map in
5608 gcc/config/i386.c. GCC also defines a third numbering scheme in
5609 gcc/config/i386.c, which it designates as the "default" register
5610 map used in 64bit mode. This last register numbering scheme is
5611 implemented in dbx64_register_map, and is used for AMD64; see
5614 Currently, each GCC i386 target always uses the same register
5615 numbering scheme across all its supported debugging formats
5616 i.e. SDB (COFF), stabs and DWARF 2. This is because
5617 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
5618 DBX_REGISTER_NUMBER macro which is defined by each target's
5619 respective config header in a manner independent of the requested
5620 output debugging format.
5622 This does not match the arrangement below, which presumes that
5623 the SDB and stabs numbering schemes differ from the DWARF and
5624 DWARF 2 ones. The reason for this arrangement is that it is
5625 likely to get the numbering scheme for the target's
5626 default/native debug format right. For targets where GCC is the
5627 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
5628 targets where the native toolchain uses a different numbering
5629 scheme for a particular debug format (stabs-in-ELF on Solaris)
5630 the defaults below will have to be overridden, like
5631 i386_elf_init_abi() does. */
5633 /* Use the dbx register numbering scheme for stabs and COFF. */
5634 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
5635 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
5637 /* Use the SVR4 register numbering scheme for DWARF 2. */
5638 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
5640 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
5641 be in use on any of the supported i386 targets. */
5643 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
5645 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
5647 /* Call dummy code. */
5648 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
5650 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
5651 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
5652 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
5654 set_gdbarch_return_value (gdbarch, i386_return_value);
5656 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
5658 /* Stack grows downward. */
5659 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
5661 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc);
5662 set_gdbarch_decr_pc_after_break (gdbarch, 1);
5663 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
5665 set_gdbarch_frame_args_skip (gdbarch, 8);
5667 set_gdbarch_print_insn (gdbarch, i386_print_insn);
5669 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
5671 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
5673 /* Add the i386 register groups. */
5674 i386_add_reggroups (gdbarch);
5675 tdep->register_reggroup_p = i386_register_reggroup_p;
5677 /* Helper for function argument information. */
5678 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
5680 /* Hook the function epilogue frame unwinder. This unwinder is
5681 appended to the list first, so that it supercedes the Dwarf
5682 unwinder in function epilogues (where the Dwarf unwinder
5683 currently fails). */
5684 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
5686 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
5687 to the list before the prologue-based unwinders, so that Dwarf
5688 CFI info will be used if it is available. */
5689 dwarf2_append_unwinders (gdbarch);
5691 frame_base_set_default (gdbarch, &i386_frame_base);
5693 /* Wire in the MMX registers. */
5694 set_gdbarch_num_pseudo_regs (gdbarch, i386_num_mmx_regs);
5695 set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read);
5696 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
5698 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
5699 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
5701 /* The default ABI includes general-purpose registers,
5702 floating-point registers, and the SSE registers. */
5703 set_gdbarch_num_regs (gdbarch, I386_SSE_NUM_REGS);
5705 /* Get the x86 target description from INFO. */
5706 tdesc = info.target_desc;
5707 if (! tdesc_has_registers (tdesc))
5709 tdep->tdesc = tdesc;
5711 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
5712 tdep->register_names = i386_register_names;
5714 tdesc_data = tdesc_data_alloc ();
5716 /* Hook in ABI-specific overrides, if they have been registered. */
5717 info.tdep_info = (void *) tdesc_data;
5718 gdbarch_init_osabi (info, gdbarch);
5720 /* Target description may be changed. */
5721 tdesc = tdep->tdesc;
5723 if (!i386_validate_tdesc_p (tdep, tdesc_data))
5725 tdesc_data_cleanup (tdesc_data);
5727 gdbarch_free (gdbarch);
5731 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
5733 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
5734 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
5736 /* Hook in the legacy prologue-based unwinders last (fallback). */
5737 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
5738 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
5740 /* If we have a register mapping, enable the generic core file
5741 support, unless it has already been enabled. */
5742 if (tdep->gregset_reg_offset
5743 && !gdbarch_regset_from_core_section_p (gdbarch))
5744 set_gdbarch_regset_from_core_section (gdbarch,
5745 i386_regset_from_core_section);
5747 /* Unless support for MMX has been disabled, make %mm0 the first
5749 if (tdep->mm0_regnum == 0)
5750 tdep->mm0_regnum = gdbarch_num_regs (gdbarch);
5752 set_gdbarch_skip_permanent_breakpoint (gdbarch,
5753 i386_skip_permanent_breakpoint);
5755 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
5756 i386_fast_tracepoint_valid_at);
5761 static enum gdb_osabi
5762 i386_coff_osabi_sniffer (bfd *abfd)
5764 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
5765 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
5766 return GDB_OSABI_GO32;
5768 return GDB_OSABI_UNKNOWN;
5772 /* Provide a prototype to silence -Wmissing-prototypes. */
5773 void _initialize_i386_tdep (void);
5776 _initialize_i386_tdep (void)
5778 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
5780 /* Add the variable that controls the disassembly flavor. */
5781 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
5782 &disassembly_flavor, _("\
5783 Set the disassembly flavor."), _("\
5784 Show the disassembly flavor."), _("\
5785 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
5787 NULL, /* FIXME: i18n: */
5788 &setlist, &showlist);
5790 /* Add the variable that controls the convention for returning
5792 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
5793 &struct_convention, _("\
5794 Set the convention for returning small structs."), _("\
5795 Show the convention for returning small structs."), _("\
5796 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
5799 NULL, /* FIXME: i18n: */
5800 &setlist, &showlist);
5802 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
5803 i386_coff_osabi_sniffer);
5805 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
5806 i386_svr4_init_abi);
5807 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
5808 i386_go32_init_abi);
5810 /* Initialize the i386-specific register groups. */
5811 i386_init_reggroups ();
5813 /* Initialize the standard target descriptions. */
5814 initialize_tdesc_i386 ();