1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2015 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
38 #include "reggroups.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "x86-xstate.h"
52 #include "record-full.h"
53 #include "features/i386/i386.c"
54 #include "features/i386/i386-avx.c"
55 #include "features/i386/i386-mpx.c"
56 #include "features/i386/i386-avx512.c"
57 #include "features/i386/i386-mmx.c"
62 #include "stap-probe.h"
63 #include "user-regs.h"
64 #include "cli/cli-utils.h"
65 #include "expression.h"
66 #include "parser-defs.h"
71 static const char *i386_register_names[] =
73 "eax", "ecx", "edx", "ebx",
74 "esp", "ebp", "esi", "edi",
75 "eip", "eflags", "cs", "ss",
76 "ds", "es", "fs", "gs",
77 "st0", "st1", "st2", "st3",
78 "st4", "st5", "st6", "st7",
79 "fctrl", "fstat", "ftag", "fiseg",
80 "fioff", "foseg", "fooff", "fop",
81 "xmm0", "xmm1", "xmm2", "xmm3",
82 "xmm4", "xmm5", "xmm6", "xmm7",
86 static const char *i386_zmm_names[] =
88 "zmm0", "zmm1", "zmm2", "zmm3",
89 "zmm4", "zmm5", "zmm6", "zmm7"
92 static const char *i386_zmmh_names[] =
94 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
95 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
98 static const char *i386_k_names[] =
100 "k0", "k1", "k2", "k3",
101 "k4", "k5", "k6", "k7"
104 static const char *i386_ymm_names[] =
106 "ymm0", "ymm1", "ymm2", "ymm3",
107 "ymm4", "ymm5", "ymm6", "ymm7",
110 static const char *i386_ymmh_names[] =
112 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
113 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
116 static const char *i386_mpx_names[] =
118 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
121 /* Register names for MPX pseudo-registers. */
123 static const char *i386_bnd_names[] =
125 "bnd0", "bnd1", "bnd2", "bnd3"
128 /* Register names for MMX pseudo-registers. */
130 static const char *i386_mmx_names[] =
132 "mm0", "mm1", "mm2", "mm3",
133 "mm4", "mm5", "mm6", "mm7"
136 /* Register names for byte pseudo-registers. */
138 static const char *i386_byte_names[] =
140 "al", "cl", "dl", "bl",
141 "ah", "ch", "dh", "bh"
144 /* Register names for word pseudo-registers. */
146 static const char *i386_word_names[] =
148 "ax", "cx", "dx", "bx",
152 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
153 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
154 we have 16 upper ZMM regs that have to be handled differently. */
156 const int num_lower_zmm_regs = 16;
161 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
163 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
164 int mm0_regnum = tdep->mm0_regnum;
169 regnum -= mm0_regnum;
170 return regnum >= 0 && regnum < tdep->num_mmx_regs;
176 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
178 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
180 regnum -= tdep->al_regnum;
181 return regnum >= 0 && regnum < tdep->num_byte_regs;
187 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
189 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
191 regnum -= tdep->ax_regnum;
192 return regnum >= 0 && regnum < tdep->num_word_regs;
195 /* Dword register? */
198 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
200 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
201 int eax_regnum = tdep->eax_regnum;
206 regnum -= eax_regnum;
207 return regnum >= 0 && regnum < tdep->num_dword_regs;
210 /* AVX512 register? */
213 i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum)
215 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
216 int zmm0h_regnum = tdep->zmm0h_regnum;
218 if (zmm0h_regnum < 0)
221 regnum -= zmm0h_regnum;
222 return regnum >= 0 && regnum < tdep->num_zmm_regs;
226 i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum)
228 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
229 int zmm0_regnum = tdep->zmm0_regnum;
234 regnum -= zmm0_regnum;
235 return regnum >= 0 && regnum < tdep->num_zmm_regs;
239 i386_k_regnum_p (struct gdbarch *gdbarch, int regnum)
241 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
242 int k0_regnum = tdep->k0_regnum;
248 return regnum >= 0 && regnum < I387_NUM_K_REGS;
252 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
254 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
255 int ymm0h_regnum = tdep->ymm0h_regnum;
257 if (ymm0h_regnum < 0)
260 regnum -= ymm0h_regnum;
261 return regnum >= 0 && regnum < tdep->num_ymm_regs;
267 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
269 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
270 int ymm0_regnum = tdep->ymm0_regnum;
275 regnum -= ymm0_regnum;
276 return regnum >= 0 && regnum < tdep->num_ymm_regs;
280 i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
282 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
283 int ymm16h_regnum = tdep->ymm16h_regnum;
285 if (ymm16h_regnum < 0)
288 regnum -= ymm16h_regnum;
289 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
293 i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
295 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
296 int ymm16_regnum = tdep->ymm16_regnum;
298 if (ymm16_regnum < 0)
301 regnum -= ymm16_regnum;
302 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
308 i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum)
310 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
311 int bnd0_regnum = tdep->bnd0_regnum;
316 regnum -= bnd0_regnum;
317 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
323 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
325 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
326 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
328 if (num_xmm_regs == 0)
331 regnum -= I387_XMM0_REGNUM (tdep);
332 return regnum >= 0 && regnum < num_xmm_regs;
335 /* XMM_512 register? */
338 i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
340 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
341 int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep);
343 if (num_xmm_avx512_regs == 0)
346 regnum -= I387_XMM16_REGNUM (tdep);
347 return regnum >= 0 && regnum < num_xmm_avx512_regs;
351 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
353 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
355 if (I387_NUM_XMM_REGS (tdep) == 0)
358 return (regnum == I387_MXCSR_REGNUM (tdep));
364 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
366 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
368 if (I387_ST0_REGNUM (tdep) < 0)
371 return (I387_ST0_REGNUM (tdep) <= regnum
372 && regnum < I387_FCTRL_REGNUM (tdep));
376 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
378 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
380 if (I387_ST0_REGNUM (tdep) < 0)
383 return (I387_FCTRL_REGNUM (tdep) <= regnum
384 && regnum < I387_XMM0_REGNUM (tdep));
387 /* BNDr (raw) register? */
390 i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum)
392 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
394 if (I387_BND0R_REGNUM (tdep) < 0)
397 regnum -= tdep->bnd0r_regnum;
398 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
401 /* BND control register? */
404 i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum)
406 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
408 if (I387_BNDCFGU_REGNUM (tdep) < 0)
411 regnum -= I387_BNDCFGU_REGNUM (tdep);
412 return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS;
415 /* Return the name of register REGNUM, or the empty string if it is
416 an anonymous register. */
419 i386_register_name (struct gdbarch *gdbarch, int regnum)
421 /* Hide the upper YMM registers. */
422 if (i386_ymmh_regnum_p (gdbarch, regnum))
425 /* Hide the upper YMM16-31 registers. */
426 if (i386_ymmh_avx512_regnum_p (gdbarch, regnum))
429 /* Hide the upper ZMM registers. */
430 if (i386_zmmh_regnum_p (gdbarch, regnum))
433 return tdesc_register_name (gdbarch, regnum);
436 /* Return the name of register REGNUM. */
439 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
441 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
442 if (i386_bnd_regnum_p (gdbarch, regnum))
443 return i386_bnd_names[regnum - tdep->bnd0_regnum];
444 if (i386_mmx_regnum_p (gdbarch, regnum))
445 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
446 else if (i386_ymm_regnum_p (gdbarch, regnum))
447 return i386_ymm_names[regnum - tdep->ymm0_regnum];
448 else if (i386_zmm_regnum_p (gdbarch, regnum))
449 return i386_zmm_names[regnum - tdep->zmm0_regnum];
450 else if (i386_byte_regnum_p (gdbarch, regnum))
451 return i386_byte_names[regnum - tdep->al_regnum];
452 else if (i386_word_regnum_p (gdbarch, regnum))
453 return i386_word_names[regnum - tdep->ax_regnum];
455 internal_error (__FILE__, __LINE__, _("invalid regnum"));
458 /* Convert a dbx register number REG to the appropriate register
459 number used by GDB. */
462 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
464 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
466 /* This implements what GCC calls the "default" register map
467 (dbx_register_map[]). */
469 if (reg >= 0 && reg <= 7)
471 /* General-purpose registers. The debug info calls %ebp
472 register 4, and %esp register 5. */
479 else if (reg >= 12 && reg <= 19)
481 /* Floating-point registers. */
482 return reg - 12 + I387_ST0_REGNUM (tdep);
484 else if (reg >= 21 && reg <= 28)
487 int ymm0_regnum = tdep->ymm0_regnum;
490 && i386_xmm_regnum_p (gdbarch, reg))
491 return reg - 21 + ymm0_regnum;
493 return reg - 21 + I387_XMM0_REGNUM (tdep);
495 else if (reg >= 29 && reg <= 36)
498 return reg - 29 + I387_MM0_REGNUM (tdep);
501 /* This will hopefully provoke a warning. */
502 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
505 /* Convert SVR4 register number REG to the appropriate register number
509 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
511 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
513 /* This implements the GCC register map that tries to be compatible
514 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
516 /* The SVR4 register numbering includes %eip and %eflags, and
517 numbers the floating point registers differently. */
518 if (reg >= 0 && reg <= 9)
520 /* General-purpose registers. */
523 else if (reg >= 11 && reg <= 18)
525 /* Floating-point registers. */
526 return reg - 11 + I387_ST0_REGNUM (tdep);
528 else if (reg >= 21 && reg <= 36)
530 /* The SSE and MMX registers have the same numbers as with dbx. */
531 return i386_dbx_reg_to_regnum (gdbarch, reg);
536 case 37: return I387_FCTRL_REGNUM (tdep);
537 case 38: return I387_FSTAT_REGNUM (tdep);
538 case 39: return I387_MXCSR_REGNUM (tdep);
539 case 40: return I386_ES_REGNUM;
540 case 41: return I386_CS_REGNUM;
541 case 42: return I386_SS_REGNUM;
542 case 43: return I386_DS_REGNUM;
543 case 44: return I386_FS_REGNUM;
544 case 45: return I386_GS_REGNUM;
547 /* This will hopefully provoke a warning. */
548 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
553 /* This is the variable that is set with "set disassembly-flavor", and
554 its legitimate values. */
555 static const char att_flavor[] = "att";
556 static const char intel_flavor[] = "intel";
557 static const char *const valid_flavors[] =
563 static const char *disassembly_flavor = att_flavor;
566 /* Use the program counter to determine the contents and size of a
567 breakpoint instruction. Return a pointer to a string of bytes that
568 encode a breakpoint instruction, store the length of the string in
569 *LEN and optionally adjust *PC to point to the correct memory
570 location for inserting the breakpoint.
572 On the i386 we have a single breakpoint that fits in a single byte
573 and can be inserted anywhere.
575 This function is 64-bit safe. */
577 static const gdb_byte *
578 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
580 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */
582 *len = sizeof (break_insn);
586 /* Displaced instruction handling. */
588 /* Skip the legacy instruction prefixes in INSN.
589 Not all prefixes are valid for any particular insn
590 but we needn't care, the insn will fault if it's invalid.
591 The result is a pointer to the first opcode byte,
592 or NULL if we run off the end of the buffer. */
595 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
597 gdb_byte *end = insn + max_len;
603 case DATA_PREFIX_OPCODE:
604 case ADDR_PREFIX_OPCODE:
605 case CS_PREFIX_OPCODE:
606 case DS_PREFIX_OPCODE:
607 case ES_PREFIX_OPCODE:
608 case FS_PREFIX_OPCODE:
609 case GS_PREFIX_OPCODE:
610 case SS_PREFIX_OPCODE:
611 case LOCK_PREFIX_OPCODE:
612 case REPE_PREFIX_OPCODE:
613 case REPNE_PREFIX_OPCODE:
625 i386_absolute_jmp_p (const gdb_byte *insn)
627 /* jmp far (absolute address in operand). */
633 /* jump near, absolute indirect (/4). */
634 if ((insn[1] & 0x38) == 0x20)
637 /* jump far, absolute indirect (/5). */
638 if ((insn[1] & 0x38) == 0x28)
645 /* Return non-zero if INSN is a jump, zero otherwise. */
648 i386_jmp_p (const gdb_byte *insn)
650 /* jump short, relative. */
654 /* jump near, relative. */
658 return i386_absolute_jmp_p (insn);
662 i386_absolute_call_p (const gdb_byte *insn)
664 /* call far, absolute. */
670 /* Call near, absolute indirect (/2). */
671 if ((insn[1] & 0x38) == 0x10)
674 /* Call far, absolute indirect (/3). */
675 if ((insn[1] & 0x38) == 0x18)
683 i386_ret_p (const gdb_byte *insn)
687 case 0xc2: /* ret near, pop N bytes. */
688 case 0xc3: /* ret near */
689 case 0xca: /* ret far, pop N bytes. */
690 case 0xcb: /* ret far */
691 case 0xcf: /* iret */
700 i386_call_p (const gdb_byte *insn)
702 if (i386_absolute_call_p (insn))
705 /* call near, relative. */
712 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
713 length in bytes. Otherwise, return zero. */
716 i386_syscall_p (const gdb_byte *insn, int *lengthp)
718 /* Is it 'int $0x80'? */
719 if ((insn[0] == 0xcd && insn[1] == 0x80)
720 /* Or is it 'sysenter'? */
721 || (insn[0] == 0x0f && insn[1] == 0x34)
722 /* Or is it 'syscall'? */
723 || (insn[0] == 0x0f && insn[1] == 0x05))
732 /* The gdbarch insn_is_call method. */
735 i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
737 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
739 read_code (addr, buf, I386_MAX_INSN_LEN);
740 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
742 return i386_call_p (insn);
745 /* The gdbarch insn_is_ret method. */
748 i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
750 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
752 read_code (addr, buf, I386_MAX_INSN_LEN);
753 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
755 return i386_ret_p (insn);
758 /* The gdbarch insn_is_jump method. */
761 i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
763 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
765 read_code (addr, buf, I386_MAX_INSN_LEN);
766 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
768 return i386_jmp_p (insn);
771 /* Some kernels may run one past a syscall insn, so we have to cope.
772 Otherwise this is just simple_displaced_step_copy_insn. */
774 struct displaced_step_closure *
775 i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
776 CORE_ADDR from, CORE_ADDR to,
777 struct regcache *regs)
779 size_t len = gdbarch_max_insn_length (gdbarch);
780 gdb_byte *buf = xmalloc (len);
782 read_memory (from, buf, len);
784 /* GDB may get control back after the insn after the syscall.
785 Presumably this is a kernel bug.
786 If this is a syscall, make sure there's a nop afterwards. */
791 insn = i386_skip_prefixes (buf, len);
792 if (insn != NULL && i386_syscall_p (insn, &syscall_length))
793 insn[syscall_length] = NOP_OPCODE;
796 write_memory (to, buf, len);
800 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
801 paddress (gdbarch, from), paddress (gdbarch, to));
802 displaced_step_dump_bytes (gdb_stdlog, buf, len);
805 return (struct displaced_step_closure *) buf;
808 /* Fix up the state of registers and memory after having single-stepped
809 a displaced instruction. */
812 i386_displaced_step_fixup (struct gdbarch *gdbarch,
813 struct displaced_step_closure *closure,
814 CORE_ADDR from, CORE_ADDR to,
815 struct regcache *regs)
817 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
819 /* The offset we applied to the instruction's address.
820 This could well be negative (when viewed as a signed 32-bit
821 value), but ULONGEST won't reflect that, so take care when
823 ULONGEST insn_offset = to - from;
825 /* Since we use simple_displaced_step_copy_insn, our closure is a
826 copy of the instruction. */
827 gdb_byte *insn = (gdb_byte *) closure;
828 /* The start of the insn, needed in case we see some prefixes. */
829 gdb_byte *insn_start = insn;
832 fprintf_unfiltered (gdb_stdlog,
833 "displaced: fixup (%s, %s), "
834 "insn = 0x%02x 0x%02x ...\n",
835 paddress (gdbarch, from), paddress (gdbarch, to),
838 /* The list of issues to contend with here is taken from
839 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
840 Yay for Free Software! */
842 /* Relocate the %eip, if necessary. */
844 /* The instruction recognizers we use assume any leading prefixes
845 have been skipped. */
847 /* This is the size of the buffer in closure. */
848 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
849 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
850 /* If there are too many prefixes, just ignore the insn.
851 It will fault when run. */
856 /* Except in the case of absolute or indirect jump or call
857 instructions, or a return instruction, the new eip is relative to
858 the displaced instruction; make it relative. Well, signal
859 handler returns don't need relocation either, but we use the
860 value of %eip to recognize those; see below. */
861 if (! i386_absolute_jmp_p (insn)
862 && ! i386_absolute_call_p (insn)
863 && ! i386_ret_p (insn))
868 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
870 /* A signal trampoline system call changes the %eip, resuming
871 execution of the main program after the signal handler has
872 returned. That makes them like 'return' instructions; we
873 shouldn't relocate %eip.
875 But most system calls don't, and we do need to relocate %eip.
877 Our heuristic for distinguishing these cases: if stepping
878 over the system call instruction left control directly after
879 the instruction, the we relocate --- control almost certainly
880 doesn't belong in the displaced copy. Otherwise, we assume
881 the instruction has put control where it belongs, and leave
882 it unrelocated. Goodness help us if there are PC-relative
884 if (i386_syscall_p (insn, &insn_len)
885 && orig_eip != to + (insn - insn_start) + insn_len
886 /* GDB can get control back after the insn after the syscall.
887 Presumably this is a kernel bug.
888 i386_displaced_step_copy_insn ensures its a nop,
889 we add one to the length for it. */
890 && orig_eip != to + (insn - insn_start) + insn_len + 1)
893 fprintf_unfiltered (gdb_stdlog,
894 "displaced: syscall changed %%eip; "
899 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
901 /* If we just stepped over a breakpoint insn, we don't backup
902 the pc on purpose; this is to match behaviour without
905 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
908 fprintf_unfiltered (gdb_stdlog,
910 "relocated %%eip from %s to %s\n",
911 paddress (gdbarch, orig_eip),
912 paddress (gdbarch, eip));
916 /* If the instruction was PUSHFL, then the TF bit will be set in the
917 pushed value, and should be cleared. We'll leave this for later,
918 since GDB already messes up the TF flag when stepping over a
921 /* If the instruction was a call, the return address now atop the
922 stack is the address following the copied instruction. We need
923 to make it the address following the original instruction. */
924 if (i386_call_p (insn))
928 const ULONGEST retaddr_len = 4;
930 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
931 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
932 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
933 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
936 fprintf_unfiltered (gdb_stdlog,
937 "displaced: relocated return addr at %s to %s\n",
938 paddress (gdbarch, esp),
939 paddress (gdbarch, retaddr));
944 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
946 target_write_memory (*to, buf, len);
951 i386_relocate_instruction (struct gdbarch *gdbarch,
952 CORE_ADDR *to, CORE_ADDR oldloc)
954 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
955 gdb_byte buf[I386_MAX_INSN_LEN];
956 int offset = 0, rel32, newrel;
958 gdb_byte *insn = buf;
960 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
962 insn_length = gdb_buffered_insn_length (gdbarch, insn,
963 I386_MAX_INSN_LEN, oldloc);
965 /* Get past the prefixes. */
966 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
968 /* Adjust calls with 32-bit relative addresses as push/jump, with
969 the address pushed being the location where the original call in
970 the user program would return to. */
973 gdb_byte push_buf[16];
974 unsigned int ret_addr;
976 /* Where "ret" in the original code will return to. */
977 ret_addr = oldloc + insn_length;
978 push_buf[0] = 0x68; /* pushq $... */
979 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
981 append_insns (to, 5, push_buf);
983 /* Convert the relative call to a relative jump. */
986 /* Adjust the destination offset. */
987 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
988 newrel = (oldloc - *to) + rel32;
989 store_signed_integer (insn + 1, 4, byte_order, newrel);
992 fprintf_unfiltered (gdb_stdlog,
993 "Adjusted insn rel32=%s at %s to"
995 hex_string (rel32), paddress (gdbarch, oldloc),
996 hex_string (newrel), paddress (gdbarch, *to));
998 /* Write the adjusted jump into its displaced location. */
999 append_insns (to, 5, insn);
1003 /* Adjust jumps with 32-bit relative addresses. Calls are already
1005 if (insn[0] == 0xe9)
1007 /* Adjust conditional jumps. */
1008 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1013 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1014 newrel = (oldloc - *to) + rel32;
1015 store_signed_integer (insn + offset, 4, byte_order, newrel);
1016 if (debug_displaced)
1017 fprintf_unfiltered (gdb_stdlog,
1018 "Adjusted insn rel32=%s at %s to"
1019 " rel32=%s at %s\n",
1020 hex_string (rel32), paddress (gdbarch, oldloc),
1021 hex_string (newrel), paddress (gdbarch, *to));
1024 /* Write the adjusted instructions into their displaced
1026 append_insns (to, insn_length, buf);
1030 #ifdef I386_REGNO_TO_SYMMETRY
1031 #error "The Sequent Symmetry is no longer supported."
1034 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1035 and %esp "belong" to the calling function. Therefore these
1036 registers should be saved if they're going to be modified. */
1038 /* The maximum number of saved registers. This should include all
1039 registers mentioned above, and %eip. */
1040 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1042 struct i386_frame_cache
1050 /* Saved registers. */
1051 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
1056 /* Stack space reserved for local variables. */
1060 /* Allocate and initialize a frame cache. */
1062 static struct i386_frame_cache *
1063 i386_alloc_frame_cache (void)
1065 struct i386_frame_cache *cache;
1068 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
1073 cache->sp_offset = -4;
1076 /* Saved registers. We initialize these to -1 since zero is a valid
1077 offset (that's where %ebp is supposed to be stored). */
1078 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1079 cache->saved_regs[i] = -1;
1080 cache->saved_sp = 0;
1081 cache->saved_sp_reg = -1;
1082 cache->pc_in_eax = 0;
1084 /* Frameless until proven otherwise. */
1090 /* If the instruction at PC is a jump, return the address of its
1091 target. Otherwise, return PC. */
1094 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
1096 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1101 if (target_read_code (pc, &op, 1))
1108 op = read_code_unsigned_integer (pc + 1, 1, byte_order);
1114 /* Relative jump: if data16 == 0, disp32, else disp16. */
1117 delta = read_memory_integer (pc + 2, 2, byte_order);
1119 /* Include the size of the jmp instruction (including the
1125 delta = read_memory_integer (pc + 1, 4, byte_order);
1127 /* Include the size of the jmp instruction. */
1132 /* Relative jump, disp8 (ignore data16). */
1133 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
1135 delta += data16 + 2;
1142 /* Check whether PC points at a prologue for a function returning a
1143 structure or union. If so, it updates CACHE and returns the
1144 address of the first instruction after the code sequence that
1145 removes the "hidden" argument from the stack or CURRENT_PC,
1146 whichever is smaller. Otherwise, return PC. */
1149 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
1150 struct i386_frame_cache *cache)
1152 /* Functions that return a structure or union start with:
1155 xchgl %eax, (%esp) 0x87 0x04 0x24
1156 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1158 (the System V compiler puts out the second `xchg' instruction,
1159 and the assembler doesn't try to optimize it, so the 'sib' form
1160 gets generated). This sequence is used to get the address of the
1161 return buffer for a function that returns a structure. */
1162 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
1163 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
1167 if (current_pc <= pc)
1170 if (target_read_code (pc, &op, 1))
1173 if (op != 0x58) /* popl %eax */
1176 if (target_read_code (pc + 1, buf, 4))
1179 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
1182 if (current_pc == pc)
1184 cache->sp_offset += 4;
1188 if (current_pc == pc + 1)
1190 cache->pc_in_eax = 1;
1194 if (buf[1] == proto1[1])
1201 i386_skip_probe (CORE_ADDR pc)
1203 /* A function may start with
1217 if (target_read_code (pc, &op, 1))
1220 if (op == 0x68 || op == 0x6a)
1224 /* Skip past the `pushl' instruction; it has either a one-byte or a
1225 four-byte operand, depending on the opcode. */
1231 /* Read the following 8 bytes, which should be `call _probe' (6
1232 bytes) followed by `addl $4,%esp' (2 bytes). */
1233 read_memory (pc + delta, buf, sizeof (buf));
1234 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
1235 pc += delta + sizeof (buf);
1241 /* GCC 4.1 and later, can put code in the prologue to realign the
1242 stack pointer. Check whether PC points to such code, and update
1243 CACHE accordingly. Return the first instruction after the code
1244 sequence or CURRENT_PC, whichever is smaller. If we don't
1245 recognize the code, return PC. */
1248 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1249 struct i386_frame_cache *cache)
1251 /* There are 2 code sequences to re-align stack before the frame
1254 1. Use a caller-saved saved register:
1260 2. Use a callee-saved saved register:
1267 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1269 0x83 0xe4 0xf0 andl $-16, %esp
1270 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1275 int offset, offset_and;
1276 static int regnums[8] = {
1277 I386_EAX_REGNUM, /* %eax */
1278 I386_ECX_REGNUM, /* %ecx */
1279 I386_EDX_REGNUM, /* %edx */
1280 I386_EBX_REGNUM, /* %ebx */
1281 I386_ESP_REGNUM, /* %esp */
1282 I386_EBP_REGNUM, /* %ebp */
1283 I386_ESI_REGNUM, /* %esi */
1284 I386_EDI_REGNUM /* %edi */
1287 if (target_read_code (pc, buf, sizeof buf))
1290 /* Check caller-saved saved register. The first instruction has
1291 to be "leal 4(%esp), %reg". */
1292 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1294 /* MOD must be binary 10 and R/M must be binary 100. */
1295 if ((buf[1] & 0xc7) != 0x44)
1298 /* REG has register number. */
1299 reg = (buf[1] >> 3) & 7;
1304 /* Check callee-saved saved register. The first instruction
1305 has to be "pushl %reg". */
1306 if ((buf[0] & 0xf8) != 0x50)
1312 /* The next instruction has to be "leal 8(%esp), %reg". */
1313 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1316 /* MOD must be binary 10 and R/M must be binary 100. */
1317 if ((buf[2] & 0xc7) != 0x44)
1320 /* REG has register number. Registers in pushl and leal have to
1322 if (reg != ((buf[2] >> 3) & 7))
1328 /* Rigister can't be %esp nor %ebp. */
1329 if (reg == 4 || reg == 5)
1332 /* The next instruction has to be "andl $-XXX, %esp". */
1333 if (buf[offset + 1] != 0xe4
1334 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1337 offset_and = offset;
1338 offset += buf[offset] == 0x81 ? 6 : 3;
1340 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1341 0xfc. REG must be binary 110 and MOD must be binary 01. */
1342 if (buf[offset] != 0xff
1343 || buf[offset + 2] != 0xfc
1344 || (buf[offset + 1] & 0xf8) != 0x70)
1347 /* R/M has register. Registers in leal and pushl have to be the
1349 if (reg != (buf[offset + 1] & 7))
1352 if (current_pc > pc + offset_and)
1353 cache->saved_sp_reg = regnums[reg];
1355 return min (pc + offset + 3, current_pc);
1358 /* Maximum instruction length we need to handle. */
1359 #define I386_MAX_MATCHED_INSN_LEN 6
1361 /* Instruction description. */
1365 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
1366 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
1369 /* Return whether instruction at PC matches PATTERN. */
1372 i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern)
1376 if (target_read_code (pc, &op, 1))
1379 if ((op & pattern.mask[0]) == pattern.insn[0])
1381 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1382 int insn_matched = 1;
1385 gdb_assert (pattern.len > 1);
1386 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN);
1388 if (target_read_code (pc + 1, buf, pattern.len - 1))
1391 for (i = 1; i < pattern.len; i++)
1393 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i])
1396 return insn_matched;
1401 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1402 the first instruction description that matches. Otherwise, return
1405 static struct i386_insn *
1406 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns)
1408 struct i386_insn *pattern;
1410 for (pattern = insn_patterns; pattern->len > 0; pattern++)
1412 if (i386_match_pattern (pc, *pattern))
1419 /* Return whether PC points inside a sequence of instructions that
1420 matches INSN_PATTERNS. */
1423 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns)
1425 CORE_ADDR current_pc;
1427 struct i386_insn *insn;
1429 insn = i386_match_insn (pc, insn_patterns);
1434 ix = insn - insn_patterns;
1435 for (i = ix - 1; i >= 0; i--)
1437 current_pc -= insn_patterns[i].len;
1439 if (!i386_match_pattern (current_pc, insn_patterns[i]))
1443 current_pc = pc + insn->len;
1444 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++)
1446 if (!i386_match_pattern (current_pc, *insn))
1449 current_pc += insn->len;
1455 /* Some special instructions that might be migrated by GCC into the
1456 part of the prologue that sets up the new stack frame. Because the
1457 stack frame hasn't been setup yet, no registers have been saved
1458 yet, and only the scratch registers %eax, %ecx and %edx can be
1461 struct i386_insn i386_frame_setup_skip_insns[] =
1463 /* Check for `movb imm8, r' and `movl imm32, r'.
1465 ??? Should we handle 16-bit operand-sizes here? */
1467 /* `movb imm8, %al' and `movb imm8, %ah' */
1468 /* `movb imm8, %cl' and `movb imm8, %ch' */
1469 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1470 /* `movb imm8, %dl' and `movb imm8, %dh' */
1471 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1472 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1473 { 5, { 0xb8 }, { 0xfe } },
1474 /* `movl imm32, %edx' */
1475 { 5, { 0xba }, { 0xff } },
1477 /* Check for `mov imm32, r32'. Note that there is an alternative
1478 encoding for `mov m32, %eax'.
1480 ??? Should we handle SIB adressing here?
1481 ??? Should we handle 16-bit operand-sizes here? */
1483 /* `movl m32, %eax' */
1484 { 5, { 0xa1 }, { 0xff } },
1485 /* `movl m32, %eax' and `mov; m32, %ecx' */
1486 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1487 /* `movl m32, %edx' */
1488 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1490 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1491 Because of the symmetry, there are actually two ways to encode
1492 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1493 opcode bytes 0x31 and 0x33 for `xorl'. */
1495 /* `subl %eax, %eax' */
1496 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1497 /* `subl %ecx, %ecx' */
1498 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1499 /* `subl %edx, %edx' */
1500 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1501 /* `xorl %eax, %eax' */
1502 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1503 /* `xorl %ecx, %ecx' */
1504 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1505 /* `xorl %edx, %edx' */
1506 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1511 /* Check whether PC points to a no-op instruction. */
1513 i386_skip_noop (CORE_ADDR pc)
1518 if (target_read_code (pc, &op, 1))
1524 /* Ignore `nop' instruction. */
1528 if (target_read_code (pc, &op, 1))
1532 /* Ignore no-op instruction `mov %edi, %edi'.
1533 Microsoft system dlls often start with
1534 a `mov %edi,%edi' instruction.
1535 The 5 bytes before the function start are
1536 filled with `nop' instructions.
1537 This pattern can be used for hot-patching:
1538 The `mov %edi, %edi' instruction can be replaced by a
1539 near jump to the location of the 5 `nop' instructions
1540 which can be replaced by a 32-bit jump to anywhere
1541 in the 32-bit address space. */
1543 else if (op == 0x8b)
1545 if (target_read_code (pc + 1, &op, 1))
1551 if (target_read_code (pc, &op, 1))
1561 /* Check whether PC points at a code that sets up a new stack frame.
1562 If so, it updates CACHE and returns the address of the first
1563 instruction after the sequence that sets up the frame or LIMIT,
1564 whichever is smaller. If we don't recognize the code, return PC. */
1567 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1568 CORE_ADDR pc, CORE_ADDR limit,
1569 struct i386_frame_cache *cache)
1571 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1572 struct i386_insn *insn;
1579 if (target_read_code (pc, &op, 1))
1582 if (op == 0x55) /* pushl %ebp */
1584 /* Take into account that we've executed the `pushl %ebp' that
1585 starts this instruction sequence. */
1586 cache->saved_regs[I386_EBP_REGNUM] = 0;
1587 cache->sp_offset += 4;
1590 /* If that's all, return now. */
1594 /* Check for some special instructions that might be migrated by
1595 GCC into the prologue and skip them. At this point in the
1596 prologue, code should only touch the scratch registers %eax,
1597 %ecx and %edx, so while the number of posibilities is sheer,
1600 Make sure we only skip these instructions if we later see the
1601 `movl %esp, %ebp' that actually sets up the frame. */
1602 while (pc + skip < limit)
1604 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1611 /* If that's all, return now. */
1612 if (limit <= pc + skip)
1615 if (target_read_code (pc + skip, &op, 1))
1618 /* The i386 prologue looks like
1624 and a different prologue can be generated for atom.
1628 lea -0x10(%esp),%esp
1630 We handle both of them here. */
1634 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1636 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1642 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1647 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1648 if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order)
1657 /* OK, we actually have a frame. We just don't know how large
1658 it is yet. Set its size to zero. We'll adjust it if
1659 necessary. We also now commit to skipping the special
1660 instructions mentioned before. */
1663 /* If that's all, return now. */
1667 /* Check for stack adjustment
1673 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1674 reg, so we don't have to worry about a data16 prefix. */
1675 if (target_read_code (pc, &op, 1))
1679 /* `subl' with 8-bit immediate. */
1680 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1681 /* Some instruction starting with 0x83 other than `subl'. */
1684 /* `subl' with signed 8-bit immediate (though it wouldn't
1685 make sense to be negative). */
1686 cache->locals = read_code_integer (pc + 2, 1, byte_order);
1689 else if (op == 0x81)
1691 /* Maybe it is `subl' with a 32-bit immediate. */
1692 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1693 /* Some instruction starting with 0x81 other than `subl'. */
1696 /* It is `subl' with a 32-bit immediate. */
1697 cache->locals = read_code_integer (pc + 2, 4, byte_order);
1700 else if (op == 0x8d)
1702 /* The ModR/M byte is 0x64. */
1703 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64)
1705 /* 'lea' with 8-bit displacement. */
1706 cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order);
1711 /* Some instruction other than `subl' nor 'lea'. */
1715 else if (op == 0xc8) /* enter */
1717 cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order);
1724 /* Check whether PC points at code that saves registers on the stack.
1725 If so, it updates CACHE and returns the address of the first
1726 instruction after the register saves or CURRENT_PC, whichever is
1727 smaller. Otherwise, return PC. */
1730 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1731 struct i386_frame_cache *cache)
1733 CORE_ADDR offset = 0;
1737 if (cache->locals > 0)
1738 offset -= cache->locals;
1739 for (i = 0; i < 8 && pc < current_pc; i++)
1741 if (target_read_code (pc, &op, 1))
1743 if (op < 0x50 || op > 0x57)
1747 cache->saved_regs[op - 0x50] = offset;
1748 cache->sp_offset += 4;
1755 /* Do a full analysis of the prologue at PC and update CACHE
1756 accordingly. Bail out early if CURRENT_PC is reached. Return the
1757 address where the analysis stopped.
1759 We handle these cases:
1761 The startup sequence can be at the start of the function, or the
1762 function can start with a branch to startup code at the end.
1764 %ebp can be set up with either the 'enter' instruction, or "pushl
1765 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1766 once used in the System V compiler).
1768 Local space is allocated just below the saved %ebp by either the
1769 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1770 16-bit unsigned argument for space to allocate, and the 'addl'
1771 instruction could have either a signed byte, or 32-bit immediate.
1773 Next, the registers used by this function are pushed. With the
1774 System V compiler they will always be in the order: %edi, %esi,
1775 %ebx (and sometimes a harmless bug causes it to also save but not
1776 restore %eax); however, the code below is willing to see the pushes
1777 in any order, and will handle up to 8 of them.
1779 If the setup sequence is at the end of the function, then the next
1780 instruction will be a branch back to the start. */
1783 i386_analyze_prologue (struct gdbarch *gdbarch,
1784 CORE_ADDR pc, CORE_ADDR current_pc,
1785 struct i386_frame_cache *cache)
1787 pc = i386_skip_noop (pc);
1788 pc = i386_follow_jump (gdbarch, pc);
1789 pc = i386_analyze_struct_return (pc, current_pc, cache);
1790 pc = i386_skip_probe (pc);
1791 pc = i386_analyze_stack_align (pc, current_pc, cache);
1792 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1793 return i386_analyze_register_saves (pc, current_pc, cache);
1796 /* Return PC of first real instruction. */
1799 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1801 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1803 static gdb_byte pic_pat[6] =
1805 0xe8, 0, 0, 0, 0, /* call 0x0 */
1806 0x5b, /* popl %ebx */
1808 struct i386_frame_cache cache;
1812 CORE_ADDR func_addr;
1814 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
1816 CORE_ADDR post_prologue_pc
1817 = skip_prologue_using_sal (gdbarch, func_addr);
1818 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
1820 /* Clang always emits a line note before the prologue and another
1821 one after. We trust clang to emit usable line notes. */
1822 if (post_prologue_pc
1824 && COMPUNIT_PRODUCER (cust) != NULL
1825 && startswith (COMPUNIT_PRODUCER (cust), "clang ")))
1826 return max (start_pc, post_prologue_pc);
1830 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1831 if (cache.locals < 0)
1834 /* Found valid frame setup. */
1836 /* The native cc on SVR4 in -K PIC mode inserts the following code
1837 to get the address of the global offset table (GOT) into register
1842 movl %ebx,x(%ebp) (optional)
1845 This code is with the rest of the prologue (at the end of the
1846 function), so we have to skip it to get to the first real
1847 instruction at the start of the function. */
1849 for (i = 0; i < 6; i++)
1851 if (target_read_code (pc + i, &op, 1))
1854 if (pic_pat[i] != op)
1861 if (target_read_code (pc + delta, &op, 1))
1864 if (op == 0x89) /* movl %ebx, x(%ebp) */
1866 op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order);
1868 if (op == 0x5d) /* One byte offset from %ebp. */
1870 else if (op == 0x9d) /* Four byte offset from %ebp. */
1872 else /* Unexpected instruction. */
1875 if (target_read_code (pc + delta, &op, 1))
1880 if (delta > 0 && op == 0x81
1881 && read_code_unsigned_integer (pc + delta + 1, 1, byte_order)
1888 /* If the function starts with a branch (to startup code at the end)
1889 the last instruction should bring us back to the first
1890 instruction of the real code. */
1891 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1892 pc = i386_follow_jump (gdbarch, pc);
1897 /* Check that the code pointed to by PC corresponds to a call to
1898 __main, skip it if so. Return PC otherwise. */
1901 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1903 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1906 if (target_read_code (pc, &op, 1))
1912 if (target_read_code (pc + 1, buf, sizeof buf) == 0)
1914 /* Make sure address is computed correctly as a 32bit
1915 integer even if CORE_ADDR is 64 bit wide. */
1916 struct bound_minimal_symbol s;
1917 CORE_ADDR call_dest;
1919 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1920 call_dest = call_dest & 0xffffffffU;
1921 s = lookup_minimal_symbol_by_pc (call_dest);
1922 if (s.minsym != NULL
1923 && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL
1924 && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0)
1932 /* This function is 64-bit safe. */
1935 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1939 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1940 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1944 /* Normal frames. */
1947 i386_frame_cache_1 (struct frame_info *this_frame,
1948 struct i386_frame_cache *cache)
1950 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1951 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1955 cache->pc = get_frame_func (this_frame);
1957 /* In principle, for normal frames, %ebp holds the frame pointer,
1958 which holds the base address for the current stack frame.
1959 However, for functions that don't need it, the frame pointer is
1960 optional. For these "frameless" functions the frame pointer is
1961 actually the frame pointer of the calling frame. Signal
1962 trampolines are just a special case of a "frameless" function.
1963 They (usually) share their frame pointer with the frame that was
1964 in progress when the signal occurred. */
1966 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1967 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1968 if (cache->base == 0)
1974 /* For normal frames, %eip is stored at 4(%ebp). */
1975 cache->saved_regs[I386_EIP_REGNUM] = 4;
1978 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
1981 if (cache->locals < 0)
1983 /* We didn't find a valid frame, which means that CACHE->base
1984 currently holds the frame pointer for our calling frame. If
1985 we're at the start of a function, or somewhere half-way its
1986 prologue, the function's frame probably hasn't been fully
1987 setup yet. Try to reconstruct the base address for the stack
1988 frame by looking at the stack pointer. For truly "frameless"
1989 functions this might work too. */
1991 if (cache->saved_sp_reg != -1)
1993 /* Saved stack pointer has been saved. */
1994 get_frame_register (this_frame, cache->saved_sp_reg, buf);
1995 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
1997 /* We're halfway aligning the stack. */
1998 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
1999 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
2001 /* This will be added back below. */
2002 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
2004 else if (cache->pc != 0
2005 || target_read_code (get_frame_pc (this_frame), buf, 1))
2007 /* We're in a known function, but did not find a frame
2008 setup. Assume that the function does not use %ebp.
2009 Alternatively, we may have jumped to an invalid
2010 address; in that case there is definitely no new
2012 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2013 cache->base = extract_unsigned_integer (buf, 4, byte_order)
2017 /* We're in an unknown function. We could not find the start
2018 of the function to analyze the prologue; our best option is
2019 to assume a typical frame layout with the caller's %ebp
2021 cache->saved_regs[I386_EBP_REGNUM] = 0;
2024 if (cache->saved_sp_reg != -1)
2026 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2027 register may be unavailable). */
2028 if (cache->saved_sp == 0
2029 && deprecated_frame_register_read (this_frame,
2030 cache->saved_sp_reg, buf))
2031 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2033 /* Now that we have the base address for the stack frame we can
2034 calculate the value of %esp in the calling frame. */
2035 else if (cache->saved_sp == 0)
2036 cache->saved_sp = cache->base + 8;
2038 /* Adjust all the saved registers such that they contain addresses
2039 instead of offsets. */
2040 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
2041 if (cache->saved_regs[i] != -1)
2042 cache->saved_regs[i] += cache->base;
2047 static struct i386_frame_cache *
2048 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
2050 struct i386_frame_cache *cache;
2055 cache = i386_alloc_frame_cache ();
2056 *this_cache = cache;
2060 i386_frame_cache_1 (this_frame, cache);
2062 CATCH (ex, RETURN_MASK_ERROR)
2064 if (ex.error != NOT_AVAILABLE_ERROR)
2065 throw_exception (ex);
2073 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
2074 struct frame_id *this_id)
2076 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2079 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2080 else if (cache->base == 0)
2082 /* This marks the outermost frame. */
2086 /* See the end of i386_push_dummy_call. */
2087 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2091 static enum unwind_stop_reason
2092 i386_frame_unwind_stop_reason (struct frame_info *this_frame,
2095 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2098 return UNWIND_UNAVAILABLE;
2100 /* This marks the outermost frame. */
2101 if (cache->base == 0)
2102 return UNWIND_OUTERMOST;
2104 return UNWIND_NO_REASON;
2107 static struct value *
2108 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2111 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2113 gdb_assert (regnum >= 0);
2115 /* The System V ABI says that:
2117 "The flags register contains the system flags, such as the
2118 direction flag and the carry flag. The direction flag must be
2119 set to the forward (that is, zero) direction before entry and
2120 upon exit from a function. Other user flags have no specified
2121 role in the standard calling sequence and are not preserved."
2123 To guarantee the "upon exit" part of that statement we fake a
2124 saved flags register that has its direction flag cleared.
2126 Note that GCC doesn't seem to rely on the fact that the direction
2127 flag is cleared after a function return; it always explicitly
2128 clears the flag before operations where it matters.
2130 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2131 right thing to do. The way we fake the flags register here makes
2132 it impossible to change it. */
2134 if (regnum == I386_EFLAGS_REGNUM)
2138 val = get_frame_register_unsigned (this_frame, regnum);
2140 return frame_unwind_got_constant (this_frame, regnum, val);
2143 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
2144 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
2146 if (regnum == I386_ESP_REGNUM
2147 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1))
2149 /* If the SP has been saved, but we don't know where, then this
2150 means that SAVED_SP_REG register was found unavailable back
2151 when we built the cache. */
2152 if (cache->saved_sp == 0)
2153 return frame_unwind_got_register (this_frame, regnum,
2154 cache->saved_sp_reg);
2156 return frame_unwind_got_constant (this_frame, regnum,
2160 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2161 return frame_unwind_got_memory (this_frame, regnum,
2162 cache->saved_regs[regnum]);
2164 return frame_unwind_got_register (this_frame, regnum, regnum);
2167 static const struct frame_unwind i386_frame_unwind =
2170 i386_frame_unwind_stop_reason,
2172 i386_frame_prev_register,
2174 default_frame_sniffer
2177 /* Normal frames, but in a function epilogue. */
2179 /* Implement the stack_frame_destroyed_p gdbarch method.
2181 The epilogue is defined here as the 'ret' instruction, which will
2182 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2183 the function's stack frame. */
2186 i386_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2189 struct compunit_symtab *cust;
2191 cust = find_pc_compunit_symtab (pc);
2192 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
2195 if (target_read_memory (pc, &insn, 1))
2196 return 0; /* Can't read memory at pc. */
2198 if (insn != 0xc3) /* 'ret' instruction. */
2205 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
2206 struct frame_info *this_frame,
2207 void **this_prologue_cache)
2209 if (frame_relative_level (this_frame) == 0)
2210 return i386_stack_frame_destroyed_p (get_frame_arch (this_frame),
2211 get_frame_pc (this_frame));
2216 static struct i386_frame_cache *
2217 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2219 struct i386_frame_cache *cache;
2225 cache = i386_alloc_frame_cache ();
2226 *this_cache = cache;
2230 cache->pc = get_frame_func (this_frame);
2232 /* At this point the stack looks as if we just entered the
2233 function, with the return address at the top of the
2235 sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM);
2236 cache->base = sp + cache->sp_offset;
2237 cache->saved_sp = cache->base + 8;
2238 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
2242 CATCH (ex, RETURN_MASK_ERROR)
2244 if (ex.error != NOT_AVAILABLE_ERROR)
2245 throw_exception (ex);
2252 static enum unwind_stop_reason
2253 i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2256 struct i386_frame_cache *cache =
2257 i386_epilogue_frame_cache (this_frame, this_cache);
2260 return UNWIND_UNAVAILABLE;
2262 return UNWIND_NO_REASON;
2266 i386_epilogue_frame_this_id (struct frame_info *this_frame,
2268 struct frame_id *this_id)
2270 struct i386_frame_cache *cache =
2271 i386_epilogue_frame_cache (this_frame, this_cache);
2274 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2276 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2279 static struct value *
2280 i386_epilogue_frame_prev_register (struct frame_info *this_frame,
2281 void **this_cache, int regnum)
2283 /* Make sure we've initialized the cache. */
2284 i386_epilogue_frame_cache (this_frame, this_cache);
2286 return i386_frame_prev_register (this_frame, this_cache, regnum);
2289 static const struct frame_unwind i386_epilogue_frame_unwind =
2292 i386_epilogue_frame_unwind_stop_reason,
2293 i386_epilogue_frame_this_id,
2294 i386_epilogue_frame_prev_register,
2296 i386_epilogue_frame_sniffer
2300 /* Stack-based trampolines. */
2302 /* These trampolines are used on cross x86 targets, when taking the
2303 address of a nested function. When executing these trampolines,
2304 no stack frame is set up, so we are in a similar situation as in
2305 epilogues and i386_epilogue_frame_this_id can be re-used. */
2307 /* Static chain passed in register. */
2309 struct i386_insn i386_tramp_chain_in_reg_insns[] =
2311 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2312 { 5, { 0xb8 }, { 0xfe } },
2315 { 5, { 0xe9 }, { 0xff } },
2320 /* Static chain passed on stack (when regparm=3). */
2322 struct i386_insn i386_tramp_chain_on_stack_insns[] =
2325 { 5, { 0x68 }, { 0xff } },
2328 { 5, { 0xe9 }, { 0xff } },
2333 /* Return whether PC points inside a stack trampoline. */
2336 i386_in_stack_tramp_p (CORE_ADDR pc)
2341 /* A stack trampoline is detected if no name is associated
2342 to the current pc and if it points inside a trampoline
2345 find_pc_partial_function (pc, &name, NULL, NULL);
2349 if (target_read_memory (pc, &insn, 1))
2352 if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns)
2353 && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns))
2360 i386_stack_tramp_frame_sniffer (const struct frame_unwind *self,
2361 struct frame_info *this_frame,
2364 if (frame_relative_level (this_frame) == 0)
2365 return i386_in_stack_tramp_p (get_frame_pc (this_frame));
2370 static const struct frame_unwind i386_stack_tramp_frame_unwind =
2373 i386_epilogue_frame_unwind_stop_reason,
2374 i386_epilogue_frame_this_id,
2375 i386_epilogue_frame_prev_register,
2377 i386_stack_tramp_frame_sniffer
2380 /* Generate a bytecode expression to get the value of the saved PC. */
2383 i386_gen_return_address (struct gdbarch *gdbarch,
2384 struct agent_expr *ax, struct axs_value *value,
2387 /* The following sequence assumes the traditional use of the base
2389 ax_reg (ax, I386_EBP_REGNUM);
2391 ax_simple (ax, aop_add);
2392 value->type = register_type (gdbarch, I386_EIP_REGNUM);
2393 value->kind = axs_lvalue_memory;
2397 /* Signal trampolines. */
2399 static struct i386_frame_cache *
2400 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2402 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2403 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2404 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2405 struct i386_frame_cache *cache;
2412 cache = i386_alloc_frame_cache ();
2416 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2417 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
2419 addr = tdep->sigcontext_addr (this_frame);
2420 if (tdep->sc_reg_offset)
2424 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
2426 for (i = 0; i < tdep->sc_num_regs; i++)
2427 if (tdep->sc_reg_offset[i] != -1)
2428 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2432 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
2433 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
2438 CATCH (ex, RETURN_MASK_ERROR)
2440 if (ex.error != NOT_AVAILABLE_ERROR)
2441 throw_exception (ex);
2445 *this_cache = cache;
2449 static enum unwind_stop_reason
2450 i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2453 struct i386_frame_cache *cache =
2454 i386_sigtramp_frame_cache (this_frame, this_cache);
2457 return UNWIND_UNAVAILABLE;
2459 return UNWIND_NO_REASON;
2463 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
2464 struct frame_id *this_id)
2466 struct i386_frame_cache *cache =
2467 i386_sigtramp_frame_cache (this_frame, this_cache);
2470 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2473 /* See the end of i386_push_dummy_call. */
2474 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
2478 static struct value *
2479 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
2480 void **this_cache, int regnum)
2482 /* Make sure we've initialized the cache. */
2483 i386_sigtramp_frame_cache (this_frame, this_cache);
2485 return i386_frame_prev_register (this_frame, this_cache, regnum);
2489 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
2490 struct frame_info *this_frame,
2491 void **this_prologue_cache)
2493 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2495 /* We shouldn't even bother if we don't have a sigcontext_addr
2497 if (tdep->sigcontext_addr == NULL)
2500 if (tdep->sigtramp_p != NULL)
2502 if (tdep->sigtramp_p (this_frame))
2506 if (tdep->sigtramp_start != 0)
2508 CORE_ADDR pc = get_frame_pc (this_frame);
2510 gdb_assert (tdep->sigtramp_end != 0);
2511 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2518 static const struct frame_unwind i386_sigtramp_frame_unwind =
2521 i386_sigtramp_frame_unwind_stop_reason,
2522 i386_sigtramp_frame_this_id,
2523 i386_sigtramp_frame_prev_register,
2525 i386_sigtramp_frame_sniffer
2530 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
2532 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2537 static const struct frame_base i386_frame_base =
2540 i386_frame_base_address,
2541 i386_frame_base_address,
2542 i386_frame_base_address
2545 static struct frame_id
2546 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2550 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
2552 /* See the end of i386_push_dummy_call. */
2553 return frame_id_build (fp + 8, get_frame_pc (this_frame));
2556 /* _Decimal128 function return values need 16-byte alignment on the
2560 i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2562 return sp & -(CORE_ADDR)16;
2566 /* Figure out where the longjmp will land. Slurp the args out of the
2567 stack. We expect the first arg to be a pointer to the jmp_buf
2568 structure from which we extract the address that we will land at.
2569 This address is copied into PC. This routine returns non-zero on
2573 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2576 CORE_ADDR sp, jb_addr;
2577 struct gdbarch *gdbarch = get_frame_arch (frame);
2578 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2579 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2581 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2582 longjmp will land. */
2583 if (jb_pc_offset == -1)
2586 get_frame_register (frame, I386_ESP_REGNUM, buf);
2587 sp = extract_unsigned_integer (buf, 4, byte_order);
2588 if (target_read_memory (sp + 4, buf, 4))
2591 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
2592 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
2595 *pc = extract_unsigned_integer (buf, 4, byte_order);
2600 /* Check whether TYPE must be 16-byte-aligned when passed as a
2601 function argument. 16-byte vectors, _Decimal128 and structures or
2602 unions containing such types must be 16-byte-aligned; other
2603 arguments are 4-byte-aligned. */
2606 i386_16_byte_align_p (struct type *type)
2608 type = check_typedef (type);
2609 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
2610 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
2611 && TYPE_LENGTH (type) == 16)
2613 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2614 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
2615 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2616 || TYPE_CODE (type) == TYPE_CODE_UNION)
2619 for (i = 0; i < TYPE_NFIELDS (type); i++)
2621 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
2628 /* Implementation for set_gdbarch_push_dummy_code. */
2631 i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
2632 struct value **args, int nargs, struct type *value_type,
2633 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
2634 struct regcache *regcache)
2636 /* Use 0xcc breakpoint - 1 byte. */
2640 /* Keep the stack aligned. */
2645 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2646 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2647 struct value **args, CORE_ADDR sp, int struct_return,
2648 CORE_ADDR struct_addr)
2650 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2656 /* Determine the total space required for arguments and struct
2657 return address in a first pass (allowing for 16-byte-aligned
2658 arguments), then push arguments in a second pass. */
2660 for (write_pass = 0; write_pass < 2; write_pass++)
2662 int args_space_used = 0;
2668 /* Push value address. */
2669 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2670 write_memory (sp, buf, 4);
2671 args_space_used += 4;
2677 for (i = 0; i < nargs; i++)
2679 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2683 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2684 args_space_used = align_up (args_space_used, 16);
2686 write_memory (sp + args_space_used,
2687 value_contents_all (args[i]), len);
2688 /* The System V ABI says that:
2690 "An argument's size is increased, if necessary, to make it a
2691 multiple of [32-bit] words. This may require tail padding,
2692 depending on the size of the argument."
2694 This makes sure the stack stays word-aligned. */
2695 args_space_used += align_up (len, 4);
2699 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2700 args_space = align_up (args_space, 16);
2701 args_space += align_up (len, 4);
2709 /* The original System V ABI only requires word alignment,
2710 but modern incarnations need 16-byte alignment in order
2711 to support SSE. Since wasting a few bytes here isn't
2712 harmful we unconditionally enforce 16-byte alignment. */
2717 /* Store return address. */
2719 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2720 write_memory (sp, buf, 4);
2722 /* Finally, update the stack pointer... */
2723 store_unsigned_integer (buf, 4, byte_order, sp);
2724 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
2726 /* ...and fake a frame pointer. */
2727 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
2729 /* MarkK wrote: This "+ 8" is all over the place:
2730 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2731 i386_dummy_id). It's there, since all frame unwinders for
2732 a given target have to agree (within a certain margin) on the
2733 definition of the stack address of a frame. Otherwise frame id
2734 comparison might not work correctly. Since DWARF2/GCC uses the
2735 stack address *before* the function call as a frame's CFA. On
2736 the i386, when %ebp is used as a frame pointer, the offset
2737 between the contents %ebp and the CFA as defined by GCC. */
2741 /* These registers are used for returning integers (and on some
2742 targets also for returning `struct' and `union' values when their
2743 size and alignment match an integer type). */
2744 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2745 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2747 /* Read, for architecture GDBARCH, a function return value of TYPE
2748 from REGCACHE, and copy that into VALBUF. */
2751 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2752 struct regcache *regcache, gdb_byte *valbuf)
2754 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2755 int len = TYPE_LENGTH (type);
2756 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2758 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2760 if (tdep->st0_regnum < 0)
2762 warning (_("Cannot find floating-point return value."));
2763 memset (valbuf, 0, len);
2767 /* Floating-point return values can be found in %st(0). Convert
2768 its contents to the desired type. This is probably not
2769 exactly how it would happen on the target itself, but it is
2770 the best we can do. */
2771 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2772 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
2776 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2777 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2779 if (len <= low_size)
2781 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2782 memcpy (valbuf, buf, len);
2784 else if (len <= (low_size + high_size))
2786 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2787 memcpy (valbuf, buf, low_size);
2788 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2789 memcpy (valbuf + low_size, buf, len - low_size);
2792 internal_error (__FILE__, __LINE__,
2793 _("Cannot extract return value of %d bytes long."),
2798 /* Write, for architecture GDBARCH, a function return value of TYPE
2799 from VALBUF into REGCACHE. */
2802 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2803 struct regcache *regcache, const gdb_byte *valbuf)
2805 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2806 int len = TYPE_LENGTH (type);
2808 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2811 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2813 if (tdep->st0_regnum < 0)
2815 warning (_("Cannot set floating-point return value."));
2819 /* Returning floating-point values is a bit tricky. Apart from
2820 storing the return value in %st(0), we have to simulate the
2821 state of the FPU at function return point. */
2823 /* Convert the value found in VALBUF to the extended
2824 floating-point format used by the FPU. This is probably
2825 not exactly how it would happen on the target itself, but
2826 it is the best we can do. */
2827 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
2828 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2830 /* Set the top of the floating-point register stack to 7. The
2831 actual value doesn't really matter, but 7 is what a normal
2832 function return would end up with if the program started out
2833 with a freshly initialized FPU. */
2834 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2836 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2838 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2839 the floating-point register stack to 7, the appropriate value
2840 for the tag word is 0x3fff. */
2841 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2845 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2846 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2848 if (len <= low_size)
2849 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2850 else if (len <= (low_size + high_size))
2852 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2853 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
2854 len - low_size, valbuf + low_size);
2857 internal_error (__FILE__, __LINE__,
2858 _("Cannot store return value of %d bytes long."), len);
2863 /* This is the variable that is set with "set struct-convention", and
2864 its legitimate values. */
2865 static const char default_struct_convention[] = "default";
2866 static const char pcc_struct_convention[] = "pcc";
2867 static const char reg_struct_convention[] = "reg";
2868 static const char *const valid_conventions[] =
2870 default_struct_convention,
2871 pcc_struct_convention,
2872 reg_struct_convention,
2875 static const char *struct_convention = default_struct_convention;
2877 /* Return non-zero if TYPE, which is assumed to be a structure,
2878 a union type, or an array type, should be returned in registers
2879 for architecture GDBARCH. */
2882 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2884 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2885 enum type_code code = TYPE_CODE (type);
2886 int len = TYPE_LENGTH (type);
2888 gdb_assert (code == TYPE_CODE_STRUCT
2889 || code == TYPE_CODE_UNION
2890 || code == TYPE_CODE_ARRAY);
2892 if (struct_convention == pcc_struct_convention
2893 || (struct_convention == default_struct_convention
2894 && tdep->struct_return == pcc_struct_return))
2897 /* Structures consisting of a single `float', `double' or 'long
2898 double' member are returned in %st(0). */
2899 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2901 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2902 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2903 return (len == 4 || len == 8 || len == 12);
2906 return (len == 1 || len == 2 || len == 4 || len == 8);
2909 /* Determine, for architecture GDBARCH, how a return value of TYPE
2910 should be returned. If it is supposed to be returned in registers,
2911 and READBUF is non-zero, read the appropriate value from REGCACHE,
2912 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2913 from WRITEBUF into REGCACHE. */
2915 static enum return_value_convention
2916 i386_return_value (struct gdbarch *gdbarch, struct value *function,
2917 struct type *type, struct regcache *regcache,
2918 gdb_byte *readbuf, const gdb_byte *writebuf)
2920 enum type_code code = TYPE_CODE (type);
2922 if (((code == TYPE_CODE_STRUCT
2923 || code == TYPE_CODE_UNION
2924 || code == TYPE_CODE_ARRAY)
2925 && !i386_reg_struct_return_p (gdbarch, type))
2926 /* Complex double and long double uses the struct return covention. */
2927 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16)
2928 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24)
2929 /* 128-bit decimal float uses the struct return convention. */
2930 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2932 /* The System V ABI says that:
2934 "A function that returns a structure or union also sets %eax
2935 to the value of the original address of the caller's area
2936 before it returns. Thus when the caller receives control
2937 again, the address of the returned object resides in register
2938 %eax and can be used to access the object."
2940 So the ABI guarantees that we can always find the return
2941 value just after the function has returned. */
2943 /* Note that the ABI doesn't mention functions returning arrays,
2944 which is something possible in certain languages such as Ada.
2945 In this case, the value is returned as if it was wrapped in
2946 a record, so the convention applied to records also applies
2953 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2954 read_memory (addr, readbuf, TYPE_LENGTH (type));
2957 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2960 /* This special case is for structures consisting of a single
2961 `float', `double' or 'long double' member. These structures are
2962 returned in %st(0). For these structures, we call ourselves
2963 recursively, changing TYPE into the type of the first member of
2964 the structure. Since that should work for all structures that
2965 have only one member, we don't bother to check the member's type
2967 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2969 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2970 return i386_return_value (gdbarch, function, type, regcache,
2975 i386_extract_return_value (gdbarch, type, regcache, readbuf);
2977 i386_store_return_value (gdbarch, type, regcache, writebuf);
2979 return RETURN_VALUE_REGISTER_CONVENTION;
2984 i387_ext_type (struct gdbarch *gdbarch)
2986 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2988 if (!tdep->i387_ext_type)
2990 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
2991 gdb_assert (tdep->i387_ext_type != NULL);
2994 return tdep->i387_ext_type;
2997 /* Construct type for pseudo BND registers. We can't use
2998 tdesc_find_type since a complement of one value has to be used
2999 to describe the upper bound. */
3001 static struct type *
3002 i386_bnd_type (struct gdbarch *gdbarch)
3004 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3007 if (!tdep->i386_bnd_type)
3009 struct type *t, *bound_t;
3010 const struct builtin_type *bt = builtin_type (gdbarch);
3012 /* The type we're building is described bellow: */
3017 void *ubound; /* One complement of raw ubound field. */
3021 t = arch_composite_type (gdbarch,
3022 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT);
3024 append_composite_type_field (t, "lbound", bt->builtin_data_ptr);
3025 append_composite_type_field (t, "ubound", bt->builtin_data_ptr);
3027 TYPE_NAME (t) = "builtin_type_bound128";
3028 tdep->i386_bnd_type = t;
3031 return tdep->i386_bnd_type;
3034 /* Construct vector type for pseudo ZMM registers. We can't use
3035 tdesc_find_type since ZMM isn't described in target description. */
3037 static struct type *
3038 i386_zmm_type (struct gdbarch *gdbarch)
3040 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3042 if (!tdep->i386_zmm_type)
3044 const struct builtin_type *bt = builtin_type (gdbarch);
3046 /* The type we're building is this: */
3048 union __gdb_builtin_type_vec512i
3050 int128_t uint128[4];
3051 int64_t v4_int64[8];
3052 int32_t v8_int32[16];
3053 int16_t v16_int16[32];
3054 int8_t v32_int8[64];
3055 double v4_double[8];
3062 t = arch_composite_type (gdbarch,
3063 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION);
3064 append_composite_type_field (t, "v16_float",
3065 init_vector_type (bt->builtin_float, 16));
3066 append_composite_type_field (t, "v8_double",
3067 init_vector_type (bt->builtin_double, 8));
3068 append_composite_type_field (t, "v64_int8",
3069 init_vector_type (bt->builtin_int8, 64));
3070 append_composite_type_field (t, "v32_int16",
3071 init_vector_type (bt->builtin_int16, 32));
3072 append_composite_type_field (t, "v16_int32",
3073 init_vector_type (bt->builtin_int32, 16));
3074 append_composite_type_field (t, "v8_int64",
3075 init_vector_type (bt->builtin_int64, 8));
3076 append_composite_type_field (t, "v4_int128",
3077 init_vector_type (bt->builtin_int128, 4));
3079 TYPE_VECTOR (t) = 1;
3080 TYPE_NAME (t) = "builtin_type_vec512i";
3081 tdep->i386_zmm_type = t;
3084 return tdep->i386_zmm_type;
3087 /* Construct vector type for pseudo YMM registers. We can't use
3088 tdesc_find_type since YMM isn't described in target description. */
3090 static struct type *
3091 i386_ymm_type (struct gdbarch *gdbarch)
3093 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3095 if (!tdep->i386_ymm_type)
3097 const struct builtin_type *bt = builtin_type (gdbarch);
3099 /* The type we're building is this: */
3101 union __gdb_builtin_type_vec256i
3103 int128_t uint128[2];
3104 int64_t v2_int64[4];
3105 int32_t v4_int32[8];
3106 int16_t v8_int16[16];
3107 int8_t v16_int8[32];
3108 double v2_double[4];
3115 t = arch_composite_type (gdbarch,
3116 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
3117 append_composite_type_field (t, "v8_float",
3118 init_vector_type (bt->builtin_float, 8));
3119 append_composite_type_field (t, "v4_double",
3120 init_vector_type (bt->builtin_double, 4));
3121 append_composite_type_field (t, "v32_int8",
3122 init_vector_type (bt->builtin_int8, 32));
3123 append_composite_type_field (t, "v16_int16",
3124 init_vector_type (bt->builtin_int16, 16));
3125 append_composite_type_field (t, "v8_int32",
3126 init_vector_type (bt->builtin_int32, 8));
3127 append_composite_type_field (t, "v4_int64",
3128 init_vector_type (bt->builtin_int64, 4));
3129 append_composite_type_field (t, "v2_int128",
3130 init_vector_type (bt->builtin_int128, 2));
3132 TYPE_VECTOR (t) = 1;
3133 TYPE_NAME (t) = "builtin_type_vec256i";
3134 tdep->i386_ymm_type = t;
3137 return tdep->i386_ymm_type;
3140 /* Construct vector type for MMX registers. */
3141 static struct type *
3142 i386_mmx_type (struct gdbarch *gdbarch)
3144 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3146 if (!tdep->i386_mmx_type)
3148 const struct builtin_type *bt = builtin_type (gdbarch);
3150 /* The type we're building is this: */
3152 union __gdb_builtin_type_vec64i
3155 int32_t v2_int32[2];
3156 int16_t v4_int16[4];
3163 t = arch_composite_type (gdbarch,
3164 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
3166 append_composite_type_field (t, "uint64", bt->builtin_int64);
3167 append_composite_type_field (t, "v2_int32",
3168 init_vector_type (bt->builtin_int32, 2));
3169 append_composite_type_field (t, "v4_int16",
3170 init_vector_type (bt->builtin_int16, 4));
3171 append_composite_type_field (t, "v8_int8",
3172 init_vector_type (bt->builtin_int8, 8));
3174 TYPE_VECTOR (t) = 1;
3175 TYPE_NAME (t) = "builtin_type_vec64i";
3176 tdep->i386_mmx_type = t;
3179 return tdep->i386_mmx_type;
3182 /* Return the GDB type object for the "standard" data type of data in
3186 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3188 if (i386_bnd_regnum_p (gdbarch, regnum))
3189 return i386_bnd_type (gdbarch);
3190 if (i386_mmx_regnum_p (gdbarch, regnum))
3191 return i386_mmx_type (gdbarch);
3192 else if (i386_ymm_regnum_p (gdbarch, regnum))
3193 return i386_ymm_type (gdbarch);
3194 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3195 return i386_ymm_type (gdbarch);
3196 else if (i386_zmm_regnum_p (gdbarch, regnum))
3197 return i386_zmm_type (gdbarch);
3200 const struct builtin_type *bt = builtin_type (gdbarch);
3201 if (i386_byte_regnum_p (gdbarch, regnum))
3202 return bt->builtin_int8;
3203 else if (i386_word_regnum_p (gdbarch, regnum))
3204 return bt->builtin_int16;
3205 else if (i386_dword_regnum_p (gdbarch, regnum))
3206 return bt->builtin_int32;
3207 else if (i386_k_regnum_p (gdbarch, regnum))
3208 return bt->builtin_int64;
3211 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3214 /* Map a cooked register onto a raw register or memory. For the i386,
3215 the MMX registers need to be mapped onto floating point registers. */
3218 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
3220 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
3225 mmxreg = regnum - tdep->mm0_regnum;
3226 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
3227 tos = (fstat >> 11) & 0x7;
3228 fpreg = (mmxreg + tos) % 8;
3230 return (I387_ST0_REGNUM (tdep) + fpreg);
3233 /* A helper function for us by i386_pseudo_register_read_value and
3234 amd64_pseudo_register_read_value. It does all the work but reads
3235 the data into an already-allocated value. */
3238 i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
3239 struct regcache *regcache,
3241 struct value *result_value)
3243 gdb_byte raw_buf[MAX_REGISTER_SIZE];
3244 enum register_status status;
3245 gdb_byte *buf = value_contents_raw (result_value);
3247 if (i386_mmx_regnum_p (gdbarch, regnum))
3249 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3251 /* Extract (always little endian). */
3252 status = regcache_raw_read (regcache, fpnum, raw_buf);
3253 if (status != REG_VALID)
3254 mark_value_bytes_unavailable (result_value, 0,
3255 TYPE_LENGTH (value_type (result_value)));
3257 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
3261 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3262 if (i386_bnd_regnum_p (gdbarch, regnum))
3264 regnum -= tdep->bnd0_regnum;
3266 /* Extract (always little endian). Read lower 128bits. */
3267 status = regcache_raw_read (regcache,
3268 I387_BND0R_REGNUM (tdep) + regnum,
3270 if (status != REG_VALID)
3271 mark_value_bytes_unavailable (result_value, 0, 16);
3274 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3275 LONGEST upper, lower;
3276 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3278 lower = extract_unsigned_integer (raw_buf, 8, byte_order);
3279 upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order);
3282 memcpy (buf, &lower, size);
3283 memcpy (buf + size, &upper, size);
3286 else if (i386_k_regnum_p (gdbarch, regnum))
3288 regnum -= tdep->k0_regnum;
3290 /* Extract (always little endian). */
3291 status = regcache_raw_read (regcache,
3292 tdep->k0_regnum + regnum,
3294 if (status != REG_VALID)
3295 mark_value_bytes_unavailable (result_value, 0, 8);
3297 memcpy (buf, raw_buf, 8);
3299 else if (i386_zmm_regnum_p (gdbarch, regnum))
3301 regnum -= tdep->zmm0_regnum;
3303 if (regnum < num_lower_zmm_regs)
3305 /* Extract (always little endian). Read lower 128bits. */
3306 status = regcache_raw_read (regcache,
3307 I387_XMM0_REGNUM (tdep) + regnum,
3309 if (status != REG_VALID)
3310 mark_value_bytes_unavailable (result_value, 0, 16);
3312 memcpy (buf, raw_buf, 16);
3314 /* Extract (always little endian). Read upper 128bits. */
3315 status = regcache_raw_read (regcache,
3316 tdep->ymm0h_regnum + regnum,
3318 if (status != REG_VALID)
3319 mark_value_bytes_unavailable (result_value, 16, 16);
3321 memcpy (buf + 16, raw_buf, 16);
3325 /* Extract (always little endian). Read lower 128bits. */
3326 status = regcache_raw_read (regcache,
3327 I387_XMM16_REGNUM (tdep) + regnum
3328 - num_lower_zmm_regs,
3330 if (status != REG_VALID)
3331 mark_value_bytes_unavailable (result_value, 0, 16);
3333 memcpy (buf, raw_buf, 16);
3335 /* Extract (always little endian). Read upper 128bits. */
3336 status = regcache_raw_read (regcache,
3337 I387_YMM16H_REGNUM (tdep) + regnum
3338 - num_lower_zmm_regs,
3340 if (status != REG_VALID)
3341 mark_value_bytes_unavailable (result_value, 16, 16);
3343 memcpy (buf + 16, raw_buf, 16);
3346 /* Read upper 256bits. */
3347 status = regcache_raw_read (regcache,
3348 tdep->zmm0h_regnum + regnum,
3350 if (status != REG_VALID)
3351 mark_value_bytes_unavailable (result_value, 32, 32);
3353 memcpy (buf + 32, raw_buf, 32);
3355 else if (i386_ymm_regnum_p (gdbarch, regnum))
3357 regnum -= tdep->ymm0_regnum;
3359 /* Extract (always little endian). Read lower 128bits. */
3360 status = regcache_raw_read (regcache,
3361 I387_XMM0_REGNUM (tdep) + regnum,
3363 if (status != REG_VALID)
3364 mark_value_bytes_unavailable (result_value, 0, 16);
3366 memcpy (buf, raw_buf, 16);
3367 /* Read upper 128bits. */
3368 status = regcache_raw_read (regcache,
3369 tdep->ymm0h_regnum + regnum,
3371 if (status != REG_VALID)
3372 mark_value_bytes_unavailable (result_value, 16, 32);
3374 memcpy (buf + 16, raw_buf, 16);
3376 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3378 regnum -= tdep->ymm16_regnum;
3379 /* Extract (always little endian). Read lower 128bits. */
3380 status = regcache_raw_read (regcache,
3381 I387_XMM16_REGNUM (tdep) + regnum,
3383 if (status != REG_VALID)
3384 mark_value_bytes_unavailable (result_value, 0, 16);
3386 memcpy (buf, raw_buf, 16);
3387 /* Read upper 128bits. */
3388 status = regcache_raw_read (regcache,
3389 tdep->ymm16h_regnum + regnum,
3391 if (status != REG_VALID)
3392 mark_value_bytes_unavailable (result_value, 16, 16);
3394 memcpy (buf + 16, raw_buf, 16);
3396 else if (i386_word_regnum_p (gdbarch, regnum))
3398 int gpnum = regnum - tdep->ax_regnum;
3400 /* Extract (always little endian). */
3401 status = regcache_raw_read (regcache, gpnum, raw_buf);
3402 if (status != REG_VALID)
3403 mark_value_bytes_unavailable (result_value, 0,
3404 TYPE_LENGTH (value_type (result_value)));
3406 memcpy (buf, raw_buf, 2);
3408 else if (i386_byte_regnum_p (gdbarch, regnum))
3410 /* Check byte pseudo registers last since this function will
3411 be called from amd64_pseudo_register_read, which handles
3412 byte pseudo registers differently. */
3413 int gpnum = regnum - tdep->al_regnum;
3415 /* Extract (always little endian). We read both lower and
3417 status = regcache_raw_read (regcache, gpnum % 4, raw_buf);
3418 if (status != REG_VALID)
3419 mark_value_bytes_unavailable (result_value, 0,
3420 TYPE_LENGTH (value_type (result_value)));
3421 else if (gpnum >= 4)
3422 memcpy (buf, raw_buf + 1, 1);
3424 memcpy (buf, raw_buf, 1);
3427 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3431 static struct value *
3432 i386_pseudo_register_read_value (struct gdbarch *gdbarch,
3433 struct regcache *regcache,
3436 struct value *result;
3438 result = allocate_value (register_type (gdbarch, regnum));
3439 VALUE_LVAL (result) = lval_register;
3440 VALUE_REGNUM (result) = regnum;
3442 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result);
3448 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3449 int regnum, const gdb_byte *buf)
3451 gdb_byte raw_buf[MAX_REGISTER_SIZE];
3453 if (i386_mmx_regnum_p (gdbarch, regnum))
3455 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3458 regcache_raw_read (regcache, fpnum, raw_buf);
3459 /* ... Modify ... (always little endian). */
3460 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
3462 regcache_raw_write (regcache, fpnum, raw_buf);
3466 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3468 if (i386_bnd_regnum_p (gdbarch, regnum))
3470 ULONGEST upper, lower;
3471 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3472 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3474 /* New values from input value. */
3475 regnum -= tdep->bnd0_regnum;
3476 lower = extract_unsigned_integer (buf, size, byte_order);
3477 upper = extract_unsigned_integer (buf + size, size, byte_order);
3479 /* Fetching register buffer. */
3480 regcache_raw_read (regcache,
3481 I387_BND0R_REGNUM (tdep) + regnum,
3486 /* Set register bits. */
3487 memcpy (raw_buf, &lower, 8);
3488 memcpy (raw_buf + 8, &upper, 8);
3491 regcache_raw_write (regcache,
3492 I387_BND0R_REGNUM (tdep) + regnum,
3495 else if (i386_k_regnum_p (gdbarch, regnum))
3497 regnum -= tdep->k0_regnum;
3499 regcache_raw_write (regcache,
3500 tdep->k0_regnum + regnum,
3503 else if (i386_zmm_regnum_p (gdbarch, regnum))
3505 regnum -= tdep->zmm0_regnum;
3507 if (regnum < num_lower_zmm_regs)
3509 /* Write lower 128bits. */
3510 regcache_raw_write (regcache,
3511 I387_XMM0_REGNUM (tdep) + regnum,
3513 /* Write upper 128bits. */
3514 regcache_raw_write (regcache,
3515 I387_YMM0_REGNUM (tdep) + regnum,
3520 /* Write lower 128bits. */
3521 regcache_raw_write (regcache,
3522 I387_XMM16_REGNUM (tdep) + regnum
3523 - num_lower_zmm_regs,
3525 /* Write upper 128bits. */
3526 regcache_raw_write (regcache,
3527 I387_YMM16H_REGNUM (tdep) + regnum
3528 - num_lower_zmm_regs,
3531 /* Write upper 256bits. */
3532 regcache_raw_write (regcache,
3533 tdep->zmm0h_regnum + regnum,
3536 else if (i386_ymm_regnum_p (gdbarch, regnum))
3538 regnum -= tdep->ymm0_regnum;
3540 /* ... Write lower 128bits. */
3541 regcache_raw_write (regcache,
3542 I387_XMM0_REGNUM (tdep) + regnum,
3544 /* ... Write upper 128bits. */
3545 regcache_raw_write (regcache,
3546 tdep->ymm0h_regnum + regnum,
3549 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3551 regnum -= tdep->ymm16_regnum;
3553 /* ... Write lower 128bits. */
3554 regcache_raw_write (regcache,
3555 I387_XMM16_REGNUM (tdep) + regnum,
3557 /* ... Write upper 128bits. */
3558 regcache_raw_write (regcache,
3559 tdep->ymm16h_regnum + regnum,
3562 else if (i386_word_regnum_p (gdbarch, regnum))
3564 int gpnum = regnum - tdep->ax_regnum;
3567 regcache_raw_read (regcache, gpnum, raw_buf);
3568 /* ... Modify ... (always little endian). */
3569 memcpy (raw_buf, buf, 2);
3571 regcache_raw_write (regcache, gpnum, raw_buf);
3573 else if (i386_byte_regnum_p (gdbarch, regnum))
3575 /* Check byte pseudo registers last since this function will
3576 be called from amd64_pseudo_register_read, which handles
3577 byte pseudo registers differently. */
3578 int gpnum = regnum - tdep->al_regnum;
3580 /* Read ... We read both lower and upper registers. */
3581 regcache_raw_read (regcache, gpnum % 4, raw_buf);
3582 /* ... Modify ... (always little endian). */
3584 memcpy (raw_buf + 1, buf, 1);
3586 memcpy (raw_buf, buf, 1);
3588 regcache_raw_write (regcache, gpnum % 4, raw_buf);
3591 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3596 /* Return the register number of the register allocated by GCC after
3597 REGNUM, or -1 if there is no such register. */
3600 i386_next_regnum (int regnum)
3602 /* GCC allocates the registers in the order:
3604 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3606 Since storing a variable in %esp doesn't make any sense we return
3607 -1 for %ebp and for %esp itself. */
3608 static int next_regnum[] =
3610 I386_EDX_REGNUM, /* Slot for %eax. */
3611 I386_EBX_REGNUM, /* Slot for %ecx. */
3612 I386_ECX_REGNUM, /* Slot for %edx. */
3613 I386_ESI_REGNUM, /* Slot for %ebx. */
3614 -1, -1, /* Slots for %esp and %ebp. */
3615 I386_EDI_REGNUM, /* Slot for %esi. */
3616 I386_EBP_REGNUM /* Slot for %edi. */
3619 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
3620 return next_regnum[regnum];
3625 /* Return nonzero if a value of type TYPE stored in register REGNUM
3626 needs any special handling. */
3629 i386_convert_register_p (struct gdbarch *gdbarch,
3630 int regnum, struct type *type)
3632 int len = TYPE_LENGTH (type);
3634 /* Values may be spread across multiple registers. Most debugging
3635 formats aren't expressive enough to specify the locations, so
3636 some heuristics is involved. Right now we only handle types that
3637 have a length that is a multiple of the word size, since GCC
3638 doesn't seem to put any other types into registers. */
3639 if (len > 4 && len % 4 == 0)
3641 int last_regnum = regnum;
3645 last_regnum = i386_next_regnum (last_regnum);
3649 if (last_regnum != -1)
3653 return i387_convert_register_p (gdbarch, regnum, type);
3656 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3657 return its contents in TO. */
3660 i386_register_to_value (struct frame_info *frame, int regnum,
3661 struct type *type, gdb_byte *to,
3662 int *optimizedp, int *unavailablep)
3664 struct gdbarch *gdbarch = get_frame_arch (frame);
3665 int len = TYPE_LENGTH (type);
3667 if (i386_fp_regnum_p (gdbarch, regnum))
3668 return i387_register_to_value (frame, regnum, type, to,
3669 optimizedp, unavailablep);
3671 /* Read a value spread across multiple registers. */
3673 gdb_assert (len > 4 && len % 4 == 0);
3677 gdb_assert (regnum != -1);
3678 gdb_assert (register_size (gdbarch, regnum) == 4);
3680 if (!get_frame_register_bytes (frame, regnum, 0,
3681 register_size (gdbarch, regnum),
3682 to, optimizedp, unavailablep))
3685 regnum = i386_next_regnum (regnum);
3690 *optimizedp = *unavailablep = 0;
3694 /* Write the contents FROM of a value of type TYPE into register
3695 REGNUM in frame FRAME. */
3698 i386_value_to_register (struct frame_info *frame, int regnum,
3699 struct type *type, const gdb_byte *from)
3701 int len = TYPE_LENGTH (type);
3703 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
3705 i387_value_to_register (frame, regnum, type, from);
3709 /* Write a value spread across multiple registers. */
3711 gdb_assert (len > 4 && len % 4 == 0);
3715 gdb_assert (regnum != -1);
3716 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
3718 put_frame_register (frame, regnum, from);
3719 regnum = i386_next_regnum (regnum);
3725 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3726 in the general-purpose register set REGSET to register cache
3727 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3730 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
3731 int regnum, const void *gregs, size_t len)
3733 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3734 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3735 const gdb_byte *regs = gregs;
3738 gdb_assert (len >= tdep->sizeof_gregset);
3740 for (i = 0; i < tdep->gregset_num_regs; i++)
3742 if ((regnum == i || regnum == -1)
3743 && tdep->gregset_reg_offset[i] != -1)
3744 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
3748 /* Collect register REGNUM from the register cache REGCACHE and store
3749 it in the buffer specified by GREGS and LEN as described by the
3750 general-purpose register set REGSET. If REGNUM is -1, do this for
3751 all registers in REGSET. */
3754 i386_collect_gregset (const struct regset *regset,
3755 const struct regcache *regcache,
3756 int regnum, void *gregs, size_t len)
3758 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3759 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3760 gdb_byte *regs = gregs;
3763 gdb_assert (len >= tdep->sizeof_gregset);
3765 for (i = 0; i < tdep->gregset_num_regs; i++)
3767 if ((regnum == i || regnum == -1)
3768 && tdep->gregset_reg_offset[i] != -1)
3769 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
3773 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3774 in the floating-point register set REGSET to register cache
3775 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3778 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
3779 int regnum, const void *fpregs, size_t len)
3781 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3782 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3784 if (len == I387_SIZEOF_FXSAVE)
3786 i387_supply_fxsave (regcache, regnum, fpregs);
3790 gdb_assert (len >= tdep->sizeof_fpregset);
3791 i387_supply_fsave (regcache, regnum, fpregs);
3794 /* Collect register REGNUM from the register cache REGCACHE and store
3795 it in the buffer specified by FPREGS and LEN as described by the
3796 floating-point register set REGSET. If REGNUM is -1, do this for
3797 all registers in REGSET. */
3800 i386_collect_fpregset (const struct regset *regset,
3801 const struct regcache *regcache,
3802 int regnum, void *fpregs, size_t len)
3804 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3805 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3807 if (len == I387_SIZEOF_FXSAVE)
3809 i387_collect_fxsave (regcache, regnum, fpregs);
3813 gdb_assert (len >= tdep->sizeof_fpregset);
3814 i387_collect_fsave (regcache, regnum, fpregs);
3817 /* Register set definitions. */
3819 const struct regset i386_gregset =
3821 NULL, i386_supply_gregset, i386_collect_gregset
3824 const struct regset i386_fpregset =
3826 NULL, i386_supply_fpregset, i386_collect_fpregset
3829 /* Default iterator over core file register note sections. */
3832 i386_iterate_over_regset_sections (struct gdbarch *gdbarch,
3833 iterate_over_regset_sections_cb *cb,
3835 const struct regcache *regcache)
3837 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3839 cb (".reg", tdep->sizeof_gregset, &i386_gregset, NULL, cb_data);
3840 if (tdep->sizeof_fpregset)
3841 cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
3845 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3848 i386_pe_skip_trampoline_code (struct frame_info *frame,
3849 CORE_ADDR pc, char *name)
3851 struct gdbarch *gdbarch = get_frame_arch (frame);
3852 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3855 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
3857 unsigned long indirect =
3858 read_memory_unsigned_integer (pc + 2, 4, byte_order);
3859 struct minimal_symbol *indsym =
3860 indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0;
3861 const char *symname = indsym ? MSYMBOL_LINKAGE_NAME (indsym) : 0;
3865 if (startswith (symname, "__imp_")
3866 || startswith (symname, "_imp_"))
3868 read_memory_unsigned_integer (indirect, 4, byte_order);
3871 return 0; /* Not a trampoline. */
3875 /* Return whether the THIS_FRAME corresponds to a sigtramp
3879 i386_sigtramp_p (struct frame_info *this_frame)
3881 CORE_ADDR pc = get_frame_pc (this_frame);
3884 find_pc_partial_function (pc, &name, NULL, NULL);
3885 return (name && strcmp ("_sigtramp", name) == 0);
3889 /* We have two flavours of disassembly. The machinery on this page
3890 deals with switching between those. */
3893 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
3895 gdb_assert (disassembly_flavor == att_flavor
3896 || disassembly_flavor == intel_flavor);
3898 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3899 constified, cast to prevent a compiler warning. */
3900 info->disassembler_options = (char *) disassembly_flavor;
3902 return print_insn_i386 (pc, info);
3906 /* There are a few i386 architecture variants that differ only
3907 slightly from the generic i386 target. For now, we don't give them
3908 their own source file, but include them here. As a consequence,
3909 they'll always be included. */
3911 /* System V Release 4 (SVR4). */
3913 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3917 i386_svr4_sigtramp_p (struct frame_info *this_frame)
3919 CORE_ADDR pc = get_frame_pc (this_frame);
3922 /* The origin of these symbols is currently unknown. */
3923 find_pc_partial_function (pc, &name, NULL, NULL);
3924 return (name && (strcmp ("_sigreturn", name) == 0
3925 || strcmp ("sigvechandler", name) == 0));
3928 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3929 address of the associated sigcontext (ucontext) structure. */
3932 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
3934 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3935 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3939 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
3940 sp = extract_unsigned_integer (buf, 4, byte_order);
3942 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
3947 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
3951 i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s)
3953 return (*s == '$' /* Literal number. */
3954 || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */
3955 || (*s == '(' && s[1] == '%') /* Register indirection. */
3956 || (*s == '%' && isalpha (s[1]))); /* Register access. */
3959 /* Helper function for i386_stap_parse_special_token.
3961 This function parses operands of the form `-8+3+1(%rbp)', which
3962 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
3964 Return 1 if the operand was parsed successfully, zero
3968 i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch,
3969 struct stap_parse_info *p)
3971 const char *s = p->arg;
3973 if (isdigit (*s) || *s == '-' || *s == '+')
3977 long displacements[3];
3993 if (!isdigit ((unsigned char) *s))
3996 displacements[0] = strtol (s, &endp, 10);
3999 if (*s != '+' && *s != '-')
4001 /* We are not dealing with a triplet. */
4014 if (!isdigit ((unsigned char) *s))
4017 displacements[1] = strtol (s, &endp, 10);
4020 if (*s != '+' && *s != '-')
4022 /* We are not dealing with a triplet. */
4035 if (!isdigit ((unsigned char) *s))
4038 displacements[2] = strtol (s, &endp, 10);
4041 if (*s != '(' || s[1] != '%')
4047 while (isalnum (*s))
4053 len = s - start - 1;
4054 regname = alloca (len + 1);
4056 strncpy (regname, start, len);
4057 regname[len] = '\0';
4059 if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1)
4060 error (_("Invalid register name `%s' on expression `%s'."),
4061 regname, p->saved_arg);
4063 for (i = 0; i < 3; i++)
4065 write_exp_elt_opcode (&p->pstate, OP_LONG);
4067 (&p->pstate, builtin_type (gdbarch)->builtin_long);
4068 write_exp_elt_longcst (&p->pstate, displacements[i]);
4069 write_exp_elt_opcode (&p->pstate, OP_LONG);
4071 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4074 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4077 write_exp_string (&p->pstate, str);
4078 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4080 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4081 write_exp_elt_type (&p->pstate,
4082 builtin_type (gdbarch)->builtin_data_ptr);
4083 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4085 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4086 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4087 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4089 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4090 write_exp_elt_type (&p->pstate,
4091 lookup_pointer_type (p->arg_type));
4092 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4094 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4104 /* Helper function for i386_stap_parse_special_token.
4106 This function parses operands of the form `register base +
4107 (register index * size) + offset', as represented in
4108 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4110 Return 1 if the operand was parsed successfully, zero
4114 i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch,
4115 struct stap_parse_info *p)
4117 const char *s = p->arg;
4119 if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+')
4121 int offset_minus = 0;
4130 struct stoken base_token, index_token;
4140 if (offset_minus && !isdigit (*s))
4147 offset = strtol (s, &endp, 10);
4151 if (*s != '(' || s[1] != '%')
4157 while (isalnum (*s))
4160 if (*s != ',' || s[1] != '%')
4163 len_base = s - start;
4164 base = alloca (len_base + 1);
4165 strncpy (base, start, len_base);
4166 base[len_base] = '\0';
4168 if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1)
4169 error (_("Invalid register name `%s' on expression `%s'."),
4170 base, p->saved_arg);
4175 while (isalnum (*s))
4178 len_index = s - start;
4179 index = alloca (len_index + 1);
4180 strncpy (index, start, len_index);
4181 index[len_index] = '\0';
4183 if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1)
4184 error (_("Invalid register name `%s' on expression `%s'."),
4185 index, p->saved_arg);
4187 if (*s != ',' && *s != ')')
4203 size = strtol (s, &endp, 10);
4214 write_exp_elt_opcode (&p->pstate, OP_LONG);
4215 write_exp_elt_type (&p->pstate,
4216 builtin_type (gdbarch)->builtin_long);
4217 write_exp_elt_longcst (&p->pstate, offset);
4218 write_exp_elt_opcode (&p->pstate, OP_LONG);
4220 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4223 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4224 base_token.ptr = base;
4225 base_token.length = len_base;
4226 write_exp_string (&p->pstate, base_token);
4227 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4230 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4232 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4233 index_token.ptr = index;
4234 index_token.length = len_index;
4235 write_exp_string (&p->pstate, index_token);
4236 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4240 write_exp_elt_opcode (&p->pstate, OP_LONG);
4241 write_exp_elt_type (&p->pstate,
4242 builtin_type (gdbarch)->builtin_long);
4243 write_exp_elt_longcst (&p->pstate, size);
4244 write_exp_elt_opcode (&p->pstate, OP_LONG);
4246 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4247 write_exp_elt_opcode (&p->pstate, BINOP_MUL);
4250 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4252 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4253 write_exp_elt_type (&p->pstate,
4254 lookup_pointer_type (p->arg_type));
4255 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4257 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4267 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4271 i386_stap_parse_special_token (struct gdbarch *gdbarch,
4272 struct stap_parse_info *p)
4274 /* In order to parse special tokens, we use a state-machine that go
4275 through every known token and try to get a match. */
4279 THREE_ARG_DISPLACEMENT,
4284 current_state = TRIPLET;
4286 /* The special tokens to be parsed here are:
4288 - `register base + (register index * size) + offset', as represented
4289 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4291 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4292 `*(-8 + 3 - 1 + (void *) $eax)'. */
4294 while (current_state != DONE)
4296 switch (current_state)
4299 if (i386_stap_parse_special_token_triplet (gdbarch, p))
4303 case THREE_ARG_DISPLACEMENT:
4304 if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p))
4309 /* Advancing to the next state. */
4318 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always
4319 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */
4322 i386_gnu_triplet_regexp (struct gdbarch *gdbarch)
4324 return "(x86_64|i.86)";
4332 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4334 static const char *const stap_integer_prefixes[] = { "$", NULL };
4335 static const char *const stap_register_prefixes[] = { "%", NULL };
4336 static const char *const stap_register_indirection_prefixes[] = { "(",
4338 static const char *const stap_register_indirection_suffixes[] = { ")",
4341 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4342 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4344 /* Registering SystemTap handlers. */
4345 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
4346 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
4347 set_gdbarch_stap_register_indirection_prefixes (gdbarch,
4348 stap_register_indirection_prefixes);
4349 set_gdbarch_stap_register_indirection_suffixes (gdbarch,
4350 stap_register_indirection_suffixes);
4351 set_gdbarch_stap_is_single_operand (gdbarch,
4352 i386_stap_is_single_operand);
4353 set_gdbarch_stap_parse_special_token (gdbarch,
4354 i386_stap_parse_special_token);
4356 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
4359 /* System V Release 4 (SVR4). */
4362 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4364 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4366 /* System V Release 4 uses ELF. */
4367 i386_elf_init_abi (info, gdbarch);
4369 /* System V Release 4 has shared libraries. */
4370 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
4372 tdep->sigtramp_p = i386_svr4_sigtramp_p;
4373 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
4374 tdep->sc_pc_offset = 36 + 14 * 4;
4375 tdep->sc_sp_offset = 36 + 17 * 4;
4377 tdep->jb_pc_offset = 20;
4383 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4385 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4387 /* DJGPP doesn't have any special frames for signal handlers. */
4388 tdep->sigtramp_p = NULL;
4390 tdep->jb_pc_offset = 36;
4392 /* DJGPP does not support the SSE registers. */
4393 if (! tdesc_has_registers (info.target_desc))
4394 tdep->tdesc = tdesc_i386_mmx;
4396 /* Native compiler is GCC, which uses the SVR4 register numbering
4397 even in COFF and STABS. See the comment in i386_gdbarch_init,
4398 before the calls to set_gdbarch_stab_reg_to_regnum and
4399 set_gdbarch_sdb_reg_to_regnum. */
4400 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4401 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4403 set_gdbarch_has_dos_based_file_system (gdbarch, 1);
4405 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
4409 /* i386 register groups. In addition to the normal groups, add "mmx"
4412 static struct reggroup *i386_sse_reggroup;
4413 static struct reggroup *i386_mmx_reggroup;
4416 i386_init_reggroups (void)
4418 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
4419 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
4423 i386_add_reggroups (struct gdbarch *gdbarch)
4425 reggroup_add (gdbarch, i386_sse_reggroup);
4426 reggroup_add (gdbarch, i386_mmx_reggroup);
4427 reggroup_add (gdbarch, general_reggroup);
4428 reggroup_add (gdbarch, float_reggroup);
4429 reggroup_add (gdbarch, all_reggroup);
4430 reggroup_add (gdbarch, save_reggroup);
4431 reggroup_add (gdbarch, restore_reggroup);
4432 reggroup_add (gdbarch, vector_reggroup);
4433 reggroup_add (gdbarch, system_reggroup);
4437 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
4438 struct reggroup *group)
4440 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4441 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
4442 ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p,
4443 bndr_regnum_p, bnd_regnum_p, k_regnum_p, zmm_regnum_p, zmmh_regnum_p,
4444 zmm_avx512_regnum_p, mpx_ctrl_regnum_p, xmm_avx512_regnum_p,
4445 avx512_p, avx_p, sse_p;
4447 /* Don't include pseudo registers, except for MMX, in any register
4449 if (i386_byte_regnum_p (gdbarch, regnum))
4452 if (i386_word_regnum_p (gdbarch, regnum))
4455 if (i386_dword_regnum_p (gdbarch, regnum))
4458 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
4459 if (group == i386_mmx_reggroup)
4460 return mmx_regnum_p;
4462 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
4463 xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum);
4464 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
4465 if (group == i386_sse_reggroup)
4466 return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p;
4468 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
4469 ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum);
4470 zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum);
4472 avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4473 == X86_XSTATE_AVX512_MASK);
4474 avx_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4475 == X86_XSTATE_AVX_MASK) && !avx512_p;
4476 sse_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4477 == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p;
4479 if (group == vector_reggroup)
4480 return (mmx_regnum_p
4481 || (zmm_regnum_p && avx512_p)
4482 || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p)
4483 || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p)
4486 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
4487 || i386_fpc_regnum_p (gdbarch, regnum));
4488 if (group == float_reggroup)
4491 /* For "info reg all", don't include upper YMM registers nor XMM
4492 registers when AVX is supported. */
4493 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
4494 ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum);
4495 zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum);
4496 if (group == all_reggroup
4497 && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p)
4498 || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p)
4500 || ymmh_avx512_regnum_p
4504 bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum);
4505 if (group == all_reggroup
4506 && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4507 return bnd_regnum_p;
4509 bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum);
4510 if (group == all_reggroup
4511 && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4514 mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum);
4515 if (group == all_reggroup
4516 && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4517 return mpx_ctrl_regnum_p;
4519 if (group == general_reggroup)
4520 return (!fp_regnum_p
4524 && !xmm_avx512_regnum_p
4527 && !ymm_avx512_regnum_p
4528 && !ymmh_avx512_regnum_p
4531 && !mpx_ctrl_regnum_p
4535 return default_register_reggroup_p (gdbarch, regnum, group);
4539 /* Get the ARGIth function argument for the current function. */
4542 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
4545 struct gdbarch *gdbarch = get_frame_arch (frame);
4546 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4547 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
4548 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
4551 #define PREFIX_REPZ 0x01
4552 #define PREFIX_REPNZ 0x02
4553 #define PREFIX_LOCK 0x04
4554 #define PREFIX_DATA 0x08
4555 #define PREFIX_ADDR 0x10
4567 /* i386 arith/logic operations */
4580 struct i386_record_s
4582 struct gdbarch *gdbarch;
4583 struct regcache *regcache;
4584 CORE_ADDR orig_addr;
4590 uint8_t mod, reg, rm;
4599 /* Parse the "modrm" part of the memory address irp->addr points at.
4600 Returns -1 if something goes wrong, 0 otherwise. */
4603 i386_record_modrm (struct i386_record_s *irp)
4605 struct gdbarch *gdbarch = irp->gdbarch;
4607 if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1))
4611 irp->mod = (irp->modrm >> 6) & 3;
4612 irp->reg = (irp->modrm >> 3) & 7;
4613 irp->rm = irp->modrm & 7;
4618 /* Extract the memory address that the current instruction writes to,
4619 and return it in *ADDR. Return -1 if something goes wrong. */
4622 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
4624 struct gdbarch *gdbarch = irp->gdbarch;
4625 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4630 if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM])
4637 uint8_t base = irp->rm;
4642 if (record_read_memory (gdbarch, irp->addr, &byte, 1))
4645 scale = (byte >> 6) & 3;
4646 index = ((byte >> 3) & 7) | irp->rex_x;
4654 if ((base & 7) == 5)
4657 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4660 *addr = extract_signed_integer (buf, 4, byte_order);
4661 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
4662 *addr += irp->addr + irp->rip_offset;
4666 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4669 *addr = (int8_t) buf[0];
4672 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4674 *addr = extract_signed_integer (buf, 4, byte_order);
4682 if (base == 4 && irp->popl_esp_hack)
4683 *addr += irp->popl_esp_hack;
4684 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
4687 if (irp->aflag == 2)
4692 *addr = (uint32_t) (offset64 + *addr);
4694 if (havesib && (index != 4 || scale != 0))
4696 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
4698 if (irp->aflag == 2)
4699 *addr += offset64 << scale;
4701 *addr = (uint32_t) (*addr + (offset64 << scale));
4706 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4707 address from 32-bit to 64-bit. */
4708 *addr = (uint32_t) *addr;
4719 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4722 *addr = extract_signed_integer (buf, 2, byte_order);
4728 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4731 *addr = (int8_t) buf[0];
4734 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4737 *addr = extract_signed_integer (buf, 2, byte_order);
4744 regcache_raw_read_unsigned (irp->regcache,
4745 irp->regmap[X86_RECORD_REBX_REGNUM],
4747 *addr = (uint32_t) (*addr + offset64);
4748 regcache_raw_read_unsigned (irp->regcache,
4749 irp->regmap[X86_RECORD_RESI_REGNUM],
4751 *addr = (uint32_t) (*addr + offset64);
4754 regcache_raw_read_unsigned (irp->regcache,
4755 irp->regmap[X86_RECORD_REBX_REGNUM],
4757 *addr = (uint32_t) (*addr + offset64);
4758 regcache_raw_read_unsigned (irp->regcache,
4759 irp->regmap[X86_RECORD_REDI_REGNUM],
4761 *addr = (uint32_t) (*addr + offset64);
4764 regcache_raw_read_unsigned (irp->regcache,
4765 irp->regmap[X86_RECORD_REBP_REGNUM],
4767 *addr = (uint32_t) (*addr + offset64);
4768 regcache_raw_read_unsigned (irp->regcache,
4769 irp->regmap[X86_RECORD_RESI_REGNUM],
4771 *addr = (uint32_t) (*addr + offset64);
4774 regcache_raw_read_unsigned (irp->regcache,
4775 irp->regmap[X86_RECORD_REBP_REGNUM],
4777 *addr = (uint32_t) (*addr + offset64);
4778 regcache_raw_read_unsigned (irp->regcache,
4779 irp->regmap[X86_RECORD_REDI_REGNUM],
4781 *addr = (uint32_t) (*addr + offset64);
4784 regcache_raw_read_unsigned (irp->regcache,
4785 irp->regmap[X86_RECORD_RESI_REGNUM],
4787 *addr = (uint32_t) (*addr + offset64);
4790 regcache_raw_read_unsigned (irp->regcache,
4791 irp->regmap[X86_RECORD_REDI_REGNUM],
4793 *addr = (uint32_t) (*addr + offset64);
4796 regcache_raw_read_unsigned (irp->regcache,
4797 irp->regmap[X86_RECORD_REBP_REGNUM],
4799 *addr = (uint32_t) (*addr + offset64);
4802 regcache_raw_read_unsigned (irp->regcache,
4803 irp->regmap[X86_RECORD_REBX_REGNUM],
4805 *addr = (uint32_t) (*addr + offset64);
4815 /* Record the address and contents of the memory that will be changed
4816 by the current instruction. Return -1 if something goes wrong, 0
4820 i386_record_lea_modrm (struct i386_record_s *irp)
4822 struct gdbarch *gdbarch = irp->gdbarch;
4825 if (irp->override >= 0)
4827 if (record_full_memory_query)
4831 target_terminal_ours ();
4833 Process record ignores the memory change of instruction at address %s\n\
4834 because it can't get the value of the segment register.\n\
4835 Do you want to stop the program?"),
4836 paddress (gdbarch, irp->orig_addr));
4837 target_terminal_inferior ();
4845 if (i386_record_lea_modrm_addr (irp, &addr))
4848 if (record_full_arch_list_add_mem (addr, 1 << irp->ot))
4854 /* Record the effects of a push operation. Return -1 if something
4855 goes wrong, 0 otherwise. */
4858 i386_record_push (struct i386_record_s *irp, int size)
4862 if (record_full_arch_list_add_reg (irp->regcache,
4863 irp->regmap[X86_RECORD_RESP_REGNUM]))
4865 regcache_raw_read_unsigned (irp->regcache,
4866 irp->regmap[X86_RECORD_RESP_REGNUM],
4868 if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size))
4875 /* Defines contents to record. */
4876 #define I386_SAVE_FPU_REGS 0xfffd
4877 #define I386_SAVE_FPU_ENV 0xfffe
4878 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4880 /* Record the values of the floating point registers which will be
4881 changed by the current instruction. Returns -1 if something is
4882 wrong, 0 otherwise. */
4884 static int i386_record_floats (struct gdbarch *gdbarch,
4885 struct i386_record_s *ir,
4888 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4891 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4892 happen. Currently we store st0-st7 registers, but we need not store all
4893 registers all the time, in future we use ftag register and record only
4894 those who are not marked as an empty. */
4896 if (I386_SAVE_FPU_REGS == iregnum)
4898 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
4900 if (record_full_arch_list_add_reg (ir->regcache, i))
4904 else if (I386_SAVE_FPU_ENV == iregnum)
4906 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4908 if (record_full_arch_list_add_reg (ir->regcache, i))
4912 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
4914 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4916 if (record_full_arch_list_add_reg (ir->regcache, i))
4920 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
4921 (iregnum <= I387_FOP_REGNUM (tdep)))
4923 if (record_full_arch_list_add_reg (ir->regcache,iregnum))
4928 /* Parameter error. */
4931 if(I386_SAVE_FPU_ENV != iregnum)
4933 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4935 if (record_full_arch_list_add_reg (ir->regcache, i))
4942 /* Parse the current instruction, and record the values of the
4943 registers and memory that will be changed by the current
4944 instruction. Returns -1 if something goes wrong, 0 otherwise. */
4946 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
4947 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
4950 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
4951 CORE_ADDR input_addr)
4953 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4959 gdb_byte buf[MAX_REGISTER_SIZE];
4960 struct i386_record_s ir;
4961 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4965 memset (&ir, 0, sizeof (struct i386_record_s));
4966 ir.regcache = regcache;
4967 ir.addr = input_addr;
4968 ir.orig_addr = input_addr;
4972 ir.popl_esp_hack = 0;
4973 ir.regmap = tdep->record_regmap;
4974 ir.gdbarch = gdbarch;
4976 if (record_debug > 1)
4977 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
4979 paddress (gdbarch, ir.addr));
4984 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
4987 switch (opcode8) /* Instruction prefixes */
4989 case REPE_PREFIX_OPCODE:
4990 prefixes |= PREFIX_REPZ;
4992 case REPNE_PREFIX_OPCODE:
4993 prefixes |= PREFIX_REPNZ;
4995 case LOCK_PREFIX_OPCODE:
4996 prefixes |= PREFIX_LOCK;
4998 case CS_PREFIX_OPCODE:
4999 ir.override = X86_RECORD_CS_REGNUM;
5001 case SS_PREFIX_OPCODE:
5002 ir.override = X86_RECORD_SS_REGNUM;
5004 case DS_PREFIX_OPCODE:
5005 ir.override = X86_RECORD_DS_REGNUM;
5007 case ES_PREFIX_OPCODE:
5008 ir.override = X86_RECORD_ES_REGNUM;
5010 case FS_PREFIX_OPCODE:
5011 ir.override = X86_RECORD_FS_REGNUM;
5013 case GS_PREFIX_OPCODE:
5014 ir.override = X86_RECORD_GS_REGNUM;
5016 case DATA_PREFIX_OPCODE:
5017 prefixes |= PREFIX_DATA;
5019 case ADDR_PREFIX_OPCODE:
5020 prefixes |= PREFIX_ADDR;
5022 case 0x40: /* i386 inc %eax */
5023 case 0x41: /* i386 inc %ecx */
5024 case 0x42: /* i386 inc %edx */
5025 case 0x43: /* i386 inc %ebx */
5026 case 0x44: /* i386 inc %esp */
5027 case 0x45: /* i386 inc %ebp */
5028 case 0x46: /* i386 inc %esi */
5029 case 0x47: /* i386 inc %edi */
5030 case 0x48: /* i386 dec %eax */
5031 case 0x49: /* i386 dec %ecx */
5032 case 0x4a: /* i386 dec %edx */
5033 case 0x4b: /* i386 dec %ebx */
5034 case 0x4c: /* i386 dec %esp */
5035 case 0x4d: /* i386 dec %ebp */
5036 case 0x4e: /* i386 dec %esi */
5037 case 0x4f: /* i386 dec %edi */
5038 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
5041 rex_w = (opcode8 >> 3) & 1;
5042 rex_r = (opcode8 & 0x4) << 1;
5043 ir.rex_x = (opcode8 & 0x2) << 2;
5044 ir.rex_b = (opcode8 & 0x1) << 3;
5046 else /* 32 bit target */
5055 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
5061 if (prefixes & PREFIX_DATA)
5064 if (prefixes & PREFIX_ADDR)
5066 else if (ir.regmap[X86_RECORD_R8_REGNUM])
5069 /* Now check op code. */
5070 opcode = (uint32_t) opcode8;
5075 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5078 opcode = (uint32_t) opcode8 | 0x0f00;
5082 case 0x00: /* arith & logic */
5130 if (((opcode >> 3) & 7) != OP_CMPL)
5132 if ((opcode & 1) == 0)
5135 ir.ot = ir.dflag + OT_WORD;
5137 switch ((opcode >> 1) & 3)
5139 case 0: /* OP Ev, Gv */
5140 if (i386_record_modrm (&ir))
5144 if (i386_record_lea_modrm (&ir))
5150 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5152 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5155 case 1: /* OP Gv, Ev */
5156 if (i386_record_modrm (&ir))
5159 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5161 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5163 case 2: /* OP A, Iv */
5164 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5168 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5171 case 0x80: /* GRP1 */
5175 if (i386_record_modrm (&ir))
5178 if (ir.reg != OP_CMPL)
5180 if ((opcode & 1) == 0)
5183 ir.ot = ir.dflag + OT_WORD;
5190 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5191 if (i386_record_lea_modrm (&ir))
5195 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5197 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5200 case 0x40: /* inc */
5209 case 0x48: /* dec */
5218 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7);
5219 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5222 case 0xf6: /* GRP3 */
5224 if ((opcode & 1) == 0)
5227 ir.ot = ir.dflag + OT_WORD;
5228 if (i386_record_modrm (&ir))
5231 if (ir.mod != 3 && ir.reg == 0)
5232 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5237 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5243 if (i386_record_lea_modrm (&ir))
5249 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5251 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5253 if (ir.reg == 3) /* neg */
5254 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5260 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5261 if (ir.ot != OT_BYTE)
5262 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5263 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5267 opcode = opcode << 8 | ir.modrm;
5273 case 0xfe: /* GRP4 */
5274 case 0xff: /* GRP5 */
5275 if (i386_record_modrm (&ir))
5277 if (ir.reg >= 2 && opcode == 0xfe)
5280 opcode = opcode << 8 | ir.modrm;
5287 if ((opcode & 1) == 0)
5290 ir.ot = ir.dflag + OT_WORD;
5293 if (i386_record_lea_modrm (&ir))
5299 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5301 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5303 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5306 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5308 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5310 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5313 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5314 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5316 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5320 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5323 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5325 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5330 opcode = opcode << 8 | ir.modrm;
5336 case 0x84: /* test */
5340 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5343 case 0x98: /* CWDE/CBW */
5344 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5347 case 0x99: /* CDQ/CWD */
5348 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5349 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5352 case 0x0faf: /* imul */
5355 ir.ot = ir.dflag + OT_WORD;
5356 if (i386_record_modrm (&ir))
5359 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5360 else if (opcode == 0x6b)
5363 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5365 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5366 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5369 case 0x0fc0: /* xadd */
5371 if ((opcode & 1) == 0)
5374 ir.ot = ir.dflag + OT_WORD;
5375 if (i386_record_modrm (&ir))
5380 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5382 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5383 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5385 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5389 if (i386_record_lea_modrm (&ir))
5391 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5393 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5395 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5398 case 0x0fb0: /* cmpxchg */
5400 if ((opcode & 1) == 0)
5403 ir.ot = ir.dflag + OT_WORD;
5404 if (i386_record_modrm (&ir))
5409 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5410 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5412 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5416 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5417 if (i386_record_lea_modrm (&ir))
5420 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5423 case 0x0fc7: /* cmpxchg8b */
5424 if (i386_record_modrm (&ir))
5429 opcode = opcode << 8 | ir.modrm;
5432 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5433 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5434 if (i386_record_lea_modrm (&ir))
5436 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5439 case 0x50: /* push */
5449 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5451 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5455 case 0x06: /* push es */
5456 case 0x0e: /* push cs */
5457 case 0x16: /* push ss */
5458 case 0x1e: /* push ds */
5459 if (ir.regmap[X86_RECORD_R8_REGNUM])
5464 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5468 case 0x0fa0: /* push fs */
5469 case 0x0fa8: /* push gs */
5470 if (ir.regmap[X86_RECORD_R8_REGNUM])
5475 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5479 case 0x60: /* pusha */
5480 if (ir.regmap[X86_RECORD_R8_REGNUM])
5485 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
5489 case 0x58: /* pop */
5497 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5498 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5501 case 0x61: /* popa */
5502 if (ir.regmap[X86_RECORD_R8_REGNUM])
5507 for (regnum = X86_RECORD_REAX_REGNUM;
5508 regnum <= X86_RECORD_REDI_REGNUM;
5510 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5513 case 0x8f: /* pop */
5514 if (ir.regmap[X86_RECORD_R8_REGNUM])
5515 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
5517 ir.ot = ir.dflag + OT_WORD;
5518 if (i386_record_modrm (&ir))
5521 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5524 ir.popl_esp_hack = 1 << ir.ot;
5525 if (i386_record_lea_modrm (&ir))
5528 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5531 case 0xc8: /* enter */
5532 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5533 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5535 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5539 case 0xc9: /* leave */
5540 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5541 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5544 case 0x07: /* pop es */
5545 if (ir.regmap[X86_RECORD_R8_REGNUM])
5550 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5551 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
5552 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5555 case 0x17: /* pop ss */
5556 if (ir.regmap[X86_RECORD_R8_REGNUM])
5561 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5562 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
5563 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5566 case 0x1f: /* pop ds */
5567 if (ir.regmap[X86_RECORD_R8_REGNUM])
5572 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5573 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
5574 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5577 case 0x0fa1: /* pop fs */
5578 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5579 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
5580 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5583 case 0x0fa9: /* pop gs */
5584 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5585 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
5586 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5589 case 0x88: /* mov */
5593 if ((opcode & 1) == 0)
5596 ir.ot = ir.dflag + OT_WORD;
5598 if (i386_record_modrm (&ir))
5603 if (opcode == 0xc6 || opcode == 0xc7)
5604 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5605 if (i386_record_lea_modrm (&ir))
5610 if (opcode == 0xc6 || opcode == 0xc7)
5612 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5614 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5618 case 0x8a: /* mov */
5620 if ((opcode & 1) == 0)
5623 ir.ot = ir.dflag + OT_WORD;
5624 if (i386_record_modrm (&ir))
5627 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5629 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5632 case 0x8c: /* mov seg */
5633 if (i386_record_modrm (&ir))
5638 opcode = opcode << 8 | ir.modrm;
5643 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5647 if (i386_record_lea_modrm (&ir))
5652 case 0x8e: /* mov seg */
5653 if (i386_record_modrm (&ir))
5658 regnum = X86_RECORD_ES_REGNUM;
5661 regnum = X86_RECORD_SS_REGNUM;
5664 regnum = X86_RECORD_DS_REGNUM;
5667 regnum = X86_RECORD_FS_REGNUM;
5670 regnum = X86_RECORD_GS_REGNUM;
5674 opcode = opcode << 8 | ir.modrm;
5678 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5679 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5682 case 0x0fb6: /* movzbS */
5683 case 0x0fb7: /* movzwS */
5684 case 0x0fbe: /* movsbS */
5685 case 0x0fbf: /* movswS */
5686 if (i386_record_modrm (&ir))
5688 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5691 case 0x8d: /* lea */
5692 if (i386_record_modrm (&ir))
5697 opcode = opcode << 8 | ir.modrm;
5702 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5704 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5707 case 0xa0: /* mov EAX */
5710 case 0xd7: /* xlat */
5711 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5714 case 0xa2: /* mov EAX */
5716 if (ir.override >= 0)
5718 if (record_full_memory_query)
5722 target_terminal_ours ();
5724 Process record ignores the memory change of instruction at address %s\n\
5725 because it can't get the value of the segment register.\n\
5726 Do you want to stop the program?"),
5727 paddress (gdbarch, ir.orig_addr));
5728 target_terminal_inferior ();
5735 if ((opcode & 1) == 0)
5738 ir.ot = ir.dflag + OT_WORD;
5741 if (record_read_memory (gdbarch, ir.addr, buf, 8))
5744 addr = extract_unsigned_integer (buf, 8, byte_order);
5748 if (record_read_memory (gdbarch, ir.addr, buf, 4))
5751 addr = extract_unsigned_integer (buf, 4, byte_order);
5755 if (record_read_memory (gdbarch, ir.addr, buf, 2))
5758 addr = extract_unsigned_integer (buf, 2, byte_order);
5760 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
5765 case 0xb0: /* mov R, Ib */
5773 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
5774 ? ((opcode & 0x7) | ir.rex_b)
5775 : ((opcode & 0x7) & 0x3));
5778 case 0xb8: /* mov R, Iv */
5786 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5789 case 0x91: /* xchg R, EAX */
5796 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5797 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7);
5800 case 0x86: /* xchg Ev, Gv */
5802 if ((opcode & 1) == 0)
5805 ir.ot = ir.dflag + OT_WORD;
5806 if (i386_record_modrm (&ir))
5811 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5813 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5817 if (i386_record_lea_modrm (&ir))
5821 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5823 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5826 case 0xc4: /* les Gv */
5827 case 0xc5: /* lds Gv */
5828 if (ir.regmap[X86_RECORD_R8_REGNUM])
5834 case 0x0fb2: /* lss Gv */
5835 case 0x0fb4: /* lfs Gv */
5836 case 0x0fb5: /* lgs Gv */
5837 if (i386_record_modrm (&ir))
5845 opcode = opcode << 8 | ir.modrm;
5850 case 0xc4: /* les Gv */
5851 regnum = X86_RECORD_ES_REGNUM;
5853 case 0xc5: /* lds Gv */
5854 regnum = X86_RECORD_DS_REGNUM;
5856 case 0x0fb2: /* lss Gv */
5857 regnum = X86_RECORD_SS_REGNUM;
5859 case 0x0fb4: /* lfs Gv */
5860 regnum = X86_RECORD_FS_REGNUM;
5862 case 0x0fb5: /* lgs Gv */
5863 regnum = X86_RECORD_GS_REGNUM;
5866 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5867 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5868 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5871 case 0xc0: /* shifts */
5877 if ((opcode & 1) == 0)
5880 ir.ot = ir.dflag + OT_WORD;
5881 if (i386_record_modrm (&ir))
5883 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
5885 if (i386_record_lea_modrm (&ir))
5891 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5893 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5895 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5902 if (i386_record_modrm (&ir))
5906 if (record_full_arch_list_add_reg (ir.regcache, ir.rm))
5911 if (i386_record_lea_modrm (&ir))
5916 case 0xd8: /* Floats. */
5924 if (i386_record_modrm (&ir))
5926 ir.reg |= ((opcode & 7) << 3);
5932 if (i386_record_lea_modrm_addr (&ir, &addr64))
5940 /* For fcom, ficom nothing to do. */
5946 /* For fcomp, ficomp pop FPU stack, store all. */
5947 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5974 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5975 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5976 of code, always affects st(0) register. */
5977 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6001 /* Handling fld, fild. */
6002 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6006 switch (ir.reg >> 4)
6009 if (record_full_arch_list_add_mem (addr64, 4))
6013 if (record_full_arch_list_add_mem (addr64, 8))
6019 if (record_full_arch_list_add_mem (addr64, 2))
6025 switch (ir.reg >> 4)
6028 if (record_full_arch_list_add_mem (addr64, 4))
6030 if (3 == (ir.reg & 7))
6032 /* For fstp m32fp. */
6033 if (i386_record_floats (gdbarch, &ir,
6034 I386_SAVE_FPU_REGS))
6039 if (record_full_arch_list_add_mem (addr64, 4))
6041 if ((3 == (ir.reg & 7))
6042 || (5 == (ir.reg & 7))
6043 || (7 == (ir.reg & 7)))
6045 /* For fstp insn. */
6046 if (i386_record_floats (gdbarch, &ir,
6047 I386_SAVE_FPU_REGS))
6052 if (record_full_arch_list_add_mem (addr64, 8))
6054 if (3 == (ir.reg & 7))
6056 /* For fstp m64fp. */
6057 if (i386_record_floats (gdbarch, &ir,
6058 I386_SAVE_FPU_REGS))
6063 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
6065 /* For fistp, fbld, fild, fbstp. */
6066 if (i386_record_floats (gdbarch, &ir,
6067 I386_SAVE_FPU_REGS))
6072 if (record_full_arch_list_add_mem (addr64, 2))
6081 if (i386_record_floats (gdbarch, &ir,
6082 I386_SAVE_FPU_ENV_REG_STACK))
6087 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
6092 if (i386_record_floats (gdbarch, &ir,
6093 I386_SAVE_FPU_ENV_REG_STACK))
6099 if (record_full_arch_list_add_mem (addr64, 28))
6104 if (record_full_arch_list_add_mem (addr64, 14))
6110 if (record_full_arch_list_add_mem (addr64, 2))
6112 /* Insn fstp, fbstp. */
6113 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6118 if (record_full_arch_list_add_mem (addr64, 10))
6124 if (record_full_arch_list_add_mem (addr64, 28))
6130 if (record_full_arch_list_add_mem (addr64, 14))
6134 if (record_full_arch_list_add_mem (addr64, 80))
6137 if (i386_record_floats (gdbarch, &ir,
6138 I386_SAVE_FPU_ENV_REG_STACK))
6142 if (record_full_arch_list_add_mem (addr64, 8))
6145 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6150 opcode = opcode << 8 | ir.modrm;
6155 /* Opcode is an extension of modR/M byte. */
6161 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6165 if (0x0c == (ir.modrm >> 4))
6167 if ((ir.modrm & 0x0f) <= 7)
6169 if (i386_record_floats (gdbarch, &ir,
6170 I386_SAVE_FPU_REGS))
6175 if (i386_record_floats (gdbarch, &ir,
6176 I387_ST0_REGNUM (tdep)))
6178 /* If only st(0) is changing, then we have already
6180 if ((ir.modrm & 0x0f) - 0x08)
6182 if (i386_record_floats (gdbarch, &ir,
6183 I387_ST0_REGNUM (tdep) +
6184 ((ir.modrm & 0x0f) - 0x08)))
6202 if (i386_record_floats (gdbarch, &ir,
6203 I387_ST0_REGNUM (tdep)))
6221 if (i386_record_floats (gdbarch, &ir,
6222 I386_SAVE_FPU_REGS))
6226 if (i386_record_floats (gdbarch, &ir,
6227 I387_ST0_REGNUM (tdep)))
6229 if (i386_record_floats (gdbarch, &ir,
6230 I387_ST0_REGNUM (tdep) + 1))
6237 if (0xe9 == ir.modrm)
6239 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6242 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6244 if (i386_record_floats (gdbarch, &ir,
6245 I387_ST0_REGNUM (tdep)))
6247 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6249 if (i386_record_floats (gdbarch, &ir,
6250 I387_ST0_REGNUM (tdep) +
6254 else if ((ir.modrm & 0x0f) - 0x08)
6256 if (i386_record_floats (gdbarch, &ir,
6257 I387_ST0_REGNUM (tdep) +
6258 ((ir.modrm & 0x0f) - 0x08)))
6264 if (0xe3 == ir.modrm)
6266 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
6269 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6271 if (i386_record_floats (gdbarch, &ir,
6272 I387_ST0_REGNUM (tdep)))
6274 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6276 if (i386_record_floats (gdbarch, &ir,
6277 I387_ST0_REGNUM (tdep) +
6281 else if ((ir.modrm & 0x0f) - 0x08)
6283 if (i386_record_floats (gdbarch, &ir,
6284 I387_ST0_REGNUM (tdep) +
6285 ((ir.modrm & 0x0f) - 0x08)))
6291 if ((0x0c == ir.modrm >> 4)
6292 || (0x0d == ir.modrm >> 4)
6293 || (0x0f == ir.modrm >> 4))
6295 if ((ir.modrm & 0x0f) <= 7)
6297 if (i386_record_floats (gdbarch, &ir,
6298 I387_ST0_REGNUM (tdep) +
6304 if (i386_record_floats (gdbarch, &ir,
6305 I387_ST0_REGNUM (tdep) +
6306 ((ir.modrm & 0x0f) - 0x08)))
6312 if (0x0c == ir.modrm >> 4)
6314 if (i386_record_floats (gdbarch, &ir,
6315 I387_FTAG_REGNUM (tdep)))
6318 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6320 if ((ir.modrm & 0x0f) <= 7)
6322 if (i386_record_floats (gdbarch, &ir,
6323 I387_ST0_REGNUM (tdep) +
6329 if (i386_record_floats (gdbarch, &ir,
6330 I386_SAVE_FPU_REGS))
6336 if ((0x0c == ir.modrm >> 4)
6337 || (0x0e == ir.modrm >> 4)
6338 || (0x0f == ir.modrm >> 4)
6339 || (0xd9 == ir.modrm))
6341 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6346 if (0xe0 == ir.modrm)
6348 if (record_full_arch_list_add_reg (ir.regcache,
6352 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6354 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6362 case 0xa4: /* movsS */
6364 case 0xaa: /* stosS */
6366 case 0x6c: /* insS */
6368 regcache_raw_read_unsigned (ir.regcache,
6369 ir.regmap[X86_RECORD_RECX_REGNUM],
6375 if ((opcode & 1) == 0)
6378 ir.ot = ir.dflag + OT_WORD;
6379 regcache_raw_read_unsigned (ir.regcache,
6380 ir.regmap[X86_RECORD_REDI_REGNUM],
6383 regcache_raw_read_unsigned (ir.regcache,
6384 ir.regmap[X86_RECORD_ES_REGNUM],
6386 regcache_raw_read_unsigned (ir.regcache,
6387 ir.regmap[X86_RECORD_DS_REGNUM],
6389 if (ir.aflag && (es != ds))
6391 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6392 if (record_full_memory_query)
6396 target_terminal_ours ();
6398 Process record ignores the memory change of instruction at address %s\n\
6399 because it can't get the value of the segment register.\n\
6400 Do you want to stop the program?"),
6401 paddress (gdbarch, ir.orig_addr));
6402 target_terminal_inferior ();
6409 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
6413 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6414 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6415 if (opcode == 0xa4 || opcode == 0xa5)
6416 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6417 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6418 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6422 case 0xa6: /* cmpsS */
6424 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6425 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6426 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6427 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6428 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6431 case 0xac: /* lodsS */
6433 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6434 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6435 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6436 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6437 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6440 case 0xae: /* scasS */
6442 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6443 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6444 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6445 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6448 case 0x6e: /* outsS */
6450 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6451 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6452 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6453 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6456 case 0xe4: /* port I/O */
6460 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6461 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6471 case 0xc2: /* ret im */
6472 case 0xc3: /* ret */
6473 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6474 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6477 case 0xca: /* lret im */
6478 case 0xcb: /* lret */
6479 case 0xcf: /* iret */
6480 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6481 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6482 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6485 case 0xe8: /* call im */
6486 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6488 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6492 case 0x9a: /* lcall im */
6493 if (ir.regmap[X86_RECORD_R8_REGNUM])
6498 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6499 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6503 case 0xe9: /* jmp im */
6504 case 0xea: /* ljmp im */
6505 case 0xeb: /* jmp Jb */
6506 case 0x70: /* jcc Jb */
6522 case 0x0f80: /* jcc Jv */
6540 case 0x0f90: /* setcc Gv */
6556 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6558 if (i386_record_modrm (&ir))
6561 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
6565 if (i386_record_lea_modrm (&ir))
6570 case 0x0f40: /* cmov Gv, Ev */
6586 if (i386_record_modrm (&ir))
6589 if (ir.dflag == OT_BYTE)
6591 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
6595 case 0x9c: /* pushf */
6596 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6597 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6599 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6603 case 0x9d: /* popf */
6604 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6605 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6608 case 0x9e: /* sahf */
6609 if (ir.regmap[X86_RECORD_R8_REGNUM])
6615 case 0xf5: /* cmc */
6616 case 0xf8: /* clc */
6617 case 0xf9: /* stc */
6618 case 0xfc: /* cld */
6619 case 0xfd: /* std */
6620 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6623 case 0x9f: /* lahf */
6624 if (ir.regmap[X86_RECORD_R8_REGNUM])
6629 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6630 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6633 /* bit operations */
6634 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6635 ir.ot = ir.dflag + OT_WORD;
6636 if (i386_record_modrm (&ir))
6641 opcode = opcode << 8 | ir.modrm;
6647 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6650 if (i386_record_lea_modrm (&ir))
6654 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6657 case 0x0fa3: /* bt Gv, Ev */
6658 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6661 case 0x0fab: /* bts */
6662 case 0x0fb3: /* btr */
6663 case 0x0fbb: /* btc */
6664 ir.ot = ir.dflag + OT_WORD;
6665 if (i386_record_modrm (&ir))
6668 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6672 if (i386_record_lea_modrm_addr (&ir, &addr64))
6674 regcache_raw_read_unsigned (ir.regcache,
6675 ir.regmap[ir.reg | rex_r],
6680 addr64 += ((int16_t) addr >> 4) << 4;
6683 addr64 += ((int32_t) addr >> 5) << 5;
6686 addr64 += ((int64_t) addr >> 6) << 6;
6689 if (record_full_arch_list_add_mem (addr64, 1 << ir.ot))
6691 if (i386_record_lea_modrm (&ir))
6694 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6697 case 0x0fbc: /* bsf */
6698 case 0x0fbd: /* bsr */
6699 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6700 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6704 case 0x27: /* daa */
6705 case 0x2f: /* das */
6706 case 0x37: /* aaa */
6707 case 0x3f: /* aas */
6708 case 0xd4: /* aam */
6709 case 0xd5: /* aad */
6710 if (ir.regmap[X86_RECORD_R8_REGNUM])
6715 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6716 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6720 case 0x90: /* nop */
6721 if (prefixes & PREFIX_LOCK)
6728 case 0x9b: /* fwait */
6729 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
6731 opcode = (uint32_t) opcode8;
6737 case 0xcc: /* int3 */
6738 printf_unfiltered (_("Process record does not support instruction "
6745 case 0xcd: /* int */
6749 if (record_read_memory (gdbarch, ir.addr, &interrupt, 1))
6752 if (interrupt != 0x80
6753 || tdep->i386_intx80_record == NULL)
6755 printf_unfiltered (_("Process record does not support "
6756 "instruction int 0x%02x.\n"),
6761 ret = tdep->i386_intx80_record (ir.regcache);
6768 case 0xce: /* into */
6769 printf_unfiltered (_("Process record does not support "
6770 "instruction into.\n"));
6775 case 0xfa: /* cli */
6776 case 0xfb: /* sti */
6779 case 0x62: /* bound */
6780 printf_unfiltered (_("Process record does not support "
6781 "instruction bound.\n"));
6786 case 0x0fc8: /* bswap reg */
6794 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
6797 case 0xd6: /* salc */
6798 if (ir.regmap[X86_RECORD_R8_REGNUM])
6803 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6804 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6807 case 0xe0: /* loopnz */
6808 case 0xe1: /* loopz */
6809 case 0xe2: /* loop */
6810 case 0xe3: /* jecxz */
6811 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6812 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6815 case 0x0f30: /* wrmsr */
6816 printf_unfiltered (_("Process record does not support "
6817 "instruction wrmsr.\n"));
6822 case 0x0f32: /* rdmsr */
6823 printf_unfiltered (_("Process record does not support "
6824 "instruction rdmsr.\n"));
6829 case 0x0f31: /* rdtsc */
6830 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6831 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6834 case 0x0f34: /* sysenter */
6837 if (ir.regmap[X86_RECORD_R8_REGNUM])
6842 if (tdep->i386_sysenter_record == NULL)
6844 printf_unfiltered (_("Process record does not support "
6845 "instruction sysenter.\n"));
6849 ret = tdep->i386_sysenter_record (ir.regcache);
6855 case 0x0f35: /* sysexit */
6856 printf_unfiltered (_("Process record does not support "
6857 "instruction sysexit.\n"));
6862 case 0x0f05: /* syscall */
6865 if (tdep->i386_syscall_record == NULL)
6867 printf_unfiltered (_("Process record does not support "
6868 "instruction syscall.\n"));
6872 ret = tdep->i386_syscall_record (ir.regcache);
6878 case 0x0f07: /* sysret */
6879 printf_unfiltered (_("Process record does not support "
6880 "instruction sysret.\n"));
6885 case 0x0fa2: /* cpuid */
6886 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6887 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6888 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6889 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
6892 case 0xf4: /* hlt */
6893 printf_unfiltered (_("Process record does not support "
6894 "instruction hlt.\n"));
6900 if (i386_record_modrm (&ir))
6907 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6911 if (i386_record_lea_modrm (&ir))
6920 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6924 opcode = opcode << 8 | ir.modrm;
6931 if (i386_record_modrm (&ir))
6942 opcode = opcode << 8 | ir.modrm;
6945 if (ir.override >= 0)
6947 if (record_full_memory_query)
6951 target_terminal_ours ();
6953 Process record ignores the memory change of instruction at address %s\n\
6954 because it can't get the value of the segment register.\n\
6955 Do you want to stop the program?"),
6956 paddress (gdbarch, ir.orig_addr));
6957 target_terminal_inferior ();
6964 if (i386_record_lea_modrm_addr (&ir, &addr64))
6966 if (record_full_arch_list_add_mem (addr64, 2))
6969 if (ir.regmap[X86_RECORD_R8_REGNUM])
6971 if (record_full_arch_list_add_mem (addr64, 8))
6976 if (record_full_arch_list_add_mem (addr64, 4))
6987 case 0: /* monitor */
6990 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6994 opcode = opcode << 8 | ir.modrm;
7002 if (ir.override >= 0)
7004 if (record_full_memory_query)
7008 target_terminal_ours ();
7010 Process record ignores the memory change of instruction at address %s\n\
7011 because it can't get the value of the segment register.\n\
7012 Do you want to stop the program?"),
7013 paddress (gdbarch, ir.orig_addr));
7014 target_terminal_inferior ();
7023 if (i386_record_lea_modrm_addr (&ir, &addr64))
7025 if (record_full_arch_list_add_mem (addr64, 2))
7028 if (ir.regmap[X86_RECORD_R8_REGNUM])
7030 if (record_full_arch_list_add_mem (addr64, 8))
7035 if (record_full_arch_list_add_mem (addr64, 4))
7047 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7048 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7052 else if (ir.rm == 1)
7059 opcode = opcode << 8 | ir.modrm;
7066 if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
7072 if (i386_record_lea_modrm (&ir))
7075 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7078 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7080 case 7: /* invlpg */
7083 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
7084 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
7088 opcode = opcode << 8 | ir.modrm;
7093 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7097 opcode = opcode << 8 | ir.modrm;
7103 case 0x0f08: /* invd */
7104 case 0x0f09: /* wbinvd */
7107 case 0x63: /* arpl */
7108 if (i386_record_modrm (&ir))
7110 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
7112 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
7113 ? (ir.reg | rex_r) : ir.rm);
7117 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
7118 if (i386_record_lea_modrm (&ir))
7121 if (!ir.regmap[X86_RECORD_R8_REGNUM])
7122 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7125 case 0x0f02: /* lar */
7126 case 0x0f03: /* lsl */
7127 if (i386_record_modrm (&ir))
7129 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7130 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7134 if (i386_record_modrm (&ir))
7136 if (ir.mod == 3 && ir.reg == 3)
7139 opcode = opcode << 8 | ir.modrm;
7151 /* nop (multi byte) */
7154 case 0x0f20: /* mov reg, crN */
7155 case 0x0f22: /* mov crN, reg */
7156 if (i386_record_modrm (&ir))
7158 if ((ir.modrm & 0xc0) != 0xc0)
7161 opcode = opcode << 8 | ir.modrm;
7172 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7174 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7178 opcode = opcode << 8 | ir.modrm;
7184 case 0x0f21: /* mov reg, drN */
7185 case 0x0f23: /* mov drN, reg */
7186 if (i386_record_modrm (&ir))
7188 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
7189 || ir.reg == 5 || ir.reg >= 8)
7192 opcode = opcode << 8 | ir.modrm;
7196 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7198 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7201 case 0x0f06: /* clts */
7202 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7205 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7207 case 0x0f0d: /* 3DNow! prefetch */
7210 case 0x0f0e: /* 3DNow! femms */
7211 case 0x0f77: /* emms */
7212 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
7214 record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
7217 case 0x0f0f: /* 3DNow! data */
7218 if (i386_record_modrm (&ir))
7220 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7225 case 0x0c: /* 3DNow! pi2fw */
7226 case 0x0d: /* 3DNow! pi2fd */
7227 case 0x1c: /* 3DNow! pf2iw */
7228 case 0x1d: /* 3DNow! pf2id */
7229 case 0x8a: /* 3DNow! pfnacc */
7230 case 0x8e: /* 3DNow! pfpnacc */
7231 case 0x90: /* 3DNow! pfcmpge */
7232 case 0x94: /* 3DNow! pfmin */
7233 case 0x96: /* 3DNow! pfrcp */
7234 case 0x97: /* 3DNow! pfrsqrt */
7235 case 0x9a: /* 3DNow! pfsub */
7236 case 0x9e: /* 3DNow! pfadd */
7237 case 0xa0: /* 3DNow! pfcmpgt */
7238 case 0xa4: /* 3DNow! pfmax */
7239 case 0xa6: /* 3DNow! pfrcpit1 */
7240 case 0xa7: /* 3DNow! pfrsqit1 */
7241 case 0xaa: /* 3DNow! pfsubr */
7242 case 0xae: /* 3DNow! pfacc */
7243 case 0xb0: /* 3DNow! pfcmpeq */
7244 case 0xb4: /* 3DNow! pfmul */
7245 case 0xb6: /* 3DNow! pfrcpit2 */
7246 case 0xb7: /* 3DNow! pmulhrw */
7247 case 0xbb: /* 3DNow! pswapd */
7248 case 0xbf: /* 3DNow! pavgusb */
7249 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7250 goto no_support_3dnow_data;
7251 record_full_arch_list_add_reg (ir.regcache, ir.reg);
7255 no_support_3dnow_data:
7256 opcode = (opcode << 8) | opcode8;
7262 case 0x0faa: /* rsm */
7263 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7264 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7265 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
7266 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7267 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
7268 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
7269 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
7270 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
7271 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
7275 if (i386_record_modrm (&ir))
7279 case 0: /* fxsave */
7283 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7284 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
7286 if (record_full_arch_list_add_mem (tmpu64, 512))
7291 case 1: /* fxrstor */
7295 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7297 for (i = I387_MM0_REGNUM (tdep);
7298 i386_mmx_regnum_p (gdbarch, i); i++)
7299 record_full_arch_list_add_reg (ir.regcache, i);
7301 for (i = I387_XMM0_REGNUM (tdep);
7302 i386_xmm_regnum_p (gdbarch, i); i++)
7303 record_full_arch_list_add_reg (ir.regcache, i);
7305 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7306 record_full_arch_list_add_reg (ir.regcache,
7307 I387_MXCSR_REGNUM(tdep));
7309 for (i = I387_ST0_REGNUM (tdep);
7310 i386_fp_regnum_p (gdbarch, i); i++)
7311 record_full_arch_list_add_reg (ir.regcache, i);
7313 for (i = I387_FCTRL_REGNUM (tdep);
7314 i386_fpc_regnum_p (gdbarch, i); i++)
7315 record_full_arch_list_add_reg (ir.regcache, i);
7319 case 2: /* ldmxcsr */
7320 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7322 record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
7325 case 3: /* stmxcsr */
7327 if (i386_record_lea_modrm (&ir))
7331 case 5: /* lfence */
7332 case 6: /* mfence */
7333 case 7: /* sfence clflush */
7337 opcode = (opcode << 8) | ir.modrm;
7343 case 0x0fc3: /* movnti */
7344 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
7345 if (i386_record_modrm (&ir))
7350 if (i386_record_lea_modrm (&ir))
7354 /* Add prefix to opcode. */
7469 /* Mask out PREFIX_ADDR. */
7470 switch ((prefixes & ~PREFIX_ADDR))
7482 reswitch_prefix_add:
7490 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7493 opcode = (uint32_t) opcode8 | opcode << 8;
7494 goto reswitch_prefix_add;
7497 case 0x0f10: /* movups */
7498 case 0x660f10: /* movupd */
7499 case 0xf30f10: /* movss */
7500 case 0xf20f10: /* movsd */
7501 case 0x0f12: /* movlps */
7502 case 0x660f12: /* movlpd */
7503 case 0xf30f12: /* movsldup */
7504 case 0xf20f12: /* movddup */
7505 case 0x0f14: /* unpcklps */
7506 case 0x660f14: /* unpcklpd */
7507 case 0x0f15: /* unpckhps */
7508 case 0x660f15: /* unpckhpd */
7509 case 0x0f16: /* movhps */
7510 case 0x660f16: /* movhpd */
7511 case 0xf30f16: /* movshdup */
7512 case 0x0f28: /* movaps */
7513 case 0x660f28: /* movapd */
7514 case 0x0f2a: /* cvtpi2ps */
7515 case 0x660f2a: /* cvtpi2pd */
7516 case 0xf30f2a: /* cvtsi2ss */
7517 case 0xf20f2a: /* cvtsi2sd */
7518 case 0x0f2c: /* cvttps2pi */
7519 case 0x660f2c: /* cvttpd2pi */
7520 case 0x0f2d: /* cvtps2pi */
7521 case 0x660f2d: /* cvtpd2pi */
7522 case 0x660f3800: /* pshufb */
7523 case 0x660f3801: /* phaddw */
7524 case 0x660f3802: /* phaddd */
7525 case 0x660f3803: /* phaddsw */
7526 case 0x660f3804: /* pmaddubsw */
7527 case 0x660f3805: /* phsubw */
7528 case 0x660f3806: /* phsubd */
7529 case 0x660f3807: /* phsubsw */
7530 case 0x660f3808: /* psignb */
7531 case 0x660f3809: /* psignw */
7532 case 0x660f380a: /* psignd */
7533 case 0x660f380b: /* pmulhrsw */
7534 case 0x660f3810: /* pblendvb */
7535 case 0x660f3814: /* blendvps */
7536 case 0x660f3815: /* blendvpd */
7537 case 0x660f381c: /* pabsb */
7538 case 0x660f381d: /* pabsw */
7539 case 0x660f381e: /* pabsd */
7540 case 0x660f3820: /* pmovsxbw */
7541 case 0x660f3821: /* pmovsxbd */
7542 case 0x660f3822: /* pmovsxbq */
7543 case 0x660f3823: /* pmovsxwd */
7544 case 0x660f3824: /* pmovsxwq */
7545 case 0x660f3825: /* pmovsxdq */
7546 case 0x660f3828: /* pmuldq */
7547 case 0x660f3829: /* pcmpeqq */
7548 case 0x660f382a: /* movntdqa */
7549 case 0x660f3a08: /* roundps */
7550 case 0x660f3a09: /* roundpd */
7551 case 0x660f3a0a: /* roundss */
7552 case 0x660f3a0b: /* roundsd */
7553 case 0x660f3a0c: /* blendps */
7554 case 0x660f3a0d: /* blendpd */
7555 case 0x660f3a0e: /* pblendw */
7556 case 0x660f3a0f: /* palignr */
7557 case 0x660f3a20: /* pinsrb */
7558 case 0x660f3a21: /* insertps */
7559 case 0x660f3a22: /* pinsrd pinsrq */
7560 case 0x660f3a40: /* dpps */
7561 case 0x660f3a41: /* dppd */
7562 case 0x660f3a42: /* mpsadbw */
7563 case 0x660f3a60: /* pcmpestrm */
7564 case 0x660f3a61: /* pcmpestri */
7565 case 0x660f3a62: /* pcmpistrm */
7566 case 0x660f3a63: /* pcmpistri */
7567 case 0x0f51: /* sqrtps */
7568 case 0x660f51: /* sqrtpd */
7569 case 0xf20f51: /* sqrtsd */
7570 case 0xf30f51: /* sqrtss */
7571 case 0x0f52: /* rsqrtps */
7572 case 0xf30f52: /* rsqrtss */
7573 case 0x0f53: /* rcpps */
7574 case 0xf30f53: /* rcpss */
7575 case 0x0f54: /* andps */
7576 case 0x660f54: /* andpd */
7577 case 0x0f55: /* andnps */
7578 case 0x660f55: /* andnpd */
7579 case 0x0f56: /* orps */
7580 case 0x660f56: /* orpd */
7581 case 0x0f57: /* xorps */
7582 case 0x660f57: /* xorpd */
7583 case 0x0f58: /* addps */
7584 case 0x660f58: /* addpd */
7585 case 0xf20f58: /* addsd */
7586 case 0xf30f58: /* addss */
7587 case 0x0f59: /* mulps */
7588 case 0x660f59: /* mulpd */
7589 case 0xf20f59: /* mulsd */
7590 case 0xf30f59: /* mulss */
7591 case 0x0f5a: /* cvtps2pd */
7592 case 0x660f5a: /* cvtpd2ps */
7593 case 0xf20f5a: /* cvtsd2ss */
7594 case 0xf30f5a: /* cvtss2sd */
7595 case 0x0f5b: /* cvtdq2ps */
7596 case 0x660f5b: /* cvtps2dq */
7597 case 0xf30f5b: /* cvttps2dq */
7598 case 0x0f5c: /* subps */
7599 case 0x660f5c: /* subpd */
7600 case 0xf20f5c: /* subsd */
7601 case 0xf30f5c: /* subss */
7602 case 0x0f5d: /* minps */
7603 case 0x660f5d: /* minpd */
7604 case 0xf20f5d: /* minsd */
7605 case 0xf30f5d: /* minss */
7606 case 0x0f5e: /* divps */
7607 case 0x660f5e: /* divpd */
7608 case 0xf20f5e: /* divsd */
7609 case 0xf30f5e: /* divss */
7610 case 0x0f5f: /* maxps */
7611 case 0x660f5f: /* maxpd */
7612 case 0xf20f5f: /* maxsd */
7613 case 0xf30f5f: /* maxss */
7614 case 0x660f60: /* punpcklbw */
7615 case 0x660f61: /* punpcklwd */
7616 case 0x660f62: /* punpckldq */
7617 case 0x660f63: /* packsswb */
7618 case 0x660f64: /* pcmpgtb */
7619 case 0x660f65: /* pcmpgtw */
7620 case 0x660f66: /* pcmpgtd */
7621 case 0x660f67: /* packuswb */
7622 case 0x660f68: /* punpckhbw */
7623 case 0x660f69: /* punpckhwd */
7624 case 0x660f6a: /* punpckhdq */
7625 case 0x660f6b: /* packssdw */
7626 case 0x660f6c: /* punpcklqdq */
7627 case 0x660f6d: /* punpckhqdq */
7628 case 0x660f6e: /* movd */
7629 case 0x660f6f: /* movdqa */
7630 case 0xf30f6f: /* movdqu */
7631 case 0x660f70: /* pshufd */
7632 case 0xf20f70: /* pshuflw */
7633 case 0xf30f70: /* pshufhw */
7634 case 0x660f74: /* pcmpeqb */
7635 case 0x660f75: /* pcmpeqw */
7636 case 0x660f76: /* pcmpeqd */
7637 case 0x660f7c: /* haddpd */
7638 case 0xf20f7c: /* haddps */
7639 case 0x660f7d: /* hsubpd */
7640 case 0xf20f7d: /* hsubps */
7641 case 0xf30f7e: /* movq */
7642 case 0x0fc2: /* cmpps */
7643 case 0x660fc2: /* cmppd */
7644 case 0xf20fc2: /* cmpsd */
7645 case 0xf30fc2: /* cmpss */
7646 case 0x660fc4: /* pinsrw */
7647 case 0x0fc6: /* shufps */
7648 case 0x660fc6: /* shufpd */
7649 case 0x660fd0: /* addsubpd */
7650 case 0xf20fd0: /* addsubps */
7651 case 0x660fd1: /* psrlw */
7652 case 0x660fd2: /* psrld */
7653 case 0x660fd3: /* psrlq */
7654 case 0x660fd4: /* paddq */
7655 case 0x660fd5: /* pmullw */
7656 case 0xf30fd6: /* movq2dq */
7657 case 0x660fd8: /* psubusb */
7658 case 0x660fd9: /* psubusw */
7659 case 0x660fda: /* pminub */
7660 case 0x660fdb: /* pand */
7661 case 0x660fdc: /* paddusb */
7662 case 0x660fdd: /* paddusw */
7663 case 0x660fde: /* pmaxub */
7664 case 0x660fdf: /* pandn */
7665 case 0x660fe0: /* pavgb */
7666 case 0x660fe1: /* psraw */
7667 case 0x660fe2: /* psrad */
7668 case 0x660fe3: /* pavgw */
7669 case 0x660fe4: /* pmulhuw */
7670 case 0x660fe5: /* pmulhw */
7671 case 0x660fe6: /* cvttpd2dq */
7672 case 0xf20fe6: /* cvtpd2dq */
7673 case 0xf30fe6: /* cvtdq2pd */
7674 case 0x660fe8: /* psubsb */
7675 case 0x660fe9: /* psubsw */
7676 case 0x660fea: /* pminsw */
7677 case 0x660feb: /* por */
7678 case 0x660fec: /* paddsb */
7679 case 0x660fed: /* paddsw */
7680 case 0x660fee: /* pmaxsw */
7681 case 0x660fef: /* pxor */
7682 case 0xf20ff0: /* lddqu */
7683 case 0x660ff1: /* psllw */
7684 case 0x660ff2: /* pslld */
7685 case 0x660ff3: /* psllq */
7686 case 0x660ff4: /* pmuludq */
7687 case 0x660ff5: /* pmaddwd */
7688 case 0x660ff6: /* psadbw */
7689 case 0x660ff8: /* psubb */
7690 case 0x660ff9: /* psubw */
7691 case 0x660ffa: /* psubd */
7692 case 0x660ffb: /* psubq */
7693 case 0x660ffc: /* paddb */
7694 case 0x660ffd: /* paddw */
7695 case 0x660ffe: /* paddd */
7696 if (i386_record_modrm (&ir))
7699 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
7701 record_full_arch_list_add_reg (ir.regcache,
7702 I387_XMM0_REGNUM (tdep) + ir.reg);
7703 if ((opcode & 0xfffffffc) == 0x660f3a60)
7704 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7707 case 0x0f11: /* movups */
7708 case 0x660f11: /* movupd */
7709 case 0xf30f11: /* movss */
7710 case 0xf20f11: /* movsd */
7711 case 0x0f13: /* movlps */
7712 case 0x660f13: /* movlpd */
7713 case 0x0f17: /* movhps */
7714 case 0x660f17: /* movhpd */
7715 case 0x0f29: /* movaps */
7716 case 0x660f29: /* movapd */
7717 case 0x660f3a14: /* pextrb */
7718 case 0x660f3a15: /* pextrw */
7719 case 0x660f3a16: /* pextrd pextrq */
7720 case 0x660f3a17: /* extractps */
7721 case 0x660f7f: /* movdqa */
7722 case 0xf30f7f: /* movdqu */
7723 if (i386_record_modrm (&ir))
7727 if (opcode == 0x0f13 || opcode == 0x660f13
7728 || opcode == 0x0f17 || opcode == 0x660f17)
7731 if (!i386_xmm_regnum_p (gdbarch,
7732 I387_XMM0_REGNUM (tdep) + ir.rm))
7734 record_full_arch_list_add_reg (ir.regcache,
7735 I387_XMM0_REGNUM (tdep) + ir.rm);
7757 if (i386_record_lea_modrm (&ir))
7762 case 0x0f2b: /* movntps */
7763 case 0x660f2b: /* movntpd */
7764 case 0x0fe7: /* movntq */
7765 case 0x660fe7: /* movntdq */
7768 if (opcode == 0x0fe7)
7772 if (i386_record_lea_modrm (&ir))
7776 case 0xf30f2c: /* cvttss2si */
7777 case 0xf20f2c: /* cvttsd2si */
7778 case 0xf30f2d: /* cvtss2si */
7779 case 0xf20f2d: /* cvtsd2si */
7780 case 0xf20f38f0: /* crc32 */
7781 case 0xf20f38f1: /* crc32 */
7782 case 0x0f50: /* movmskps */
7783 case 0x660f50: /* movmskpd */
7784 case 0x0fc5: /* pextrw */
7785 case 0x660fc5: /* pextrw */
7786 case 0x0fd7: /* pmovmskb */
7787 case 0x660fd7: /* pmovmskb */
7788 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7791 case 0x0f3800: /* pshufb */
7792 case 0x0f3801: /* phaddw */
7793 case 0x0f3802: /* phaddd */
7794 case 0x0f3803: /* phaddsw */
7795 case 0x0f3804: /* pmaddubsw */
7796 case 0x0f3805: /* phsubw */
7797 case 0x0f3806: /* phsubd */
7798 case 0x0f3807: /* phsubsw */
7799 case 0x0f3808: /* psignb */
7800 case 0x0f3809: /* psignw */
7801 case 0x0f380a: /* psignd */
7802 case 0x0f380b: /* pmulhrsw */
7803 case 0x0f381c: /* pabsb */
7804 case 0x0f381d: /* pabsw */
7805 case 0x0f381e: /* pabsd */
7806 case 0x0f382b: /* packusdw */
7807 case 0x0f3830: /* pmovzxbw */
7808 case 0x0f3831: /* pmovzxbd */
7809 case 0x0f3832: /* pmovzxbq */
7810 case 0x0f3833: /* pmovzxwd */
7811 case 0x0f3834: /* pmovzxwq */
7812 case 0x0f3835: /* pmovzxdq */
7813 case 0x0f3837: /* pcmpgtq */
7814 case 0x0f3838: /* pminsb */
7815 case 0x0f3839: /* pminsd */
7816 case 0x0f383a: /* pminuw */
7817 case 0x0f383b: /* pminud */
7818 case 0x0f383c: /* pmaxsb */
7819 case 0x0f383d: /* pmaxsd */
7820 case 0x0f383e: /* pmaxuw */
7821 case 0x0f383f: /* pmaxud */
7822 case 0x0f3840: /* pmulld */
7823 case 0x0f3841: /* phminposuw */
7824 case 0x0f3a0f: /* palignr */
7825 case 0x0f60: /* punpcklbw */
7826 case 0x0f61: /* punpcklwd */
7827 case 0x0f62: /* punpckldq */
7828 case 0x0f63: /* packsswb */
7829 case 0x0f64: /* pcmpgtb */
7830 case 0x0f65: /* pcmpgtw */
7831 case 0x0f66: /* pcmpgtd */
7832 case 0x0f67: /* packuswb */
7833 case 0x0f68: /* punpckhbw */
7834 case 0x0f69: /* punpckhwd */
7835 case 0x0f6a: /* punpckhdq */
7836 case 0x0f6b: /* packssdw */
7837 case 0x0f6e: /* movd */
7838 case 0x0f6f: /* movq */
7839 case 0x0f70: /* pshufw */
7840 case 0x0f74: /* pcmpeqb */
7841 case 0x0f75: /* pcmpeqw */
7842 case 0x0f76: /* pcmpeqd */
7843 case 0x0fc4: /* pinsrw */
7844 case 0x0fd1: /* psrlw */
7845 case 0x0fd2: /* psrld */
7846 case 0x0fd3: /* psrlq */
7847 case 0x0fd4: /* paddq */
7848 case 0x0fd5: /* pmullw */
7849 case 0xf20fd6: /* movdq2q */
7850 case 0x0fd8: /* psubusb */
7851 case 0x0fd9: /* psubusw */
7852 case 0x0fda: /* pminub */
7853 case 0x0fdb: /* pand */
7854 case 0x0fdc: /* paddusb */
7855 case 0x0fdd: /* paddusw */
7856 case 0x0fde: /* pmaxub */
7857 case 0x0fdf: /* pandn */
7858 case 0x0fe0: /* pavgb */
7859 case 0x0fe1: /* psraw */
7860 case 0x0fe2: /* psrad */
7861 case 0x0fe3: /* pavgw */
7862 case 0x0fe4: /* pmulhuw */
7863 case 0x0fe5: /* pmulhw */
7864 case 0x0fe8: /* psubsb */
7865 case 0x0fe9: /* psubsw */
7866 case 0x0fea: /* pminsw */
7867 case 0x0feb: /* por */
7868 case 0x0fec: /* paddsb */
7869 case 0x0fed: /* paddsw */
7870 case 0x0fee: /* pmaxsw */
7871 case 0x0fef: /* pxor */
7872 case 0x0ff1: /* psllw */
7873 case 0x0ff2: /* pslld */
7874 case 0x0ff3: /* psllq */
7875 case 0x0ff4: /* pmuludq */
7876 case 0x0ff5: /* pmaddwd */
7877 case 0x0ff6: /* psadbw */
7878 case 0x0ff8: /* psubb */
7879 case 0x0ff9: /* psubw */
7880 case 0x0ffa: /* psubd */
7881 case 0x0ffb: /* psubq */
7882 case 0x0ffc: /* paddb */
7883 case 0x0ffd: /* paddw */
7884 case 0x0ffe: /* paddd */
7885 if (i386_record_modrm (&ir))
7887 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7889 record_full_arch_list_add_reg (ir.regcache,
7890 I387_MM0_REGNUM (tdep) + ir.reg);
7893 case 0x0f71: /* psllw */
7894 case 0x0f72: /* pslld */
7895 case 0x0f73: /* psllq */
7896 if (i386_record_modrm (&ir))
7898 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7900 record_full_arch_list_add_reg (ir.regcache,
7901 I387_MM0_REGNUM (tdep) + ir.rm);
7904 case 0x660f71: /* psllw */
7905 case 0x660f72: /* pslld */
7906 case 0x660f73: /* psllq */
7907 if (i386_record_modrm (&ir))
7910 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
7912 record_full_arch_list_add_reg (ir.regcache,
7913 I387_XMM0_REGNUM (tdep) + ir.rm);
7916 case 0x0f7e: /* movd */
7917 case 0x660f7e: /* movd */
7918 if (i386_record_modrm (&ir))
7921 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7928 if (i386_record_lea_modrm (&ir))
7933 case 0x0f7f: /* movq */
7934 if (i386_record_modrm (&ir))
7938 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7940 record_full_arch_list_add_reg (ir.regcache,
7941 I387_MM0_REGNUM (tdep) + ir.rm);
7946 if (i386_record_lea_modrm (&ir))
7951 case 0xf30fb8: /* popcnt */
7952 if (i386_record_modrm (&ir))
7954 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
7955 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7958 case 0x660fd6: /* movq */
7959 if (i386_record_modrm (&ir))
7964 if (!i386_xmm_regnum_p (gdbarch,
7965 I387_XMM0_REGNUM (tdep) + ir.rm))
7967 record_full_arch_list_add_reg (ir.regcache,
7968 I387_XMM0_REGNUM (tdep) + ir.rm);
7973 if (i386_record_lea_modrm (&ir))
7978 case 0x660f3817: /* ptest */
7979 case 0x0f2e: /* ucomiss */
7980 case 0x660f2e: /* ucomisd */
7981 case 0x0f2f: /* comiss */
7982 case 0x660f2f: /* comisd */
7983 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7986 case 0x0ff7: /* maskmovq */
7987 regcache_raw_read_unsigned (ir.regcache,
7988 ir.regmap[X86_RECORD_REDI_REGNUM],
7990 if (record_full_arch_list_add_mem (addr, 64))
7994 case 0x660ff7: /* maskmovdqu */
7995 regcache_raw_read_unsigned (ir.regcache,
7996 ir.regmap[X86_RECORD_REDI_REGNUM],
7998 if (record_full_arch_list_add_mem (addr, 128))
8013 /* In the future, maybe still need to deal with need_dasm. */
8014 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
8015 if (record_full_arch_list_add_end ())
8021 printf_unfiltered (_("Process record does not support instruction 0x%02x "
8022 "at address %s.\n"),
8023 (unsigned int) (opcode),
8024 paddress (gdbarch, ir.orig_addr));
8028 static const int i386_record_regmap[] =
8030 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
8031 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
8032 0, 0, 0, 0, 0, 0, 0, 0,
8033 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
8034 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
8037 /* Check that the given address appears suitable for a fast
8038 tracepoint, which on x86-64 means that we need an instruction of at
8039 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8040 jump and not have to worry about program jumps to an address in the
8041 middle of the tracepoint jump. On x86, it may be possible to use
8042 4-byte jumps with a 2-byte offset to a trampoline located in the
8043 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8044 of instruction to replace, and 0 if not, plus an explanatory
8048 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, CORE_ADDR addr,
8052 static struct ui_file *gdb_null = NULL;
8054 /* Ask the target for the minimum instruction length supported. */
8055 jumplen = target_get_min_fast_tracepoint_insn_len ();
8059 /* If the target does not support the get_min_fast_tracepoint_insn_len
8060 operation, assume that fast tracepoints will always be implemented
8061 using 4-byte relative jumps on both x86 and x86-64. */
8064 else if (jumplen == 0)
8066 /* If the target does support get_min_fast_tracepoint_insn_len but
8067 returns zero, then the IPA has not loaded yet. In this case,
8068 we optimistically assume that truncated 2-byte relative jumps
8069 will be available on x86, and compensate later if this assumption
8070 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8071 jumps will always be used. */
8072 jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4;
8075 /* Dummy file descriptor for the disassembler. */
8077 gdb_null = ui_file_new ();
8079 /* Check for fit. */
8080 len = gdb_print_insn (gdbarch, addr, gdb_null, NULL);
8084 /* Return a bit of target-specific detail to add to the caller's
8085 generic failure message. */
8087 *msg = xstrprintf (_("; instruction is only %d bytes long, "
8088 "need at least %d bytes for the jump"),
8101 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
8102 struct tdesc_arch_data *tdesc_data)
8104 const struct target_desc *tdesc = tdep->tdesc;
8105 const struct tdesc_feature *feature_core;
8107 const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx,
8109 int i, num_regs, valid_p;
8111 if (! tdesc_has_registers (tdesc))
8114 /* Get core registers. */
8115 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
8116 if (feature_core == NULL)
8119 /* Get SSE registers. */
8120 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
8122 /* Try AVX registers. */
8123 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
8125 /* Try MPX registers. */
8126 feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx");
8128 /* Try AVX512 registers. */
8129 feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512");
8133 /* The XCR0 bits. */
8136 /* AVX512 register description requires AVX register description. */
8140 tdep->xcr0 = X86_XSTATE_MPX_AVX512_MASK;
8142 /* It may have been set by OSABI initialization function. */
8143 if (tdep->k0_regnum < 0)
8145 tdep->k_register_names = i386_k_names;
8146 tdep->k0_regnum = I386_K0_REGNUM;
8149 for (i = 0; i < I387_NUM_K_REGS; i++)
8150 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8151 tdep->k0_regnum + i,
8154 if (tdep->num_zmm_regs == 0)
8156 tdep->zmmh_register_names = i386_zmmh_names;
8157 tdep->num_zmm_regs = 8;
8158 tdep->zmm0h_regnum = I386_ZMM0H_REGNUM;
8161 for (i = 0; i < tdep->num_zmm_regs; i++)
8162 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8163 tdep->zmm0h_regnum + i,
8164 tdep->zmmh_register_names[i]);
8166 for (i = 0; i < tdep->num_xmm_avx512_regs; i++)
8167 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8168 tdep->xmm16_regnum + i,
8169 tdep->xmm_avx512_register_names[i]);
8171 for (i = 0; i < tdep->num_ymm_avx512_regs; i++)
8172 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8173 tdep->ymm16h_regnum + i,
8174 tdep->ymm16h_register_names[i]);
8178 /* AVX register description requires SSE register description. */
8182 if (!feature_avx512)
8183 tdep->xcr0 = X86_XSTATE_AVX_MASK;
8185 /* It may have been set by OSABI initialization function. */
8186 if (tdep->num_ymm_regs == 0)
8188 tdep->ymmh_register_names = i386_ymmh_names;
8189 tdep->num_ymm_regs = 8;
8190 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
8193 for (i = 0; i < tdep->num_ymm_regs; i++)
8194 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
8195 tdep->ymm0h_regnum + i,
8196 tdep->ymmh_register_names[i]);
8198 else if (feature_sse)
8199 tdep->xcr0 = X86_XSTATE_SSE_MASK;
8202 tdep->xcr0 = X86_XSTATE_X87_MASK;
8203 tdep->num_xmm_regs = 0;
8206 num_regs = tdep->num_core_regs;
8207 for (i = 0; i < num_regs; i++)
8208 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
8209 tdep->register_names[i]);
8213 /* Need to include %mxcsr, so add one. */
8214 num_regs += tdep->num_xmm_regs + 1;
8215 for (; i < num_regs; i++)
8216 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
8217 tdep->register_names[i]);
8222 tdep->xcr0 |= X86_XSTATE_MPX_MASK;
8224 if (tdep->bnd0r_regnum < 0)
8226 tdep->mpx_register_names = i386_mpx_names;
8227 tdep->bnd0r_regnum = I386_BND0R_REGNUM;
8228 tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM;
8231 for (i = 0; i < I387_NUM_MPX_REGS; i++)
8232 valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data,
8233 I387_BND0R_REGNUM (tdep) + i,
8234 tdep->mpx_register_names[i]);
8241 static struct gdbarch *
8242 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8244 struct gdbarch_tdep *tdep;
8245 struct gdbarch *gdbarch;
8246 struct tdesc_arch_data *tdesc_data;
8247 const struct target_desc *tdesc;
8255 /* If there is already a candidate, use it. */
8256 arches = gdbarch_list_lookup_by_info (arches, &info);
8258 return arches->gdbarch;
8260 /* Allocate space for the new architecture. */
8261 tdep = XCNEW (struct gdbarch_tdep);
8262 gdbarch = gdbarch_alloc (&info, tdep);
8264 /* General-purpose registers. */
8265 tdep->gregset_reg_offset = NULL;
8266 tdep->gregset_num_regs = I386_NUM_GREGS;
8267 tdep->sizeof_gregset = 0;
8269 /* Floating-point registers. */
8270 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
8271 tdep->fpregset = &i386_fpregset;
8273 /* The default settings include the FPU registers, the MMX registers
8274 and the SSE registers. This can be overridden for a specific ABI
8275 by adjusting the members `st0_regnum', `mm0_regnum' and
8276 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8277 will show up in the output of "info all-registers". */
8279 tdep->st0_regnum = I386_ST0_REGNUM;
8281 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8282 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
8284 tdep->jb_pc_offset = -1;
8285 tdep->struct_return = pcc_struct_return;
8286 tdep->sigtramp_start = 0;
8287 tdep->sigtramp_end = 0;
8288 tdep->sigtramp_p = i386_sigtramp_p;
8289 tdep->sigcontext_addr = NULL;
8290 tdep->sc_reg_offset = NULL;
8291 tdep->sc_pc_offset = -1;
8292 tdep->sc_sp_offset = -1;
8294 tdep->xsave_xcr0_offset = -1;
8296 tdep->record_regmap = i386_record_regmap;
8298 set_gdbarch_long_long_align_bit (gdbarch, 32);
8300 /* The format used for `long double' on almost all i386 targets is
8301 the i387 extended floating-point format. In fact, of all targets
8302 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8303 on having a `long double' that's not `long' at all. */
8304 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
8306 /* Although the i387 extended floating-point has only 80 significant
8307 bits, a `long double' actually takes up 96, probably to enforce
8309 set_gdbarch_long_double_bit (gdbarch, 96);
8311 /* Register numbers of various important registers. */
8312 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
8313 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
8314 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
8315 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
8317 /* NOTE: kettenis/20040418: GCC does have two possible register
8318 numbering schemes on the i386: dbx and SVR4. These schemes
8319 differ in how they number %ebp, %esp, %eflags, and the
8320 floating-point registers, and are implemented by the arrays
8321 dbx_register_map[] and svr4_dbx_register_map in
8322 gcc/config/i386.c. GCC also defines a third numbering scheme in
8323 gcc/config/i386.c, which it designates as the "default" register
8324 map used in 64bit mode. This last register numbering scheme is
8325 implemented in dbx64_register_map, and is used for AMD64; see
8328 Currently, each GCC i386 target always uses the same register
8329 numbering scheme across all its supported debugging formats
8330 i.e. SDB (COFF), stabs and DWARF 2. This is because
8331 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8332 DBX_REGISTER_NUMBER macro which is defined by each target's
8333 respective config header in a manner independent of the requested
8334 output debugging format.
8336 This does not match the arrangement below, which presumes that
8337 the SDB and stabs numbering schemes differ from the DWARF and
8338 DWARF 2 ones. The reason for this arrangement is that it is
8339 likely to get the numbering scheme for the target's
8340 default/native debug format right. For targets where GCC is the
8341 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8342 targets where the native toolchain uses a different numbering
8343 scheme for a particular debug format (stabs-in-ELF on Solaris)
8344 the defaults below will have to be overridden, like
8345 i386_elf_init_abi() does. */
8347 /* Use the dbx register numbering scheme for stabs and COFF. */
8348 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8349 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8351 /* Use the SVR4 register numbering scheme for DWARF 2. */
8352 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
8354 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8355 be in use on any of the supported i386 targets. */
8357 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
8359 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
8361 /* Call dummy code. */
8362 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
8363 set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code);
8364 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
8365 set_gdbarch_frame_align (gdbarch, i386_frame_align);
8367 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
8368 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
8369 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
8371 set_gdbarch_return_value (gdbarch, i386_return_value);
8373 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
8375 /* Stack grows downward. */
8376 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8378 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc);
8379 set_gdbarch_decr_pc_after_break (gdbarch, 1);
8380 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
8382 set_gdbarch_frame_args_skip (gdbarch, 8);
8384 set_gdbarch_print_insn (gdbarch, i386_print_insn);
8386 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
8388 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
8390 /* Add the i386 register groups. */
8391 i386_add_reggroups (gdbarch);
8392 tdep->register_reggroup_p = i386_register_reggroup_p;
8394 /* Helper for function argument information. */
8395 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
8397 /* Hook the function epilogue frame unwinder. This unwinder is
8398 appended to the list first, so that it supercedes the DWARF
8399 unwinder in function epilogues (where the DWARF unwinder
8400 currently fails). */
8401 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
8403 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8404 to the list before the prologue-based unwinders, so that DWARF
8405 CFI info will be used if it is available. */
8406 dwarf2_append_unwinders (gdbarch);
8408 frame_base_set_default (gdbarch, &i386_frame_base);
8410 /* Pseudo registers may be changed by amd64_init_abi. */
8411 set_gdbarch_pseudo_register_read_value (gdbarch,
8412 i386_pseudo_register_read_value);
8413 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
8415 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
8416 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
8418 /* Override the normal target description method to make the AVX
8419 upper halves anonymous. */
8420 set_gdbarch_register_name (gdbarch, i386_register_name);
8422 /* Even though the default ABI only includes general-purpose registers,
8423 floating-point registers and the SSE registers, we have to leave a
8424 gap for the upper AVX, MPX and AVX512 registers. */
8425 set_gdbarch_num_regs (gdbarch, I386_AVX512_NUM_REGS);
8427 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
8429 /* Get the x86 target description from INFO. */
8430 tdesc = info.target_desc;
8431 if (! tdesc_has_registers (tdesc))
8433 tdep->tdesc = tdesc;
8435 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
8436 tdep->register_names = i386_register_names;
8438 /* No upper YMM registers. */
8439 tdep->ymmh_register_names = NULL;
8440 tdep->ymm0h_regnum = -1;
8442 /* No upper ZMM registers. */
8443 tdep->zmmh_register_names = NULL;
8444 tdep->zmm0h_regnum = -1;
8446 /* No high XMM registers. */
8447 tdep->xmm_avx512_register_names = NULL;
8448 tdep->xmm16_regnum = -1;
8450 /* No upper YMM16-31 registers. */
8451 tdep->ymm16h_register_names = NULL;
8452 tdep->ymm16h_regnum = -1;
8454 tdep->num_byte_regs = 8;
8455 tdep->num_word_regs = 8;
8456 tdep->num_dword_regs = 0;
8457 tdep->num_mmx_regs = 8;
8458 tdep->num_ymm_regs = 0;
8460 /* No MPX registers. */
8461 tdep->bnd0r_regnum = -1;
8462 tdep->bndcfgu_regnum = -1;
8464 /* No AVX512 registers. */
8465 tdep->k0_regnum = -1;
8466 tdep->num_zmm_regs = 0;
8467 tdep->num_ymm_avx512_regs = 0;
8468 tdep->num_xmm_avx512_regs = 0;
8470 tdesc_data = tdesc_data_alloc ();
8472 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
8474 set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address);
8476 set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call);
8477 set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret);
8478 set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump);
8480 /* Hook in ABI-specific overrides, if they have been registered. */
8481 info.tdep_info = (void *) tdesc_data;
8482 gdbarch_init_osabi (info, gdbarch);
8484 if (!i386_validate_tdesc_p (tdep, tdesc_data))
8486 tdesc_data_cleanup (tdesc_data);
8488 gdbarch_free (gdbarch);
8492 num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0);
8494 /* Wire in pseudo registers. Number of pseudo registers may be
8496 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
8497 + tdep->num_word_regs
8498 + tdep->num_dword_regs
8499 + tdep->num_mmx_regs
8500 + tdep->num_ymm_regs
8502 + tdep->num_ymm_avx512_regs
8503 + tdep->num_zmm_regs));
8505 /* Target description may be changed. */
8506 tdesc = tdep->tdesc;
8508 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
8510 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8511 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
8513 /* Make %al the first pseudo-register. */
8514 tdep->al_regnum = gdbarch_num_regs (gdbarch);
8515 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
8517 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
8518 if (tdep->num_dword_regs)
8520 /* Support dword pseudo-register if it hasn't been disabled. */
8521 tdep->eax_regnum = ymm0_regnum;
8522 ymm0_regnum += tdep->num_dword_regs;
8525 tdep->eax_regnum = -1;
8527 mm0_regnum = ymm0_regnum;
8528 if (tdep->num_ymm_regs)
8530 /* Support YMM pseudo-register if it is available. */
8531 tdep->ymm0_regnum = ymm0_regnum;
8532 mm0_regnum += tdep->num_ymm_regs;
8535 tdep->ymm0_regnum = -1;
8537 if (tdep->num_ymm_avx512_regs)
8539 /* Support YMM16-31 pseudo registers if available. */
8540 tdep->ymm16_regnum = mm0_regnum;
8541 mm0_regnum += tdep->num_ymm_avx512_regs;
8544 tdep->ymm16_regnum = -1;
8546 if (tdep->num_zmm_regs)
8548 /* Support ZMM pseudo-register if it is available. */
8549 tdep->zmm0_regnum = mm0_regnum;
8550 mm0_regnum += tdep->num_zmm_regs;
8553 tdep->zmm0_regnum = -1;
8555 bnd0_regnum = mm0_regnum;
8556 if (tdep->num_mmx_regs != 0)
8558 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8559 tdep->mm0_regnum = mm0_regnum;
8560 bnd0_regnum += tdep->num_mmx_regs;
8563 tdep->mm0_regnum = -1;
8565 if (tdep->bnd0r_regnum > 0)
8566 tdep->bnd0_regnum = bnd0_regnum;
8568 tdep-> bnd0_regnum = -1;
8570 /* Hook in the legacy prologue-based unwinders last (fallback). */
8571 frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind);
8572 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
8573 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
8575 /* If we have a register mapping, enable the generic core file
8576 support, unless it has already been enabled. */
8577 if (tdep->gregset_reg_offset
8578 && !gdbarch_iterate_over_regset_sections_p (gdbarch))
8579 set_gdbarch_iterate_over_regset_sections
8580 (gdbarch, i386_iterate_over_regset_sections);
8582 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
8583 i386_fast_tracepoint_valid_at);
8588 static enum gdb_osabi
8589 i386_coff_osabi_sniffer (bfd *abfd)
8591 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
8592 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
8593 return GDB_OSABI_GO32;
8595 return GDB_OSABI_UNKNOWN;
8599 /* Return the target description for a specified XSAVE feature mask. */
8601 const struct target_desc *
8602 i386_target_description (uint64_t xcr0)
8604 switch (xcr0 & X86_XSTATE_ALL_MASK)
8606 case X86_XSTATE_MPX_AVX512_MASK:
8607 case X86_XSTATE_AVX512_MASK:
8608 return tdesc_i386_avx512;
8609 case X86_XSTATE_MPX_MASK:
8610 return tdesc_i386_mpx;
8611 case X86_XSTATE_AVX_MASK:
8612 return tdesc_i386_avx;
8618 #define MPX_BASE_MASK (~(ULONGEST) 0xfff)
8620 /* Find the bound directory base address. */
8622 static unsigned long
8623 i386_mpx_bd_base (void)
8625 struct regcache *rcache;
8626 struct gdbarch_tdep *tdep;
8628 enum register_status regstatus;
8629 struct gdb_exception except;
8631 rcache = get_current_regcache ();
8632 tdep = gdbarch_tdep (get_regcache_arch (rcache));
8634 regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret);
8636 if (regstatus != REG_VALID)
8637 error (_("BNDCFGU register invalid, read status %d."), regstatus);
8639 return ret & MPX_BASE_MASK;
8642 /* Check if the current target is MPX enabled. */
8645 i386_mpx_enabled (void)
8647 const struct gdbarch_tdep *tdep = gdbarch_tdep (get_current_arch ());
8648 const struct target_desc *tdesc = tdep->tdesc;
8650 return (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL);
8653 #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */
8654 #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */
8655 #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */
8656 #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */
8658 /* Find the bound table entry given the pointer location and the base
8659 address of the table. */
8662 i386_mpx_get_bt_entry (CORE_ADDR ptr, CORE_ADDR bd_base)
8666 CORE_ADDR mpx_bd_mask, bd_ptr_r_shift, bd_ptr_l_shift;
8667 CORE_ADDR bt_mask, bt_select_r_shift, bt_select_l_shift;
8668 CORE_ADDR bd_entry_addr;
8671 struct gdbarch *gdbarch = get_current_arch ();
8672 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8675 if (gdbarch_ptr_bit (gdbarch) == 64)
8677 mpx_bd_mask = (CORE_ADDR) MPX_BD_MASK;
8678 bd_ptr_r_shift = 20;
8680 bt_select_r_shift = 3;
8681 bt_select_l_shift = 5;
8682 bt_mask = (CORE_ADDR) MPX_BT_MASK;
8684 if ( sizeof (CORE_ADDR) == 4)
8685 error (_("operation not supported"));
8689 mpx_bd_mask = MPX_BD_MASK_32;
8690 bd_ptr_r_shift = 12;
8692 bt_select_r_shift = 2;
8693 bt_select_l_shift = 4;
8694 bt_mask = MPX_BT_MASK_32;
8697 offset1 = ((ptr & mpx_bd_mask) >> bd_ptr_r_shift) << bd_ptr_l_shift;
8698 bd_entry_addr = bd_base + offset1;
8699 bd_entry = read_memory_typed_address (bd_entry_addr, data_ptr_type);
8701 if ((bd_entry & 0x1) == 0)
8702 error (_("Invalid bounds directory entry at %s."),
8703 paddress (get_current_arch (), bd_entry_addr));
8705 /* Clearing status bit. */
8707 bt_addr = bd_entry & ~bt_select_r_shift;
8708 offset2 = ((ptr & bt_mask) >> bt_select_r_shift) << bt_select_l_shift;
8710 return bt_addr + offset2;
8713 /* Print routine for the mpx bounds. */
8716 i386_mpx_print_bounds (const CORE_ADDR bt_entry[4])
8718 struct ui_out *uiout = current_uiout;
8720 struct gdbarch *gdbarch = get_current_arch ();
8721 CORE_ADDR onecompl = ~((CORE_ADDR) 0);
8722 int bounds_in_map = ((~bt_entry[1] == 0 && bt_entry[0] == onecompl) ? 1 : 0);
8724 if (bounds_in_map == 1)
8726 ui_out_text (uiout, "Null bounds on map:");
8727 ui_out_text (uiout, " pointer value = ");
8728 ui_out_field_core_addr (uiout, "pointer-value", gdbarch, bt_entry[2]);
8729 ui_out_text (uiout, ".");
8730 ui_out_text (uiout, "\n");
8734 ui_out_text (uiout, "{lbound = ");
8735 ui_out_field_core_addr (uiout, "lower-bound", gdbarch, bt_entry[0]);
8736 ui_out_text (uiout, ", ubound = ");
8738 /* The upper bound is stored in 1's complement. */
8739 ui_out_field_core_addr (uiout, "upper-bound", gdbarch, ~bt_entry[1]);
8740 ui_out_text (uiout, "}: pointer value = ");
8741 ui_out_field_core_addr (uiout, "pointer-value", gdbarch, bt_entry[2]);
8743 if (gdbarch_ptr_bit (gdbarch) == 64)
8744 size = ( (~(int64_t) bt_entry[1]) - (int64_t) bt_entry[0]);
8746 size = ( ~((int32_t) bt_entry[1]) - (int32_t) bt_entry[0]);
8748 /* In case the bounds are 0x0 and 0xffff... the difference will be -1.
8749 -1 represents in this sense full memory access, and there is no need
8752 size = (size > -1 ? size + 1 : size);
8753 ui_out_text (uiout, ", size = ");
8754 ui_out_field_fmt (uiout, "size", "%s", plongest (size));
8756 ui_out_text (uiout, ", metadata = ");
8757 ui_out_field_core_addr (uiout, "metadata", gdbarch, bt_entry[3]);
8758 ui_out_text (uiout, "\n");
8762 /* Implement the command "show mpx bound". */
8765 i386_mpx_info_bounds (char *args, int from_tty)
8767 CORE_ADDR bd_base = 0;
8769 CORE_ADDR bt_entry_addr = 0;
8770 CORE_ADDR bt_entry[4];
8772 struct gdbarch *gdbarch = get_current_arch ();
8773 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8775 if (!i386_mpx_enabled ())
8777 printf_unfiltered (_("Intel(R) Memory Protection Extensions not "
8778 "supported on this target.\n"));
8784 printf_unfiltered (_("Address of pointer variable expected.\n"));
8788 addr = parse_and_eval_address (args);
8790 bd_base = i386_mpx_bd_base ();
8791 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8793 memset (bt_entry, 0, sizeof (bt_entry));
8795 for (i = 0; i < 4; i++)
8796 bt_entry[i] = read_memory_typed_address (bt_entry_addr
8797 + i * data_ptr_type->length,
8800 i386_mpx_print_bounds (bt_entry);
8803 /* Implement the command "set mpx bound". */
8806 i386_mpx_set_bounds (char *args, int from_tty)
8808 CORE_ADDR bd_base = 0;
8809 CORE_ADDR addr, lower, upper;
8810 CORE_ADDR bt_entry_addr = 0;
8811 CORE_ADDR bt_entry[2];
8812 const char *input = args;
8814 struct gdbarch *gdbarch = get_current_arch ();
8815 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8816 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8818 if (!i386_mpx_enabled ())
8819 error (_("Intel(R) Memory Protection Extensions not supported\
8823 error (_("Pointer value expected."));
8825 addr = value_as_address (parse_to_comma_and_eval (&input));
8827 if (input[0] == ',')
8829 if (input[0] == '\0')
8830 error (_("wrong number of arguments: missing lower and upper bound."));
8831 lower = value_as_address (parse_to_comma_and_eval (&input));
8833 if (input[0] == ',')
8835 if (input[0] == '\0')
8836 error (_("Wrong number of arguments; Missing upper bound."));
8837 upper = value_as_address (parse_to_comma_and_eval (&input));
8839 bd_base = i386_mpx_bd_base ();
8840 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8841 for (i = 0; i < 2; i++)
8842 bt_entry[i] = read_memory_typed_address (bt_entry_addr
8843 + i * data_ptr_type->length,
8845 bt_entry[0] = (uint64_t) lower;
8846 bt_entry[1] = ~(uint64_t) upper;
8848 for (i = 0; i < 2; i++)
8849 write_memory_unsigned_integer (bt_entry_addr + i * data_ptr_type->length,
8850 data_ptr_type->length, byte_order,
8854 static struct cmd_list_element *mpx_set_cmdlist, *mpx_show_cmdlist;
8856 /* Helper function for the CLI commands. */
8859 set_mpx_cmd (char *args, int from_tty)
8861 help_list (mpx_set_cmdlist, "set mpx ", all_commands, gdb_stdout);
8864 /* Helper function for the CLI commands. */
8867 show_mpx_cmd (char *args, int from_tty)
8869 cmd_show_list (mpx_show_cmdlist, from_tty, "");
8872 /* Provide a prototype to silence -Wmissing-prototypes. */
8873 void _initialize_i386_tdep (void);
8876 _initialize_i386_tdep (void)
8878 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
8880 /* Add the variable that controls the disassembly flavor. */
8881 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
8882 &disassembly_flavor, _("\
8883 Set the disassembly flavor."), _("\
8884 Show the disassembly flavor."), _("\
8885 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
8887 NULL, /* FIXME: i18n: */
8888 &setlist, &showlist);
8890 /* Add the variable that controls the convention for returning
8892 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
8893 &struct_convention, _("\
8894 Set the convention for returning small structs."), _("\
8895 Show the convention for returning small structs."), _("\
8896 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
8899 NULL, /* FIXME: i18n: */
8900 &setlist, &showlist);
8902 /* Add "mpx" prefix for the set commands. */
8904 add_prefix_cmd ("mpx", class_support, set_mpx_cmd, _("\
8905 Set Intel(R) Memory Protection Extensions specific variables."),
8906 &mpx_set_cmdlist, "set mpx ",
8907 0 /* allow-unknown */, &setlist);
8909 /* Add "mpx" prefix for the show commands. */
8911 add_prefix_cmd ("mpx", class_support, show_mpx_cmd, _("\
8912 Show Intel(R) Memory Protection Extensions specific variables."),
8913 &mpx_show_cmdlist, "show mpx ",
8914 0 /* allow-unknown */, &showlist);
8916 /* Add "bound" command for the show mpx commands list. */
8918 add_cmd ("bound", no_class, i386_mpx_info_bounds,
8919 "Show the memory bounds for a given array/pointer storage\
8920 in the bound table.",
8923 /* Add "bound" command for the set mpx commands list. */
8925 add_cmd ("bound", no_class, i386_mpx_set_bounds,
8926 "Set the memory bounds for a given array/pointer storage\
8927 in the bound table.",
8930 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
8931 i386_coff_osabi_sniffer);
8933 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
8934 i386_svr4_init_abi);
8935 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
8936 i386_go32_init_abi);
8938 /* Initialize the i386-specific register groups. */
8939 i386_init_reggroups ();
8941 /* Initialize the standard target descriptions. */
8942 initialize_tdesc_i386 ();
8943 initialize_tdesc_i386_mmx ();
8944 initialize_tdesc_i386_avx ();
8945 initialize_tdesc_i386_mpx ();
8946 initialize_tdesc_i386_avx512 ();
8948 /* Tell remote stub that we support XML target description. */
8949 register_remote_support_xml ("i386");