1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2013 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
37 #include "reggroups.h"
46 #include "exceptions.h"
47 #include "gdb_assert.h"
50 #include "i386-tdep.h"
51 #include "i387-tdep.h"
52 #include "i386-xstate.h"
55 #include "record-full.h"
58 #include "features/i386/i386.c"
59 #include "features/i386/i386-avx.c"
60 #include "features/i386/i386-mpx.c"
61 #include "features/i386/i386-mmx.c"
66 #include "stap-probe.h"
67 #include "user-regs.h"
68 #include "cli/cli-utils.h"
69 #include "expression.h"
70 #include "parser-defs.h"
75 static const char *i386_register_names[] =
77 "eax", "ecx", "edx", "ebx",
78 "esp", "ebp", "esi", "edi",
79 "eip", "eflags", "cs", "ss",
80 "ds", "es", "fs", "gs",
81 "st0", "st1", "st2", "st3",
82 "st4", "st5", "st6", "st7",
83 "fctrl", "fstat", "ftag", "fiseg",
84 "fioff", "foseg", "fooff", "fop",
85 "xmm0", "xmm1", "xmm2", "xmm3",
86 "xmm4", "xmm5", "xmm6", "xmm7",
90 static const char *i386_ymm_names[] =
92 "ymm0", "ymm1", "ymm2", "ymm3",
93 "ymm4", "ymm5", "ymm6", "ymm7",
96 static const char *i386_ymmh_names[] =
98 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
99 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
102 static const char *i386_mpx_names[] =
104 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
107 /* Register names for MPX pseudo-registers. */
109 static const char *i386_bnd_names[] =
111 "bnd0", "bnd1", "bnd2", "bnd3"
114 /* Register names for MMX pseudo-registers. */
116 static const char *i386_mmx_names[] =
118 "mm0", "mm1", "mm2", "mm3",
119 "mm4", "mm5", "mm6", "mm7"
122 /* Register names for byte pseudo-registers. */
124 static const char *i386_byte_names[] =
126 "al", "cl", "dl", "bl",
127 "ah", "ch", "dh", "bh"
130 /* Register names for word pseudo-registers. */
132 static const char *i386_word_names[] =
134 "ax", "cx", "dx", "bx",
141 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
143 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
144 int mm0_regnum = tdep->mm0_regnum;
149 regnum -= mm0_regnum;
150 return regnum >= 0 && regnum < tdep->num_mmx_regs;
156 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
158 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
160 regnum -= tdep->al_regnum;
161 return regnum >= 0 && regnum < tdep->num_byte_regs;
167 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
169 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
171 regnum -= tdep->ax_regnum;
172 return regnum >= 0 && regnum < tdep->num_word_regs;
175 /* Dword register? */
178 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
180 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
181 int eax_regnum = tdep->eax_regnum;
186 regnum -= eax_regnum;
187 return regnum >= 0 && regnum < tdep->num_dword_regs;
191 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
193 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
194 int ymm0h_regnum = tdep->ymm0h_regnum;
196 if (ymm0h_regnum < 0)
199 regnum -= ymm0h_regnum;
200 return regnum >= 0 && regnum < tdep->num_ymm_regs;
206 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
208 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
209 int ymm0_regnum = tdep->ymm0_regnum;
214 regnum -= ymm0_regnum;
215 return regnum >= 0 && regnum < tdep->num_ymm_regs;
221 i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum)
223 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
224 int bnd0_regnum = tdep->bnd0_regnum;
229 regnum -= bnd0_regnum;
230 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
236 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
238 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
239 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
241 if (num_xmm_regs == 0)
244 regnum -= I387_XMM0_REGNUM (tdep);
245 return regnum >= 0 && regnum < num_xmm_regs;
249 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
251 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
253 if (I387_NUM_XMM_REGS (tdep) == 0)
256 return (regnum == I387_MXCSR_REGNUM (tdep));
262 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
264 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
266 if (I387_ST0_REGNUM (tdep) < 0)
269 return (I387_ST0_REGNUM (tdep) <= regnum
270 && regnum < I387_FCTRL_REGNUM (tdep));
274 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
276 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
278 if (I387_ST0_REGNUM (tdep) < 0)
281 return (I387_FCTRL_REGNUM (tdep) <= regnum
282 && regnum < I387_XMM0_REGNUM (tdep));
285 /* BNDr (raw) register? */
288 i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum)
290 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
292 if (I387_BND0R_REGNUM (tdep) < 0)
295 regnum -= tdep->bnd0r_regnum;
296 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
299 /* BND control register? */
302 i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum)
304 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
306 if (I387_BNDCFGU_REGNUM (tdep) < 0)
309 regnum -= I387_BNDCFGU_REGNUM (tdep);
310 return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS;
313 /* Return the name of register REGNUM, or the empty string if it is
314 an anonymous register. */
317 i386_register_name (struct gdbarch *gdbarch, int regnum)
319 /* Hide the upper YMM registers. */
320 if (i386_ymmh_regnum_p (gdbarch, regnum))
323 return tdesc_register_name (gdbarch, regnum);
326 /* Return the name of register REGNUM. */
329 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
331 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
332 if (i386_bnd_regnum_p (gdbarch, regnum))
333 return i386_bnd_names[regnum - tdep->bnd0_regnum];
334 if (i386_mmx_regnum_p (gdbarch, regnum))
335 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
336 else if (i386_ymm_regnum_p (gdbarch, regnum))
337 return i386_ymm_names[regnum - tdep->ymm0_regnum];
338 else if (i386_byte_regnum_p (gdbarch, regnum))
339 return i386_byte_names[regnum - tdep->al_regnum];
340 else if (i386_word_regnum_p (gdbarch, regnum))
341 return i386_word_names[regnum - tdep->ax_regnum];
343 internal_error (__FILE__, __LINE__, _("invalid regnum"));
346 /* Convert a dbx register number REG to the appropriate register
347 number used by GDB. */
350 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
352 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
354 /* This implements what GCC calls the "default" register map
355 (dbx_register_map[]). */
357 if (reg >= 0 && reg <= 7)
359 /* General-purpose registers. The debug info calls %ebp
360 register 4, and %esp register 5. */
367 else if (reg >= 12 && reg <= 19)
369 /* Floating-point registers. */
370 return reg - 12 + I387_ST0_REGNUM (tdep);
372 else if (reg >= 21 && reg <= 28)
375 int ymm0_regnum = tdep->ymm0_regnum;
378 && i386_xmm_regnum_p (gdbarch, reg))
379 return reg - 21 + ymm0_regnum;
381 return reg - 21 + I387_XMM0_REGNUM (tdep);
383 else if (reg >= 29 && reg <= 36)
386 return reg - 29 + I387_MM0_REGNUM (tdep);
389 /* This will hopefully provoke a warning. */
390 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
393 /* Convert SVR4 register number REG to the appropriate register number
397 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
399 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
401 /* This implements the GCC register map that tries to be compatible
402 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
404 /* The SVR4 register numbering includes %eip and %eflags, and
405 numbers the floating point registers differently. */
406 if (reg >= 0 && reg <= 9)
408 /* General-purpose registers. */
411 else if (reg >= 11 && reg <= 18)
413 /* Floating-point registers. */
414 return reg - 11 + I387_ST0_REGNUM (tdep);
416 else if (reg >= 21 && reg <= 36)
418 /* The SSE and MMX registers have the same numbers as with dbx. */
419 return i386_dbx_reg_to_regnum (gdbarch, reg);
424 case 37: return I387_FCTRL_REGNUM (tdep);
425 case 38: return I387_FSTAT_REGNUM (tdep);
426 case 39: return I387_MXCSR_REGNUM (tdep);
427 case 40: return I386_ES_REGNUM;
428 case 41: return I386_CS_REGNUM;
429 case 42: return I386_SS_REGNUM;
430 case 43: return I386_DS_REGNUM;
431 case 44: return I386_FS_REGNUM;
432 case 45: return I386_GS_REGNUM;
435 /* This will hopefully provoke a warning. */
436 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
441 /* This is the variable that is set with "set disassembly-flavor", and
442 its legitimate values. */
443 static const char att_flavor[] = "att";
444 static const char intel_flavor[] = "intel";
445 static const char *const valid_flavors[] =
451 static const char *disassembly_flavor = att_flavor;
454 /* Use the program counter to determine the contents and size of a
455 breakpoint instruction. Return a pointer to a string of bytes that
456 encode a breakpoint instruction, store the length of the string in
457 *LEN and optionally adjust *PC to point to the correct memory
458 location for inserting the breakpoint.
460 On the i386 we have a single breakpoint that fits in a single byte
461 and can be inserted anywhere.
463 This function is 64-bit safe. */
465 static const gdb_byte *
466 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
468 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */
470 *len = sizeof (break_insn);
474 /* Displaced instruction handling. */
476 /* Skip the legacy instruction prefixes in INSN.
477 Not all prefixes are valid for any particular insn
478 but we needn't care, the insn will fault if it's invalid.
479 The result is a pointer to the first opcode byte,
480 or NULL if we run off the end of the buffer. */
483 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
485 gdb_byte *end = insn + max_len;
491 case DATA_PREFIX_OPCODE:
492 case ADDR_PREFIX_OPCODE:
493 case CS_PREFIX_OPCODE:
494 case DS_PREFIX_OPCODE:
495 case ES_PREFIX_OPCODE:
496 case FS_PREFIX_OPCODE:
497 case GS_PREFIX_OPCODE:
498 case SS_PREFIX_OPCODE:
499 case LOCK_PREFIX_OPCODE:
500 case REPE_PREFIX_OPCODE:
501 case REPNE_PREFIX_OPCODE:
513 i386_absolute_jmp_p (const gdb_byte *insn)
515 /* jmp far (absolute address in operand). */
521 /* jump near, absolute indirect (/4). */
522 if ((insn[1] & 0x38) == 0x20)
525 /* jump far, absolute indirect (/5). */
526 if ((insn[1] & 0x38) == 0x28)
534 i386_absolute_call_p (const gdb_byte *insn)
536 /* call far, absolute. */
542 /* Call near, absolute indirect (/2). */
543 if ((insn[1] & 0x38) == 0x10)
546 /* Call far, absolute indirect (/3). */
547 if ((insn[1] & 0x38) == 0x18)
555 i386_ret_p (const gdb_byte *insn)
559 case 0xc2: /* ret near, pop N bytes. */
560 case 0xc3: /* ret near */
561 case 0xca: /* ret far, pop N bytes. */
562 case 0xcb: /* ret far */
563 case 0xcf: /* iret */
572 i386_call_p (const gdb_byte *insn)
574 if (i386_absolute_call_p (insn))
577 /* call near, relative. */
584 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
585 length in bytes. Otherwise, return zero. */
588 i386_syscall_p (const gdb_byte *insn, int *lengthp)
590 /* Is it 'int $0x80'? */
591 if ((insn[0] == 0xcd && insn[1] == 0x80)
592 /* Or is it 'sysenter'? */
593 || (insn[0] == 0x0f && insn[1] == 0x34)
594 /* Or is it 'syscall'? */
595 || (insn[0] == 0x0f && insn[1] == 0x05))
604 /* Some kernels may run one past a syscall insn, so we have to cope.
605 Otherwise this is just simple_displaced_step_copy_insn. */
607 struct displaced_step_closure *
608 i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
609 CORE_ADDR from, CORE_ADDR to,
610 struct regcache *regs)
612 size_t len = gdbarch_max_insn_length (gdbarch);
613 gdb_byte *buf = xmalloc (len);
615 read_memory (from, buf, len);
617 /* GDB may get control back after the insn after the syscall.
618 Presumably this is a kernel bug.
619 If this is a syscall, make sure there's a nop afterwards. */
624 insn = i386_skip_prefixes (buf, len);
625 if (insn != NULL && i386_syscall_p (insn, &syscall_length))
626 insn[syscall_length] = NOP_OPCODE;
629 write_memory (to, buf, len);
633 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
634 paddress (gdbarch, from), paddress (gdbarch, to));
635 displaced_step_dump_bytes (gdb_stdlog, buf, len);
638 return (struct displaced_step_closure *) buf;
641 /* Fix up the state of registers and memory after having single-stepped
642 a displaced instruction. */
645 i386_displaced_step_fixup (struct gdbarch *gdbarch,
646 struct displaced_step_closure *closure,
647 CORE_ADDR from, CORE_ADDR to,
648 struct regcache *regs)
650 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
652 /* The offset we applied to the instruction's address.
653 This could well be negative (when viewed as a signed 32-bit
654 value), but ULONGEST won't reflect that, so take care when
656 ULONGEST insn_offset = to - from;
658 /* Since we use simple_displaced_step_copy_insn, our closure is a
659 copy of the instruction. */
660 gdb_byte *insn = (gdb_byte *) closure;
661 /* The start of the insn, needed in case we see some prefixes. */
662 gdb_byte *insn_start = insn;
665 fprintf_unfiltered (gdb_stdlog,
666 "displaced: fixup (%s, %s), "
667 "insn = 0x%02x 0x%02x ...\n",
668 paddress (gdbarch, from), paddress (gdbarch, to),
671 /* The list of issues to contend with here is taken from
672 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
673 Yay for Free Software! */
675 /* Relocate the %eip, if necessary. */
677 /* The instruction recognizers we use assume any leading prefixes
678 have been skipped. */
680 /* This is the size of the buffer in closure. */
681 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
682 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
683 /* If there are too many prefixes, just ignore the insn.
684 It will fault when run. */
689 /* Except in the case of absolute or indirect jump or call
690 instructions, or a return instruction, the new eip is relative to
691 the displaced instruction; make it relative. Well, signal
692 handler returns don't need relocation either, but we use the
693 value of %eip to recognize those; see below. */
694 if (! i386_absolute_jmp_p (insn)
695 && ! i386_absolute_call_p (insn)
696 && ! i386_ret_p (insn))
701 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
703 /* A signal trampoline system call changes the %eip, resuming
704 execution of the main program after the signal handler has
705 returned. That makes them like 'return' instructions; we
706 shouldn't relocate %eip.
708 But most system calls don't, and we do need to relocate %eip.
710 Our heuristic for distinguishing these cases: if stepping
711 over the system call instruction left control directly after
712 the instruction, the we relocate --- control almost certainly
713 doesn't belong in the displaced copy. Otherwise, we assume
714 the instruction has put control where it belongs, and leave
715 it unrelocated. Goodness help us if there are PC-relative
717 if (i386_syscall_p (insn, &insn_len)
718 && orig_eip != to + (insn - insn_start) + insn_len
719 /* GDB can get control back after the insn after the syscall.
720 Presumably this is a kernel bug.
721 i386_displaced_step_copy_insn ensures its a nop,
722 we add one to the length for it. */
723 && orig_eip != to + (insn - insn_start) + insn_len + 1)
726 fprintf_unfiltered (gdb_stdlog,
727 "displaced: syscall changed %%eip; "
732 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
734 /* If we just stepped over a breakpoint insn, we don't backup
735 the pc on purpose; this is to match behaviour without
738 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
741 fprintf_unfiltered (gdb_stdlog,
743 "relocated %%eip from %s to %s\n",
744 paddress (gdbarch, orig_eip),
745 paddress (gdbarch, eip));
749 /* If the instruction was PUSHFL, then the TF bit will be set in the
750 pushed value, and should be cleared. We'll leave this for later,
751 since GDB already messes up the TF flag when stepping over a
754 /* If the instruction was a call, the return address now atop the
755 stack is the address following the copied instruction. We need
756 to make it the address following the original instruction. */
757 if (i386_call_p (insn))
761 const ULONGEST retaddr_len = 4;
763 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
764 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
765 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
766 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
769 fprintf_unfiltered (gdb_stdlog,
770 "displaced: relocated return addr at %s to %s\n",
771 paddress (gdbarch, esp),
772 paddress (gdbarch, retaddr));
777 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
779 target_write_memory (*to, buf, len);
784 i386_relocate_instruction (struct gdbarch *gdbarch,
785 CORE_ADDR *to, CORE_ADDR oldloc)
787 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
788 gdb_byte buf[I386_MAX_INSN_LEN];
789 int offset = 0, rel32, newrel;
791 gdb_byte *insn = buf;
793 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
795 insn_length = gdb_buffered_insn_length (gdbarch, insn,
796 I386_MAX_INSN_LEN, oldloc);
798 /* Get past the prefixes. */
799 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
801 /* Adjust calls with 32-bit relative addresses as push/jump, with
802 the address pushed being the location where the original call in
803 the user program would return to. */
806 gdb_byte push_buf[16];
807 unsigned int ret_addr;
809 /* Where "ret" in the original code will return to. */
810 ret_addr = oldloc + insn_length;
811 push_buf[0] = 0x68; /* pushq $... */
812 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
814 append_insns (to, 5, push_buf);
816 /* Convert the relative call to a relative jump. */
819 /* Adjust the destination offset. */
820 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
821 newrel = (oldloc - *to) + rel32;
822 store_signed_integer (insn + 1, 4, byte_order, newrel);
825 fprintf_unfiltered (gdb_stdlog,
826 "Adjusted insn rel32=%s at %s to"
828 hex_string (rel32), paddress (gdbarch, oldloc),
829 hex_string (newrel), paddress (gdbarch, *to));
831 /* Write the adjusted jump into its displaced location. */
832 append_insns (to, 5, insn);
836 /* Adjust jumps with 32-bit relative addresses. Calls are already
840 /* Adjust conditional jumps. */
841 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
846 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
847 newrel = (oldloc - *to) + rel32;
848 store_signed_integer (insn + offset, 4, byte_order, newrel);
850 fprintf_unfiltered (gdb_stdlog,
851 "Adjusted insn rel32=%s at %s to"
853 hex_string (rel32), paddress (gdbarch, oldloc),
854 hex_string (newrel), paddress (gdbarch, *to));
857 /* Write the adjusted instructions into their displaced
859 append_insns (to, insn_length, buf);
863 #ifdef I386_REGNO_TO_SYMMETRY
864 #error "The Sequent Symmetry is no longer supported."
867 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
868 and %esp "belong" to the calling function. Therefore these
869 registers should be saved if they're going to be modified. */
871 /* The maximum number of saved registers. This should include all
872 registers mentioned above, and %eip. */
873 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
875 struct i386_frame_cache
883 /* Saved registers. */
884 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
889 /* Stack space reserved for local variables. */
893 /* Allocate and initialize a frame cache. */
895 static struct i386_frame_cache *
896 i386_alloc_frame_cache (void)
898 struct i386_frame_cache *cache;
901 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
906 cache->sp_offset = -4;
909 /* Saved registers. We initialize these to -1 since zero is a valid
910 offset (that's where %ebp is supposed to be stored). */
911 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
912 cache->saved_regs[i] = -1;
914 cache->saved_sp_reg = -1;
915 cache->pc_in_eax = 0;
917 /* Frameless until proven otherwise. */
923 /* If the instruction at PC is a jump, return the address of its
924 target. Otherwise, return PC. */
927 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
929 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
934 if (target_read_code (pc, &op, 1))
941 op = read_code_unsigned_integer (pc + 1, 1, byte_order);
947 /* Relative jump: if data16 == 0, disp32, else disp16. */
950 delta = read_memory_integer (pc + 2, 2, byte_order);
952 /* Include the size of the jmp instruction (including the
958 delta = read_memory_integer (pc + 1, 4, byte_order);
960 /* Include the size of the jmp instruction. */
965 /* Relative jump, disp8 (ignore data16). */
966 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
975 /* Check whether PC points at a prologue for a function returning a
976 structure or union. If so, it updates CACHE and returns the
977 address of the first instruction after the code sequence that
978 removes the "hidden" argument from the stack or CURRENT_PC,
979 whichever is smaller. Otherwise, return PC. */
982 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
983 struct i386_frame_cache *cache)
985 /* Functions that return a structure or union start with:
988 xchgl %eax, (%esp) 0x87 0x04 0x24
989 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
991 (the System V compiler puts out the second `xchg' instruction,
992 and the assembler doesn't try to optimize it, so the 'sib' form
993 gets generated). This sequence is used to get the address of the
994 return buffer for a function that returns a structure. */
995 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
996 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
1000 if (current_pc <= pc)
1003 if (target_read_code (pc, &op, 1))
1006 if (op != 0x58) /* popl %eax */
1009 if (target_read_code (pc + 1, buf, 4))
1012 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
1015 if (current_pc == pc)
1017 cache->sp_offset += 4;
1021 if (current_pc == pc + 1)
1023 cache->pc_in_eax = 1;
1027 if (buf[1] == proto1[1])
1034 i386_skip_probe (CORE_ADDR pc)
1036 /* A function may start with
1050 if (target_read_code (pc, &op, 1))
1053 if (op == 0x68 || op == 0x6a)
1057 /* Skip past the `pushl' instruction; it has either a one-byte or a
1058 four-byte operand, depending on the opcode. */
1064 /* Read the following 8 bytes, which should be `call _probe' (6
1065 bytes) followed by `addl $4,%esp' (2 bytes). */
1066 read_memory (pc + delta, buf, sizeof (buf));
1067 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
1068 pc += delta + sizeof (buf);
1074 /* GCC 4.1 and later, can put code in the prologue to realign the
1075 stack pointer. Check whether PC points to such code, and update
1076 CACHE accordingly. Return the first instruction after the code
1077 sequence or CURRENT_PC, whichever is smaller. If we don't
1078 recognize the code, return PC. */
1081 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1082 struct i386_frame_cache *cache)
1084 /* There are 2 code sequences to re-align stack before the frame
1087 1. Use a caller-saved saved register:
1093 2. Use a callee-saved saved register:
1100 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1102 0x83 0xe4 0xf0 andl $-16, %esp
1103 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1108 int offset, offset_and;
1109 static int regnums[8] = {
1110 I386_EAX_REGNUM, /* %eax */
1111 I386_ECX_REGNUM, /* %ecx */
1112 I386_EDX_REGNUM, /* %edx */
1113 I386_EBX_REGNUM, /* %ebx */
1114 I386_ESP_REGNUM, /* %esp */
1115 I386_EBP_REGNUM, /* %ebp */
1116 I386_ESI_REGNUM, /* %esi */
1117 I386_EDI_REGNUM /* %edi */
1120 if (target_read_code (pc, buf, sizeof buf))
1123 /* Check caller-saved saved register. The first instruction has
1124 to be "leal 4(%esp), %reg". */
1125 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1127 /* MOD must be binary 10 and R/M must be binary 100. */
1128 if ((buf[1] & 0xc7) != 0x44)
1131 /* REG has register number. */
1132 reg = (buf[1] >> 3) & 7;
1137 /* Check callee-saved saved register. The first instruction
1138 has to be "pushl %reg". */
1139 if ((buf[0] & 0xf8) != 0x50)
1145 /* The next instruction has to be "leal 8(%esp), %reg". */
1146 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1149 /* MOD must be binary 10 and R/M must be binary 100. */
1150 if ((buf[2] & 0xc7) != 0x44)
1153 /* REG has register number. Registers in pushl and leal have to
1155 if (reg != ((buf[2] >> 3) & 7))
1161 /* Rigister can't be %esp nor %ebp. */
1162 if (reg == 4 || reg == 5)
1165 /* The next instruction has to be "andl $-XXX, %esp". */
1166 if (buf[offset + 1] != 0xe4
1167 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1170 offset_and = offset;
1171 offset += buf[offset] == 0x81 ? 6 : 3;
1173 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1174 0xfc. REG must be binary 110 and MOD must be binary 01. */
1175 if (buf[offset] != 0xff
1176 || buf[offset + 2] != 0xfc
1177 || (buf[offset + 1] & 0xf8) != 0x70)
1180 /* R/M has register. Registers in leal and pushl have to be the
1182 if (reg != (buf[offset + 1] & 7))
1185 if (current_pc > pc + offset_and)
1186 cache->saved_sp_reg = regnums[reg];
1188 return min (pc + offset + 3, current_pc);
1191 /* Maximum instruction length we need to handle. */
1192 #define I386_MAX_MATCHED_INSN_LEN 6
1194 /* Instruction description. */
1198 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
1199 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
1202 /* Return whether instruction at PC matches PATTERN. */
1205 i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern)
1209 if (target_read_code (pc, &op, 1))
1212 if ((op & pattern.mask[0]) == pattern.insn[0])
1214 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1215 int insn_matched = 1;
1218 gdb_assert (pattern.len > 1);
1219 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN);
1221 if (target_read_code (pc + 1, buf, pattern.len - 1))
1224 for (i = 1; i < pattern.len; i++)
1226 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i])
1229 return insn_matched;
1234 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1235 the first instruction description that matches. Otherwise, return
1238 static struct i386_insn *
1239 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns)
1241 struct i386_insn *pattern;
1243 for (pattern = insn_patterns; pattern->len > 0; pattern++)
1245 if (i386_match_pattern (pc, *pattern))
1252 /* Return whether PC points inside a sequence of instructions that
1253 matches INSN_PATTERNS. */
1256 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns)
1258 CORE_ADDR current_pc;
1260 struct i386_insn *insn;
1262 insn = i386_match_insn (pc, insn_patterns);
1267 ix = insn - insn_patterns;
1268 for (i = ix - 1; i >= 0; i--)
1270 current_pc -= insn_patterns[i].len;
1272 if (!i386_match_pattern (current_pc, insn_patterns[i]))
1276 current_pc = pc + insn->len;
1277 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++)
1279 if (!i386_match_pattern (current_pc, *insn))
1282 current_pc += insn->len;
1288 /* Some special instructions that might be migrated by GCC into the
1289 part of the prologue that sets up the new stack frame. Because the
1290 stack frame hasn't been setup yet, no registers have been saved
1291 yet, and only the scratch registers %eax, %ecx and %edx can be
1294 struct i386_insn i386_frame_setup_skip_insns[] =
1296 /* Check for `movb imm8, r' and `movl imm32, r'.
1298 ??? Should we handle 16-bit operand-sizes here? */
1300 /* `movb imm8, %al' and `movb imm8, %ah' */
1301 /* `movb imm8, %cl' and `movb imm8, %ch' */
1302 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1303 /* `movb imm8, %dl' and `movb imm8, %dh' */
1304 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1305 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1306 { 5, { 0xb8 }, { 0xfe } },
1307 /* `movl imm32, %edx' */
1308 { 5, { 0xba }, { 0xff } },
1310 /* Check for `mov imm32, r32'. Note that there is an alternative
1311 encoding for `mov m32, %eax'.
1313 ??? Should we handle SIB adressing here?
1314 ??? Should we handle 16-bit operand-sizes here? */
1316 /* `movl m32, %eax' */
1317 { 5, { 0xa1 }, { 0xff } },
1318 /* `movl m32, %eax' and `mov; m32, %ecx' */
1319 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1320 /* `movl m32, %edx' */
1321 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1323 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1324 Because of the symmetry, there are actually two ways to encode
1325 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1326 opcode bytes 0x31 and 0x33 for `xorl'. */
1328 /* `subl %eax, %eax' */
1329 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1330 /* `subl %ecx, %ecx' */
1331 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1332 /* `subl %edx, %edx' */
1333 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1334 /* `xorl %eax, %eax' */
1335 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1336 /* `xorl %ecx, %ecx' */
1337 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1338 /* `xorl %edx, %edx' */
1339 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1344 /* Check whether PC points to a no-op instruction. */
1346 i386_skip_noop (CORE_ADDR pc)
1351 if (target_read_code (pc, &op, 1))
1357 /* Ignore `nop' instruction. */
1361 if (target_read_code (pc, &op, 1))
1365 /* Ignore no-op instruction `mov %edi, %edi'.
1366 Microsoft system dlls often start with
1367 a `mov %edi,%edi' instruction.
1368 The 5 bytes before the function start are
1369 filled with `nop' instructions.
1370 This pattern can be used for hot-patching:
1371 The `mov %edi, %edi' instruction can be replaced by a
1372 near jump to the location of the 5 `nop' instructions
1373 which can be replaced by a 32-bit jump to anywhere
1374 in the 32-bit address space. */
1376 else if (op == 0x8b)
1378 if (target_read_code (pc + 1, &op, 1))
1384 if (target_read_code (pc, &op, 1))
1394 /* Check whether PC points at a code that sets up a new stack frame.
1395 If so, it updates CACHE and returns the address of the first
1396 instruction after the sequence that sets up the frame or LIMIT,
1397 whichever is smaller. If we don't recognize the code, return PC. */
1400 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1401 CORE_ADDR pc, CORE_ADDR limit,
1402 struct i386_frame_cache *cache)
1404 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1405 struct i386_insn *insn;
1412 if (target_read_code (pc, &op, 1))
1415 if (op == 0x55) /* pushl %ebp */
1417 /* Take into account that we've executed the `pushl %ebp' that
1418 starts this instruction sequence. */
1419 cache->saved_regs[I386_EBP_REGNUM] = 0;
1420 cache->sp_offset += 4;
1423 /* If that's all, return now. */
1427 /* Check for some special instructions that might be migrated by
1428 GCC into the prologue and skip them. At this point in the
1429 prologue, code should only touch the scratch registers %eax,
1430 %ecx and %edx, so while the number of posibilities is sheer,
1433 Make sure we only skip these instructions if we later see the
1434 `movl %esp, %ebp' that actually sets up the frame. */
1435 while (pc + skip < limit)
1437 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1444 /* If that's all, return now. */
1445 if (limit <= pc + skip)
1448 if (target_read_code (pc + skip, &op, 1))
1451 /* The i386 prologue looks like
1457 and a different prologue can be generated for atom.
1461 lea -0x10(%esp),%esp
1463 We handle both of them here. */
1467 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1469 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1475 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1480 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1481 if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order)
1490 /* OK, we actually have a frame. We just don't know how large
1491 it is yet. Set its size to zero. We'll adjust it if
1492 necessary. We also now commit to skipping the special
1493 instructions mentioned before. */
1496 /* If that's all, return now. */
1500 /* Check for stack adjustment
1506 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1507 reg, so we don't have to worry about a data16 prefix. */
1508 if (target_read_code (pc, &op, 1))
1512 /* `subl' with 8-bit immediate. */
1513 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1514 /* Some instruction starting with 0x83 other than `subl'. */
1517 /* `subl' with signed 8-bit immediate (though it wouldn't
1518 make sense to be negative). */
1519 cache->locals = read_code_integer (pc + 2, 1, byte_order);
1522 else if (op == 0x81)
1524 /* Maybe it is `subl' with a 32-bit immediate. */
1525 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1526 /* Some instruction starting with 0x81 other than `subl'. */
1529 /* It is `subl' with a 32-bit immediate. */
1530 cache->locals = read_code_integer (pc + 2, 4, byte_order);
1533 else if (op == 0x8d)
1535 /* The ModR/M byte is 0x64. */
1536 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64)
1538 /* 'lea' with 8-bit displacement. */
1539 cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order);
1544 /* Some instruction other than `subl' nor 'lea'. */
1548 else if (op == 0xc8) /* enter */
1550 cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order);
1557 /* Check whether PC points at code that saves registers on the stack.
1558 If so, it updates CACHE and returns the address of the first
1559 instruction after the register saves or CURRENT_PC, whichever is
1560 smaller. Otherwise, return PC. */
1563 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1564 struct i386_frame_cache *cache)
1566 CORE_ADDR offset = 0;
1570 if (cache->locals > 0)
1571 offset -= cache->locals;
1572 for (i = 0; i < 8 && pc < current_pc; i++)
1574 if (target_read_code (pc, &op, 1))
1576 if (op < 0x50 || op > 0x57)
1580 cache->saved_regs[op - 0x50] = offset;
1581 cache->sp_offset += 4;
1588 /* Do a full analysis of the prologue at PC and update CACHE
1589 accordingly. Bail out early if CURRENT_PC is reached. Return the
1590 address where the analysis stopped.
1592 We handle these cases:
1594 The startup sequence can be at the start of the function, or the
1595 function can start with a branch to startup code at the end.
1597 %ebp can be set up with either the 'enter' instruction, or "pushl
1598 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1599 once used in the System V compiler).
1601 Local space is allocated just below the saved %ebp by either the
1602 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1603 16-bit unsigned argument for space to allocate, and the 'addl'
1604 instruction could have either a signed byte, or 32-bit immediate.
1606 Next, the registers used by this function are pushed. With the
1607 System V compiler they will always be in the order: %edi, %esi,
1608 %ebx (and sometimes a harmless bug causes it to also save but not
1609 restore %eax); however, the code below is willing to see the pushes
1610 in any order, and will handle up to 8 of them.
1612 If the setup sequence is at the end of the function, then the next
1613 instruction will be a branch back to the start. */
1616 i386_analyze_prologue (struct gdbarch *gdbarch,
1617 CORE_ADDR pc, CORE_ADDR current_pc,
1618 struct i386_frame_cache *cache)
1620 pc = i386_skip_noop (pc);
1621 pc = i386_follow_jump (gdbarch, pc);
1622 pc = i386_analyze_struct_return (pc, current_pc, cache);
1623 pc = i386_skip_probe (pc);
1624 pc = i386_analyze_stack_align (pc, current_pc, cache);
1625 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1626 return i386_analyze_register_saves (pc, current_pc, cache);
1629 /* Return PC of first real instruction. */
1632 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1634 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1636 static gdb_byte pic_pat[6] =
1638 0xe8, 0, 0, 0, 0, /* call 0x0 */
1639 0x5b, /* popl %ebx */
1641 struct i386_frame_cache cache;
1645 CORE_ADDR func_addr;
1647 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
1649 CORE_ADDR post_prologue_pc
1650 = skip_prologue_using_sal (gdbarch, func_addr);
1651 struct symtab *s = find_pc_symtab (func_addr);
1653 /* Clang always emits a line note before the prologue and another
1654 one after. We trust clang to emit usable line notes. */
1655 if (post_prologue_pc
1657 && s->producer != NULL
1658 && strncmp (s->producer, "clang ", sizeof ("clang ") - 1) == 0))
1659 return max (start_pc, post_prologue_pc);
1663 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1664 if (cache.locals < 0)
1667 /* Found valid frame setup. */
1669 /* The native cc on SVR4 in -K PIC mode inserts the following code
1670 to get the address of the global offset table (GOT) into register
1675 movl %ebx,x(%ebp) (optional)
1678 This code is with the rest of the prologue (at the end of the
1679 function), so we have to skip it to get to the first real
1680 instruction at the start of the function. */
1682 for (i = 0; i < 6; i++)
1684 if (target_read_code (pc + i, &op, 1))
1687 if (pic_pat[i] != op)
1694 if (target_read_code (pc + delta, &op, 1))
1697 if (op == 0x89) /* movl %ebx, x(%ebp) */
1699 op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order);
1701 if (op == 0x5d) /* One byte offset from %ebp. */
1703 else if (op == 0x9d) /* Four byte offset from %ebp. */
1705 else /* Unexpected instruction. */
1708 if (target_read_code (pc + delta, &op, 1))
1713 if (delta > 0 && op == 0x81
1714 && read_code_unsigned_integer (pc + delta + 1, 1, byte_order)
1721 /* If the function starts with a branch (to startup code at the end)
1722 the last instruction should bring us back to the first
1723 instruction of the real code. */
1724 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1725 pc = i386_follow_jump (gdbarch, pc);
1730 /* Check that the code pointed to by PC corresponds to a call to
1731 __main, skip it if so. Return PC otherwise. */
1734 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1736 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1739 if (target_read_code (pc, &op, 1))
1745 if (target_read_code (pc + 1, buf, sizeof buf) == 0)
1747 /* Make sure address is computed correctly as a 32bit
1748 integer even if CORE_ADDR is 64 bit wide. */
1749 struct bound_minimal_symbol s;
1750 CORE_ADDR call_dest;
1752 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1753 call_dest = call_dest & 0xffffffffU;
1754 s = lookup_minimal_symbol_by_pc (call_dest);
1755 if (s.minsym != NULL
1756 && SYMBOL_LINKAGE_NAME (s.minsym) != NULL
1757 && strcmp (SYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0)
1765 /* This function is 64-bit safe. */
1768 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1772 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1773 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1777 /* Normal frames. */
1780 i386_frame_cache_1 (struct frame_info *this_frame,
1781 struct i386_frame_cache *cache)
1783 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1784 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1788 cache->pc = get_frame_func (this_frame);
1790 /* In principle, for normal frames, %ebp holds the frame pointer,
1791 which holds the base address for the current stack frame.
1792 However, for functions that don't need it, the frame pointer is
1793 optional. For these "frameless" functions the frame pointer is
1794 actually the frame pointer of the calling frame. Signal
1795 trampolines are just a special case of a "frameless" function.
1796 They (usually) share their frame pointer with the frame that was
1797 in progress when the signal occurred. */
1799 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1800 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1801 if (cache->base == 0)
1807 /* For normal frames, %eip is stored at 4(%ebp). */
1808 cache->saved_regs[I386_EIP_REGNUM] = 4;
1811 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
1814 if (cache->locals < 0)
1816 /* We didn't find a valid frame, which means that CACHE->base
1817 currently holds the frame pointer for our calling frame. If
1818 we're at the start of a function, or somewhere half-way its
1819 prologue, the function's frame probably hasn't been fully
1820 setup yet. Try to reconstruct the base address for the stack
1821 frame by looking at the stack pointer. For truly "frameless"
1822 functions this might work too. */
1824 if (cache->saved_sp_reg != -1)
1826 /* Saved stack pointer has been saved. */
1827 get_frame_register (this_frame, cache->saved_sp_reg, buf);
1828 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
1830 /* We're halfway aligning the stack. */
1831 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
1832 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
1834 /* This will be added back below. */
1835 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
1837 else if (cache->pc != 0
1838 || target_read_code (get_frame_pc (this_frame), buf, 1))
1840 /* We're in a known function, but did not find a frame
1841 setup. Assume that the function does not use %ebp.
1842 Alternatively, we may have jumped to an invalid
1843 address; in that case there is definitely no new
1845 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1846 cache->base = extract_unsigned_integer (buf, 4, byte_order)
1850 /* We're in an unknown function. We could not find the start
1851 of the function to analyze the prologue; our best option is
1852 to assume a typical frame layout with the caller's %ebp
1854 cache->saved_regs[I386_EBP_REGNUM] = 0;
1857 if (cache->saved_sp_reg != -1)
1859 /* Saved stack pointer has been saved (but the SAVED_SP_REG
1860 register may be unavailable). */
1861 if (cache->saved_sp == 0
1862 && deprecated_frame_register_read (this_frame,
1863 cache->saved_sp_reg, buf))
1864 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
1866 /* Now that we have the base address for the stack frame we can
1867 calculate the value of %esp in the calling frame. */
1868 else if (cache->saved_sp == 0)
1869 cache->saved_sp = cache->base + 8;
1871 /* Adjust all the saved registers such that they contain addresses
1872 instead of offsets. */
1873 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1874 if (cache->saved_regs[i] != -1)
1875 cache->saved_regs[i] += cache->base;
1880 static struct i386_frame_cache *
1881 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
1883 volatile struct gdb_exception ex;
1884 struct i386_frame_cache *cache;
1889 cache = i386_alloc_frame_cache ();
1890 *this_cache = cache;
1892 TRY_CATCH (ex, RETURN_MASK_ERROR)
1894 i386_frame_cache_1 (this_frame, cache);
1896 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
1897 throw_exception (ex);
1903 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
1904 struct frame_id *this_id)
1906 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1909 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
1910 else if (cache->base == 0)
1912 /* This marks the outermost frame. */
1916 /* See the end of i386_push_dummy_call. */
1917 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
1921 static enum unwind_stop_reason
1922 i386_frame_unwind_stop_reason (struct frame_info *this_frame,
1925 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1928 return UNWIND_UNAVAILABLE;
1930 /* This marks the outermost frame. */
1931 if (cache->base == 0)
1932 return UNWIND_OUTERMOST;
1934 return UNWIND_NO_REASON;
1937 static struct value *
1938 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
1941 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1943 gdb_assert (regnum >= 0);
1945 /* The System V ABI says that:
1947 "The flags register contains the system flags, such as the
1948 direction flag and the carry flag. The direction flag must be
1949 set to the forward (that is, zero) direction before entry and
1950 upon exit from a function. Other user flags have no specified
1951 role in the standard calling sequence and are not preserved."
1953 To guarantee the "upon exit" part of that statement we fake a
1954 saved flags register that has its direction flag cleared.
1956 Note that GCC doesn't seem to rely on the fact that the direction
1957 flag is cleared after a function return; it always explicitly
1958 clears the flag before operations where it matters.
1960 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1961 right thing to do. The way we fake the flags register here makes
1962 it impossible to change it. */
1964 if (regnum == I386_EFLAGS_REGNUM)
1968 val = get_frame_register_unsigned (this_frame, regnum);
1970 return frame_unwind_got_constant (this_frame, regnum, val);
1973 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
1974 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
1976 if (regnum == I386_ESP_REGNUM
1977 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1))
1979 /* If the SP has been saved, but we don't know where, then this
1980 means that SAVED_SP_REG register was found unavailable back
1981 when we built the cache. */
1982 if (cache->saved_sp == 0)
1983 return frame_unwind_got_register (this_frame, regnum,
1984 cache->saved_sp_reg);
1986 return frame_unwind_got_constant (this_frame, regnum,
1990 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
1991 return frame_unwind_got_memory (this_frame, regnum,
1992 cache->saved_regs[regnum]);
1994 return frame_unwind_got_register (this_frame, regnum, regnum);
1997 static const struct frame_unwind i386_frame_unwind =
2000 i386_frame_unwind_stop_reason,
2002 i386_frame_prev_register,
2004 default_frame_sniffer
2007 /* Normal frames, but in a function epilogue. */
2009 /* The epilogue is defined here as the 'ret' instruction, which will
2010 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2011 the function's stack frame. */
2014 i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2017 struct symtab *symtab;
2019 symtab = find_pc_symtab (pc);
2020 if (symtab && symtab->epilogue_unwind_valid)
2023 if (target_read_memory (pc, &insn, 1))
2024 return 0; /* Can't read memory at pc. */
2026 if (insn != 0xc3) /* 'ret' instruction. */
2033 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
2034 struct frame_info *this_frame,
2035 void **this_prologue_cache)
2037 if (frame_relative_level (this_frame) == 0)
2038 return i386_in_function_epilogue_p (get_frame_arch (this_frame),
2039 get_frame_pc (this_frame));
2044 static struct i386_frame_cache *
2045 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2047 volatile struct gdb_exception ex;
2048 struct i386_frame_cache *cache;
2054 cache = i386_alloc_frame_cache ();
2055 *this_cache = cache;
2057 TRY_CATCH (ex, RETURN_MASK_ERROR)
2059 cache->pc = get_frame_func (this_frame);
2061 /* At this point the stack looks as if we just entered the
2062 function, with the return address at the top of the
2064 sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM);
2065 cache->base = sp + cache->sp_offset;
2066 cache->saved_sp = cache->base + 8;
2067 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
2071 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2072 throw_exception (ex);
2077 static enum unwind_stop_reason
2078 i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2081 struct i386_frame_cache *cache =
2082 i386_epilogue_frame_cache (this_frame, this_cache);
2085 return UNWIND_UNAVAILABLE;
2087 return UNWIND_NO_REASON;
2091 i386_epilogue_frame_this_id (struct frame_info *this_frame,
2093 struct frame_id *this_id)
2095 struct i386_frame_cache *cache =
2096 i386_epilogue_frame_cache (this_frame, this_cache);
2099 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2101 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2104 static struct value *
2105 i386_epilogue_frame_prev_register (struct frame_info *this_frame,
2106 void **this_cache, int regnum)
2108 /* Make sure we've initialized the cache. */
2109 i386_epilogue_frame_cache (this_frame, this_cache);
2111 return i386_frame_prev_register (this_frame, this_cache, regnum);
2114 static const struct frame_unwind i386_epilogue_frame_unwind =
2117 i386_epilogue_frame_unwind_stop_reason,
2118 i386_epilogue_frame_this_id,
2119 i386_epilogue_frame_prev_register,
2121 i386_epilogue_frame_sniffer
2125 /* Stack-based trampolines. */
2127 /* These trampolines are used on cross x86 targets, when taking the
2128 address of a nested function. When executing these trampolines,
2129 no stack frame is set up, so we are in a similar situation as in
2130 epilogues and i386_epilogue_frame_this_id can be re-used. */
2132 /* Static chain passed in register. */
2134 struct i386_insn i386_tramp_chain_in_reg_insns[] =
2136 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2137 { 5, { 0xb8 }, { 0xfe } },
2140 { 5, { 0xe9 }, { 0xff } },
2145 /* Static chain passed on stack (when regparm=3). */
2147 struct i386_insn i386_tramp_chain_on_stack_insns[] =
2150 { 5, { 0x68 }, { 0xff } },
2153 { 5, { 0xe9 }, { 0xff } },
2158 /* Return whether PC points inside a stack trampoline. */
2161 i386_in_stack_tramp_p (CORE_ADDR pc)
2166 /* A stack trampoline is detected if no name is associated
2167 to the current pc and if it points inside a trampoline
2170 find_pc_partial_function (pc, &name, NULL, NULL);
2174 if (target_read_memory (pc, &insn, 1))
2177 if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns)
2178 && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns))
2185 i386_stack_tramp_frame_sniffer (const struct frame_unwind *self,
2186 struct frame_info *this_frame,
2189 if (frame_relative_level (this_frame) == 0)
2190 return i386_in_stack_tramp_p (get_frame_pc (this_frame));
2195 static const struct frame_unwind i386_stack_tramp_frame_unwind =
2198 i386_epilogue_frame_unwind_stop_reason,
2199 i386_epilogue_frame_this_id,
2200 i386_epilogue_frame_prev_register,
2202 i386_stack_tramp_frame_sniffer
2205 /* Generate a bytecode expression to get the value of the saved PC. */
2208 i386_gen_return_address (struct gdbarch *gdbarch,
2209 struct agent_expr *ax, struct axs_value *value,
2212 /* The following sequence assumes the traditional use of the base
2214 ax_reg (ax, I386_EBP_REGNUM);
2216 ax_simple (ax, aop_add);
2217 value->type = register_type (gdbarch, I386_EIP_REGNUM);
2218 value->kind = axs_lvalue_memory;
2222 /* Signal trampolines. */
2224 static struct i386_frame_cache *
2225 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2227 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2228 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2229 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2230 volatile struct gdb_exception ex;
2231 struct i386_frame_cache *cache;
2238 cache = i386_alloc_frame_cache ();
2240 TRY_CATCH (ex, RETURN_MASK_ERROR)
2242 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2243 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
2245 addr = tdep->sigcontext_addr (this_frame);
2246 if (tdep->sc_reg_offset)
2250 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
2252 for (i = 0; i < tdep->sc_num_regs; i++)
2253 if (tdep->sc_reg_offset[i] != -1)
2254 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2258 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
2259 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
2264 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2265 throw_exception (ex);
2267 *this_cache = cache;
2271 static enum unwind_stop_reason
2272 i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2275 struct i386_frame_cache *cache =
2276 i386_sigtramp_frame_cache (this_frame, this_cache);
2279 return UNWIND_UNAVAILABLE;
2281 return UNWIND_NO_REASON;
2285 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
2286 struct frame_id *this_id)
2288 struct i386_frame_cache *cache =
2289 i386_sigtramp_frame_cache (this_frame, this_cache);
2292 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2295 /* See the end of i386_push_dummy_call. */
2296 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
2300 static struct value *
2301 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
2302 void **this_cache, int regnum)
2304 /* Make sure we've initialized the cache. */
2305 i386_sigtramp_frame_cache (this_frame, this_cache);
2307 return i386_frame_prev_register (this_frame, this_cache, regnum);
2311 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
2312 struct frame_info *this_frame,
2313 void **this_prologue_cache)
2315 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2317 /* We shouldn't even bother if we don't have a sigcontext_addr
2319 if (tdep->sigcontext_addr == NULL)
2322 if (tdep->sigtramp_p != NULL)
2324 if (tdep->sigtramp_p (this_frame))
2328 if (tdep->sigtramp_start != 0)
2330 CORE_ADDR pc = get_frame_pc (this_frame);
2332 gdb_assert (tdep->sigtramp_end != 0);
2333 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2340 static const struct frame_unwind i386_sigtramp_frame_unwind =
2343 i386_sigtramp_frame_unwind_stop_reason,
2344 i386_sigtramp_frame_this_id,
2345 i386_sigtramp_frame_prev_register,
2347 i386_sigtramp_frame_sniffer
2352 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
2354 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2359 static const struct frame_base i386_frame_base =
2362 i386_frame_base_address,
2363 i386_frame_base_address,
2364 i386_frame_base_address
2367 static struct frame_id
2368 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2372 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
2374 /* See the end of i386_push_dummy_call. */
2375 return frame_id_build (fp + 8, get_frame_pc (this_frame));
2378 /* _Decimal128 function return values need 16-byte alignment on the
2382 i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2384 return sp & -(CORE_ADDR)16;
2388 /* Figure out where the longjmp will land. Slurp the args out of the
2389 stack. We expect the first arg to be a pointer to the jmp_buf
2390 structure from which we extract the address that we will land at.
2391 This address is copied into PC. This routine returns non-zero on
2395 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2398 CORE_ADDR sp, jb_addr;
2399 struct gdbarch *gdbarch = get_frame_arch (frame);
2400 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2401 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2403 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2404 longjmp will land. */
2405 if (jb_pc_offset == -1)
2408 get_frame_register (frame, I386_ESP_REGNUM, buf);
2409 sp = extract_unsigned_integer (buf, 4, byte_order);
2410 if (target_read_memory (sp + 4, buf, 4))
2413 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
2414 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
2417 *pc = extract_unsigned_integer (buf, 4, byte_order);
2422 /* Check whether TYPE must be 16-byte-aligned when passed as a
2423 function argument. 16-byte vectors, _Decimal128 and structures or
2424 unions containing such types must be 16-byte-aligned; other
2425 arguments are 4-byte-aligned. */
2428 i386_16_byte_align_p (struct type *type)
2430 type = check_typedef (type);
2431 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
2432 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
2433 && TYPE_LENGTH (type) == 16)
2435 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2436 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
2437 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2438 || TYPE_CODE (type) == TYPE_CODE_UNION)
2441 for (i = 0; i < TYPE_NFIELDS (type); i++)
2443 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
2450 /* Implementation for set_gdbarch_push_dummy_code. */
2453 i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
2454 struct value **args, int nargs, struct type *value_type,
2455 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
2456 struct regcache *regcache)
2458 /* Use 0xcc breakpoint - 1 byte. */
2462 /* Keep the stack aligned. */
2467 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2468 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2469 struct value **args, CORE_ADDR sp, int struct_return,
2470 CORE_ADDR struct_addr)
2472 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2478 /* Determine the total space required for arguments and struct
2479 return address in a first pass (allowing for 16-byte-aligned
2480 arguments), then push arguments in a second pass. */
2482 for (write_pass = 0; write_pass < 2; write_pass++)
2484 int args_space_used = 0;
2490 /* Push value address. */
2491 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2492 write_memory (sp, buf, 4);
2493 args_space_used += 4;
2499 for (i = 0; i < nargs; i++)
2501 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2505 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2506 args_space_used = align_up (args_space_used, 16);
2508 write_memory (sp + args_space_used,
2509 value_contents_all (args[i]), len);
2510 /* The System V ABI says that:
2512 "An argument's size is increased, if necessary, to make it a
2513 multiple of [32-bit] words. This may require tail padding,
2514 depending on the size of the argument."
2516 This makes sure the stack stays word-aligned. */
2517 args_space_used += align_up (len, 4);
2521 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2522 args_space = align_up (args_space, 16);
2523 args_space += align_up (len, 4);
2531 /* The original System V ABI only requires word alignment,
2532 but modern incarnations need 16-byte alignment in order
2533 to support SSE. Since wasting a few bytes here isn't
2534 harmful we unconditionally enforce 16-byte alignment. */
2539 /* Store return address. */
2541 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2542 write_memory (sp, buf, 4);
2544 /* Finally, update the stack pointer... */
2545 store_unsigned_integer (buf, 4, byte_order, sp);
2546 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
2548 /* ...and fake a frame pointer. */
2549 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
2551 /* MarkK wrote: This "+ 8" is all over the place:
2552 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2553 i386_dummy_id). It's there, since all frame unwinders for
2554 a given target have to agree (within a certain margin) on the
2555 definition of the stack address of a frame. Otherwise frame id
2556 comparison might not work correctly. Since DWARF2/GCC uses the
2557 stack address *before* the function call as a frame's CFA. On
2558 the i386, when %ebp is used as a frame pointer, the offset
2559 between the contents %ebp and the CFA as defined by GCC. */
2563 /* These registers are used for returning integers (and on some
2564 targets also for returning `struct' and `union' values when their
2565 size and alignment match an integer type). */
2566 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2567 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2569 /* Read, for architecture GDBARCH, a function return value of TYPE
2570 from REGCACHE, and copy that into VALBUF. */
2573 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2574 struct regcache *regcache, gdb_byte *valbuf)
2576 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2577 int len = TYPE_LENGTH (type);
2578 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2580 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2582 if (tdep->st0_regnum < 0)
2584 warning (_("Cannot find floating-point return value."));
2585 memset (valbuf, 0, len);
2589 /* Floating-point return values can be found in %st(0). Convert
2590 its contents to the desired type. This is probably not
2591 exactly how it would happen on the target itself, but it is
2592 the best we can do. */
2593 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2594 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
2598 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2599 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2601 if (len <= low_size)
2603 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2604 memcpy (valbuf, buf, len);
2606 else if (len <= (low_size + high_size))
2608 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2609 memcpy (valbuf, buf, low_size);
2610 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2611 memcpy (valbuf + low_size, buf, len - low_size);
2614 internal_error (__FILE__, __LINE__,
2615 _("Cannot extract return value of %d bytes long."),
2620 /* Write, for architecture GDBARCH, a function return value of TYPE
2621 from VALBUF into REGCACHE. */
2624 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2625 struct regcache *regcache, const gdb_byte *valbuf)
2627 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2628 int len = TYPE_LENGTH (type);
2630 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2633 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2635 if (tdep->st0_regnum < 0)
2637 warning (_("Cannot set floating-point return value."));
2641 /* Returning floating-point values is a bit tricky. Apart from
2642 storing the return value in %st(0), we have to simulate the
2643 state of the FPU at function return point. */
2645 /* Convert the value found in VALBUF to the extended
2646 floating-point format used by the FPU. This is probably
2647 not exactly how it would happen on the target itself, but
2648 it is the best we can do. */
2649 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
2650 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2652 /* Set the top of the floating-point register stack to 7. The
2653 actual value doesn't really matter, but 7 is what a normal
2654 function return would end up with if the program started out
2655 with a freshly initialized FPU. */
2656 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2658 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2660 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2661 the floating-point register stack to 7, the appropriate value
2662 for the tag word is 0x3fff. */
2663 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2667 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2668 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2670 if (len <= low_size)
2671 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2672 else if (len <= (low_size + high_size))
2674 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2675 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
2676 len - low_size, valbuf + low_size);
2679 internal_error (__FILE__, __LINE__,
2680 _("Cannot store return value of %d bytes long."), len);
2685 /* This is the variable that is set with "set struct-convention", and
2686 its legitimate values. */
2687 static const char default_struct_convention[] = "default";
2688 static const char pcc_struct_convention[] = "pcc";
2689 static const char reg_struct_convention[] = "reg";
2690 static const char *const valid_conventions[] =
2692 default_struct_convention,
2693 pcc_struct_convention,
2694 reg_struct_convention,
2697 static const char *struct_convention = default_struct_convention;
2699 /* Return non-zero if TYPE, which is assumed to be a structure,
2700 a union type, or an array type, should be returned in registers
2701 for architecture GDBARCH. */
2704 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2706 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2707 enum type_code code = TYPE_CODE (type);
2708 int len = TYPE_LENGTH (type);
2710 gdb_assert (code == TYPE_CODE_STRUCT
2711 || code == TYPE_CODE_UNION
2712 || code == TYPE_CODE_ARRAY);
2714 if (struct_convention == pcc_struct_convention
2715 || (struct_convention == default_struct_convention
2716 && tdep->struct_return == pcc_struct_return))
2719 /* Structures consisting of a single `float', `double' or 'long
2720 double' member are returned in %st(0). */
2721 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2723 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2724 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2725 return (len == 4 || len == 8 || len == 12);
2728 return (len == 1 || len == 2 || len == 4 || len == 8);
2731 /* Determine, for architecture GDBARCH, how a return value of TYPE
2732 should be returned. If it is supposed to be returned in registers,
2733 and READBUF is non-zero, read the appropriate value from REGCACHE,
2734 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2735 from WRITEBUF into REGCACHE. */
2737 static enum return_value_convention
2738 i386_return_value (struct gdbarch *gdbarch, struct value *function,
2739 struct type *type, struct regcache *regcache,
2740 gdb_byte *readbuf, const gdb_byte *writebuf)
2742 enum type_code code = TYPE_CODE (type);
2744 if (((code == TYPE_CODE_STRUCT
2745 || code == TYPE_CODE_UNION
2746 || code == TYPE_CODE_ARRAY)
2747 && !i386_reg_struct_return_p (gdbarch, type))
2748 /* Complex double and long double uses the struct return covention. */
2749 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16)
2750 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24)
2751 /* 128-bit decimal float uses the struct return convention. */
2752 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2754 /* The System V ABI says that:
2756 "A function that returns a structure or union also sets %eax
2757 to the value of the original address of the caller's area
2758 before it returns. Thus when the caller receives control
2759 again, the address of the returned object resides in register
2760 %eax and can be used to access the object."
2762 So the ABI guarantees that we can always find the return
2763 value just after the function has returned. */
2765 /* Note that the ABI doesn't mention functions returning arrays,
2766 which is something possible in certain languages such as Ada.
2767 In this case, the value is returned as if it was wrapped in
2768 a record, so the convention applied to records also applies
2775 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2776 read_memory (addr, readbuf, TYPE_LENGTH (type));
2779 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2782 /* This special case is for structures consisting of a single
2783 `float', `double' or 'long double' member. These structures are
2784 returned in %st(0). For these structures, we call ourselves
2785 recursively, changing TYPE into the type of the first member of
2786 the structure. Since that should work for all structures that
2787 have only one member, we don't bother to check the member's type
2789 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2791 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2792 return i386_return_value (gdbarch, function, type, regcache,
2797 i386_extract_return_value (gdbarch, type, regcache, readbuf);
2799 i386_store_return_value (gdbarch, type, regcache, writebuf);
2801 return RETURN_VALUE_REGISTER_CONVENTION;
2806 i387_ext_type (struct gdbarch *gdbarch)
2808 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2810 if (!tdep->i387_ext_type)
2812 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
2813 gdb_assert (tdep->i387_ext_type != NULL);
2816 return tdep->i387_ext_type;
2819 /* Construct type for pseudo BND registers. We can't use
2820 tdesc_find_type since a complement of one value has to be used
2821 to describe the upper bound. */
2823 static struct type *
2824 i386_bnd_type (struct gdbarch *gdbarch)
2826 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2829 if (!tdep->i386_bnd_type)
2831 struct type *t, *bound_t;
2832 const struct builtin_type *bt = builtin_type (gdbarch);
2834 /* The type we're building is described bellow: */
2839 void *ubound; /* One complement of raw ubound field. */
2843 t = arch_composite_type (gdbarch,
2844 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT);
2846 append_composite_type_field (t, "lbound", bt->builtin_data_ptr);
2847 append_composite_type_field (t, "ubound", bt->builtin_data_ptr);
2849 TYPE_NAME (t) = "builtin_type_bound128";
2850 tdep->i386_bnd_type = t;
2853 return tdep->i386_bnd_type;
2856 /* Construct vector type for pseudo YMM registers. We can't use
2857 tdesc_find_type since YMM isn't described in target description. */
2859 static struct type *
2860 i386_ymm_type (struct gdbarch *gdbarch)
2862 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2864 if (!tdep->i386_ymm_type)
2866 const struct builtin_type *bt = builtin_type (gdbarch);
2868 /* The type we're building is this: */
2870 union __gdb_builtin_type_vec256i
2872 int128_t uint128[2];
2873 int64_t v2_int64[4];
2874 int32_t v4_int32[8];
2875 int16_t v8_int16[16];
2876 int8_t v16_int8[32];
2877 double v2_double[4];
2884 t = arch_composite_type (gdbarch,
2885 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
2886 append_composite_type_field (t, "v8_float",
2887 init_vector_type (bt->builtin_float, 8));
2888 append_composite_type_field (t, "v4_double",
2889 init_vector_type (bt->builtin_double, 4));
2890 append_composite_type_field (t, "v32_int8",
2891 init_vector_type (bt->builtin_int8, 32));
2892 append_composite_type_field (t, "v16_int16",
2893 init_vector_type (bt->builtin_int16, 16));
2894 append_composite_type_field (t, "v8_int32",
2895 init_vector_type (bt->builtin_int32, 8));
2896 append_composite_type_field (t, "v4_int64",
2897 init_vector_type (bt->builtin_int64, 4));
2898 append_composite_type_field (t, "v2_int128",
2899 init_vector_type (bt->builtin_int128, 2));
2901 TYPE_VECTOR (t) = 1;
2902 TYPE_NAME (t) = "builtin_type_vec256i";
2903 tdep->i386_ymm_type = t;
2906 return tdep->i386_ymm_type;
2909 /* Construct vector type for MMX registers. */
2910 static struct type *
2911 i386_mmx_type (struct gdbarch *gdbarch)
2913 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2915 if (!tdep->i386_mmx_type)
2917 const struct builtin_type *bt = builtin_type (gdbarch);
2919 /* The type we're building is this: */
2921 union __gdb_builtin_type_vec64i
2924 int32_t v2_int32[2];
2925 int16_t v4_int16[4];
2932 t = arch_composite_type (gdbarch,
2933 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
2935 append_composite_type_field (t, "uint64", bt->builtin_int64);
2936 append_composite_type_field (t, "v2_int32",
2937 init_vector_type (bt->builtin_int32, 2));
2938 append_composite_type_field (t, "v4_int16",
2939 init_vector_type (bt->builtin_int16, 4));
2940 append_composite_type_field (t, "v8_int8",
2941 init_vector_type (bt->builtin_int8, 8));
2943 TYPE_VECTOR (t) = 1;
2944 TYPE_NAME (t) = "builtin_type_vec64i";
2945 tdep->i386_mmx_type = t;
2948 return tdep->i386_mmx_type;
2951 /* Return the GDB type object for the "standard" data type of data in
2955 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2957 if (i386_bnd_regnum_p (gdbarch, regnum))
2958 return i386_bnd_type (gdbarch);
2959 if (i386_mmx_regnum_p (gdbarch, regnum))
2960 return i386_mmx_type (gdbarch);
2961 else if (i386_ymm_regnum_p (gdbarch, regnum))
2962 return i386_ymm_type (gdbarch);
2965 const struct builtin_type *bt = builtin_type (gdbarch);
2966 if (i386_byte_regnum_p (gdbarch, regnum))
2967 return bt->builtin_int8;
2968 else if (i386_word_regnum_p (gdbarch, regnum))
2969 return bt->builtin_int16;
2970 else if (i386_dword_regnum_p (gdbarch, regnum))
2971 return bt->builtin_int32;
2974 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2977 /* Map a cooked register onto a raw register or memory. For the i386,
2978 the MMX registers need to be mapped onto floating point registers. */
2981 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
2983 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
2988 mmxreg = regnum - tdep->mm0_regnum;
2989 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2990 tos = (fstat >> 11) & 0x7;
2991 fpreg = (mmxreg + tos) % 8;
2993 return (I387_ST0_REGNUM (tdep) + fpreg);
2996 /* A helper function for us by i386_pseudo_register_read_value and
2997 amd64_pseudo_register_read_value. It does all the work but reads
2998 the data into an already-allocated value. */
3001 i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
3002 struct regcache *regcache,
3004 struct value *result_value)
3006 gdb_byte raw_buf[MAX_REGISTER_SIZE];
3007 enum register_status status;
3008 gdb_byte *buf = value_contents_raw (result_value);
3010 if (i386_mmx_regnum_p (gdbarch, regnum))
3012 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3014 /* Extract (always little endian). */
3015 status = regcache_raw_read (regcache, fpnum, raw_buf);
3016 if (status != REG_VALID)
3017 mark_value_bytes_unavailable (result_value, 0,
3018 TYPE_LENGTH (value_type (result_value)));
3020 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
3024 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3025 if (i386_bnd_regnum_p (gdbarch, regnum))
3027 regnum -= tdep->bnd0_regnum;
3029 /* Extract (always little endian). Read lower 128bits. */
3030 status = regcache_raw_read (regcache,
3031 I387_BND0R_REGNUM (tdep) + regnum,
3033 if (status != REG_VALID)
3034 mark_value_bytes_unavailable (result_value, 0, 16);
3037 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3038 LONGEST upper, lower;
3039 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3041 lower = extract_unsigned_integer (raw_buf, 8, byte_order);
3042 upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order);
3045 memcpy (buf, &lower, size);
3046 memcpy (buf + size, &upper, size);
3049 else if (i386_ymm_regnum_p (gdbarch, regnum))
3051 regnum -= tdep->ymm0_regnum;
3053 /* Extract (always little endian). Read lower 128bits. */
3054 status = regcache_raw_read (regcache,
3055 I387_XMM0_REGNUM (tdep) + regnum,
3057 if (status != REG_VALID)
3058 mark_value_bytes_unavailable (result_value, 0, 16);
3060 memcpy (buf, raw_buf, 16);
3061 /* Read upper 128bits. */
3062 status = regcache_raw_read (regcache,
3063 tdep->ymm0h_regnum + regnum,
3065 if (status != REG_VALID)
3066 mark_value_bytes_unavailable (result_value, 16, 32);
3068 memcpy (buf + 16, raw_buf, 16);
3070 else if (i386_word_regnum_p (gdbarch, regnum))
3072 int gpnum = regnum - tdep->ax_regnum;
3074 /* Extract (always little endian). */
3075 status = regcache_raw_read (regcache, gpnum, raw_buf);
3076 if (status != REG_VALID)
3077 mark_value_bytes_unavailable (result_value, 0,
3078 TYPE_LENGTH (value_type (result_value)));
3080 memcpy (buf, raw_buf, 2);
3082 else if (i386_byte_regnum_p (gdbarch, regnum))
3084 /* Check byte pseudo registers last since this function will
3085 be called from amd64_pseudo_register_read, which handles
3086 byte pseudo registers differently. */
3087 int gpnum = regnum - tdep->al_regnum;
3089 /* Extract (always little endian). We read both lower and
3091 status = regcache_raw_read (regcache, gpnum % 4, raw_buf);
3092 if (status != REG_VALID)
3093 mark_value_bytes_unavailable (result_value, 0,
3094 TYPE_LENGTH (value_type (result_value)));
3095 else if (gpnum >= 4)
3096 memcpy (buf, raw_buf + 1, 1);
3098 memcpy (buf, raw_buf, 1);
3101 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3105 static struct value *
3106 i386_pseudo_register_read_value (struct gdbarch *gdbarch,
3107 struct regcache *regcache,
3110 struct value *result;
3112 result = allocate_value (register_type (gdbarch, regnum));
3113 VALUE_LVAL (result) = lval_register;
3114 VALUE_REGNUM (result) = regnum;
3116 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result);
3122 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3123 int regnum, const gdb_byte *buf)
3125 gdb_byte raw_buf[MAX_REGISTER_SIZE];
3127 if (i386_mmx_regnum_p (gdbarch, regnum))
3129 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3132 regcache_raw_read (regcache, fpnum, raw_buf);
3133 /* ... Modify ... (always little endian). */
3134 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
3136 regcache_raw_write (regcache, fpnum, raw_buf);
3140 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3142 if (i386_bnd_regnum_p (gdbarch, regnum))
3144 ULONGEST upper, lower;
3145 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3146 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3148 /* New values from input value. */
3149 regnum -= tdep->bnd0_regnum;
3150 lower = extract_unsigned_integer (buf, size, byte_order);
3151 upper = extract_unsigned_integer (buf + size, size, byte_order);
3153 /* Fetching register buffer. */
3154 regcache_raw_read (regcache,
3155 I387_BND0R_REGNUM (tdep) + regnum,
3160 /* Set register bits. */
3161 memcpy (raw_buf, &lower, 8);
3162 memcpy (raw_buf + 8, &upper, 8);
3165 regcache_raw_write (regcache,
3166 I387_BND0R_REGNUM (tdep) + regnum,
3169 else if (i386_ymm_regnum_p (gdbarch, regnum))
3171 regnum -= tdep->ymm0_regnum;
3173 /* ... Write lower 128bits. */
3174 regcache_raw_write (regcache,
3175 I387_XMM0_REGNUM (tdep) + regnum,
3177 /* ... Write upper 128bits. */
3178 regcache_raw_write (regcache,
3179 tdep->ymm0h_regnum + regnum,
3182 else if (i386_word_regnum_p (gdbarch, regnum))
3184 int gpnum = regnum - tdep->ax_regnum;
3187 regcache_raw_read (regcache, gpnum, raw_buf);
3188 /* ... Modify ... (always little endian). */
3189 memcpy (raw_buf, buf, 2);
3191 regcache_raw_write (regcache, gpnum, raw_buf);
3193 else if (i386_byte_regnum_p (gdbarch, regnum))
3195 /* Check byte pseudo registers last since this function will
3196 be called from amd64_pseudo_register_read, which handles
3197 byte pseudo registers differently. */
3198 int gpnum = regnum - tdep->al_regnum;
3200 /* Read ... We read both lower and upper registers. */
3201 regcache_raw_read (regcache, gpnum % 4, raw_buf);
3202 /* ... Modify ... (always little endian). */
3204 memcpy (raw_buf + 1, buf, 1);
3206 memcpy (raw_buf, buf, 1);
3208 regcache_raw_write (regcache, gpnum % 4, raw_buf);
3211 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3216 /* Return the register number of the register allocated by GCC after
3217 REGNUM, or -1 if there is no such register. */
3220 i386_next_regnum (int regnum)
3222 /* GCC allocates the registers in the order:
3224 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3226 Since storing a variable in %esp doesn't make any sense we return
3227 -1 for %ebp and for %esp itself. */
3228 static int next_regnum[] =
3230 I386_EDX_REGNUM, /* Slot for %eax. */
3231 I386_EBX_REGNUM, /* Slot for %ecx. */
3232 I386_ECX_REGNUM, /* Slot for %edx. */
3233 I386_ESI_REGNUM, /* Slot for %ebx. */
3234 -1, -1, /* Slots for %esp and %ebp. */
3235 I386_EDI_REGNUM, /* Slot for %esi. */
3236 I386_EBP_REGNUM /* Slot for %edi. */
3239 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
3240 return next_regnum[regnum];
3245 /* Return nonzero if a value of type TYPE stored in register REGNUM
3246 needs any special handling. */
3249 i386_convert_register_p (struct gdbarch *gdbarch,
3250 int regnum, struct type *type)
3252 int len = TYPE_LENGTH (type);
3254 /* Values may be spread across multiple registers. Most debugging
3255 formats aren't expressive enough to specify the locations, so
3256 some heuristics is involved. Right now we only handle types that
3257 have a length that is a multiple of the word size, since GCC
3258 doesn't seem to put any other types into registers. */
3259 if (len > 4 && len % 4 == 0)
3261 int last_regnum = regnum;
3265 last_regnum = i386_next_regnum (last_regnum);
3269 if (last_regnum != -1)
3273 return i387_convert_register_p (gdbarch, regnum, type);
3276 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3277 return its contents in TO. */
3280 i386_register_to_value (struct frame_info *frame, int regnum,
3281 struct type *type, gdb_byte *to,
3282 int *optimizedp, int *unavailablep)
3284 struct gdbarch *gdbarch = get_frame_arch (frame);
3285 int len = TYPE_LENGTH (type);
3287 if (i386_fp_regnum_p (gdbarch, regnum))
3288 return i387_register_to_value (frame, regnum, type, to,
3289 optimizedp, unavailablep);
3291 /* Read a value spread across multiple registers. */
3293 gdb_assert (len > 4 && len % 4 == 0);
3297 gdb_assert (regnum != -1);
3298 gdb_assert (register_size (gdbarch, regnum) == 4);
3300 if (!get_frame_register_bytes (frame, regnum, 0,
3301 register_size (gdbarch, regnum),
3302 to, optimizedp, unavailablep))
3305 regnum = i386_next_regnum (regnum);
3310 *optimizedp = *unavailablep = 0;
3314 /* Write the contents FROM of a value of type TYPE into register
3315 REGNUM in frame FRAME. */
3318 i386_value_to_register (struct frame_info *frame, int regnum,
3319 struct type *type, const gdb_byte *from)
3321 int len = TYPE_LENGTH (type);
3323 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
3325 i387_value_to_register (frame, regnum, type, from);
3329 /* Write a value spread across multiple registers. */
3331 gdb_assert (len > 4 && len % 4 == 0);
3335 gdb_assert (regnum != -1);
3336 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
3338 put_frame_register (frame, regnum, from);
3339 regnum = i386_next_regnum (regnum);
3345 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3346 in the general-purpose register set REGSET to register cache
3347 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3350 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
3351 int regnum, const void *gregs, size_t len)
3353 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3354 const gdb_byte *regs = gregs;
3357 gdb_assert (len == tdep->sizeof_gregset);
3359 for (i = 0; i < tdep->gregset_num_regs; i++)
3361 if ((regnum == i || regnum == -1)
3362 && tdep->gregset_reg_offset[i] != -1)
3363 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
3367 /* Collect register REGNUM from the register cache REGCACHE and store
3368 it in the buffer specified by GREGS and LEN as described by the
3369 general-purpose register set REGSET. If REGNUM is -1, do this for
3370 all registers in REGSET. */
3373 i386_collect_gregset (const struct regset *regset,
3374 const struct regcache *regcache,
3375 int regnum, void *gregs, size_t len)
3377 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3378 gdb_byte *regs = gregs;
3381 gdb_assert (len == tdep->sizeof_gregset);
3383 for (i = 0; i < tdep->gregset_num_regs; i++)
3385 if ((regnum == i || regnum == -1)
3386 && tdep->gregset_reg_offset[i] != -1)
3387 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
3391 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3392 in the floating-point register set REGSET to register cache
3393 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3396 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
3397 int regnum, const void *fpregs, size_t len)
3399 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3401 if (len == I387_SIZEOF_FXSAVE)
3403 i387_supply_fxsave (regcache, regnum, fpregs);
3407 gdb_assert (len == tdep->sizeof_fpregset);
3408 i387_supply_fsave (regcache, regnum, fpregs);
3411 /* Collect register REGNUM from the register cache REGCACHE and store
3412 it in the buffer specified by FPREGS and LEN as described by the
3413 floating-point register set REGSET. If REGNUM is -1, do this for
3414 all registers in REGSET. */
3417 i386_collect_fpregset (const struct regset *regset,
3418 const struct regcache *regcache,
3419 int regnum, void *fpregs, size_t len)
3421 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3423 if (len == I387_SIZEOF_FXSAVE)
3425 i387_collect_fxsave (regcache, regnum, fpregs);
3429 gdb_assert (len == tdep->sizeof_fpregset);
3430 i387_collect_fsave (regcache, regnum, fpregs);
3433 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
3436 i386_supply_xstateregset (const struct regset *regset,
3437 struct regcache *regcache, int regnum,
3438 const void *xstateregs, size_t len)
3440 i387_supply_xsave (regcache, regnum, xstateregs);
3443 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
3446 i386_collect_xstateregset (const struct regset *regset,
3447 const struct regcache *regcache,
3448 int regnum, void *xstateregs, size_t len)
3450 i387_collect_xsave (regcache, regnum, xstateregs, 1);
3453 /* Return the appropriate register set for the core section identified
3454 by SECT_NAME and SECT_SIZE. */
3456 const struct regset *
3457 i386_regset_from_core_section (struct gdbarch *gdbarch,
3458 const char *sect_name, size_t sect_size)
3460 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3462 if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset)
3464 if (tdep->gregset == NULL)
3465 tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset,
3466 i386_collect_gregset);
3467 return tdep->gregset;
3470 if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
3471 || (strcmp (sect_name, ".reg-xfp") == 0
3472 && sect_size == I387_SIZEOF_FXSAVE))
3474 if (tdep->fpregset == NULL)
3475 tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset,
3476 i386_collect_fpregset);
3477 return tdep->fpregset;
3480 if (strcmp (sect_name, ".reg-xstate") == 0)
3482 if (tdep->xstateregset == NULL)
3483 tdep->xstateregset = regset_alloc (gdbarch,
3484 i386_supply_xstateregset,
3485 i386_collect_xstateregset);
3487 return tdep->xstateregset;
3494 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3497 i386_pe_skip_trampoline_code (struct frame_info *frame,
3498 CORE_ADDR pc, char *name)
3500 struct gdbarch *gdbarch = get_frame_arch (frame);
3501 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3504 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
3506 unsigned long indirect =
3507 read_memory_unsigned_integer (pc + 2, 4, byte_order);
3508 struct minimal_symbol *indsym =
3509 indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0;
3510 const char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0;
3514 if (strncmp (symname, "__imp_", 6) == 0
3515 || strncmp (symname, "_imp_", 5) == 0)
3517 read_memory_unsigned_integer (indirect, 4, byte_order);
3520 return 0; /* Not a trampoline. */
3524 /* Return whether the THIS_FRAME corresponds to a sigtramp
3528 i386_sigtramp_p (struct frame_info *this_frame)
3530 CORE_ADDR pc = get_frame_pc (this_frame);
3533 find_pc_partial_function (pc, &name, NULL, NULL);
3534 return (name && strcmp ("_sigtramp", name) == 0);
3538 /* We have two flavours of disassembly. The machinery on this page
3539 deals with switching between those. */
3542 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
3544 gdb_assert (disassembly_flavor == att_flavor
3545 || disassembly_flavor == intel_flavor);
3547 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3548 constified, cast to prevent a compiler warning. */
3549 info->disassembler_options = (char *) disassembly_flavor;
3551 return print_insn_i386 (pc, info);
3555 /* There are a few i386 architecture variants that differ only
3556 slightly from the generic i386 target. For now, we don't give them
3557 their own source file, but include them here. As a consequence,
3558 they'll always be included. */
3560 /* System V Release 4 (SVR4). */
3562 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3566 i386_svr4_sigtramp_p (struct frame_info *this_frame)
3568 CORE_ADDR pc = get_frame_pc (this_frame);
3571 /* The origin of these symbols is currently unknown. */
3572 find_pc_partial_function (pc, &name, NULL, NULL);
3573 return (name && (strcmp ("_sigreturn", name) == 0
3574 || strcmp ("sigvechandler", name) == 0));
3577 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3578 address of the associated sigcontext (ucontext) structure. */
3581 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
3583 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3584 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3588 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
3589 sp = extract_unsigned_integer (buf, 4, byte_order);
3591 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
3596 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
3600 i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s)
3602 return (*s == '$' /* Literal number. */
3603 || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */
3604 || (*s == '(' && s[1] == '%') /* Register indirection. */
3605 || (*s == '%' && isalpha (s[1]))); /* Register access. */
3608 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
3612 i386_stap_parse_special_token (struct gdbarch *gdbarch,
3613 struct stap_parse_info *p)
3615 /* In order to parse special tokens, we use a state-machine that go
3616 through every known token and try to get a match. */
3620 THREE_ARG_DISPLACEMENT,
3624 current_state = TRIPLET;
3626 /* The special tokens to be parsed here are:
3628 - `register base + (register index * size) + offset', as represented
3629 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
3631 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
3632 `*(-8 + 3 - 1 + (void *) $eax)'. */
3634 while (current_state != DONE)
3636 const char *s = p->arg;
3638 switch (current_state)
3642 if (isdigit (*s) || *s == '-' || *s == '+')
3646 long displacements[3];
3662 displacements[0] = strtol (s, &endp, 10);
3665 if (*s != '+' && *s != '-')
3667 /* We are not dealing with a triplet. */
3680 displacements[1] = strtol (s, &endp, 10);
3683 if (*s != '+' && *s != '-')
3685 /* We are not dealing with a triplet. */
3698 displacements[2] = strtol (s, &endp, 10);
3701 if (*s != '(' || s[1] != '%')
3707 while (isalnum (*s))
3714 regname = alloca (len + 1);
3716 strncpy (regname, start, len);
3717 regname[len] = '\0';
3719 if (user_reg_map_name_to_regnum (gdbarch,
3720 regname, len) == -1)
3721 error (_("Invalid register name `%s' "
3722 "on expression `%s'."),
3723 regname, p->saved_arg);
3725 for (i = 0; i < 3; i++)
3727 write_exp_elt_opcode (OP_LONG);
3729 (builtin_type (gdbarch)->builtin_long);
3730 write_exp_elt_longcst (displacements[i]);
3731 write_exp_elt_opcode (OP_LONG);
3733 write_exp_elt_opcode (UNOP_NEG);
3736 write_exp_elt_opcode (OP_REGISTER);
3739 write_exp_string (str);
3740 write_exp_elt_opcode (OP_REGISTER);
3742 write_exp_elt_opcode (UNOP_CAST);
3743 write_exp_elt_type (builtin_type (gdbarch)->builtin_data_ptr);
3744 write_exp_elt_opcode (UNOP_CAST);
3746 write_exp_elt_opcode (BINOP_ADD);
3747 write_exp_elt_opcode (BINOP_ADD);
3748 write_exp_elt_opcode (BINOP_ADD);
3750 write_exp_elt_opcode (UNOP_CAST);
3751 write_exp_elt_type (lookup_pointer_type (p->arg_type));
3752 write_exp_elt_opcode (UNOP_CAST);
3754 write_exp_elt_opcode (UNOP_IND);
3762 case THREE_ARG_DISPLACEMENT:
3764 if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+')
3766 int offset_minus = 0;
3775 struct stoken base_token, index_token;
3785 if (offset_minus && !isdigit (*s))
3792 offset = strtol (s, &endp, 10);
3796 if (*s != '(' || s[1] != '%')
3802 while (isalnum (*s))
3805 if (*s != ',' || s[1] != '%')
3808 len_base = s - start;
3809 base = alloca (len_base + 1);
3810 strncpy (base, start, len_base);
3811 base[len_base] = '\0';
3813 if (user_reg_map_name_to_regnum (gdbarch,
3814 base, len_base) == -1)
3815 error (_("Invalid register name `%s' "
3816 "on expression `%s'."),
3817 base, p->saved_arg);
3822 while (isalnum (*s))
3825 len_index = s - start;
3826 index = alloca (len_index + 1);
3827 strncpy (index, start, len_index);
3828 index[len_index] = '\0';
3830 if (user_reg_map_name_to_regnum (gdbarch,
3831 index, len_index) == -1)
3832 error (_("Invalid register name `%s' "
3833 "on expression `%s'."),
3834 index, p->saved_arg);
3836 if (*s != ',' && *s != ')')
3852 size = strtol (s, &endp, 10);
3863 write_exp_elt_opcode (OP_LONG);
3865 (builtin_type (gdbarch)->builtin_long);
3866 write_exp_elt_longcst (offset);
3867 write_exp_elt_opcode (OP_LONG);
3869 write_exp_elt_opcode (UNOP_NEG);
3872 write_exp_elt_opcode (OP_REGISTER);
3873 base_token.ptr = base;
3874 base_token.length = len_base;
3875 write_exp_string (base_token);
3876 write_exp_elt_opcode (OP_REGISTER);
3879 write_exp_elt_opcode (BINOP_ADD);
3881 write_exp_elt_opcode (OP_REGISTER);
3882 index_token.ptr = index;
3883 index_token.length = len_index;
3884 write_exp_string (index_token);
3885 write_exp_elt_opcode (OP_REGISTER);
3889 write_exp_elt_opcode (OP_LONG);
3891 (builtin_type (gdbarch)->builtin_long);
3892 write_exp_elt_longcst (size);
3893 write_exp_elt_opcode (OP_LONG);
3895 write_exp_elt_opcode (UNOP_NEG);
3896 write_exp_elt_opcode (BINOP_MUL);
3899 write_exp_elt_opcode (BINOP_ADD);
3901 write_exp_elt_opcode (UNOP_CAST);
3902 write_exp_elt_type (lookup_pointer_type (p->arg_type));
3903 write_exp_elt_opcode (UNOP_CAST);
3905 write_exp_elt_opcode (UNOP_IND);
3915 /* Advancing to the next state. */
3927 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3929 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3930 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3932 /* Registering SystemTap handlers. */
3933 set_gdbarch_stap_integer_prefix (gdbarch, "$");
3934 set_gdbarch_stap_register_prefix (gdbarch, "%");
3935 set_gdbarch_stap_register_indirection_prefix (gdbarch, "(");
3936 set_gdbarch_stap_register_indirection_suffix (gdbarch, ")");
3937 set_gdbarch_stap_is_single_operand (gdbarch,
3938 i386_stap_is_single_operand);
3939 set_gdbarch_stap_parse_special_token (gdbarch,
3940 i386_stap_parse_special_token);
3943 /* System V Release 4 (SVR4). */
3946 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3948 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3950 /* System V Release 4 uses ELF. */
3951 i386_elf_init_abi (info, gdbarch);
3953 /* System V Release 4 has shared libraries. */
3954 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
3956 tdep->sigtramp_p = i386_svr4_sigtramp_p;
3957 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
3958 tdep->sc_pc_offset = 36 + 14 * 4;
3959 tdep->sc_sp_offset = 36 + 17 * 4;
3961 tdep->jb_pc_offset = 20;
3967 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3969 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3971 /* DJGPP doesn't have any special frames for signal handlers. */
3972 tdep->sigtramp_p = NULL;
3974 tdep->jb_pc_offset = 36;
3976 /* DJGPP does not support the SSE registers. */
3977 if (! tdesc_has_registers (info.target_desc))
3978 tdep->tdesc = tdesc_i386_mmx;
3980 /* Native compiler is GCC, which uses the SVR4 register numbering
3981 even in COFF and STABS. See the comment in i386_gdbarch_init,
3982 before the calls to set_gdbarch_stab_reg_to_regnum and
3983 set_gdbarch_sdb_reg_to_regnum. */
3984 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3985 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3987 set_gdbarch_has_dos_based_file_system (gdbarch, 1);
3991 /* i386 register groups. In addition to the normal groups, add "mmx"
3994 static struct reggroup *i386_sse_reggroup;
3995 static struct reggroup *i386_mmx_reggroup;
3998 i386_init_reggroups (void)
4000 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
4001 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
4005 i386_add_reggroups (struct gdbarch *gdbarch)
4007 reggroup_add (gdbarch, i386_sse_reggroup);
4008 reggroup_add (gdbarch, i386_mmx_reggroup);
4009 reggroup_add (gdbarch, general_reggroup);
4010 reggroup_add (gdbarch, float_reggroup);
4011 reggroup_add (gdbarch, all_reggroup);
4012 reggroup_add (gdbarch, save_reggroup);
4013 reggroup_add (gdbarch, restore_reggroup);
4014 reggroup_add (gdbarch, vector_reggroup);
4015 reggroup_add (gdbarch, system_reggroup);
4019 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
4020 struct reggroup *group)
4022 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4023 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
4024 ymm_regnum_p, ymmh_regnum_p, bndr_regnum_p, bnd_regnum_p,
4027 /* Don't include pseudo registers, except for MMX, in any register
4029 if (i386_byte_regnum_p (gdbarch, regnum))
4032 if (i386_word_regnum_p (gdbarch, regnum))
4035 if (i386_dword_regnum_p (gdbarch, regnum))
4038 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
4039 if (group == i386_mmx_reggroup)
4040 return mmx_regnum_p;
4042 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
4043 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
4044 if (group == i386_sse_reggroup)
4045 return xmm_regnum_p || mxcsr_regnum_p;
4047 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
4048 if (group == vector_reggroup)
4049 return (mmx_regnum_p
4053 && ((tdep->xcr0 & I386_XSTATE_AVX_MASK)
4054 == I386_XSTATE_SSE_MASK)));
4056 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
4057 || i386_fpc_regnum_p (gdbarch, regnum));
4058 if (group == float_reggroup)
4061 /* For "info reg all", don't include upper YMM registers nor XMM
4062 registers when AVX is supported. */
4063 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
4064 if (group == all_reggroup
4066 && (tdep->xcr0 & I386_XSTATE_AVX))
4070 bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum);
4071 if (group == all_reggroup
4072 && ((bnd_regnum_p && (tdep->xcr0 & I386_XSTATE_MPX_MASK))))
4073 return bnd_regnum_p;
4075 bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum);
4076 if (group == all_reggroup
4077 && ((bndr_regnum_p && (tdep->xcr0 & I386_XSTATE_MPX_MASK))))
4080 mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum);
4081 if (group == all_reggroup
4082 && ((mpx_ctrl_regnum_p && (tdep->xcr0 & I386_XSTATE_MPX_MASK))))
4083 return mpx_ctrl_regnum_p;
4085 if (group == general_reggroup)
4086 return (!fp_regnum_p
4094 && !mpx_ctrl_regnum_p);
4096 return default_register_reggroup_p (gdbarch, regnum, group);
4100 /* Get the ARGIth function argument for the current function. */
4103 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
4106 struct gdbarch *gdbarch = get_frame_arch (frame);
4107 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4108 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
4109 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
4113 i386_skip_permanent_breakpoint (struct regcache *regcache)
4115 CORE_ADDR current_pc = regcache_read_pc (regcache);
4117 /* On i386, breakpoint is exactly 1 byte long, so we just
4118 adjust the PC in the regcache. */
4120 regcache_write_pc (regcache, current_pc);
4124 #define PREFIX_REPZ 0x01
4125 #define PREFIX_REPNZ 0x02
4126 #define PREFIX_LOCK 0x04
4127 #define PREFIX_DATA 0x08
4128 #define PREFIX_ADDR 0x10
4140 /* i386 arith/logic operations */
4153 struct i386_record_s
4155 struct gdbarch *gdbarch;
4156 struct regcache *regcache;
4157 CORE_ADDR orig_addr;
4163 uint8_t mod, reg, rm;
4172 /* Parse the "modrm" part of the memory address irp->addr points at.
4173 Returns -1 if something goes wrong, 0 otherwise. */
4176 i386_record_modrm (struct i386_record_s *irp)
4178 struct gdbarch *gdbarch = irp->gdbarch;
4180 if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1))
4184 irp->mod = (irp->modrm >> 6) & 3;
4185 irp->reg = (irp->modrm >> 3) & 7;
4186 irp->rm = irp->modrm & 7;
4191 /* Extract the memory address that the current instruction writes to,
4192 and return it in *ADDR. Return -1 if something goes wrong. */
4195 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
4197 struct gdbarch *gdbarch = irp->gdbarch;
4198 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4210 uint8_t base = irp->rm;
4215 if (record_read_memory (gdbarch, irp->addr, &byte, 1))
4218 scale = (byte >> 6) & 3;
4219 index = ((byte >> 3) & 7) | irp->rex_x;
4227 if ((base & 7) == 5)
4230 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4233 *addr = extract_signed_integer (buf, 4, byte_order);
4234 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
4235 *addr += irp->addr + irp->rip_offset;
4239 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4242 *addr = (int8_t) buf[0];
4245 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4247 *addr = extract_signed_integer (buf, 4, byte_order);
4255 if (base == 4 && irp->popl_esp_hack)
4256 *addr += irp->popl_esp_hack;
4257 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
4260 if (irp->aflag == 2)
4265 *addr = (uint32_t) (offset64 + *addr);
4267 if (havesib && (index != 4 || scale != 0))
4269 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
4271 if (irp->aflag == 2)
4272 *addr += offset64 << scale;
4274 *addr = (uint32_t) (*addr + (offset64 << scale));
4285 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4288 *addr = extract_signed_integer (buf, 2, byte_order);
4294 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4297 *addr = (int8_t) buf[0];
4300 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4303 *addr = extract_signed_integer (buf, 2, byte_order);
4310 regcache_raw_read_unsigned (irp->regcache,
4311 irp->regmap[X86_RECORD_REBX_REGNUM],
4313 *addr = (uint32_t) (*addr + offset64);
4314 regcache_raw_read_unsigned (irp->regcache,
4315 irp->regmap[X86_RECORD_RESI_REGNUM],
4317 *addr = (uint32_t) (*addr + offset64);
4320 regcache_raw_read_unsigned (irp->regcache,
4321 irp->regmap[X86_RECORD_REBX_REGNUM],
4323 *addr = (uint32_t) (*addr + offset64);
4324 regcache_raw_read_unsigned (irp->regcache,
4325 irp->regmap[X86_RECORD_REDI_REGNUM],
4327 *addr = (uint32_t) (*addr + offset64);
4330 regcache_raw_read_unsigned (irp->regcache,
4331 irp->regmap[X86_RECORD_REBP_REGNUM],
4333 *addr = (uint32_t) (*addr + offset64);
4334 regcache_raw_read_unsigned (irp->regcache,
4335 irp->regmap[X86_RECORD_RESI_REGNUM],
4337 *addr = (uint32_t) (*addr + offset64);
4340 regcache_raw_read_unsigned (irp->regcache,
4341 irp->regmap[X86_RECORD_REBP_REGNUM],
4343 *addr = (uint32_t) (*addr + offset64);
4344 regcache_raw_read_unsigned (irp->regcache,
4345 irp->regmap[X86_RECORD_REDI_REGNUM],
4347 *addr = (uint32_t) (*addr + offset64);
4350 regcache_raw_read_unsigned (irp->regcache,
4351 irp->regmap[X86_RECORD_RESI_REGNUM],
4353 *addr = (uint32_t) (*addr + offset64);
4356 regcache_raw_read_unsigned (irp->regcache,
4357 irp->regmap[X86_RECORD_REDI_REGNUM],
4359 *addr = (uint32_t) (*addr + offset64);
4362 regcache_raw_read_unsigned (irp->regcache,
4363 irp->regmap[X86_RECORD_REBP_REGNUM],
4365 *addr = (uint32_t) (*addr + offset64);
4368 regcache_raw_read_unsigned (irp->regcache,
4369 irp->regmap[X86_RECORD_REBX_REGNUM],
4371 *addr = (uint32_t) (*addr + offset64);
4381 /* Record the address and contents of the memory that will be changed
4382 by the current instruction. Return -1 if something goes wrong, 0
4386 i386_record_lea_modrm (struct i386_record_s *irp)
4388 struct gdbarch *gdbarch = irp->gdbarch;
4391 if (irp->override >= 0)
4393 if (record_full_memory_query)
4397 target_terminal_ours ();
4399 Process record ignores the memory change of instruction at address %s\n\
4400 because it can't get the value of the segment register.\n\
4401 Do you want to stop the program?"),
4402 paddress (gdbarch, irp->orig_addr));
4403 target_terminal_inferior ();
4411 if (i386_record_lea_modrm_addr (irp, &addr))
4414 if (record_full_arch_list_add_mem (addr, 1 << irp->ot))
4420 /* Record the effects of a push operation. Return -1 if something
4421 goes wrong, 0 otherwise. */
4424 i386_record_push (struct i386_record_s *irp, int size)
4428 if (record_full_arch_list_add_reg (irp->regcache,
4429 irp->regmap[X86_RECORD_RESP_REGNUM]))
4431 regcache_raw_read_unsigned (irp->regcache,
4432 irp->regmap[X86_RECORD_RESP_REGNUM],
4434 if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size))
4441 /* Defines contents to record. */
4442 #define I386_SAVE_FPU_REGS 0xfffd
4443 #define I386_SAVE_FPU_ENV 0xfffe
4444 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4446 /* Record the values of the floating point registers which will be
4447 changed by the current instruction. Returns -1 if something is
4448 wrong, 0 otherwise. */
4450 static int i386_record_floats (struct gdbarch *gdbarch,
4451 struct i386_record_s *ir,
4454 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4457 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4458 happen. Currently we store st0-st7 registers, but we need not store all
4459 registers all the time, in future we use ftag register and record only
4460 those who are not marked as an empty. */
4462 if (I386_SAVE_FPU_REGS == iregnum)
4464 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
4466 if (record_full_arch_list_add_reg (ir->regcache, i))
4470 else if (I386_SAVE_FPU_ENV == iregnum)
4472 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4474 if (record_full_arch_list_add_reg (ir->regcache, i))
4478 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
4480 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4482 if (record_full_arch_list_add_reg (ir->regcache, i))
4486 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
4487 (iregnum <= I387_FOP_REGNUM (tdep)))
4489 if (record_full_arch_list_add_reg (ir->regcache,iregnum))
4494 /* Parameter error. */
4497 if(I386_SAVE_FPU_ENV != iregnum)
4499 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4501 if (record_full_arch_list_add_reg (ir->regcache, i))
4508 /* Parse the current instruction, and record the values of the
4509 registers and memory that will be changed by the current
4510 instruction. Returns -1 if something goes wrong, 0 otherwise. */
4512 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
4513 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
4516 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
4517 CORE_ADDR input_addr)
4519 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4525 gdb_byte buf[MAX_REGISTER_SIZE];
4526 struct i386_record_s ir;
4527 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4531 memset (&ir, 0, sizeof (struct i386_record_s));
4532 ir.regcache = regcache;
4533 ir.addr = input_addr;
4534 ir.orig_addr = input_addr;
4538 ir.popl_esp_hack = 0;
4539 ir.regmap = tdep->record_regmap;
4540 ir.gdbarch = gdbarch;
4542 if (record_debug > 1)
4543 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
4545 paddress (gdbarch, ir.addr));
4550 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
4553 switch (opcode8) /* Instruction prefixes */
4555 case REPE_PREFIX_OPCODE:
4556 prefixes |= PREFIX_REPZ;
4558 case REPNE_PREFIX_OPCODE:
4559 prefixes |= PREFIX_REPNZ;
4561 case LOCK_PREFIX_OPCODE:
4562 prefixes |= PREFIX_LOCK;
4564 case CS_PREFIX_OPCODE:
4565 ir.override = X86_RECORD_CS_REGNUM;
4567 case SS_PREFIX_OPCODE:
4568 ir.override = X86_RECORD_SS_REGNUM;
4570 case DS_PREFIX_OPCODE:
4571 ir.override = X86_RECORD_DS_REGNUM;
4573 case ES_PREFIX_OPCODE:
4574 ir.override = X86_RECORD_ES_REGNUM;
4576 case FS_PREFIX_OPCODE:
4577 ir.override = X86_RECORD_FS_REGNUM;
4579 case GS_PREFIX_OPCODE:
4580 ir.override = X86_RECORD_GS_REGNUM;
4582 case DATA_PREFIX_OPCODE:
4583 prefixes |= PREFIX_DATA;
4585 case ADDR_PREFIX_OPCODE:
4586 prefixes |= PREFIX_ADDR;
4588 case 0x40: /* i386 inc %eax */
4589 case 0x41: /* i386 inc %ecx */
4590 case 0x42: /* i386 inc %edx */
4591 case 0x43: /* i386 inc %ebx */
4592 case 0x44: /* i386 inc %esp */
4593 case 0x45: /* i386 inc %ebp */
4594 case 0x46: /* i386 inc %esi */
4595 case 0x47: /* i386 inc %edi */
4596 case 0x48: /* i386 dec %eax */
4597 case 0x49: /* i386 dec %ecx */
4598 case 0x4a: /* i386 dec %edx */
4599 case 0x4b: /* i386 dec %ebx */
4600 case 0x4c: /* i386 dec %esp */
4601 case 0x4d: /* i386 dec %ebp */
4602 case 0x4e: /* i386 dec %esi */
4603 case 0x4f: /* i386 dec %edi */
4604 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
4607 rex_w = (opcode8 >> 3) & 1;
4608 rex_r = (opcode8 & 0x4) << 1;
4609 ir.rex_x = (opcode8 & 0x2) << 2;
4610 ir.rex_b = (opcode8 & 0x1) << 3;
4612 else /* 32 bit target */
4621 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
4627 if (prefixes & PREFIX_DATA)
4630 if (prefixes & PREFIX_ADDR)
4632 else if (ir.regmap[X86_RECORD_R8_REGNUM])
4635 /* Now check op code. */
4636 opcode = (uint32_t) opcode8;
4641 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
4644 opcode = (uint32_t) opcode8 | 0x0f00;
4648 case 0x00: /* arith & logic */
4696 if (((opcode >> 3) & 7) != OP_CMPL)
4698 if ((opcode & 1) == 0)
4701 ir.ot = ir.dflag + OT_WORD;
4703 switch ((opcode >> 1) & 3)
4705 case 0: /* OP Ev, Gv */
4706 if (i386_record_modrm (&ir))
4710 if (i386_record_lea_modrm (&ir))
4716 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4718 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
4721 case 1: /* OP Gv, Ev */
4722 if (i386_record_modrm (&ir))
4725 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4727 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
4729 case 2: /* OP A, Iv */
4730 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4734 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4737 case 0x80: /* GRP1 */
4741 if (i386_record_modrm (&ir))
4744 if (ir.reg != OP_CMPL)
4746 if ((opcode & 1) == 0)
4749 ir.ot = ir.dflag + OT_WORD;
4756 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4757 if (i386_record_lea_modrm (&ir))
4761 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
4763 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4766 case 0x40: /* inc */
4775 case 0x48: /* dec */
4784 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7);
4785 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4788 case 0xf6: /* GRP3 */
4790 if ((opcode & 1) == 0)
4793 ir.ot = ir.dflag + OT_WORD;
4794 if (i386_record_modrm (&ir))
4797 if (ir.mod != 3 && ir.reg == 0)
4798 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4803 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4809 if (i386_record_lea_modrm (&ir))
4815 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4817 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
4819 if (ir.reg == 3) /* neg */
4820 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4826 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4827 if (ir.ot != OT_BYTE)
4828 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
4829 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4833 opcode = opcode << 8 | ir.modrm;
4839 case 0xfe: /* GRP4 */
4840 case 0xff: /* GRP5 */
4841 if (i386_record_modrm (&ir))
4843 if (ir.reg >= 2 && opcode == 0xfe)
4846 opcode = opcode << 8 | ir.modrm;
4853 if ((opcode & 1) == 0)
4856 ir.ot = ir.dflag + OT_WORD;
4859 if (i386_record_lea_modrm (&ir))
4865 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4867 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
4869 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4872 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4874 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4876 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4879 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
4880 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4882 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4886 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4889 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4891 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4896 opcode = opcode << 8 | ir.modrm;
4902 case 0x84: /* test */
4906 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4909 case 0x98: /* CWDE/CBW */
4910 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4913 case 0x99: /* CDQ/CWD */
4914 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4915 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
4918 case 0x0faf: /* imul */
4921 ir.ot = ir.dflag + OT_WORD;
4922 if (i386_record_modrm (&ir))
4925 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4926 else if (opcode == 0x6b)
4929 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4931 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
4932 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4935 case 0x0fc0: /* xadd */
4937 if ((opcode & 1) == 0)
4940 ir.ot = ir.dflag + OT_WORD;
4941 if (i386_record_modrm (&ir))
4946 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4948 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
4949 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4951 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
4955 if (i386_record_lea_modrm (&ir))
4957 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4959 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
4961 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4964 case 0x0fb0: /* cmpxchg */
4966 if ((opcode & 1) == 0)
4969 ir.ot = ir.dflag + OT_WORD;
4970 if (i386_record_modrm (&ir))
4975 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4976 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4978 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
4982 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4983 if (i386_record_lea_modrm (&ir))
4986 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4989 case 0x0fc7: /* cmpxchg8b */
4990 if (i386_record_modrm (&ir))
4995 opcode = opcode << 8 | ir.modrm;
4998 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4999 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5000 if (i386_record_lea_modrm (&ir))
5002 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5005 case 0x50: /* push */
5015 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5017 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5021 case 0x06: /* push es */
5022 case 0x0e: /* push cs */
5023 case 0x16: /* push ss */
5024 case 0x1e: /* push ds */
5025 if (ir.regmap[X86_RECORD_R8_REGNUM])
5030 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5034 case 0x0fa0: /* push fs */
5035 case 0x0fa8: /* push gs */
5036 if (ir.regmap[X86_RECORD_R8_REGNUM])
5041 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5045 case 0x60: /* pusha */
5046 if (ir.regmap[X86_RECORD_R8_REGNUM])
5051 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
5055 case 0x58: /* pop */
5063 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5064 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5067 case 0x61: /* popa */
5068 if (ir.regmap[X86_RECORD_R8_REGNUM])
5073 for (regnum = X86_RECORD_REAX_REGNUM;
5074 regnum <= X86_RECORD_REDI_REGNUM;
5076 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5079 case 0x8f: /* pop */
5080 if (ir.regmap[X86_RECORD_R8_REGNUM])
5081 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
5083 ir.ot = ir.dflag + OT_WORD;
5084 if (i386_record_modrm (&ir))
5087 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5090 ir.popl_esp_hack = 1 << ir.ot;
5091 if (i386_record_lea_modrm (&ir))
5094 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5097 case 0xc8: /* enter */
5098 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5099 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5101 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5105 case 0xc9: /* leave */
5106 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5107 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5110 case 0x07: /* pop es */
5111 if (ir.regmap[X86_RECORD_R8_REGNUM])
5116 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5117 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
5118 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5121 case 0x17: /* pop ss */
5122 if (ir.regmap[X86_RECORD_R8_REGNUM])
5127 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5128 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
5129 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5132 case 0x1f: /* pop ds */
5133 if (ir.regmap[X86_RECORD_R8_REGNUM])
5138 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5139 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
5140 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5143 case 0x0fa1: /* pop fs */
5144 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5145 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
5146 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5149 case 0x0fa9: /* pop gs */
5150 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5151 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
5152 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5155 case 0x88: /* mov */
5159 if ((opcode & 1) == 0)
5162 ir.ot = ir.dflag + OT_WORD;
5164 if (i386_record_modrm (&ir))
5169 if (opcode == 0xc6 || opcode == 0xc7)
5170 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5171 if (i386_record_lea_modrm (&ir))
5176 if (opcode == 0xc6 || opcode == 0xc7)
5178 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5180 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5184 case 0x8a: /* mov */
5186 if ((opcode & 1) == 0)
5189 ir.ot = ir.dflag + OT_WORD;
5190 if (i386_record_modrm (&ir))
5193 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5195 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5198 case 0x8c: /* mov seg */
5199 if (i386_record_modrm (&ir))
5204 opcode = opcode << 8 | ir.modrm;
5209 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5213 if (i386_record_lea_modrm (&ir))
5218 case 0x8e: /* mov seg */
5219 if (i386_record_modrm (&ir))
5224 regnum = X86_RECORD_ES_REGNUM;
5227 regnum = X86_RECORD_SS_REGNUM;
5230 regnum = X86_RECORD_DS_REGNUM;
5233 regnum = X86_RECORD_FS_REGNUM;
5236 regnum = X86_RECORD_GS_REGNUM;
5240 opcode = opcode << 8 | ir.modrm;
5244 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5245 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5248 case 0x0fb6: /* movzbS */
5249 case 0x0fb7: /* movzwS */
5250 case 0x0fbe: /* movsbS */
5251 case 0x0fbf: /* movswS */
5252 if (i386_record_modrm (&ir))
5254 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5257 case 0x8d: /* lea */
5258 if (i386_record_modrm (&ir))
5263 opcode = opcode << 8 | ir.modrm;
5268 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5270 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5273 case 0xa0: /* mov EAX */
5276 case 0xd7: /* xlat */
5277 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5280 case 0xa2: /* mov EAX */
5282 if (ir.override >= 0)
5284 if (record_full_memory_query)
5288 target_terminal_ours ();
5290 Process record ignores the memory change of instruction at address %s\n\
5291 because it can't get the value of the segment register.\n\
5292 Do you want to stop the program?"),
5293 paddress (gdbarch, ir.orig_addr));
5294 target_terminal_inferior ();
5301 if ((opcode & 1) == 0)
5304 ir.ot = ir.dflag + OT_WORD;
5307 if (record_read_memory (gdbarch, ir.addr, buf, 8))
5310 addr = extract_unsigned_integer (buf, 8, byte_order);
5314 if (record_read_memory (gdbarch, ir.addr, buf, 4))
5317 addr = extract_unsigned_integer (buf, 4, byte_order);
5321 if (record_read_memory (gdbarch, ir.addr, buf, 2))
5324 addr = extract_unsigned_integer (buf, 2, byte_order);
5326 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
5331 case 0xb0: /* mov R, Ib */
5339 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
5340 ? ((opcode & 0x7) | ir.rex_b)
5341 : ((opcode & 0x7) & 0x3));
5344 case 0xb8: /* mov R, Iv */
5352 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5355 case 0x91: /* xchg R, EAX */
5362 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5363 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7);
5366 case 0x86: /* xchg Ev, Gv */
5368 if ((opcode & 1) == 0)
5371 ir.ot = ir.dflag + OT_WORD;
5372 if (i386_record_modrm (&ir))
5377 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5379 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5383 if (i386_record_lea_modrm (&ir))
5387 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5389 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5392 case 0xc4: /* les Gv */
5393 case 0xc5: /* lds Gv */
5394 if (ir.regmap[X86_RECORD_R8_REGNUM])
5400 case 0x0fb2: /* lss Gv */
5401 case 0x0fb4: /* lfs Gv */
5402 case 0x0fb5: /* lgs Gv */
5403 if (i386_record_modrm (&ir))
5411 opcode = opcode << 8 | ir.modrm;
5416 case 0xc4: /* les Gv */
5417 regnum = X86_RECORD_ES_REGNUM;
5419 case 0xc5: /* lds Gv */
5420 regnum = X86_RECORD_DS_REGNUM;
5422 case 0x0fb2: /* lss Gv */
5423 regnum = X86_RECORD_SS_REGNUM;
5425 case 0x0fb4: /* lfs Gv */
5426 regnum = X86_RECORD_FS_REGNUM;
5428 case 0x0fb5: /* lgs Gv */
5429 regnum = X86_RECORD_GS_REGNUM;
5432 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5433 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5434 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5437 case 0xc0: /* shifts */
5443 if ((opcode & 1) == 0)
5446 ir.ot = ir.dflag + OT_WORD;
5447 if (i386_record_modrm (&ir))
5449 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
5451 if (i386_record_lea_modrm (&ir))
5457 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5459 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5461 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5468 if (i386_record_modrm (&ir))
5472 if (record_full_arch_list_add_reg (ir.regcache, ir.rm))
5477 if (i386_record_lea_modrm (&ir))
5482 case 0xd8: /* Floats. */
5490 if (i386_record_modrm (&ir))
5492 ir.reg |= ((opcode & 7) << 3);
5498 if (i386_record_lea_modrm_addr (&ir, &addr64))
5506 /* For fcom, ficom nothing to do. */
5512 /* For fcomp, ficomp pop FPU stack, store all. */
5513 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5540 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5541 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5542 of code, always affects st(0) register. */
5543 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
5567 /* Handling fld, fild. */
5568 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5572 switch (ir.reg >> 4)
5575 if (record_full_arch_list_add_mem (addr64, 4))
5579 if (record_full_arch_list_add_mem (addr64, 8))
5585 if (record_full_arch_list_add_mem (addr64, 2))
5591 switch (ir.reg >> 4)
5594 if (record_full_arch_list_add_mem (addr64, 4))
5596 if (3 == (ir.reg & 7))
5598 /* For fstp m32fp. */
5599 if (i386_record_floats (gdbarch, &ir,
5600 I386_SAVE_FPU_REGS))
5605 if (record_full_arch_list_add_mem (addr64, 4))
5607 if ((3 == (ir.reg & 7))
5608 || (5 == (ir.reg & 7))
5609 || (7 == (ir.reg & 7)))
5611 /* For fstp insn. */
5612 if (i386_record_floats (gdbarch, &ir,
5613 I386_SAVE_FPU_REGS))
5618 if (record_full_arch_list_add_mem (addr64, 8))
5620 if (3 == (ir.reg & 7))
5622 /* For fstp m64fp. */
5623 if (i386_record_floats (gdbarch, &ir,
5624 I386_SAVE_FPU_REGS))
5629 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
5631 /* For fistp, fbld, fild, fbstp. */
5632 if (i386_record_floats (gdbarch, &ir,
5633 I386_SAVE_FPU_REGS))
5638 if (record_full_arch_list_add_mem (addr64, 2))
5647 if (i386_record_floats (gdbarch, &ir,
5648 I386_SAVE_FPU_ENV_REG_STACK))
5653 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
5658 if (i386_record_floats (gdbarch, &ir,
5659 I386_SAVE_FPU_ENV_REG_STACK))
5665 if (record_full_arch_list_add_mem (addr64, 28))
5670 if (record_full_arch_list_add_mem (addr64, 14))
5676 if (record_full_arch_list_add_mem (addr64, 2))
5678 /* Insn fstp, fbstp. */
5679 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5684 if (record_full_arch_list_add_mem (addr64, 10))
5690 if (record_full_arch_list_add_mem (addr64, 28))
5696 if (record_full_arch_list_add_mem (addr64, 14))
5700 if (record_full_arch_list_add_mem (addr64, 80))
5703 if (i386_record_floats (gdbarch, &ir,
5704 I386_SAVE_FPU_ENV_REG_STACK))
5708 if (record_full_arch_list_add_mem (addr64, 8))
5711 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5716 opcode = opcode << 8 | ir.modrm;
5721 /* Opcode is an extension of modR/M byte. */
5727 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
5731 if (0x0c == (ir.modrm >> 4))
5733 if ((ir.modrm & 0x0f) <= 7)
5735 if (i386_record_floats (gdbarch, &ir,
5736 I386_SAVE_FPU_REGS))
5741 if (i386_record_floats (gdbarch, &ir,
5742 I387_ST0_REGNUM (tdep)))
5744 /* If only st(0) is changing, then we have already
5746 if ((ir.modrm & 0x0f) - 0x08)
5748 if (i386_record_floats (gdbarch, &ir,
5749 I387_ST0_REGNUM (tdep) +
5750 ((ir.modrm & 0x0f) - 0x08)))
5768 if (i386_record_floats (gdbarch, &ir,
5769 I387_ST0_REGNUM (tdep)))
5787 if (i386_record_floats (gdbarch, &ir,
5788 I386_SAVE_FPU_REGS))
5792 if (i386_record_floats (gdbarch, &ir,
5793 I387_ST0_REGNUM (tdep)))
5795 if (i386_record_floats (gdbarch, &ir,
5796 I387_ST0_REGNUM (tdep) + 1))
5803 if (0xe9 == ir.modrm)
5805 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5808 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
5810 if (i386_record_floats (gdbarch, &ir,
5811 I387_ST0_REGNUM (tdep)))
5813 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
5815 if (i386_record_floats (gdbarch, &ir,
5816 I387_ST0_REGNUM (tdep) +
5820 else if ((ir.modrm & 0x0f) - 0x08)
5822 if (i386_record_floats (gdbarch, &ir,
5823 I387_ST0_REGNUM (tdep) +
5824 ((ir.modrm & 0x0f) - 0x08)))
5830 if (0xe3 == ir.modrm)
5832 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
5835 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
5837 if (i386_record_floats (gdbarch, &ir,
5838 I387_ST0_REGNUM (tdep)))
5840 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
5842 if (i386_record_floats (gdbarch, &ir,
5843 I387_ST0_REGNUM (tdep) +
5847 else if ((ir.modrm & 0x0f) - 0x08)
5849 if (i386_record_floats (gdbarch, &ir,
5850 I387_ST0_REGNUM (tdep) +
5851 ((ir.modrm & 0x0f) - 0x08)))
5857 if ((0x0c == ir.modrm >> 4)
5858 || (0x0d == ir.modrm >> 4)
5859 || (0x0f == ir.modrm >> 4))
5861 if ((ir.modrm & 0x0f) <= 7)
5863 if (i386_record_floats (gdbarch, &ir,
5864 I387_ST0_REGNUM (tdep) +
5870 if (i386_record_floats (gdbarch, &ir,
5871 I387_ST0_REGNUM (tdep) +
5872 ((ir.modrm & 0x0f) - 0x08)))
5878 if (0x0c == ir.modrm >> 4)
5880 if (i386_record_floats (gdbarch, &ir,
5881 I387_FTAG_REGNUM (tdep)))
5884 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
5886 if ((ir.modrm & 0x0f) <= 7)
5888 if (i386_record_floats (gdbarch, &ir,
5889 I387_ST0_REGNUM (tdep) +
5895 if (i386_record_floats (gdbarch, &ir,
5896 I386_SAVE_FPU_REGS))
5902 if ((0x0c == ir.modrm >> 4)
5903 || (0x0e == ir.modrm >> 4)
5904 || (0x0f == ir.modrm >> 4)
5905 || (0xd9 == ir.modrm))
5907 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5912 if (0xe0 == ir.modrm)
5914 if (record_full_arch_list_add_reg (ir.regcache,
5918 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
5920 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5928 case 0xa4: /* movsS */
5930 case 0xaa: /* stosS */
5932 case 0x6c: /* insS */
5934 regcache_raw_read_unsigned (ir.regcache,
5935 ir.regmap[X86_RECORD_RECX_REGNUM],
5941 if ((opcode & 1) == 0)
5944 ir.ot = ir.dflag + OT_WORD;
5945 regcache_raw_read_unsigned (ir.regcache,
5946 ir.regmap[X86_RECORD_REDI_REGNUM],
5949 regcache_raw_read_unsigned (ir.regcache,
5950 ir.regmap[X86_RECORD_ES_REGNUM],
5952 regcache_raw_read_unsigned (ir.regcache,
5953 ir.regmap[X86_RECORD_DS_REGNUM],
5955 if (ir.aflag && (es != ds))
5957 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5958 if (record_full_memory_query)
5962 target_terminal_ours ();
5964 Process record ignores the memory change of instruction at address %s\n\
5965 because it can't get the value of the segment register.\n\
5966 Do you want to stop the program?"),
5967 paddress (gdbarch, ir.orig_addr));
5968 target_terminal_inferior ();
5975 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
5979 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5980 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5981 if (opcode == 0xa4 || opcode == 0xa5)
5982 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5983 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5984 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5988 case 0xa6: /* cmpsS */
5990 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5991 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5992 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5993 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5994 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5997 case 0xac: /* lodsS */
5999 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6000 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6001 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6002 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6003 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6006 case 0xae: /* scasS */
6008 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6009 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6010 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6011 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6014 case 0x6e: /* outsS */
6016 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6017 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6018 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6019 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6022 case 0xe4: /* port I/O */
6026 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6027 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6037 case 0xc2: /* ret im */
6038 case 0xc3: /* ret */
6039 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6040 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6043 case 0xca: /* lret im */
6044 case 0xcb: /* lret */
6045 case 0xcf: /* iret */
6046 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6047 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6048 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6051 case 0xe8: /* call im */
6052 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6054 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6058 case 0x9a: /* lcall im */
6059 if (ir.regmap[X86_RECORD_R8_REGNUM])
6064 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6065 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6069 case 0xe9: /* jmp im */
6070 case 0xea: /* ljmp im */
6071 case 0xeb: /* jmp Jb */
6072 case 0x70: /* jcc Jb */
6088 case 0x0f80: /* jcc Jv */
6106 case 0x0f90: /* setcc Gv */
6122 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6124 if (i386_record_modrm (&ir))
6127 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
6131 if (i386_record_lea_modrm (&ir))
6136 case 0x0f40: /* cmov Gv, Ev */
6152 if (i386_record_modrm (&ir))
6155 if (ir.dflag == OT_BYTE)
6157 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
6161 case 0x9c: /* pushf */
6162 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6163 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6165 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6169 case 0x9d: /* popf */
6170 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6171 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6174 case 0x9e: /* sahf */
6175 if (ir.regmap[X86_RECORD_R8_REGNUM])
6181 case 0xf5: /* cmc */
6182 case 0xf8: /* clc */
6183 case 0xf9: /* stc */
6184 case 0xfc: /* cld */
6185 case 0xfd: /* std */
6186 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6189 case 0x9f: /* lahf */
6190 if (ir.regmap[X86_RECORD_R8_REGNUM])
6195 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6196 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6199 /* bit operations */
6200 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6201 ir.ot = ir.dflag + OT_WORD;
6202 if (i386_record_modrm (&ir))
6207 opcode = opcode << 8 | ir.modrm;
6213 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6216 if (i386_record_lea_modrm (&ir))
6220 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6223 case 0x0fa3: /* bt Gv, Ev */
6224 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6227 case 0x0fab: /* bts */
6228 case 0x0fb3: /* btr */
6229 case 0x0fbb: /* btc */
6230 ir.ot = ir.dflag + OT_WORD;
6231 if (i386_record_modrm (&ir))
6234 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6238 if (i386_record_lea_modrm_addr (&ir, &addr64))
6240 regcache_raw_read_unsigned (ir.regcache,
6241 ir.regmap[ir.reg | rex_r],
6246 addr64 += ((int16_t) addr >> 4) << 4;
6249 addr64 += ((int32_t) addr >> 5) << 5;
6252 addr64 += ((int64_t) addr >> 6) << 6;
6255 if (record_full_arch_list_add_mem (addr64, 1 << ir.ot))
6257 if (i386_record_lea_modrm (&ir))
6260 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6263 case 0x0fbc: /* bsf */
6264 case 0x0fbd: /* bsr */
6265 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6266 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6270 case 0x27: /* daa */
6271 case 0x2f: /* das */
6272 case 0x37: /* aaa */
6273 case 0x3f: /* aas */
6274 case 0xd4: /* aam */
6275 case 0xd5: /* aad */
6276 if (ir.regmap[X86_RECORD_R8_REGNUM])
6281 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6282 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6286 case 0x90: /* nop */
6287 if (prefixes & PREFIX_LOCK)
6294 case 0x9b: /* fwait */
6295 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
6297 opcode = (uint32_t) opcode8;
6303 case 0xcc: /* int3 */
6304 printf_unfiltered (_("Process record does not support instruction "
6311 case 0xcd: /* int */
6315 if (record_read_memory (gdbarch, ir.addr, &interrupt, 1))
6318 if (interrupt != 0x80
6319 || tdep->i386_intx80_record == NULL)
6321 printf_unfiltered (_("Process record does not support "
6322 "instruction int 0x%02x.\n"),
6327 ret = tdep->i386_intx80_record (ir.regcache);
6334 case 0xce: /* into */
6335 printf_unfiltered (_("Process record does not support "
6336 "instruction into.\n"));
6341 case 0xfa: /* cli */
6342 case 0xfb: /* sti */
6345 case 0x62: /* bound */
6346 printf_unfiltered (_("Process record does not support "
6347 "instruction bound.\n"));
6352 case 0x0fc8: /* bswap reg */
6360 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
6363 case 0xd6: /* salc */
6364 if (ir.regmap[X86_RECORD_R8_REGNUM])
6369 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6370 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6373 case 0xe0: /* loopnz */
6374 case 0xe1: /* loopz */
6375 case 0xe2: /* loop */
6376 case 0xe3: /* jecxz */
6377 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6378 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6381 case 0x0f30: /* wrmsr */
6382 printf_unfiltered (_("Process record does not support "
6383 "instruction wrmsr.\n"));
6388 case 0x0f32: /* rdmsr */
6389 printf_unfiltered (_("Process record does not support "
6390 "instruction rdmsr.\n"));
6395 case 0x0f31: /* rdtsc */
6396 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6397 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6400 case 0x0f34: /* sysenter */
6403 if (ir.regmap[X86_RECORD_R8_REGNUM])
6408 if (tdep->i386_sysenter_record == NULL)
6410 printf_unfiltered (_("Process record does not support "
6411 "instruction sysenter.\n"));
6415 ret = tdep->i386_sysenter_record (ir.regcache);
6421 case 0x0f35: /* sysexit */
6422 printf_unfiltered (_("Process record does not support "
6423 "instruction sysexit.\n"));
6428 case 0x0f05: /* syscall */
6431 if (tdep->i386_syscall_record == NULL)
6433 printf_unfiltered (_("Process record does not support "
6434 "instruction syscall.\n"));
6438 ret = tdep->i386_syscall_record (ir.regcache);
6444 case 0x0f07: /* sysret */
6445 printf_unfiltered (_("Process record does not support "
6446 "instruction sysret.\n"));
6451 case 0x0fa2: /* cpuid */
6452 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6453 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6454 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6455 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
6458 case 0xf4: /* hlt */
6459 printf_unfiltered (_("Process record does not support "
6460 "instruction hlt.\n"));
6466 if (i386_record_modrm (&ir))
6473 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6477 if (i386_record_lea_modrm (&ir))
6486 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6490 opcode = opcode << 8 | ir.modrm;
6497 if (i386_record_modrm (&ir))
6508 opcode = opcode << 8 | ir.modrm;
6511 if (ir.override >= 0)
6513 if (record_full_memory_query)
6517 target_terminal_ours ();
6519 Process record ignores the memory change of instruction at address %s\n\
6520 because it can't get the value of the segment register.\n\
6521 Do you want to stop the program?"),
6522 paddress (gdbarch, ir.orig_addr));
6523 target_terminal_inferior ();
6530 if (i386_record_lea_modrm_addr (&ir, &addr64))
6532 if (record_full_arch_list_add_mem (addr64, 2))
6535 if (ir.regmap[X86_RECORD_R8_REGNUM])
6537 if (record_full_arch_list_add_mem (addr64, 8))
6542 if (record_full_arch_list_add_mem (addr64, 4))
6553 case 0: /* monitor */
6556 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6560 opcode = opcode << 8 | ir.modrm;
6568 if (ir.override >= 0)
6570 if (record_full_memory_query)
6574 target_terminal_ours ();
6576 Process record ignores the memory change of instruction at address %s\n\
6577 because it can't get the value of the segment register.\n\
6578 Do you want to stop the program?"),
6579 paddress (gdbarch, ir.orig_addr));
6580 target_terminal_inferior ();
6589 if (i386_record_lea_modrm_addr (&ir, &addr64))
6591 if (record_full_arch_list_add_mem (addr64, 2))
6594 if (ir.regmap[X86_RECORD_R8_REGNUM])
6596 if (record_full_arch_list_add_mem (addr64, 8))
6601 if (record_full_arch_list_add_mem (addr64, 4))
6613 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6614 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6618 else if (ir.rm == 1)
6625 opcode = opcode << 8 | ir.modrm;
6632 if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
6638 if (i386_record_lea_modrm (&ir))
6641 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6644 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6646 case 7: /* invlpg */
6649 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
6650 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
6654 opcode = opcode << 8 | ir.modrm;
6659 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6663 opcode = opcode << 8 | ir.modrm;
6669 case 0x0f08: /* invd */
6670 case 0x0f09: /* wbinvd */
6673 case 0x63: /* arpl */
6674 if (i386_record_modrm (&ir))
6676 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
6678 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
6679 ? (ir.reg | rex_r) : ir.rm);
6683 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
6684 if (i386_record_lea_modrm (&ir))
6687 if (!ir.regmap[X86_RECORD_R8_REGNUM])
6688 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6691 case 0x0f02: /* lar */
6692 case 0x0f03: /* lsl */
6693 if (i386_record_modrm (&ir))
6695 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6696 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6700 if (i386_record_modrm (&ir))
6702 if (ir.mod == 3 && ir.reg == 3)
6705 opcode = opcode << 8 | ir.modrm;
6717 /* nop (multi byte) */
6720 case 0x0f20: /* mov reg, crN */
6721 case 0x0f22: /* mov crN, reg */
6722 if (i386_record_modrm (&ir))
6724 if ((ir.modrm & 0xc0) != 0xc0)
6727 opcode = opcode << 8 | ir.modrm;
6738 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6740 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6744 opcode = opcode << 8 | ir.modrm;
6750 case 0x0f21: /* mov reg, drN */
6751 case 0x0f23: /* mov drN, reg */
6752 if (i386_record_modrm (&ir))
6754 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
6755 || ir.reg == 5 || ir.reg >= 8)
6758 opcode = opcode << 8 | ir.modrm;
6762 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6764 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6767 case 0x0f06: /* clts */
6768 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6771 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
6773 case 0x0f0d: /* 3DNow! prefetch */
6776 case 0x0f0e: /* 3DNow! femms */
6777 case 0x0f77: /* emms */
6778 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
6780 record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
6783 case 0x0f0f: /* 3DNow! data */
6784 if (i386_record_modrm (&ir))
6786 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
6791 case 0x0c: /* 3DNow! pi2fw */
6792 case 0x0d: /* 3DNow! pi2fd */
6793 case 0x1c: /* 3DNow! pf2iw */
6794 case 0x1d: /* 3DNow! pf2id */
6795 case 0x8a: /* 3DNow! pfnacc */
6796 case 0x8e: /* 3DNow! pfpnacc */
6797 case 0x90: /* 3DNow! pfcmpge */
6798 case 0x94: /* 3DNow! pfmin */
6799 case 0x96: /* 3DNow! pfrcp */
6800 case 0x97: /* 3DNow! pfrsqrt */
6801 case 0x9a: /* 3DNow! pfsub */
6802 case 0x9e: /* 3DNow! pfadd */
6803 case 0xa0: /* 3DNow! pfcmpgt */
6804 case 0xa4: /* 3DNow! pfmax */
6805 case 0xa6: /* 3DNow! pfrcpit1 */
6806 case 0xa7: /* 3DNow! pfrsqit1 */
6807 case 0xaa: /* 3DNow! pfsubr */
6808 case 0xae: /* 3DNow! pfacc */
6809 case 0xb0: /* 3DNow! pfcmpeq */
6810 case 0xb4: /* 3DNow! pfmul */
6811 case 0xb6: /* 3DNow! pfrcpit2 */
6812 case 0xb7: /* 3DNow! pmulhrw */
6813 case 0xbb: /* 3DNow! pswapd */
6814 case 0xbf: /* 3DNow! pavgusb */
6815 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
6816 goto no_support_3dnow_data;
6817 record_full_arch_list_add_reg (ir.regcache, ir.reg);
6821 no_support_3dnow_data:
6822 opcode = (opcode << 8) | opcode8;
6828 case 0x0faa: /* rsm */
6829 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6830 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6831 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6832 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6833 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
6834 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6835 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
6836 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6837 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6841 if (i386_record_modrm (&ir))
6845 case 0: /* fxsave */
6849 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6850 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
6852 if (record_full_arch_list_add_mem (tmpu64, 512))
6857 case 1: /* fxrstor */
6861 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6863 for (i = I387_MM0_REGNUM (tdep);
6864 i386_mmx_regnum_p (gdbarch, i); i++)
6865 record_full_arch_list_add_reg (ir.regcache, i);
6867 for (i = I387_XMM0_REGNUM (tdep);
6868 i386_xmm_regnum_p (gdbarch, i); i++)
6869 record_full_arch_list_add_reg (ir.regcache, i);
6871 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
6872 record_full_arch_list_add_reg (ir.regcache,
6873 I387_MXCSR_REGNUM(tdep));
6875 for (i = I387_ST0_REGNUM (tdep);
6876 i386_fp_regnum_p (gdbarch, i); i++)
6877 record_full_arch_list_add_reg (ir.regcache, i);
6879 for (i = I387_FCTRL_REGNUM (tdep);
6880 i386_fpc_regnum_p (gdbarch, i); i++)
6881 record_full_arch_list_add_reg (ir.regcache, i);
6885 case 2: /* ldmxcsr */
6886 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
6888 record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
6891 case 3: /* stmxcsr */
6893 if (i386_record_lea_modrm (&ir))
6897 case 5: /* lfence */
6898 case 6: /* mfence */
6899 case 7: /* sfence clflush */
6903 opcode = (opcode << 8) | ir.modrm;
6909 case 0x0fc3: /* movnti */
6910 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
6911 if (i386_record_modrm (&ir))
6916 if (i386_record_lea_modrm (&ir))
6920 /* Add prefix to opcode. */
7047 reswitch_prefix_add:
7055 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7058 opcode = (uint32_t) opcode8 | opcode << 8;
7059 goto reswitch_prefix_add;
7062 case 0x0f10: /* movups */
7063 case 0x660f10: /* movupd */
7064 case 0xf30f10: /* movss */
7065 case 0xf20f10: /* movsd */
7066 case 0x0f12: /* movlps */
7067 case 0x660f12: /* movlpd */
7068 case 0xf30f12: /* movsldup */
7069 case 0xf20f12: /* movddup */
7070 case 0x0f14: /* unpcklps */
7071 case 0x660f14: /* unpcklpd */
7072 case 0x0f15: /* unpckhps */
7073 case 0x660f15: /* unpckhpd */
7074 case 0x0f16: /* movhps */
7075 case 0x660f16: /* movhpd */
7076 case 0xf30f16: /* movshdup */
7077 case 0x0f28: /* movaps */
7078 case 0x660f28: /* movapd */
7079 case 0x0f2a: /* cvtpi2ps */
7080 case 0x660f2a: /* cvtpi2pd */
7081 case 0xf30f2a: /* cvtsi2ss */
7082 case 0xf20f2a: /* cvtsi2sd */
7083 case 0x0f2c: /* cvttps2pi */
7084 case 0x660f2c: /* cvttpd2pi */
7085 case 0x0f2d: /* cvtps2pi */
7086 case 0x660f2d: /* cvtpd2pi */
7087 case 0x660f3800: /* pshufb */
7088 case 0x660f3801: /* phaddw */
7089 case 0x660f3802: /* phaddd */
7090 case 0x660f3803: /* phaddsw */
7091 case 0x660f3804: /* pmaddubsw */
7092 case 0x660f3805: /* phsubw */
7093 case 0x660f3806: /* phsubd */
7094 case 0x660f3807: /* phsubsw */
7095 case 0x660f3808: /* psignb */
7096 case 0x660f3809: /* psignw */
7097 case 0x660f380a: /* psignd */
7098 case 0x660f380b: /* pmulhrsw */
7099 case 0x660f3810: /* pblendvb */
7100 case 0x660f3814: /* blendvps */
7101 case 0x660f3815: /* blendvpd */
7102 case 0x660f381c: /* pabsb */
7103 case 0x660f381d: /* pabsw */
7104 case 0x660f381e: /* pabsd */
7105 case 0x660f3820: /* pmovsxbw */
7106 case 0x660f3821: /* pmovsxbd */
7107 case 0x660f3822: /* pmovsxbq */
7108 case 0x660f3823: /* pmovsxwd */
7109 case 0x660f3824: /* pmovsxwq */
7110 case 0x660f3825: /* pmovsxdq */
7111 case 0x660f3828: /* pmuldq */
7112 case 0x660f3829: /* pcmpeqq */
7113 case 0x660f382a: /* movntdqa */
7114 case 0x660f3a08: /* roundps */
7115 case 0x660f3a09: /* roundpd */
7116 case 0x660f3a0a: /* roundss */
7117 case 0x660f3a0b: /* roundsd */
7118 case 0x660f3a0c: /* blendps */
7119 case 0x660f3a0d: /* blendpd */
7120 case 0x660f3a0e: /* pblendw */
7121 case 0x660f3a0f: /* palignr */
7122 case 0x660f3a20: /* pinsrb */
7123 case 0x660f3a21: /* insertps */
7124 case 0x660f3a22: /* pinsrd pinsrq */
7125 case 0x660f3a40: /* dpps */
7126 case 0x660f3a41: /* dppd */
7127 case 0x660f3a42: /* mpsadbw */
7128 case 0x660f3a60: /* pcmpestrm */
7129 case 0x660f3a61: /* pcmpestri */
7130 case 0x660f3a62: /* pcmpistrm */
7131 case 0x660f3a63: /* pcmpistri */
7132 case 0x0f51: /* sqrtps */
7133 case 0x660f51: /* sqrtpd */
7134 case 0xf20f51: /* sqrtsd */
7135 case 0xf30f51: /* sqrtss */
7136 case 0x0f52: /* rsqrtps */
7137 case 0xf30f52: /* rsqrtss */
7138 case 0x0f53: /* rcpps */
7139 case 0xf30f53: /* rcpss */
7140 case 0x0f54: /* andps */
7141 case 0x660f54: /* andpd */
7142 case 0x0f55: /* andnps */
7143 case 0x660f55: /* andnpd */
7144 case 0x0f56: /* orps */
7145 case 0x660f56: /* orpd */
7146 case 0x0f57: /* xorps */
7147 case 0x660f57: /* xorpd */
7148 case 0x0f58: /* addps */
7149 case 0x660f58: /* addpd */
7150 case 0xf20f58: /* addsd */
7151 case 0xf30f58: /* addss */
7152 case 0x0f59: /* mulps */
7153 case 0x660f59: /* mulpd */
7154 case 0xf20f59: /* mulsd */
7155 case 0xf30f59: /* mulss */
7156 case 0x0f5a: /* cvtps2pd */
7157 case 0x660f5a: /* cvtpd2ps */
7158 case 0xf20f5a: /* cvtsd2ss */
7159 case 0xf30f5a: /* cvtss2sd */
7160 case 0x0f5b: /* cvtdq2ps */
7161 case 0x660f5b: /* cvtps2dq */
7162 case 0xf30f5b: /* cvttps2dq */
7163 case 0x0f5c: /* subps */
7164 case 0x660f5c: /* subpd */
7165 case 0xf20f5c: /* subsd */
7166 case 0xf30f5c: /* subss */
7167 case 0x0f5d: /* minps */
7168 case 0x660f5d: /* minpd */
7169 case 0xf20f5d: /* minsd */
7170 case 0xf30f5d: /* minss */
7171 case 0x0f5e: /* divps */
7172 case 0x660f5e: /* divpd */
7173 case 0xf20f5e: /* divsd */
7174 case 0xf30f5e: /* divss */
7175 case 0x0f5f: /* maxps */
7176 case 0x660f5f: /* maxpd */
7177 case 0xf20f5f: /* maxsd */
7178 case 0xf30f5f: /* maxss */
7179 case 0x660f60: /* punpcklbw */
7180 case 0x660f61: /* punpcklwd */
7181 case 0x660f62: /* punpckldq */
7182 case 0x660f63: /* packsswb */
7183 case 0x660f64: /* pcmpgtb */
7184 case 0x660f65: /* pcmpgtw */
7185 case 0x660f66: /* pcmpgtd */
7186 case 0x660f67: /* packuswb */
7187 case 0x660f68: /* punpckhbw */
7188 case 0x660f69: /* punpckhwd */
7189 case 0x660f6a: /* punpckhdq */
7190 case 0x660f6b: /* packssdw */
7191 case 0x660f6c: /* punpcklqdq */
7192 case 0x660f6d: /* punpckhqdq */
7193 case 0x660f6e: /* movd */
7194 case 0x660f6f: /* movdqa */
7195 case 0xf30f6f: /* movdqu */
7196 case 0x660f70: /* pshufd */
7197 case 0xf20f70: /* pshuflw */
7198 case 0xf30f70: /* pshufhw */
7199 case 0x660f74: /* pcmpeqb */
7200 case 0x660f75: /* pcmpeqw */
7201 case 0x660f76: /* pcmpeqd */
7202 case 0x660f7c: /* haddpd */
7203 case 0xf20f7c: /* haddps */
7204 case 0x660f7d: /* hsubpd */
7205 case 0xf20f7d: /* hsubps */
7206 case 0xf30f7e: /* movq */
7207 case 0x0fc2: /* cmpps */
7208 case 0x660fc2: /* cmppd */
7209 case 0xf20fc2: /* cmpsd */
7210 case 0xf30fc2: /* cmpss */
7211 case 0x660fc4: /* pinsrw */
7212 case 0x0fc6: /* shufps */
7213 case 0x660fc6: /* shufpd */
7214 case 0x660fd0: /* addsubpd */
7215 case 0xf20fd0: /* addsubps */
7216 case 0x660fd1: /* psrlw */
7217 case 0x660fd2: /* psrld */
7218 case 0x660fd3: /* psrlq */
7219 case 0x660fd4: /* paddq */
7220 case 0x660fd5: /* pmullw */
7221 case 0xf30fd6: /* movq2dq */
7222 case 0x660fd8: /* psubusb */
7223 case 0x660fd9: /* psubusw */
7224 case 0x660fda: /* pminub */
7225 case 0x660fdb: /* pand */
7226 case 0x660fdc: /* paddusb */
7227 case 0x660fdd: /* paddusw */
7228 case 0x660fde: /* pmaxub */
7229 case 0x660fdf: /* pandn */
7230 case 0x660fe0: /* pavgb */
7231 case 0x660fe1: /* psraw */
7232 case 0x660fe2: /* psrad */
7233 case 0x660fe3: /* pavgw */
7234 case 0x660fe4: /* pmulhuw */
7235 case 0x660fe5: /* pmulhw */
7236 case 0x660fe6: /* cvttpd2dq */
7237 case 0xf20fe6: /* cvtpd2dq */
7238 case 0xf30fe6: /* cvtdq2pd */
7239 case 0x660fe8: /* psubsb */
7240 case 0x660fe9: /* psubsw */
7241 case 0x660fea: /* pminsw */
7242 case 0x660feb: /* por */
7243 case 0x660fec: /* paddsb */
7244 case 0x660fed: /* paddsw */
7245 case 0x660fee: /* pmaxsw */
7246 case 0x660fef: /* pxor */
7247 case 0xf20ff0: /* lddqu */
7248 case 0x660ff1: /* psllw */
7249 case 0x660ff2: /* pslld */
7250 case 0x660ff3: /* psllq */
7251 case 0x660ff4: /* pmuludq */
7252 case 0x660ff5: /* pmaddwd */
7253 case 0x660ff6: /* psadbw */
7254 case 0x660ff8: /* psubb */
7255 case 0x660ff9: /* psubw */
7256 case 0x660ffa: /* psubd */
7257 case 0x660ffb: /* psubq */
7258 case 0x660ffc: /* paddb */
7259 case 0x660ffd: /* paddw */
7260 case 0x660ffe: /* paddd */
7261 if (i386_record_modrm (&ir))
7264 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
7266 record_full_arch_list_add_reg (ir.regcache,
7267 I387_XMM0_REGNUM (tdep) + ir.reg);
7268 if ((opcode & 0xfffffffc) == 0x660f3a60)
7269 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7272 case 0x0f11: /* movups */
7273 case 0x660f11: /* movupd */
7274 case 0xf30f11: /* movss */
7275 case 0xf20f11: /* movsd */
7276 case 0x0f13: /* movlps */
7277 case 0x660f13: /* movlpd */
7278 case 0x0f17: /* movhps */
7279 case 0x660f17: /* movhpd */
7280 case 0x0f29: /* movaps */
7281 case 0x660f29: /* movapd */
7282 case 0x660f3a14: /* pextrb */
7283 case 0x660f3a15: /* pextrw */
7284 case 0x660f3a16: /* pextrd pextrq */
7285 case 0x660f3a17: /* extractps */
7286 case 0x660f7f: /* movdqa */
7287 case 0xf30f7f: /* movdqu */
7288 if (i386_record_modrm (&ir))
7292 if (opcode == 0x0f13 || opcode == 0x660f13
7293 || opcode == 0x0f17 || opcode == 0x660f17)
7296 if (!i386_xmm_regnum_p (gdbarch,
7297 I387_XMM0_REGNUM (tdep) + ir.rm))
7299 record_full_arch_list_add_reg (ir.regcache,
7300 I387_XMM0_REGNUM (tdep) + ir.rm);
7322 if (i386_record_lea_modrm (&ir))
7327 case 0x0f2b: /* movntps */
7328 case 0x660f2b: /* movntpd */
7329 case 0x0fe7: /* movntq */
7330 case 0x660fe7: /* movntdq */
7333 if (opcode == 0x0fe7)
7337 if (i386_record_lea_modrm (&ir))
7341 case 0xf30f2c: /* cvttss2si */
7342 case 0xf20f2c: /* cvttsd2si */
7343 case 0xf30f2d: /* cvtss2si */
7344 case 0xf20f2d: /* cvtsd2si */
7345 case 0xf20f38f0: /* crc32 */
7346 case 0xf20f38f1: /* crc32 */
7347 case 0x0f50: /* movmskps */
7348 case 0x660f50: /* movmskpd */
7349 case 0x0fc5: /* pextrw */
7350 case 0x660fc5: /* pextrw */
7351 case 0x0fd7: /* pmovmskb */
7352 case 0x660fd7: /* pmovmskb */
7353 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7356 case 0x0f3800: /* pshufb */
7357 case 0x0f3801: /* phaddw */
7358 case 0x0f3802: /* phaddd */
7359 case 0x0f3803: /* phaddsw */
7360 case 0x0f3804: /* pmaddubsw */
7361 case 0x0f3805: /* phsubw */
7362 case 0x0f3806: /* phsubd */
7363 case 0x0f3807: /* phsubsw */
7364 case 0x0f3808: /* psignb */
7365 case 0x0f3809: /* psignw */
7366 case 0x0f380a: /* psignd */
7367 case 0x0f380b: /* pmulhrsw */
7368 case 0x0f381c: /* pabsb */
7369 case 0x0f381d: /* pabsw */
7370 case 0x0f381e: /* pabsd */
7371 case 0x0f382b: /* packusdw */
7372 case 0x0f3830: /* pmovzxbw */
7373 case 0x0f3831: /* pmovzxbd */
7374 case 0x0f3832: /* pmovzxbq */
7375 case 0x0f3833: /* pmovzxwd */
7376 case 0x0f3834: /* pmovzxwq */
7377 case 0x0f3835: /* pmovzxdq */
7378 case 0x0f3837: /* pcmpgtq */
7379 case 0x0f3838: /* pminsb */
7380 case 0x0f3839: /* pminsd */
7381 case 0x0f383a: /* pminuw */
7382 case 0x0f383b: /* pminud */
7383 case 0x0f383c: /* pmaxsb */
7384 case 0x0f383d: /* pmaxsd */
7385 case 0x0f383e: /* pmaxuw */
7386 case 0x0f383f: /* pmaxud */
7387 case 0x0f3840: /* pmulld */
7388 case 0x0f3841: /* phminposuw */
7389 case 0x0f3a0f: /* palignr */
7390 case 0x0f60: /* punpcklbw */
7391 case 0x0f61: /* punpcklwd */
7392 case 0x0f62: /* punpckldq */
7393 case 0x0f63: /* packsswb */
7394 case 0x0f64: /* pcmpgtb */
7395 case 0x0f65: /* pcmpgtw */
7396 case 0x0f66: /* pcmpgtd */
7397 case 0x0f67: /* packuswb */
7398 case 0x0f68: /* punpckhbw */
7399 case 0x0f69: /* punpckhwd */
7400 case 0x0f6a: /* punpckhdq */
7401 case 0x0f6b: /* packssdw */
7402 case 0x0f6e: /* movd */
7403 case 0x0f6f: /* movq */
7404 case 0x0f70: /* pshufw */
7405 case 0x0f74: /* pcmpeqb */
7406 case 0x0f75: /* pcmpeqw */
7407 case 0x0f76: /* pcmpeqd */
7408 case 0x0fc4: /* pinsrw */
7409 case 0x0fd1: /* psrlw */
7410 case 0x0fd2: /* psrld */
7411 case 0x0fd3: /* psrlq */
7412 case 0x0fd4: /* paddq */
7413 case 0x0fd5: /* pmullw */
7414 case 0xf20fd6: /* movdq2q */
7415 case 0x0fd8: /* psubusb */
7416 case 0x0fd9: /* psubusw */
7417 case 0x0fda: /* pminub */
7418 case 0x0fdb: /* pand */
7419 case 0x0fdc: /* paddusb */
7420 case 0x0fdd: /* paddusw */
7421 case 0x0fde: /* pmaxub */
7422 case 0x0fdf: /* pandn */
7423 case 0x0fe0: /* pavgb */
7424 case 0x0fe1: /* psraw */
7425 case 0x0fe2: /* psrad */
7426 case 0x0fe3: /* pavgw */
7427 case 0x0fe4: /* pmulhuw */
7428 case 0x0fe5: /* pmulhw */
7429 case 0x0fe8: /* psubsb */
7430 case 0x0fe9: /* psubsw */
7431 case 0x0fea: /* pminsw */
7432 case 0x0feb: /* por */
7433 case 0x0fec: /* paddsb */
7434 case 0x0fed: /* paddsw */
7435 case 0x0fee: /* pmaxsw */
7436 case 0x0fef: /* pxor */
7437 case 0x0ff1: /* psllw */
7438 case 0x0ff2: /* pslld */
7439 case 0x0ff3: /* psllq */
7440 case 0x0ff4: /* pmuludq */
7441 case 0x0ff5: /* pmaddwd */
7442 case 0x0ff6: /* psadbw */
7443 case 0x0ff8: /* psubb */
7444 case 0x0ff9: /* psubw */
7445 case 0x0ffa: /* psubd */
7446 case 0x0ffb: /* psubq */
7447 case 0x0ffc: /* paddb */
7448 case 0x0ffd: /* paddw */
7449 case 0x0ffe: /* paddd */
7450 if (i386_record_modrm (&ir))
7452 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7454 record_full_arch_list_add_reg (ir.regcache,
7455 I387_MM0_REGNUM (tdep) + ir.reg);
7458 case 0x0f71: /* psllw */
7459 case 0x0f72: /* pslld */
7460 case 0x0f73: /* psllq */
7461 if (i386_record_modrm (&ir))
7463 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7465 record_full_arch_list_add_reg (ir.regcache,
7466 I387_MM0_REGNUM (tdep) + ir.rm);
7469 case 0x660f71: /* psllw */
7470 case 0x660f72: /* pslld */
7471 case 0x660f73: /* psllq */
7472 if (i386_record_modrm (&ir))
7475 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
7477 record_full_arch_list_add_reg (ir.regcache,
7478 I387_XMM0_REGNUM (tdep) + ir.rm);
7481 case 0x0f7e: /* movd */
7482 case 0x660f7e: /* movd */
7483 if (i386_record_modrm (&ir))
7486 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7493 if (i386_record_lea_modrm (&ir))
7498 case 0x0f7f: /* movq */
7499 if (i386_record_modrm (&ir))
7503 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7505 record_full_arch_list_add_reg (ir.regcache,
7506 I387_MM0_REGNUM (tdep) + ir.rm);
7511 if (i386_record_lea_modrm (&ir))
7516 case 0xf30fb8: /* popcnt */
7517 if (i386_record_modrm (&ir))
7519 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
7520 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7523 case 0x660fd6: /* movq */
7524 if (i386_record_modrm (&ir))
7529 if (!i386_xmm_regnum_p (gdbarch,
7530 I387_XMM0_REGNUM (tdep) + ir.rm))
7532 record_full_arch_list_add_reg (ir.regcache,
7533 I387_XMM0_REGNUM (tdep) + ir.rm);
7538 if (i386_record_lea_modrm (&ir))
7543 case 0x660f3817: /* ptest */
7544 case 0x0f2e: /* ucomiss */
7545 case 0x660f2e: /* ucomisd */
7546 case 0x0f2f: /* comiss */
7547 case 0x660f2f: /* comisd */
7548 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7551 case 0x0ff7: /* maskmovq */
7552 regcache_raw_read_unsigned (ir.regcache,
7553 ir.regmap[X86_RECORD_REDI_REGNUM],
7555 if (record_full_arch_list_add_mem (addr, 64))
7559 case 0x660ff7: /* maskmovdqu */
7560 regcache_raw_read_unsigned (ir.regcache,
7561 ir.regmap[X86_RECORD_REDI_REGNUM],
7563 if (record_full_arch_list_add_mem (addr, 128))
7578 /* In the future, maybe still need to deal with need_dasm. */
7579 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
7580 if (record_full_arch_list_add_end ())
7586 printf_unfiltered (_("Process record does not support instruction 0x%02x "
7587 "at address %s.\n"),
7588 (unsigned int) (opcode),
7589 paddress (gdbarch, ir.orig_addr));
7593 static const int i386_record_regmap[] =
7595 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
7596 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
7597 0, 0, 0, 0, 0, 0, 0, 0,
7598 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
7599 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
7602 /* Check that the given address appears suitable for a fast
7603 tracepoint, which on x86-64 means that we need an instruction of at
7604 least 5 bytes, so that we can overwrite it with a 4-byte-offset
7605 jump and not have to worry about program jumps to an address in the
7606 middle of the tracepoint jump. On x86, it may be possible to use
7607 4-byte jumps with a 2-byte offset to a trampoline located in the
7608 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
7609 of instruction to replace, and 0 if not, plus an explanatory
7613 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch,
7614 CORE_ADDR addr, int *isize, char **msg)
7617 static struct ui_file *gdb_null = NULL;
7619 /* Ask the target for the minimum instruction length supported. */
7620 jumplen = target_get_min_fast_tracepoint_insn_len ();
7624 /* If the target does not support the get_min_fast_tracepoint_insn_len
7625 operation, assume that fast tracepoints will always be implemented
7626 using 4-byte relative jumps on both x86 and x86-64. */
7629 else if (jumplen == 0)
7631 /* If the target does support get_min_fast_tracepoint_insn_len but
7632 returns zero, then the IPA has not loaded yet. In this case,
7633 we optimistically assume that truncated 2-byte relative jumps
7634 will be available on x86, and compensate later if this assumption
7635 turns out to be incorrect. On x86-64 architectures, 4-byte relative
7636 jumps will always be used. */
7637 jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4;
7640 /* Dummy file descriptor for the disassembler. */
7642 gdb_null = ui_file_new ();
7644 /* Check for fit. */
7645 len = gdb_print_insn (gdbarch, addr, gdb_null, NULL);
7651 /* Return a bit of target-specific detail to add to the caller's
7652 generic failure message. */
7654 *msg = xstrprintf (_("; instruction is only %d bytes long, "
7655 "need at least %d bytes for the jump"),
7668 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
7669 struct tdesc_arch_data *tdesc_data)
7671 const struct target_desc *tdesc = tdep->tdesc;
7672 const struct tdesc_feature *feature_core;
7673 const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx;
7674 int i, num_regs, valid_p;
7676 if (! tdesc_has_registers (tdesc))
7679 /* Get core registers. */
7680 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
7681 if (feature_core == NULL)
7684 /* Get SSE registers. */
7685 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
7687 /* Try AVX registers. */
7688 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
7690 /* Try MPX registers. */
7691 feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx");
7695 /* The XCR0 bits. */
7698 /* AVX register description requires SSE register description. */
7702 tdep->xcr0 = I386_XSTATE_AVX_MASK;
7704 /* It may have been set by OSABI initialization function. */
7705 if (tdep->num_ymm_regs == 0)
7707 tdep->ymmh_register_names = i386_ymmh_names;
7708 tdep->num_ymm_regs = 8;
7709 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
7712 for (i = 0; i < tdep->num_ymm_regs; i++)
7713 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
7714 tdep->ymm0h_regnum + i,
7715 tdep->ymmh_register_names[i]);
7717 else if (feature_sse)
7718 tdep->xcr0 = I386_XSTATE_SSE_MASK;
7721 tdep->xcr0 = I386_XSTATE_X87_MASK;
7722 tdep->num_xmm_regs = 0;
7725 num_regs = tdep->num_core_regs;
7726 for (i = 0; i < num_regs; i++)
7727 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
7728 tdep->register_names[i]);
7732 /* Need to include %mxcsr, so add one. */
7733 num_regs += tdep->num_xmm_regs + 1;
7734 for (; i < num_regs; i++)
7735 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
7736 tdep->register_names[i]);
7741 tdep->xcr0 = I386_XSTATE_MPX_MASK;
7743 if (tdep->bnd0r_regnum < 0)
7745 tdep->mpx_register_names = i386_mpx_names;
7746 tdep->bnd0r_regnum = I386_BND0R_REGNUM;
7747 tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM;
7750 for (i = 0; i < I387_NUM_MPX_REGS; i++)
7751 valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data,
7752 I387_BND0R_REGNUM (tdep) + i,
7753 tdep->mpx_register_names[i]);
7760 static struct gdbarch *
7761 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
7763 struct gdbarch_tdep *tdep;
7764 struct gdbarch *gdbarch;
7765 struct tdesc_arch_data *tdesc_data;
7766 const struct target_desc *tdesc;
7772 /* If there is already a candidate, use it. */
7773 arches = gdbarch_list_lookup_by_info (arches, &info);
7775 return arches->gdbarch;
7777 /* Allocate space for the new architecture. */
7778 tdep = XCALLOC (1, struct gdbarch_tdep);
7779 gdbarch = gdbarch_alloc (&info, tdep);
7781 /* General-purpose registers. */
7782 tdep->gregset = NULL;
7783 tdep->gregset_reg_offset = NULL;
7784 tdep->gregset_num_regs = I386_NUM_GREGS;
7785 tdep->sizeof_gregset = 0;
7787 /* Floating-point registers. */
7788 tdep->fpregset = NULL;
7789 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
7791 tdep->xstateregset = NULL;
7793 /* The default settings include the FPU registers, the MMX registers
7794 and the SSE registers. This can be overridden for a specific ABI
7795 by adjusting the members `st0_regnum', `mm0_regnum' and
7796 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
7797 will show up in the output of "info all-registers". */
7799 tdep->st0_regnum = I386_ST0_REGNUM;
7801 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
7802 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
7804 tdep->jb_pc_offset = -1;
7805 tdep->struct_return = pcc_struct_return;
7806 tdep->sigtramp_start = 0;
7807 tdep->sigtramp_end = 0;
7808 tdep->sigtramp_p = i386_sigtramp_p;
7809 tdep->sigcontext_addr = NULL;
7810 tdep->sc_reg_offset = NULL;
7811 tdep->sc_pc_offset = -1;
7812 tdep->sc_sp_offset = -1;
7814 tdep->xsave_xcr0_offset = -1;
7816 tdep->record_regmap = i386_record_regmap;
7818 set_gdbarch_long_long_align_bit (gdbarch, 32);
7820 /* The format used for `long double' on almost all i386 targets is
7821 the i387 extended floating-point format. In fact, of all targets
7822 in the GCC 2.95 tree, only OSF/1 does it different, and insists
7823 on having a `long double' that's not `long' at all. */
7824 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
7826 /* Although the i387 extended floating-point has only 80 significant
7827 bits, a `long double' actually takes up 96, probably to enforce
7829 set_gdbarch_long_double_bit (gdbarch, 96);
7831 /* Register numbers of various important registers. */
7832 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
7833 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
7834 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
7835 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
7837 /* NOTE: kettenis/20040418: GCC does have two possible register
7838 numbering schemes on the i386: dbx and SVR4. These schemes
7839 differ in how they number %ebp, %esp, %eflags, and the
7840 floating-point registers, and are implemented by the arrays
7841 dbx_register_map[] and svr4_dbx_register_map in
7842 gcc/config/i386.c. GCC also defines a third numbering scheme in
7843 gcc/config/i386.c, which it designates as the "default" register
7844 map used in 64bit mode. This last register numbering scheme is
7845 implemented in dbx64_register_map, and is used for AMD64; see
7848 Currently, each GCC i386 target always uses the same register
7849 numbering scheme across all its supported debugging formats
7850 i.e. SDB (COFF), stabs and DWARF 2. This is because
7851 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7852 DBX_REGISTER_NUMBER macro which is defined by each target's
7853 respective config header in a manner independent of the requested
7854 output debugging format.
7856 This does not match the arrangement below, which presumes that
7857 the SDB and stabs numbering schemes differ from the DWARF and
7858 DWARF 2 ones. The reason for this arrangement is that it is
7859 likely to get the numbering scheme for the target's
7860 default/native debug format right. For targets where GCC is the
7861 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7862 targets where the native toolchain uses a different numbering
7863 scheme for a particular debug format (stabs-in-ELF on Solaris)
7864 the defaults below will have to be overridden, like
7865 i386_elf_init_abi() does. */
7867 /* Use the dbx register numbering scheme for stabs and COFF. */
7868 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
7869 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
7871 /* Use the SVR4 register numbering scheme for DWARF 2. */
7872 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
7874 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7875 be in use on any of the supported i386 targets. */
7877 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
7879 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
7881 /* Call dummy code. */
7882 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
7883 set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code);
7884 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
7885 set_gdbarch_frame_align (gdbarch, i386_frame_align);
7887 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
7888 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
7889 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
7891 set_gdbarch_return_value (gdbarch, i386_return_value);
7893 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
7895 /* Stack grows downward. */
7896 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
7898 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc);
7899 set_gdbarch_decr_pc_after_break (gdbarch, 1);
7900 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
7902 set_gdbarch_frame_args_skip (gdbarch, 8);
7904 set_gdbarch_print_insn (gdbarch, i386_print_insn);
7906 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
7908 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
7910 /* Add the i386 register groups. */
7911 i386_add_reggroups (gdbarch);
7912 tdep->register_reggroup_p = i386_register_reggroup_p;
7914 /* Helper for function argument information. */
7915 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
7917 /* Hook the function epilogue frame unwinder. This unwinder is
7918 appended to the list first, so that it supercedes the DWARF
7919 unwinder in function epilogues (where the DWARF unwinder
7920 currently fails). */
7921 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
7923 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7924 to the list before the prologue-based unwinders, so that DWARF
7925 CFI info will be used if it is available. */
7926 dwarf2_append_unwinders (gdbarch);
7928 frame_base_set_default (gdbarch, &i386_frame_base);
7930 /* Pseudo registers may be changed by amd64_init_abi. */
7931 set_gdbarch_pseudo_register_read_value (gdbarch,
7932 i386_pseudo_register_read_value);
7933 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
7935 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
7936 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
7938 /* Override the normal target description method to make the AVX
7939 upper halves anonymous. */
7940 set_gdbarch_register_name (gdbarch, i386_register_name);
7942 /* Even though the default ABI only includes general-purpose registers,
7943 floating-point registers and the SSE registers, we have to leave a
7944 gap for the upper AVX registers and the MPX registers. */
7945 set_gdbarch_num_regs (gdbarch, I386_MPX_NUM_REGS);
7947 /* Get the x86 target description from INFO. */
7948 tdesc = info.target_desc;
7949 if (! tdesc_has_registers (tdesc))
7951 tdep->tdesc = tdesc;
7953 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
7954 tdep->register_names = i386_register_names;
7956 /* No upper YMM registers. */
7957 tdep->ymmh_register_names = NULL;
7958 tdep->ymm0h_regnum = -1;
7960 tdep->num_byte_regs = 8;
7961 tdep->num_word_regs = 8;
7962 tdep->num_dword_regs = 0;
7963 tdep->num_mmx_regs = 8;
7964 tdep->num_ymm_regs = 0;
7966 /* No MPX registers. */
7967 tdep->bnd0r_regnum = -1;
7968 tdep->bndcfgu_regnum = -1;
7970 tdesc_data = tdesc_data_alloc ();
7972 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
7974 set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address);
7976 /* Hook in ABI-specific overrides, if they have been registered. */
7977 info.tdep_info = (void *) tdesc_data;
7978 gdbarch_init_osabi (info, gdbarch);
7980 if (!i386_validate_tdesc_p (tdep, tdesc_data))
7982 tdesc_data_cleanup (tdesc_data);
7984 gdbarch_free (gdbarch);
7988 num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0);
7990 /* Wire in pseudo registers. Number of pseudo registers may be
7992 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
7993 + tdep->num_word_regs
7994 + tdep->num_dword_regs
7995 + tdep->num_mmx_regs
7996 + tdep->num_ymm_regs
7999 /* Target description may be changed. */
8000 tdesc = tdep->tdesc;
8002 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
8004 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8005 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
8007 /* Make %al the first pseudo-register. */
8008 tdep->al_regnum = gdbarch_num_regs (gdbarch);
8009 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
8011 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
8012 if (tdep->num_dword_regs)
8014 /* Support dword pseudo-register if it hasn't been disabled. */
8015 tdep->eax_regnum = ymm0_regnum;
8016 ymm0_regnum += tdep->num_dword_regs;
8019 tdep->eax_regnum = -1;
8021 mm0_regnum = ymm0_regnum;
8022 if (tdep->num_ymm_regs)
8024 /* Support YMM pseudo-register if it is available. */
8025 tdep->ymm0_regnum = ymm0_regnum;
8026 mm0_regnum += tdep->num_ymm_regs;
8029 tdep->ymm0_regnum = -1;
8031 bnd0_regnum = mm0_regnum;
8032 if (tdep->num_mmx_regs != 0)
8034 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8035 tdep->mm0_regnum = mm0_regnum;
8036 bnd0_regnum += tdep->num_mmx_regs;
8039 tdep->mm0_regnum = -1;
8041 if (tdep->bnd0r_regnum > 0)
8042 tdep->bnd0_regnum = bnd0_regnum;
8044 tdep-> bnd0_regnum = -1;
8046 /* Hook in the legacy prologue-based unwinders last (fallback). */
8047 frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind);
8048 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
8049 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
8051 /* If we have a register mapping, enable the generic core file
8052 support, unless it has already been enabled. */
8053 if (tdep->gregset_reg_offset
8054 && !gdbarch_regset_from_core_section_p (gdbarch))
8055 set_gdbarch_regset_from_core_section (gdbarch,
8056 i386_regset_from_core_section);
8058 set_gdbarch_skip_permanent_breakpoint (gdbarch,
8059 i386_skip_permanent_breakpoint);
8061 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
8062 i386_fast_tracepoint_valid_at);
8067 static enum gdb_osabi
8068 i386_coff_osabi_sniffer (bfd *abfd)
8070 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
8071 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
8072 return GDB_OSABI_GO32;
8074 return GDB_OSABI_UNKNOWN;
8078 /* Provide a prototype to silence -Wmissing-prototypes. */
8079 void _initialize_i386_tdep (void);
8082 _initialize_i386_tdep (void)
8084 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
8086 /* Add the variable that controls the disassembly flavor. */
8087 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
8088 &disassembly_flavor, _("\
8089 Set the disassembly flavor."), _("\
8090 Show the disassembly flavor."), _("\
8091 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
8093 NULL, /* FIXME: i18n: */
8094 &setlist, &showlist);
8096 /* Add the variable that controls the convention for returning
8098 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
8099 &struct_convention, _("\
8100 Set the convention for returning small structs."), _("\
8101 Show the convention for returning small structs."), _("\
8102 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
8105 NULL, /* FIXME: i18n: */
8106 &setlist, &showlist);
8108 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
8109 i386_coff_osabi_sniffer);
8111 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
8112 i386_svr4_init_abi);
8113 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
8114 i386_go32_init_abi);
8116 /* Initialize the i386-specific register groups. */
8117 i386_init_reggroups ();
8119 /* Initialize the standard target descriptions. */
8120 initialize_tdesc_i386 ();
8121 initialize_tdesc_i386_mmx ();
8122 initialize_tdesc_i386_avx ();
8123 initialize_tdesc_i386_mpx ();
8125 /* Tell remote stub that we support XML target description. */
8126 register_remote_support_xml ("i386");