1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
38 #include "reggroups.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "x86-xstate.h"
52 #include "record-full.h"
53 #include "features/i386/i386.c"
54 #include "features/i386/i386-avx.c"
55 #include "features/i386/i386-mpx.c"
56 #include "features/i386/i386-avx-mpx.c"
57 #include "features/i386/i386-avx512.c"
58 #include "features/i386/i386-mmx.c"
63 #include "stap-probe.h"
64 #include "user-regs.h"
65 #include "cli/cli-utils.h"
66 #include "expression.h"
67 #include "parser-defs.h"
73 static const char *i386_register_names[] =
75 "eax", "ecx", "edx", "ebx",
76 "esp", "ebp", "esi", "edi",
77 "eip", "eflags", "cs", "ss",
78 "ds", "es", "fs", "gs",
79 "st0", "st1", "st2", "st3",
80 "st4", "st5", "st6", "st7",
81 "fctrl", "fstat", "ftag", "fiseg",
82 "fioff", "foseg", "fooff", "fop",
83 "xmm0", "xmm1", "xmm2", "xmm3",
84 "xmm4", "xmm5", "xmm6", "xmm7",
88 static const char *i386_zmm_names[] =
90 "zmm0", "zmm1", "zmm2", "zmm3",
91 "zmm4", "zmm5", "zmm6", "zmm7"
94 static const char *i386_zmmh_names[] =
96 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
97 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
100 static const char *i386_k_names[] =
102 "k0", "k1", "k2", "k3",
103 "k4", "k5", "k6", "k7"
106 static const char *i386_ymm_names[] =
108 "ymm0", "ymm1", "ymm2", "ymm3",
109 "ymm4", "ymm5", "ymm6", "ymm7",
112 static const char *i386_ymmh_names[] =
114 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
115 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
118 static const char *i386_mpx_names[] =
120 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
123 /* Register names for MPX pseudo-registers. */
125 static const char *i386_bnd_names[] =
127 "bnd0", "bnd1", "bnd2", "bnd3"
130 /* Register names for MMX pseudo-registers. */
132 static const char *i386_mmx_names[] =
134 "mm0", "mm1", "mm2", "mm3",
135 "mm4", "mm5", "mm6", "mm7"
138 /* Register names for byte pseudo-registers. */
140 static const char *i386_byte_names[] =
142 "al", "cl", "dl", "bl",
143 "ah", "ch", "dh", "bh"
146 /* Register names for word pseudo-registers. */
148 static const char *i386_word_names[] =
150 "ax", "cx", "dx", "bx",
154 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
155 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
156 we have 16 upper ZMM regs that have to be handled differently. */
158 const int num_lower_zmm_regs = 16;
163 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
165 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
166 int mm0_regnum = tdep->mm0_regnum;
171 regnum -= mm0_regnum;
172 return regnum >= 0 && regnum < tdep->num_mmx_regs;
178 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
180 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
182 regnum -= tdep->al_regnum;
183 return regnum >= 0 && regnum < tdep->num_byte_regs;
189 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
191 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
193 regnum -= tdep->ax_regnum;
194 return regnum >= 0 && regnum < tdep->num_word_regs;
197 /* Dword register? */
200 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
202 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
203 int eax_regnum = tdep->eax_regnum;
208 regnum -= eax_regnum;
209 return regnum >= 0 && regnum < tdep->num_dword_regs;
212 /* AVX512 register? */
215 i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum)
217 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
218 int zmm0h_regnum = tdep->zmm0h_regnum;
220 if (zmm0h_regnum < 0)
223 regnum -= zmm0h_regnum;
224 return regnum >= 0 && regnum < tdep->num_zmm_regs;
228 i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum)
230 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
231 int zmm0_regnum = tdep->zmm0_regnum;
236 regnum -= zmm0_regnum;
237 return regnum >= 0 && regnum < tdep->num_zmm_regs;
241 i386_k_regnum_p (struct gdbarch *gdbarch, int regnum)
243 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
244 int k0_regnum = tdep->k0_regnum;
250 return regnum >= 0 && regnum < I387_NUM_K_REGS;
254 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
256 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
257 int ymm0h_regnum = tdep->ymm0h_regnum;
259 if (ymm0h_regnum < 0)
262 regnum -= ymm0h_regnum;
263 return regnum >= 0 && regnum < tdep->num_ymm_regs;
269 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
271 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
272 int ymm0_regnum = tdep->ymm0_regnum;
277 regnum -= ymm0_regnum;
278 return regnum >= 0 && regnum < tdep->num_ymm_regs;
282 i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
284 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
285 int ymm16h_regnum = tdep->ymm16h_regnum;
287 if (ymm16h_regnum < 0)
290 regnum -= ymm16h_regnum;
291 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
295 i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
297 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
298 int ymm16_regnum = tdep->ymm16_regnum;
300 if (ymm16_regnum < 0)
303 regnum -= ymm16_regnum;
304 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
310 i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum)
312 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
313 int bnd0_regnum = tdep->bnd0_regnum;
318 regnum -= bnd0_regnum;
319 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
325 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
327 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
328 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
330 if (num_xmm_regs == 0)
333 regnum -= I387_XMM0_REGNUM (tdep);
334 return regnum >= 0 && regnum < num_xmm_regs;
337 /* XMM_512 register? */
340 i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
342 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
343 int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep);
345 if (num_xmm_avx512_regs == 0)
348 regnum -= I387_XMM16_REGNUM (tdep);
349 return regnum >= 0 && regnum < num_xmm_avx512_regs;
353 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
355 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
357 if (I387_NUM_XMM_REGS (tdep) == 0)
360 return (regnum == I387_MXCSR_REGNUM (tdep));
366 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
368 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
370 if (I387_ST0_REGNUM (tdep) < 0)
373 return (I387_ST0_REGNUM (tdep) <= regnum
374 && regnum < I387_FCTRL_REGNUM (tdep));
378 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
380 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
382 if (I387_ST0_REGNUM (tdep) < 0)
385 return (I387_FCTRL_REGNUM (tdep) <= regnum
386 && regnum < I387_XMM0_REGNUM (tdep));
389 /* BNDr (raw) register? */
392 i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum)
394 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
396 if (I387_BND0R_REGNUM (tdep) < 0)
399 regnum -= tdep->bnd0r_regnum;
400 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
403 /* BND control register? */
406 i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum)
408 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
410 if (I387_BNDCFGU_REGNUM (tdep) < 0)
413 regnum -= I387_BNDCFGU_REGNUM (tdep);
414 return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS;
417 /* Return the name of register REGNUM, or the empty string if it is
418 an anonymous register. */
421 i386_register_name (struct gdbarch *gdbarch, int regnum)
423 /* Hide the upper YMM registers. */
424 if (i386_ymmh_regnum_p (gdbarch, regnum))
427 /* Hide the upper YMM16-31 registers. */
428 if (i386_ymmh_avx512_regnum_p (gdbarch, regnum))
431 /* Hide the upper ZMM registers. */
432 if (i386_zmmh_regnum_p (gdbarch, regnum))
435 return tdesc_register_name (gdbarch, regnum);
438 /* Return the name of register REGNUM. */
441 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
443 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
444 if (i386_bnd_regnum_p (gdbarch, regnum))
445 return i386_bnd_names[regnum - tdep->bnd0_regnum];
446 if (i386_mmx_regnum_p (gdbarch, regnum))
447 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
448 else if (i386_ymm_regnum_p (gdbarch, regnum))
449 return i386_ymm_names[regnum - tdep->ymm0_regnum];
450 else if (i386_zmm_regnum_p (gdbarch, regnum))
451 return i386_zmm_names[regnum - tdep->zmm0_regnum];
452 else if (i386_byte_regnum_p (gdbarch, regnum))
453 return i386_byte_names[regnum - tdep->al_regnum];
454 else if (i386_word_regnum_p (gdbarch, regnum))
455 return i386_word_names[regnum - tdep->ax_regnum];
457 internal_error (__FILE__, __LINE__, _("invalid regnum"));
460 /* Convert a dbx register number REG to the appropriate register
461 number used by GDB. */
464 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
466 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
468 /* This implements what GCC calls the "default" register map
469 (dbx_register_map[]). */
471 if (reg >= 0 && reg <= 7)
473 /* General-purpose registers. The debug info calls %ebp
474 register 4, and %esp register 5. */
481 else if (reg >= 12 && reg <= 19)
483 /* Floating-point registers. */
484 return reg - 12 + I387_ST0_REGNUM (tdep);
486 else if (reg >= 21 && reg <= 28)
489 int ymm0_regnum = tdep->ymm0_regnum;
492 && i386_xmm_regnum_p (gdbarch, reg))
493 return reg - 21 + ymm0_regnum;
495 return reg - 21 + I387_XMM0_REGNUM (tdep);
497 else if (reg >= 29 && reg <= 36)
500 return reg - 29 + I387_MM0_REGNUM (tdep);
503 /* This will hopefully provoke a warning. */
504 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
507 /* Convert SVR4 DWARF register number REG to the appropriate register number
511 i386_svr4_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
513 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
515 /* This implements the GCC register map that tries to be compatible
516 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
518 /* The SVR4 register numbering includes %eip and %eflags, and
519 numbers the floating point registers differently. */
520 if (reg >= 0 && reg <= 9)
522 /* General-purpose registers. */
525 else if (reg >= 11 && reg <= 18)
527 /* Floating-point registers. */
528 return reg - 11 + I387_ST0_REGNUM (tdep);
530 else if (reg >= 21 && reg <= 36)
532 /* The SSE and MMX registers have the same numbers as with dbx. */
533 return i386_dbx_reg_to_regnum (gdbarch, reg);
538 case 37: return I387_FCTRL_REGNUM (tdep);
539 case 38: return I387_FSTAT_REGNUM (tdep);
540 case 39: return I387_MXCSR_REGNUM (tdep);
541 case 40: return I386_ES_REGNUM;
542 case 41: return I386_CS_REGNUM;
543 case 42: return I386_SS_REGNUM;
544 case 43: return I386_DS_REGNUM;
545 case 44: return I386_FS_REGNUM;
546 case 45: return I386_GS_REGNUM;
552 /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return
553 num_regs + num_pseudo_regs for other debug formats. */
556 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
558 int regnum = i386_svr4_dwarf_reg_to_regnum (gdbarch, reg);
561 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
567 /* This is the variable that is set with "set disassembly-flavor", and
568 its legitimate values. */
569 static const char att_flavor[] = "att";
570 static const char intel_flavor[] = "intel";
571 static const char *const valid_flavors[] =
577 static const char *disassembly_flavor = att_flavor;
580 /* Use the program counter to determine the contents and size of a
581 breakpoint instruction. Return a pointer to a string of bytes that
582 encode a breakpoint instruction, store the length of the string in
583 *LEN and optionally adjust *PC to point to the correct memory
584 location for inserting the breakpoint.
586 On the i386 we have a single breakpoint that fits in a single byte
587 and can be inserted anywhere.
589 This function is 64-bit safe. */
591 static const gdb_byte break_insn[] = { 0xcc }; /* int 3 */
593 GDBARCH_BREAKPOINT_MANIPULATION (i386, break_insn)
595 /* Displaced instruction handling. */
597 /* Skip the legacy instruction prefixes in INSN.
598 Not all prefixes are valid for any particular insn
599 but we needn't care, the insn will fault if it's invalid.
600 The result is a pointer to the first opcode byte,
601 or NULL if we run off the end of the buffer. */
604 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
606 gdb_byte *end = insn + max_len;
612 case DATA_PREFIX_OPCODE:
613 case ADDR_PREFIX_OPCODE:
614 case CS_PREFIX_OPCODE:
615 case DS_PREFIX_OPCODE:
616 case ES_PREFIX_OPCODE:
617 case FS_PREFIX_OPCODE:
618 case GS_PREFIX_OPCODE:
619 case SS_PREFIX_OPCODE:
620 case LOCK_PREFIX_OPCODE:
621 case REPE_PREFIX_OPCODE:
622 case REPNE_PREFIX_OPCODE:
634 i386_absolute_jmp_p (const gdb_byte *insn)
636 /* jmp far (absolute address in operand). */
642 /* jump near, absolute indirect (/4). */
643 if ((insn[1] & 0x38) == 0x20)
646 /* jump far, absolute indirect (/5). */
647 if ((insn[1] & 0x38) == 0x28)
654 /* Return non-zero if INSN is a jump, zero otherwise. */
657 i386_jmp_p (const gdb_byte *insn)
659 /* jump short, relative. */
663 /* jump near, relative. */
667 return i386_absolute_jmp_p (insn);
671 i386_absolute_call_p (const gdb_byte *insn)
673 /* call far, absolute. */
679 /* Call near, absolute indirect (/2). */
680 if ((insn[1] & 0x38) == 0x10)
683 /* Call far, absolute indirect (/3). */
684 if ((insn[1] & 0x38) == 0x18)
692 i386_ret_p (const gdb_byte *insn)
696 case 0xc2: /* ret near, pop N bytes. */
697 case 0xc3: /* ret near */
698 case 0xca: /* ret far, pop N bytes. */
699 case 0xcb: /* ret far */
700 case 0xcf: /* iret */
709 i386_call_p (const gdb_byte *insn)
711 if (i386_absolute_call_p (insn))
714 /* call near, relative. */
721 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
722 length in bytes. Otherwise, return zero. */
725 i386_syscall_p (const gdb_byte *insn, int *lengthp)
727 /* Is it 'int $0x80'? */
728 if ((insn[0] == 0xcd && insn[1] == 0x80)
729 /* Or is it 'sysenter'? */
730 || (insn[0] == 0x0f && insn[1] == 0x34)
731 /* Or is it 'syscall'? */
732 || (insn[0] == 0x0f && insn[1] == 0x05))
741 /* The gdbarch insn_is_call method. */
744 i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
746 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
748 read_code (addr, buf, I386_MAX_INSN_LEN);
749 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
751 return i386_call_p (insn);
754 /* The gdbarch insn_is_ret method. */
757 i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
759 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
761 read_code (addr, buf, I386_MAX_INSN_LEN);
762 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
764 return i386_ret_p (insn);
767 /* The gdbarch insn_is_jump method. */
770 i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
772 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
774 read_code (addr, buf, I386_MAX_INSN_LEN);
775 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
777 return i386_jmp_p (insn);
780 /* Some kernels may run one past a syscall insn, so we have to cope.
781 Otherwise this is just simple_displaced_step_copy_insn. */
783 struct displaced_step_closure *
784 i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
785 CORE_ADDR from, CORE_ADDR to,
786 struct regcache *regs)
788 size_t len = gdbarch_max_insn_length (gdbarch);
789 gdb_byte *buf = (gdb_byte *) xmalloc (len);
791 read_memory (from, buf, len);
793 /* GDB may get control back after the insn after the syscall.
794 Presumably this is a kernel bug.
795 If this is a syscall, make sure there's a nop afterwards. */
800 insn = i386_skip_prefixes (buf, len);
801 if (insn != NULL && i386_syscall_p (insn, &syscall_length))
802 insn[syscall_length] = NOP_OPCODE;
805 write_memory (to, buf, len);
809 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
810 paddress (gdbarch, from), paddress (gdbarch, to));
811 displaced_step_dump_bytes (gdb_stdlog, buf, len);
814 return (struct displaced_step_closure *) buf;
817 /* Fix up the state of registers and memory after having single-stepped
818 a displaced instruction. */
821 i386_displaced_step_fixup (struct gdbarch *gdbarch,
822 struct displaced_step_closure *closure,
823 CORE_ADDR from, CORE_ADDR to,
824 struct regcache *regs)
826 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
828 /* The offset we applied to the instruction's address.
829 This could well be negative (when viewed as a signed 32-bit
830 value), but ULONGEST won't reflect that, so take care when
832 ULONGEST insn_offset = to - from;
834 /* Since we use simple_displaced_step_copy_insn, our closure is a
835 copy of the instruction. */
836 gdb_byte *insn = (gdb_byte *) closure;
837 /* The start of the insn, needed in case we see some prefixes. */
838 gdb_byte *insn_start = insn;
841 fprintf_unfiltered (gdb_stdlog,
842 "displaced: fixup (%s, %s), "
843 "insn = 0x%02x 0x%02x ...\n",
844 paddress (gdbarch, from), paddress (gdbarch, to),
847 /* The list of issues to contend with here is taken from
848 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
849 Yay for Free Software! */
851 /* Relocate the %eip, if necessary. */
853 /* The instruction recognizers we use assume any leading prefixes
854 have been skipped. */
856 /* This is the size of the buffer in closure. */
857 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
858 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
859 /* If there are too many prefixes, just ignore the insn.
860 It will fault when run. */
865 /* Except in the case of absolute or indirect jump or call
866 instructions, or a return instruction, the new eip is relative to
867 the displaced instruction; make it relative. Well, signal
868 handler returns don't need relocation either, but we use the
869 value of %eip to recognize those; see below. */
870 if (! i386_absolute_jmp_p (insn)
871 && ! i386_absolute_call_p (insn)
872 && ! i386_ret_p (insn))
877 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
879 /* A signal trampoline system call changes the %eip, resuming
880 execution of the main program after the signal handler has
881 returned. That makes them like 'return' instructions; we
882 shouldn't relocate %eip.
884 But most system calls don't, and we do need to relocate %eip.
886 Our heuristic for distinguishing these cases: if stepping
887 over the system call instruction left control directly after
888 the instruction, the we relocate --- control almost certainly
889 doesn't belong in the displaced copy. Otherwise, we assume
890 the instruction has put control where it belongs, and leave
891 it unrelocated. Goodness help us if there are PC-relative
893 if (i386_syscall_p (insn, &insn_len)
894 && orig_eip != to + (insn - insn_start) + insn_len
895 /* GDB can get control back after the insn after the syscall.
896 Presumably this is a kernel bug.
897 i386_displaced_step_copy_insn ensures its a nop,
898 we add one to the length for it. */
899 && orig_eip != to + (insn - insn_start) + insn_len + 1)
902 fprintf_unfiltered (gdb_stdlog,
903 "displaced: syscall changed %%eip; "
908 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
910 /* If we just stepped over a breakpoint insn, we don't backup
911 the pc on purpose; this is to match behaviour without
914 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
917 fprintf_unfiltered (gdb_stdlog,
919 "relocated %%eip from %s to %s\n",
920 paddress (gdbarch, orig_eip),
921 paddress (gdbarch, eip));
925 /* If the instruction was PUSHFL, then the TF bit will be set in the
926 pushed value, and should be cleared. We'll leave this for later,
927 since GDB already messes up the TF flag when stepping over a
930 /* If the instruction was a call, the return address now atop the
931 stack is the address following the copied instruction. We need
932 to make it the address following the original instruction. */
933 if (i386_call_p (insn))
937 const ULONGEST retaddr_len = 4;
939 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
940 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
941 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
942 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
945 fprintf_unfiltered (gdb_stdlog,
946 "displaced: relocated return addr at %s to %s\n",
947 paddress (gdbarch, esp),
948 paddress (gdbarch, retaddr));
953 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
955 target_write_memory (*to, buf, len);
960 i386_relocate_instruction (struct gdbarch *gdbarch,
961 CORE_ADDR *to, CORE_ADDR oldloc)
963 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
964 gdb_byte buf[I386_MAX_INSN_LEN];
965 int offset = 0, rel32, newrel;
967 gdb_byte *insn = buf;
969 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
971 insn_length = gdb_buffered_insn_length (gdbarch, insn,
972 I386_MAX_INSN_LEN, oldloc);
974 /* Get past the prefixes. */
975 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
977 /* Adjust calls with 32-bit relative addresses as push/jump, with
978 the address pushed being the location where the original call in
979 the user program would return to. */
982 gdb_byte push_buf[16];
983 unsigned int ret_addr;
985 /* Where "ret" in the original code will return to. */
986 ret_addr = oldloc + insn_length;
987 push_buf[0] = 0x68; /* pushq $... */
988 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
990 append_insns (to, 5, push_buf);
992 /* Convert the relative call to a relative jump. */
995 /* Adjust the destination offset. */
996 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
997 newrel = (oldloc - *to) + rel32;
998 store_signed_integer (insn + 1, 4, byte_order, newrel);
1000 if (debug_displaced)
1001 fprintf_unfiltered (gdb_stdlog,
1002 "Adjusted insn rel32=%s at %s to"
1003 " rel32=%s at %s\n",
1004 hex_string (rel32), paddress (gdbarch, oldloc),
1005 hex_string (newrel), paddress (gdbarch, *to));
1007 /* Write the adjusted jump into its displaced location. */
1008 append_insns (to, 5, insn);
1012 /* Adjust jumps with 32-bit relative addresses. Calls are already
1014 if (insn[0] == 0xe9)
1016 /* Adjust conditional jumps. */
1017 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1022 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1023 newrel = (oldloc - *to) + rel32;
1024 store_signed_integer (insn + offset, 4, byte_order, newrel);
1025 if (debug_displaced)
1026 fprintf_unfiltered (gdb_stdlog,
1027 "Adjusted insn rel32=%s at %s to"
1028 " rel32=%s at %s\n",
1029 hex_string (rel32), paddress (gdbarch, oldloc),
1030 hex_string (newrel), paddress (gdbarch, *to));
1033 /* Write the adjusted instructions into their displaced
1035 append_insns (to, insn_length, buf);
1039 #ifdef I386_REGNO_TO_SYMMETRY
1040 #error "The Sequent Symmetry is no longer supported."
1043 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1044 and %esp "belong" to the calling function. Therefore these
1045 registers should be saved if they're going to be modified. */
1047 /* The maximum number of saved registers. This should include all
1048 registers mentioned above, and %eip. */
1049 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1051 struct i386_frame_cache
1059 /* Saved registers. */
1060 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
1065 /* Stack space reserved for local variables. */
1069 /* Allocate and initialize a frame cache. */
1071 static struct i386_frame_cache *
1072 i386_alloc_frame_cache (void)
1074 struct i386_frame_cache *cache;
1077 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
1082 cache->sp_offset = -4;
1085 /* Saved registers. We initialize these to -1 since zero is a valid
1086 offset (that's where %ebp is supposed to be stored). */
1087 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1088 cache->saved_regs[i] = -1;
1089 cache->saved_sp = 0;
1090 cache->saved_sp_reg = -1;
1091 cache->pc_in_eax = 0;
1093 /* Frameless until proven otherwise. */
1099 /* If the instruction at PC is a jump, return the address of its
1100 target. Otherwise, return PC. */
1103 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
1105 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1110 if (target_read_code (pc, &op, 1))
1117 op = read_code_unsigned_integer (pc + 1, 1, byte_order);
1123 /* Relative jump: if data16 == 0, disp32, else disp16. */
1126 delta = read_memory_integer (pc + 2, 2, byte_order);
1128 /* Include the size of the jmp instruction (including the
1134 delta = read_memory_integer (pc + 1, 4, byte_order);
1136 /* Include the size of the jmp instruction. */
1141 /* Relative jump, disp8 (ignore data16). */
1142 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
1144 delta += data16 + 2;
1151 /* Check whether PC points at a prologue for a function returning a
1152 structure or union. If so, it updates CACHE and returns the
1153 address of the first instruction after the code sequence that
1154 removes the "hidden" argument from the stack or CURRENT_PC,
1155 whichever is smaller. Otherwise, return PC. */
1158 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
1159 struct i386_frame_cache *cache)
1161 /* Functions that return a structure or union start with:
1164 xchgl %eax, (%esp) 0x87 0x04 0x24
1165 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1167 (the System V compiler puts out the second `xchg' instruction,
1168 and the assembler doesn't try to optimize it, so the 'sib' form
1169 gets generated). This sequence is used to get the address of the
1170 return buffer for a function that returns a structure. */
1171 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
1172 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
1176 if (current_pc <= pc)
1179 if (target_read_code (pc, &op, 1))
1182 if (op != 0x58) /* popl %eax */
1185 if (target_read_code (pc + 1, buf, 4))
1188 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
1191 if (current_pc == pc)
1193 cache->sp_offset += 4;
1197 if (current_pc == pc + 1)
1199 cache->pc_in_eax = 1;
1203 if (buf[1] == proto1[1])
1210 i386_skip_probe (CORE_ADDR pc)
1212 /* A function may start with
1226 if (target_read_code (pc, &op, 1))
1229 if (op == 0x68 || op == 0x6a)
1233 /* Skip past the `pushl' instruction; it has either a one-byte or a
1234 four-byte operand, depending on the opcode. */
1240 /* Read the following 8 bytes, which should be `call _probe' (6
1241 bytes) followed by `addl $4,%esp' (2 bytes). */
1242 read_memory (pc + delta, buf, sizeof (buf));
1243 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
1244 pc += delta + sizeof (buf);
1250 /* GCC 4.1 and later, can put code in the prologue to realign the
1251 stack pointer. Check whether PC points to such code, and update
1252 CACHE accordingly. Return the first instruction after the code
1253 sequence or CURRENT_PC, whichever is smaller. If we don't
1254 recognize the code, return PC. */
1257 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1258 struct i386_frame_cache *cache)
1260 /* There are 2 code sequences to re-align stack before the frame
1263 1. Use a caller-saved saved register:
1269 2. Use a callee-saved saved register:
1276 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1278 0x83 0xe4 0xf0 andl $-16, %esp
1279 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1284 int offset, offset_and;
1285 static int regnums[8] = {
1286 I386_EAX_REGNUM, /* %eax */
1287 I386_ECX_REGNUM, /* %ecx */
1288 I386_EDX_REGNUM, /* %edx */
1289 I386_EBX_REGNUM, /* %ebx */
1290 I386_ESP_REGNUM, /* %esp */
1291 I386_EBP_REGNUM, /* %ebp */
1292 I386_ESI_REGNUM, /* %esi */
1293 I386_EDI_REGNUM /* %edi */
1296 if (target_read_code (pc, buf, sizeof buf))
1299 /* Check caller-saved saved register. The first instruction has
1300 to be "leal 4(%esp), %reg". */
1301 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1303 /* MOD must be binary 10 and R/M must be binary 100. */
1304 if ((buf[1] & 0xc7) != 0x44)
1307 /* REG has register number. */
1308 reg = (buf[1] >> 3) & 7;
1313 /* Check callee-saved saved register. The first instruction
1314 has to be "pushl %reg". */
1315 if ((buf[0] & 0xf8) != 0x50)
1321 /* The next instruction has to be "leal 8(%esp), %reg". */
1322 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1325 /* MOD must be binary 10 and R/M must be binary 100. */
1326 if ((buf[2] & 0xc7) != 0x44)
1329 /* REG has register number. Registers in pushl and leal have to
1331 if (reg != ((buf[2] >> 3) & 7))
1337 /* Rigister can't be %esp nor %ebp. */
1338 if (reg == 4 || reg == 5)
1341 /* The next instruction has to be "andl $-XXX, %esp". */
1342 if (buf[offset + 1] != 0xe4
1343 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1346 offset_and = offset;
1347 offset += buf[offset] == 0x81 ? 6 : 3;
1349 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1350 0xfc. REG must be binary 110 and MOD must be binary 01. */
1351 if (buf[offset] != 0xff
1352 || buf[offset + 2] != 0xfc
1353 || (buf[offset + 1] & 0xf8) != 0x70)
1356 /* R/M has register. Registers in leal and pushl have to be the
1358 if (reg != (buf[offset + 1] & 7))
1361 if (current_pc > pc + offset_and)
1362 cache->saved_sp_reg = regnums[reg];
1364 return std::min (pc + offset + 3, current_pc);
1367 /* Maximum instruction length we need to handle. */
1368 #define I386_MAX_MATCHED_INSN_LEN 6
1370 /* Instruction description. */
1374 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
1375 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
1378 /* Return whether instruction at PC matches PATTERN. */
1381 i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern)
1385 if (target_read_code (pc, &op, 1))
1388 if ((op & pattern.mask[0]) == pattern.insn[0])
1390 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1391 int insn_matched = 1;
1394 gdb_assert (pattern.len > 1);
1395 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN);
1397 if (target_read_code (pc + 1, buf, pattern.len - 1))
1400 for (i = 1; i < pattern.len; i++)
1402 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i])
1405 return insn_matched;
1410 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1411 the first instruction description that matches. Otherwise, return
1414 static struct i386_insn *
1415 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns)
1417 struct i386_insn *pattern;
1419 for (pattern = insn_patterns; pattern->len > 0; pattern++)
1421 if (i386_match_pattern (pc, *pattern))
1428 /* Return whether PC points inside a sequence of instructions that
1429 matches INSN_PATTERNS. */
1432 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns)
1434 CORE_ADDR current_pc;
1436 struct i386_insn *insn;
1438 insn = i386_match_insn (pc, insn_patterns);
1443 ix = insn - insn_patterns;
1444 for (i = ix - 1; i >= 0; i--)
1446 current_pc -= insn_patterns[i].len;
1448 if (!i386_match_pattern (current_pc, insn_patterns[i]))
1452 current_pc = pc + insn->len;
1453 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++)
1455 if (!i386_match_pattern (current_pc, *insn))
1458 current_pc += insn->len;
1464 /* Some special instructions that might be migrated by GCC into the
1465 part of the prologue that sets up the new stack frame. Because the
1466 stack frame hasn't been setup yet, no registers have been saved
1467 yet, and only the scratch registers %eax, %ecx and %edx can be
1470 struct i386_insn i386_frame_setup_skip_insns[] =
1472 /* Check for `movb imm8, r' and `movl imm32, r'.
1474 ??? Should we handle 16-bit operand-sizes here? */
1476 /* `movb imm8, %al' and `movb imm8, %ah' */
1477 /* `movb imm8, %cl' and `movb imm8, %ch' */
1478 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1479 /* `movb imm8, %dl' and `movb imm8, %dh' */
1480 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1481 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1482 { 5, { 0xb8 }, { 0xfe } },
1483 /* `movl imm32, %edx' */
1484 { 5, { 0xba }, { 0xff } },
1486 /* Check for `mov imm32, r32'. Note that there is an alternative
1487 encoding for `mov m32, %eax'.
1489 ??? Should we handle SIB adressing here?
1490 ??? Should we handle 16-bit operand-sizes here? */
1492 /* `movl m32, %eax' */
1493 { 5, { 0xa1 }, { 0xff } },
1494 /* `movl m32, %eax' and `mov; m32, %ecx' */
1495 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1496 /* `movl m32, %edx' */
1497 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1499 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1500 Because of the symmetry, there are actually two ways to encode
1501 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1502 opcode bytes 0x31 and 0x33 for `xorl'. */
1504 /* `subl %eax, %eax' */
1505 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1506 /* `subl %ecx, %ecx' */
1507 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1508 /* `subl %edx, %edx' */
1509 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1510 /* `xorl %eax, %eax' */
1511 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1512 /* `xorl %ecx, %ecx' */
1513 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1514 /* `xorl %edx, %edx' */
1515 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1520 /* Check whether PC points to a no-op instruction. */
1522 i386_skip_noop (CORE_ADDR pc)
1527 if (target_read_code (pc, &op, 1))
1533 /* Ignore `nop' instruction. */
1537 if (target_read_code (pc, &op, 1))
1541 /* Ignore no-op instruction `mov %edi, %edi'.
1542 Microsoft system dlls often start with
1543 a `mov %edi,%edi' instruction.
1544 The 5 bytes before the function start are
1545 filled with `nop' instructions.
1546 This pattern can be used for hot-patching:
1547 The `mov %edi, %edi' instruction can be replaced by a
1548 near jump to the location of the 5 `nop' instructions
1549 which can be replaced by a 32-bit jump to anywhere
1550 in the 32-bit address space. */
1552 else if (op == 0x8b)
1554 if (target_read_code (pc + 1, &op, 1))
1560 if (target_read_code (pc, &op, 1))
1570 /* Check whether PC points at a code that sets up a new stack frame.
1571 If so, it updates CACHE and returns the address of the first
1572 instruction after the sequence that sets up the frame or LIMIT,
1573 whichever is smaller. If we don't recognize the code, return PC. */
1576 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1577 CORE_ADDR pc, CORE_ADDR limit,
1578 struct i386_frame_cache *cache)
1580 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1581 struct i386_insn *insn;
1588 if (target_read_code (pc, &op, 1))
1591 if (op == 0x55) /* pushl %ebp */
1593 /* Take into account that we've executed the `pushl %ebp' that
1594 starts this instruction sequence. */
1595 cache->saved_regs[I386_EBP_REGNUM] = 0;
1596 cache->sp_offset += 4;
1599 /* If that's all, return now. */
1603 /* Check for some special instructions that might be migrated by
1604 GCC into the prologue and skip them. At this point in the
1605 prologue, code should only touch the scratch registers %eax,
1606 %ecx and %edx, so while the number of posibilities is sheer,
1609 Make sure we only skip these instructions if we later see the
1610 `movl %esp, %ebp' that actually sets up the frame. */
1611 while (pc + skip < limit)
1613 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1620 /* If that's all, return now. */
1621 if (limit <= pc + skip)
1624 if (target_read_code (pc + skip, &op, 1))
1627 /* The i386 prologue looks like
1633 and a different prologue can be generated for atom.
1637 lea -0x10(%esp),%esp
1639 We handle both of them here. */
1643 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1645 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1651 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1656 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1657 if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order)
1666 /* OK, we actually have a frame. We just don't know how large
1667 it is yet. Set its size to zero. We'll adjust it if
1668 necessary. We also now commit to skipping the special
1669 instructions mentioned before. */
1672 /* If that's all, return now. */
1676 /* Check for stack adjustment
1682 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1683 reg, so we don't have to worry about a data16 prefix. */
1684 if (target_read_code (pc, &op, 1))
1688 /* `subl' with 8-bit immediate. */
1689 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1690 /* Some instruction starting with 0x83 other than `subl'. */
1693 /* `subl' with signed 8-bit immediate (though it wouldn't
1694 make sense to be negative). */
1695 cache->locals = read_code_integer (pc + 2, 1, byte_order);
1698 else if (op == 0x81)
1700 /* Maybe it is `subl' with a 32-bit immediate. */
1701 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1702 /* Some instruction starting with 0x81 other than `subl'. */
1705 /* It is `subl' with a 32-bit immediate. */
1706 cache->locals = read_code_integer (pc + 2, 4, byte_order);
1709 else if (op == 0x8d)
1711 /* The ModR/M byte is 0x64. */
1712 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64)
1714 /* 'lea' with 8-bit displacement. */
1715 cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order);
1720 /* Some instruction other than `subl' nor 'lea'. */
1724 else if (op == 0xc8) /* enter */
1726 cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order);
1733 /* Check whether PC points at code that saves registers on the stack.
1734 If so, it updates CACHE and returns the address of the first
1735 instruction after the register saves or CURRENT_PC, whichever is
1736 smaller. Otherwise, return PC. */
1739 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1740 struct i386_frame_cache *cache)
1742 CORE_ADDR offset = 0;
1746 if (cache->locals > 0)
1747 offset -= cache->locals;
1748 for (i = 0; i < 8 && pc < current_pc; i++)
1750 if (target_read_code (pc, &op, 1))
1752 if (op < 0x50 || op > 0x57)
1756 cache->saved_regs[op - 0x50] = offset;
1757 cache->sp_offset += 4;
1764 /* Do a full analysis of the prologue at PC and update CACHE
1765 accordingly. Bail out early if CURRENT_PC is reached. Return the
1766 address where the analysis stopped.
1768 We handle these cases:
1770 The startup sequence can be at the start of the function, or the
1771 function can start with a branch to startup code at the end.
1773 %ebp can be set up with either the 'enter' instruction, or "pushl
1774 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1775 once used in the System V compiler).
1777 Local space is allocated just below the saved %ebp by either the
1778 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1779 16-bit unsigned argument for space to allocate, and the 'addl'
1780 instruction could have either a signed byte, or 32-bit immediate.
1782 Next, the registers used by this function are pushed. With the
1783 System V compiler they will always be in the order: %edi, %esi,
1784 %ebx (and sometimes a harmless bug causes it to also save but not
1785 restore %eax); however, the code below is willing to see the pushes
1786 in any order, and will handle up to 8 of them.
1788 If the setup sequence is at the end of the function, then the next
1789 instruction will be a branch back to the start. */
1792 i386_analyze_prologue (struct gdbarch *gdbarch,
1793 CORE_ADDR pc, CORE_ADDR current_pc,
1794 struct i386_frame_cache *cache)
1796 pc = i386_skip_noop (pc);
1797 pc = i386_follow_jump (gdbarch, pc);
1798 pc = i386_analyze_struct_return (pc, current_pc, cache);
1799 pc = i386_skip_probe (pc);
1800 pc = i386_analyze_stack_align (pc, current_pc, cache);
1801 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1802 return i386_analyze_register_saves (pc, current_pc, cache);
1805 /* Return PC of first real instruction. */
1808 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1810 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1812 static gdb_byte pic_pat[6] =
1814 0xe8, 0, 0, 0, 0, /* call 0x0 */
1815 0x5b, /* popl %ebx */
1817 struct i386_frame_cache cache;
1821 CORE_ADDR func_addr;
1823 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
1825 CORE_ADDR post_prologue_pc
1826 = skip_prologue_using_sal (gdbarch, func_addr);
1827 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
1829 /* Clang always emits a line note before the prologue and another
1830 one after. We trust clang to emit usable line notes. */
1831 if (post_prologue_pc
1833 && COMPUNIT_PRODUCER (cust) != NULL
1834 && startswith (COMPUNIT_PRODUCER (cust), "clang ")))
1835 return std::max (start_pc, post_prologue_pc);
1839 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1840 if (cache.locals < 0)
1843 /* Found valid frame setup. */
1845 /* The native cc on SVR4 in -K PIC mode inserts the following code
1846 to get the address of the global offset table (GOT) into register
1851 movl %ebx,x(%ebp) (optional)
1854 This code is with the rest of the prologue (at the end of the
1855 function), so we have to skip it to get to the first real
1856 instruction at the start of the function. */
1858 for (i = 0; i < 6; i++)
1860 if (target_read_code (pc + i, &op, 1))
1863 if (pic_pat[i] != op)
1870 if (target_read_code (pc + delta, &op, 1))
1873 if (op == 0x89) /* movl %ebx, x(%ebp) */
1875 op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order);
1877 if (op == 0x5d) /* One byte offset from %ebp. */
1879 else if (op == 0x9d) /* Four byte offset from %ebp. */
1881 else /* Unexpected instruction. */
1884 if (target_read_code (pc + delta, &op, 1))
1889 if (delta > 0 && op == 0x81
1890 && read_code_unsigned_integer (pc + delta + 1, 1, byte_order)
1897 /* If the function starts with a branch (to startup code at the end)
1898 the last instruction should bring us back to the first
1899 instruction of the real code. */
1900 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1901 pc = i386_follow_jump (gdbarch, pc);
1906 /* Check that the code pointed to by PC corresponds to a call to
1907 __main, skip it if so. Return PC otherwise. */
1910 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1912 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1915 if (target_read_code (pc, &op, 1))
1921 if (target_read_code (pc + 1, buf, sizeof buf) == 0)
1923 /* Make sure address is computed correctly as a 32bit
1924 integer even if CORE_ADDR is 64 bit wide. */
1925 struct bound_minimal_symbol s;
1926 CORE_ADDR call_dest;
1928 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1929 call_dest = call_dest & 0xffffffffU;
1930 s = lookup_minimal_symbol_by_pc (call_dest);
1931 if (s.minsym != NULL
1932 && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL
1933 && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0)
1941 /* This function is 64-bit safe. */
1944 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1948 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1949 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1953 /* Normal frames. */
1956 i386_frame_cache_1 (struct frame_info *this_frame,
1957 struct i386_frame_cache *cache)
1959 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1960 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1964 cache->pc = get_frame_func (this_frame);
1966 /* In principle, for normal frames, %ebp holds the frame pointer,
1967 which holds the base address for the current stack frame.
1968 However, for functions that don't need it, the frame pointer is
1969 optional. For these "frameless" functions the frame pointer is
1970 actually the frame pointer of the calling frame. Signal
1971 trampolines are just a special case of a "frameless" function.
1972 They (usually) share their frame pointer with the frame that was
1973 in progress when the signal occurred. */
1975 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1976 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1977 if (cache->base == 0)
1983 /* For normal frames, %eip is stored at 4(%ebp). */
1984 cache->saved_regs[I386_EIP_REGNUM] = 4;
1987 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
1990 if (cache->locals < 0)
1992 /* We didn't find a valid frame, which means that CACHE->base
1993 currently holds the frame pointer for our calling frame. If
1994 we're at the start of a function, or somewhere half-way its
1995 prologue, the function's frame probably hasn't been fully
1996 setup yet. Try to reconstruct the base address for the stack
1997 frame by looking at the stack pointer. For truly "frameless"
1998 functions this might work too. */
2000 if (cache->saved_sp_reg != -1)
2002 /* Saved stack pointer has been saved. */
2003 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2004 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2006 /* We're halfway aligning the stack. */
2007 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
2008 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
2010 /* This will be added back below. */
2011 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
2013 else if (cache->pc != 0
2014 || target_read_code (get_frame_pc (this_frame), buf, 1))
2016 /* We're in a known function, but did not find a frame
2017 setup. Assume that the function does not use %ebp.
2018 Alternatively, we may have jumped to an invalid
2019 address; in that case there is definitely no new
2021 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2022 cache->base = extract_unsigned_integer (buf, 4, byte_order)
2026 /* We're in an unknown function. We could not find the start
2027 of the function to analyze the prologue; our best option is
2028 to assume a typical frame layout with the caller's %ebp
2030 cache->saved_regs[I386_EBP_REGNUM] = 0;
2033 if (cache->saved_sp_reg != -1)
2035 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2036 register may be unavailable). */
2037 if (cache->saved_sp == 0
2038 && deprecated_frame_register_read (this_frame,
2039 cache->saved_sp_reg, buf))
2040 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2042 /* Now that we have the base address for the stack frame we can
2043 calculate the value of %esp in the calling frame. */
2044 else if (cache->saved_sp == 0)
2045 cache->saved_sp = cache->base + 8;
2047 /* Adjust all the saved registers such that they contain addresses
2048 instead of offsets. */
2049 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
2050 if (cache->saved_regs[i] != -1)
2051 cache->saved_regs[i] += cache->base;
2056 static struct i386_frame_cache *
2057 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
2059 struct i386_frame_cache *cache;
2062 return (struct i386_frame_cache *) *this_cache;
2064 cache = i386_alloc_frame_cache ();
2065 *this_cache = cache;
2069 i386_frame_cache_1 (this_frame, cache);
2071 CATCH (ex, RETURN_MASK_ERROR)
2073 if (ex.error != NOT_AVAILABLE_ERROR)
2074 throw_exception (ex);
2082 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
2083 struct frame_id *this_id)
2085 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2088 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2089 else if (cache->base == 0)
2091 /* This marks the outermost frame. */
2095 /* See the end of i386_push_dummy_call. */
2096 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2100 static enum unwind_stop_reason
2101 i386_frame_unwind_stop_reason (struct frame_info *this_frame,
2104 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2107 return UNWIND_UNAVAILABLE;
2109 /* This marks the outermost frame. */
2110 if (cache->base == 0)
2111 return UNWIND_OUTERMOST;
2113 return UNWIND_NO_REASON;
2116 static struct value *
2117 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2120 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2122 gdb_assert (regnum >= 0);
2124 /* The System V ABI says that:
2126 "The flags register contains the system flags, such as the
2127 direction flag and the carry flag. The direction flag must be
2128 set to the forward (that is, zero) direction before entry and
2129 upon exit from a function. Other user flags have no specified
2130 role in the standard calling sequence and are not preserved."
2132 To guarantee the "upon exit" part of that statement we fake a
2133 saved flags register that has its direction flag cleared.
2135 Note that GCC doesn't seem to rely on the fact that the direction
2136 flag is cleared after a function return; it always explicitly
2137 clears the flag before operations where it matters.
2139 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2140 right thing to do. The way we fake the flags register here makes
2141 it impossible to change it. */
2143 if (regnum == I386_EFLAGS_REGNUM)
2147 val = get_frame_register_unsigned (this_frame, regnum);
2149 return frame_unwind_got_constant (this_frame, regnum, val);
2152 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
2153 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
2155 if (regnum == I386_ESP_REGNUM
2156 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1))
2158 /* If the SP has been saved, but we don't know where, then this
2159 means that SAVED_SP_REG register was found unavailable back
2160 when we built the cache. */
2161 if (cache->saved_sp == 0)
2162 return frame_unwind_got_register (this_frame, regnum,
2163 cache->saved_sp_reg);
2165 return frame_unwind_got_constant (this_frame, regnum,
2169 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2170 return frame_unwind_got_memory (this_frame, regnum,
2171 cache->saved_regs[regnum]);
2173 return frame_unwind_got_register (this_frame, regnum, regnum);
2176 static const struct frame_unwind i386_frame_unwind =
2179 i386_frame_unwind_stop_reason,
2181 i386_frame_prev_register,
2183 default_frame_sniffer
2186 /* Normal frames, but in a function epilogue. */
2188 /* Implement the stack_frame_destroyed_p gdbarch method.
2190 The epilogue is defined here as the 'ret' instruction, which will
2191 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2192 the function's stack frame. */
2195 i386_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2198 struct compunit_symtab *cust;
2200 cust = find_pc_compunit_symtab (pc);
2201 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
2204 if (target_read_memory (pc, &insn, 1))
2205 return 0; /* Can't read memory at pc. */
2207 if (insn != 0xc3) /* 'ret' instruction. */
2214 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
2215 struct frame_info *this_frame,
2216 void **this_prologue_cache)
2218 if (frame_relative_level (this_frame) == 0)
2219 return i386_stack_frame_destroyed_p (get_frame_arch (this_frame),
2220 get_frame_pc (this_frame));
2225 static struct i386_frame_cache *
2226 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2228 struct i386_frame_cache *cache;
2232 return (struct i386_frame_cache *) *this_cache;
2234 cache = i386_alloc_frame_cache ();
2235 *this_cache = cache;
2239 cache->pc = get_frame_func (this_frame);
2241 /* At this point the stack looks as if we just entered the
2242 function, with the return address at the top of the
2244 sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM);
2245 cache->base = sp + cache->sp_offset;
2246 cache->saved_sp = cache->base + 8;
2247 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
2251 CATCH (ex, RETURN_MASK_ERROR)
2253 if (ex.error != NOT_AVAILABLE_ERROR)
2254 throw_exception (ex);
2261 static enum unwind_stop_reason
2262 i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2265 struct i386_frame_cache *cache =
2266 i386_epilogue_frame_cache (this_frame, this_cache);
2269 return UNWIND_UNAVAILABLE;
2271 return UNWIND_NO_REASON;
2275 i386_epilogue_frame_this_id (struct frame_info *this_frame,
2277 struct frame_id *this_id)
2279 struct i386_frame_cache *cache =
2280 i386_epilogue_frame_cache (this_frame, this_cache);
2283 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2285 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2288 static struct value *
2289 i386_epilogue_frame_prev_register (struct frame_info *this_frame,
2290 void **this_cache, int regnum)
2292 /* Make sure we've initialized the cache. */
2293 i386_epilogue_frame_cache (this_frame, this_cache);
2295 return i386_frame_prev_register (this_frame, this_cache, regnum);
2298 static const struct frame_unwind i386_epilogue_frame_unwind =
2301 i386_epilogue_frame_unwind_stop_reason,
2302 i386_epilogue_frame_this_id,
2303 i386_epilogue_frame_prev_register,
2305 i386_epilogue_frame_sniffer
2309 /* Stack-based trampolines. */
2311 /* These trampolines are used on cross x86 targets, when taking the
2312 address of a nested function. When executing these trampolines,
2313 no stack frame is set up, so we are in a similar situation as in
2314 epilogues and i386_epilogue_frame_this_id can be re-used. */
2316 /* Static chain passed in register. */
2318 struct i386_insn i386_tramp_chain_in_reg_insns[] =
2320 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2321 { 5, { 0xb8 }, { 0xfe } },
2324 { 5, { 0xe9 }, { 0xff } },
2329 /* Static chain passed on stack (when regparm=3). */
2331 struct i386_insn i386_tramp_chain_on_stack_insns[] =
2334 { 5, { 0x68 }, { 0xff } },
2337 { 5, { 0xe9 }, { 0xff } },
2342 /* Return whether PC points inside a stack trampoline. */
2345 i386_in_stack_tramp_p (CORE_ADDR pc)
2350 /* A stack trampoline is detected if no name is associated
2351 to the current pc and if it points inside a trampoline
2354 find_pc_partial_function (pc, &name, NULL, NULL);
2358 if (target_read_memory (pc, &insn, 1))
2361 if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns)
2362 && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns))
2369 i386_stack_tramp_frame_sniffer (const struct frame_unwind *self,
2370 struct frame_info *this_frame,
2373 if (frame_relative_level (this_frame) == 0)
2374 return i386_in_stack_tramp_p (get_frame_pc (this_frame));
2379 static const struct frame_unwind i386_stack_tramp_frame_unwind =
2382 i386_epilogue_frame_unwind_stop_reason,
2383 i386_epilogue_frame_this_id,
2384 i386_epilogue_frame_prev_register,
2386 i386_stack_tramp_frame_sniffer
2389 /* Generate a bytecode expression to get the value of the saved PC. */
2392 i386_gen_return_address (struct gdbarch *gdbarch,
2393 struct agent_expr *ax, struct axs_value *value,
2396 /* The following sequence assumes the traditional use of the base
2398 ax_reg (ax, I386_EBP_REGNUM);
2400 ax_simple (ax, aop_add);
2401 value->type = register_type (gdbarch, I386_EIP_REGNUM);
2402 value->kind = axs_lvalue_memory;
2406 /* Signal trampolines. */
2408 static struct i386_frame_cache *
2409 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2411 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2412 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2413 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2414 struct i386_frame_cache *cache;
2419 return (struct i386_frame_cache *) *this_cache;
2421 cache = i386_alloc_frame_cache ();
2425 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2426 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
2428 addr = tdep->sigcontext_addr (this_frame);
2429 if (tdep->sc_reg_offset)
2433 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
2435 for (i = 0; i < tdep->sc_num_regs; i++)
2436 if (tdep->sc_reg_offset[i] != -1)
2437 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2441 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
2442 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
2447 CATCH (ex, RETURN_MASK_ERROR)
2449 if (ex.error != NOT_AVAILABLE_ERROR)
2450 throw_exception (ex);
2454 *this_cache = cache;
2458 static enum unwind_stop_reason
2459 i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2462 struct i386_frame_cache *cache =
2463 i386_sigtramp_frame_cache (this_frame, this_cache);
2466 return UNWIND_UNAVAILABLE;
2468 return UNWIND_NO_REASON;
2472 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
2473 struct frame_id *this_id)
2475 struct i386_frame_cache *cache =
2476 i386_sigtramp_frame_cache (this_frame, this_cache);
2479 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2482 /* See the end of i386_push_dummy_call. */
2483 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
2487 static struct value *
2488 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
2489 void **this_cache, int regnum)
2491 /* Make sure we've initialized the cache. */
2492 i386_sigtramp_frame_cache (this_frame, this_cache);
2494 return i386_frame_prev_register (this_frame, this_cache, regnum);
2498 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
2499 struct frame_info *this_frame,
2500 void **this_prologue_cache)
2502 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2504 /* We shouldn't even bother if we don't have a sigcontext_addr
2506 if (tdep->sigcontext_addr == NULL)
2509 if (tdep->sigtramp_p != NULL)
2511 if (tdep->sigtramp_p (this_frame))
2515 if (tdep->sigtramp_start != 0)
2517 CORE_ADDR pc = get_frame_pc (this_frame);
2519 gdb_assert (tdep->sigtramp_end != 0);
2520 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2527 static const struct frame_unwind i386_sigtramp_frame_unwind =
2530 i386_sigtramp_frame_unwind_stop_reason,
2531 i386_sigtramp_frame_this_id,
2532 i386_sigtramp_frame_prev_register,
2534 i386_sigtramp_frame_sniffer
2539 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
2541 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2546 static const struct frame_base i386_frame_base =
2549 i386_frame_base_address,
2550 i386_frame_base_address,
2551 i386_frame_base_address
2554 static struct frame_id
2555 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2559 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
2561 /* See the end of i386_push_dummy_call. */
2562 return frame_id_build (fp + 8, get_frame_pc (this_frame));
2565 /* _Decimal128 function return values need 16-byte alignment on the
2569 i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2571 return sp & -(CORE_ADDR)16;
2575 /* Figure out where the longjmp will land. Slurp the args out of the
2576 stack. We expect the first arg to be a pointer to the jmp_buf
2577 structure from which we extract the address that we will land at.
2578 This address is copied into PC. This routine returns non-zero on
2582 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2585 CORE_ADDR sp, jb_addr;
2586 struct gdbarch *gdbarch = get_frame_arch (frame);
2587 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2588 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2590 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2591 longjmp will land. */
2592 if (jb_pc_offset == -1)
2595 get_frame_register (frame, I386_ESP_REGNUM, buf);
2596 sp = extract_unsigned_integer (buf, 4, byte_order);
2597 if (target_read_memory (sp + 4, buf, 4))
2600 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
2601 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
2604 *pc = extract_unsigned_integer (buf, 4, byte_order);
2609 /* Check whether TYPE must be 16-byte-aligned when passed as a
2610 function argument. 16-byte vectors, _Decimal128 and structures or
2611 unions containing such types must be 16-byte-aligned; other
2612 arguments are 4-byte-aligned. */
2615 i386_16_byte_align_p (struct type *type)
2617 type = check_typedef (type);
2618 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
2619 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
2620 && TYPE_LENGTH (type) == 16)
2622 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2623 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
2624 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2625 || TYPE_CODE (type) == TYPE_CODE_UNION)
2628 for (i = 0; i < TYPE_NFIELDS (type); i++)
2630 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
2637 /* Implementation for set_gdbarch_push_dummy_code. */
2640 i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
2641 struct value **args, int nargs, struct type *value_type,
2642 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
2643 struct regcache *regcache)
2645 /* Use 0xcc breakpoint - 1 byte. */
2649 /* Keep the stack aligned. */
2654 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2655 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2656 struct value **args, CORE_ADDR sp, int struct_return,
2657 CORE_ADDR struct_addr)
2659 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2665 /* Determine the total space required for arguments and struct
2666 return address in a first pass (allowing for 16-byte-aligned
2667 arguments), then push arguments in a second pass. */
2669 for (write_pass = 0; write_pass < 2; write_pass++)
2671 int args_space_used = 0;
2677 /* Push value address. */
2678 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2679 write_memory (sp, buf, 4);
2680 args_space_used += 4;
2686 for (i = 0; i < nargs; i++)
2688 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2692 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2693 args_space_used = align_up (args_space_used, 16);
2695 write_memory (sp + args_space_used,
2696 value_contents_all (args[i]), len);
2697 /* The System V ABI says that:
2699 "An argument's size is increased, if necessary, to make it a
2700 multiple of [32-bit] words. This may require tail padding,
2701 depending on the size of the argument."
2703 This makes sure the stack stays word-aligned. */
2704 args_space_used += align_up (len, 4);
2708 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2709 args_space = align_up (args_space, 16);
2710 args_space += align_up (len, 4);
2718 /* The original System V ABI only requires word alignment,
2719 but modern incarnations need 16-byte alignment in order
2720 to support SSE. Since wasting a few bytes here isn't
2721 harmful we unconditionally enforce 16-byte alignment. */
2726 /* Store return address. */
2728 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2729 write_memory (sp, buf, 4);
2731 /* Finally, update the stack pointer... */
2732 store_unsigned_integer (buf, 4, byte_order, sp);
2733 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
2735 /* ...and fake a frame pointer. */
2736 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
2738 /* MarkK wrote: This "+ 8" is all over the place:
2739 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2740 i386_dummy_id). It's there, since all frame unwinders for
2741 a given target have to agree (within a certain margin) on the
2742 definition of the stack address of a frame. Otherwise frame id
2743 comparison might not work correctly. Since DWARF2/GCC uses the
2744 stack address *before* the function call as a frame's CFA. On
2745 the i386, when %ebp is used as a frame pointer, the offset
2746 between the contents %ebp and the CFA as defined by GCC. */
2750 /* These registers are used for returning integers (and on some
2751 targets also for returning `struct' and `union' values when their
2752 size and alignment match an integer type). */
2753 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2754 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2756 /* Read, for architecture GDBARCH, a function return value of TYPE
2757 from REGCACHE, and copy that into VALBUF. */
2760 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2761 struct regcache *regcache, gdb_byte *valbuf)
2763 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2764 int len = TYPE_LENGTH (type);
2765 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2767 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2769 if (tdep->st0_regnum < 0)
2771 warning (_("Cannot find floating-point return value."));
2772 memset (valbuf, 0, len);
2776 /* Floating-point return values can be found in %st(0). Convert
2777 its contents to the desired type. This is probably not
2778 exactly how it would happen on the target itself, but it is
2779 the best we can do. */
2780 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2781 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
2785 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2786 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2788 if (len <= low_size)
2790 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2791 memcpy (valbuf, buf, len);
2793 else if (len <= (low_size + high_size))
2795 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2796 memcpy (valbuf, buf, low_size);
2797 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2798 memcpy (valbuf + low_size, buf, len - low_size);
2801 internal_error (__FILE__, __LINE__,
2802 _("Cannot extract return value of %d bytes long."),
2807 /* Write, for architecture GDBARCH, a function return value of TYPE
2808 from VALBUF into REGCACHE. */
2811 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2812 struct regcache *regcache, const gdb_byte *valbuf)
2814 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2815 int len = TYPE_LENGTH (type);
2817 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2820 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2822 if (tdep->st0_regnum < 0)
2824 warning (_("Cannot set floating-point return value."));
2828 /* Returning floating-point values is a bit tricky. Apart from
2829 storing the return value in %st(0), we have to simulate the
2830 state of the FPU at function return point. */
2832 /* Convert the value found in VALBUF to the extended
2833 floating-point format used by the FPU. This is probably
2834 not exactly how it would happen on the target itself, but
2835 it is the best we can do. */
2836 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
2837 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2839 /* Set the top of the floating-point register stack to 7. The
2840 actual value doesn't really matter, but 7 is what a normal
2841 function return would end up with if the program started out
2842 with a freshly initialized FPU. */
2843 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2845 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2847 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2848 the floating-point register stack to 7, the appropriate value
2849 for the tag word is 0x3fff. */
2850 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2854 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2855 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2857 if (len <= low_size)
2858 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2859 else if (len <= (low_size + high_size))
2861 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2862 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
2863 len - low_size, valbuf + low_size);
2866 internal_error (__FILE__, __LINE__,
2867 _("Cannot store return value of %d bytes long."), len);
2872 /* This is the variable that is set with "set struct-convention", and
2873 its legitimate values. */
2874 static const char default_struct_convention[] = "default";
2875 static const char pcc_struct_convention[] = "pcc";
2876 static const char reg_struct_convention[] = "reg";
2877 static const char *const valid_conventions[] =
2879 default_struct_convention,
2880 pcc_struct_convention,
2881 reg_struct_convention,
2884 static const char *struct_convention = default_struct_convention;
2886 /* Return non-zero if TYPE, which is assumed to be a structure,
2887 a union type, or an array type, should be returned in registers
2888 for architecture GDBARCH. */
2891 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2893 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2894 enum type_code code = TYPE_CODE (type);
2895 int len = TYPE_LENGTH (type);
2897 gdb_assert (code == TYPE_CODE_STRUCT
2898 || code == TYPE_CODE_UNION
2899 || code == TYPE_CODE_ARRAY);
2901 if (struct_convention == pcc_struct_convention
2902 || (struct_convention == default_struct_convention
2903 && tdep->struct_return == pcc_struct_return))
2906 /* Structures consisting of a single `float', `double' or 'long
2907 double' member are returned in %st(0). */
2908 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2910 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2911 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2912 return (len == 4 || len == 8 || len == 12);
2915 return (len == 1 || len == 2 || len == 4 || len == 8);
2918 /* Determine, for architecture GDBARCH, how a return value of TYPE
2919 should be returned. If it is supposed to be returned in registers,
2920 and READBUF is non-zero, read the appropriate value from REGCACHE,
2921 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2922 from WRITEBUF into REGCACHE. */
2924 static enum return_value_convention
2925 i386_return_value (struct gdbarch *gdbarch, struct value *function,
2926 struct type *type, struct regcache *regcache,
2927 gdb_byte *readbuf, const gdb_byte *writebuf)
2929 enum type_code code = TYPE_CODE (type);
2931 if (((code == TYPE_CODE_STRUCT
2932 || code == TYPE_CODE_UNION
2933 || code == TYPE_CODE_ARRAY)
2934 && !i386_reg_struct_return_p (gdbarch, type))
2935 /* Complex double and long double uses the struct return covention. */
2936 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16)
2937 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24)
2938 /* 128-bit decimal float uses the struct return convention. */
2939 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2941 /* The System V ABI says that:
2943 "A function that returns a structure or union also sets %eax
2944 to the value of the original address of the caller's area
2945 before it returns. Thus when the caller receives control
2946 again, the address of the returned object resides in register
2947 %eax and can be used to access the object."
2949 So the ABI guarantees that we can always find the return
2950 value just after the function has returned. */
2952 /* Note that the ABI doesn't mention functions returning arrays,
2953 which is something possible in certain languages such as Ada.
2954 In this case, the value is returned as if it was wrapped in
2955 a record, so the convention applied to records also applies
2962 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2963 read_memory (addr, readbuf, TYPE_LENGTH (type));
2966 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2969 /* This special case is for structures consisting of a single
2970 `float', `double' or 'long double' member. These structures are
2971 returned in %st(0). For these structures, we call ourselves
2972 recursively, changing TYPE into the type of the first member of
2973 the structure. Since that should work for all structures that
2974 have only one member, we don't bother to check the member's type
2976 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2978 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2979 return i386_return_value (gdbarch, function, type, regcache,
2984 i386_extract_return_value (gdbarch, type, regcache, readbuf);
2986 i386_store_return_value (gdbarch, type, regcache, writebuf);
2988 return RETURN_VALUE_REGISTER_CONVENTION;
2993 i387_ext_type (struct gdbarch *gdbarch)
2995 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2997 if (!tdep->i387_ext_type)
2999 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
3000 gdb_assert (tdep->i387_ext_type != NULL);
3003 return tdep->i387_ext_type;
3006 /* Construct type for pseudo BND registers. We can't use
3007 tdesc_find_type since a complement of one value has to be used
3008 to describe the upper bound. */
3010 static struct type *
3011 i386_bnd_type (struct gdbarch *gdbarch)
3013 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3016 if (!tdep->i386_bnd_type)
3019 const struct builtin_type *bt = builtin_type (gdbarch);
3021 /* The type we're building is described bellow: */
3026 void *ubound; /* One complement of raw ubound field. */
3030 t = arch_composite_type (gdbarch,
3031 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT);
3033 append_composite_type_field (t, "lbound", bt->builtin_data_ptr);
3034 append_composite_type_field (t, "ubound", bt->builtin_data_ptr);
3036 TYPE_NAME (t) = "builtin_type_bound128";
3037 tdep->i386_bnd_type = t;
3040 return tdep->i386_bnd_type;
3043 /* Construct vector type for pseudo ZMM registers. We can't use
3044 tdesc_find_type since ZMM isn't described in target description. */
3046 static struct type *
3047 i386_zmm_type (struct gdbarch *gdbarch)
3049 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3051 if (!tdep->i386_zmm_type)
3053 const struct builtin_type *bt = builtin_type (gdbarch);
3055 /* The type we're building is this: */
3057 union __gdb_builtin_type_vec512i
3059 int128_t uint128[4];
3060 int64_t v4_int64[8];
3061 int32_t v8_int32[16];
3062 int16_t v16_int16[32];
3063 int8_t v32_int8[64];
3064 double v4_double[8];
3071 t = arch_composite_type (gdbarch,
3072 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION);
3073 append_composite_type_field (t, "v16_float",
3074 init_vector_type (bt->builtin_float, 16));
3075 append_composite_type_field (t, "v8_double",
3076 init_vector_type (bt->builtin_double, 8));
3077 append_composite_type_field (t, "v64_int8",
3078 init_vector_type (bt->builtin_int8, 64));
3079 append_composite_type_field (t, "v32_int16",
3080 init_vector_type (bt->builtin_int16, 32));
3081 append_composite_type_field (t, "v16_int32",
3082 init_vector_type (bt->builtin_int32, 16));
3083 append_composite_type_field (t, "v8_int64",
3084 init_vector_type (bt->builtin_int64, 8));
3085 append_composite_type_field (t, "v4_int128",
3086 init_vector_type (bt->builtin_int128, 4));
3088 TYPE_VECTOR (t) = 1;
3089 TYPE_NAME (t) = "builtin_type_vec512i";
3090 tdep->i386_zmm_type = t;
3093 return tdep->i386_zmm_type;
3096 /* Construct vector type for pseudo YMM registers. We can't use
3097 tdesc_find_type since YMM isn't described in target description. */
3099 static struct type *
3100 i386_ymm_type (struct gdbarch *gdbarch)
3102 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3104 if (!tdep->i386_ymm_type)
3106 const struct builtin_type *bt = builtin_type (gdbarch);
3108 /* The type we're building is this: */
3110 union __gdb_builtin_type_vec256i
3112 int128_t uint128[2];
3113 int64_t v2_int64[4];
3114 int32_t v4_int32[8];
3115 int16_t v8_int16[16];
3116 int8_t v16_int8[32];
3117 double v2_double[4];
3124 t = arch_composite_type (gdbarch,
3125 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
3126 append_composite_type_field (t, "v8_float",
3127 init_vector_type (bt->builtin_float, 8));
3128 append_composite_type_field (t, "v4_double",
3129 init_vector_type (bt->builtin_double, 4));
3130 append_composite_type_field (t, "v32_int8",
3131 init_vector_type (bt->builtin_int8, 32));
3132 append_composite_type_field (t, "v16_int16",
3133 init_vector_type (bt->builtin_int16, 16));
3134 append_composite_type_field (t, "v8_int32",
3135 init_vector_type (bt->builtin_int32, 8));
3136 append_composite_type_field (t, "v4_int64",
3137 init_vector_type (bt->builtin_int64, 4));
3138 append_composite_type_field (t, "v2_int128",
3139 init_vector_type (bt->builtin_int128, 2));
3141 TYPE_VECTOR (t) = 1;
3142 TYPE_NAME (t) = "builtin_type_vec256i";
3143 tdep->i386_ymm_type = t;
3146 return tdep->i386_ymm_type;
3149 /* Construct vector type for MMX registers. */
3150 static struct type *
3151 i386_mmx_type (struct gdbarch *gdbarch)
3153 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3155 if (!tdep->i386_mmx_type)
3157 const struct builtin_type *bt = builtin_type (gdbarch);
3159 /* The type we're building is this: */
3161 union __gdb_builtin_type_vec64i
3164 int32_t v2_int32[2];
3165 int16_t v4_int16[4];
3172 t = arch_composite_type (gdbarch,
3173 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
3175 append_composite_type_field (t, "uint64", bt->builtin_int64);
3176 append_composite_type_field (t, "v2_int32",
3177 init_vector_type (bt->builtin_int32, 2));
3178 append_composite_type_field (t, "v4_int16",
3179 init_vector_type (bt->builtin_int16, 4));
3180 append_composite_type_field (t, "v8_int8",
3181 init_vector_type (bt->builtin_int8, 8));
3183 TYPE_VECTOR (t) = 1;
3184 TYPE_NAME (t) = "builtin_type_vec64i";
3185 tdep->i386_mmx_type = t;
3188 return tdep->i386_mmx_type;
3191 /* Return the GDB type object for the "standard" data type of data in
3195 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3197 if (i386_bnd_regnum_p (gdbarch, regnum))
3198 return i386_bnd_type (gdbarch);
3199 if (i386_mmx_regnum_p (gdbarch, regnum))
3200 return i386_mmx_type (gdbarch);
3201 else if (i386_ymm_regnum_p (gdbarch, regnum))
3202 return i386_ymm_type (gdbarch);
3203 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3204 return i386_ymm_type (gdbarch);
3205 else if (i386_zmm_regnum_p (gdbarch, regnum))
3206 return i386_zmm_type (gdbarch);
3209 const struct builtin_type *bt = builtin_type (gdbarch);
3210 if (i386_byte_regnum_p (gdbarch, regnum))
3211 return bt->builtin_int8;
3212 else if (i386_word_regnum_p (gdbarch, regnum))
3213 return bt->builtin_int16;
3214 else if (i386_dword_regnum_p (gdbarch, regnum))
3215 return bt->builtin_int32;
3216 else if (i386_k_regnum_p (gdbarch, regnum))
3217 return bt->builtin_int64;
3220 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3223 /* Map a cooked register onto a raw register or memory. For the i386,
3224 the MMX registers need to be mapped onto floating point registers. */
3227 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
3229 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
3234 mmxreg = regnum - tdep->mm0_regnum;
3235 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
3236 tos = (fstat >> 11) & 0x7;
3237 fpreg = (mmxreg + tos) % 8;
3239 return (I387_ST0_REGNUM (tdep) + fpreg);
3242 /* A helper function for us by i386_pseudo_register_read_value and
3243 amd64_pseudo_register_read_value. It does all the work but reads
3244 the data into an already-allocated value. */
3247 i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
3248 struct regcache *regcache,
3250 struct value *result_value)
3252 gdb_byte raw_buf[MAX_REGISTER_SIZE];
3253 enum register_status status;
3254 gdb_byte *buf = value_contents_raw (result_value);
3256 if (i386_mmx_regnum_p (gdbarch, regnum))
3258 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3260 /* Extract (always little endian). */
3261 status = regcache_raw_read (regcache, fpnum, raw_buf);
3262 if (status != REG_VALID)
3263 mark_value_bytes_unavailable (result_value, 0,
3264 TYPE_LENGTH (value_type (result_value)));
3266 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
3270 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3271 if (i386_bnd_regnum_p (gdbarch, regnum))
3273 regnum -= tdep->bnd0_regnum;
3275 /* Extract (always little endian). Read lower 128bits. */
3276 status = regcache_raw_read (regcache,
3277 I387_BND0R_REGNUM (tdep) + regnum,
3279 if (status != REG_VALID)
3280 mark_value_bytes_unavailable (result_value, 0, 16);
3283 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3284 LONGEST upper, lower;
3285 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3287 lower = extract_unsigned_integer (raw_buf, 8, byte_order);
3288 upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order);
3291 memcpy (buf, &lower, size);
3292 memcpy (buf + size, &upper, size);
3295 else if (i386_k_regnum_p (gdbarch, regnum))
3297 regnum -= tdep->k0_regnum;
3299 /* Extract (always little endian). */
3300 status = regcache_raw_read (regcache,
3301 tdep->k0_regnum + regnum,
3303 if (status != REG_VALID)
3304 mark_value_bytes_unavailable (result_value, 0, 8);
3306 memcpy (buf, raw_buf, 8);
3308 else if (i386_zmm_regnum_p (gdbarch, regnum))
3310 regnum -= tdep->zmm0_regnum;
3312 if (regnum < num_lower_zmm_regs)
3314 /* Extract (always little endian). Read lower 128bits. */
3315 status = regcache_raw_read (regcache,
3316 I387_XMM0_REGNUM (tdep) + regnum,
3318 if (status != REG_VALID)
3319 mark_value_bytes_unavailable (result_value, 0, 16);
3321 memcpy (buf, raw_buf, 16);
3323 /* Extract (always little endian). Read upper 128bits. */
3324 status = regcache_raw_read (regcache,
3325 tdep->ymm0h_regnum + regnum,
3327 if (status != REG_VALID)
3328 mark_value_bytes_unavailable (result_value, 16, 16);
3330 memcpy (buf + 16, raw_buf, 16);
3334 /* Extract (always little endian). Read lower 128bits. */
3335 status = regcache_raw_read (regcache,
3336 I387_XMM16_REGNUM (tdep) + regnum
3337 - num_lower_zmm_regs,
3339 if (status != REG_VALID)
3340 mark_value_bytes_unavailable (result_value, 0, 16);
3342 memcpy (buf, raw_buf, 16);
3344 /* Extract (always little endian). Read upper 128bits. */
3345 status = regcache_raw_read (regcache,
3346 I387_YMM16H_REGNUM (tdep) + regnum
3347 - num_lower_zmm_regs,
3349 if (status != REG_VALID)
3350 mark_value_bytes_unavailable (result_value, 16, 16);
3352 memcpy (buf + 16, raw_buf, 16);
3355 /* Read upper 256bits. */
3356 status = regcache_raw_read (regcache,
3357 tdep->zmm0h_regnum + regnum,
3359 if (status != REG_VALID)
3360 mark_value_bytes_unavailable (result_value, 32, 32);
3362 memcpy (buf + 32, raw_buf, 32);
3364 else if (i386_ymm_regnum_p (gdbarch, regnum))
3366 regnum -= tdep->ymm0_regnum;
3368 /* Extract (always little endian). Read lower 128bits. */
3369 status = regcache_raw_read (regcache,
3370 I387_XMM0_REGNUM (tdep) + regnum,
3372 if (status != REG_VALID)
3373 mark_value_bytes_unavailable (result_value, 0, 16);
3375 memcpy (buf, raw_buf, 16);
3376 /* Read upper 128bits. */
3377 status = regcache_raw_read (regcache,
3378 tdep->ymm0h_regnum + regnum,
3380 if (status != REG_VALID)
3381 mark_value_bytes_unavailable (result_value, 16, 32);
3383 memcpy (buf + 16, raw_buf, 16);
3385 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3387 regnum -= tdep->ymm16_regnum;
3388 /* Extract (always little endian). Read lower 128bits. */
3389 status = regcache_raw_read (regcache,
3390 I387_XMM16_REGNUM (tdep) + regnum,
3392 if (status != REG_VALID)
3393 mark_value_bytes_unavailable (result_value, 0, 16);
3395 memcpy (buf, raw_buf, 16);
3396 /* Read upper 128bits. */
3397 status = regcache_raw_read (regcache,
3398 tdep->ymm16h_regnum + regnum,
3400 if (status != REG_VALID)
3401 mark_value_bytes_unavailable (result_value, 16, 16);
3403 memcpy (buf + 16, raw_buf, 16);
3405 else if (i386_word_regnum_p (gdbarch, regnum))
3407 int gpnum = regnum - tdep->ax_regnum;
3409 /* Extract (always little endian). */
3410 status = regcache_raw_read (regcache, gpnum, raw_buf);
3411 if (status != REG_VALID)
3412 mark_value_bytes_unavailable (result_value, 0,
3413 TYPE_LENGTH (value_type (result_value)));
3415 memcpy (buf, raw_buf, 2);
3417 else if (i386_byte_regnum_p (gdbarch, regnum))
3419 int gpnum = regnum - tdep->al_regnum;
3421 /* Extract (always little endian). We read both lower and
3423 status = regcache_raw_read (regcache, gpnum % 4, raw_buf);
3424 if (status != REG_VALID)
3425 mark_value_bytes_unavailable (result_value, 0,
3426 TYPE_LENGTH (value_type (result_value)));
3427 else if (gpnum >= 4)
3428 memcpy (buf, raw_buf + 1, 1);
3430 memcpy (buf, raw_buf, 1);
3433 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3437 static struct value *
3438 i386_pseudo_register_read_value (struct gdbarch *gdbarch,
3439 struct regcache *regcache,
3442 struct value *result;
3444 result = allocate_value (register_type (gdbarch, regnum));
3445 VALUE_LVAL (result) = lval_register;
3446 VALUE_REGNUM (result) = regnum;
3448 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result);
3454 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3455 int regnum, const gdb_byte *buf)
3457 gdb_byte raw_buf[MAX_REGISTER_SIZE];
3459 if (i386_mmx_regnum_p (gdbarch, regnum))
3461 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3464 regcache_raw_read (regcache, fpnum, raw_buf);
3465 /* ... Modify ... (always little endian). */
3466 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
3468 regcache_raw_write (regcache, fpnum, raw_buf);
3472 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3474 if (i386_bnd_regnum_p (gdbarch, regnum))
3476 ULONGEST upper, lower;
3477 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3478 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3480 /* New values from input value. */
3481 regnum -= tdep->bnd0_regnum;
3482 lower = extract_unsigned_integer (buf, size, byte_order);
3483 upper = extract_unsigned_integer (buf + size, size, byte_order);
3485 /* Fetching register buffer. */
3486 regcache_raw_read (regcache,
3487 I387_BND0R_REGNUM (tdep) + regnum,
3492 /* Set register bits. */
3493 memcpy (raw_buf, &lower, 8);
3494 memcpy (raw_buf + 8, &upper, 8);
3497 regcache_raw_write (regcache,
3498 I387_BND0R_REGNUM (tdep) + regnum,
3501 else if (i386_k_regnum_p (gdbarch, regnum))
3503 regnum -= tdep->k0_regnum;
3505 regcache_raw_write (regcache,
3506 tdep->k0_regnum + regnum,
3509 else if (i386_zmm_regnum_p (gdbarch, regnum))
3511 regnum -= tdep->zmm0_regnum;
3513 if (regnum < num_lower_zmm_regs)
3515 /* Write lower 128bits. */
3516 regcache_raw_write (regcache,
3517 I387_XMM0_REGNUM (tdep) + regnum,
3519 /* Write upper 128bits. */
3520 regcache_raw_write (regcache,
3521 I387_YMM0_REGNUM (tdep) + regnum,
3526 /* Write lower 128bits. */
3527 regcache_raw_write (regcache,
3528 I387_XMM16_REGNUM (tdep) + regnum
3529 - num_lower_zmm_regs,
3531 /* Write upper 128bits. */
3532 regcache_raw_write (regcache,
3533 I387_YMM16H_REGNUM (tdep) + regnum
3534 - num_lower_zmm_regs,
3537 /* Write upper 256bits. */
3538 regcache_raw_write (regcache,
3539 tdep->zmm0h_regnum + regnum,
3542 else if (i386_ymm_regnum_p (gdbarch, regnum))
3544 regnum -= tdep->ymm0_regnum;
3546 /* ... Write lower 128bits. */
3547 regcache_raw_write (regcache,
3548 I387_XMM0_REGNUM (tdep) + regnum,
3550 /* ... Write upper 128bits. */
3551 regcache_raw_write (regcache,
3552 tdep->ymm0h_regnum + regnum,
3555 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3557 regnum -= tdep->ymm16_regnum;
3559 /* ... Write lower 128bits. */
3560 regcache_raw_write (regcache,
3561 I387_XMM16_REGNUM (tdep) + regnum,
3563 /* ... Write upper 128bits. */
3564 regcache_raw_write (regcache,
3565 tdep->ymm16h_regnum + regnum,
3568 else if (i386_word_regnum_p (gdbarch, regnum))
3570 int gpnum = regnum - tdep->ax_regnum;
3573 regcache_raw_read (regcache, gpnum, raw_buf);
3574 /* ... Modify ... (always little endian). */
3575 memcpy (raw_buf, buf, 2);
3577 regcache_raw_write (regcache, gpnum, raw_buf);
3579 else if (i386_byte_regnum_p (gdbarch, regnum))
3581 int gpnum = regnum - tdep->al_regnum;
3583 /* Read ... We read both lower and upper registers. */
3584 regcache_raw_read (regcache, gpnum % 4, raw_buf);
3585 /* ... Modify ... (always little endian). */
3587 memcpy (raw_buf + 1, buf, 1);
3589 memcpy (raw_buf, buf, 1);
3591 regcache_raw_write (regcache, gpnum % 4, raw_buf);
3594 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3598 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
3601 i386_ax_pseudo_register_collect (struct gdbarch *gdbarch,
3602 struct agent_expr *ax, int regnum)
3604 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3606 if (i386_mmx_regnum_p (gdbarch, regnum))
3608 /* MMX to FPU register mapping depends on current TOS. Let's just
3609 not care and collect everything... */
3612 ax_reg_mask (ax, I387_FSTAT_REGNUM (tdep));
3613 for (i = 0; i < 8; i++)
3614 ax_reg_mask (ax, I387_ST0_REGNUM (tdep) + i);
3617 else if (i386_bnd_regnum_p (gdbarch, regnum))
3619 regnum -= tdep->bnd0_regnum;
3620 ax_reg_mask (ax, I387_BND0R_REGNUM (tdep) + regnum);
3623 else if (i386_k_regnum_p (gdbarch, regnum))
3625 regnum -= tdep->k0_regnum;
3626 ax_reg_mask (ax, tdep->k0_regnum + regnum);
3629 else if (i386_zmm_regnum_p (gdbarch, regnum))
3631 regnum -= tdep->zmm0_regnum;
3632 if (regnum < num_lower_zmm_regs)
3634 ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum);
3635 ax_reg_mask (ax, tdep->ymm0h_regnum + regnum);
3639 ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum
3640 - num_lower_zmm_regs);
3641 ax_reg_mask (ax, I387_YMM16H_REGNUM (tdep) + regnum
3642 - num_lower_zmm_regs);
3644 ax_reg_mask (ax, tdep->zmm0h_regnum + regnum);
3647 else if (i386_ymm_regnum_p (gdbarch, regnum))
3649 regnum -= tdep->ymm0_regnum;
3650 ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum);
3651 ax_reg_mask (ax, tdep->ymm0h_regnum + regnum);
3654 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3656 regnum -= tdep->ymm16_regnum;
3657 ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum);
3658 ax_reg_mask (ax, tdep->ymm16h_regnum + regnum);
3661 else if (i386_word_regnum_p (gdbarch, regnum))
3663 int gpnum = regnum - tdep->ax_regnum;
3665 ax_reg_mask (ax, gpnum);
3668 else if (i386_byte_regnum_p (gdbarch, regnum))
3670 int gpnum = regnum - tdep->al_regnum;
3672 ax_reg_mask (ax, gpnum % 4);
3676 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3681 /* Return the register number of the register allocated by GCC after
3682 REGNUM, or -1 if there is no such register. */
3685 i386_next_regnum (int regnum)
3687 /* GCC allocates the registers in the order:
3689 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3691 Since storing a variable in %esp doesn't make any sense we return
3692 -1 for %ebp and for %esp itself. */
3693 static int next_regnum[] =
3695 I386_EDX_REGNUM, /* Slot for %eax. */
3696 I386_EBX_REGNUM, /* Slot for %ecx. */
3697 I386_ECX_REGNUM, /* Slot for %edx. */
3698 I386_ESI_REGNUM, /* Slot for %ebx. */
3699 -1, -1, /* Slots for %esp and %ebp. */
3700 I386_EDI_REGNUM, /* Slot for %esi. */
3701 I386_EBP_REGNUM /* Slot for %edi. */
3704 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
3705 return next_regnum[regnum];
3710 /* Return nonzero if a value of type TYPE stored in register REGNUM
3711 needs any special handling. */
3714 i386_convert_register_p (struct gdbarch *gdbarch,
3715 int regnum, struct type *type)
3717 int len = TYPE_LENGTH (type);
3719 /* Values may be spread across multiple registers. Most debugging
3720 formats aren't expressive enough to specify the locations, so
3721 some heuristics is involved. Right now we only handle types that
3722 have a length that is a multiple of the word size, since GCC
3723 doesn't seem to put any other types into registers. */
3724 if (len > 4 && len % 4 == 0)
3726 int last_regnum = regnum;
3730 last_regnum = i386_next_regnum (last_regnum);
3734 if (last_regnum != -1)
3738 return i387_convert_register_p (gdbarch, regnum, type);
3741 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3742 return its contents in TO. */
3745 i386_register_to_value (struct frame_info *frame, int regnum,
3746 struct type *type, gdb_byte *to,
3747 int *optimizedp, int *unavailablep)
3749 struct gdbarch *gdbarch = get_frame_arch (frame);
3750 int len = TYPE_LENGTH (type);
3752 if (i386_fp_regnum_p (gdbarch, regnum))
3753 return i387_register_to_value (frame, regnum, type, to,
3754 optimizedp, unavailablep);
3756 /* Read a value spread across multiple registers. */
3758 gdb_assert (len > 4 && len % 4 == 0);
3762 gdb_assert (regnum != -1);
3763 gdb_assert (register_size (gdbarch, regnum) == 4);
3765 if (!get_frame_register_bytes (frame, regnum, 0,
3766 register_size (gdbarch, regnum),
3767 to, optimizedp, unavailablep))
3770 regnum = i386_next_regnum (regnum);
3775 *optimizedp = *unavailablep = 0;
3779 /* Write the contents FROM of a value of type TYPE into register
3780 REGNUM in frame FRAME. */
3783 i386_value_to_register (struct frame_info *frame, int regnum,
3784 struct type *type, const gdb_byte *from)
3786 int len = TYPE_LENGTH (type);
3788 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
3790 i387_value_to_register (frame, regnum, type, from);
3794 /* Write a value spread across multiple registers. */
3796 gdb_assert (len > 4 && len % 4 == 0);
3800 gdb_assert (regnum != -1);
3801 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
3803 put_frame_register (frame, regnum, from);
3804 regnum = i386_next_regnum (regnum);
3810 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3811 in the general-purpose register set REGSET to register cache
3812 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3815 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
3816 int regnum, const void *gregs, size_t len)
3818 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3819 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3820 const gdb_byte *regs = (const gdb_byte *) gregs;
3823 gdb_assert (len >= tdep->sizeof_gregset);
3825 for (i = 0; i < tdep->gregset_num_regs; i++)
3827 if ((regnum == i || regnum == -1)
3828 && tdep->gregset_reg_offset[i] != -1)
3829 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
3833 /* Collect register REGNUM from the register cache REGCACHE and store
3834 it in the buffer specified by GREGS and LEN as described by the
3835 general-purpose register set REGSET. If REGNUM is -1, do this for
3836 all registers in REGSET. */
3839 i386_collect_gregset (const struct regset *regset,
3840 const struct regcache *regcache,
3841 int regnum, void *gregs, size_t len)
3843 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3844 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3845 gdb_byte *regs = (gdb_byte *) gregs;
3848 gdb_assert (len >= tdep->sizeof_gregset);
3850 for (i = 0; i < tdep->gregset_num_regs; i++)
3852 if ((regnum == i || regnum == -1)
3853 && tdep->gregset_reg_offset[i] != -1)
3854 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
3858 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3859 in the floating-point register set REGSET to register cache
3860 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3863 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
3864 int regnum, const void *fpregs, size_t len)
3866 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3867 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3869 if (len == I387_SIZEOF_FXSAVE)
3871 i387_supply_fxsave (regcache, regnum, fpregs);
3875 gdb_assert (len >= tdep->sizeof_fpregset);
3876 i387_supply_fsave (regcache, regnum, fpregs);
3879 /* Collect register REGNUM from the register cache REGCACHE and store
3880 it in the buffer specified by FPREGS and LEN as described by the
3881 floating-point register set REGSET. If REGNUM is -1, do this for
3882 all registers in REGSET. */
3885 i386_collect_fpregset (const struct regset *regset,
3886 const struct regcache *regcache,
3887 int regnum, void *fpregs, size_t len)
3889 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3890 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3892 if (len == I387_SIZEOF_FXSAVE)
3894 i387_collect_fxsave (regcache, regnum, fpregs);
3898 gdb_assert (len >= tdep->sizeof_fpregset);
3899 i387_collect_fsave (regcache, regnum, fpregs);
3902 /* Register set definitions. */
3904 const struct regset i386_gregset =
3906 NULL, i386_supply_gregset, i386_collect_gregset
3909 const struct regset i386_fpregset =
3911 NULL, i386_supply_fpregset, i386_collect_fpregset
3914 /* Default iterator over core file register note sections. */
3917 i386_iterate_over_regset_sections (struct gdbarch *gdbarch,
3918 iterate_over_regset_sections_cb *cb,
3920 const struct regcache *regcache)
3922 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3924 cb (".reg", tdep->sizeof_gregset, &i386_gregset, NULL, cb_data);
3925 if (tdep->sizeof_fpregset)
3926 cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
3930 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3933 i386_pe_skip_trampoline_code (struct frame_info *frame,
3934 CORE_ADDR pc, char *name)
3936 struct gdbarch *gdbarch = get_frame_arch (frame);
3937 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3940 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
3942 unsigned long indirect =
3943 read_memory_unsigned_integer (pc + 2, 4, byte_order);
3944 struct minimal_symbol *indsym =
3945 indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0;
3946 const char *symname = indsym ? MSYMBOL_LINKAGE_NAME (indsym) : 0;
3950 if (startswith (symname, "__imp_")
3951 || startswith (symname, "_imp_"))
3953 read_memory_unsigned_integer (indirect, 4, byte_order);
3956 return 0; /* Not a trampoline. */
3960 /* Return whether the THIS_FRAME corresponds to a sigtramp
3964 i386_sigtramp_p (struct frame_info *this_frame)
3966 CORE_ADDR pc = get_frame_pc (this_frame);
3969 find_pc_partial_function (pc, &name, NULL, NULL);
3970 return (name && strcmp ("_sigtramp", name) == 0);
3974 /* We have two flavours of disassembly. The machinery on this page
3975 deals with switching between those. */
3978 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
3980 gdb_assert (disassembly_flavor == att_flavor
3981 || disassembly_flavor == intel_flavor);
3983 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3984 constified, cast to prevent a compiler warning. */
3985 info->disassembler_options = (char *) disassembly_flavor;
3987 return print_insn_i386 (pc, info);
3991 /* There are a few i386 architecture variants that differ only
3992 slightly from the generic i386 target. For now, we don't give them
3993 their own source file, but include them here. As a consequence,
3994 they'll always be included. */
3996 /* System V Release 4 (SVR4). */
3998 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
4002 i386_svr4_sigtramp_p (struct frame_info *this_frame)
4004 CORE_ADDR pc = get_frame_pc (this_frame);
4007 /* The origin of these symbols is currently unknown. */
4008 find_pc_partial_function (pc, &name, NULL, NULL);
4009 return (name && (strcmp ("_sigreturn", name) == 0
4010 || strcmp ("sigvechandler", name) == 0));
4013 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
4014 address of the associated sigcontext (ucontext) structure. */
4017 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
4019 struct gdbarch *gdbarch = get_frame_arch (this_frame);
4020 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4024 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
4025 sp = extract_unsigned_integer (buf, 4, byte_order);
4027 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
4032 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
4036 i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s)
4038 return (*s == '$' /* Literal number. */
4039 || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */
4040 || (*s == '(' && s[1] == '%') /* Register indirection. */
4041 || (*s == '%' && isalpha (s[1]))); /* Register access. */
4044 /* Helper function for i386_stap_parse_special_token.
4046 This function parses operands of the form `-8+3+1(%rbp)', which
4047 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
4049 Return 1 if the operand was parsed successfully, zero
4053 i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch,
4054 struct stap_parse_info *p)
4056 const char *s = p->arg;
4058 if (isdigit (*s) || *s == '-' || *s == '+')
4062 long displacements[3];
4078 if (!isdigit ((unsigned char) *s))
4081 displacements[0] = strtol (s, &endp, 10);
4084 if (*s != '+' && *s != '-')
4086 /* We are not dealing with a triplet. */
4099 if (!isdigit ((unsigned char) *s))
4102 displacements[1] = strtol (s, &endp, 10);
4105 if (*s != '+' && *s != '-')
4107 /* We are not dealing with a triplet. */
4120 if (!isdigit ((unsigned char) *s))
4123 displacements[2] = strtol (s, &endp, 10);
4126 if (*s != '(' || s[1] != '%')
4132 while (isalnum (*s))
4138 len = s - start - 1;
4139 regname = (char *) alloca (len + 1);
4141 strncpy (regname, start, len);
4142 regname[len] = '\0';
4144 if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1)
4145 error (_("Invalid register name `%s' on expression `%s'."),
4146 regname, p->saved_arg);
4148 for (i = 0; i < 3; i++)
4150 write_exp_elt_opcode (&p->pstate, OP_LONG);
4152 (&p->pstate, builtin_type (gdbarch)->builtin_long);
4153 write_exp_elt_longcst (&p->pstate, displacements[i]);
4154 write_exp_elt_opcode (&p->pstate, OP_LONG);
4156 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4159 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4162 write_exp_string (&p->pstate, str);
4163 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4165 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4166 write_exp_elt_type (&p->pstate,
4167 builtin_type (gdbarch)->builtin_data_ptr);
4168 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4170 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4171 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4172 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4174 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4175 write_exp_elt_type (&p->pstate,
4176 lookup_pointer_type (p->arg_type));
4177 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4179 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4189 /* Helper function for i386_stap_parse_special_token.
4191 This function parses operands of the form `register base +
4192 (register index * size) + offset', as represented in
4193 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4195 Return 1 if the operand was parsed successfully, zero
4199 i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch,
4200 struct stap_parse_info *p)
4202 const char *s = p->arg;
4204 if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+')
4206 int offset_minus = 0;
4215 struct stoken base_token, index_token;
4225 if (offset_minus && !isdigit (*s))
4232 offset = strtol (s, &endp, 10);
4236 if (*s != '(' || s[1] != '%')
4242 while (isalnum (*s))
4245 if (*s != ',' || s[1] != '%')
4248 len_base = s - start;
4249 base = (char *) alloca (len_base + 1);
4250 strncpy (base, start, len_base);
4251 base[len_base] = '\0';
4253 if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1)
4254 error (_("Invalid register name `%s' on expression `%s'."),
4255 base, p->saved_arg);
4260 while (isalnum (*s))
4263 len_index = s - start;
4264 index = (char *) alloca (len_index + 1);
4265 strncpy (index, start, len_index);
4266 index[len_index] = '\0';
4268 if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1)
4269 error (_("Invalid register name `%s' on expression `%s'."),
4270 index, p->saved_arg);
4272 if (*s != ',' && *s != ')')
4288 size = strtol (s, &endp, 10);
4299 write_exp_elt_opcode (&p->pstate, OP_LONG);
4300 write_exp_elt_type (&p->pstate,
4301 builtin_type (gdbarch)->builtin_long);
4302 write_exp_elt_longcst (&p->pstate, offset);
4303 write_exp_elt_opcode (&p->pstate, OP_LONG);
4305 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4308 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4309 base_token.ptr = base;
4310 base_token.length = len_base;
4311 write_exp_string (&p->pstate, base_token);
4312 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4315 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4317 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4318 index_token.ptr = index;
4319 index_token.length = len_index;
4320 write_exp_string (&p->pstate, index_token);
4321 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4325 write_exp_elt_opcode (&p->pstate, OP_LONG);
4326 write_exp_elt_type (&p->pstate,
4327 builtin_type (gdbarch)->builtin_long);
4328 write_exp_elt_longcst (&p->pstate, size);
4329 write_exp_elt_opcode (&p->pstate, OP_LONG);
4331 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4332 write_exp_elt_opcode (&p->pstate, BINOP_MUL);
4335 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4337 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4338 write_exp_elt_type (&p->pstate,
4339 lookup_pointer_type (p->arg_type));
4340 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4342 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4352 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4356 i386_stap_parse_special_token (struct gdbarch *gdbarch,
4357 struct stap_parse_info *p)
4359 /* In order to parse special tokens, we use a state-machine that go
4360 through every known token and try to get a match. */
4364 THREE_ARG_DISPLACEMENT,
4369 current_state = TRIPLET;
4371 /* The special tokens to be parsed here are:
4373 - `register base + (register index * size) + offset', as represented
4374 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4376 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4377 `*(-8 + 3 - 1 + (void *) $eax)'. */
4379 while (current_state != DONE)
4381 switch (current_state)
4384 if (i386_stap_parse_special_token_triplet (gdbarch, p))
4388 case THREE_ARG_DISPLACEMENT:
4389 if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p))
4394 /* Advancing to the next state. */
4403 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always
4404 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */
4407 i386_gnu_triplet_regexp (struct gdbarch *gdbarch)
4409 return "(x86_64|i.86)";
4417 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4419 static const char *const stap_integer_prefixes[] = { "$", NULL };
4420 static const char *const stap_register_prefixes[] = { "%", NULL };
4421 static const char *const stap_register_indirection_prefixes[] = { "(",
4423 static const char *const stap_register_indirection_suffixes[] = { ")",
4426 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4427 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4429 /* Registering SystemTap handlers. */
4430 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
4431 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
4432 set_gdbarch_stap_register_indirection_prefixes (gdbarch,
4433 stap_register_indirection_prefixes);
4434 set_gdbarch_stap_register_indirection_suffixes (gdbarch,
4435 stap_register_indirection_suffixes);
4436 set_gdbarch_stap_is_single_operand (gdbarch,
4437 i386_stap_is_single_operand);
4438 set_gdbarch_stap_parse_special_token (gdbarch,
4439 i386_stap_parse_special_token);
4441 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
4444 /* System V Release 4 (SVR4). */
4447 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4449 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4451 /* System V Release 4 uses ELF. */
4452 i386_elf_init_abi (info, gdbarch);
4454 /* System V Release 4 has shared libraries. */
4455 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
4457 tdep->sigtramp_p = i386_svr4_sigtramp_p;
4458 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
4459 tdep->sc_pc_offset = 36 + 14 * 4;
4460 tdep->sc_sp_offset = 36 + 17 * 4;
4462 tdep->jb_pc_offset = 20;
4468 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4470 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4472 /* DJGPP doesn't have any special frames for signal handlers. */
4473 tdep->sigtramp_p = NULL;
4475 tdep->jb_pc_offset = 36;
4477 /* DJGPP does not support the SSE registers. */
4478 if (! tdesc_has_registers (info.target_desc))
4479 tdep->tdesc = tdesc_i386_mmx;
4481 /* Native compiler is GCC, which uses the SVR4 register numbering
4482 even in COFF and STABS. See the comment in i386_gdbarch_init,
4483 before the calls to set_gdbarch_stab_reg_to_regnum and
4484 set_gdbarch_sdb_reg_to_regnum. */
4485 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4486 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4488 set_gdbarch_has_dos_based_file_system (gdbarch, 1);
4490 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
4494 /* i386 register groups. In addition to the normal groups, add "mmx"
4497 static struct reggroup *i386_sse_reggroup;
4498 static struct reggroup *i386_mmx_reggroup;
4501 i386_init_reggroups (void)
4503 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
4504 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
4508 i386_add_reggroups (struct gdbarch *gdbarch)
4510 reggroup_add (gdbarch, i386_sse_reggroup);
4511 reggroup_add (gdbarch, i386_mmx_reggroup);
4512 reggroup_add (gdbarch, general_reggroup);
4513 reggroup_add (gdbarch, float_reggroup);
4514 reggroup_add (gdbarch, all_reggroup);
4515 reggroup_add (gdbarch, save_reggroup);
4516 reggroup_add (gdbarch, restore_reggroup);
4517 reggroup_add (gdbarch, vector_reggroup);
4518 reggroup_add (gdbarch, system_reggroup);
4522 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
4523 struct reggroup *group)
4525 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4526 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
4527 ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p,
4528 bndr_regnum_p, bnd_regnum_p, k_regnum_p, zmm_regnum_p, zmmh_regnum_p,
4529 zmm_avx512_regnum_p, mpx_ctrl_regnum_p, xmm_avx512_regnum_p,
4530 avx512_p, avx_p, sse_p;
4532 /* Don't include pseudo registers, except for MMX, in any register
4534 if (i386_byte_regnum_p (gdbarch, regnum))
4537 if (i386_word_regnum_p (gdbarch, regnum))
4540 if (i386_dword_regnum_p (gdbarch, regnum))
4543 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
4544 if (group == i386_mmx_reggroup)
4545 return mmx_regnum_p;
4547 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
4548 xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum);
4549 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
4550 if (group == i386_sse_reggroup)
4551 return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p;
4553 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
4554 ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum);
4555 zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum);
4557 avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4558 == X86_XSTATE_AVX512_MASK);
4559 avx_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4560 == X86_XSTATE_AVX_MASK) && !avx512_p;
4561 sse_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4562 == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p;
4564 if (group == vector_reggroup)
4565 return (mmx_regnum_p
4566 || (zmm_regnum_p && avx512_p)
4567 || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p)
4568 || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p)
4571 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
4572 || i386_fpc_regnum_p (gdbarch, regnum));
4573 if (group == float_reggroup)
4576 /* For "info reg all", don't include upper YMM registers nor XMM
4577 registers when AVX is supported. */
4578 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
4579 ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum);
4580 zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum);
4581 if (group == all_reggroup
4582 && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p)
4583 || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p)
4585 || ymmh_avx512_regnum_p
4589 bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum);
4590 if (group == all_reggroup
4591 && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4592 return bnd_regnum_p;
4594 bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum);
4595 if (group == all_reggroup
4596 && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4599 mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum);
4600 if (group == all_reggroup
4601 && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4602 return mpx_ctrl_regnum_p;
4604 if (group == general_reggroup)
4605 return (!fp_regnum_p
4609 && !xmm_avx512_regnum_p
4612 && !ymm_avx512_regnum_p
4613 && !ymmh_avx512_regnum_p
4616 && !mpx_ctrl_regnum_p
4620 return default_register_reggroup_p (gdbarch, regnum, group);
4624 /* Get the ARGIth function argument for the current function. */
4627 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
4630 struct gdbarch *gdbarch = get_frame_arch (frame);
4631 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4632 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
4633 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
4636 #define PREFIX_REPZ 0x01
4637 #define PREFIX_REPNZ 0x02
4638 #define PREFIX_LOCK 0x04
4639 #define PREFIX_DATA 0x08
4640 #define PREFIX_ADDR 0x10
4652 /* i386 arith/logic operations */
4665 struct i386_record_s
4667 struct gdbarch *gdbarch;
4668 struct regcache *regcache;
4669 CORE_ADDR orig_addr;
4675 uint8_t mod, reg, rm;
4684 /* Parse the "modrm" part of the memory address irp->addr points at.
4685 Returns -1 if something goes wrong, 0 otherwise. */
4688 i386_record_modrm (struct i386_record_s *irp)
4690 struct gdbarch *gdbarch = irp->gdbarch;
4692 if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1))
4696 irp->mod = (irp->modrm >> 6) & 3;
4697 irp->reg = (irp->modrm >> 3) & 7;
4698 irp->rm = irp->modrm & 7;
4703 /* Extract the memory address that the current instruction writes to,
4704 and return it in *ADDR. Return -1 if something goes wrong. */
4707 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
4709 struct gdbarch *gdbarch = irp->gdbarch;
4710 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4715 if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM])
4722 uint8_t base = irp->rm;
4727 if (record_read_memory (gdbarch, irp->addr, &byte, 1))
4730 scale = (byte >> 6) & 3;
4731 index = ((byte >> 3) & 7) | irp->rex_x;
4739 if ((base & 7) == 5)
4742 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4745 *addr = extract_signed_integer (buf, 4, byte_order);
4746 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
4747 *addr += irp->addr + irp->rip_offset;
4751 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4754 *addr = (int8_t) buf[0];
4757 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4759 *addr = extract_signed_integer (buf, 4, byte_order);
4767 if (base == 4 && irp->popl_esp_hack)
4768 *addr += irp->popl_esp_hack;
4769 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
4772 if (irp->aflag == 2)
4777 *addr = (uint32_t) (offset64 + *addr);
4779 if (havesib && (index != 4 || scale != 0))
4781 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
4783 if (irp->aflag == 2)
4784 *addr += offset64 << scale;
4786 *addr = (uint32_t) (*addr + (offset64 << scale));
4791 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4792 address from 32-bit to 64-bit. */
4793 *addr = (uint32_t) *addr;
4804 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4807 *addr = extract_signed_integer (buf, 2, byte_order);
4813 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4816 *addr = (int8_t) buf[0];
4819 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4822 *addr = extract_signed_integer (buf, 2, byte_order);
4829 regcache_raw_read_unsigned (irp->regcache,
4830 irp->regmap[X86_RECORD_REBX_REGNUM],
4832 *addr = (uint32_t) (*addr + offset64);
4833 regcache_raw_read_unsigned (irp->regcache,
4834 irp->regmap[X86_RECORD_RESI_REGNUM],
4836 *addr = (uint32_t) (*addr + offset64);
4839 regcache_raw_read_unsigned (irp->regcache,
4840 irp->regmap[X86_RECORD_REBX_REGNUM],
4842 *addr = (uint32_t) (*addr + offset64);
4843 regcache_raw_read_unsigned (irp->regcache,
4844 irp->regmap[X86_RECORD_REDI_REGNUM],
4846 *addr = (uint32_t) (*addr + offset64);
4849 regcache_raw_read_unsigned (irp->regcache,
4850 irp->regmap[X86_RECORD_REBP_REGNUM],
4852 *addr = (uint32_t) (*addr + offset64);
4853 regcache_raw_read_unsigned (irp->regcache,
4854 irp->regmap[X86_RECORD_RESI_REGNUM],
4856 *addr = (uint32_t) (*addr + offset64);
4859 regcache_raw_read_unsigned (irp->regcache,
4860 irp->regmap[X86_RECORD_REBP_REGNUM],
4862 *addr = (uint32_t) (*addr + offset64);
4863 regcache_raw_read_unsigned (irp->regcache,
4864 irp->regmap[X86_RECORD_REDI_REGNUM],
4866 *addr = (uint32_t) (*addr + offset64);
4869 regcache_raw_read_unsigned (irp->regcache,
4870 irp->regmap[X86_RECORD_RESI_REGNUM],
4872 *addr = (uint32_t) (*addr + offset64);
4875 regcache_raw_read_unsigned (irp->regcache,
4876 irp->regmap[X86_RECORD_REDI_REGNUM],
4878 *addr = (uint32_t) (*addr + offset64);
4881 regcache_raw_read_unsigned (irp->regcache,
4882 irp->regmap[X86_RECORD_REBP_REGNUM],
4884 *addr = (uint32_t) (*addr + offset64);
4887 regcache_raw_read_unsigned (irp->regcache,
4888 irp->regmap[X86_RECORD_REBX_REGNUM],
4890 *addr = (uint32_t) (*addr + offset64);
4900 /* Record the address and contents of the memory that will be changed
4901 by the current instruction. Return -1 if something goes wrong, 0
4905 i386_record_lea_modrm (struct i386_record_s *irp)
4907 struct gdbarch *gdbarch = irp->gdbarch;
4910 if (irp->override >= 0)
4912 if (record_full_memory_query)
4915 Process record ignores the memory change of instruction at address %s\n\
4916 because it can't get the value of the segment register.\n\
4917 Do you want to stop the program?"),
4918 paddress (gdbarch, irp->orig_addr)))
4925 if (i386_record_lea_modrm_addr (irp, &addr))
4928 if (record_full_arch_list_add_mem (addr, 1 << irp->ot))
4934 /* Record the effects of a push operation. Return -1 if something
4935 goes wrong, 0 otherwise. */
4938 i386_record_push (struct i386_record_s *irp, int size)
4942 if (record_full_arch_list_add_reg (irp->regcache,
4943 irp->regmap[X86_RECORD_RESP_REGNUM]))
4945 regcache_raw_read_unsigned (irp->regcache,
4946 irp->regmap[X86_RECORD_RESP_REGNUM],
4948 if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size))
4955 /* Defines contents to record. */
4956 #define I386_SAVE_FPU_REGS 0xfffd
4957 #define I386_SAVE_FPU_ENV 0xfffe
4958 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4960 /* Record the values of the floating point registers which will be
4961 changed by the current instruction. Returns -1 if something is
4962 wrong, 0 otherwise. */
4964 static int i386_record_floats (struct gdbarch *gdbarch,
4965 struct i386_record_s *ir,
4968 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4971 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4972 happen. Currently we store st0-st7 registers, but we need not store all
4973 registers all the time, in future we use ftag register and record only
4974 those who are not marked as an empty. */
4976 if (I386_SAVE_FPU_REGS == iregnum)
4978 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
4980 if (record_full_arch_list_add_reg (ir->regcache, i))
4984 else if (I386_SAVE_FPU_ENV == iregnum)
4986 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4988 if (record_full_arch_list_add_reg (ir->regcache, i))
4992 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
4994 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4996 if (record_full_arch_list_add_reg (ir->regcache, i))
5000 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
5001 (iregnum <= I387_FOP_REGNUM (tdep)))
5003 if (record_full_arch_list_add_reg (ir->regcache,iregnum))
5008 /* Parameter error. */
5011 if(I386_SAVE_FPU_ENV != iregnum)
5013 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
5015 if (record_full_arch_list_add_reg (ir->regcache, i))
5022 /* Parse the current instruction, and record the values of the
5023 registers and memory that will be changed by the current
5024 instruction. Returns -1 if something goes wrong, 0 otherwise. */
5026 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
5027 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
5030 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
5031 CORE_ADDR input_addr)
5033 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5039 gdb_byte buf[MAX_REGISTER_SIZE];
5040 struct i386_record_s ir;
5041 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5045 memset (&ir, 0, sizeof (struct i386_record_s));
5046 ir.regcache = regcache;
5047 ir.addr = input_addr;
5048 ir.orig_addr = input_addr;
5052 ir.popl_esp_hack = 0;
5053 ir.regmap = tdep->record_regmap;
5054 ir.gdbarch = gdbarch;
5056 if (record_debug > 1)
5057 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
5059 paddress (gdbarch, ir.addr));
5064 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5067 switch (opcode8) /* Instruction prefixes */
5069 case REPE_PREFIX_OPCODE:
5070 prefixes |= PREFIX_REPZ;
5072 case REPNE_PREFIX_OPCODE:
5073 prefixes |= PREFIX_REPNZ;
5075 case LOCK_PREFIX_OPCODE:
5076 prefixes |= PREFIX_LOCK;
5078 case CS_PREFIX_OPCODE:
5079 ir.override = X86_RECORD_CS_REGNUM;
5081 case SS_PREFIX_OPCODE:
5082 ir.override = X86_RECORD_SS_REGNUM;
5084 case DS_PREFIX_OPCODE:
5085 ir.override = X86_RECORD_DS_REGNUM;
5087 case ES_PREFIX_OPCODE:
5088 ir.override = X86_RECORD_ES_REGNUM;
5090 case FS_PREFIX_OPCODE:
5091 ir.override = X86_RECORD_FS_REGNUM;
5093 case GS_PREFIX_OPCODE:
5094 ir.override = X86_RECORD_GS_REGNUM;
5096 case DATA_PREFIX_OPCODE:
5097 prefixes |= PREFIX_DATA;
5099 case ADDR_PREFIX_OPCODE:
5100 prefixes |= PREFIX_ADDR;
5102 case 0x40: /* i386 inc %eax */
5103 case 0x41: /* i386 inc %ecx */
5104 case 0x42: /* i386 inc %edx */
5105 case 0x43: /* i386 inc %ebx */
5106 case 0x44: /* i386 inc %esp */
5107 case 0x45: /* i386 inc %ebp */
5108 case 0x46: /* i386 inc %esi */
5109 case 0x47: /* i386 inc %edi */
5110 case 0x48: /* i386 dec %eax */
5111 case 0x49: /* i386 dec %ecx */
5112 case 0x4a: /* i386 dec %edx */
5113 case 0x4b: /* i386 dec %ebx */
5114 case 0x4c: /* i386 dec %esp */
5115 case 0x4d: /* i386 dec %ebp */
5116 case 0x4e: /* i386 dec %esi */
5117 case 0x4f: /* i386 dec %edi */
5118 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
5121 rex_w = (opcode8 >> 3) & 1;
5122 rex_r = (opcode8 & 0x4) << 1;
5123 ir.rex_x = (opcode8 & 0x2) << 2;
5124 ir.rex_b = (opcode8 & 0x1) << 3;
5126 else /* 32 bit target */
5135 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
5141 if (prefixes & PREFIX_DATA)
5144 if (prefixes & PREFIX_ADDR)
5146 else if (ir.regmap[X86_RECORD_R8_REGNUM])
5149 /* Now check op code. */
5150 opcode = (uint32_t) opcode8;
5155 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5158 opcode = (uint32_t) opcode8 | 0x0f00;
5162 case 0x00: /* arith & logic */
5210 if (((opcode >> 3) & 7) != OP_CMPL)
5212 if ((opcode & 1) == 0)
5215 ir.ot = ir.dflag + OT_WORD;
5217 switch ((opcode >> 1) & 3)
5219 case 0: /* OP Ev, Gv */
5220 if (i386_record_modrm (&ir))
5224 if (i386_record_lea_modrm (&ir))
5230 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5232 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5235 case 1: /* OP Gv, Ev */
5236 if (i386_record_modrm (&ir))
5239 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5241 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5243 case 2: /* OP A, Iv */
5244 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5248 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5251 case 0x80: /* GRP1 */
5255 if (i386_record_modrm (&ir))
5258 if (ir.reg != OP_CMPL)
5260 if ((opcode & 1) == 0)
5263 ir.ot = ir.dflag + OT_WORD;
5270 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5271 if (i386_record_lea_modrm (&ir))
5275 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5277 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5280 case 0x40: /* inc */
5289 case 0x48: /* dec */
5298 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7);
5299 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5302 case 0xf6: /* GRP3 */
5304 if ((opcode & 1) == 0)
5307 ir.ot = ir.dflag + OT_WORD;
5308 if (i386_record_modrm (&ir))
5311 if (ir.mod != 3 && ir.reg == 0)
5312 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5317 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5323 if (i386_record_lea_modrm (&ir))
5329 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5331 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5333 if (ir.reg == 3) /* neg */
5334 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5340 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5341 if (ir.ot != OT_BYTE)
5342 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5343 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5347 opcode = opcode << 8 | ir.modrm;
5353 case 0xfe: /* GRP4 */
5354 case 0xff: /* GRP5 */
5355 if (i386_record_modrm (&ir))
5357 if (ir.reg >= 2 && opcode == 0xfe)
5360 opcode = opcode << 8 | ir.modrm;
5367 if ((opcode & 1) == 0)
5370 ir.ot = ir.dflag + OT_WORD;
5373 if (i386_record_lea_modrm (&ir))
5379 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5381 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5383 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5386 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5388 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5390 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5393 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5394 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5396 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5400 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5403 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5405 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5410 opcode = opcode << 8 | ir.modrm;
5416 case 0x84: /* test */
5420 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5423 case 0x98: /* CWDE/CBW */
5424 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5427 case 0x99: /* CDQ/CWD */
5428 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5429 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5432 case 0x0faf: /* imul */
5435 ir.ot = ir.dflag + OT_WORD;
5436 if (i386_record_modrm (&ir))
5439 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5440 else if (opcode == 0x6b)
5443 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5445 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5446 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5449 case 0x0fc0: /* xadd */
5451 if ((opcode & 1) == 0)
5454 ir.ot = ir.dflag + OT_WORD;
5455 if (i386_record_modrm (&ir))
5460 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5462 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5463 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5465 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5469 if (i386_record_lea_modrm (&ir))
5471 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5473 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5475 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5478 case 0x0fb0: /* cmpxchg */
5480 if ((opcode & 1) == 0)
5483 ir.ot = ir.dflag + OT_WORD;
5484 if (i386_record_modrm (&ir))
5489 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5490 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5492 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5496 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5497 if (i386_record_lea_modrm (&ir))
5500 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5503 case 0x0fc7: /* cmpxchg8b */
5504 if (i386_record_modrm (&ir))
5509 opcode = opcode << 8 | ir.modrm;
5512 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5513 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5514 if (i386_record_lea_modrm (&ir))
5516 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5519 case 0x50: /* push */
5529 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5531 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5535 case 0x06: /* push es */
5536 case 0x0e: /* push cs */
5537 case 0x16: /* push ss */
5538 case 0x1e: /* push ds */
5539 if (ir.regmap[X86_RECORD_R8_REGNUM])
5544 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5548 case 0x0fa0: /* push fs */
5549 case 0x0fa8: /* push gs */
5550 if (ir.regmap[X86_RECORD_R8_REGNUM])
5555 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5559 case 0x60: /* pusha */
5560 if (ir.regmap[X86_RECORD_R8_REGNUM])
5565 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
5569 case 0x58: /* pop */
5577 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5578 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5581 case 0x61: /* popa */
5582 if (ir.regmap[X86_RECORD_R8_REGNUM])
5587 for (regnum = X86_RECORD_REAX_REGNUM;
5588 regnum <= X86_RECORD_REDI_REGNUM;
5590 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5593 case 0x8f: /* pop */
5594 if (ir.regmap[X86_RECORD_R8_REGNUM])
5595 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
5597 ir.ot = ir.dflag + OT_WORD;
5598 if (i386_record_modrm (&ir))
5601 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5604 ir.popl_esp_hack = 1 << ir.ot;
5605 if (i386_record_lea_modrm (&ir))
5608 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5611 case 0xc8: /* enter */
5612 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5613 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5615 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5619 case 0xc9: /* leave */
5620 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5621 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5624 case 0x07: /* pop es */
5625 if (ir.regmap[X86_RECORD_R8_REGNUM])
5630 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5631 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
5632 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5635 case 0x17: /* pop ss */
5636 if (ir.regmap[X86_RECORD_R8_REGNUM])
5641 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5642 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
5643 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5646 case 0x1f: /* pop ds */
5647 if (ir.regmap[X86_RECORD_R8_REGNUM])
5652 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5653 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
5654 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5657 case 0x0fa1: /* pop fs */
5658 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5659 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
5660 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5663 case 0x0fa9: /* pop gs */
5664 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5665 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
5666 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5669 case 0x88: /* mov */
5673 if ((opcode & 1) == 0)
5676 ir.ot = ir.dflag + OT_WORD;
5678 if (i386_record_modrm (&ir))
5683 if (opcode == 0xc6 || opcode == 0xc7)
5684 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5685 if (i386_record_lea_modrm (&ir))
5690 if (opcode == 0xc6 || opcode == 0xc7)
5692 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5694 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5698 case 0x8a: /* mov */
5700 if ((opcode & 1) == 0)
5703 ir.ot = ir.dflag + OT_WORD;
5704 if (i386_record_modrm (&ir))
5707 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5709 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5712 case 0x8c: /* mov seg */
5713 if (i386_record_modrm (&ir))
5718 opcode = opcode << 8 | ir.modrm;
5723 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5727 if (i386_record_lea_modrm (&ir))
5732 case 0x8e: /* mov seg */
5733 if (i386_record_modrm (&ir))
5738 regnum = X86_RECORD_ES_REGNUM;
5741 regnum = X86_RECORD_SS_REGNUM;
5744 regnum = X86_RECORD_DS_REGNUM;
5747 regnum = X86_RECORD_FS_REGNUM;
5750 regnum = X86_RECORD_GS_REGNUM;
5754 opcode = opcode << 8 | ir.modrm;
5758 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5759 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5762 case 0x0fb6: /* movzbS */
5763 case 0x0fb7: /* movzwS */
5764 case 0x0fbe: /* movsbS */
5765 case 0x0fbf: /* movswS */
5766 if (i386_record_modrm (&ir))
5768 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5771 case 0x8d: /* lea */
5772 if (i386_record_modrm (&ir))
5777 opcode = opcode << 8 | ir.modrm;
5782 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5784 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5787 case 0xa0: /* mov EAX */
5790 case 0xd7: /* xlat */
5791 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5794 case 0xa2: /* mov EAX */
5796 if (ir.override >= 0)
5798 if (record_full_memory_query)
5801 Process record ignores the memory change of instruction at address %s\n\
5802 because it can't get the value of the segment register.\n\
5803 Do you want to stop the program?"),
5804 paddress (gdbarch, ir.orig_addr)))
5810 if ((opcode & 1) == 0)
5813 ir.ot = ir.dflag + OT_WORD;
5816 if (record_read_memory (gdbarch, ir.addr, buf, 8))
5819 addr = extract_unsigned_integer (buf, 8, byte_order);
5823 if (record_read_memory (gdbarch, ir.addr, buf, 4))
5826 addr = extract_unsigned_integer (buf, 4, byte_order);
5830 if (record_read_memory (gdbarch, ir.addr, buf, 2))
5833 addr = extract_unsigned_integer (buf, 2, byte_order);
5835 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
5840 case 0xb0: /* mov R, Ib */
5848 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
5849 ? ((opcode & 0x7) | ir.rex_b)
5850 : ((opcode & 0x7) & 0x3));
5853 case 0xb8: /* mov R, Iv */
5861 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5864 case 0x91: /* xchg R, EAX */
5871 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5872 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7);
5875 case 0x86: /* xchg Ev, Gv */
5877 if ((opcode & 1) == 0)
5880 ir.ot = ir.dflag + OT_WORD;
5881 if (i386_record_modrm (&ir))
5886 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5888 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5892 if (i386_record_lea_modrm (&ir))
5896 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5898 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5901 case 0xc4: /* les Gv */
5902 case 0xc5: /* lds Gv */
5903 if (ir.regmap[X86_RECORD_R8_REGNUM])
5909 case 0x0fb2: /* lss Gv */
5910 case 0x0fb4: /* lfs Gv */
5911 case 0x0fb5: /* lgs Gv */
5912 if (i386_record_modrm (&ir))
5920 opcode = opcode << 8 | ir.modrm;
5925 case 0xc4: /* les Gv */
5926 regnum = X86_RECORD_ES_REGNUM;
5928 case 0xc5: /* lds Gv */
5929 regnum = X86_RECORD_DS_REGNUM;
5931 case 0x0fb2: /* lss Gv */
5932 regnum = X86_RECORD_SS_REGNUM;
5934 case 0x0fb4: /* lfs Gv */
5935 regnum = X86_RECORD_FS_REGNUM;
5937 case 0x0fb5: /* lgs Gv */
5938 regnum = X86_RECORD_GS_REGNUM;
5941 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5942 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5943 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5946 case 0xc0: /* shifts */
5952 if ((opcode & 1) == 0)
5955 ir.ot = ir.dflag + OT_WORD;
5956 if (i386_record_modrm (&ir))
5958 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
5960 if (i386_record_lea_modrm (&ir))
5966 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5968 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5970 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5977 if (i386_record_modrm (&ir))
5981 if (record_full_arch_list_add_reg (ir.regcache, ir.rm))
5986 if (i386_record_lea_modrm (&ir))
5991 case 0xd8: /* Floats. */
5999 if (i386_record_modrm (&ir))
6001 ir.reg |= ((opcode & 7) << 3);
6007 if (i386_record_lea_modrm_addr (&ir, &addr64))
6015 /* For fcom, ficom nothing to do. */
6021 /* For fcomp, ficomp pop FPU stack, store all. */
6022 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6049 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
6050 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
6051 of code, always affects st(0) register. */
6052 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6076 /* Handling fld, fild. */
6077 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6081 switch (ir.reg >> 4)
6084 if (record_full_arch_list_add_mem (addr64, 4))
6088 if (record_full_arch_list_add_mem (addr64, 8))
6094 if (record_full_arch_list_add_mem (addr64, 2))
6100 switch (ir.reg >> 4)
6103 if (record_full_arch_list_add_mem (addr64, 4))
6105 if (3 == (ir.reg & 7))
6107 /* For fstp m32fp. */
6108 if (i386_record_floats (gdbarch, &ir,
6109 I386_SAVE_FPU_REGS))
6114 if (record_full_arch_list_add_mem (addr64, 4))
6116 if ((3 == (ir.reg & 7))
6117 || (5 == (ir.reg & 7))
6118 || (7 == (ir.reg & 7)))
6120 /* For fstp insn. */
6121 if (i386_record_floats (gdbarch, &ir,
6122 I386_SAVE_FPU_REGS))
6127 if (record_full_arch_list_add_mem (addr64, 8))
6129 if (3 == (ir.reg & 7))
6131 /* For fstp m64fp. */
6132 if (i386_record_floats (gdbarch, &ir,
6133 I386_SAVE_FPU_REGS))
6138 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
6140 /* For fistp, fbld, fild, fbstp. */
6141 if (i386_record_floats (gdbarch, &ir,
6142 I386_SAVE_FPU_REGS))
6147 if (record_full_arch_list_add_mem (addr64, 2))
6156 if (i386_record_floats (gdbarch, &ir,
6157 I386_SAVE_FPU_ENV_REG_STACK))
6162 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
6167 if (i386_record_floats (gdbarch, &ir,
6168 I386_SAVE_FPU_ENV_REG_STACK))
6174 if (record_full_arch_list_add_mem (addr64, 28))
6179 if (record_full_arch_list_add_mem (addr64, 14))
6185 if (record_full_arch_list_add_mem (addr64, 2))
6187 /* Insn fstp, fbstp. */
6188 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6193 if (record_full_arch_list_add_mem (addr64, 10))
6199 if (record_full_arch_list_add_mem (addr64, 28))
6205 if (record_full_arch_list_add_mem (addr64, 14))
6209 if (record_full_arch_list_add_mem (addr64, 80))
6212 if (i386_record_floats (gdbarch, &ir,
6213 I386_SAVE_FPU_ENV_REG_STACK))
6217 if (record_full_arch_list_add_mem (addr64, 8))
6220 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6225 opcode = opcode << 8 | ir.modrm;
6230 /* Opcode is an extension of modR/M byte. */
6236 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6240 if (0x0c == (ir.modrm >> 4))
6242 if ((ir.modrm & 0x0f) <= 7)
6244 if (i386_record_floats (gdbarch, &ir,
6245 I386_SAVE_FPU_REGS))
6250 if (i386_record_floats (gdbarch, &ir,
6251 I387_ST0_REGNUM (tdep)))
6253 /* If only st(0) is changing, then we have already
6255 if ((ir.modrm & 0x0f) - 0x08)
6257 if (i386_record_floats (gdbarch, &ir,
6258 I387_ST0_REGNUM (tdep) +
6259 ((ir.modrm & 0x0f) - 0x08)))
6277 if (i386_record_floats (gdbarch, &ir,
6278 I387_ST0_REGNUM (tdep)))
6296 if (i386_record_floats (gdbarch, &ir,
6297 I386_SAVE_FPU_REGS))
6301 if (i386_record_floats (gdbarch, &ir,
6302 I387_ST0_REGNUM (tdep)))
6304 if (i386_record_floats (gdbarch, &ir,
6305 I387_ST0_REGNUM (tdep) + 1))
6312 if (0xe9 == ir.modrm)
6314 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6317 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6319 if (i386_record_floats (gdbarch, &ir,
6320 I387_ST0_REGNUM (tdep)))
6322 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6324 if (i386_record_floats (gdbarch, &ir,
6325 I387_ST0_REGNUM (tdep) +
6329 else if ((ir.modrm & 0x0f) - 0x08)
6331 if (i386_record_floats (gdbarch, &ir,
6332 I387_ST0_REGNUM (tdep) +
6333 ((ir.modrm & 0x0f) - 0x08)))
6339 if (0xe3 == ir.modrm)
6341 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
6344 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6346 if (i386_record_floats (gdbarch, &ir,
6347 I387_ST0_REGNUM (tdep)))
6349 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6351 if (i386_record_floats (gdbarch, &ir,
6352 I387_ST0_REGNUM (tdep) +
6356 else if ((ir.modrm & 0x0f) - 0x08)
6358 if (i386_record_floats (gdbarch, &ir,
6359 I387_ST0_REGNUM (tdep) +
6360 ((ir.modrm & 0x0f) - 0x08)))
6366 if ((0x0c == ir.modrm >> 4)
6367 || (0x0d == ir.modrm >> 4)
6368 || (0x0f == ir.modrm >> 4))
6370 if ((ir.modrm & 0x0f) <= 7)
6372 if (i386_record_floats (gdbarch, &ir,
6373 I387_ST0_REGNUM (tdep) +
6379 if (i386_record_floats (gdbarch, &ir,
6380 I387_ST0_REGNUM (tdep) +
6381 ((ir.modrm & 0x0f) - 0x08)))
6387 if (0x0c == ir.modrm >> 4)
6389 if (i386_record_floats (gdbarch, &ir,
6390 I387_FTAG_REGNUM (tdep)))
6393 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6395 if ((ir.modrm & 0x0f) <= 7)
6397 if (i386_record_floats (gdbarch, &ir,
6398 I387_ST0_REGNUM (tdep) +
6404 if (i386_record_floats (gdbarch, &ir,
6405 I386_SAVE_FPU_REGS))
6411 if ((0x0c == ir.modrm >> 4)
6412 || (0x0e == ir.modrm >> 4)
6413 || (0x0f == ir.modrm >> 4)
6414 || (0xd9 == ir.modrm))
6416 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6421 if (0xe0 == ir.modrm)
6423 if (record_full_arch_list_add_reg (ir.regcache,
6427 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6429 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6437 case 0xa4: /* movsS */
6439 case 0xaa: /* stosS */
6441 case 0x6c: /* insS */
6443 regcache_raw_read_unsigned (ir.regcache,
6444 ir.regmap[X86_RECORD_RECX_REGNUM],
6450 if ((opcode & 1) == 0)
6453 ir.ot = ir.dflag + OT_WORD;
6454 regcache_raw_read_unsigned (ir.regcache,
6455 ir.regmap[X86_RECORD_REDI_REGNUM],
6458 regcache_raw_read_unsigned (ir.regcache,
6459 ir.regmap[X86_RECORD_ES_REGNUM],
6461 regcache_raw_read_unsigned (ir.regcache,
6462 ir.regmap[X86_RECORD_DS_REGNUM],
6464 if (ir.aflag && (es != ds))
6466 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6467 if (record_full_memory_query)
6470 Process record ignores the memory change of instruction at address %s\n\
6471 because it can't get the value of the segment register.\n\
6472 Do you want to stop the program?"),
6473 paddress (gdbarch, ir.orig_addr)))
6479 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
6483 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6484 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6485 if (opcode == 0xa4 || opcode == 0xa5)
6486 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6487 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6488 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6492 case 0xa6: /* cmpsS */
6494 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6495 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6496 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6497 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6498 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6501 case 0xac: /* lodsS */
6503 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6504 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6505 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6506 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6507 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6510 case 0xae: /* scasS */
6512 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6513 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6514 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6515 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6518 case 0x6e: /* outsS */
6520 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6521 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6522 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6523 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6526 case 0xe4: /* port I/O */
6530 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6531 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6541 case 0xc2: /* ret im */
6542 case 0xc3: /* ret */
6543 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6544 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6547 case 0xca: /* lret im */
6548 case 0xcb: /* lret */
6549 case 0xcf: /* iret */
6550 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6551 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6552 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6555 case 0xe8: /* call im */
6556 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6558 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6562 case 0x9a: /* lcall im */
6563 if (ir.regmap[X86_RECORD_R8_REGNUM])
6568 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6569 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6573 case 0xe9: /* jmp im */
6574 case 0xea: /* ljmp im */
6575 case 0xeb: /* jmp Jb */
6576 case 0x70: /* jcc Jb */
6592 case 0x0f80: /* jcc Jv */
6610 case 0x0f90: /* setcc Gv */
6626 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6628 if (i386_record_modrm (&ir))
6631 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
6635 if (i386_record_lea_modrm (&ir))
6640 case 0x0f40: /* cmov Gv, Ev */
6656 if (i386_record_modrm (&ir))
6659 if (ir.dflag == OT_BYTE)
6661 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
6665 case 0x9c: /* pushf */
6666 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6667 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6669 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6673 case 0x9d: /* popf */
6674 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6675 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6678 case 0x9e: /* sahf */
6679 if (ir.regmap[X86_RECORD_R8_REGNUM])
6685 case 0xf5: /* cmc */
6686 case 0xf8: /* clc */
6687 case 0xf9: /* stc */
6688 case 0xfc: /* cld */
6689 case 0xfd: /* std */
6690 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6693 case 0x9f: /* lahf */
6694 if (ir.regmap[X86_RECORD_R8_REGNUM])
6699 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6700 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6703 /* bit operations */
6704 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6705 ir.ot = ir.dflag + OT_WORD;
6706 if (i386_record_modrm (&ir))
6711 opcode = opcode << 8 | ir.modrm;
6717 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6720 if (i386_record_lea_modrm (&ir))
6724 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6727 case 0x0fa3: /* bt Gv, Ev */
6728 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6731 case 0x0fab: /* bts */
6732 case 0x0fb3: /* btr */
6733 case 0x0fbb: /* btc */
6734 ir.ot = ir.dflag + OT_WORD;
6735 if (i386_record_modrm (&ir))
6738 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6742 if (i386_record_lea_modrm_addr (&ir, &addr64))
6744 regcache_raw_read_unsigned (ir.regcache,
6745 ir.regmap[ir.reg | rex_r],
6750 addr64 += ((int16_t) addr >> 4) << 4;
6753 addr64 += ((int32_t) addr >> 5) << 5;
6756 addr64 += ((int64_t) addr >> 6) << 6;
6759 if (record_full_arch_list_add_mem (addr64, 1 << ir.ot))
6761 if (i386_record_lea_modrm (&ir))
6764 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6767 case 0x0fbc: /* bsf */
6768 case 0x0fbd: /* bsr */
6769 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6770 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6774 case 0x27: /* daa */
6775 case 0x2f: /* das */
6776 case 0x37: /* aaa */
6777 case 0x3f: /* aas */
6778 case 0xd4: /* aam */
6779 case 0xd5: /* aad */
6780 if (ir.regmap[X86_RECORD_R8_REGNUM])
6785 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6786 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6790 case 0x90: /* nop */
6791 if (prefixes & PREFIX_LOCK)
6798 case 0x9b: /* fwait */
6799 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
6801 opcode = (uint32_t) opcode8;
6807 case 0xcc: /* int3 */
6808 printf_unfiltered (_("Process record does not support instruction "
6815 case 0xcd: /* int */
6819 if (record_read_memory (gdbarch, ir.addr, &interrupt, 1))
6822 if (interrupt != 0x80
6823 || tdep->i386_intx80_record == NULL)
6825 printf_unfiltered (_("Process record does not support "
6826 "instruction int 0x%02x.\n"),
6831 ret = tdep->i386_intx80_record (ir.regcache);
6838 case 0xce: /* into */
6839 printf_unfiltered (_("Process record does not support "
6840 "instruction into.\n"));
6845 case 0xfa: /* cli */
6846 case 0xfb: /* sti */
6849 case 0x62: /* bound */
6850 printf_unfiltered (_("Process record does not support "
6851 "instruction bound.\n"));
6856 case 0x0fc8: /* bswap reg */
6864 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
6867 case 0xd6: /* salc */
6868 if (ir.regmap[X86_RECORD_R8_REGNUM])
6873 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6874 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6877 case 0xe0: /* loopnz */
6878 case 0xe1: /* loopz */
6879 case 0xe2: /* loop */
6880 case 0xe3: /* jecxz */
6881 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6882 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6885 case 0x0f30: /* wrmsr */
6886 printf_unfiltered (_("Process record does not support "
6887 "instruction wrmsr.\n"));
6892 case 0x0f32: /* rdmsr */
6893 printf_unfiltered (_("Process record does not support "
6894 "instruction rdmsr.\n"));
6899 case 0x0f31: /* rdtsc */
6900 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6901 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6904 case 0x0f34: /* sysenter */
6907 if (ir.regmap[X86_RECORD_R8_REGNUM])
6912 if (tdep->i386_sysenter_record == NULL)
6914 printf_unfiltered (_("Process record does not support "
6915 "instruction sysenter.\n"));
6919 ret = tdep->i386_sysenter_record (ir.regcache);
6925 case 0x0f35: /* sysexit */
6926 printf_unfiltered (_("Process record does not support "
6927 "instruction sysexit.\n"));
6932 case 0x0f05: /* syscall */
6935 if (tdep->i386_syscall_record == NULL)
6937 printf_unfiltered (_("Process record does not support "
6938 "instruction syscall.\n"));
6942 ret = tdep->i386_syscall_record (ir.regcache);
6948 case 0x0f07: /* sysret */
6949 printf_unfiltered (_("Process record does not support "
6950 "instruction sysret.\n"));
6955 case 0x0fa2: /* cpuid */
6956 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6957 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6958 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6959 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
6962 case 0xf4: /* hlt */
6963 printf_unfiltered (_("Process record does not support "
6964 "instruction hlt.\n"));
6970 if (i386_record_modrm (&ir))
6977 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6981 if (i386_record_lea_modrm (&ir))
6990 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6994 opcode = opcode << 8 | ir.modrm;
7001 if (i386_record_modrm (&ir))
7012 opcode = opcode << 8 | ir.modrm;
7015 if (ir.override >= 0)
7017 if (record_full_memory_query)
7020 Process record ignores the memory change of instruction at address %s\n\
7021 because it can't get the value of the segment register.\n\
7022 Do you want to stop the program?"),
7023 paddress (gdbarch, ir.orig_addr)))
7029 if (i386_record_lea_modrm_addr (&ir, &addr64))
7031 if (record_full_arch_list_add_mem (addr64, 2))
7034 if (ir.regmap[X86_RECORD_R8_REGNUM])
7036 if (record_full_arch_list_add_mem (addr64, 8))
7041 if (record_full_arch_list_add_mem (addr64, 4))
7052 case 0: /* monitor */
7055 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7059 opcode = opcode << 8 | ir.modrm;
7067 if (ir.override >= 0)
7069 if (record_full_memory_query)
7072 Process record ignores the memory change of instruction at address %s\n\
7073 because it can't get the value of the segment register.\n\
7074 Do you want to stop the program?"),
7075 paddress (gdbarch, ir.orig_addr)))
7083 if (i386_record_lea_modrm_addr (&ir, &addr64))
7085 if (record_full_arch_list_add_mem (addr64, 2))
7088 if (ir.regmap[X86_RECORD_R8_REGNUM])
7090 if (record_full_arch_list_add_mem (addr64, 8))
7095 if (record_full_arch_list_add_mem (addr64, 4))
7107 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7108 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7112 else if (ir.rm == 1)
7119 opcode = opcode << 8 | ir.modrm;
7126 if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
7132 if (i386_record_lea_modrm (&ir))
7135 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7138 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7140 case 7: /* invlpg */
7143 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
7144 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
7148 opcode = opcode << 8 | ir.modrm;
7153 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7157 opcode = opcode << 8 | ir.modrm;
7163 case 0x0f08: /* invd */
7164 case 0x0f09: /* wbinvd */
7167 case 0x63: /* arpl */
7168 if (i386_record_modrm (&ir))
7170 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
7172 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
7173 ? (ir.reg | rex_r) : ir.rm);
7177 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
7178 if (i386_record_lea_modrm (&ir))
7181 if (!ir.regmap[X86_RECORD_R8_REGNUM])
7182 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7185 case 0x0f02: /* lar */
7186 case 0x0f03: /* lsl */
7187 if (i386_record_modrm (&ir))
7189 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7190 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7194 if (i386_record_modrm (&ir))
7196 if (ir.mod == 3 && ir.reg == 3)
7199 opcode = opcode << 8 | ir.modrm;
7211 /* nop (multi byte) */
7214 case 0x0f20: /* mov reg, crN */
7215 case 0x0f22: /* mov crN, reg */
7216 if (i386_record_modrm (&ir))
7218 if ((ir.modrm & 0xc0) != 0xc0)
7221 opcode = opcode << 8 | ir.modrm;
7232 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7234 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7238 opcode = opcode << 8 | ir.modrm;
7244 case 0x0f21: /* mov reg, drN */
7245 case 0x0f23: /* mov drN, reg */
7246 if (i386_record_modrm (&ir))
7248 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
7249 || ir.reg == 5 || ir.reg >= 8)
7252 opcode = opcode << 8 | ir.modrm;
7256 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7258 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7261 case 0x0f06: /* clts */
7262 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7265 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7267 case 0x0f0d: /* 3DNow! prefetch */
7270 case 0x0f0e: /* 3DNow! femms */
7271 case 0x0f77: /* emms */
7272 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
7274 record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
7277 case 0x0f0f: /* 3DNow! data */
7278 if (i386_record_modrm (&ir))
7280 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7285 case 0x0c: /* 3DNow! pi2fw */
7286 case 0x0d: /* 3DNow! pi2fd */
7287 case 0x1c: /* 3DNow! pf2iw */
7288 case 0x1d: /* 3DNow! pf2id */
7289 case 0x8a: /* 3DNow! pfnacc */
7290 case 0x8e: /* 3DNow! pfpnacc */
7291 case 0x90: /* 3DNow! pfcmpge */
7292 case 0x94: /* 3DNow! pfmin */
7293 case 0x96: /* 3DNow! pfrcp */
7294 case 0x97: /* 3DNow! pfrsqrt */
7295 case 0x9a: /* 3DNow! pfsub */
7296 case 0x9e: /* 3DNow! pfadd */
7297 case 0xa0: /* 3DNow! pfcmpgt */
7298 case 0xa4: /* 3DNow! pfmax */
7299 case 0xa6: /* 3DNow! pfrcpit1 */
7300 case 0xa7: /* 3DNow! pfrsqit1 */
7301 case 0xaa: /* 3DNow! pfsubr */
7302 case 0xae: /* 3DNow! pfacc */
7303 case 0xb0: /* 3DNow! pfcmpeq */
7304 case 0xb4: /* 3DNow! pfmul */
7305 case 0xb6: /* 3DNow! pfrcpit2 */
7306 case 0xb7: /* 3DNow! pmulhrw */
7307 case 0xbb: /* 3DNow! pswapd */
7308 case 0xbf: /* 3DNow! pavgusb */
7309 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7310 goto no_support_3dnow_data;
7311 record_full_arch_list_add_reg (ir.regcache, ir.reg);
7315 no_support_3dnow_data:
7316 opcode = (opcode << 8) | opcode8;
7322 case 0x0faa: /* rsm */
7323 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7324 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7325 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
7326 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7327 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
7328 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
7329 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
7330 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
7331 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
7335 if (i386_record_modrm (&ir))
7339 case 0: /* fxsave */
7343 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7344 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
7346 if (record_full_arch_list_add_mem (tmpu64, 512))
7351 case 1: /* fxrstor */
7355 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7357 for (i = I387_MM0_REGNUM (tdep);
7358 i386_mmx_regnum_p (gdbarch, i); i++)
7359 record_full_arch_list_add_reg (ir.regcache, i);
7361 for (i = I387_XMM0_REGNUM (tdep);
7362 i386_xmm_regnum_p (gdbarch, i); i++)
7363 record_full_arch_list_add_reg (ir.regcache, i);
7365 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7366 record_full_arch_list_add_reg (ir.regcache,
7367 I387_MXCSR_REGNUM(tdep));
7369 for (i = I387_ST0_REGNUM (tdep);
7370 i386_fp_regnum_p (gdbarch, i); i++)
7371 record_full_arch_list_add_reg (ir.regcache, i);
7373 for (i = I387_FCTRL_REGNUM (tdep);
7374 i386_fpc_regnum_p (gdbarch, i); i++)
7375 record_full_arch_list_add_reg (ir.regcache, i);
7379 case 2: /* ldmxcsr */
7380 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7382 record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
7385 case 3: /* stmxcsr */
7387 if (i386_record_lea_modrm (&ir))
7391 case 5: /* lfence */
7392 case 6: /* mfence */
7393 case 7: /* sfence clflush */
7397 opcode = (opcode << 8) | ir.modrm;
7403 case 0x0fc3: /* movnti */
7404 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
7405 if (i386_record_modrm (&ir))
7410 if (i386_record_lea_modrm (&ir))
7414 /* Add prefix to opcode. */
7529 /* Mask out PREFIX_ADDR. */
7530 switch ((prefixes & ~PREFIX_ADDR))
7542 reswitch_prefix_add:
7550 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7553 opcode = (uint32_t) opcode8 | opcode << 8;
7554 goto reswitch_prefix_add;
7557 case 0x0f10: /* movups */
7558 case 0x660f10: /* movupd */
7559 case 0xf30f10: /* movss */
7560 case 0xf20f10: /* movsd */
7561 case 0x0f12: /* movlps */
7562 case 0x660f12: /* movlpd */
7563 case 0xf30f12: /* movsldup */
7564 case 0xf20f12: /* movddup */
7565 case 0x0f14: /* unpcklps */
7566 case 0x660f14: /* unpcklpd */
7567 case 0x0f15: /* unpckhps */
7568 case 0x660f15: /* unpckhpd */
7569 case 0x0f16: /* movhps */
7570 case 0x660f16: /* movhpd */
7571 case 0xf30f16: /* movshdup */
7572 case 0x0f28: /* movaps */
7573 case 0x660f28: /* movapd */
7574 case 0x0f2a: /* cvtpi2ps */
7575 case 0x660f2a: /* cvtpi2pd */
7576 case 0xf30f2a: /* cvtsi2ss */
7577 case 0xf20f2a: /* cvtsi2sd */
7578 case 0x0f2c: /* cvttps2pi */
7579 case 0x660f2c: /* cvttpd2pi */
7580 case 0x0f2d: /* cvtps2pi */
7581 case 0x660f2d: /* cvtpd2pi */
7582 case 0x660f3800: /* pshufb */
7583 case 0x660f3801: /* phaddw */
7584 case 0x660f3802: /* phaddd */
7585 case 0x660f3803: /* phaddsw */
7586 case 0x660f3804: /* pmaddubsw */
7587 case 0x660f3805: /* phsubw */
7588 case 0x660f3806: /* phsubd */
7589 case 0x660f3807: /* phsubsw */
7590 case 0x660f3808: /* psignb */
7591 case 0x660f3809: /* psignw */
7592 case 0x660f380a: /* psignd */
7593 case 0x660f380b: /* pmulhrsw */
7594 case 0x660f3810: /* pblendvb */
7595 case 0x660f3814: /* blendvps */
7596 case 0x660f3815: /* blendvpd */
7597 case 0x660f381c: /* pabsb */
7598 case 0x660f381d: /* pabsw */
7599 case 0x660f381e: /* pabsd */
7600 case 0x660f3820: /* pmovsxbw */
7601 case 0x660f3821: /* pmovsxbd */
7602 case 0x660f3822: /* pmovsxbq */
7603 case 0x660f3823: /* pmovsxwd */
7604 case 0x660f3824: /* pmovsxwq */
7605 case 0x660f3825: /* pmovsxdq */
7606 case 0x660f3828: /* pmuldq */
7607 case 0x660f3829: /* pcmpeqq */
7608 case 0x660f382a: /* movntdqa */
7609 case 0x660f3a08: /* roundps */
7610 case 0x660f3a09: /* roundpd */
7611 case 0x660f3a0a: /* roundss */
7612 case 0x660f3a0b: /* roundsd */
7613 case 0x660f3a0c: /* blendps */
7614 case 0x660f3a0d: /* blendpd */
7615 case 0x660f3a0e: /* pblendw */
7616 case 0x660f3a0f: /* palignr */
7617 case 0x660f3a20: /* pinsrb */
7618 case 0x660f3a21: /* insertps */
7619 case 0x660f3a22: /* pinsrd pinsrq */
7620 case 0x660f3a40: /* dpps */
7621 case 0x660f3a41: /* dppd */
7622 case 0x660f3a42: /* mpsadbw */
7623 case 0x660f3a60: /* pcmpestrm */
7624 case 0x660f3a61: /* pcmpestri */
7625 case 0x660f3a62: /* pcmpistrm */
7626 case 0x660f3a63: /* pcmpistri */
7627 case 0x0f51: /* sqrtps */
7628 case 0x660f51: /* sqrtpd */
7629 case 0xf20f51: /* sqrtsd */
7630 case 0xf30f51: /* sqrtss */
7631 case 0x0f52: /* rsqrtps */
7632 case 0xf30f52: /* rsqrtss */
7633 case 0x0f53: /* rcpps */
7634 case 0xf30f53: /* rcpss */
7635 case 0x0f54: /* andps */
7636 case 0x660f54: /* andpd */
7637 case 0x0f55: /* andnps */
7638 case 0x660f55: /* andnpd */
7639 case 0x0f56: /* orps */
7640 case 0x660f56: /* orpd */
7641 case 0x0f57: /* xorps */
7642 case 0x660f57: /* xorpd */
7643 case 0x0f58: /* addps */
7644 case 0x660f58: /* addpd */
7645 case 0xf20f58: /* addsd */
7646 case 0xf30f58: /* addss */
7647 case 0x0f59: /* mulps */
7648 case 0x660f59: /* mulpd */
7649 case 0xf20f59: /* mulsd */
7650 case 0xf30f59: /* mulss */
7651 case 0x0f5a: /* cvtps2pd */
7652 case 0x660f5a: /* cvtpd2ps */
7653 case 0xf20f5a: /* cvtsd2ss */
7654 case 0xf30f5a: /* cvtss2sd */
7655 case 0x0f5b: /* cvtdq2ps */
7656 case 0x660f5b: /* cvtps2dq */
7657 case 0xf30f5b: /* cvttps2dq */
7658 case 0x0f5c: /* subps */
7659 case 0x660f5c: /* subpd */
7660 case 0xf20f5c: /* subsd */
7661 case 0xf30f5c: /* subss */
7662 case 0x0f5d: /* minps */
7663 case 0x660f5d: /* minpd */
7664 case 0xf20f5d: /* minsd */
7665 case 0xf30f5d: /* minss */
7666 case 0x0f5e: /* divps */
7667 case 0x660f5e: /* divpd */
7668 case 0xf20f5e: /* divsd */
7669 case 0xf30f5e: /* divss */
7670 case 0x0f5f: /* maxps */
7671 case 0x660f5f: /* maxpd */
7672 case 0xf20f5f: /* maxsd */
7673 case 0xf30f5f: /* maxss */
7674 case 0x660f60: /* punpcklbw */
7675 case 0x660f61: /* punpcklwd */
7676 case 0x660f62: /* punpckldq */
7677 case 0x660f63: /* packsswb */
7678 case 0x660f64: /* pcmpgtb */
7679 case 0x660f65: /* pcmpgtw */
7680 case 0x660f66: /* pcmpgtd */
7681 case 0x660f67: /* packuswb */
7682 case 0x660f68: /* punpckhbw */
7683 case 0x660f69: /* punpckhwd */
7684 case 0x660f6a: /* punpckhdq */
7685 case 0x660f6b: /* packssdw */
7686 case 0x660f6c: /* punpcklqdq */
7687 case 0x660f6d: /* punpckhqdq */
7688 case 0x660f6e: /* movd */
7689 case 0x660f6f: /* movdqa */
7690 case 0xf30f6f: /* movdqu */
7691 case 0x660f70: /* pshufd */
7692 case 0xf20f70: /* pshuflw */
7693 case 0xf30f70: /* pshufhw */
7694 case 0x660f74: /* pcmpeqb */
7695 case 0x660f75: /* pcmpeqw */
7696 case 0x660f76: /* pcmpeqd */
7697 case 0x660f7c: /* haddpd */
7698 case 0xf20f7c: /* haddps */
7699 case 0x660f7d: /* hsubpd */
7700 case 0xf20f7d: /* hsubps */
7701 case 0xf30f7e: /* movq */
7702 case 0x0fc2: /* cmpps */
7703 case 0x660fc2: /* cmppd */
7704 case 0xf20fc2: /* cmpsd */
7705 case 0xf30fc2: /* cmpss */
7706 case 0x660fc4: /* pinsrw */
7707 case 0x0fc6: /* shufps */
7708 case 0x660fc6: /* shufpd */
7709 case 0x660fd0: /* addsubpd */
7710 case 0xf20fd0: /* addsubps */
7711 case 0x660fd1: /* psrlw */
7712 case 0x660fd2: /* psrld */
7713 case 0x660fd3: /* psrlq */
7714 case 0x660fd4: /* paddq */
7715 case 0x660fd5: /* pmullw */
7716 case 0xf30fd6: /* movq2dq */
7717 case 0x660fd8: /* psubusb */
7718 case 0x660fd9: /* psubusw */
7719 case 0x660fda: /* pminub */
7720 case 0x660fdb: /* pand */
7721 case 0x660fdc: /* paddusb */
7722 case 0x660fdd: /* paddusw */
7723 case 0x660fde: /* pmaxub */
7724 case 0x660fdf: /* pandn */
7725 case 0x660fe0: /* pavgb */
7726 case 0x660fe1: /* psraw */
7727 case 0x660fe2: /* psrad */
7728 case 0x660fe3: /* pavgw */
7729 case 0x660fe4: /* pmulhuw */
7730 case 0x660fe5: /* pmulhw */
7731 case 0x660fe6: /* cvttpd2dq */
7732 case 0xf20fe6: /* cvtpd2dq */
7733 case 0xf30fe6: /* cvtdq2pd */
7734 case 0x660fe8: /* psubsb */
7735 case 0x660fe9: /* psubsw */
7736 case 0x660fea: /* pminsw */
7737 case 0x660feb: /* por */
7738 case 0x660fec: /* paddsb */
7739 case 0x660fed: /* paddsw */
7740 case 0x660fee: /* pmaxsw */
7741 case 0x660fef: /* pxor */
7742 case 0xf20ff0: /* lddqu */
7743 case 0x660ff1: /* psllw */
7744 case 0x660ff2: /* pslld */
7745 case 0x660ff3: /* psllq */
7746 case 0x660ff4: /* pmuludq */
7747 case 0x660ff5: /* pmaddwd */
7748 case 0x660ff6: /* psadbw */
7749 case 0x660ff8: /* psubb */
7750 case 0x660ff9: /* psubw */
7751 case 0x660ffa: /* psubd */
7752 case 0x660ffb: /* psubq */
7753 case 0x660ffc: /* paddb */
7754 case 0x660ffd: /* paddw */
7755 case 0x660ffe: /* paddd */
7756 if (i386_record_modrm (&ir))
7759 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
7761 record_full_arch_list_add_reg (ir.regcache,
7762 I387_XMM0_REGNUM (tdep) + ir.reg);
7763 if ((opcode & 0xfffffffc) == 0x660f3a60)
7764 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7767 case 0x0f11: /* movups */
7768 case 0x660f11: /* movupd */
7769 case 0xf30f11: /* movss */
7770 case 0xf20f11: /* movsd */
7771 case 0x0f13: /* movlps */
7772 case 0x660f13: /* movlpd */
7773 case 0x0f17: /* movhps */
7774 case 0x660f17: /* movhpd */
7775 case 0x0f29: /* movaps */
7776 case 0x660f29: /* movapd */
7777 case 0x660f3a14: /* pextrb */
7778 case 0x660f3a15: /* pextrw */
7779 case 0x660f3a16: /* pextrd pextrq */
7780 case 0x660f3a17: /* extractps */
7781 case 0x660f7f: /* movdqa */
7782 case 0xf30f7f: /* movdqu */
7783 if (i386_record_modrm (&ir))
7787 if (opcode == 0x0f13 || opcode == 0x660f13
7788 || opcode == 0x0f17 || opcode == 0x660f17)
7791 if (!i386_xmm_regnum_p (gdbarch,
7792 I387_XMM0_REGNUM (tdep) + ir.rm))
7794 record_full_arch_list_add_reg (ir.regcache,
7795 I387_XMM0_REGNUM (tdep) + ir.rm);
7817 if (i386_record_lea_modrm (&ir))
7822 case 0x0f2b: /* movntps */
7823 case 0x660f2b: /* movntpd */
7824 case 0x0fe7: /* movntq */
7825 case 0x660fe7: /* movntdq */
7828 if (opcode == 0x0fe7)
7832 if (i386_record_lea_modrm (&ir))
7836 case 0xf30f2c: /* cvttss2si */
7837 case 0xf20f2c: /* cvttsd2si */
7838 case 0xf30f2d: /* cvtss2si */
7839 case 0xf20f2d: /* cvtsd2si */
7840 case 0xf20f38f0: /* crc32 */
7841 case 0xf20f38f1: /* crc32 */
7842 case 0x0f50: /* movmskps */
7843 case 0x660f50: /* movmskpd */
7844 case 0x0fc5: /* pextrw */
7845 case 0x660fc5: /* pextrw */
7846 case 0x0fd7: /* pmovmskb */
7847 case 0x660fd7: /* pmovmskb */
7848 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7851 case 0x0f3800: /* pshufb */
7852 case 0x0f3801: /* phaddw */
7853 case 0x0f3802: /* phaddd */
7854 case 0x0f3803: /* phaddsw */
7855 case 0x0f3804: /* pmaddubsw */
7856 case 0x0f3805: /* phsubw */
7857 case 0x0f3806: /* phsubd */
7858 case 0x0f3807: /* phsubsw */
7859 case 0x0f3808: /* psignb */
7860 case 0x0f3809: /* psignw */
7861 case 0x0f380a: /* psignd */
7862 case 0x0f380b: /* pmulhrsw */
7863 case 0x0f381c: /* pabsb */
7864 case 0x0f381d: /* pabsw */
7865 case 0x0f381e: /* pabsd */
7866 case 0x0f382b: /* packusdw */
7867 case 0x0f3830: /* pmovzxbw */
7868 case 0x0f3831: /* pmovzxbd */
7869 case 0x0f3832: /* pmovzxbq */
7870 case 0x0f3833: /* pmovzxwd */
7871 case 0x0f3834: /* pmovzxwq */
7872 case 0x0f3835: /* pmovzxdq */
7873 case 0x0f3837: /* pcmpgtq */
7874 case 0x0f3838: /* pminsb */
7875 case 0x0f3839: /* pminsd */
7876 case 0x0f383a: /* pminuw */
7877 case 0x0f383b: /* pminud */
7878 case 0x0f383c: /* pmaxsb */
7879 case 0x0f383d: /* pmaxsd */
7880 case 0x0f383e: /* pmaxuw */
7881 case 0x0f383f: /* pmaxud */
7882 case 0x0f3840: /* pmulld */
7883 case 0x0f3841: /* phminposuw */
7884 case 0x0f3a0f: /* palignr */
7885 case 0x0f60: /* punpcklbw */
7886 case 0x0f61: /* punpcklwd */
7887 case 0x0f62: /* punpckldq */
7888 case 0x0f63: /* packsswb */
7889 case 0x0f64: /* pcmpgtb */
7890 case 0x0f65: /* pcmpgtw */
7891 case 0x0f66: /* pcmpgtd */
7892 case 0x0f67: /* packuswb */
7893 case 0x0f68: /* punpckhbw */
7894 case 0x0f69: /* punpckhwd */
7895 case 0x0f6a: /* punpckhdq */
7896 case 0x0f6b: /* packssdw */
7897 case 0x0f6e: /* movd */
7898 case 0x0f6f: /* movq */
7899 case 0x0f70: /* pshufw */
7900 case 0x0f74: /* pcmpeqb */
7901 case 0x0f75: /* pcmpeqw */
7902 case 0x0f76: /* pcmpeqd */
7903 case 0x0fc4: /* pinsrw */
7904 case 0x0fd1: /* psrlw */
7905 case 0x0fd2: /* psrld */
7906 case 0x0fd3: /* psrlq */
7907 case 0x0fd4: /* paddq */
7908 case 0x0fd5: /* pmullw */
7909 case 0xf20fd6: /* movdq2q */
7910 case 0x0fd8: /* psubusb */
7911 case 0x0fd9: /* psubusw */
7912 case 0x0fda: /* pminub */
7913 case 0x0fdb: /* pand */
7914 case 0x0fdc: /* paddusb */
7915 case 0x0fdd: /* paddusw */
7916 case 0x0fde: /* pmaxub */
7917 case 0x0fdf: /* pandn */
7918 case 0x0fe0: /* pavgb */
7919 case 0x0fe1: /* psraw */
7920 case 0x0fe2: /* psrad */
7921 case 0x0fe3: /* pavgw */
7922 case 0x0fe4: /* pmulhuw */
7923 case 0x0fe5: /* pmulhw */
7924 case 0x0fe8: /* psubsb */
7925 case 0x0fe9: /* psubsw */
7926 case 0x0fea: /* pminsw */
7927 case 0x0feb: /* por */
7928 case 0x0fec: /* paddsb */
7929 case 0x0fed: /* paddsw */
7930 case 0x0fee: /* pmaxsw */
7931 case 0x0fef: /* pxor */
7932 case 0x0ff1: /* psllw */
7933 case 0x0ff2: /* pslld */
7934 case 0x0ff3: /* psllq */
7935 case 0x0ff4: /* pmuludq */
7936 case 0x0ff5: /* pmaddwd */
7937 case 0x0ff6: /* psadbw */
7938 case 0x0ff8: /* psubb */
7939 case 0x0ff9: /* psubw */
7940 case 0x0ffa: /* psubd */
7941 case 0x0ffb: /* psubq */
7942 case 0x0ffc: /* paddb */
7943 case 0x0ffd: /* paddw */
7944 case 0x0ffe: /* paddd */
7945 if (i386_record_modrm (&ir))
7947 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7949 record_full_arch_list_add_reg (ir.regcache,
7950 I387_MM0_REGNUM (tdep) + ir.reg);
7953 case 0x0f71: /* psllw */
7954 case 0x0f72: /* pslld */
7955 case 0x0f73: /* psllq */
7956 if (i386_record_modrm (&ir))
7958 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7960 record_full_arch_list_add_reg (ir.regcache,
7961 I387_MM0_REGNUM (tdep) + ir.rm);
7964 case 0x660f71: /* psllw */
7965 case 0x660f72: /* pslld */
7966 case 0x660f73: /* psllq */
7967 if (i386_record_modrm (&ir))
7970 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
7972 record_full_arch_list_add_reg (ir.regcache,
7973 I387_XMM0_REGNUM (tdep) + ir.rm);
7976 case 0x0f7e: /* movd */
7977 case 0x660f7e: /* movd */
7978 if (i386_record_modrm (&ir))
7981 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7988 if (i386_record_lea_modrm (&ir))
7993 case 0x0f7f: /* movq */
7994 if (i386_record_modrm (&ir))
7998 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
8000 record_full_arch_list_add_reg (ir.regcache,
8001 I387_MM0_REGNUM (tdep) + ir.rm);
8006 if (i386_record_lea_modrm (&ir))
8011 case 0xf30fb8: /* popcnt */
8012 if (i386_record_modrm (&ir))
8014 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
8015 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
8018 case 0x660fd6: /* movq */
8019 if (i386_record_modrm (&ir))
8024 if (!i386_xmm_regnum_p (gdbarch,
8025 I387_XMM0_REGNUM (tdep) + ir.rm))
8027 record_full_arch_list_add_reg (ir.regcache,
8028 I387_XMM0_REGNUM (tdep) + ir.rm);
8033 if (i386_record_lea_modrm (&ir))
8038 case 0x660f3817: /* ptest */
8039 case 0x0f2e: /* ucomiss */
8040 case 0x660f2e: /* ucomisd */
8041 case 0x0f2f: /* comiss */
8042 case 0x660f2f: /* comisd */
8043 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
8046 case 0x0ff7: /* maskmovq */
8047 regcache_raw_read_unsigned (ir.regcache,
8048 ir.regmap[X86_RECORD_REDI_REGNUM],
8050 if (record_full_arch_list_add_mem (addr, 64))
8054 case 0x660ff7: /* maskmovdqu */
8055 regcache_raw_read_unsigned (ir.regcache,
8056 ir.regmap[X86_RECORD_REDI_REGNUM],
8058 if (record_full_arch_list_add_mem (addr, 128))
8073 /* In the future, maybe still need to deal with need_dasm. */
8074 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
8075 if (record_full_arch_list_add_end ())
8081 printf_unfiltered (_("Process record does not support instruction 0x%02x "
8082 "at address %s.\n"),
8083 (unsigned int) (opcode),
8084 paddress (gdbarch, ir.orig_addr));
8088 static const int i386_record_regmap[] =
8090 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
8091 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
8092 0, 0, 0, 0, 0, 0, 0, 0,
8093 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
8094 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
8097 /* Check that the given address appears suitable for a fast
8098 tracepoint, which on x86-64 means that we need an instruction of at
8099 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8100 jump and not have to worry about program jumps to an address in the
8101 middle of the tracepoint jump. On x86, it may be possible to use
8102 4-byte jumps with a 2-byte offset to a trampoline located in the
8103 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8104 of instruction to replace, and 0 if not, plus an explanatory
8108 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, CORE_ADDR addr,
8112 static struct ui_file *gdb_null = NULL;
8114 /* Ask the target for the minimum instruction length supported. */
8115 jumplen = target_get_min_fast_tracepoint_insn_len ();
8119 /* If the target does not support the get_min_fast_tracepoint_insn_len
8120 operation, assume that fast tracepoints will always be implemented
8121 using 4-byte relative jumps on both x86 and x86-64. */
8124 else if (jumplen == 0)
8126 /* If the target does support get_min_fast_tracepoint_insn_len but
8127 returns zero, then the IPA has not loaded yet. In this case,
8128 we optimistically assume that truncated 2-byte relative jumps
8129 will be available on x86, and compensate later if this assumption
8130 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8131 jumps will always be used. */
8132 jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4;
8135 /* Dummy file descriptor for the disassembler. */
8137 gdb_null = ui_file_new ();
8139 /* Check for fit. */
8140 len = gdb_print_insn (gdbarch, addr, gdb_null, NULL);
8144 /* Return a bit of target-specific detail to add to the caller's
8145 generic failure message. */
8147 *msg = xstrprintf (_("; instruction is only %d bytes long, "
8148 "need at least %d bytes for the jump"),
8160 /* Return a floating-point format for a floating-point variable of
8161 length LEN in bits. If non-NULL, NAME is the name of its type.
8162 If no suitable type is found, return NULL. */
8164 const struct floatformat **
8165 i386_floatformat_for_type (struct gdbarch *gdbarch,
8166 const char *name, int len)
8168 if (len == 128 && name)
8169 if (strcmp (name, "__float128") == 0
8170 || strcmp (name, "_Float128") == 0
8171 || strcmp (name, "complex _Float128") == 0)
8172 return floatformats_ia64_quad;
8174 return default_floatformat_for_type (gdbarch, name, len);
8178 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
8179 struct tdesc_arch_data *tdesc_data)
8181 const struct target_desc *tdesc = tdep->tdesc;
8182 const struct tdesc_feature *feature_core;
8184 const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx,
8186 int i, num_regs, valid_p;
8188 if (! tdesc_has_registers (tdesc))
8191 /* Get core registers. */
8192 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
8193 if (feature_core == NULL)
8196 /* Get SSE registers. */
8197 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
8199 /* Try AVX registers. */
8200 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
8202 /* Try MPX registers. */
8203 feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx");
8205 /* Try AVX512 registers. */
8206 feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512");
8210 /* The XCR0 bits. */
8213 /* AVX512 register description requires AVX register description. */
8217 tdep->xcr0 = X86_XSTATE_MPX_AVX512_MASK;
8219 /* It may have been set by OSABI initialization function. */
8220 if (tdep->k0_regnum < 0)
8222 tdep->k_register_names = i386_k_names;
8223 tdep->k0_regnum = I386_K0_REGNUM;
8226 for (i = 0; i < I387_NUM_K_REGS; i++)
8227 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8228 tdep->k0_regnum + i,
8231 if (tdep->num_zmm_regs == 0)
8233 tdep->zmmh_register_names = i386_zmmh_names;
8234 tdep->num_zmm_regs = 8;
8235 tdep->zmm0h_regnum = I386_ZMM0H_REGNUM;
8238 for (i = 0; i < tdep->num_zmm_regs; i++)
8239 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8240 tdep->zmm0h_regnum + i,
8241 tdep->zmmh_register_names[i]);
8243 for (i = 0; i < tdep->num_xmm_avx512_regs; i++)
8244 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8245 tdep->xmm16_regnum + i,
8246 tdep->xmm_avx512_register_names[i]);
8248 for (i = 0; i < tdep->num_ymm_avx512_regs; i++)
8249 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8250 tdep->ymm16h_regnum + i,
8251 tdep->ymm16h_register_names[i]);
8255 /* AVX register description requires SSE register description. */
8259 if (!feature_avx512)
8260 tdep->xcr0 = X86_XSTATE_AVX_MASK;
8262 /* It may have been set by OSABI initialization function. */
8263 if (tdep->num_ymm_regs == 0)
8265 tdep->ymmh_register_names = i386_ymmh_names;
8266 tdep->num_ymm_regs = 8;
8267 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
8270 for (i = 0; i < tdep->num_ymm_regs; i++)
8271 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
8272 tdep->ymm0h_regnum + i,
8273 tdep->ymmh_register_names[i]);
8275 else if (feature_sse)
8276 tdep->xcr0 = X86_XSTATE_SSE_MASK;
8279 tdep->xcr0 = X86_XSTATE_X87_MASK;
8280 tdep->num_xmm_regs = 0;
8283 num_regs = tdep->num_core_regs;
8284 for (i = 0; i < num_regs; i++)
8285 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
8286 tdep->register_names[i]);
8290 /* Need to include %mxcsr, so add one. */
8291 num_regs += tdep->num_xmm_regs + 1;
8292 for (; i < num_regs; i++)
8293 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
8294 tdep->register_names[i]);
8299 tdep->xcr0 |= X86_XSTATE_MPX_MASK;
8301 if (tdep->bnd0r_regnum < 0)
8303 tdep->mpx_register_names = i386_mpx_names;
8304 tdep->bnd0r_regnum = I386_BND0R_REGNUM;
8305 tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM;
8308 for (i = 0; i < I387_NUM_MPX_REGS; i++)
8309 valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data,
8310 I387_BND0R_REGNUM (tdep) + i,
8311 tdep->mpx_register_names[i]);
8318 static struct gdbarch *
8319 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8321 struct gdbarch_tdep *tdep;
8322 struct gdbarch *gdbarch;
8323 struct tdesc_arch_data *tdesc_data;
8324 const struct target_desc *tdesc;
8330 /* If there is already a candidate, use it. */
8331 arches = gdbarch_list_lookup_by_info (arches, &info);
8333 return arches->gdbarch;
8335 /* Allocate space for the new architecture. */
8336 tdep = XCNEW (struct gdbarch_tdep);
8337 gdbarch = gdbarch_alloc (&info, tdep);
8339 /* General-purpose registers. */
8340 tdep->gregset_reg_offset = NULL;
8341 tdep->gregset_num_regs = I386_NUM_GREGS;
8342 tdep->sizeof_gregset = 0;
8344 /* Floating-point registers. */
8345 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
8346 tdep->fpregset = &i386_fpregset;
8348 /* The default settings include the FPU registers, the MMX registers
8349 and the SSE registers. This can be overridden for a specific ABI
8350 by adjusting the members `st0_regnum', `mm0_regnum' and
8351 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8352 will show up in the output of "info all-registers". */
8354 tdep->st0_regnum = I386_ST0_REGNUM;
8356 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8357 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
8359 tdep->jb_pc_offset = -1;
8360 tdep->struct_return = pcc_struct_return;
8361 tdep->sigtramp_start = 0;
8362 tdep->sigtramp_end = 0;
8363 tdep->sigtramp_p = i386_sigtramp_p;
8364 tdep->sigcontext_addr = NULL;
8365 tdep->sc_reg_offset = NULL;
8366 tdep->sc_pc_offset = -1;
8367 tdep->sc_sp_offset = -1;
8369 tdep->xsave_xcr0_offset = -1;
8371 tdep->record_regmap = i386_record_regmap;
8373 set_gdbarch_long_long_align_bit (gdbarch, 32);
8375 /* The format used for `long double' on almost all i386 targets is
8376 the i387 extended floating-point format. In fact, of all targets
8377 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8378 on having a `long double' that's not `long' at all. */
8379 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
8381 /* Although the i387 extended floating-point has only 80 significant
8382 bits, a `long double' actually takes up 96, probably to enforce
8384 set_gdbarch_long_double_bit (gdbarch, 96);
8386 /* Support for floating-point data type variants. */
8387 set_gdbarch_floatformat_for_type (gdbarch, i386_floatformat_for_type);
8389 /* Register numbers of various important registers. */
8390 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
8391 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
8392 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
8393 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
8395 /* NOTE: kettenis/20040418: GCC does have two possible register
8396 numbering schemes on the i386: dbx and SVR4. These schemes
8397 differ in how they number %ebp, %esp, %eflags, and the
8398 floating-point registers, and are implemented by the arrays
8399 dbx_register_map[] and svr4_dbx_register_map in
8400 gcc/config/i386.c. GCC also defines a third numbering scheme in
8401 gcc/config/i386.c, which it designates as the "default" register
8402 map used in 64bit mode. This last register numbering scheme is
8403 implemented in dbx64_register_map, and is used for AMD64; see
8406 Currently, each GCC i386 target always uses the same register
8407 numbering scheme across all its supported debugging formats
8408 i.e. SDB (COFF), stabs and DWARF 2. This is because
8409 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8410 DBX_REGISTER_NUMBER macro which is defined by each target's
8411 respective config header in a manner independent of the requested
8412 output debugging format.
8414 This does not match the arrangement below, which presumes that
8415 the SDB and stabs numbering schemes differ from the DWARF and
8416 DWARF 2 ones. The reason for this arrangement is that it is
8417 likely to get the numbering scheme for the target's
8418 default/native debug format right. For targets where GCC is the
8419 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8420 targets where the native toolchain uses a different numbering
8421 scheme for a particular debug format (stabs-in-ELF on Solaris)
8422 the defaults below will have to be overridden, like
8423 i386_elf_init_abi() does. */
8425 /* Use the dbx register numbering scheme for stabs and COFF. */
8426 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8427 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8429 /* Use the SVR4 register numbering scheme for DWARF 2. */
8430 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_dwarf_reg_to_regnum);
8432 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8433 be in use on any of the supported i386 targets. */
8435 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
8437 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
8439 /* Call dummy code. */
8440 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
8441 set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code);
8442 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
8443 set_gdbarch_frame_align (gdbarch, i386_frame_align);
8445 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
8446 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
8447 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
8449 set_gdbarch_return_value (gdbarch, i386_return_value);
8451 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
8453 /* Stack grows downward. */
8454 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8456 SET_GDBARCH_BREAKPOINT_MANIPULATION (i386);
8457 set_gdbarch_decr_pc_after_break (gdbarch, 1);
8458 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
8460 set_gdbarch_frame_args_skip (gdbarch, 8);
8462 set_gdbarch_print_insn (gdbarch, i386_print_insn);
8464 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
8466 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
8468 /* Add the i386 register groups. */
8469 i386_add_reggroups (gdbarch);
8470 tdep->register_reggroup_p = i386_register_reggroup_p;
8472 /* Helper for function argument information. */
8473 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
8475 /* Hook the function epilogue frame unwinder. This unwinder is
8476 appended to the list first, so that it supercedes the DWARF
8477 unwinder in function epilogues (where the DWARF unwinder
8478 currently fails). */
8479 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
8481 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8482 to the list before the prologue-based unwinders, so that DWARF
8483 CFI info will be used if it is available. */
8484 dwarf2_append_unwinders (gdbarch);
8486 frame_base_set_default (gdbarch, &i386_frame_base);
8488 /* Pseudo registers may be changed by amd64_init_abi. */
8489 set_gdbarch_pseudo_register_read_value (gdbarch,
8490 i386_pseudo_register_read_value);
8491 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
8492 set_gdbarch_ax_pseudo_register_collect (gdbarch,
8493 i386_ax_pseudo_register_collect);
8495 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
8496 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
8498 /* Override the normal target description method to make the AVX
8499 upper halves anonymous. */
8500 set_gdbarch_register_name (gdbarch, i386_register_name);
8502 /* Even though the default ABI only includes general-purpose registers,
8503 floating-point registers and the SSE registers, we have to leave a
8504 gap for the upper AVX, MPX and AVX512 registers. */
8505 set_gdbarch_num_regs (gdbarch, I386_AVX512_NUM_REGS);
8507 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
8509 /* Get the x86 target description from INFO. */
8510 tdesc = info.target_desc;
8511 if (! tdesc_has_registers (tdesc))
8513 tdep->tdesc = tdesc;
8515 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
8516 tdep->register_names = i386_register_names;
8518 /* No upper YMM registers. */
8519 tdep->ymmh_register_names = NULL;
8520 tdep->ymm0h_regnum = -1;
8522 /* No upper ZMM registers. */
8523 tdep->zmmh_register_names = NULL;
8524 tdep->zmm0h_regnum = -1;
8526 /* No high XMM registers. */
8527 tdep->xmm_avx512_register_names = NULL;
8528 tdep->xmm16_regnum = -1;
8530 /* No upper YMM16-31 registers. */
8531 tdep->ymm16h_register_names = NULL;
8532 tdep->ymm16h_regnum = -1;
8534 tdep->num_byte_regs = 8;
8535 tdep->num_word_regs = 8;
8536 tdep->num_dword_regs = 0;
8537 tdep->num_mmx_regs = 8;
8538 tdep->num_ymm_regs = 0;
8540 /* No MPX registers. */
8541 tdep->bnd0r_regnum = -1;
8542 tdep->bndcfgu_regnum = -1;
8544 /* No AVX512 registers. */
8545 tdep->k0_regnum = -1;
8546 tdep->num_zmm_regs = 0;
8547 tdep->num_ymm_avx512_regs = 0;
8548 tdep->num_xmm_avx512_regs = 0;
8550 tdesc_data = tdesc_data_alloc ();
8552 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
8554 set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address);
8556 set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call);
8557 set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret);
8558 set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump);
8560 /* Hook in ABI-specific overrides, if they have been registered. */
8561 info.tdep_info = tdesc_data;
8562 gdbarch_init_osabi (info, gdbarch);
8564 if (!i386_validate_tdesc_p (tdep, tdesc_data))
8566 tdesc_data_cleanup (tdesc_data);
8568 gdbarch_free (gdbarch);
8572 num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0);
8574 /* Wire in pseudo registers. Number of pseudo registers may be
8576 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
8577 + tdep->num_word_regs
8578 + tdep->num_dword_regs
8579 + tdep->num_mmx_regs
8580 + tdep->num_ymm_regs
8582 + tdep->num_ymm_avx512_regs
8583 + tdep->num_zmm_regs));
8585 /* Target description may be changed. */
8586 tdesc = tdep->tdesc;
8588 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
8590 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8591 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
8593 /* Make %al the first pseudo-register. */
8594 tdep->al_regnum = gdbarch_num_regs (gdbarch);
8595 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
8597 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
8598 if (tdep->num_dword_regs)
8600 /* Support dword pseudo-register if it hasn't been disabled. */
8601 tdep->eax_regnum = ymm0_regnum;
8602 ymm0_regnum += tdep->num_dword_regs;
8605 tdep->eax_regnum = -1;
8607 mm0_regnum = ymm0_regnum;
8608 if (tdep->num_ymm_regs)
8610 /* Support YMM pseudo-register if it is available. */
8611 tdep->ymm0_regnum = ymm0_regnum;
8612 mm0_regnum += tdep->num_ymm_regs;
8615 tdep->ymm0_regnum = -1;
8617 if (tdep->num_ymm_avx512_regs)
8619 /* Support YMM16-31 pseudo registers if available. */
8620 tdep->ymm16_regnum = mm0_regnum;
8621 mm0_regnum += tdep->num_ymm_avx512_regs;
8624 tdep->ymm16_regnum = -1;
8626 if (tdep->num_zmm_regs)
8628 /* Support ZMM pseudo-register if it is available. */
8629 tdep->zmm0_regnum = mm0_regnum;
8630 mm0_regnum += tdep->num_zmm_regs;
8633 tdep->zmm0_regnum = -1;
8635 bnd0_regnum = mm0_regnum;
8636 if (tdep->num_mmx_regs != 0)
8638 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8639 tdep->mm0_regnum = mm0_regnum;
8640 bnd0_regnum += tdep->num_mmx_regs;
8643 tdep->mm0_regnum = -1;
8645 if (tdep->bnd0r_regnum > 0)
8646 tdep->bnd0_regnum = bnd0_regnum;
8648 tdep-> bnd0_regnum = -1;
8650 /* Hook in the legacy prologue-based unwinders last (fallback). */
8651 frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind);
8652 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
8653 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
8655 /* If we have a register mapping, enable the generic core file
8656 support, unless it has already been enabled. */
8657 if (tdep->gregset_reg_offset
8658 && !gdbarch_iterate_over_regset_sections_p (gdbarch))
8659 set_gdbarch_iterate_over_regset_sections
8660 (gdbarch, i386_iterate_over_regset_sections);
8662 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
8663 i386_fast_tracepoint_valid_at);
8668 static enum gdb_osabi
8669 i386_coff_osabi_sniffer (bfd *abfd)
8671 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
8672 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
8673 return GDB_OSABI_GO32;
8675 return GDB_OSABI_UNKNOWN;
8679 /* Return the target description for a specified XSAVE feature mask. */
8681 const struct target_desc *
8682 i386_target_description (uint64_t xcr0)
8684 switch (xcr0 & X86_XSTATE_ALL_MASK)
8686 case X86_XSTATE_MPX_AVX512_MASK:
8687 case X86_XSTATE_AVX512_MASK:
8688 return tdesc_i386_avx512;
8689 case X86_XSTATE_AVX_MPX_MASK:
8690 return tdesc_i386_avx_mpx;
8691 case X86_XSTATE_MPX_MASK:
8692 return tdesc_i386_mpx;
8693 case X86_XSTATE_AVX_MASK:
8694 return tdesc_i386_avx;
8700 #define MPX_BASE_MASK (~(ULONGEST) 0xfff)
8702 /* Find the bound directory base address. */
8704 static unsigned long
8705 i386_mpx_bd_base (void)
8707 struct regcache *rcache;
8708 struct gdbarch_tdep *tdep;
8710 enum register_status regstatus;
8712 rcache = get_current_regcache ();
8713 tdep = gdbarch_tdep (get_regcache_arch (rcache));
8715 regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret);
8717 if (regstatus != REG_VALID)
8718 error (_("BNDCFGU register invalid, read status %d."), regstatus);
8720 return ret & MPX_BASE_MASK;
8724 i386_mpx_enabled (void)
8726 const struct gdbarch_tdep *tdep = gdbarch_tdep (get_current_arch ());
8727 const struct target_desc *tdesc = tdep->tdesc;
8729 return (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL);
8732 #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */
8733 #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */
8734 #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */
8735 #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */
8737 /* Find the bound table entry given the pointer location and the base
8738 address of the table. */
8741 i386_mpx_get_bt_entry (CORE_ADDR ptr, CORE_ADDR bd_base)
8745 CORE_ADDR mpx_bd_mask, bd_ptr_r_shift, bd_ptr_l_shift;
8746 CORE_ADDR bt_mask, bt_select_r_shift, bt_select_l_shift;
8747 CORE_ADDR bd_entry_addr;
8750 struct gdbarch *gdbarch = get_current_arch ();
8751 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8754 if (gdbarch_ptr_bit (gdbarch) == 64)
8756 mpx_bd_mask = (CORE_ADDR) MPX_BD_MASK;
8757 bd_ptr_r_shift = 20;
8759 bt_select_r_shift = 3;
8760 bt_select_l_shift = 5;
8761 bt_mask = (CORE_ADDR) MPX_BT_MASK;
8763 if ( sizeof (CORE_ADDR) == 4)
8764 error (_("bound table examination not supported\
8765 for 64-bit process with 32-bit GDB"));
8769 mpx_bd_mask = MPX_BD_MASK_32;
8770 bd_ptr_r_shift = 12;
8772 bt_select_r_shift = 2;
8773 bt_select_l_shift = 4;
8774 bt_mask = MPX_BT_MASK_32;
8777 offset1 = ((ptr & mpx_bd_mask) >> bd_ptr_r_shift) << bd_ptr_l_shift;
8778 bd_entry_addr = bd_base + offset1;
8779 bd_entry = read_memory_typed_address (bd_entry_addr, data_ptr_type);
8781 if ((bd_entry & 0x1) == 0)
8782 error (_("Invalid bounds directory entry at %s."),
8783 paddress (get_current_arch (), bd_entry_addr));
8785 /* Clearing status bit. */
8787 bt_addr = bd_entry & ~bt_select_r_shift;
8788 offset2 = ((ptr & bt_mask) >> bt_select_r_shift) << bt_select_l_shift;
8790 return bt_addr + offset2;
8793 /* Print routine for the mpx bounds. */
8796 i386_mpx_print_bounds (const CORE_ADDR bt_entry[4])
8798 struct ui_out *uiout = current_uiout;
8800 struct gdbarch *gdbarch = get_current_arch ();
8801 CORE_ADDR onecompl = ~((CORE_ADDR) 0);
8802 int bounds_in_map = ((~bt_entry[1] == 0 && bt_entry[0] == onecompl) ? 1 : 0);
8804 if (bounds_in_map == 1)
8806 ui_out_text (uiout, "Null bounds on map:");
8807 ui_out_text (uiout, " pointer value = ");
8808 ui_out_field_core_addr (uiout, "pointer-value", gdbarch, bt_entry[2]);
8809 ui_out_text (uiout, ".");
8810 ui_out_text (uiout, "\n");
8814 ui_out_text (uiout, "{lbound = ");
8815 ui_out_field_core_addr (uiout, "lower-bound", gdbarch, bt_entry[0]);
8816 ui_out_text (uiout, ", ubound = ");
8818 /* The upper bound is stored in 1's complement. */
8819 ui_out_field_core_addr (uiout, "upper-bound", gdbarch, ~bt_entry[1]);
8820 ui_out_text (uiout, "}: pointer value = ");
8821 ui_out_field_core_addr (uiout, "pointer-value", gdbarch, bt_entry[2]);
8823 if (gdbarch_ptr_bit (gdbarch) == 64)
8824 size = ( (~(int64_t) bt_entry[1]) - (int64_t) bt_entry[0]);
8826 size = ( ~((int32_t) bt_entry[1]) - (int32_t) bt_entry[0]);
8828 /* In case the bounds are 0x0 and 0xffff... the difference will be -1.
8829 -1 represents in this sense full memory access, and there is no need
8832 size = (size > -1 ? size + 1 : size);
8833 ui_out_text (uiout, ", size = ");
8834 ui_out_field_fmt (uiout, "size", "%s", plongest (size));
8836 ui_out_text (uiout, ", metadata = ");
8837 ui_out_field_core_addr (uiout, "metadata", gdbarch, bt_entry[3]);
8838 ui_out_text (uiout, "\n");
8842 /* Implement the command "show mpx bound". */
8845 i386_mpx_info_bounds (char *args, int from_tty)
8847 CORE_ADDR bd_base = 0;
8849 CORE_ADDR bt_entry_addr = 0;
8850 CORE_ADDR bt_entry[4];
8852 struct gdbarch *gdbarch = get_current_arch ();
8853 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8855 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386
8856 || !i386_mpx_enabled ())
8858 printf_unfiltered (_("Intel Memory Protection Extensions not "
8859 "supported on this target.\n"));
8865 printf_unfiltered (_("Address of pointer variable expected.\n"));
8869 addr = parse_and_eval_address (args);
8871 bd_base = i386_mpx_bd_base ();
8872 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8874 memset (bt_entry, 0, sizeof (bt_entry));
8876 for (i = 0; i < 4; i++)
8877 bt_entry[i] = read_memory_typed_address (bt_entry_addr
8878 + i * TYPE_LENGTH (data_ptr_type),
8881 i386_mpx_print_bounds (bt_entry);
8884 /* Implement the command "set mpx bound". */
8887 i386_mpx_set_bounds (char *args, int from_tty)
8889 CORE_ADDR bd_base = 0;
8890 CORE_ADDR addr, lower, upper;
8891 CORE_ADDR bt_entry_addr = 0;
8892 CORE_ADDR bt_entry[2];
8893 const char *input = args;
8895 struct gdbarch *gdbarch = get_current_arch ();
8896 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8897 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8899 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386
8900 || !i386_mpx_enabled ())
8901 error (_("Intel Memory Protection Extensions not supported\
8905 error (_("Pointer value expected."));
8907 addr = value_as_address (parse_to_comma_and_eval (&input));
8909 if (input[0] == ',')
8911 if (input[0] == '\0')
8912 error (_("wrong number of arguments: missing lower and upper bound."));
8913 lower = value_as_address (parse_to_comma_and_eval (&input));
8915 if (input[0] == ',')
8917 if (input[0] == '\0')
8918 error (_("Wrong number of arguments; Missing upper bound."));
8919 upper = value_as_address (parse_to_comma_and_eval (&input));
8921 bd_base = i386_mpx_bd_base ();
8922 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8923 for (i = 0; i < 2; i++)
8924 bt_entry[i] = read_memory_typed_address (bt_entry_addr
8925 + i * TYPE_LENGTH (data_ptr_type),
8927 bt_entry[0] = (uint64_t) lower;
8928 bt_entry[1] = ~(uint64_t) upper;
8930 for (i = 0; i < 2; i++)
8931 write_memory_unsigned_integer (bt_entry_addr
8932 + i * TYPE_LENGTH (data_ptr_type),
8933 TYPE_LENGTH (data_ptr_type), byte_order,
8937 static struct cmd_list_element *mpx_set_cmdlist, *mpx_show_cmdlist;
8939 /* Helper function for the CLI commands. */
8942 set_mpx_cmd (char *args, int from_tty)
8944 help_list (mpx_set_cmdlist, "set mpx ", all_commands, gdb_stdout);
8947 /* Helper function for the CLI commands. */
8950 show_mpx_cmd (char *args, int from_tty)
8952 cmd_show_list (mpx_show_cmdlist, from_tty, "");
8955 /* Provide a prototype to silence -Wmissing-prototypes. */
8956 void _initialize_i386_tdep (void);
8959 _initialize_i386_tdep (void)
8961 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
8963 /* Add the variable that controls the disassembly flavor. */
8964 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
8965 &disassembly_flavor, _("\
8966 Set the disassembly flavor."), _("\
8967 Show the disassembly flavor."), _("\
8968 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
8970 NULL, /* FIXME: i18n: */
8971 &setlist, &showlist);
8973 /* Add the variable that controls the convention for returning
8975 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
8976 &struct_convention, _("\
8977 Set the convention for returning small structs."), _("\
8978 Show the convention for returning small structs."), _("\
8979 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
8982 NULL, /* FIXME: i18n: */
8983 &setlist, &showlist);
8985 /* Add "mpx" prefix for the set commands. */
8987 add_prefix_cmd ("mpx", class_support, set_mpx_cmd, _("\
8988 Set Intel Memory Protection Extensions specific variables."),
8989 &mpx_set_cmdlist, "set mpx ",
8990 0 /* allow-unknown */, &setlist);
8992 /* Add "mpx" prefix for the show commands. */
8994 add_prefix_cmd ("mpx", class_support, show_mpx_cmd, _("\
8995 Show Intel Memory Protection Extensions specific variables."),
8996 &mpx_show_cmdlist, "show mpx ",
8997 0 /* allow-unknown */, &showlist);
8999 /* Add "bound" command for the show mpx commands list. */
9001 add_cmd ("bound", no_class, i386_mpx_info_bounds,
9002 "Show the memory bounds for a given array/pointer storage\
9003 in the bound table.",
9006 /* Add "bound" command for the set mpx commands list. */
9008 add_cmd ("bound", no_class, i386_mpx_set_bounds,
9009 "Set the memory bounds for a given array/pointer storage\
9010 in the bound table.",
9013 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
9014 i386_coff_osabi_sniffer);
9016 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
9017 i386_svr4_init_abi);
9018 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
9019 i386_go32_init_abi);
9021 /* Initialize the i386-specific register groups. */
9022 i386_init_reggroups ();
9024 /* Initialize the standard target descriptions. */
9025 initialize_tdesc_i386 ();
9026 initialize_tdesc_i386_mmx ();
9027 initialize_tdesc_i386_avx ();
9028 initialize_tdesc_i386_mpx ();
9029 initialize_tdesc_i386_avx_mpx ();
9030 initialize_tdesc_i386_avx512 ();
9032 /* Tell remote stub that we support XML target description. */
9033 register_remote_support_xml ("i386");