1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
37 #include "reggroups.h"
46 #include "exceptions.h"
47 #include "gdb_assert.h"
48 #include "gdb_string.h"
50 #include "i386-tdep.h"
51 #include "i387-tdep.h"
52 #include "i386-xstate.h"
57 #include "features/i386/i386.c"
58 #include "features/i386/i386-avx.c"
59 #include "features/i386/i386-mmx.c"
64 #include "stap-probe.h"
65 #include "user-regs.h"
66 #include "cli/cli-utils.h"
67 #include "expression.h"
68 #include "parser-defs.h"
73 static const char *i386_register_names[] =
75 "eax", "ecx", "edx", "ebx",
76 "esp", "ebp", "esi", "edi",
77 "eip", "eflags", "cs", "ss",
78 "ds", "es", "fs", "gs",
79 "st0", "st1", "st2", "st3",
80 "st4", "st5", "st6", "st7",
81 "fctrl", "fstat", "ftag", "fiseg",
82 "fioff", "foseg", "fooff", "fop",
83 "xmm0", "xmm1", "xmm2", "xmm3",
84 "xmm4", "xmm5", "xmm6", "xmm7",
88 static const char *i386_ymm_names[] =
90 "ymm0", "ymm1", "ymm2", "ymm3",
91 "ymm4", "ymm5", "ymm6", "ymm7",
94 static const char *i386_ymmh_names[] =
96 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
97 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
100 /* Register names for MMX pseudo-registers. */
102 static const char *i386_mmx_names[] =
104 "mm0", "mm1", "mm2", "mm3",
105 "mm4", "mm5", "mm6", "mm7"
108 /* Register names for byte pseudo-registers. */
110 static const char *i386_byte_names[] =
112 "al", "cl", "dl", "bl",
113 "ah", "ch", "dh", "bh"
116 /* Register names for word pseudo-registers. */
118 static const char *i386_word_names[] =
120 "ax", "cx", "dx", "bx",
127 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
129 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
130 int mm0_regnum = tdep->mm0_regnum;
135 regnum -= mm0_regnum;
136 return regnum >= 0 && regnum < tdep->num_mmx_regs;
142 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
144 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
146 regnum -= tdep->al_regnum;
147 return regnum >= 0 && regnum < tdep->num_byte_regs;
153 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
155 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
157 regnum -= tdep->ax_regnum;
158 return regnum >= 0 && regnum < tdep->num_word_regs;
161 /* Dword register? */
164 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
166 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
167 int eax_regnum = tdep->eax_regnum;
172 regnum -= eax_regnum;
173 return regnum >= 0 && regnum < tdep->num_dword_regs;
177 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
179 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
180 int ymm0h_regnum = tdep->ymm0h_regnum;
182 if (ymm0h_regnum < 0)
185 regnum -= ymm0h_regnum;
186 return regnum >= 0 && regnum < tdep->num_ymm_regs;
192 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
194 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
195 int ymm0_regnum = tdep->ymm0_regnum;
200 regnum -= ymm0_regnum;
201 return regnum >= 0 && regnum < tdep->num_ymm_regs;
207 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
209 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
210 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
212 if (num_xmm_regs == 0)
215 regnum -= I387_XMM0_REGNUM (tdep);
216 return regnum >= 0 && regnum < num_xmm_regs;
220 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
222 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
224 if (I387_NUM_XMM_REGS (tdep) == 0)
227 return (regnum == I387_MXCSR_REGNUM (tdep));
233 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
235 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
237 if (I387_ST0_REGNUM (tdep) < 0)
240 return (I387_ST0_REGNUM (tdep) <= regnum
241 && regnum < I387_FCTRL_REGNUM (tdep));
245 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
247 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
249 if (I387_ST0_REGNUM (tdep) < 0)
252 return (I387_FCTRL_REGNUM (tdep) <= regnum
253 && regnum < I387_XMM0_REGNUM (tdep));
256 /* Return the name of register REGNUM, or the empty string if it is
257 an anonymous register. */
260 i386_register_name (struct gdbarch *gdbarch, int regnum)
262 /* Hide the upper YMM registers. */
263 if (i386_ymmh_regnum_p (gdbarch, regnum))
266 return tdesc_register_name (gdbarch, regnum);
269 /* Return the name of register REGNUM. */
272 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
274 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
275 if (i386_mmx_regnum_p (gdbarch, regnum))
276 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
277 else if (i386_ymm_regnum_p (gdbarch, regnum))
278 return i386_ymm_names[regnum - tdep->ymm0_regnum];
279 else if (i386_byte_regnum_p (gdbarch, regnum))
280 return i386_byte_names[regnum - tdep->al_regnum];
281 else if (i386_word_regnum_p (gdbarch, regnum))
282 return i386_word_names[regnum - tdep->ax_regnum];
284 internal_error (__FILE__, __LINE__, _("invalid regnum"));
287 /* Convert a dbx register number REG to the appropriate register
288 number used by GDB. */
291 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
293 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
295 /* This implements what GCC calls the "default" register map
296 (dbx_register_map[]). */
298 if (reg >= 0 && reg <= 7)
300 /* General-purpose registers. The debug info calls %ebp
301 register 4, and %esp register 5. */
308 else if (reg >= 12 && reg <= 19)
310 /* Floating-point registers. */
311 return reg - 12 + I387_ST0_REGNUM (tdep);
313 else if (reg >= 21 && reg <= 28)
316 int ymm0_regnum = tdep->ymm0_regnum;
319 && i386_xmm_regnum_p (gdbarch, reg))
320 return reg - 21 + ymm0_regnum;
322 return reg - 21 + I387_XMM0_REGNUM (tdep);
324 else if (reg >= 29 && reg <= 36)
327 return reg - 29 + I387_MM0_REGNUM (tdep);
330 /* This will hopefully provoke a warning. */
331 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
334 /* Convert SVR4 register number REG to the appropriate register number
338 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
340 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
342 /* This implements the GCC register map that tries to be compatible
343 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
345 /* The SVR4 register numbering includes %eip and %eflags, and
346 numbers the floating point registers differently. */
347 if (reg >= 0 && reg <= 9)
349 /* General-purpose registers. */
352 else if (reg >= 11 && reg <= 18)
354 /* Floating-point registers. */
355 return reg - 11 + I387_ST0_REGNUM (tdep);
357 else if (reg >= 21 && reg <= 36)
359 /* The SSE and MMX registers have the same numbers as with dbx. */
360 return i386_dbx_reg_to_regnum (gdbarch, reg);
365 case 37: return I387_FCTRL_REGNUM (tdep);
366 case 38: return I387_FSTAT_REGNUM (tdep);
367 case 39: return I387_MXCSR_REGNUM (tdep);
368 case 40: return I386_ES_REGNUM;
369 case 41: return I386_CS_REGNUM;
370 case 42: return I386_SS_REGNUM;
371 case 43: return I386_DS_REGNUM;
372 case 44: return I386_FS_REGNUM;
373 case 45: return I386_GS_REGNUM;
376 /* This will hopefully provoke a warning. */
377 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
382 /* This is the variable that is set with "set disassembly-flavor", and
383 its legitimate values. */
384 static const char att_flavor[] = "att";
385 static const char intel_flavor[] = "intel";
386 static const char *const valid_flavors[] =
392 static const char *disassembly_flavor = att_flavor;
395 /* Use the program counter to determine the contents and size of a
396 breakpoint instruction. Return a pointer to a string of bytes that
397 encode a breakpoint instruction, store the length of the string in
398 *LEN and optionally adjust *PC to point to the correct memory
399 location for inserting the breakpoint.
401 On the i386 we have a single breakpoint that fits in a single byte
402 and can be inserted anywhere.
404 This function is 64-bit safe. */
406 static const gdb_byte *
407 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
409 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */
411 *len = sizeof (break_insn);
415 /* Displaced instruction handling. */
417 /* Skip the legacy instruction prefixes in INSN.
418 Not all prefixes are valid for any particular insn
419 but we needn't care, the insn will fault if it's invalid.
420 The result is a pointer to the first opcode byte,
421 or NULL if we run off the end of the buffer. */
424 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
426 gdb_byte *end = insn + max_len;
432 case DATA_PREFIX_OPCODE:
433 case ADDR_PREFIX_OPCODE:
434 case CS_PREFIX_OPCODE:
435 case DS_PREFIX_OPCODE:
436 case ES_PREFIX_OPCODE:
437 case FS_PREFIX_OPCODE:
438 case GS_PREFIX_OPCODE:
439 case SS_PREFIX_OPCODE:
440 case LOCK_PREFIX_OPCODE:
441 case REPE_PREFIX_OPCODE:
442 case REPNE_PREFIX_OPCODE:
454 i386_absolute_jmp_p (const gdb_byte *insn)
456 /* jmp far (absolute address in operand). */
462 /* jump near, absolute indirect (/4). */
463 if ((insn[1] & 0x38) == 0x20)
466 /* jump far, absolute indirect (/5). */
467 if ((insn[1] & 0x38) == 0x28)
475 i386_absolute_call_p (const gdb_byte *insn)
477 /* call far, absolute. */
483 /* Call near, absolute indirect (/2). */
484 if ((insn[1] & 0x38) == 0x10)
487 /* Call far, absolute indirect (/3). */
488 if ((insn[1] & 0x38) == 0x18)
496 i386_ret_p (const gdb_byte *insn)
500 case 0xc2: /* ret near, pop N bytes. */
501 case 0xc3: /* ret near */
502 case 0xca: /* ret far, pop N bytes. */
503 case 0xcb: /* ret far */
504 case 0xcf: /* iret */
513 i386_call_p (const gdb_byte *insn)
515 if (i386_absolute_call_p (insn))
518 /* call near, relative. */
525 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
526 length in bytes. Otherwise, return zero. */
529 i386_syscall_p (const gdb_byte *insn, int *lengthp)
531 /* Is it 'int $0x80'? */
532 if ((insn[0] == 0xcd && insn[1] == 0x80)
533 /* Or is it 'sysenter'? */
534 || (insn[0] == 0x0f && insn[1] == 0x34)
535 /* Or is it 'syscall'? */
536 || (insn[0] == 0x0f && insn[1] == 0x05))
545 /* Some kernels may run one past a syscall insn, so we have to cope.
546 Otherwise this is just simple_displaced_step_copy_insn. */
548 struct displaced_step_closure *
549 i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
550 CORE_ADDR from, CORE_ADDR to,
551 struct regcache *regs)
553 size_t len = gdbarch_max_insn_length (gdbarch);
554 gdb_byte *buf = xmalloc (len);
556 read_memory (from, buf, len);
558 /* GDB may get control back after the insn after the syscall.
559 Presumably this is a kernel bug.
560 If this is a syscall, make sure there's a nop afterwards. */
565 insn = i386_skip_prefixes (buf, len);
566 if (insn != NULL && i386_syscall_p (insn, &syscall_length))
567 insn[syscall_length] = NOP_OPCODE;
570 write_memory (to, buf, len);
574 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
575 paddress (gdbarch, from), paddress (gdbarch, to));
576 displaced_step_dump_bytes (gdb_stdlog, buf, len);
579 return (struct displaced_step_closure *) buf;
582 /* Fix up the state of registers and memory after having single-stepped
583 a displaced instruction. */
586 i386_displaced_step_fixup (struct gdbarch *gdbarch,
587 struct displaced_step_closure *closure,
588 CORE_ADDR from, CORE_ADDR to,
589 struct regcache *regs)
591 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
593 /* The offset we applied to the instruction's address.
594 This could well be negative (when viewed as a signed 32-bit
595 value), but ULONGEST won't reflect that, so take care when
597 ULONGEST insn_offset = to - from;
599 /* Since we use simple_displaced_step_copy_insn, our closure is a
600 copy of the instruction. */
601 gdb_byte *insn = (gdb_byte *) closure;
602 /* The start of the insn, needed in case we see some prefixes. */
603 gdb_byte *insn_start = insn;
606 fprintf_unfiltered (gdb_stdlog,
607 "displaced: fixup (%s, %s), "
608 "insn = 0x%02x 0x%02x ...\n",
609 paddress (gdbarch, from), paddress (gdbarch, to),
612 /* The list of issues to contend with here is taken from
613 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
614 Yay for Free Software! */
616 /* Relocate the %eip, if necessary. */
618 /* The instruction recognizers we use assume any leading prefixes
619 have been skipped. */
621 /* This is the size of the buffer in closure. */
622 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
623 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
624 /* If there are too many prefixes, just ignore the insn.
625 It will fault when run. */
630 /* Except in the case of absolute or indirect jump or call
631 instructions, or a return instruction, the new eip is relative to
632 the displaced instruction; make it relative. Well, signal
633 handler returns don't need relocation either, but we use the
634 value of %eip to recognize those; see below. */
635 if (! i386_absolute_jmp_p (insn)
636 && ! i386_absolute_call_p (insn)
637 && ! i386_ret_p (insn))
642 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
644 /* A signal trampoline system call changes the %eip, resuming
645 execution of the main program after the signal handler has
646 returned. That makes them like 'return' instructions; we
647 shouldn't relocate %eip.
649 But most system calls don't, and we do need to relocate %eip.
651 Our heuristic for distinguishing these cases: if stepping
652 over the system call instruction left control directly after
653 the instruction, the we relocate --- control almost certainly
654 doesn't belong in the displaced copy. Otherwise, we assume
655 the instruction has put control where it belongs, and leave
656 it unrelocated. Goodness help us if there are PC-relative
658 if (i386_syscall_p (insn, &insn_len)
659 && orig_eip != to + (insn - insn_start) + insn_len
660 /* GDB can get control back after the insn after the syscall.
661 Presumably this is a kernel bug.
662 i386_displaced_step_copy_insn ensures its a nop,
663 we add one to the length for it. */
664 && orig_eip != to + (insn - insn_start) + insn_len + 1)
667 fprintf_unfiltered (gdb_stdlog,
668 "displaced: syscall changed %%eip; "
673 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
675 /* If we just stepped over a breakpoint insn, we don't backup
676 the pc on purpose; this is to match behaviour without
679 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
682 fprintf_unfiltered (gdb_stdlog,
684 "relocated %%eip from %s to %s\n",
685 paddress (gdbarch, orig_eip),
686 paddress (gdbarch, eip));
690 /* If the instruction was PUSHFL, then the TF bit will be set in the
691 pushed value, and should be cleared. We'll leave this for later,
692 since GDB already messes up the TF flag when stepping over a
695 /* If the instruction was a call, the return address now atop the
696 stack is the address following the copied instruction. We need
697 to make it the address following the original instruction. */
698 if (i386_call_p (insn))
702 const ULONGEST retaddr_len = 4;
704 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
705 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
706 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
707 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
710 fprintf_unfiltered (gdb_stdlog,
711 "displaced: relocated return addr at %s to %s\n",
712 paddress (gdbarch, esp),
713 paddress (gdbarch, retaddr));
718 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
720 target_write_memory (*to, buf, len);
725 i386_relocate_instruction (struct gdbarch *gdbarch,
726 CORE_ADDR *to, CORE_ADDR oldloc)
728 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
729 gdb_byte buf[I386_MAX_INSN_LEN];
730 int offset = 0, rel32, newrel;
732 gdb_byte *insn = buf;
734 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
736 insn_length = gdb_buffered_insn_length (gdbarch, insn,
737 I386_MAX_INSN_LEN, oldloc);
739 /* Get past the prefixes. */
740 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
742 /* Adjust calls with 32-bit relative addresses as push/jump, with
743 the address pushed being the location where the original call in
744 the user program would return to. */
747 gdb_byte push_buf[16];
748 unsigned int ret_addr;
750 /* Where "ret" in the original code will return to. */
751 ret_addr = oldloc + insn_length;
752 push_buf[0] = 0x68; /* pushq $... */
753 memcpy (&push_buf[1], &ret_addr, 4);
755 append_insns (to, 5, push_buf);
757 /* Convert the relative call to a relative jump. */
760 /* Adjust the destination offset. */
761 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
762 newrel = (oldloc - *to) + rel32;
763 store_signed_integer (insn + 1, 4, byte_order, newrel);
766 fprintf_unfiltered (gdb_stdlog,
767 "Adjusted insn rel32=%s at %s to"
769 hex_string (rel32), paddress (gdbarch, oldloc),
770 hex_string (newrel), paddress (gdbarch, *to));
772 /* Write the adjusted jump into its displaced location. */
773 append_insns (to, 5, insn);
777 /* Adjust jumps with 32-bit relative addresses. Calls are already
781 /* Adjust conditional jumps. */
782 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
787 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
788 newrel = (oldloc - *to) + rel32;
789 store_signed_integer (insn + offset, 4, byte_order, newrel);
791 fprintf_unfiltered (gdb_stdlog,
792 "Adjusted insn rel32=%s at %s to"
794 hex_string (rel32), paddress (gdbarch, oldloc),
795 hex_string (newrel), paddress (gdbarch, *to));
798 /* Write the adjusted instructions into their displaced
800 append_insns (to, insn_length, buf);
804 #ifdef I386_REGNO_TO_SYMMETRY
805 #error "The Sequent Symmetry is no longer supported."
808 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
809 and %esp "belong" to the calling function. Therefore these
810 registers should be saved if they're going to be modified. */
812 /* The maximum number of saved registers. This should include all
813 registers mentioned above, and %eip. */
814 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
816 struct i386_frame_cache
824 /* Saved registers. */
825 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
830 /* Stack space reserved for local variables. */
834 /* Allocate and initialize a frame cache. */
836 static struct i386_frame_cache *
837 i386_alloc_frame_cache (void)
839 struct i386_frame_cache *cache;
842 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
847 cache->sp_offset = -4;
850 /* Saved registers. We initialize these to -1 since zero is a valid
851 offset (that's where %ebp is supposed to be stored). */
852 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
853 cache->saved_regs[i] = -1;
855 cache->saved_sp_reg = -1;
856 cache->pc_in_eax = 0;
858 /* Frameless until proven otherwise. */
864 /* If the instruction at PC is a jump, return the address of its
865 target. Otherwise, return PC. */
868 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
870 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
875 if (target_read_memory (pc, &op, 1))
881 op = read_memory_unsigned_integer (pc + 1, 1, byte_order);
887 /* Relative jump: if data16 == 0, disp32, else disp16. */
890 delta = read_memory_integer (pc + 2, 2, byte_order);
892 /* Include the size of the jmp instruction (including the
898 delta = read_memory_integer (pc + 1, 4, byte_order);
900 /* Include the size of the jmp instruction. */
905 /* Relative jump, disp8 (ignore data16). */
906 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
915 /* Check whether PC points at a prologue for a function returning a
916 structure or union. If so, it updates CACHE and returns the
917 address of the first instruction after the code sequence that
918 removes the "hidden" argument from the stack or CURRENT_PC,
919 whichever is smaller. Otherwise, return PC. */
922 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
923 struct i386_frame_cache *cache)
925 /* Functions that return a structure or union start with:
928 xchgl %eax, (%esp) 0x87 0x04 0x24
929 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
931 (the System V compiler puts out the second `xchg' instruction,
932 and the assembler doesn't try to optimize it, so the 'sib' form
933 gets generated). This sequence is used to get the address of the
934 return buffer for a function that returns a structure. */
935 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
936 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
940 if (current_pc <= pc)
943 if (target_read_memory (pc, &op, 1))
946 if (op != 0x58) /* popl %eax */
949 if (target_read_memory (pc + 1, buf, 4))
952 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
955 if (current_pc == pc)
957 cache->sp_offset += 4;
961 if (current_pc == pc + 1)
963 cache->pc_in_eax = 1;
967 if (buf[1] == proto1[1])
974 i386_skip_probe (CORE_ADDR pc)
976 /* A function may start with
990 if (target_read_memory (pc, &op, 1))
993 if (op == 0x68 || op == 0x6a)
997 /* Skip past the `pushl' instruction; it has either a one-byte or a
998 four-byte operand, depending on the opcode. */
1004 /* Read the following 8 bytes, which should be `call _probe' (6
1005 bytes) followed by `addl $4,%esp' (2 bytes). */
1006 read_memory (pc + delta, buf, sizeof (buf));
1007 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
1008 pc += delta + sizeof (buf);
1014 /* GCC 4.1 and later, can put code in the prologue to realign the
1015 stack pointer. Check whether PC points to such code, and update
1016 CACHE accordingly. Return the first instruction after the code
1017 sequence or CURRENT_PC, whichever is smaller. If we don't
1018 recognize the code, return PC. */
1021 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1022 struct i386_frame_cache *cache)
1024 /* There are 2 code sequences to re-align stack before the frame
1027 1. Use a caller-saved saved register:
1033 2. Use a callee-saved saved register:
1040 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1042 0x83 0xe4 0xf0 andl $-16, %esp
1043 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1048 int offset, offset_and;
1049 static int regnums[8] = {
1050 I386_EAX_REGNUM, /* %eax */
1051 I386_ECX_REGNUM, /* %ecx */
1052 I386_EDX_REGNUM, /* %edx */
1053 I386_EBX_REGNUM, /* %ebx */
1054 I386_ESP_REGNUM, /* %esp */
1055 I386_EBP_REGNUM, /* %ebp */
1056 I386_ESI_REGNUM, /* %esi */
1057 I386_EDI_REGNUM /* %edi */
1060 if (target_read_memory (pc, buf, sizeof buf))
1063 /* Check caller-saved saved register. The first instruction has
1064 to be "leal 4(%esp), %reg". */
1065 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1067 /* MOD must be binary 10 and R/M must be binary 100. */
1068 if ((buf[1] & 0xc7) != 0x44)
1071 /* REG has register number. */
1072 reg = (buf[1] >> 3) & 7;
1077 /* Check callee-saved saved register. The first instruction
1078 has to be "pushl %reg". */
1079 if ((buf[0] & 0xf8) != 0x50)
1085 /* The next instruction has to be "leal 8(%esp), %reg". */
1086 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1089 /* MOD must be binary 10 and R/M must be binary 100. */
1090 if ((buf[2] & 0xc7) != 0x44)
1093 /* REG has register number. Registers in pushl and leal have to
1095 if (reg != ((buf[2] >> 3) & 7))
1101 /* Rigister can't be %esp nor %ebp. */
1102 if (reg == 4 || reg == 5)
1105 /* The next instruction has to be "andl $-XXX, %esp". */
1106 if (buf[offset + 1] != 0xe4
1107 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1110 offset_and = offset;
1111 offset += buf[offset] == 0x81 ? 6 : 3;
1113 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1114 0xfc. REG must be binary 110 and MOD must be binary 01. */
1115 if (buf[offset] != 0xff
1116 || buf[offset + 2] != 0xfc
1117 || (buf[offset + 1] & 0xf8) != 0x70)
1120 /* R/M has register. Registers in leal and pushl have to be the
1122 if (reg != (buf[offset + 1] & 7))
1125 if (current_pc > pc + offset_and)
1126 cache->saved_sp_reg = regnums[reg];
1128 return min (pc + offset + 3, current_pc);
1131 /* Maximum instruction length we need to handle. */
1132 #define I386_MAX_MATCHED_INSN_LEN 6
1134 /* Instruction description. */
1138 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
1139 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
1142 /* Return whether instruction at PC matches PATTERN. */
1145 i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern)
1149 if (target_read_memory (pc, &op, 1))
1152 if ((op & pattern.mask[0]) == pattern.insn[0])
1154 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1155 int insn_matched = 1;
1158 gdb_assert (pattern.len > 1);
1159 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN);
1161 if (target_read_memory (pc + 1, buf, pattern.len - 1))
1164 for (i = 1; i < pattern.len; i++)
1166 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i])
1169 return insn_matched;
1174 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1175 the first instruction description that matches. Otherwise, return
1178 static struct i386_insn *
1179 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns)
1181 struct i386_insn *pattern;
1183 for (pattern = insn_patterns; pattern->len > 0; pattern++)
1185 if (i386_match_pattern (pc, *pattern))
1192 /* Return whether PC points inside a sequence of instructions that
1193 matches INSN_PATTERNS. */
1196 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns)
1198 CORE_ADDR current_pc;
1201 struct i386_insn *insn;
1203 insn = i386_match_insn (pc, insn_patterns);
1208 ix = insn - insn_patterns;
1209 for (i = ix - 1; i >= 0; i--)
1211 current_pc -= insn_patterns[i].len;
1213 if (!i386_match_pattern (current_pc, insn_patterns[i]))
1217 current_pc = pc + insn->len;
1218 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++)
1220 if (!i386_match_pattern (current_pc, *insn))
1223 current_pc += insn->len;
1229 /* Some special instructions that might be migrated by GCC into the
1230 part of the prologue that sets up the new stack frame. Because the
1231 stack frame hasn't been setup yet, no registers have been saved
1232 yet, and only the scratch registers %eax, %ecx and %edx can be
1235 struct i386_insn i386_frame_setup_skip_insns[] =
1237 /* Check for `movb imm8, r' and `movl imm32, r'.
1239 ??? Should we handle 16-bit operand-sizes here? */
1241 /* `movb imm8, %al' and `movb imm8, %ah' */
1242 /* `movb imm8, %cl' and `movb imm8, %ch' */
1243 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1244 /* `movb imm8, %dl' and `movb imm8, %dh' */
1245 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1246 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1247 { 5, { 0xb8 }, { 0xfe } },
1248 /* `movl imm32, %edx' */
1249 { 5, { 0xba }, { 0xff } },
1251 /* Check for `mov imm32, r32'. Note that there is an alternative
1252 encoding for `mov m32, %eax'.
1254 ??? Should we handle SIB adressing here?
1255 ??? Should we handle 16-bit operand-sizes here? */
1257 /* `movl m32, %eax' */
1258 { 5, { 0xa1 }, { 0xff } },
1259 /* `movl m32, %eax' and `mov; m32, %ecx' */
1260 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1261 /* `movl m32, %edx' */
1262 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1264 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1265 Because of the symmetry, there are actually two ways to encode
1266 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1267 opcode bytes 0x31 and 0x33 for `xorl'. */
1269 /* `subl %eax, %eax' */
1270 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1271 /* `subl %ecx, %ecx' */
1272 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1273 /* `subl %edx, %edx' */
1274 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1275 /* `xorl %eax, %eax' */
1276 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1277 /* `xorl %ecx, %ecx' */
1278 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1279 /* `xorl %edx, %edx' */
1280 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1285 /* Check whether PC points to a no-op instruction. */
1287 i386_skip_noop (CORE_ADDR pc)
1292 if (target_read_memory (pc, &op, 1))
1298 /* Ignore `nop' instruction. */
1302 if (target_read_memory (pc, &op, 1))
1306 /* Ignore no-op instruction `mov %edi, %edi'.
1307 Microsoft system dlls often start with
1308 a `mov %edi,%edi' instruction.
1309 The 5 bytes before the function start are
1310 filled with `nop' instructions.
1311 This pattern can be used for hot-patching:
1312 The `mov %edi, %edi' instruction can be replaced by a
1313 near jump to the location of the 5 `nop' instructions
1314 which can be replaced by a 32-bit jump to anywhere
1315 in the 32-bit address space. */
1317 else if (op == 0x8b)
1319 if (target_read_memory (pc + 1, &op, 1))
1325 if (target_read_memory (pc, &op, 1))
1335 /* Check whether PC points at a code that sets up a new stack frame.
1336 If so, it updates CACHE and returns the address of the first
1337 instruction after the sequence that sets up the frame or LIMIT,
1338 whichever is smaller. If we don't recognize the code, return PC. */
1341 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1342 CORE_ADDR pc, CORE_ADDR limit,
1343 struct i386_frame_cache *cache)
1345 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1346 struct i386_insn *insn;
1353 if (target_read_memory (pc, &op, 1))
1356 if (op == 0x55) /* pushl %ebp */
1358 /* Take into account that we've executed the `pushl %ebp' that
1359 starts this instruction sequence. */
1360 cache->saved_regs[I386_EBP_REGNUM] = 0;
1361 cache->sp_offset += 4;
1364 /* If that's all, return now. */
1368 /* Check for some special instructions that might be migrated by
1369 GCC into the prologue and skip them. At this point in the
1370 prologue, code should only touch the scratch registers %eax,
1371 %ecx and %edx, so while the number of posibilities is sheer,
1374 Make sure we only skip these instructions if we later see the
1375 `movl %esp, %ebp' that actually sets up the frame. */
1376 while (pc + skip < limit)
1378 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1385 /* If that's all, return now. */
1386 if (limit <= pc + skip)
1389 if (target_read_memory (pc + skip, &op, 1))
1392 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1396 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1401 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1409 /* OK, we actually have a frame. We just don't know how large
1410 it is yet. Set its size to zero. We'll adjust it if
1411 necessary. We also now commit to skipping the special
1412 instructions mentioned before. */
1416 /* If that's all, return now. */
1420 /* Check for stack adjustment
1424 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1425 reg, so we don't have to worry about a data16 prefix. */
1426 if (target_read_memory (pc, &op, 1))
1430 /* `subl' with 8-bit immediate. */
1431 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1432 /* Some instruction starting with 0x83 other than `subl'. */
1435 /* `subl' with signed 8-bit immediate (though it wouldn't
1436 make sense to be negative). */
1437 cache->locals = read_memory_integer (pc + 2, 1, byte_order);
1440 else if (op == 0x81)
1442 /* Maybe it is `subl' with a 32-bit immediate. */
1443 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1444 /* Some instruction starting with 0x81 other than `subl'. */
1447 /* It is `subl' with a 32-bit immediate. */
1448 cache->locals = read_memory_integer (pc + 2, 4, byte_order);
1453 /* Some instruction other than `subl'. */
1457 else if (op == 0xc8) /* enter */
1459 cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order);
1466 /* Check whether PC points at code that saves registers on the stack.
1467 If so, it updates CACHE and returns the address of the first
1468 instruction after the register saves or CURRENT_PC, whichever is
1469 smaller. Otherwise, return PC. */
1472 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1473 struct i386_frame_cache *cache)
1475 CORE_ADDR offset = 0;
1479 if (cache->locals > 0)
1480 offset -= cache->locals;
1481 for (i = 0; i < 8 && pc < current_pc; i++)
1483 if (target_read_memory (pc, &op, 1))
1485 if (op < 0x50 || op > 0x57)
1489 cache->saved_regs[op - 0x50] = offset;
1490 cache->sp_offset += 4;
1497 /* Do a full analysis of the prologue at PC and update CACHE
1498 accordingly. Bail out early if CURRENT_PC is reached. Return the
1499 address where the analysis stopped.
1501 We handle these cases:
1503 The startup sequence can be at the start of the function, or the
1504 function can start with a branch to startup code at the end.
1506 %ebp can be set up with either the 'enter' instruction, or "pushl
1507 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1508 once used in the System V compiler).
1510 Local space is allocated just below the saved %ebp by either the
1511 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1512 16-bit unsigned argument for space to allocate, and the 'addl'
1513 instruction could have either a signed byte, or 32-bit immediate.
1515 Next, the registers used by this function are pushed. With the
1516 System V compiler they will always be in the order: %edi, %esi,
1517 %ebx (and sometimes a harmless bug causes it to also save but not
1518 restore %eax); however, the code below is willing to see the pushes
1519 in any order, and will handle up to 8 of them.
1521 If the setup sequence is at the end of the function, then the next
1522 instruction will be a branch back to the start. */
1525 i386_analyze_prologue (struct gdbarch *gdbarch,
1526 CORE_ADDR pc, CORE_ADDR current_pc,
1527 struct i386_frame_cache *cache)
1529 pc = i386_skip_noop (pc);
1530 pc = i386_follow_jump (gdbarch, pc);
1531 pc = i386_analyze_struct_return (pc, current_pc, cache);
1532 pc = i386_skip_probe (pc);
1533 pc = i386_analyze_stack_align (pc, current_pc, cache);
1534 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1535 return i386_analyze_register_saves (pc, current_pc, cache);
1538 /* Return PC of first real instruction. */
1541 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1543 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1545 static gdb_byte pic_pat[6] =
1547 0xe8, 0, 0, 0, 0, /* call 0x0 */
1548 0x5b, /* popl %ebx */
1550 struct i386_frame_cache cache;
1556 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1557 if (cache.locals < 0)
1560 /* Found valid frame setup. */
1562 /* The native cc on SVR4 in -K PIC mode inserts the following code
1563 to get the address of the global offset table (GOT) into register
1568 movl %ebx,x(%ebp) (optional)
1571 This code is with the rest of the prologue (at the end of the
1572 function), so we have to skip it to get to the first real
1573 instruction at the start of the function. */
1575 for (i = 0; i < 6; i++)
1577 if (target_read_memory (pc + i, &op, 1))
1580 if (pic_pat[i] != op)
1587 if (target_read_memory (pc + delta, &op, 1))
1590 if (op == 0x89) /* movl %ebx, x(%ebp) */
1592 op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order);
1594 if (op == 0x5d) /* One byte offset from %ebp. */
1596 else if (op == 0x9d) /* Four byte offset from %ebp. */
1598 else /* Unexpected instruction. */
1601 if (target_read_memory (pc + delta, &op, 1))
1606 if (delta > 0 && op == 0x81
1607 && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order)
1614 /* If the function starts with a branch (to startup code at the end)
1615 the last instruction should bring us back to the first
1616 instruction of the real code. */
1617 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1618 pc = i386_follow_jump (gdbarch, pc);
1623 /* Check that the code pointed to by PC corresponds to a call to
1624 __main, skip it if so. Return PC otherwise. */
1627 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1629 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1632 if (target_read_memory (pc, &op, 1))
1638 if (target_read_memory (pc + 1, buf, sizeof buf) == 0)
1640 /* Make sure address is computed correctly as a 32bit
1641 integer even if CORE_ADDR is 64 bit wide. */
1642 struct minimal_symbol *s;
1643 CORE_ADDR call_dest;
1645 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1646 call_dest = call_dest & 0xffffffffU;
1647 s = lookup_minimal_symbol_by_pc (call_dest);
1649 && SYMBOL_LINKAGE_NAME (s) != NULL
1650 && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0)
1658 /* This function is 64-bit safe. */
1661 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1665 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1666 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1670 /* Normal frames. */
1673 i386_frame_cache_1 (struct frame_info *this_frame,
1674 struct i386_frame_cache *cache)
1676 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1677 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1681 cache->pc = get_frame_func (this_frame);
1683 /* In principle, for normal frames, %ebp holds the frame pointer,
1684 which holds the base address for the current stack frame.
1685 However, for functions that don't need it, the frame pointer is
1686 optional. For these "frameless" functions the frame pointer is
1687 actually the frame pointer of the calling frame. Signal
1688 trampolines are just a special case of a "frameless" function.
1689 They (usually) share their frame pointer with the frame that was
1690 in progress when the signal occurred. */
1692 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1693 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1694 if (cache->base == 0)
1700 /* For normal frames, %eip is stored at 4(%ebp). */
1701 cache->saved_regs[I386_EIP_REGNUM] = 4;
1704 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
1707 if (cache->locals < 0)
1709 /* We didn't find a valid frame, which means that CACHE->base
1710 currently holds the frame pointer for our calling frame. If
1711 we're at the start of a function, or somewhere half-way its
1712 prologue, the function's frame probably hasn't been fully
1713 setup yet. Try to reconstruct the base address for the stack
1714 frame by looking at the stack pointer. For truly "frameless"
1715 functions this might work too. */
1717 if (cache->saved_sp_reg != -1)
1719 /* Saved stack pointer has been saved. */
1720 get_frame_register (this_frame, cache->saved_sp_reg, buf);
1721 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
1723 /* We're halfway aligning the stack. */
1724 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
1725 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
1727 /* This will be added back below. */
1728 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
1730 else if (cache->pc != 0
1731 || target_read_memory (get_frame_pc (this_frame), buf, 1))
1733 /* We're in a known function, but did not find a frame
1734 setup. Assume that the function does not use %ebp.
1735 Alternatively, we may have jumped to an invalid
1736 address; in that case there is definitely no new
1738 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1739 cache->base = extract_unsigned_integer (buf, 4, byte_order)
1743 /* We're in an unknown function. We could not find the start
1744 of the function to analyze the prologue; our best option is
1745 to assume a typical frame layout with the caller's %ebp
1747 cache->saved_regs[I386_EBP_REGNUM] = 0;
1750 if (cache->saved_sp_reg != -1)
1752 /* Saved stack pointer has been saved (but the SAVED_SP_REG
1753 register may be unavailable). */
1754 if (cache->saved_sp == 0
1755 && frame_register_read (this_frame, cache->saved_sp_reg, buf))
1756 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
1758 /* Now that we have the base address for the stack frame we can
1759 calculate the value of %esp in the calling frame. */
1760 else if (cache->saved_sp == 0)
1761 cache->saved_sp = cache->base + 8;
1763 /* Adjust all the saved registers such that they contain addresses
1764 instead of offsets. */
1765 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1766 if (cache->saved_regs[i] != -1)
1767 cache->saved_regs[i] += cache->base;
1772 static struct i386_frame_cache *
1773 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
1775 volatile struct gdb_exception ex;
1776 struct i386_frame_cache *cache;
1781 cache = i386_alloc_frame_cache ();
1782 *this_cache = cache;
1784 TRY_CATCH (ex, RETURN_MASK_ERROR)
1786 i386_frame_cache_1 (this_frame, cache);
1788 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
1789 throw_exception (ex);
1795 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
1796 struct frame_id *this_id)
1798 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1800 /* This marks the outermost frame. */
1801 if (cache->base == 0)
1804 /* See the end of i386_push_dummy_call. */
1805 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
1808 static enum unwind_stop_reason
1809 i386_frame_unwind_stop_reason (struct frame_info *this_frame,
1812 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1815 return UNWIND_UNAVAILABLE;
1817 /* This marks the outermost frame. */
1818 if (cache->base == 0)
1819 return UNWIND_OUTERMOST;
1821 return UNWIND_NO_REASON;
1824 static struct value *
1825 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
1828 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1830 gdb_assert (regnum >= 0);
1832 /* The System V ABI says that:
1834 "The flags register contains the system flags, such as the
1835 direction flag and the carry flag. The direction flag must be
1836 set to the forward (that is, zero) direction before entry and
1837 upon exit from a function. Other user flags have no specified
1838 role in the standard calling sequence and are not preserved."
1840 To guarantee the "upon exit" part of that statement we fake a
1841 saved flags register that has its direction flag cleared.
1843 Note that GCC doesn't seem to rely on the fact that the direction
1844 flag is cleared after a function return; it always explicitly
1845 clears the flag before operations where it matters.
1847 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1848 right thing to do. The way we fake the flags register here makes
1849 it impossible to change it. */
1851 if (regnum == I386_EFLAGS_REGNUM)
1855 val = get_frame_register_unsigned (this_frame, regnum);
1857 return frame_unwind_got_constant (this_frame, regnum, val);
1860 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
1861 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
1863 if (regnum == I386_ESP_REGNUM
1864 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1))
1866 /* If the SP has been saved, but we don't know where, then this
1867 means that SAVED_SP_REG register was found unavailable back
1868 when we built the cache. */
1869 if (cache->saved_sp == 0)
1870 return frame_unwind_got_register (this_frame, regnum,
1871 cache->saved_sp_reg);
1873 return frame_unwind_got_constant (this_frame, regnum,
1877 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
1878 return frame_unwind_got_memory (this_frame, regnum,
1879 cache->saved_regs[regnum]);
1881 return frame_unwind_got_register (this_frame, regnum, regnum);
1884 static const struct frame_unwind i386_frame_unwind =
1887 i386_frame_unwind_stop_reason,
1889 i386_frame_prev_register,
1891 default_frame_sniffer
1894 /* Normal frames, but in a function epilogue. */
1896 /* The epilogue is defined here as the 'ret' instruction, which will
1897 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1898 the function's stack frame. */
1901 i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1904 struct symtab *symtab;
1906 symtab = find_pc_symtab (pc);
1907 if (symtab && symtab->epilogue_unwind_valid)
1910 if (target_read_memory (pc, &insn, 1))
1911 return 0; /* Can't read memory at pc. */
1913 if (insn != 0xc3) /* 'ret' instruction. */
1920 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
1921 struct frame_info *this_frame,
1922 void **this_prologue_cache)
1924 if (frame_relative_level (this_frame) == 0)
1925 return i386_in_function_epilogue_p (get_frame_arch (this_frame),
1926 get_frame_pc (this_frame));
1931 static struct i386_frame_cache *
1932 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
1934 volatile struct gdb_exception ex;
1935 struct i386_frame_cache *cache;
1941 cache = i386_alloc_frame_cache ();
1942 *this_cache = cache;
1944 TRY_CATCH (ex, RETURN_MASK_ERROR)
1946 cache->pc = get_frame_func (this_frame);
1948 /* At this point the stack looks as if we just entered the
1949 function, with the return address at the top of the
1951 sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM);
1952 cache->base = sp + cache->sp_offset;
1953 cache->saved_sp = cache->base + 8;
1954 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
1958 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
1959 throw_exception (ex);
1964 static enum unwind_stop_reason
1965 i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
1968 struct i386_frame_cache *cache =
1969 i386_epilogue_frame_cache (this_frame, this_cache);
1972 return UNWIND_UNAVAILABLE;
1974 return UNWIND_NO_REASON;
1978 i386_epilogue_frame_this_id (struct frame_info *this_frame,
1980 struct frame_id *this_id)
1982 struct i386_frame_cache *cache =
1983 i386_epilogue_frame_cache (this_frame, this_cache);
1988 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
1991 static struct value *
1992 i386_epilogue_frame_prev_register (struct frame_info *this_frame,
1993 void **this_cache, int regnum)
1995 /* Make sure we've initialized the cache. */
1996 i386_epilogue_frame_cache (this_frame, this_cache);
1998 return i386_frame_prev_register (this_frame, this_cache, regnum);
2001 static const struct frame_unwind i386_epilogue_frame_unwind =
2004 i386_epilogue_frame_unwind_stop_reason,
2005 i386_epilogue_frame_this_id,
2006 i386_epilogue_frame_prev_register,
2008 i386_epilogue_frame_sniffer
2012 /* Stack-based trampolines. */
2014 /* These trampolines are used on cross x86 targets, when taking the
2015 address of a nested function. When executing these trampolines,
2016 no stack frame is set up, so we are in a similar situation as in
2017 epilogues and i386_epilogue_frame_this_id can be re-used. */
2019 /* Static chain passed in register. */
2021 struct i386_insn i386_tramp_chain_in_reg_insns[] =
2023 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2024 { 5, { 0xb8 }, { 0xfe } },
2027 { 5, { 0xe9 }, { 0xff } },
2032 /* Static chain passed on stack (when regparm=3). */
2034 struct i386_insn i386_tramp_chain_on_stack_insns[] =
2037 { 5, { 0x68 }, { 0xff } },
2040 { 5, { 0xe9 }, { 0xff } },
2045 /* Return whether PC points inside a stack trampoline. */
2048 i386_in_stack_tramp_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2053 /* A stack trampoline is detected if no name is associated
2054 to the current pc and if it points inside a trampoline
2057 find_pc_partial_function (pc, &name, NULL, NULL);
2061 if (target_read_memory (pc, &insn, 1))
2064 if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns)
2065 && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns))
2072 i386_stack_tramp_frame_sniffer (const struct frame_unwind *self,
2073 struct frame_info *this_frame,
2076 if (frame_relative_level (this_frame) == 0)
2077 return i386_in_stack_tramp_p (get_frame_arch (this_frame),
2078 get_frame_pc (this_frame));
2083 static const struct frame_unwind i386_stack_tramp_frame_unwind =
2086 i386_epilogue_frame_unwind_stop_reason,
2087 i386_epilogue_frame_this_id,
2088 i386_epilogue_frame_prev_register,
2090 i386_stack_tramp_frame_sniffer
2093 /* Generate a bytecode expression to get the value of the saved PC. */
2096 i386_gen_return_address (struct gdbarch *gdbarch,
2097 struct agent_expr *ax, struct axs_value *value,
2100 /* The following sequence assumes the traditional use of the base
2102 ax_reg (ax, I386_EBP_REGNUM);
2104 ax_simple (ax, aop_add);
2105 value->type = register_type (gdbarch, I386_EIP_REGNUM);
2106 value->kind = axs_lvalue_memory;
2110 /* Signal trampolines. */
2112 static struct i386_frame_cache *
2113 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2115 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2116 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2117 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2118 volatile struct gdb_exception ex;
2119 struct i386_frame_cache *cache;
2126 cache = i386_alloc_frame_cache ();
2128 TRY_CATCH (ex, RETURN_MASK_ERROR)
2130 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2131 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
2133 addr = tdep->sigcontext_addr (this_frame);
2134 if (tdep->sc_reg_offset)
2138 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
2140 for (i = 0; i < tdep->sc_num_regs; i++)
2141 if (tdep->sc_reg_offset[i] != -1)
2142 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2146 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
2147 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
2152 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2153 throw_exception (ex);
2155 *this_cache = cache;
2159 static enum unwind_stop_reason
2160 i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2163 struct i386_frame_cache *cache =
2164 i386_sigtramp_frame_cache (this_frame, this_cache);
2167 return UNWIND_UNAVAILABLE;
2169 return UNWIND_NO_REASON;
2173 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
2174 struct frame_id *this_id)
2176 struct i386_frame_cache *cache =
2177 i386_sigtramp_frame_cache (this_frame, this_cache);
2182 /* See the end of i386_push_dummy_call. */
2183 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
2186 static struct value *
2187 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
2188 void **this_cache, int regnum)
2190 /* Make sure we've initialized the cache. */
2191 i386_sigtramp_frame_cache (this_frame, this_cache);
2193 return i386_frame_prev_register (this_frame, this_cache, regnum);
2197 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
2198 struct frame_info *this_frame,
2199 void **this_prologue_cache)
2201 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2203 /* We shouldn't even bother if we don't have a sigcontext_addr
2205 if (tdep->sigcontext_addr == NULL)
2208 if (tdep->sigtramp_p != NULL)
2210 if (tdep->sigtramp_p (this_frame))
2214 if (tdep->sigtramp_start != 0)
2216 CORE_ADDR pc = get_frame_pc (this_frame);
2218 gdb_assert (tdep->sigtramp_end != 0);
2219 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2226 static const struct frame_unwind i386_sigtramp_frame_unwind =
2229 i386_sigtramp_frame_unwind_stop_reason,
2230 i386_sigtramp_frame_this_id,
2231 i386_sigtramp_frame_prev_register,
2233 i386_sigtramp_frame_sniffer
2238 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
2240 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2245 static const struct frame_base i386_frame_base =
2248 i386_frame_base_address,
2249 i386_frame_base_address,
2250 i386_frame_base_address
2253 static struct frame_id
2254 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2258 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
2260 /* See the end of i386_push_dummy_call. */
2261 return frame_id_build (fp + 8, get_frame_pc (this_frame));
2264 /* _Decimal128 function return values need 16-byte alignment on the
2268 i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2270 return sp & -(CORE_ADDR)16;
2274 /* Figure out where the longjmp will land. Slurp the args out of the
2275 stack. We expect the first arg to be a pointer to the jmp_buf
2276 structure from which we extract the address that we will land at.
2277 This address is copied into PC. This routine returns non-zero on
2281 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2284 CORE_ADDR sp, jb_addr;
2285 struct gdbarch *gdbarch = get_frame_arch (frame);
2286 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2287 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2289 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2290 longjmp will land. */
2291 if (jb_pc_offset == -1)
2294 get_frame_register (frame, I386_ESP_REGNUM, buf);
2295 sp = extract_unsigned_integer (buf, 4, byte_order);
2296 if (target_read_memory (sp + 4, buf, 4))
2299 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
2300 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
2303 *pc = extract_unsigned_integer (buf, 4, byte_order);
2308 /* Check whether TYPE must be 16-byte-aligned when passed as a
2309 function argument. 16-byte vectors, _Decimal128 and structures or
2310 unions containing such types must be 16-byte-aligned; other
2311 arguments are 4-byte-aligned. */
2314 i386_16_byte_align_p (struct type *type)
2316 type = check_typedef (type);
2317 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
2318 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
2319 && TYPE_LENGTH (type) == 16)
2321 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2322 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
2323 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2324 || TYPE_CODE (type) == TYPE_CODE_UNION)
2327 for (i = 0; i < TYPE_NFIELDS (type); i++)
2329 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
2337 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2338 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2339 struct value **args, CORE_ADDR sp, int struct_return,
2340 CORE_ADDR struct_addr)
2342 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2348 /* Determine the total space required for arguments and struct
2349 return address in a first pass (allowing for 16-byte-aligned
2350 arguments), then push arguments in a second pass. */
2352 for (write_pass = 0; write_pass < 2; write_pass++)
2354 int args_space_used = 0;
2355 int have_16_byte_aligned_arg = 0;
2361 /* Push value address. */
2362 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2363 write_memory (sp, buf, 4);
2364 args_space_used += 4;
2370 for (i = 0; i < nargs; i++)
2372 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2376 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2377 args_space_used = align_up (args_space_used, 16);
2379 write_memory (sp + args_space_used,
2380 value_contents_all (args[i]), len);
2381 /* The System V ABI says that:
2383 "An argument's size is increased, if necessary, to make it a
2384 multiple of [32-bit] words. This may require tail padding,
2385 depending on the size of the argument."
2387 This makes sure the stack stays word-aligned. */
2388 args_space_used += align_up (len, 4);
2392 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2394 args_space = align_up (args_space, 16);
2395 have_16_byte_aligned_arg = 1;
2397 args_space += align_up (len, 4);
2403 if (have_16_byte_aligned_arg)
2404 args_space = align_up (args_space, 16);
2409 /* Store return address. */
2411 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2412 write_memory (sp, buf, 4);
2414 /* Finally, update the stack pointer... */
2415 store_unsigned_integer (buf, 4, byte_order, sp);
2416 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
2418 /* ...and fake a frame pointer. */
2419 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
2421 /* MarkK wrote: This "+ 8" is all over the place:
2422 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2423 i386_dummy_id). It's there, since all frame unwinders for
2424 a given target have to agree (within a certain margin) on the
2425 definition of the stack address of a frame. Otherwise frame id
2426 comparison might not work correctly. Since DWARF2/GCC uses the
2427 stack address *before* the function call as a frame's CFA. On
2428 the i386, when %ebp is used as a frame pointer, the offset
2429 between the contents %ebp and the CFA as defined by GCC. */
2433 /* These registers are used for returning integers (and on some
2434 targets also for returning `struct' and `union' values when their
2435 size and alignment match an integer type). */
2436 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2437 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2439 /* Read, for architecture GDBARCH, a function return value of TYPE
2440 from REGCACHE, and copy that into VALBUF. */
2443 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2444 struct regcache *regcache, gdb_byte *valbuf)
2446 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2447 int len = TYPE_LENGTH (type);
2448 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2450 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2452 if (tdep->st0_regnum < 0)
2454 warning (_("Cannot find floating-point return value."));
2455 memset (valbuf, 0, len);
2459 /* Floating-point return values can be found in %st(0). Convert
2460 its contents to the desired type. This is probably not
2461 exactly how it would happen on the target itself, but it is
2462 the best we can do. */
2463 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2464 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
2468 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2469 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2471 if (len <= low_size)
2473 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2474 memcpy (valbuf, buf, len);
2476 else if (len <= (low_size + high_size))
2478 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2479 memcpy (valbuf, buf, low_size);
2480 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2481 memcpy (valbuf + low_size, buf, len - low_size);
2484 internal_error (__FILE__, __LINE__,
2485 _("Cannot extract return value of %d bytes long."),
2490 /* Write, for architecture GDBARCH, a function return value of TYPE
2491 from VALBUF into REGCACHE. */
2494 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2495 struct regcache *regcache, const gdb_byte *valbuf)
2497 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2498 int len = TYPE_LENGTH (type);
2500 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2503 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2505 if (tdep->st0_regnum < 0)
2507 warning (_("Cannot set floating-point return value."));
2511 /* Returning floating-point values is a bit tricky. Apart from
2512 storing the return value in %st(0), we have to simulate the
2513 state of the FPU at function return point. */
2515 /* Convert the value found in VALBUF to the extended
2516 floating-point format used by the FPU. This is probably
2517 not exactly how it would happen on the target itself, but
2518 it is the best we can do. */
2519 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
2520 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2522 /* Set the top of the floating-point register stack to 7. The
2523 actual value doesn't really matter, but 7 is what a normal
2524 function return would end up with if the program started out
2525 with a freshly initialized FPU. */
2526 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2528 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2530 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2531 the floating-point register stack to 7, the appropriate value
2532 for the tag word is 0x3fff. */
2533 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2537 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2538 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2540 if (len <= low_size)
2541 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2542 else if (len <= (low_size + high_size))
2544 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2545 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
2546 len - low_size, valbuf + low_size);
2549 internal_error (__FILE__, __LINE__,
2550 _("Cannot store return value of %d bytes long."), len);
2555 /* This is the variable that is set with "set struct-convention", and
2556 its legitimate values. */
2557 static const char default_struct_convention[] = "default";
2558 static const char pcc_struct_convention[] = "pcc";
2559 static const char reg_struct_convention[] = "reg";
2560 static const char *const valid_conventions[] =
2562 default_struct_convention,
2563 pcc_struct_convention,
2564 reg_struct_convention,
2567 static const char *struct_convention = default_struct_convention;
2569 /* Return non-zero if TYPE, which is assumed to be a structure,
2570 a union type, or an array type, should be returned in registers
2571 for architecture GDBARCH. */
2574 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2576 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2577 enum type_code code = TYPE_CODE (type);
2578 int len = TYPE_LENGTH (type);
2580 gdb_assert (code == TYPE_CODE_STRUCT
2581 || code == TYPE_CODE_UNION
2582 || code == TYPE_CODE_ARRAY);
2584 if (struct_convention == pcc_struct_convention
2585 || (struct_convention == default_struct_convention
2586 && tdep->struct_return == pcc_struct_return))
2589 /* Structures consisting of a single `float', `double' or 'long
2590 double' member are returned in %st(0). */
2591 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2593 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2594 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2595 return (len == 4 || len == 8 || len == 12);
2598 return (len == 1 || len == 2 || len == 4 || len == 8);
2601 /* Determine, for architecture GDBARCH, how a return value of TYPE
2602 should be returned. If it is supposed to be returned in registers,
2603 and READBUF is non-zero, read the appropriate value from REGCACHE,
2604 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2605 from WRITEBUF into REGCACHE. */
2607 static enum return_value_convention
2608 i386_return_value (struct gdbarch *gdbarch, struct type *func_type,
2609 struct type *type, struct regcache *regcache,
2610 gdb_byte *readbuf, const gdb_byte *writebuf)
2612 enum type_code code = TYPE_CODE (type);
2614 if (((code == TYPE_CODE_STRUCT
2615 || code == TYPE_CODE_UNION
2616 || code == TYPE_CODE_ARRAY)
2617 && !i386_reg_struct_return_p (gdbarch, type))
2618 /* 128-bit decimal float uses the struct return convention. */
2619 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2621 /* The System V ABI says that:
2623 "A function that returns a structure or union also sets %eax
2624 to the value of the original address of the caller's area
2625 before it returns. Thus when the caller receives control
2626 again, the address of the returned object resides in register
2627 %eax and can be used to access the object."
2629 So the ABI guarantees that we can always find the return
2630 value just after the function has returned. */
2632 /* Note that the ABI doesn't mention functions returning arrays,
2633 which is something possible in certain languages such as Ada.
2634 In this case, the value is returned as if it was wrapped in
2635 a record, so the convention applied to records also applies
2642 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2643 read_memory (addr, readbuf, TYPE_LENGTH (type));
2646 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2649 /* This special case is for structures consisting of a single
2650 `float', `double' or 'long double' member. These structures are
2651 returned in %st(0). For these structures, we call ourselves
2652 recursively, changing TYPE into the type of the first member of
2653 the structure. Since that should work for all structures that
2654 have only one member, we don't bother to check the member's type
2656 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2658 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2659 return i386_return_value (gdbarch, func_type, type, regcache,
2664 i386_extract_return_value (gdbarch, type, regcache, readbuf);
2666 i386_store_return_value (gdbarch, type, regcache, writebuf);
2668 return RETURN_VALUE_REGISTER_CONVENTION;
2673 i387_ext_type (struct gdbarch *gdbarch)
2675 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2677 if (!tdep->i387_ext_type)
2679 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
2680 gdb_assert (tdep->i387_ext_type != NULL);
2683 return tdep->i387_ext_type;
2686 /* Construct vector type for pseudo YMM registers. We can't use
2687 tdesc_find_type since YMM isn't described in target description. */
2689 static struct type *
2690 i386_ymm_type (struct gdbarch *gdbarch)
2692 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2694 if (!tdep->i386_ymm_type)
2696 const struct builtin_type *bt = builtin_type (gdbarch);
2698 /* The type we're building is this: */
2700 union __gdb_builtin_type_vec256i
2702 int128_t uint128[2];
2703 int64_t v2_int64[4];
2704 int32_t v4_int32[8];
2705 int16_t v8_int16[16];
2706 int8_t v16_int8[32];
2707 double v2_double[4];
2714 t = arch_composite_type (gdbarch,
2715 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
2716 append_composite_type_field (t, "v8_float",
2717 init_vector_type (bt->builtin_float, 8));
2718 append_composite_type_field (t, "v4_double",
2719 init_vector_type (bt->builtin_double, 4));
2720 append_composite_type_field (t, "v32_int8",
2721 init_vector_type (bt->builtin_int8, 32));
2722 append_composite_type_field (t, "v16_int16",
2723 init_vector_type (bt->builtin_int16, 16));
2724 append_composite_type_field (t, "v8_int32",
2725 init_vector_type (bt->builtin_int32, 8));
2726 append_composite_type_field (t, "v4_int64",
2727 init_vector_type (bt->builtin_int64, 4));
2728 append_composite_type_field (t, "v2_int128",
2729 init_vector_type (bt->builtin_int128, 2));
2731 TYPE_VECTOR (t) = 1;
2732 TYPE_NAME (t) = "builtin_type_vec256i";
2733 tdep->i386_ymm_type = t;
2736 return tdep->i386_ymm_type;
2739 /* Construct vector type for MMX registers. */
2740 static struct type *
2741 i386_mmx_type (struct gdbarch *gdbarch)
2743 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2745 if (!tdep->i386_mmx_type)
2747 const struct builtin_type *bt = builtin_type (gdbarch);
2749 /* The type we're building is this: */
2751 union __gdb_builtin_type_vec64i
2754 int32_t v2_int32[2];
2755 int16_t v4_int16[4];
2762 t = arch_composite_type (gdbarch,
2763 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
2765 append_composite_type_field (t, "uint64", bt->builtin_int64);
2766 append_composite_type_field (t, "v2_int32",
2767 init_vector_type (bt->builtin_int32, 2));
2768 append_composite_type_field (t, "v4_int16",
2769 init_vector_type (bt->builtin_int16, 4));
2770 append_composite_type_field (t, "v8_int8",
2771 init_vector_type (bt->builtin_int8, 8));
2773 TYPE_VECTOR (t) = 1;
2774 TYPE_NAME (t) = "builtin_type_vec64i";
2775 tdep->i386_mmx_type = t;
2778 return tdep->i386_mmx_type;
2781 /* Return the GDB type object for the "standard" data type of data in
2784 static struct type *
2785 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2787 if (i386_mmx_regnum_p (gdbarch, regnum))
2788 return i386_mmx_type (gdbarch);
2789 else if (i386_ymm_regnum_p (gdbarch, regnum))
2790 return i386_ymm_type (gdbarch);
2793 const struct builtin_type *bt = builtin_type (gdbarch);
2794 if (i386_byte_regnum_p (gdbarch, regnum))
2795 return bt->builtin_int8;
2796 else if (i386_word_regnum_p (gdbarch, regnum))
2797 return bt->builtin_int16;
2798 else if (i386_dword_regnum_p (gdbarch, regnum))
2799 return bt->builtin_int32;
2802 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2805 /* Map a cooked register onto a raw register or memory. For the i386,
2806 the MMX registers need to be mapped onto floating point registers. */
2809 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
2811 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
2816 mmxreg = regnum - tdep->mm0_regnum;
2817 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2818 tos = (fstat >> 11) & 0x7;
2819 fpreg = (mmxreg + tos) % 8;
2821 return (I387_ST0_REGNUM (tdep) + fpreg);
2824 /* A helper function for us by i386_pseudo_register_read_value and
2825 amd64_pseudo_register_read_value. It does all the work but reads
2826 the data into an already-allocated value. */
2829 i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
2830 struct regcache *regcache,
2832 struct value *result_value)
2834 gdb_byte raw_buf[MAX_REGISTER_SIZE];
2835 enum register_status status;
2836 gdb_byte *buf = value_contents_raw (result_value);
2838 if (i386_mmx_regnum_p (gdbarch, regnum))
2840 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2842 /* Extract (always little endian). */
2843 status = regcache_raw_read (regcache, fpnum, raw_buf);
2844 if (status != REG_VALID)
2845 mark_value_bytes_unavailable (result_value, 0,
2846 TYPE_LENGTH (value_type (result_value)));
2848 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
2852 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2854 if (i386_ymm_regnum_p (gdbarch, regnum))
2856 regnum -= tdep->ymm0_regnum;
2858 /* Extract (always little endian). Read lower 128bits. */
2859 status = regcache_raw_read (regcache,
2860 I387_XMM0_REGNUM (tdep) + regnum,
2862 if (status != REG_VALID)
2863 mark_value_bytes_unavailable (result_value, 0, 16);
2865 memcpy (buf, raw_buf, 16);
2866 /* Read upper 128bits. */
2867 status = regcache_raw_read (regcache,
2868 tdep->ymm0h_regnum + regnum,
2870 if (status != REG_VALID)
2871 mark_value_bytes_unavailable (result_value, 16, 32);
2873 memcpy (buf + 16, raw_buf, 16);
2875 else if (i386_word_regnum_p (gdbarch, regnum))
2877 int gpnum = regnum - tdep->ax_regnum;
2879 /* Extract (always little endian). */
2880 status = regcache_raw_read (regcache, gpnum, raw_buf);
2881 if (status != REG_VALID)
2882 mark_value_bytes_unavailable (result_value, 0,
2883 TYPE_LENGTH (value_type (result_value)));
2885 memcpy (buf, raw_buf, 2);
2887 else if (i386_byte_regnum_p (gdbarch, regnum))
2889 /* Check byte pseudo registers last since this function will
2890 be called from amd64_pseudo_register_read, which handles
2891 byte pseudo registers differently. */
2892 int gpnum = regnum - tdep->al_regnum;
2894 /* Extract (always little endian). We read both lower and
2896 status = regcache_raw_read (regcache, gpnum % 4, raw_buf);
2897 if (status != REG_VALID)
2898 mark_value_bytes_unavailable (result_value, 0,
2899 TYPE_LENGTH (value_type (result_value)));
2900 else if (gpnum >= 4)
2901 memcpy (buf, raw_buf + 1, 1);
2903 memcpy (buf, raw_buf, 1);
2906 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2910 static struct value *
2911 i386_pseudo_register_read_value (struct gdbarch *gdbarch,
2912 struct regcache *regcache,
2915 struct value *result;
2917 result = allocate_value (register_type (gdbarch, regnum));
2918 VALUE_LVAL (result) = lval_register;
2919 VALUE_REGNUM (result) = regnum;
2921 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result);
2927 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2928 int regnum, const gdb_byte *buf)
2930 gdb_byte raw_buf[MAX_REGISTER_SIZE];
2932 if (i386_mmx_regnum_p (gdbarch, regnum))
2934 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2937 regcache_raw_read (regcache, fpnum, raw_buf);
2938 /* ... Modify ... (always little endian). */
2939 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
2941 regcache_raw_write (regcache, fpnum, raw_buf);
2945 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2947 if (i386_ymm_regnum_p (gdbarch, regnum))
2949 regnum -= tdep->ymm0_regnum;
2951 /* ... Write lower 128bits. */
2952 regcache_raw_write (regcache,
2953 I387_XMM0_REGNUM (tdep) + regnum,
2955 /* ... Write upper 128bits. */
2956 regcache_raw_write (regcache,
2957 tdep->ymm0h_regnum + regnum,
2960 else if (i386_word_regnum_p (gdbarch, regnum))
2962 int gpnum = regnum - tdep->ax_regnum;
2965 regcache_raw_read (regcache, gpnum, raw_buf);
2966 /* ... Modify ... (always little endian). */
2967 memcpy (raw_buf, buf, 2);
2969 regcache_raw_write (regcache, gpnum, raw_buf);
2971 else if (i386_byte_regnum_p (gdbarch, regnum))
2973 /* Check byte pseudo registers last since this function will
2974 be called from amd64_pseudo_register_read, which handles
2975 byte pseudo registers differently. */
2976 int gpnum = regnum - tdep->al_regnum;
2978 /* Read ... We read both lower and upper registers. */
2979 regcache_raw_read (regcache, gpnum % 4, raw_buf);
2980 /* ... Modify ... (always little endian). */
2982 memcpy (raw_buf + 1, buf, 1);
2984 memcpy (raw_buf, buf, 1);
2986 regcache_raw_write (regcache, gpnum % 4, raw_buf);
2989 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2994 /* Return the register number of the register allocated by GCC after
2995 REGNUM, or -1 if there is no such register. */
2998 i386_next_regnum (int regnum)
3000 /* GCC allocates the registers in the order:
3002 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3004 Since storing a variable in %esp doesn't make any sense we return
3005 -1 for %ebp and for %esp itself. */
3006 static int next_regnum[] =
3008 I386_EDX_REGNUM, /* Slot for %eax. */
3009 I386_EBX_REGNUM, /* Slot for %ecx. */
3010 I386_ECX_REGNUM, /* Slot for %edx. */
3011 I386_ESI_REGNUM, /* Slot for %ebx. */
3012 -1, -1, /* Slots for %esp and %ebp. */
3013 I386_EDI_REGNUM, /* Slot for %esi. */
3014 I386_EBP_REGNUM /* Slot for %edi. */
3017 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
3018 return next_regnum[regnum];
3023 /* Return nonzero if a value of type TYPE stored in register REGNUM
3024 needs any special handling. */
3027 i386_convert_register_p (struct gdbarch *gdbarch,
3028 int regnum, struct type *type)
3030 int len = TYPE_LENGTH (type);
3032 /* Values may be spread across multiple registers. Most debugging
3033 formats aren't expressive enough to specify the locations, so
3034 some heuristics is involved. Right now we only handle types that
3035 have a length that is a multiple of the word size, since GCC
3036 doesn't seem to put any other types into registers. */
3037 if (len > 4 && len % 4 == 0)
3039 int last_regnum = regnum;
3043 last_regnum = i386_next_regnum (last_regnum);
3047 if (last_regnum != -1)
3051 return i387_convert_register_p (gdbarch, regnum, type);
3054 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3055 return its contents in TO. */
3058 i386_register_to_value (struct frame_info *frame, int regnum,
3059 struct type *type, gdb_byte *to,
3060 int *optimizedp, int *unavailablep)
3062 struct gdbarch *gdbarch = get_frame_arch (frame);
3063 int len = TYPE_LENGTH (type);
3065 if (i386_fp_regnum_p (gdbarch, regnum))
3066 return i387_register_to_value (frame, regnum, type, to,
3067 optimizedp, unavailablep);
3069 /* Read a value spread across multiple registers. */
3071 gdb_assert (len > 4 && len % 4 == 0);
3075 gdb_assert (regnum != -1);
3076 gdb_assert (register_size (gdbarch, regnum) == 4);
3078 if (!get_frame_register_bytes (frame, regnum, 0,
3079 register_size (gdbarch, regnum),
3080 to, optimizedp, unavailablep))
3083 regnum = i386_next_regnum (regnum);
3088 *optimizedp = *unavailablep = 0;
3092 /* Write the contents FROM of a value of type TYPE into register
3093 REGNUM in frame FRAME. */
3096 i386_value_to_register (struct frame_info *frame, int regnum,
3097 struct type *type, const gdb_byte *from)
3099 int len = TYPE_LENGTH (type);
3101 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
3103 i387_value_to_register (frame, regnum, type, from);
3107 /* Write a value spread across multiple registers. */
3109 gdb_assert (len > 4 && len % 4 == 0);
3113 gdb_assert (regnum != -1);
3114 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
3116 put_frame_register (frame, regnum, from);
3117 regnum = i386_next_regnum (regnum);
3123 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3124 in the general-purpose register set REGSET to register cache
3125 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3128 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
3129 int regnum, const void *gregs, size_t len)
3131 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3132 const gdb_byte *regs = gregs;
3135 gdb_assert (len == tdep->sizeof_gregset);
3137 for (i = 0; i < tdep->gregset_num_regs; i++)
3139 if ((regnum == i || regnum == -1)
3140 && tdep->gregset_reg_offset[i] != -1)
3141 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
3145 /* Collect register REGNUM from the register cache REGCACHE and store
3146 it in the buffer specified by GREGS and LEN as described by the
3147 general-purpose register set REGSET. If REGNUM is -1, do this for
3148 all registers in REGSET. */
3151 i386_collect_gregset (const struct regset *regset,
3152 const struct regcache *regcache,
3153 int regnum, void *gregs, size_t len)
3155 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3156 gdb_byte *regs = gregs;
3159 gdb_assert (len == tdep->sizeof_gregset);
3161 for (i = 0; i < tdep->gregset_num_regs; i++)
3163 if ((regnum == i || regnum == -1)
3164 && tdep->gregset_reg_offset[i] != -1)
3165 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
3169 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3170 in the floating-point register set REGSET to register cache
3171 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3174 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
3175 int regnum, const void *fpregs, size_t len)
3177 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3179 if (len == I387_SIZEOF_FXSAVE)
3181 i387_supply_fxsave (regcache, regnum, fpregs);
3185 gdb_assert (len == tdep->sizeof_fpregset);
3186 i387_supply_fsave (regcache, regnum, fpregs);
3189 /* Collect register REGNUM from the register cache REGCACHE and store
3190 it in the buffer specified by FPREGS and LEN as described by the
3191 floating-point register set REGSET. If REGNUM is -1, do this for
3192 all registers in REGSET. */
3195 i386_collect_fpregset (const struct regset *regset,
3196 const struct regcache *regcache,
3197 int regnum, void *fpregs, size_t len)
3199 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3201 if (len == I387_SIZEOF_FXSAVE)
3203 i387_collect_fxsave (regcache, regnum, fpregs);
3207 gdb_assert (len == tdep->sizeof_fpregset);
3208 i387_collect_fsave (regcache, regnum, fpregs);
3211 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
3214 i386_supply_xstateregset (const struct regset *regset,
3215 struct regcache *regcache, int regnum,
3216 const void *xstateregs, size_t len)
3218 i387_supply_xsave (regcache, regnum, xstateregs);
3221 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
3224 i386_collect_xstateregset (const struct regset *regset,
3225 const struct regcache *regcache,
3226 int regnum, void *xstateregs, size_t len)
3228 i387_collect_xsave (regcache, regnum, xstateregs, 1);
3231 /* Return the appropriate register set for the core section identified
3232 by SECT_NAME and SECT_SIZE. */
3234 const struct regset *
3235 i386_regset_from_core_section (struct gdbarch *gdbarch,
3236 const char *sect_name, size_t sect_size)
3238 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3240 if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset)
3242 if (tdep->gregset == NULL)
3243 tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset,
3244 i386_collect_gregset);
3245 return tdep->gregset;
3248 if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
3249 || (strcmp (sect_name, ".reg-xfp") == 0
3250 && sect_size == I387_SIZEOF_FXSAVE))
3252 if (tdep->fpregset == NULL)
3253 tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset,
3254 i386_collect_fpregset);
3255 return tdep->fpregset;
3258 if (strcmp (sect_name, ".reg-xstate") == 0)
3260 if (tdep->xstateregset == NULL)
3261 tdep->xstateregset = regset_alloc (gdbarch,
3262 i386_supply_xstateregset,
3263 i386_collect_xstateregset);
3265 return tdep->xstateregset;
3272 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3275 i386_pe_skip_trampoline_code (struct frame_info *frame,
3276 CORE_ADDR pc, char *name)
3278 struct gdbarch *gdbarch = get_frame_arch (frame);
3279 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3282 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
3284 unsigned long indirect =
3285 read_memory_unsigned_integer (pc + 2, 4, byte_order);
3286 struct minimal_symbol *indsym =
3287 indirect ? lookup_minimal_symbol_by_pc (indirect) : 0;
3288 const char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0;
3292 if (strncmp (symname, "__imp_", 6) == 0
3293 || strncmp (symname, "_imp_", 5) == 0)
3295 read_memory_unsigned_integer (indirect, 4, byte_order);
3298 return 0; /* Not a trampoline. */
3302 /* Return whether the THIS_FRAME corresponds to a sigtramp
3306 i386_sigtramp_p (struct frame_info *this_frame)
3308 CORE_ADDR pc = get_frame_pc (this_frame);
3311 find_pc_partial_function (pc, &name, NULL, NULL);
3312 return (name && strcmp ("_sigtramp", name) == 0);
3316 /* We have two flavours of disassembly. The machinery on this page
3317 deals with switching between those. */
3320 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
3322 gdb_assert (disassembly_flavor == att_flavor
3323 || disassembly_flavor == intel_flavor);
3325 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3326 constified, cast to prevent a compiler warning. */
3327 info->disassembler_options = (char *) disassembly_flavor;
3329 return print_insn_i386 (pc, info);
3333 /* There are a few i386 architecture variants that differ only
3334 slightly from the generic i386 target. For now, we don't give them
3335 their own source file, but include them here. As a consequence,
3336 they'll always be included. */
3338 /* System V Release 4 (SVR4). */
3340 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3344 i386_svr4_sigtramp_p (struct frame_info *this_frame)
3346 CORE_ADDR pc = get_frame_pc (this_frame);
3349 /* UnixWare uses _sigacthandler. The origin of the other symbols is
3350 currently unknown. */
3351 find_pc_partial_function (pc, &name, NULL, NULL);
3352 return (name && (strcmp ("_sigreturn", name) == 0
3353 || strcmp ("_sigacthandler", name) == 0
3354 || strcmp ("sigvechandler", name) == 0));
3357 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3358 address of the associated sigcontext (ucontext) structure. */
3361 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
3363 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3364 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3368 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
3369 sp = extract_unsigned_integer (buf, 4, byte_order);
3371 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
3376 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
3380 i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s)
3382 return (*s == '$' /* Literal number. */
3383 || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */
3384 || (*s == '(' && s[1] == '%') /* Register indirection. */
3385 || (*s == '%' && isalpha (s[1]))); /* Register access. */
3388 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
3392 i386_stap_parse_special_token (struct gdbarch *gdbarch,
3393 struct stap_parse_info *p)
3395 const char *s = p->arg;
3397 /* In order to parse special tokens, we use a state-machine that go
3398 through every known token and try to get a match. */
3402 THREE_ARG_DISPLACEMENT,
3406 current_state = TRIPLET;
3408 /* The special tokens to be parsed here are:
3410 - `register base + (register index * size) + offset', as represented
3411 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
3413 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
3414 `*(-8 + 3 - 1 + (void *) $eax)'. */
3416 while (current_state != DONE)
3418 const char *s = p->arg;
3420 switch (current_state)
3424 if (isdigit (*s) || *s == '-' || *s == '+')
3428 long displacements[3];
3443 displacements[0] = strtol (s, (char **) &s, 10);
3445 if (*s != '+' && *s != '-')
3447 /* We are not dealing with a triplet. */
3460 displacements[1] = strtol (s, (char **) &s, 10);
3462 if (*s != '+' && *s != '-')
3464 /* We are not dealing with a triplet. */
3477 displacements[2] = strtol (s, (char **) &s, 10);
3479 if (*s != '(' || s[1] != '%')
3485 while (isalnum (*s))
3492 regname = alloca (len + 1);
3494 strncpy (regname, start, len);
3495 regname[len] = '\0';
3497 if (user_reg_map_name_to_regnum (gdbarch,
3498 regname, len) == -1)
3499 error (_("Invalid register name `%s' "
3500 "on expression `%s'."),
3501 regname, p->saved_arg);
3503 for (i = 0; i < 3; i++)
3505 write_exp_elt_opcode (OP_LONG);
3507 (builtin_type (gdbarch)->builtin_long);
3508 write_exp_elt_longcst (displacements[i]);
3509 write_exp_elt_opcode (OP_LONG);
3511 write_exp_elt_opcode (UNOP_NEG);
3514 write_exp_elt_opcode (OP_REGISTER);
3517 write_exp_string (str);
3518 write_exp_elt_opcode (OP_REGISTER);
3520 write_exp_elt_opcode (UNOP_CAST);
3521 write_exp_elt_type (builtin_type (gdbarch)->builtin_data_ptr);
3522 write_exp_elt_opcode (UNOP_CAST);
3524 write_exp_elt_opcode (BINOP_ADD);
3525 write_exp_elt_opcode (BINOP_ADD);
3526 write_exp_elt_opcode (BINOP_ADD);
3528 write_exp_elt_opcode (UNOP_CAST);
3529 write_exp_elt_type (lookup_pointer_type (p->arg_type));
3530 write_exp_elt_opcode (UNOP_CAST);
3532 write_exp_elt_opcode (UNOP_IND);
3540 case THREE_ARG_DISPLACEMENT:
3542 if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+')
3544 int offset_minus = 0;
3553 struct stoken base_token, index_token;
3563 if (offset_minus && !isdigit (*s))
3567 offset = strtol (s, (char **) &s, 10);
3569 if (*s != '(' || s[1] != '%')
3575 while (isalnum (*s))
3578 if (*s != ',' || s[1] != '%')
3581 len_base = s - start;
3582 base = alloca (len_base + 1);
3583 strncpy (base, start, len_base);
3584 base[len_base] = '\0';
3586 if (user_reg_map_name_to_regnum (gdbarch,
3587 base, len_base) == -1)
3588 error (_("Invalid register name `%s' "
3589 "on expression `%s'."),
3590 base, p->saved_arg);
3595 while (isalnum (*s))
3598 len_index = s - start;
3599 index = alloca (len_index + 1);
3600 strncpy (index, start, len_index);
3601 index[len_index] = '\0';
3603 if (user_reg_map_name_to_regnum (gdbarch,
3604 index, len_index) == -1)
3605 error (_("Invalid register name `%s' "
3606 "on expression `%s'."),
3607 index, p->saved_arg);
3609 if (*s != ',' && *s != ')')
3623 size = strtol (s, (char **) &s, 10);
3633 write_exp_elt_opcode (OP_LONG);
3635 (builtin_type (gdbarch)->builtin_long);
3636 write_exp_elt_longcst (offset);
3637 write_exp_elt_opcode (OP_LONG);
3639 write_exp_elt_opcode (UNOP_NEG);
3642 write_exp_elt_opcode (OP_REGISTER);
3643 base_token.ptr = base;
3644 base_token.length = len_base;
3645 write_exp_string (base_token);
3646 write_exp_elt_opcode (OP_REGISTER);
3649 write_exp_elt_opcode (BINOP_ADD);
3651 write_exp_elt_opcode (OP_REGISTER);
3652 index_token.ptr = index;
3653 index_token.length = len_index;
3654 write_exp_string (index_token);
3655 write_exp_elt_opcode (OP_REGISTER);
3659 write_exp_elt_opcode (OP_LONG);
3661 (builtin_type (gdbarch)->builtin_long);
3662 write_exp_elt_longcst (size);
3663 write_exp_elt_opcode (OP_LONG);
3665 write_exp_elt_opcode (UNOP_NEG);
3666 write_exp_elt_opcode (BINOP_MUL);
3669 write_exp_elt_opcode (BINOP_ADD);
3671 write_exp_elt_opcode (UNOP_CAST);
3672 write_exp_elt_type (lookup_pointer_type (p->arg_type));
3673 write_exp_elt_opcode (UNOP_CAST);
3675 write_exp_elt_opcode (UNOP_IND);
3685 /* Advancing to the next state. */
3697 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3699 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3700 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3702 /* Registering SystemTap handlers. */
3703 set_gdbarch_stap_integer_prefix (gdbarch, "$");
3704 set_gdbarch_stap_register_prefix (gdbarch, "%");
3705 set_gdbarch_stap_register_indirection_prefix (gdbarch, "(");
3706 set_gdbarch_stap_register_indirection_suffix (gdbarch, ")");
3707 set_gdbarch_stap_is_single_operand (gdbarch,
3708 i386_stap_is_single_operand);
3709 set_gdbarch_stap_parse_special_token (gdbarch,
3710 i386_stap_parse_special_token);
3713 /* System V Release 4 (SVR4). */
3716 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3718 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3720 /* System V Release 4 uses ELF. */
3721 i386_elf_init_abi (info, gdbarch);
3723 /* System V Release 4 has shared libraries. */
3724 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
3726 tdep->sigtramp_p = i386_svr4_sigtramp_p;
3727 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
3728 tdep->sc_pc_offset = 36 + 14 * 4;
3729 tdep->sc_sp_offset = 36 + 17 * 4;
3731 tdep->jb_pc_offset = 20;
3737 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3739 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3741 /* DJGPP doesn't have any special frames for signal handlers. */
3742 tdep->sigtramp_p = NULL;
3744 tdep->jb_pc_offset = 36;
3746 /* DJGPP does not support the SSE registers. */
3747 if (! tdesc_has_registers (info.target_desc))
3748 tdep->tdesc = tdesc_i386_mmx;
3750 /* Native compiler is GCC, which uses the SVR4 register numbering
3751 even in COFF and STABS. See the comment in i386_gdbarch_init,
3752 before the calls to set_gdbarch_stab_reg_to_regnum and
3753 set_gdbarch_sdb_reg_to_regnum. */
3754 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3755 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3757 set_gdbarch_has_dos_based_file_system (gdbarch, 1);
3761 /* i386 register groups. In addition to the normal groups, add "mmx"
3764 static struct reggroup *i386_sse_reggroup;
3765 static struct reggroup *i386_mmx_reggroup;
3768 i386_init_reggroups (void)
3770 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
3771 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
3775 i386_add_reggroups (struct gdbarch *gdbarch)
3777 reggroup_add (gdbarch, i386_sse_reggroup);
3778 reggroup_add (gdbarch, i386_mmx_reggroup);
3779 reggroup_add (gdbarch, general_reggroup);
3780 reggroup_add (gdbarch, float_reggroup);
3781 reggroup_add (gdbarch, all_reggroup);
3782 reggroup_add (gdbarch, save_reggroup);
3783 reggroup_add (gdbarch, restore_reggroup);
3784 reggroup_add (gdbarch, vector_reggroup);
3785 reggroup_add (gdbarch, system_reggroup);
3789 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
3790 struct reggroup *group)
3792 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3793 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
3794 ymm_regnum_p, ymmh_regnum_p;
3796 /* Don't include pseudo registers, except for MMX, in any register
3798 if (i386_byte_regnum_p (gdbarch, regnum))
3801 if (i386_word_regnum_p (gdbarch, regnum))
3804 if (i386_dword_regnum_p (gdbarch, regnum))
3807 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
3808 if (group == i386_mmx_reggroup)
3809 return mmx_regnum_p;
3811 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
3812 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
3813 if (group == i386_sse_reggroup)
3814 return xmm_regnum_p || mxcsr_regnum_p;
3816 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
3817 if (group == vector_reggroup)
3818 return (mmx_regnum_p
3822 && ((tdep->xcr0 & I386_XSTATE_AVX_MASK)
3823 == I386_XSTATE_SSE_MASK)));
3825 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
3826 || i386_fpc_regnum_p (gdbarch, regnum));
3827 if (group == float_reggroup)
3830 /* For "info reg all", don't include upper YMM registers nor XMM
3831 registers when AVX is supported. */
3832 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
3833 if (group == all_reggroup
3835 && (tdep->xcr0 & I386_XSTATE_AVX))
3839 if (group == general_reggroup)
3840 return (!fp_regnum_p
3847 return default_register_reggroup_p (gdbarch, regnum, group);
3851 /* Get the ARGIth function argument for the current function. */
3854 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
3857 struct gdbarch *gdbarch = get_frame_arch (frame);
3858 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3859 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
3860 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
3864 i386_skip_permanent_breakpoint (struct regcache *regcache)
3866 CORE_ADDR current_pc = regcache_read_pc (regcache);
3868 /* On i386, breakpoint is exactly 1 byte long, so we just
3869 adjust the PC in the regcache. */
3871 regcache_write_pc (regcache, current_pc);
3875 #define PREFIX_REPZ 0x01
3876 #define PREFIX_REPNZ 0x02
3877 #define PREFIX_LOCK 0x04
3878 #define PREFIX_DATA 0x08
3879 #define PREFIX_ADDR 0x10
3891 /* i386 arith/logic operations */
3904 struct i386_record_s
3906 struct gdbarch *gdbarch;
3907 struct regcache *regcache;
3908 CORE_ADDR orig_addr;
3914 uint8_t mod, reg, rm;
3923 /* Parse "modrm" part in current memory address that irp->addr point to
3924 Return -1 if something wrong. */
3927 i386_record_modrm (struct i386_record_s *irp)
3929 struct gdbarch *gdbarch = irp->gdbarch;
3931 if (target_read_memory (irp->addr, &irp->modrm, 1))
3934 printf_unfiltered (_("Process record: error reading memory at "
3935 "addr %s len = 1.\n"),
3936 paddress (gdbarch, irp->addr));
3940 irp->mod = (irp->modrm >> 6) & 3;
3941 irp->reg = (irp->modrm >> 3) & 7;
3942 irp->rm = irp->modrm & 7;
3947 /* Get the memory address that current instruction write to and set it to
3948 the argument "addr".
3949 Return -1 if something wrong. */
3952 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
3954 struct gdbarch *gdbarch = irp->gdbarch;
3955 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3967 uint8_t base = irp->rm;
3972 if (target_read_memory (irp->addr, &byte, 1))
3975 printf_unfiltered (_("Process record: error reading memory "
3976 "at addr %s len = 1.\n"),
3977 paddress (gdbarch, irp->addr));
3981 scale = (byte >> 6) & 3;
3982 index = ((byte >> 3) & 7) | irp->rex_x;
3990 if ((base & 7) == 5)
3993 if (target_read_memory (irp->addr, buf, 4))
3996 printf_unfiltered (_("Process record: error reading "
3997 "memory at addr %s len = 4.\n"),
3998 paddress (gdbarch, irp->addr));
4002 *addr = extract_signed_integer (buf, 4, byte_order);
4003 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
4004 *addr += irp->addr + irp->rip_offset;
4008 if (target_read_memory (irp->addr, buf, 1))
4011 printf_unfiltered (_("Process record: error reading memory "
4012 "at addr %s len = 1.\n"),
4013 paddress (gdbarch, irp->addr));
4017 *addr = (int8_t) buf[0];
4020 if (target_read_memory (irp->addr, buf, 4))
4023 printf_unfiltered (_("Process record: error reading memory "
4024 "at addr %s len = 4.\n"),
4025 paddress (gdbarch, irp->addr));
4028 *addr = extract_signed_integer (buf, 4, byte_order);
4036 if (base == 4 && irp->popl_esp_hack)
4037 *addr += irp->popl_esp_hack;
4038 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
4041 if (irp->aflag == 2)
4046 *addr = (uint32_t) (offset64 + *addr);
4048 if (havesib && (index != 4 || scale != 0))
4050 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
4052 if (irp->aflag == 2)
4053 *addr += offset64 << scale;
4055 *addr = (uint32_t) (*addr + (offset64 << scale));
4066 if (target_read_memory (irp->addr, buf, 2))
4069 printf_unfiltered (_("Process record: error reading "
4070 "memory at addr %s len = 2.\n"),
4071 paddress (gdbarch, irp->addr));
4075 *addr = extract_signed_integer (buf, 2, byte_order);
4081 if (target_read_memory (irp->addr, buf, 1))
4084 printf_unfiltered (_("Process record: error reading memory "
4085 "at addr %s len = 1.\n"),
4086 paddress (gdbarch, irp->addr));
4090 *addr = (int8_t) buf[0];
4093 if (target_read_memory (irp->addr, buf, 2))
4096 printf_unfiltered (_("Process record: error reading memory "
4097 "at addr %s len = 2.\n"),
4098 paddress (gdbarch, irp->addr));
4102 *addr = extract_signed_integer (buf, 2, byte_order);
4109 regcache_raw_read_unsigned (irp->regcache,
4110 irp->regmap[X86_RECORD_REBX_REGNUM],
4112 *addr = (uint32_t) (*addr + offset64);
4113 regcache_raw_read_unsigned (irp->regcache,
4114 irp->regmap[X86_RECORD_RESI_REGNUM],
4116 *addr = (uint32_t) (*addr + offset64);
4119 regcache_raw_read_unsigned (irp->regcache,
4120 irp->regmap[X86_RECORD_REBX_REGNUM],
4122 *addr = (uint32_t) (*addr + offset64);
4123 regcache_raw_read_unsigned (irp->regcache,
4124 irp->regmap[X86_RECORD_REDI_REGNUM],
4126 *addr = (uint32_t) (*addr + offset64);
4129 regcache_raw_read_unsigned (irp->regcache,
4130 irp->regmap[X86_RECORD_REBP_REGNUM],
4132 *addr = (uint32_t) (*addr + offset64);
4133 regcache_raw_read_unsigned (irp->regcache,
4134 irp->regmap[X86_RECORD_RESI_REGNUM],
4136 *addr = (uint32_t) (*addr + offset64);
4139 regcache_raw_read_unsigned (irp->regcache,
4140 irp->regmap[X86_RECORD_REBP_REGNUM],
4142 *addr = (uint32_t) (*addr + offset64);
4143 regcache_raw_read_unsigned (irp->regcache,
4144 irp->regmap[X86_RECORD_REDI_REGNUM],
4146 *addr = (uint32_t) (*addr + offset64);
4149 regcache_raw_read_unsigned (irp->regcache,
4150 irp->regmap[X86_RECORD_RESI_REGNUM],
4152 *addr = (uint32_t) (*addr + offset64);
4155 regcache_raw_read_unsigned (irp->regcache,
4156 irp->regmap[X86_RECORD_REDI_REGNUM],
4158 *addr = (uint32_t) (*addr + offset64);
4161 regcache_raw_read_unsigned (irp->regcache,
4162 irp->regmap[X86_RECORD_REBP_REGNUM],
4164 *addr = (uint32_t) (*addr + offset64);
4167 regcache_raw_read_unsigned (irp->regcache,
4168 irp->regmap[X86_RECORD_REBX_REGNUM],
4170 *addr = (uint32_t) (*addr + offset64);
4180 /* Record the value of the memory that willbe changed in current instruction
4181 to "record_arch_list".
4182 Return -1 if something wrong. */
4185 i386_record_lea_modrm (struct i386_record_s *irp)
4187 struct gdbarch *gdbarch = irp->gdbarch;
4190 if (irp->override >= 0)
4192 if (record_memory_query)
4196 target_terminal_ours ();
4198 Process record ignores the memory change of instruction at address %s\n\
4199 because it can't get the value of the segment register.\n\
4200 Do you want to stop the program?"),
4201 paddress (gdbarch, irp->orig_addr));
4202 target_terminal_inferior ();
4210 if (i386_record_lea_modrm_addr (irp, &addr))
4213 if (record_arch_list_add_mem (addr, 1 << irp->ot))
4219 /* Record the push operation to "record_arch_list".
4220 Return -1 if something wrong. */
4223 i386_record_push (struct i386_record_s *irp, int size)
4227 if (record_arch_list_add_reg (irp->regcache,
4228 irp->regmap[X86_RECORD_RESP_REGNUM]))
4230 regcache_raw_read_unsigned (irp->regcache,
4231 irp->regmap[X86_RECORD_RESP_REGNUM],
4233 if (record_arch_list_add_mem ((CORE_ADDR) addr - size, size))
4240 /* Defines contents to record. */
4241 #define I386_SAVE_FPU_REGS 0xfffd
4242 #define I386_SAVE_FPU_ENV 0xfffe
4243 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4245 /* Record the value of floating point registers which will be changed
4246 by the current instruction to "record_arch_list". Return -1 if
4247 something is wrong. */
4249 static int i386_record_floats (struct gdbarch *gdbarch,
4250 struct i386_record_s *ir,
4253 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4256 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4257 happen. Currently we store st0-st7 registers, but we need not store all
4258 registers all the time, in future we use ftag register and record only
4259 those who are not marked as an empty. */
4261 if (I386_SAVE_FPU_REGS == iregnum)
4263 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
4265 if (record_arch_list_add_reg (ir->regcache, i))
4269 else if (I386_SAVE_FPU_ENV == iregnum)
4271 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4273 if (record_arch_list_add_reg (ir->regcache, i))
4277 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
4279 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4281 if (record_arch_list_add_reg (ir->regcache, i))
4285 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
4286 (iregnum <= I387_FOP_REGNUM (tdep)))
4288 if (record_arch_list_add_reg (ir->regcache,iregnum))
4293 /* Parameter error. */
4296 if(I386_SAVE_FPU_ENV != iregnum)
4298 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4300 if (record_arch_list_add_reg (ir->regcache, i))
4307 /* Parse the current instruction and record the values of the registers and
4308 memory that will be changed in current instruction to "record_arch_list".
4309 Return -1 if something wrong. */
4311 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
4312 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
4315 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
4316 CORE_ADDR input_addr)
4318 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4324 gdb_byte buf[MAX_REGISTER_SIZE];
4325 struct i386_record_s ir;
4326 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4331 memset (&ir, 0, sizeof (struct i386_record_s));
4332 ir.regcache = regcache;
4333 ir.addr = input_addr;
4334 ir.orig_addr = input_addr;
4338 ir.popl_esp_hack = 0;
4339 ir.regmap = tdep->record_regmap;
4340 ir.gdbarch = gdbarch;
4342 if (record_debug > 1)
4343 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
4345 paddress (gdbarch, ir.addr));
4350 if (target_read_memory (ir.addr, &opcode8, 1))
4353 printf_unfiltered (_("Process record: error reading memory at "
4354 "addr %s len = 1.\n"),
4355 paddress (gdbarch, ir.addr));
4359 switch (opcode8) /* Instruction prefixes */
4361 case REPE_PREFIX_OPCODE:
4362 prefixes |= PREFIX_REPZ;
4364 case REPNE_PREFIX_OPCODE:
4365 prefixes |= PREFIX_REPNZ;
4367 case LOCK_PREFIX_OPCODE:
4368 prefixes |= PREFIX_LOCK;
4370 case CS_PREFIX_OPCODE:
4371 ir.override = X86_RECORD_CS_REGNUM;
4373 case SS_PREFIX_OPCODE:
4374 ir.override = X86_RECORD_SS_REGNUM;
4376 case DS_PREFIX_OPCODE:
4377 ir.override = X86_RECORD_DS_REGNUM;
4379 case ES_PREFIX_OPCODE:
4380 ir.override = X86_RECORD_ES_REGNUM;
4382 case FS_PREFIX_OPCODE:
4383 ir.override = X86_RECORD_FS_REGNUM;
4385 case GS_PREFIX_OPCODE:
4386 ir.override = X86_RECORD_GS_REGNUM;
4388 case DATA_PREFIX_OPCODE:
4389 prefixes |= PREFIX_DATA;
4391 case ADDR_PREFIX_OPCODE:
4392 prefixes |= PREFIX_ADDR;
4394 case 0x40: /* i386 inc %eax */
4395 case 0x41: /* i386 inc %ecx */
4396 case 0x42: /* i386 inc %edx */
4397 case 0x43: /* i386 inc %ebx */
4398 case 0x44: /* i386 inc %esp */
4399 case 0x45: /* i386 inc %ebp */
4400 case 0x46: /* i386 inc %esi */
4401 case 0x47: /* i386 inc %edi */
4402 case 0x48: /* i386 dec %eax */
4403 case 0x49: /* i386 dec %ecx */
4404 case 0x4a: /* i386 dec %edx */
4405 case 0x4b: /* i386 dec %ebx */
4406 case 0x4c: /* i386 dec %esp */
4407 case 0x4d: /* i386 dec %ebp */
4408 case 0x4e: /* i386 dec %esi */
4409 case 0x4f: /* i386 dec %edi */
4410 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
4414 rex_w = (opcode8 >> 3) & 1;
4415 rex_r = (opcode8 & 0x4) << 1;
4416 ir.rex_x = (opcode8 & 0x2) << 2;
4417 ir.rex_b = (opcode8 & 0x1) << 3;
4419 else /* 32 bit target */
4428 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
4434 if (prefixes & PREFIX_DATA)
4437 if (prefixes & PREFIX_ADDR)
4439 else if (ir.regmap[X86_RECORD_R8_REGNUM])
4442 /* Now check op code. */
4443 opcode = (uint32_t) opcode8;
4448 if (target_read_memory (ir.addr, &opcode8, 1))
4451 printf_unfiltered (_("Process record: error reading memory at "
4452 "addr %s len = 1.\n"),
4453 paddress (gdbarch, ir.addr));
4457 opcode = (uint32_t) opcode8 | 0x0f00;
4461 case 0x00: /* arith & logic */
4509 if (((opcode >> 3) & 7) != OP_CMPL)
4511 if ((opcode & 1) == 0)
4514 ir.ot = ir.dflag + OT_WORD;
4516 switch ((opcode >> 1) & 3)
4518 case 0: /* OP Ev, Gv */
4519 if (i386_record_modrm (&ir))
4523 if (i386_record_lea_modrm (&ir))
4529 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4531 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4534 case 1: /* OP Gv, Ev */
4535 if (i386_record_modrm (&ir))
4538 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4540 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4542 case 2: /* OP A, Iv */
4543 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4547 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4550 case 0x80: /* GRP1 */
4554 if (i386_record_modrm (&ir))
4557 if (ir.reg != OP_CMPL)
4559 if ((opcode & 1) == 0)
4562 ir.ot = ir.dflag + OT_WORD;
4569 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4570 if (i386_record_lea_modrm (&ir))
4574 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
4576 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4579 case 0x40: /* inc */
4588 case 0x48: /* dec */
4597 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7);
4598 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4601 case 0xf6: /* GRP3 */
4603 if ((opcode & 1) == 0)
4606 ir.ot = ir.dflag + OT_WORD;
4607 if (i386_record_modrm (&ir))
4610 if (ir.mod != 3 && ir.reg == 0)
4611 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4616 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4622 if (i386_record_lea_modrm (&ir))
4628 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4630 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4632 if (ir.reg == 3) /* neg */
4633 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4639 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4640 if (ir.ot != OT_BYTE)
4641 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
4642 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4646 opcode = opcode << 8 | ir.modrm;
4652 case 0xfe: /* GRP4 */
4653 case 0xff: /* GRP5 */
4654 if (i386_record_modrm (&ir))
4656 if (ir.reg >= 2 && opcode == 0xfe)
4659 opcode = opcode << 8 | ir.modrm;
4666 if ((opcode & 1) == 0)
4669 ir.ot = ir.dflag + OT_WORD;
4672 if (i386_record_lea_modrm (&ir))
4678 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4680 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4682 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4685 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4687 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4689 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4692 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
4693 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4695 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4699 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4702 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4704 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4709 opcode = opcode << 8 | ir.modrm;
4715 case 0x84: /* test */
4719 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4722 case 0x98: /* CWDE/CBW */
4723 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4726 case 0x99: /* CDQ/CWD */
4727 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4728 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
4731 case 0x0faf: /* imul */
4734 ir.ot = ir.dflag + OT_WORD;
4735 if (i386_record_modrm (&ir))
4738 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4739 else if (opcode == 0x6b)
4742 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4744 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4745 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4748 case 0x0fc0: /* xadd */
4750 if ((opcode & 1) == 0)
4753 ir.ot = ir.dflag + OT_WORD;
4754 if (i386_record_modrm (&ir))
4759 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4761 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4762 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4764 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4768 if (i386_record_lea_modrm (&ir))
4770 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4772 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4774 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4777 case 0x0fb0: /* cmpxchg */
4779 if ((opcode & 1) == 0)
4782 ir.ot = ir.dflag + OT_WORD;
4783 if (i386_record_modrm (&ir))
4788 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4789 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4791 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4795 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4796 if (i386_record_lea_modrm (&ir))
4799 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4802 case 0x0fc7: /* cmpxchg8b */
4803 if (i386_record_modrm (&ir))
4808 opcode = opcode << 8 | ir.modrm;
4811 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4812 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
4813 if (i386_record_lea_modrm (&ir))
4815 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4818 case 0x50: /* push */
4828 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4830 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4834 case 0x06: /* push es */
4835 case 0x0e: /* push cs */
4836 case 0x16: /* push ss */
4837 case 0x1e: /* push ds */
4838 if (ir.regmap[X86_RECORD_R8_REGNUM])
4843 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4847 case 0x0fa0: /* push fs */
4848 case 0x0fa8: /* push gs */
4849 if (ir.regmap[X86_RECORD_R8_REGNUM])
4854 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4858 case 0x60: /* pusha */
4859 if (ir.regmap[X86_RECORD_R8_REGNUM])
4864 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
4868 case 0x58: /* pop */
4876 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4877 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
4880 case 0x61: /* popa */
4881 if (ir.regmap[X86_RECORD_R8_REGNUM])
4886 for (regnum = X86_RECORD_REAX_REGNUM;
4887 regnum <= X86_RECORD_REDI_REGNUM;
4889 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
4892 case 0x8f: /* pop */
4893 if (ir.regmap[X86_RECORD_R8_REGNUM])
4894 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
4896 ir.ot = ir.dflag + OT_WORD;
4897 if (i386_record_modrm (&ir))
4900 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
4903 ir.popl_esp_hack = 1 << ir.ot;
4904 if (i386_record_lea_modrm (&ir))
4907 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4910 case 0xc8: /* enter */
4911 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
4912 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4914 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4918 case 0xc9: /* leave */
4919 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4920 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
4923 case 0x07: /* pop es */
4924 if (ir.regmap[X86_RECORD_R8_REGNUM])
4929 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4930 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
4931 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4934 case 0x17: /* pop ss */
4935 if (ir.regmap[X86_RECORD_R8_REGNUM])
4940 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4941 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
4942 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4945 case 0x1f: /* pop ds */
4946 if (ir.regmap[X86_RECORD_R8_REGNUM])
4951 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4952 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
4953 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4956 case 0x0fa1: /* pop fs */
4957 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4958 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
4959 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4962 case 0x0fa9: /* pop gs */
4963 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4964 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
4965 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4968 case 0x88: /* mov */
4972 if ((opcode & 1) == 0)
4975 ir.ot = ir.dflag + OT_WORD;
4977 if (i386_record_modrm (&ir))
4982 if (opcode == 0xc6 || opcode == 0xc7)
4983 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4984 if (i386_record_lea_modrm (&ir))
4989 if (opcode == 0xc6 || opcode == 0xc7)
4991 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4993 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4997 case 0x8a: /* mov */
4999 if ((opcode & 1) == 0)
5002 ir.ot = ir.dflag + OT_WORD;
5003 if (i386_record_modrm (&ir))
5006 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5008 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
5011 case 0x8c: /* mov seg */
5012 if (i386_record_modrm (&ir))
5017 opcode = opcode << 8 | ir.modrm;
5022 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
5026 if (i386_record_lea_modrm (&ir))
5031 case 0x8e: /* mov seg */
5032 if (i386_record_modrm (&ir))
5037 regnum = X86_RECORD_ES_REGNUM;
5040 regnum = X86_RECORD_SS_REGNUM;
5043 regnum = X86_RECORD_DS_REGNUM;
5046 regnum = X86_RECORD_FS_REGNUM;
5049 regnum = X86_RECORD_GS_REGNUM;
5053 opcode = opcode << 8 | ir.modrm;
5057 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
5058 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5061 case 0x0fb6: /* movzbS */
5062 case 0x0fb7: /* movzwS */
5063 case 0x0fbe: /* movsbS */
5064 case 0x0fbf: /* movswS */
5065 if (i386_record_modrm (&ir))
5067 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5070 case 0x8d: /* lea */
5071 if (i386_record_modrm (&ir))
5076 opcode = opcode << 8 | ir.modrm;
5081 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5083 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
5086 case 0xa0: /* mov EAX */
5089 case 0xd7: /* xlat */
5090 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5093 case 0xa2: /* mov EAX */
5095 if (ir.override >= 0)
5097 if (record_memory_query)
5101 target_terminal_ours ();
5103 Process record ignores the memory change of instruction at address %s\n\
5104 because it can't get the value of the segment register.\n\
5105 Do you want to stop the program?"),
5106 paddress (gdbarch, ir.orig_addr));
5107 target_terminal_inferior ();
5114 if ((opcode & 1) == 0)
5117 ir.ot = ir.dflag + OT_WORD;
5120 if (target_read_memory (ir.addr, buf, 8))
5123 printf_unfiltered (_("Process record: error reading "
5124 "memory at addr 0x%s len = 8.\n"),
5125 paddress (gdbarch, ir.addr));
5129 addr = extract_unsigned_integer (buf, 8, byte_order);
5133 if (target_read_memory (ir.addr, buf, 4))
5136 printf_unfiltered (_("Process record: error reading "
5137 "memory at addr 0x%s len = 4.\n"),
5138 paddress (gdbarch, ir.addr));
5142 addr = extract_unsigned_integer (buf, 4, byte_order);
5146 if (target_read_memory (ir.addr, buf, 2))
5149 printf_unfiltered (_("Process record: error reading "
5150 "memory at addr 0x%s len = 2.\n"),
5151 paddress (gdbarch, ir.addr));
5155 addr = extract_unsigned_integer (buf, 2, byte_order);
5157 if (record_arch_list_add_mem (addr, 1 << ir.ot))
5162 case 0xb0: /* mov R, Ib */
5170 I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
5171 ? ((opcode & 0x7) | ir.rex_b)
5172 : ((opcode & 0x7) & 0x3));
5175 case 0xb8: /* mov R, Iv */
5183 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5186 case 0x91: /* xchg R, EAX */
5193 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5194 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7);
5197 case 0x86: /* xchg Ev, Gv */
5199 if ((opcode & 1) == 0)
5202 ir.ot = ir.dflag + OT_WORD;
5203 if (i386_record_modrm (&ir))
5208 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5210 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
5214 if (i386_record_lea_modrm (&ir))
5218 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5220 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
5223 case 0xc4: /* les Gv */
5224 case 0xc5: /* lds Gv */
5225 if (ir.regmap[X86_RECORD_R8_REGNUM])
5231 case 0x0fb2: /* lss Gv */
5232 case 0x0fb4: /* lfs Gv */
5233 case 0x0fb5: /* lgs Gv */
5234 if (i386_record_modrm (&ir))
5242 opcode = opcode << 8 | ir.modrm;
5247 case 0xc4: /* les Gv */
5248 regnum = X86_RECORD_ES_REGNUM;
5250 case 0xc5: /* lds Gv */
5251 regnum = X86_RECORD_DS_REGNUM;
5253 case 0x0fb2: /* lss Gv */
5254 regnum = X86_RECORD_SS_REGNUM;
5256 case 0x0fb4: /* lfs Gv */
5257 regnum = X86_RECORD_FS_REGNUM;
5259 case 0x0fb5: /* lgs Gv */
5260 regnum = X86_RECORD_GS_REGNUM;
5263 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
5264 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5265 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5268 case 0xc0: /* shifts */
5274 if ((opcode & 1) == 0)
5277 ir.ot = ir.dflag + OT_WORD;
5278 if (i386_record_modrm (&ir))
5280 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
5282 if (i386_record_lea_modrm (&ir))
5288 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5290 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
5292 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5299 if (i386_record_modrm (&ir))
5303 if (record_arch_list_add_reg (ir.regcache, ir.rm))
5308 if (i386_record_lea_modrm (&ir))
5313 case 0xd8: /* Floats. */
5321 if (i386_record_modrm (&ir))
5323 ir.reg |= ((opcode & 7) << 3);
5329 if (i386_record_lea_modrm_addr (&ir, &addr64))
5337 /* For fcom, ficom nothing to do. */
5343 /* For fcomp, ficomp pop FPU stack, store all. */
5344 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5371 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5372 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5373 of code, always affects st(0) register. */
5374 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
5398 /* Handling fld, fild. */
5399 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5403 switch (ir.reg >> 4)
5406 if (record_arch_list_add_mem (addr64, 4))
5410 if (record_arch_list_add_mem (addr64, 8))
5416 if (record_arch_list_add_mem (addr64, 2))
5422 switch (ir.reg >> 4)
5425 if (record_arch_list_add_mem (addr64, 4))
5427 if (3 == (ir.reg & 7))
5429 /* For fstp m32fp. */
5430 if (i386_record_floats (gdbarch, &ir,
5431 I386_SAVE_FPU_REGS))
5436 if (record_arch_list_add_mem (addr64, 4))
5438 if ((3 == (ir.reg & 7))
5439 || (5 == (ir.reg & 7))
5440 || (7 == (ir.reg & 7)))
5442 /* For fstp insn. */
5443 if (i386_record_floats (gdbarch, &ir,
5444 I386_SAVE_FPU_REGS))
5449 if (record_arch_list_add_mem (addr64, 8))
5451 if (3 == (ir.reg & 7))
5453 /* For fstp m64fp. */
5454 if (i386_record_floats (gdbarch, &ir,
5455 I386_SAVE_FPU_REGS))
5460 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
5462 /* For fistp, fbld, fild, fbstp. */
5463 if (i386_record_floats (gdbarch, &ir,
5464 I386_SAVE_FPU_REGS))
5469 if (record_arch_list_add_mem (addr64, 2))
5478 if (i386_record_floats (gdbarch, &ir,
5479 I386_SAVE_FPU_ENV_REG_STACK))
5484 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
5489 if (i386_record_floats (gdbarch, &ir,
5490 I386_SAVE_FPU_ENV_REG_STACK))
5496 if (record_arch_list_add_mem (addr64, 28))
5501 if (record_arch_list_add_mem (addr64, 14))
5507 if (record_arch_list_add_mem (addr64, 2))
5509 /* Insn fstp, fbstp. */
5510 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5515 if (record_arch_list_add_mem (addr64, 10))
5521 if (record_arch_list_add_mem (addr64, 28))
5527 if (record_arch_list_add_mem (addr64, 14))
5531 if (record_arch_list_add_mem (addr64, 80))
5534 if (i386_record_floats (gdbarch, &ir,
5535 I386_SAVE_FPU_ENV_REG_STACK))
5539 if (record_arch_list_add_mem (addr64, 8))
5542 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5547 opcode = opcode << 8 | ir.modrm;
5552 /* Opcode is an extension of modR/M byte. */
5558 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
5562 if (0x0c == (ir.modrm >> 4))
5564 if ((ir.modrm & 0x0f) <= 7)
5566 if (i386_record_floats (gdbarch, &ir,
5567 I386_SAVE_FPU_REGS))
5572 if (i386_record_floats (gdbarch, &ir,
5573 I387_ST0_REGNUM (tdep)))
5575 /* If only st(0) is changing, then we have already
5577 if ((ir.modrm & 0x0f) - 0x08)
5579 if (i386_record_floats (gdbarch, &ir,
5580 I387_ST0_REGNUM (tdep) +
5581 ((ir.modrm & 0x0f) - 0x08)))
5599 if (i386_record_floats (gdbarch, &ir,
5600 I387_ST0_REGNUM (tdep)))
5618 if (i386_record_floats (gdbarch, &ir,
5619 I386_SAVE_FPU_REGS))
5623 if (i386_record_floats (gdbarch, &ir,
5624 I387_ST0_REGNUM (tdep)))
5626 if (i386_record_floats (gdbarch, &ir,
5627 I387_ST0_REGNUM (tdep) + 1))
5634 if (0xe9 == ir.modrm)
5636 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5639 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
5641 if (i386_record_floats (gdbarch, &ir,
5642 I387_ST0_REGNUM (tdep)))
5644 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
5646 if (i386_record_floats (gdbarch, &ir,
5647 I387_ST0_REGNUM (tdep) +
5651 else if ((ir.modrm & 0x0f) - 0x08)
5653 if (i386_record_floats (gdbarch, &ir,
5654 I387_ST0_REGNUM (tdep) +
5655 ((ir.modrm & 0x0f) - 0x08)))
5661 if (0xe3 == ir.modrm)
5663 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
5666 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
5668 if (i386_record_floats (gdbarch, &ir,
5669 I387_ST0_REGNUM (tdep)))
5671 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
5673 if (i386_record_floats (gdbarch, &ir,
5674 I387_ST0_REGNUM (tdep) +
5678 else if ((ir.modrm & 0x0f) - 0x08)
5680 if (i386_record_floats (gdbarch, &ir,
5681 I387_ST0_REGNUM (tdep) +
5682 ((ir.modrm & 0x0f) - 0x08)))
5688 if ((0x0c == ir.modrm >> 4)
5689 || (0x0d == ir.modrm >> 4)
5690 || (0x0f == ir.modrm >> 4))
5692 if ((ir.modrm & 0x0f) <= 7)
5694 if (i386_record_floats (gdbarch, &ir,
5695 I387_ST0_REGNUM (tdep) +
5701 if (i386_record_floats (gdbarch, &ir,
5702 I387_ST0_REGNUM (tdep) +
5703 ((ir.modrm & 0x0f) - 0x08)))
5709 if (0x0c == ir.modrm >> 4)
5711 if (i386_record_floats (gdbarch, &ir,
5712 I387_FTAG_REGNUM (tdep)))
5715 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
5717 if ((ir.modrm & 0x0f) <= 7)
5719 if (i386_record_floats (gdbarch, &ir,
5720 I387_ST0_REGNUM (tdep) +
5726 if (i386_record_floats (gdbarch, &ir,
5727 I386_SAVE_FPU_REGS))
5733 if ((0x0c == ir.modrm >> 4)
5734 || (0x0e == ir.modrm >> 4)
5735 || (0x0f == ir.modrm >> 4)
5736 || (0xd9 == ir.modrm))
5738 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5743 if (0xe0 == ir.modrm)
5745 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
5748 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
5750 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5758 case 0xa4: /* movsS */
5760 case 0xaa: /* stosS */
5762 case 0x6c: /* insS */
5764 regcache_raw_read_unsigned (ir.regcache,
5765 ir.regmap[X86_RECORD_RECX_REGNUM],
5771 if ((opcode & 1) == 0)
5774 ir.ot = ir.dflag + OT_WORD;
5775 regcache_raw_read_unsigned (ir.regcache,
5776 ir.regmap[X86_RECORD_REDI_REGNUM],
5779 regcache_raw_read_unsigned (ir.regcache,
5780 ir.regmap[X86_RECORD_ES_REGNUM],
5782 regcache_raw_read_unsigned (ir.regcache,
5783 ir.regmap[X86_RECORD_DS_REGNUM],
5785 if (ir.aflag && (es != ds))
5787 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5788 if (record_memory_query)
5792 target_terminal_ours ();
5794 Process record ignores the memory change of instruction at address %s\n\
5795 because it can't get the value of the segment register.\n\
5796 Do you want to stop the program?"),
5797 paddress (gdbarch, ir.orig_addr));
5798 target_terminal_inferior ();
5805 if (record_arch_list_add_mem (addr, 1 << ir.ot))
5809 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5810 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5811 if (opcode == 0xa4 || opcode == 0xa5)
5812 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5813 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5814 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5818 case 0xa6: /* cmpsS */
5820 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5821 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5822 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5823 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5824 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5827 case 0xac: /* lodsS */
5829 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5830 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5831 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5832 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5833 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5836 case 0xae: /* scasS */
5838 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5839 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5840 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5841 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5844 case 0x6e: /* outsS */
5846 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5847 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5848 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5849 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5852 case 0xe4: /* port I/O */
5856 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5857 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5867 case 0xc2: /* ret im */
5868 case 0xc3: /* ret */
5869 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5870 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5873 case 0xca: /* lret im */
5874 case 0xcb: /* lret */
5875 case 0xcf: /* iret */
5876 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5877 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5878 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5881 case 0xe8: /* call im */
5882 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5884 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5888 case 0x9a: /* lcall im */
5889 if (ir.regmap[X86_RECORD_R8_REGNUM])
5894 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5895 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5899 case 0xe9: /* jmp im */
5900 case 0xea: /* ljmp im */
5901 case 0xeb: /* jmp Jb */
5902 case 0x70: /* jcc Jb */
5918 case 0x0f80: /* jcc Jv */
5936 case 0x0f90: /* setcc Gv */
5952 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5954 if (i386_record_modrm (&ir))
5957 I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
5961 if (i386_record_lea_modrm (&ir))
5966 case 0x0f40: /* cmov Gv, Ev */
5982 if (i386_record_modrm (&ir))
5985 if (ir.dflag == OT_BYTE)
5987 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
5991 case 0x9c: /* pushf */
5992 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5993 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5995 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5999 case 0x9d: /* popf */
6000 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6001 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6004 case 0x9e: /* sahf */
6005 if (ir.regmap[X86_RECORD_R8_REGNUM])
6011 case 0xf5: /* cmc */
6012 case 0xf8: /* clc */
6013 case 0xf9: /* stc */
6014 case 0xfc: /* cld */
6015 case 0xfd: /* std */
6016 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6019 case 0x9f: /* lahf */
6020 if (ir.regmap[X86_RECORD_R8_REGNUM])
6025 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6026 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6029 /* bit operations */
6030 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6031 ir.ot = ir.dflag + OT_WORD;
6032 if (i386_record_modrm (&ir))
6037 opcode = opcode << 8 | ir.modrm;
6043 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6046 if (i386_record_lea_modrm (&ir))
6050 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6053 case 0x0fa3: /* bt Gv, Ev */
6054 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6057 case 0x0fab: /* bts */
6058 case 0x0fb3: /* btr */
6059 case 0x0fbb: /* btc */
6060 ir.ot = ir.dflag + OT_WORD;
6061 if (i386_record_modrm (&ir))
6064 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6068 if (i386_record_lea_modrm_addr (&ir, &addr64))
6070 regcache_raw_read_unsigned (ir.regcache,
6071 ir.regmap[ir.reg | rex_r],
6076 addr64 += ((int16_t) addr >> 4) << 4;
6079 addr64 += ((int32_t) addr >> 5) << 5;
6082 addr64 += ((int64_t) addr >> 6) << 6;
6085 if (record_arch_list_add_mem (addr64, 1 << ir.ot))
6087 if (i386_record_lea_modrm (&ir))
6090 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6093 case 0x0fbc: /* bsf */
6094 case 0x0fbd: /* bsr */
6095 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6096 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6100 case 0x27: /* daa */
6101 case 0x2f: /* das */
6102 case 0x37: /* aaa */
6103 case 0x3f: /* aas */
6104 case 0xd4: /* aam */
6105 case 0xd5: /* aad */
6106 if (ir.regmap[X86_RECORD_R8_REGNUM])
6111 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6112 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6116 case 0x90: /* nop */
6117 if (prefixes & PREFIX_LOCK)
6124 case 0x9b: /* fwait */
6125 if (target_read_memory (ir.addr, &opcode8, 1))
6128 printf_unfiltered (_("Process record: error reading memory at "
6129 "addr 0x%s len = 1.\n"),
6130 paddress (gdbarch, ir.addr));
6133 opcode = (uint32_t) opcode8;
6139 case 0xcc: /* int3 */
6140 printf_unfiltered (_("Process record does not support instruction "
6147 case 0xcd: /* int */
6151 if (target_read_memory (ir.addr, &interrupt, 1))
6154 printf_unfiltered (_("Process record: error reading memory "
6155 "at addr %s len = 1.\n"),
6156 paddress (gdbarch, ir.addr));
6160 if (interrupt != 0x80
6161 || tdep->i386_intx80_record == NULL)
6163 printf_unfiltered (_("Process record does not support "
6164 "instruction int 0x%02x.\n"),
6169 ret = tdep->i386_intx80_record (ir.regcache);
6176 case 0xce: /* into */
6177 printf_unfiltered (_("Process record does not support "
6178 "instruction into.\n"));
6183 case 0xfa: /* cli */
6184 case 0xfb: /* sti */
6187 case 0x62: /* bound */
6188 printf_unfiltered (_("Process record does not support "
6189 "instruction bound.\n"));
6194 case 0x0fc8: /* bswap reg */
6202 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
6205 case 0xd6: /* salc */
6206 if (ir.regmap[X86_RECORD_R8_REGNUM])
6211 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6212 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6215 case 0xe0: /* loopnz */
6216 case 0xe1: /* loopz */
6217 case 0xe2: /* loop */
6218 case 0xe3: /* jecxz */
6219 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6220 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6223 case 0x0f30: /* wrmsr */
6224 printf_unfiltered (_("Process record does not support "
6225 "instruction wrmsr.\n"));
6230 case 0x0f32: /* rdmsr */
6231 printf_unfiltered (_("Process record does not support "
6232 "instruction rdmsr.\n"));
6237 case 0x0f31: /* rdtsc */
6238 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6239 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6242 case 0x0f34: /* sysenter */
6245 if (ir.regmap[X86_RECORD_R8_REGNUM])
6250 if (tdep->i386_sysenter_record == NULL)
6252 printf_unfiltered (_("Process record does not support "
6253 "instruction sysenter.\n"));
6257 ret = tdep->i386_sysenter_record (ir.regcache);
6263 case 0x0f35: /* sysexit */
6264 printf_unfiltered (_("Process record does not support "
6265 "instruction sysexit.\n"));
6270 case 0x0f05: /* syscall */
6273 if (tdep->i386_syscall_record == NULL)
6275 printf_unfiltered (_("Process record does not support "
6276 "instruction syscall.\n"));
6280 ret = tdep->i386_syscall_record (ir.regcache);
6286 case 0x0f07: /* sysret */
6287 printf_unfiltered (_("Process record does not support "
6288 "instruction sysret.\n"));
6293 case 0x0fa2: /* cpuid */
6294 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6295 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6296 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6297 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
6300 case 0xf4: /* hlt */
6301 printf_unfiltered (_("Process record does not support "
6302 "instruction hlt.\n"));
6308 if (i386_record_modrm (&ir))
6315 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6319 if (i386_record_lea_modrm (&ir))
6328 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6332 opcode = opcode << 8 | ir.modrm;
6339 if (i386_record_modrm (&ir))
6350 opcode = opcode << 8 | ir.modrm;
6353 if (ir.override >= 0)
6355 if (record_memory_query)
6359 target_terminal_ours ();
6361 Process record ignores the memory change of instruction at address %s\n\
6362 because it can't get the value of the segment register.\n\
6363 Do you want to stop the program?"),
6364 paddress (gdbarch, ir.orig_addr));
6365 target_terminal_inferior ();
6372 if (i386_record_lea_modrm_addr (&ir, &addr64))
6374 if (record_arch_list_add_mem (addr64, 2))
6377 if (ir.regmap[X86_RECORD_R8_REGNUM])
6379 if (record_arch_list_add_mem (addr64, 8))
6384 if (record_arch_list_add_mem (addr64, 4))
6395 case 0: /* monitor */
6398 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6402 opcode = opcode << 8 | ir.modrm;
6410 if (ir.override >= 0)
6412 if (record_memory_query)
6416 target_terminal_ours ();
6418 Process record ignores the memory change of instruction at address %s\n\
6419 because it can't get the value of the segment register.\n\
6420 Do you want to stop the program?"),
6421 paddress (gdbarch, ir.orig_addr));
6422 target_terminal_inferior ();
6431 if (i386_record_lea_modrm_addr (&ir, &addr64))
6433 if (record_arch_list_add_mem (addr64, 2))
6436 if (ir.regmap[X86_RECORD_R8_REGNUM])
6438 if (record_arch_list_add_mem (addr64, 8))
6443 if (record_arch_list_add_mem (addr64, 4))
6455 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6456 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6460 else if (ir.rm == 1)
6467 opcode = opcode << 8 | ir.modrm;
6474 if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
6480 if (i386_record_lea_modrm (&ir))
6483 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6486 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6488 case 7: /* invlpg */
6491 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
6492 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
6496 opcode = opcode << 8 | ir.modrm;
6501 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6505 opcode = opcode << 8 | ir.modrm;
6511 case 0x0f08: /* invd */
6512 case 0x0f09: /* wbinvd */
6515 case 0x63: /* arpl */
6516 if (i386_record_modrm (&ir))
6518 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
6520 I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
6521 ? (ir.reg | rex_r) : ir.rm);
6525 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
6526 if (i386_record_lea_modrm (&ir))
6529 if (!ir.regmap[X86_RECORD_R8_REGNUM])
6530 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6533 case 0x0f02: /* lar */
6534 case 0x0f03: /* lsl */
6535 if (i386_record_modrm (&ir))
6537 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6538 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6542 if (i386_record_modrm (&ir))
6544 if (ir.mod == 3 && ir.reg == 3)
6547 opcode = opcode << 8 | ir.modrm;
6559 /* nop (multi byte) */
6562 case 0x0f20: /* mov reg, crN */
6563 case 0x0f22: /* mov crN, reg */
6564 if (i386_record_modrm (&ir))
6566 if ((ir.modrm & 0xc0) != 0xc0)
6569 opcode = opcode << 8 | ir.modrm;
6580 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6582 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6586 opcode = opcode << 8 | ir.modrm;
6592 case 0x0f21: /* mov reg, drN */
6593 case 0x0f23: /* mov drN, reg */
6594 if (i386_record_modrm (&ir))
6596 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
6597 || ir.reg == 5 || ir.reg >= 8)
6600 opcode = opcode << 8 | ir.modrm;
6604 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6606 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6609 case 0x0f06: /* clts */
6610 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6613 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
6615 case 0x0f0d: /* 3DNow! prefetch */
6618 case 0x0f0e: /* 3DNow! femms */
6619 case 0x0f77: /* emms */
6620 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
6622 record_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
6625 case 0x0f0f: /* 3DNow! data */
6626 if (i386_record_modrm (&ir))
6628 if (target_read_memory (ir.addr, &opcode8, 1))
6630 printf_unfiltered (_("Process record: error reading memory at "
6631 "addr %s len = 1.\n"),
6632 paddress (gdbarch, ir.addr));
6638 case 0x0c: /* 3DNow! pi2fw */
6639 case 0x0d: /* 3DNow! pi2fd */
6640 case 0x1c: /* 3DNow! pf2iw */
6641 case 0x1d: /* 3DNow! pf2id */
6642 case 0x8a: /* 3DNow! pfnacc */
6643 case 0x8e: /* 3DNow! pfpnacc */
6644 case 0x90: /* 3DNow! pfcmpge */
6645 case 0x94: /* 3DNow! pfmin */
6646 case 0x96: /* 3DNow! pfrcp */
6647 case 0x97: /* 3DNow! pfrsqrt */
6648 case 0x9a: /* 3DNow! pfsub */
6649 case 0x9e: /* 3DNow! pfadd */
6650 case 0xa0: /* 3DNow! pfcmpgt */
6651 case 0xa4: /* 3DNow! pfmax */
6652 case 0xa6: /* 3DNow! pfrcpit1 */
6653 case 0xa7: /* 3DNow! pfrsqit1 */
6654 case 0xaa: /* 3DNow! pfsubr */
6655 case 0xae: /* 3DNow! pfacc */
6656 case 0xb0: /* 3DNow! pfcmpeq */
6657 case 0xb4: /* 3DNow! pfmul */
6658 case 0xb6: /* 3DNow! pfrcpit2 */
6659 case 0xb7: /* 3DNow! pmulhrw */
6660 case 0xbb: /* 3DNow! pswapd */
6661 case 0xbf: /* 3DNow! pavgusb */
6662 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
6663 goto no_support_3dnow_data;
6664 record_arch_list_add_reg (ir.regcache, ir.reg);
6668 no_support_3dnow_data:
6669 opcode = (opcode << 8) | opcode8;
6675 case 0x0faa: /* rsm */
6676 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6677 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6678 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6679 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6680 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
6681 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6682 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
6683 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6684 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6688 if (i386_record_modrm (&ir))
6692 case 0: /* fxsave */
6696 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6697 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
6699 if (record_arch_list_add_mem (tmpu64, 512))
6704 case 1: /* fxrstor */
6708 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6710 for (i = I387_MM0_REGNUM (tdep);
6711 i386_mmx_regnum_p (gdbarch, i); i++)
6712 record_arch_list_add_reg (ir.regcache, i);
6714 for (i = I387_XMM0_REGNUM (tdep);
6715 i386_xmm_regnum_p (gdbarch, i); i++)
6716 record_arch_list_add_reg (ir.regcache, i);
6718 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
6719 record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
6721 for (i = I387_ST0_REGNUM (tdep);
6722 i386_fp_regnum_p (gdbarch, i); i++)
6723 record_arch_list_add_reg (ir.regcache, i);
6725 for (i = I387_FCTRL_REGNUM (tdep);
6726 i386_fpc_regnum_p (gdbarch, i); i++)
6727 record_arch_list_add_reg (ir.regcache, i);
6731 case 2: /* ldmxcsr */
6732 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
6734 record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
6737 case 3: /* stmxcsr */
6739 if (i386_record_lea_modrm (&ir))
6743 case 5: /* lfence */
6744 case 6: /* mfence */
6745 case 7: /* sfence clflush */
6749 opcode = (opcode << 8) | ir.modrm;
6755 case 0x0fc3: /* movnti */
6756 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
6757 if (i386_record_modrm (&ir))
6762 if (i386_record_lea_modrm (&ir))
6766 /* Add prefix to opcode. */
6893 reswitch_prefix_add:
6901 if (target_read_memory (ir.addr, &opcode8, 1))
6903 printf_unfiltered (_("Process record: error reading memory at "
6904 "addr %s len = 1.\n"),
6905 paddress (gdbarch, ir.addr));
6909 opcode = (uint32_t) opcode8 | opcode << 8;
6910 goto reswitch_prefix_add;
6913 case 0x0f10: /* movups */
6914 case 0x660f10: /* movupd */
6915 case 0xf30f10: /* movss */
6916 case 0xf20f10: /* movsd */
6917 case 0x0f12: /* movlps */
6918 case 0x660f12: /* movlpd */
6919 case 0xf30f12: /* movsldup */
6920 case 0xf20f12: /* movddup */
6921 case 0x0f14: /* unpcklps */
6922 case 0x660f14: /* unpcklpd */
6923 case 0x0f15: /* unpckhps */
6924 case 0x660f15: /* unpckhpd */
6925 case 0x0f16: /* movhps */
6926 case 0x660f16: /* movhpd */
6927 case 0xf30f16: /* movshdup */
6928 case 0x0f28: /* movaps */
6929 case 0x660f28: /* movapd */
6930 case 0x0f2a: /* cvtpi2ps */
6931 case 0x660f2a: /* cvtpi2pd */
6932 case 0xf30f2a: /* cvtsi2ss */
6933 case 0xf20f2a: /* cvtsi2sd */
6934 case 0x0f2c: /* cvttps2pi */
6935 case 0x660f2c: /* cvttpd2pi */
6936 case 0x0f2d: /* cvtps2pi */
6937 case 0x660f2d: /* cvtpd2pi */
6938 case 0x660f3800: /* pshufb */
6939 case 0x660f3801: /* phaddw */
6940 case 0x660f3802: /* phaddd */
6941 case 0x660f3803: /* phaddsw */
6942 case 0x660f3804: /* pmaddubsw */
6943 case 0x660f3805: /* phsubw */
6944 case 0x660f3806: /* phsubd */
6945 case 0x660f3807: /* phsubsw */
6946 case 0x660f3808: /* psignb */
6947 case 0x660f3809: /* psignw */
6948 case 0x660f380a: /* psignd */
6949 case 0x660f380b: /* pmulhrsw */
6950 case 0x660f3810: /* pblendvb */
6951 case 0x660f3814: /* blendvps */
6952 case 0x660f3815: /* blendvpd */
6953 case 0x660f381c: /* pabsb */
6954 case 0x660f381d: /* pabsw */
6955 case 0x660f381e: /* pabsd */
6956 case 0x660f3820: /* pmovsxbw */
6957 case 0x660f3821: /* pmovsxbd */
6958 case 0x660f3822: /* pmovsxbq */
6959 case 0x660f3823: /* pmovsxwd */
6960 case 0x660f3824: /* pmovsxwq */
6961 case 0x660f3825: /* pmovsxdq */
6962 case 0x660f3828: /* pmuldq */
6963 case 0x660f3829: /* pcmpeqq */
6964 case 0x660f382a: /* movntdqa */
6965 case 0x660f3a08: /* roundps */
6966 case 0x660f3a09: /* roundpd */
6967 case 0x660f3a0a: /* roundss */
6968 case 0x660f3a0b: /* roundsd */
6969 case 0x660f3a0c: /* blendps */
6970 case 0x660f3a0d: /* blendpd */
6971 case 0x660f3a0e: /* pblendw */
6972 case 0x660f3a0f: /* palignr */
6973 case 0x660f3a20: /* pinsrb */
6974 case 0x660f3a21: /* insertps */
6975 case 0x660f3a22: /* pinsrd pinsrq */
6976 case 0x660f3a40: /* dpps */
6977 case 0x660f3a41: /* dppd */
6978 case 0x660f3a42: /* mpsadbw */
6979 case 0x660f3a60: /* pcmpestrm */
6980 case 0x660f3a61: /* pcmpestri */
6981 case 0x660f3a62: /* pcmpistrm */
6982 case 0x660f3a63: /* pcmpistri */
6983 case 0x0f51: /* sqrtps */
6984 case 0x660f51: /* sqrtpd */
6985 case 0xf20f51: /* sqrtsd */
6986 case 0xf30f51: /* sqrtss */
6987 case 0x0f52: /* rsqrtps */
6988 case 0xf30f52: /* rsqrtss */
6989 case 0x0f53: /* rcpps */
6990 case 0xf30f53: /* rcpss */
6991 case 0x0f54: /* andps */
6992 case 0x660f54: /* andpd */
6993 case 0x0f55: /* andnps */
6994 case 0x660f55: /* andnpd */
6995 case 0x0f56: /* orps */
6996 case 0x660f56: /* orpd */
6997 case 0x0f57: /* xorps */
6998 case 0x660f57: /* xorpd */
6999 case 0x0f58: /* addps */
7000 case 0x660f58: /* addpd */
7001 case 0xf20f58: /* addsd */
7002 case 0xf30f58: /* addss */
7003 case 0x0f59: /* mulps */
7004 case 0x660f59: /* mulpd */
7005 case 0xf20f59: /* mulsd */
7006 case 0xf30f59: /* mulss */
7007 case 0x0f5a: /* cvtps2pd */
7008 case 0x660f5a: /* cvtpd2ps */
7009 case 0xf20f5a: /* cvtsd2ss */
7010 case 0xf30f5a: /* cvtss2sd */
7011 case 0x0f5b: /* cvtdq2ps */
7012 case 0x660f5b: /* cvtps2dq */
7013 case 0xf30f5b: /* cvttps2dq */
7014 case 0x0f5c: /* subps */
7015 case 0x660f5c: /* subpd */
7016 case 0xf20f5c: /* subsd */
7017 case 0xf30f5c: /* subss */
7018 case 0x0f5d: /* minps */
7019 case 0x660f5d: /* minpd */
7020 case 0xf20f5d: /* minsd */
7021 case 0xf30f5d: /* minss */
7022 case 0x0f5e: /* divps */
7023 case 0x660f5e: /* divpd */
7024 case 0xf20f5e: /* divsd */
7025 case 0xf30f5e: /* divss */
7026 case 0x0f5f: /* maxps */
7027 case 0x660f5f: /* maxpd */
7028 case 0xf20f5f: /* maxsd */
7029 case 0xf30f5f: /* maxss */
7030 case 0x660f60: /* punpcklbw */
7031 case 0x660f61: /* punpcklwd */
7032 case 0x660f62: /* punpckldq */
7033 case 0x660f63: /* packsswb */
7034 case 0x660f64: /* pcmpgtb */
7035 case 0x660f65: /* pcmpgtw */
7036 case 0x660f66: /* pcmpgtd */
7037 case 0x660f67: /* packuswb */
7038 case 0x660f68: /* punpckhbw */
7039 case 0x660f69: /* punpckhwd */
7040 case 0x660f6a: /* punpckhdq */
7041 case 0x660f6b: /* packssdw */
7042 case 0x660f6c: /* punpcklqdq */
7043 case 0x660f6d: /* punpckhqdq */
7044 case 0x660f6e: /* movd */
7045 case 0x660f6f: /* movdqa */
7046 case 0xf30f6f: /* movdqu */
7047 case 0x660f70: /* pshufd */
7048 case 0xf20f70: /* pshuflw */
7049 case 0xf30f70: /* pshufhw */
7050 case 0x660f74: /* pcmpeqb */
7051 case 0x660f75: /* pcmpeqw */
7052 case 0x660f76: /* pcmpeqd */
7053 case 0x660f7c: /* haddpd */
7054 case 0xf20f7c: /* haddps */
7055 case 0x660f7d: /* hsubpd */
7056 case 0xf20f7d: /* hsubps */
7057 case 0xf30f7e: /* movq */
7058 case 0x0fc2: /* cmpps */
7059 case 0x660fc2: /* cmppd */
7060 case 0xf20fc2: /* cmpsd */
7061 case 0xf30fc2: /* cmpss */
7062 case 0x660fc4: /* pinsrw */
7063 case 0x0fc6: /* shufps */
7064 case 0x660fc6: /* shufpd */
7065 case 0x660fd0: /* addsubpd */
7066 case 0xf20fd0: /* addsubps */
7067 case 0x660fd1: /* psrlw */
7068 case 0x660fd2: /* psrld */
7069 case 0x660fd3: /* psrlq */
7070 case 0x660fd4: /* paddq */
7071 case 0x660fd5: /* pmullw */
7072 case 0xf30fd6: /* movq2dq */
7073 case 0x660fd8: /* psubusb */
7074 case 0x660fd9: /* psubusw */
7075 case 0x660fda: /* pminub */
7076 case 0x660fdb: /* pand */
7077 case 0x660fdc: /* paddusb */
7078 case 0x660fdd: /* paddusw */
7079 case 0x660fde: /* pmaxub */
7080 case 0x660fdf: /* pandn */
7081 case 0x660fe0: /* pavgb */
7082 case 0x660fe1: /* psraw */
7083 case 0x660fe2: /* psrad */
7084 case 0x660fe3: /* pavgw */
7085 case 0x660fe4: /* pmulhuw */
7086 case 0x660fe5: /* pmulhw */
7087 case 0x660fe6: /* cvttpd2dq */
7088 case 0xf20fe6: /* cvtpd2dq */
7089 case 0xf30fe6: /* cvtdq2pd */
7090 case 0x660fe8: /* psubsb */
7091 case 0x660fe9: /* psubsw */
7092 case 0x660fea: /* pminsw */
7093 case 0x660feb: /* por */
7094 case 0x660fec: /* paddsb */
7095 case 0x660fed: /* paddsw */
7096 case 0x660fee: /* pmaxsw */
7097 case 0x660fef: /* pxor */
7098 case 0xf20ff0: /* lddqu */
7099 case 0x660ff1: /* psllw */
7100 case 0x660ff2: /* pslld */
7101 case 0x660ff3: /* psllq */
7102 case 0x660ff4: /* pmuludq */
7103 case 0x660ff5: /* pmaddwd */
7104 case 0x660ff6: /* psadbw */
7105 case 0x660ff8: /* psubb */
7106 case 0x660ff9: /* psubw */
7107 case 0x660ffa: /* psubd */
7108 case 0x660ffb: /* psubq */
7109 case 0x660ffc: /* paddb */
7110 case 0x660ffd: /* paddw */
7111 case 0x660ffe: /* paddd */
7112 if (i386_record_modrm (&ir))
7115 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
7117 record_arch_list_add_reg (ir.regcache,
7118 I387_XMM0_REGNUM (tdep) + ir.reg);
7119 if ((opcode & 0xfffffffc) == 0x660f3a60)
7120 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7123 case 0x0f11: /* movups */
7124 case 0x660f11: /* movupd */
7125 case 0xf30f11: /* movss */
7126 case 0xf20f11: /* movsd */
7127 case 0x0f13: /* movlps */
7128 case 0x660f13: /* movlpd */
7129 case 0x0f17: /* movhps */
7130 case 0x660f17: /* movhpd */
7131 case 0x0f29: /* movaps */
7132 case 0x660f29: /* movapd */
7133 case 0x660f3a14: /* pextrb */
7134 case 0x660f3a15: /* pextrw */
7135 case 0x660f3a16: /* pextrd pextrq */
7136 case 0x660f3a17: /* extractps */
7137 case 0x660f7f: /* movdqa */
7138 case 0xf30f7f: /* movdqu */
7139 if (i386_record_modrm (&ir))
7143 if (opcode == 0x0f13 || opcode == 0x660f13
7144 || opcode == 0x0f17 || opcode == 0x660f17)
7147 if (!i386_xmm_regnum_p (gdbarch,
7148 I387_XMM0_REGNUM (tdep) + ir.rm))
7150 record_arch_list_add_reg (ir.regcache,
7151 I387_XMM0_REGNUM (tdep) + ir.rm);
7173 if (i386_record_lea_modrm (&ir))
7178 case 0x0f2b: /* movntps */
7179 case 0x660f2b: /* movntpd */
7180 case 0x0fe7: /* movntq */
7181 case 0x660fe7: /* movntdq */
7184 if (opcode == 0x0fe7)
7188 if (i386_record_lea_modrm (&ir))
7192 case 0xf30f2c: /* cvttss2si */
7193 case 0xf20f2c: /* cvttsd2si */
7194 case 0xf30f2d: /* cvtss2si */
7195 case 0xf20f2d: /* cvtsd2si */
7196 case 0xf20f38f0: /* crc32 */
7197 case 0xf20f38f1: /* crc32 */
7198 case 0x0f50: /* movmskps */
7199 case 0x660f50: /* movmskpd */
7200 case 0x0fc5: /* pextrw */
7201 case 0x660fc5: /* pextrw */
7202 case 0x0fd7: /* pmovmskb */
7203 case 0x660fd7: /* pmovmskb */
7204 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7207 case 0x0f3800: /* pshufb */
7208 case 0x0f3801: /* phaddw */
7209 case 0x0f3802: /* phaddd */
7210 case 0x0f3803: /* phaddsw */
7211 case 0x0f3804: /* pmaddubsw */
7212 case 0x0f3805: /* phsubw */
7213 case 0x0f3806: /* phsubd */
7214 case 0x0f3807: /* phsubsw */
7215 case 0x0f3808: /* psignb */
7216 case 0x0f3809: /* psignw */
7217 case 0x0f380a: /* psignd */
7218 case 0x0f380b: /* pmulhrsw */
7219 case 0x0f381c: /* pabsb */
7220 case 0x0f381d: /* pabsw */
7221 case 0x0f381e: /* pabsd */
7222 case 0x0f382b: /* packusdw */
7223 case 0x0f3830: /* pmovzxbw */
7224 case 0x0f3831: /* pmovzxbd */
7225 case 0x0f3832: /* pmovzxbq */
7226 case 0x0f3833: /* pmovzxwd */
7227 case 0x0f3834: /* pmovzxwq */
7228 case 0x0f3835: /* pmovzxdq */
7229 case 0x0f3837: /* pcmpgtq */
7230 case 0x0f3838: /* pminsb */
7231 case 0x0f3839: /* pminsd */
7232 case 0x0f383a: /* pminuw */
7233 case 0x0f383b: /* pminud */
7234 case 0x0f383c: /* pmaxsb */
7235 case 0x0f383d: /* pmaxsd */
7236 case 0x0f383e: /* pmaxuw */
7237 case 0x0f383f: /* pmaxud */
7238 case 0x0f3840: /* pmulld */
7239 case 0x0f3841: /* phminposuw */
7240 case 0x0f3a0f: /* palignr */
7241 case 0x0f60: /* punpcklbw */
7242 case 0x0f61: /* punpcklwd */
7243 case 0x0f62: /* punpckldq */
7244 case 0x0f63: /* packsswb */
7245 case 0x0f64: /* pcmpgtb */
7246 case 0x0f65: /* pcmpgtw */
7247 case 0x0f66: /* pcmpgtd */
7248 case 0x0f67: /* packuswb */
7249 case 0x0f68: /* punpckhbw */
7250 case 0x0f69: /* punpckhwd */
7251 case 0x0f6a: /* punpckhdq */
7252 case 0x0f6b: /* packssdw */
7253 case 0x0f6e: /* movd */
7254 case 0x0f6f: /* movq */
7255 case 0x0f70: /* pshufw */
7256 case 0x0f74: /* pcmpeqb */
7257 case 0x0f75: /* pcmpeqw */
7258 case 0x0f76: /* pcmpeqd */
7259 case 0x0fc4: /* pinsrw */
7260 case 0x0fd1: /* psrlw */
7261 case 0x0fd2: /* psrld */
7262 case 0x0fd3: /* psrlq */
7263 case 0x0fd4: /* paddq */
7264 case 0x0fd5: /* pmullw */
7265 case 0xf20fd6: /* movdq2q */
7266 case 0x0fd8: /* psubusb */
7267 case 0x0fd9: /* psubusw */
7268 case 0x0fda: /* pminub */
7269 case 0x0fdb: /* pand */
7270 case 0x0fdc: /* paddusb */
7271 case 0x0fdd: /* paddusw */
7272 case 0x0fde: /* pmaxub */
7273 case 0x0fdf: /* pandn */
7274 case 0x0fe0: /* pavgb */
7275 case 0x0fe1: /* psraw */
7276 case 0x0fe2: /* psrad */
7277 case 0x0fe3: /* pavgw */
7278 case 0x0fe4: /* pmulhuw */
7279 case 0x0fe5: /* pmulhw */
7280 case 0x0fe8: /* psubsb */
7281 case 0x0fe9: /* psubsw */
7282 case 0x0fea: /* pminsw */
7283 case 0x0feb: /* por */
7284 case 0x0fec: /* paddsb */
7285 case 0x0fed: /* paddsw */
7286 case 0x0fee: /* pmaxsw */
7287 case 0x0fef: /* pxor */
7288 case 0x0ff1: /* psllw */
7289 case 0x0ff2: /* pslld */
7290 case 0x0ff3: /* psllq */
7291 case 0x0ff4: /* pmuludq */
7292 case 0x0ff5: /* pmaddwd */
7293 case 0x0ff6: /* psadbw */
7294 case 0x0ff8: /* psubb */
7295 case 0x0ff9: /* psubw */
7296 case 0x0ffa: /* psubd */
7297 case 0x0ffb: /* psubq */
7298 case 0x0ffc: /* paddb */
7299 case 0x0ffd: /* paddw */
7300 case 0x0ffe: /* paddd */
7301 if (i386_record_modrm (&ir))
7303 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7305 record_arch_list_add_reg (ir.regcache,
7306 I387_MM0_REGNUM (tdep) + ir.reg);
7309 case 0x0f71: /* psllw */
7310 case 0x0f72: /* pslld */
7311 case 0x0f73: /* psllq */
7312 if (i386_record_modrm (&ir))
7314 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7316 record_arch_list_add_reg (ir.regcache,
7317 I387_MM0_REGNUM (tdep) + ir.rm);
7320 case 0x660f71: /* psllw */
7321 case 0x660f72: /* pslld */
7322 case 0x660f73: /* psllq */
7323 if (i386_record_modrm (&ir))
7326 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
7328 record_arch_list_add_reg (ir.regcache,
7329 I387_XMM0_REGNUM (tdep) + ir.rm);
7332 case 0x0f7e: /* movd */
7333 case 0x660f7e: /* movd */
7334 if (i386_record_modrm (&ir))
7337 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7344 if (i386_record_lea_modrm (&ir))
7349 case 0x0f7f: /* movq */
7350 if (i386_record_modrm (&ir))
7354 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7356 record_arch_list_add_reg (ir.regcache,
7357 I387_MM0_REGNUM (tdep) + ir.rm);
7362 if (i386_record_lea_modrm (&ir))
7367 case 0xf30fb8: /* popcnt */
7368 if (i386_record_modrm (&ir))
7370 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
7371 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7374 case 0x660fd6: /* movq */
7375 if (i386_record_modrm (&ir))
7380 if (!i386_xmm_regnum_p (gdbarch,
7381 I387_XMM0_REGNUM (tdep) + ir.rm))
7383 record_arch_list_add_reg (ir.regcache,
7384 I387_XMM0_REGNUM (tdep) + ir.rm);
7389 if (i386_record_lea_modrm (&ir))
7394 case 0x660f3817: /* ptest */
7395 case 0x0f2e: /* ucomiss */
7396 case 0x660f2e: /* ucomisd */
7397 case 0x0f2f: /* comiss */
7398 case 0x660f2f: /* comisd */
7399 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7402 case 0x0ff7: /* maskmovq */
7403 regcache_raw_read_unsigned (ir.regcache,
7404 ir.regmap[X86_RECORD_REDI_REGNUM],
7406 if (record_arch_list_add_mem (addr, 64))
7410 case 0x660ff7: /* maskmovdqu */
7411 regcache_raw_read_unsigned (ir.regcache,
7412 ir.regmap[X86_RECORD_REDI_REGNUM],
7414 if (record_arch_list_add_mem (addr, 128))
7429 /* In the future, maybe still need to deal with need_dasm. */
7430 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
7431 if (record_arch_list_add_end ())
7437 printf_unfiltered (_("Process record does not support instruction 0x%02x "
7438 "at address %s.\n"),
7439 (unsigned int) (opcode),
7440 paddress (gdbarch, ir.orig_addr));
7444 static const int i386_record_regmap[] =
7446 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
7447 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
7448 0, 0, 0, 0, 0, 0, 0, 0,
7449 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
7450 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
7453 /* Check that the given address appears suitable for a fast
7454 tracepoint, which on x86-64 means that we need an instruction of at
7455 least 5 bytes, so that we can overwrite it with a 4-byte-offset
7456 jump and not have to worry about program jumps to an address in the
7457 middle of the tracepoint jump. On x86, it may be possible to use
7458 4-byte jumps with a 2-byte offset to a trampoline located in the
7459 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
7460 of instruction to replace, and 0 if not, plus an explanatory
7464 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch,
7465 CORE_ADDR addr, int *isize, char **msg)
7468 static struct ui_file *gdb_null = NULL;
7470 /* Ask the target for the minimum instruction length supported. */
7471 jumplen = target_get_min_fast_tracepoint_insn_len ();
7475 /* If the target does not support the get_min_fast_tracepoint_insn_len
7476 operation, assume that fast tracepoints will always be implemented
7477 using 4-byte relative jumps on both x86 and x86-64. */
7480 else if (jumplen == 0)
7482 /* If the target does support get_min_fast_tracepoint_insn_len but
7483 returns zero, then the IPA has not loaded yet. In this case,
7484 we optimistically assume that truncated 2-byte relative jumps
7485 will be available on x86, and compensate later if this assumption
7486 turns out to be incorrect. On x86-64 architectures, 4-byte relative
7487 jumps will always be used. */
7488 jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4;
7491 /* Dummy file descriptor for the disassembler. */
7493 gdb_null = ui_file_new ();
7495 /* Check for fit. */
7496 len = gdb_print_insn (gdbarch, addr, gdb_null, NULL);
7502 /* Return a bit of target-specific detail to add to the caller's
7503 generic failure message. */
7505 *msg = xstrprintf (_("; instruction is only %d bytes long, "
7506 "need at least %d bytes for the jump"),
7519 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
7520 struct tdesc_arch_data *tdesc_data)
7522 const struct target_desc *tdesc = tdep->tdesc;
7523 const struct tdesc_feature *feature_core;
7524 const struct tdesc_feature *feature_sse, *feature_avx;
7525 int i, num_regs, valid_p;
7527 if (! tdesc_has_registers (tdesc))
7530 /* Get core registers. */
7531 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
7532 if (feature_core == NULL)
7535 /* Get SSE registers. */
7536 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
7538 /* Try AVX registers. */
7539 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
7543 /* The XCR0 bits. */
7546 /* AVX register description requires SSE register description. */
7550 tdep->xcr0 = I386_XSTATE_AVX_MASK;
7552 /* It may have been set by OSABI initialization function. */
7553 if (tdep->num_ymm_regs == 0)
7555 tdep->ymmh_register_names = i386_ymmh_names;
7556 tdep->num_ymm_regs = 8;
7557 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
7560 for (i = 0; i < tdep->num_ymm_regs; i++)
7561 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
7562 tdep->ymm0h_regnum + i,
7563 tdep->ymmh_register_names[i]);
7565 else if (feature_sse)
7566 tdep->xcr0 = I386_XSTATE_SSE_MASK;
7569 tdep->xcr0 = I386_XSTATE_X87_MASK;
7570 tdep->num_xmm_regs = 0;
7573 num_regs = tdep->num_core_regs;
7574 for (i = 0; i < num_regs; i++)
7575 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
7576 tdep->register_names[i]);
7580 /* Need to include %mxcsr, so add one. */
7581 num_regs += tdep->num_xmm_regs + 1;
7582 for (; i < num_regs; i++)
7583 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
7584 tdep->register_names[i]);
7591 static struct gdbarch *
7592 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
7594 struct gdbarch_tdep *tdep;
7595 struct gdbarch *gdbarch;
7596 struct tdesc_arch_data *tdesc_data;
7597 const struct target_desc *tdesc;
7601 /* If there is already a candidate, use it. */
7602 arches = gdbarch_list_lookup_by_info (arches, &info);
7604 return arches->gdbarch;
7606 /* Allocate space for the new architecture. */
7607 tdep = XCALLOC (1, struct gdbarch_tdep);
7608 gdbarch = gdbarch_alloc (&info, tdep);
7610 /* General-purpose registers. */
7611 tdep->gregset = NULL;
7612 tdep->gregset_reg_offset = NULL;
7613 tdep->gregset_num_regs = I386_NUM_GREGS;
7614 tdep->sizeof_gregset = 0;
7616 /* Floating-point registers. */
7617 tdep->fpregset = NULL;
7618 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
7620 tdep->xstateregset = NULL;
7622 /* The default settings include the FPU registers, the MMX registers
7623 and the SSE registers. This can be overridden for a specific ABI
7624 by adjusting the members `st0_regnum', `mm0_regnum' and
7625 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
7626 will show up in the output of "info all-registers". */
7628 tdep->st0_regnum = I386_ST0_REGNUM;
7630 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
7631 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
7633 tdep->jb_pc_offset = -1;
7634 tdep->struct_return = pcc_struct_return;
7635 tdep->sigtramp_start = 0;
7636 tdep->sigtramp_end = 0;
7637 tdep->sigtramp_p = i386_sigtramp_p;
7638 tdep->sigcontext_addr = NULL;
7639 tdep->sc_reg_offset = NULL;
7640 tdep->sc_pc_offset = -1;
7641 tdep->sc_sp_offset = -1;
7643 tdep->xsave_xcr0_offset = -1;
7645 tdep->record_regmap = i386_record_regmap;
7647 set_gdbarch_long_long_align_bit (gdbarch, 32);
7649 /* The format used for `long double' on almost all i386 targets is
7650 the i387 extended floating-point format. In fact, of all targets
7651 in the GCC 2.95 tree, only OSF/1 does it different, and insists
7652 on having a `long double' that's not `long' at all. */
7653 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
7655 /* Although the i387 extended floating-point has only 80 significant
7656 bits, a `long double' actually takes up 96, probably to enforce
7658 set_gdbarch_long_double_bit (gdbarch, 96);
7660 /* Register numbers of various important registers. */
7661 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
7662 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
7663 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
7664 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
7666 /* NOTE: kettenis/20040418: GCC does have two possible register
7667 numbering schemes on the i386: dbx and SVR4. These schemes
7668 differ in how they number %ebp, %esp, %eflags, and the
7669 floating-point registers, and are implemented by the arrays
7670 dbx_register_map[] and svr4_dbx_register_map in
7671 gcc/config/i386.c. GCC also defines a third numbering scheme in
7672 gcc/config/i386.c, which it designates as the "default" register
7673 map used in 64bit mode. This last register numbering scheme is
7674 implemented in dbx64_register_map, and is used for AMD64; see
7677 Currently, each GCC i386 target always uses the same register
7678 numbering scheme across all its supported debugging formats
7679 i.e. SDB (COFF), stabs and DWARF 2. This is because
7680 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7681 DBX_REGISTER_NUMBER macro which is defined by each target's
7682 respective config header in a manner independent of the requested
7683 output debugging format.
7685 This does not match the arrangement below, which presumes that
7686 the SDB and stabs numbering schemes differ from the DWARF and
7687 DWARF 2 ones. The reason for this arrangement is that it is
7688 likely to get the numbering scheme for the target's
7689 default/native debug format right. For targets where GCC is the
7690 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7691 targets where the native toolchain uses a different numbering
7692 scheme for a particular debug format (stabs-in-ELF on Solaris)
7693 the defaults below will have to be overridden, like
7694 i386_elf_init_abi() does. */
7696 /* Use the dbx register numbering scheme for stabs and COFF. */
7697 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
7698 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
7700 /* Use the SVR4 register numbering scheme for DWARF 2. */
7701 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
7703 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7704 be in use on any of the supported i386 targets. */
7706 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
7708 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
7710 /* Call dummy code. */
7711 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
7712 set_gdbarch_frame_align (gdbarch, i386_frame_align);
7714 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
7715 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
7716 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
7718 set_gdbarch_return_value (gdbarch, i386_return_value);
7720 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
7722 /* Stack grows downward. */
7723 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
7725 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc);
7726 set_gdbarch_decr_pc_after_break (gdbarch, 1);
7727 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
7729 set_gdbarch_frame_args_skip (gdbarch, 8);
7731 set_gdbarch_print_insn (gdbarch, i386_print_insn);
7733 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
7735 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
7737 /* Add the i386 register groups. */
7738 i386_add_reggroups (gdbarch);
7739 tdep->register_reggroup_p = i386_register_reggroup_p;
7741 /* Helper for function argument information. */
7742 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
7744 /* Hook the function epilogue frame unwinder. This unwinder is
7745 appended to the list first, so that it supercedes the DWARF
7746 unwinder in function epilogues (where the DWARF unwinder
7747 currently fails). */
7748 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
7750 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7751 to the list before the prologue-based unwinders, so that DWARF
7752 CFI info will be used if it is available. */
7753 dwarf2_append_unwinders (gdbarch);
7755 frame_base_set_default (gdbarch, &i386_frame_base);
7757 /* Pseudo registers may be changed by amd64_init_abi. */
7758 set_gdbarch_pseudo_register_read_value (gdbarch,
7759 i386_pseudo_register_read_value);
7760 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
7762 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
7763 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
7765 /* Override the normal target description method to make the AVX
7766 upper halves anonymous. */
7767 set_gdbarch_register_name (gdbarch, i386_register_name);
7769 /* Even though the default ABI only includes general-purpose registers,
7770 floating-point registers and the SSE registers, we have to leave a
7771 gap for the upper AVX registers. */
7772 set_gdbarch_num_regs (gdbarch, I386_AVX_NUM_REGS);
7774 /* Get the x86 target description from INFO. */
7775 tdesc = info.target_desc;
7776 if (! tdesc_has_registers (tdesc))
7778 tdep->tdesc = tdesc;
7780 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
7781 tdep->register_names = i386_register_names;
7783 /* No upper YMM registers. */
7784 tdep->ymmh_register_names = NULL;
7785 tdep->ymm0h_regnum = -1;
7787 tdep->num_byte_regs = 8;
7788 tdep->num_word_regs = 8;
7789 tdep->num_dword_regs = 0;
7790 tdep->num_mmx_regs = 8;
7791 tdep->num_ymm_regs = 0;
7793 tdesc_data = tdesc_data_alloc ();
7795 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
7797 set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address);
7799 /* Hook in ABI-specific overrides, if they have been registered. */
7800 info.tdep_info = (void *) tdesc_data;
7801 gdbarch_init_osabi (info, gdbarch);
7803 if (!i386_validate_tdesc_p (tdep, tdesc_data))
7805 tdesc_data_cleanup (tdesc_data);
7807 gdbarch_free (gdbarch);
7811 /* Wire in pseudo registers. Number of pseudo registers may be
7813 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
7814 + tdep->num_word_regs
7815 + tdep->num_dword_regs
7816 + tdep->num_mmx_regs
7817 + tdep->num_ymm_regs));
7819 /* Target description may be changed. */
7820 tdesc = tdep->tdesc;
7822 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
7824 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7825 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
7827 /* Make %al the first pseudo-register. */
7828 tdep->al_regnum = gdbarch_num_regs (gdbarch);
7829 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
7831 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
7832 if (tdep->num_dword_regs)
7834 /* Support dword pseudo-register if it hasn't been disabled. */
7835 tdep->eax_regnum = ymm0_regnum;
7836 ymm0_regnum += tdep->num_dword_regs;
7839 tdep->eax_regnum = -1;
7841 mm0_regnum = ymm0_regnum;
7842 if (tdep->num_ymm_regs)
7844 /* Support YMM pseudo-register if it is available. */
7845 tdep->ymm0_regnum = ymm0_regnum;
7846 mm0_regnum += tdep->num_ymm_regs;
7849 tdep->ymm0_regnum = -1;
7851 if (tdep->num_mmx_regs != 0)
7853 /* Support MMX pseudo-register if MMX hasn't been disabled. */
7854 tdep->mm0_regnum = mm0_regnum;
7857 tdep->mm0_regnum = -1;
7859 /* Hook in the legacy prologue-based unwinders last (fallback). */
7860 frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind);
7861 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
7862 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
7864 /* If we have a register mapping, enable the generic core file
7865 support, unless it has already been enabled. */
7866 if (tdep->gregset_reg_offset
7867 && !gdbarch_regset_from_core_section_p (gdbarch))
7868 set_gdbarch_regset_from_core_section (gdbarch,
7869 i386_regset_from_core_section);
7871 set_gdbarch_skip_permanent_breakpoint (gdbarch,
7872 i386_skip_permanent_breakpoint);
7874 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
7875 i386_fast_tracepoint_valid_at);
7880 static enum gdb_osabi
7881 i386_coff_osabi_sniffer (bfd *abfd)
7883 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
7884 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
7885 return GDB_OSABI_GO32;
7887 return GDB_OSABI_UNKNOWN;
7891 /* Provide a prototype to silence -Wmissing-prototypes. */
7892 void _initialize_i386_tdep (void);
7895 _initialize_i386_tdep (void)
7897 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
7899 /* Add the variable that controls the disassembly flavor. */
7900 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
7901 &disassembly_flavor, _("\
7902 Set the disassembly flavor."), _("\
7903 Show the disassembly flavor."), _("\
7904 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7906 NULL, /* FIXME: i18n: */
7907 &setlist, &showlist);
7909 /* Add the variable that controls the convention for returning
7911 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
7912 &struct_convention, _("\
7913 Set the convention for returning small structs."), _("\
7914 Show the convention for returning small structs."), _("\
7915 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7918 NULL, /* FIXME: i18n: */
7919 &setlist, &showlist);
7921 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
7922 i386_coff_osabi_sniffer);
7924 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
7925 i386_svr4_init_abi);
7926 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
7927 i386_go32_init_abi);
7929 /* Initialize the i386-specific register groups. */
7930 i386_init_reggroups ();
7932 /* Initialize the standard target descriptions. */
7933 initialize_tdesc_i386 ();
7934 initialize_tdesc_i386_mmx ();
7935 initialize_tdesc_i386_avx ();
7937 /* Tell remote stub that we support XML target description. */
7938 register_remote_support_xml ("i386");