1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2014 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
38 #include "reggroups.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "x86-xstate.h"
52 #include "record-full.h"
55 #include "features/i386/i386.c"
56 #include "features/i386/i386-avx.c"
57 #include "features/i386/i386-mpx.c"
58 #include "features/i386/i386-avx512.c"
59 #include "features/i386/i386-mmx.c"
64 #include "stap-probe.h"
65 #include "user-regs.h"
66 #include "cli/cli-utils.h"
67 #include "expression.h"
68 #include "parser-defs.h"
73 static const char *i386_register_names[] =
75 "eax", "ecx", "edx", "ebx",
76 "esp", "ebp", "esi", "edi",
77 "eip", "eflags", "cs", "ss",
78 "ds", "es", "fs", "gs",
79 "st0", "st1", "st2", "st3",
80 "st4", "st5", "st6", "st7",
81 "fctrl", "fstat", "ftag", "fiseg",
82 "fioff", "foseg", "fooff", "fop",
83 "xmm0", "xmm1", "xmm2", "xmm3",
84 "xmm4", "xmm5", "xmm6", "xmm7",
88 static const char *i386_zmm_names[] =
90 "zmm0", "zmm1", "zmm2", "zmm3",
91 "zmm4", "zmm5", "zmm6", "zmm7"
94 static const char *i386_zmmh_names[] =
96 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
97 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
100 static const char *i386_k_names[] =
102 "k0", "k1", "k2", "k3",
103 "k4", "k5", "k6", "k7"
106 static const char *i386_ymm_names[] =
108 "ymm0", "ymm1", "ymm2", "ymm3",
109 "ymm4", "ymm5", "ymm6", "ymm7",
112 static const char *i386_ymmh_names[] =
114 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
115 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
118 static const char *i386_mpx_names[] =
120 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
123 /* Register names for MPX pseudo-registers. */
125 static const char *i386_bnd_names[] =
127 "bnd0", "bnd1", "bnd2", "bnd3"
130 /* Register names for MMX pseudo-registers. */
132 static const char *i386_mmx_names[] =
134 "mm0", "mm1", "mm2", "mm3",
135 "mm4", "mm5", "mm6", "mm7"
138 /* Register names for byte pseudo-registers. */
140 static const char *i386_byte_names[] =
142 "al", "cl", "dl", "bl",
143 "ah", "ch", "dh", "bh"
146 /* Register names for word pseudo-registers. */
148 static const char *i386_word_names[] =
150 "ax", "cx", "dx", "bx",
154 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
155 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
156 we have 16 upper ZMM regs that have to be handled differently. */
158 const int num_lower_zmm_regs = 16;
163 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
165 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
166 int mm0_regnum = tdep->mm0_regnum;
171 regnum -= mm0_regnum;
172 return regnum >= 0 && regnum < tdep->num_mmx_regs;
178 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
180 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
182 regnum -= tdep->al_regnum;
183 return regnum >= 0 && regnum < tdep->num_byte_regs;
189 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
191 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
193 regnum -= tdep->ax_regnum;
194 return regnum >= 0 && regnum < tdep->num_word_regs;
197 /* Dword register? */
200 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
202 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
203 int eax_regnum = tdep->eax_regnum;
208 regnum -= eax_regnum;
209 return regnum >= 0 && regnum < tdep->num_dword_regs;
212 /* AVX512 register? */
215 i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum)
217 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
218 int zmm0h_regnum = tdep->zmm0h_regnum;
220 if (zmm0h_regnum < 0)
223 regnum -= zmm0h_regnum;
224 return regnum >= 0 && regnum < tdep->num_zmm_regs;
228 i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum)
230 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
231 int zmm0_regnum = tdep->zmm0_regnum;
236 regnum -= zmm0_regnum;
237 return regnum >= 0 && regnum < tdep->num_zmm_regs;
241 i386_k_regnum_p (struct gdbarch *gdbarch, int regnum)
243 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
244 int k0_regnum = tdep->k0_regnum;
250 return regnum >= 0 && regnum < I387_NUM_K_REGS;
254 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
256 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
257 int ymm0h_regnum = tdep->ymm0h_regnum;
259 if (ymm0h_regnum < 0)
262 regnum -= ymm0h_regnum;
263 return regnum >= 0 && regnum < tdep->num_ymm_regs;
269 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
271 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
272 int ymm0_regnum = tdep->ymm0_regnum;
277 regnum -= ymm0_regnum;
278 return regnum >= 0 && regnum < tdep->num_ymm_regs;
282 i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
284 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
285 int ymm16h_regnum = tdep->ymm16h_regnum;
287 if (ymm16h_regnum < 0)
290 regnum -= ymm16h_regnum;
291 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
295 i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
297 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
298 int ymm16_regnum = tdep->ymm16_regnum;
300 if (ymm16_regnum < 0)
303 regnum -= ymm16_regnum;
304 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
310 i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum)
312 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
313 int bnd0_regnum = tdep->bnd0_regnum;
318 regnum -= bnd0_regnum;
319 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
325 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
327 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
328 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
330 if (num_xmm_regs == 0)
333 regnum -= I387_XMM0_REGNUM (tdep);
334 return regnum >= 0 && regnum < num_xmm_regs;
337 /* XMM_512 register? */
340 i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
342 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
343 int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep);
345 if (num_xmm_avx512_regs == 0)
348 regnum -= I387_XMM16_REGNUM (tdep);
349 return regnum >= 0 && regnum < num_xmm_avx512_regs;
353 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
355 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
357 if (I387_NUM_XMM_REGS (tdep) == 0)
360 return (regnum == I387_MXCSR_REGNUM (tdep));
366 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
368 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
370 if (I387_ST0_REGNUM (tdep) < 0)
373 return (I387_ST0_REGNUM (tdep) <= regnum
374 && regnum < I387_FCTRL_REGNUM (tdep));
378 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
380 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
382 if (I387_ST0_REGNUM (tdep) < 0)
385 return (I387_FCTRL_REGNUM (tdep) <= regnum
386 && regnum < I387_XMM0_REGNUM (tdep));
389 /* BNDr (raw) register? */
392 i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum)
394 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
396 if (I387_BND0R_REGNUM (tdep) < 0)
399 regnum -= tdep->bnd0r_regnum;
400 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
403 /* BND control register? */
406 i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum)
408 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
410 if (I387_BNDCFGU_REGNUM (tdep) < 0)
413 regnum -= I387_BNDCFGU_REGNUM (tdep);
414 return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS;
417 /* Return the name of register REGNUM, or the empty string if it is
418 an anonymous register. */
421 i386_register_name (struct gdbarch *gdbarch, int regnum)
423 /* Hide the upper YMM registers. */
424 if (i386_ymmh_regnum_p (gdbarch, regnum))
427 /* Hide the upper YMM16-31 registers. */
428 if (i386_ymmh_avx512_regnum_p (gdbarch, regnum))
431 /* Hide the upper ZMM registers. */
432 if (i386_zmmh_regnum_p (gdbarch, regnum))
435 return tdesc_register_name (gdbarch, regnum);
438 /* Return the name of register REGNUM. */
441 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
443 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
444 if (i386_bnd_regnum_p (gdbarch, regnum))
445 return i386_bnd_names[regnum - tdep->bnd0_regnum];
446 if (i386_mmx_regnum_p (gdbarch, regnum))
447 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
448 else if (i386_ymm_regnum_p (gdbarch, regnum))
449 return i386_ymm_names[regnum - tdep->ymm0_regnum];
450 else if (i386_zmm_regnum_p (gdbarch, regnum))
451 return i386_zmm_names[regnum - tdep->zmm0_regnum];
452 else if (i386_byte_regnum_p (gdbarch, regnum))
453 return i386_byte_names[regnum - tdep->al_regnum];
454 else if (i386_word_regnum_p (gdbarch, regnum))
455 return i386_word_names[regnum - tdep->ax_regnum];
457 internal_error (__FILE__, __LINE__, _("invalid regnum"));
460 /* Convert a dbx register number REG to the appropriate register
461 number used by GDB. */
464 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
466 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
468 /* This implements what GCC calls the "default" register map
469 (dbx_register_map[]). */
471 if (reg >= 0 && reg <= 7)
473 /* General-purpose registers. The debug info calls %ebp
474 register 4, and %esp register 5. */
481 else if (reg >= 12 && reg <= 19)
483 /* Floating-point registers. */
484 return reg - 12 + I387_ST0_REGNUM (tdep);
486 else if (reg >= 21 && reg <= 28)
489 int ymm0_regnum = tdep->ymm0_regnum;
492 && i386_xmm_regnum_p (gdbarch, reg))
493 return reg - 21 + ymm0_regnum;
495 return reg - 21 + I387_XMM0_REGNUM (tdep);
497 else if (reg >= 29 && reg <= 36)
500 return reg - 29 + I387_MM0_REGNUM (tdep);
503 /* This will hopefully provoke a warning. */
504 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
507 /* Convert SVR4 register number REG to the appropriate register number
511 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
513 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
515 /* This implements the GCC register map that tries to be compatible
516 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
518 /* The SVR4 register numbering includes %eip and %eflags, and
519 numbers the floating point registers differently. */
520 if (reg >= 0 && reg <= 9)
522 /* General-purpose registers. */
525 else if (reg >= 11 && reg <= 18)
527 /* Floating-point registers. */
528 return reg - 11 + I387_ST0_REGNUM (tdep);
530 else if (reg >= 21 && reg <= 36)
532 /* The SSE and MMX registers have the same numbers as with dbx. */
533 return i386_dbx_reg_to_regnum (gdbarch, reg);
538 case 37: return I387_FCTRL_REGNUM (tdep);
539 case 38: return I387_FSTAT_REGNUM (tdep);
540 case 39: return I387_MXCSR_REGNUM (tdep);
541 case 40: return I386_ES_REGNUM;
542 case 41: return I386_CS_REGNUM;
543 case 42: return I386_SS_REGNUM;
544 case 43: return I386_DS_REGNUM;
545 case 44: return I386_FS_REGNUM;
546 case 45: return I386_GS_REGNUM;
549 /* This will hopefully provoke a warning. */
550 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
555 /* This is the variable that is set with "set disassembly-flavor", and
556 its legitimate values. */
557 static const char att_flavor[] = "att";
558 static const char intel_flavor[] = "intel";
559 static const char *const valid_flavors[] =
565 static const char *disassembly_flavor = att_flavor;
568 /* Use the program counter to determine the contents and size of a
569 breakpoint instruction. Return a pointer to a string of bytes that
570 encode a breakpoint instruction, store the length of the string in
571 *LEN and optionally adjust *PC to point to the correct memory
572 location for inserting the breakpoint.
574 On the i386 we have a single breakpoint that fits in a single byte
575 and can be inserted anywhere.
577 This function is 64-bit safe. */
579 static const gdb_byte *
580 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
582 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */
584 *len = sizeof (break_insn);
588 /* Displaced instruction handling. */
590 /* Skip the legacy instruction prefixes in INSN.
591 Not all prefixes are valid for any particular insn
592 but we needn't care, the insn will fault if it's invalid.
593 The result is a pointer to the first opcode byte,
594 or NULL if we run off the end of the buffer. */
597 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
599 gdb_byte *end = insn + max_len;
605 case DATA_PREFIX_OPCODE:
606 case ADDR_PREFIX_OPCODE:
607 case CS_PREFIX_OPCODE:
608 case DS_PREFIX_OPCODE:
609 case ES_PREFIX_OPCODE:
610 case FS_PREFIX_OPCODE:
611 case GS_PREFIX_OPCODE:
612 case SS_PREFIX_OPCODE:
613 case LOCK_PREFIX_OPCODE:
614 case REPE_PREFIX_OPCODE:
615 case REPNE_PREFIX_OPCODE:
627 i386_absolute_jmp_p (const gdb_byte *insn)
629 /* jmp far (absolute address in operand). */
635 /* jump near, absolute indirect (/4). */
636 if ((insn[1] & 0x38) == 0x20)
639 /* jump far, absolute indirect (/5). */
640 if ((insn[1] & 0x38) == 0x28)
647 /* Return non-zero if INSN is a jump, zero otherwise. */
650 i386_jmp_p (const gdb_byte *insn)
652 /* jump short, relative. */
656 /* jump near, relative. */
660 return i386_absolute_jmp_p (insn);
664 i386_absolute_call_p (const gdb_byte *insn)
666 /* call far, absolute. */
672 /* Call near, absolute indirect (/2). */
673 if ((insn[1] & 0x38) == 0x10)
676 /* Call far, absolute indirect (/3). */
677 if ((insn[1] & 0x38) == 0x18)
685 i386_ret_p (const gdb_byte *insn)
689 case 0xc2: /* ret near, pop N bytes. */
690 case 0xc3: /* ret near */
691 case 0xca: /* ret far, pop N bytes. */
692 case 0xcb: /* ret far */
693 case 0xcf: /* iret */
702 i386_call_p (const gdb_byte *insn)
704 if (i386_absolute_call_p (insn))
707 /* call near, relative. */
714 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
715 length in bytes. Otherwise, return zero. */
718 i386_syscall_p (const gdb_byte *insn, int *lengthp)
720 /* Is it 'int $0x80'? */
721 if ((insn[0] == 0xcd && insn[1] == 0x80)
722 /* Or is it 'sysenter'? */
723 || (insn[0] == 0x0f && insn[1] == 0x34)
724 /* Or is it 'syscall'? */
725 || (insn[0] == 0x0f && insn[1] == 0x05))
734 /* The gdbarch insn_is_call method. */
737 i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
739 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
741 read_code (addr, buf, I386_MAX_INSN_LEN);
742 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
744 return i386_call_p (insn);
747 /* The gdbarch insn_is_ret method. */
750 i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
752 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
754 read_code (addr, buf, I386_MAX_INSN_LEN);
755 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
757 return i386_ret_p (insn);
760 /* The gdbarch insn_is_jump method. */
763 i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
765 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
767 read_code (addr, buf, I386_MAX_INSN_LEN);
768 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
770 return i386_jmp_p (insn);
773 /* Some kernels may run one past a syscall insn, so we have to cope.
774 Otherwise this is just simple_displaced_step_copy_insn. */
776 struct displaced_step_closure *
777 i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
778 CORE_ADDR from, CORE_ADDR to,
779 struct regcache *regs)
781 size_t len = gdbarch_max_insn_length (gdbarch);
782 gdb_byte *buf = xmalloc (len);
784 read_memory (from, buf, len);
786 /* GDB may get control back after the insn after the syscall.
787 Presumably this is a kernel bug.
788 If this is a syscall, make sure there's a nop afterwards. */
793 insn = i386_skip_prefixes (buf, len);
794 if (insn != NULL && i386_syscall_p (insn, &syscall_length))
795 insn[syscall_length] = NOP_OPCODE;
798 write_memory (to, buf, len);
802 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
803 paddress (gdbarch, from), paddress (gdbarch, to));
804 displaced_step_dump_bytes (gdb_stdlog, buf, len);
807 return (struct displaced_step_closure *) buf;
810 /* Fix up the state of registers and memory after having single-stepped
811 a displaced instruction. */
814 i386_displaced_step_fixup (struct gdbarch *gdbarch,
815 struct displaced_step_closure *closure,
816 CORE_ADDR from, CORE_ADDR to,
817 struct regcache *regs)
819 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
821 /* The offset we applied to the instruction's address.
822 This could well be negative (when viewed as a signed 32-bit
823 value), but ULONGEST won't reflect that, so take care when
825 ULONGEST insn_offset = to - from;
827 /* Since we use simple_displaced_step_copy_insn, our closure is a
828 copy of the instruction. */
829 gdb_byte *insn = (gdb_byte *) closure;
830 /* The start of the insn, needed in case we see some prefixes. */
831 gdb_byte *insn_start = insn;
834 fprintf_unfiltered (gdb_stdlog,
835 "displaced: fixup (%s, %s), "
836 "insn = 0x%02x 0x%02x ...\n",
837 paddress (gdbarch, from), paddress (gdbarch, to),
840 /* The list of issues to contend with here is taken from
841 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
842 Yay for Free Software! */
844 /* Relocate the %eip, if necessary. */
846 /* The instruction recognizers we use assume any leading prefixes
847 have been skipped. */
849 /* This is the size of the buffer in closure. */
850 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
851 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
852 /* If there are too many prefixes, just ignore the insn.
853 It will fault when run. */
858 /* Except in the case of absolute or indirect jump or call
859 instructions, or a return instruction, the new eip is relative to
860 the displaced instruction; make it relative. Well, signal
861 handler returns don't need relocation either, but we use the
862 value of %eip to recognize those; see below. */
863 if (! i386_absolute_jmp_p (insn)
864 && ! i386_absolute_call_p (insn)
865 && ! i386_ret_p (insn))
870 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
872 /* A signal trampoline system call changes the %eip, resuming
873 execution of the main program after the signal handler has
874 returned. That makes them like 'return' instructions; we
875 shouldn't relocate %eip.
877 But most system calls don't, and we do need to relocate %eip.
879 Our heuristic for distinguishing these cases: if stepping
880 over the system call instruction left control directly after
881 the instruction, the we relocate --- control almost certainly
882 doesn't belong in the displaced copy. Otherwise, we assume
883 the instruction has put control where it belongs, and leave
884 it unrelocated. Goodness help us if there are PC-relative
886 if (i386_syscall_p (insn, &insn_len)
887 && orig_eip != to + (insn - insn_start) + insn_len
888 /* GDB can get control back after the insn after the syscall.
889 Presumably this is a kernel bug.
890 i386_displaced_step_copy_insn ensures its a nop,
891 we add one to the length for it. */
892 && orig_eip != to + (insn - insn_start) + insn_len + 1)
895 fprintf_unfiltered (gdb_stdlog,
896 "displaced: syscall changed %%eip; "
901 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
903 /* If we just stepped over a breakpoint insn, we don't backup
904 the pc on purpose; this is to match behaviour without
907 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
910 fprintf_unfiltered (gdb_stdlog,
912 "relocated %%eip from %s to %s\n",
913 paddress (gdbarch, orig_eip),
914 paddress (gdbarch, eip));
918 /* If the instruction was PUSHFL, then the TF bit will be set in the
919 pushed value, and should be cleared. We'll leave this for later,
920 since GDB already messes up the TF flag when stepping over a
923 /* If the instruction was a call, the return address now atop the
924 stack is the address following the copied instruction. We need
925 to make it the address following the original instruction. */
926 if (i386_call_p (insn))
930 const ULONGEST retaddr_len = 4;
932 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
933 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
934 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
935 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
938 fprintf_unfiltered (gdb_stdlog,
939 "displaced: relocated return addr at %s to %s\n",
940 paddress (gdbarch, esp),
941 paddress (gdbarch, retaddr));
946 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
948 target_write_memory (*to, buf, len);
953 i386_relocate_instruction (struct gdbarch *gdbarch,
954 CORE_ADDR *to, CORE_ADDR oldloc)
956 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
957 gdb_byte buf[I386_MAX_INSN_LEN];
958 int offset = 0, rel32, newrel;
960 gdb_byte *insn = buf;
962 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
964 insn_length = gdb_buffered_insn_length (gdbarch, insn,
965 I386_MAX_INSN_LEN, oldloc);
967 /* Get past the prefixes. */
968 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
970 /* Adjust calls with 32-bit relative addresses as push/jump, with
971 the address pushed being the location where the original call in
972 the user program would return to. */
975 gdb_byte push_buf[16];
976 unsigned int ret_addr;
978 /* Where "ret" in the original code will return to. */
979 ret_addr = oldloc + insn_length;
980 push_buf[0] = 0x68; /* pushq $... */
981 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
983 append_insns (to, 5, push_buf);
985 /* Convert the relative call to a relative jump. */
988 /* Adjust the destination offset. */
989 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
990 newrel = (oldloc - *to) + rel32;
991 store_signed_integer (insn + 1, 4, byte_order, newrel);
994 fprintf_unfiltered (gdb_stdlog,
995 "Adjusted insn rel32=%s at %s to"
997 hex_string (rel32), paddress (gdbarch, oldloc),
998 hex_string (newrel), paddress (gdbarch, *to));
1000 /* Write the adjusted jump into its displaced location. */
1001 append_insns (to, 5, insn);
1005 /* Adjust jumps with 32-bit relative addresses. Calls are already
1007 if (insn[0] == 0xe9)
1009 /* Adjust conditional jumps. */
1010 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1015 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1016 newrel = (oldloc - *to) + rel32;
1017 store_signed_integer (insn + offset, 4, byte_order, newrel);
1018 if (debug_displaced)
1019 fprintf_unfiltered (gdb_stdlog,
1020 "Adjusted insn rel32=%s at %s to"
1021 " rel32=%s at %s\n",
1022 hex_string (rel32), paddress (gdbarch, oldloc),
1023 hex_string (newrel), paddress (gdbarch, *to));
1026 /* Write the adjusted instructions into their displaced
1028 append_insns (to, insn_length, buf);
1032 #ifdef I386_REGNO_TO_SYMMETRY
1033 #error "The Sequent Symmetry is no longer supported."
1036 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1037 and %esp "belong" to the calling function. Therefore these
1038 registers should be saved if they're going to be modified. */
1040 /* The maximum number of saved registers. This should include all
1041 registers mentioned above, and %eip. */
1042 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1044 struct i386_frame_cache
1052 /* Saved registers. */
1053 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
1058 /* Stack space reserved for local variables. */
1062 /* Allocate and initialize a frame cache. */
1064 static struct i386_frame_cache *
1065 i386_alloc_frame_cache (void)
1067 struct i386_frame_cache *cache;
1070 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
1075 cache->sp_offset = -4;
1078 /* Saved registers. We initialize these to -1 since zero is a valid
1079 offset (that's where %ebp is supposed to be stored). */
1080 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1081 cache->saved_regs[i] = -1;
1082 cache->saved_sp = 0;
1083 cache->saved_sp_reg = -1;
1084 cache->pc_in_eax = 0;
1086 /* Frameless until proven otherwise. */
1092 /* If the instruction at PC is a jump, return the address of its
1093 target. Otherwise, return PC. */
1096 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
1098 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1103 if (target_read_code (pc, &op, 1))
1110 op = read_code_unsigned_integer (pc + 1, 1, byte_order);
1116 /* Relative jump: if data16 == 0, disp32, else disp16. */
1119 delta = read_memory_integer (pc + 2, 2, byte_order);
1121 /* Include the size of the jmp instruction (including the
1127 delta = read_memory_integer (pc + 1, 4, byte_order);
1129 /* Include the size of the jmp instruction. */
1134 /* Relative jump, disp8 (ignore data16). */
1135 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
1137 delta += data16 + 2;
1144 /* Check whether PC points at a prologue for a function returning a
1145 structure or union. If so, it updates CACHE and returns the
1146 address of the first instruction after the code sequence that
1147 removes the "hidden" argument from the stack or CURRENT_PC,
1148 whichever is smaller. Otherwise, return PC. */
1151 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
1152 struct i386_frame_cache *cache)
1154 /* Functions that return a structure or union start with:
1157 xchgl %eax, (%esp) 0x87 0x04 0x24
1158 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1160 (the System V compiler puts out the second `xchg' instruction,
1161 and the assembler doesn't try to optimize it, so the 'sib' form
1162 gets generated). This sequence is used to get the address of the
1163 return buffer for a function that returns a structure. */
1164 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
1165 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
1169 if (current_pc <= pc)
1172 if (target_read_code (pc, &op, 1))
1175 if (op != 0x58) /* popl %eax */
1178 if (target_read_code (pc + 1, buf, 4))
1181 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
1184 if (current_pc == pc)
1186 cache->sp_offset += 4;
1190 if (current_pc == pc + 1)
1192 cache->pc_in_eax = 1;
1196 if (buf[1] == proto1[1])
1203 i386_skip_probe (CORE_ADDR pc)
1205 /* A function may start with
1219 if (target_read_code (pc, &op, 1))
1222 if (op == 0x68 || op == 0x6a)
1226 /* Skip past the `pushl' instruction; it has either a one-byte or a
1227 four-byte operand, depending on the opcode. */
1233 /* Read the following 8 bytes, which should be `call _probe' (6
1234 bytes) followed by `addl $4,%esp' (2 bytes). */
1235 read_memory (pc + delta, buf, sizeof (buf));
1236 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
1237 pc += delta + sizeof (buf);
1243 /* GCC 4.1 and later, can put code in the prologue to realign the
1244 stack pointer. Check whether PC points to such code, and update
1245 CACHE accordingly. Return the first instruction after the code
1246 sequence or CURRENT_PC, whichever is smaller. If we don't
1247 recognize the code, return PC. */
1250 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1251 struct i386_frame_cache *cache)
1253 /* There are 2 code sequences to re-align stack before the frame
1256 1. Use a caller-saved saved register:
1262 2. Use a callee-saved saved register:
1269 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1271 0x83 0xe4 0xf0 andl $-16, %esp
1272 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1277 int offset, offset_and;
1278 static int regnums[8] = {
1279 I386_EAX_REGNUM, /* %eax */
1280 I386_ECX_REGNUM, /* %ecx */
1281 I386_EDX_REGNUM, /* %edx */
1282 I386_EBX_REGNUM, /* %ebx */
1283 I386_ESP_REGNUM, /* %esp */
1284 I386_EBP_REGNUM, /* %ebp */
1285 I386_ESI_REGNUM, /* %esi */
1286 I386_EDI_REGNUM /* %edi */
1289 if (target_read_code (pc, buf, sizeof buf))
1292 /* Check caller-saved saved register. The first instruction has
1293 to be "leal 4(%esp), %reg". */
1294 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1296 /* MOD must be binary 10 and R/M must be binary 100. */
1297 if ((buf[1] & 0xc7) != 0x44)
1300 /* REG has register number. */
1301 reg = (buf[1] >> 3) & 7;
1306 /* Check callee-saved saved register. The first instruction
1307 has to be "pushl %reg". */
1308 if ((buf[0] & 0xf8) != 0x50)
1314 /* The next instruction has to be "leal 8(%esp), %reg". */
1315 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1318 /* MOD must be binary 10 and R/M must be binary 100. */
1319 if ((buf[2] & 0xc7) != 0x44)
1322 /* REG has register number. Registers in pushl and leal have to
1324 if (reg != ((buf[2] >> 3) & 7))
1330 /* Rigister can't be %esp nor %ebp. */
1331 if (reg == 4 || reg == 5)
1334 /* The next instruction has to be "andl $-XXX, %esp". */
1335 if (buf[offset + 1] != 0xe4
1336 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1339 offset_and = offset;
1340 offset += buf[offset] == 0x81 ? 6 : 3;
1342 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1343 0xfc. REG must be binary 110 and MOD must be binary 01. */
1344 if (buf[offset] != 0xff
1345 || buf[offset + 2] != 0xfc
1346 || (buf[offset + 1] & 0xf8) != 0x70)
1349 /* R/M has register. Registers in leal and pushl have to be the
1351 if (reg != (buf[offset + 1] & 7))
1354 if (current_pc > pc + offset_and)
1355 cache->saved_sp_reg = regnums[reg];
1357 return min (pc + offset + 3, current_pc);
1360 /* Maximum instruction length we need to handle. */
1361 #define I386_MAX_MATCHED_INSN_LEN 6
1363 /* Instruction description. */
1367 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
1368 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
1371 /* Return whether instruction at PC matches PATTERN. */
1374 i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern)
1378 if (target_read_code (pc, &op, 1))
1381 if ((op & pattern.mask[0]) == pattern.insn[0])
1383 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1384 int insn_matched = 1;
1387 gdb_assert (pattern.len > 1);
1388 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN);
1390 if (target_read_code (pc + 1, buf, pattern.len - 1))
1393 for (i = 1; i < pattern.len; i++)
1395 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i])
1398 return insn_matched;
1403 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1404 the first instruction description that matches. Otherwise, return
1407 static struct i386_insn *
1408 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns)
1410 struct i386_insn *pattern;
1412 for (pattern = insn_patterns; pattern->len > 0; pattern++)
1414 if (i386_match_pattern (pc, *pattern))
1421 /* Return whether PC points inside a sequence of instructions that
1422 matches INSN_PATTERNS. */
1425 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns)
1427 CORE_ADDR current_pc;
1429 struct i386_insn *insn;
1431 insn = i386_match_insn (pc, insn_patterns);
1436 ix = insn - insn_patterns;
1437 for (i = ix - 1; i >= 0; i--)
1439 current_pc -= insn_patterns[i].len;
1441 if (!i386_match_pattern (current_pc, insn_patterns[i]))
1445 current_pc = pc + insn->len;
1446 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++)
1448 if (!i386_match_pattern (current_pc, *insn))
1451 current_pc += insn->len;
1457 /* Some special instructions that might be migrated by GCC into the
1458 part of the prologue that sets up the new stack frame. Because the
1459 stack frame hasn't been setup yet, no registers have been saved
1460 yet, and only the scratch registers %eax, %ecx and %edx can be
1463 struct i386_insn i386_frame_setup_skip_insns[] =
1465 /* Check for `movb imm8, r' and `movl imm32, r'.
1467 ??? Should we handle 16-bit operand-sizes here? */
1469 /* `movb imm8, %al' and `movb imm8, %ah' */
1470 /* `movb imm8, %cl' and `movb imm8, %ch' */
1471 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1472 /* `movb imm8, %dl' and `movb imm8, %dh' */
1473 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1474 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1475 { 5, { 0xb8 }, { 0xfe } },
1476 /* `movl imm32, %edx' */
1477 { 5, { 0xba }, { 0xff } },
1479 /* Check for `mov imm32, r32'. Note that there is an alternative
1480 encoding for `mov m32, %eax'.
1482 ??? Should we handle SIB adressing here?
1483 ??? Should we handle 16-bit operand-sizes here? */
1485 /* `movl m32, %eax' */
1486 { 5, { 0xa1 }, { 0xff } },
1487 /* `movl m32, %eax' and `mov; m32, %ecx' */
1488 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1489 /* `movl m32, %edx' */
1490 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1492 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1493 Because of the symmetry, there are actually two ways to encode
1494 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1495 opcode bytes 0x31 and 0x33 for `xorl'. */
1497 /* `subl %eax, %eax' */
1498 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1499 /* `subl %ecx, %ecx' */
1500 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1501 /* `subl %edx, %edx' */
1502 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1503 /* `xorl %eax, %eax' */
1504 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1505 /* `xorl %ecx, %ecx' */
1506 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1507 /* `xorl %edx, %edx' */
1508 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1513 /* Check whether PC points to a no-op instruction. */
1515 i386_skip_noop (CORE_ADDR pc)
1520 if (target_read_code (pc, &op, 1))
1526 /* Ignore `nop' instruction. */
1530 if (target_read_code (pc, &op, 1))
1534 /* Ignore no-op instruction `mov %edi, %edi'.
1535 Microsoft system dlls often start with
1536 a `mov %edi,%edi' instruction.
1537 The 5 bytes before the function start are
1538 filled with `nop' instructions.
1539 This pattern can be used for hot-patching:
1540 The `mov %edi, %edi' instruction can be replaced by a
1541 near jump to the location of the 5 `nop' instructions
1542 which can be replaced by a 32-bit jump to anywhere
1543 in the 32-bit address space. */
1545 else if (op == 0x8b)
1547 if (target_read_code (pc + 1, &op, 1))
1553 if (target_read_code (pc, &op, 1))
1563 /* Check whether PC points at a code that sets up a new stack frame.
1564 If so, it updates CACHE and returns the address of the first
1565 instruction after the sequence that sets up the frame or LIMIT,
1566 whichever is smaller. If we don't recognize the code, return PC. */
1569 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1570 CORE_ADDR pc, CORE_ADDR limit,
1571 struct i386_frame_cache *cache)
1573 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1574 struct i386_insn *insn;
1581 if (target_read_code (pc, &op, 1))
1584 if (op == 0x55) /* pushl %ebp */
1586 /* Take into account that we've executed the `pushl %ebp' that
1587 starts this instruction sequence. */
1588 cache->saved_regs[I386_EBP_REGNUM] = 0;
1589 cache->sp_offset += 4;
1592 /* If that's all, return now. */
1596 /* Check for some special instructions that might be migrated by
1597 GCC into the prologue and skip them. At this point in the
1598 prologue, code should only touch the scratch registers %eax,
1599 %ecx and %edx, so while the number of posibilities is sheer,
1602 Make sure we only skip these instructions if we later see the
1603 `movl %esp, %ebp' that actually sets up the frame. */
1604 while (pc + skip < limit)
1606 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1613 /* If that's all, return now. */
1614 if (limit <= pc + skip)
1617 if (target_read_code (pc + skip, &op, 1))
1620 /* The i386 prologue looks like
1626 and a different prologue can be generated for atom.
1630 lea -0x10(%esp),%esp
1632 We handle both of them here. */
1636 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1638 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1644 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1649 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1650 if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order)
1659 /* OK, we actually have a frame. We just don't know how large
1660 it is yet. Set its size to zero. We'll adjust it if
1661 necessary. We also now commit to skipping the special
1662 instructions mentioned before. */
1665 /* If that's all, return now. */
1669 /* Check for stack adjustment
1675 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1676 reg, so we don't have to worry about a data16 prefix. */
1677 if (target_read_code (pc, &op, 1))
1681 /* `subl' with 8-bit immediate. */
1682 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1683 /* Some instruction starting with 0x83 other than `subl'. */
1686 /* `subl' with signed 8-bit immediate (though it wouldn't
1687 make sense to be negative). */
1688 cache->locals = read_code_integer (pc + 2, 1, byte_order);
1691 else if (op == 0x81)
1693 /* Maybe it is `subl' with a 32-bit immediate. */
1694 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1695 /* Some instruction starting with 0x81 other than `subl'. */
1698 /* It is `subl' with a 32-bit immediate. */
1699 cache->locals = read_code_integer (pc + 2, 4, byte_order);
1702 else if (op == 0x8d)
1704 /* The ModR/M byte is 0x64. */
1705 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64)
1707 /* 'lea' with 8-bit displacement. */
1708 cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order);
1713 /* Some instruction other than `subl' nor 'lea'. */
1717 else if (op == 0xc8) /* enter */
1719 cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order);
1726 /* Check whether PC points at code that saves registers on the stack.
1727 If so, it updates CACHE and returns the address of the first
1728 instruction after the register saves or CURRENT_PC, whichever is
1729 smaller. Otherwise, return PC. */
1732 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1733 struct i386_frame_cache *cache)
1735 CORE_ADDR offset = 0;
1739 if (cache->locals > 0)
1740 offset -= cache->locals;
1741 for (i = 0; i < 8 && pc < current_pc; i++)
1743 if (target_read_code (pc, &op, 1))
1745 if (op < 0x50 || op > 0x57)
1749 cache->saved_regs[op - 0x50] = offset;
1750 cache->sp_offset += 4;
1757 /* Do a full analysis of the prologue at PC and update CACHE
1758 accordingly. Bail out early if CURRENT_PC is reached. Return the
1759 address where the analysis stopped.
1761 We handle these cases:
1763 The startup sequence can be at the start of the function, or the
1764 function can start with a branch to startup code at the end.
1766 %ebp can be set up with either the 'enter' instruction, or "pushl
1767 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1768 once used in the System V compiler).
1770 Local space is allocated just below the saved %ebp by either the
1771 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1772 16-bit unsigned argument for space to allocate, and the 'addl'
1773 instruction could have either a signed byte, or 32-bit immediate.
1775 Next, the registers used by this function are pushed. With the
1776 System V compiler they will always be in the order: %edi, %esi,
1777 %ebx (and sometimes a harmless bug causes it to also save but not
1778 restore %eax); however, the code below is willing to see the pushes
1779 in any order, and will handle up to 8 of them.
1781 If the setup sequence is at the end of the function, then the next
1782 instruction will be a branch back to the start. */
1785 i386_analyze_prologue (struct gdbarch *gdbarch,
1786 CORE_ADDR pc, CORE_ADDR current_pc,
1787 struct i386_frame_cache *cache)
1789 pc = i386_skip_noop (pc);
1790 pc = i386_follow_jump (gdbarch, pc);
1791 pc = i386_analyze_struct_return (pc, current_pc, cache);
1792 pc = i386_skip_probe (pc);
1793 pc = i386_analyze_stack_align (pc, current_pc, cache);
1794 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1795 return i386_analyze_register_saves (pc, current_pc, cache);
1798 /* Return PC of first real instruction. */
1801 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1803 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1805 static gdb_byte pic_pat[6] =
1807 0xe8, 0, 0, 0, 0, /* call 0x0 */
1808 0x5b, /* popl %ebx */
1810 struct i386_frame_cache cache;
1814 CORE_ADDR func_addr;
1816 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
1818 CORE_ADDR post_prologue_pc
1819 = skip_prologue_using_sal (gdbarch, func_addr);
1820 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
1822 /* Clang always emits a line note before the prologue and another
1823 one after. We trust clang to emit usable line notes. */
1824 if (post_prologue_pc
1826 && COMPUNIT_PRODUCER (cust) != NULL
1827 && strncmp (COMPUNIT_PRODUCER (cust), "clang ",
1828 sizeof ("clang ") - 1) == 0))
1829 return max (start_pc, post_prologue_pc);
1833 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1834 if (cache.locals < 0)
1837 /* Found valid frame setup. */
1839 /* The native cc on SVR4 in -K PIC mode inserts the following code
1840 to get the address of the global offset table (GOT) into register
1845 movl %ebx,x(%ebp) (optional)
1848 This code is with the rest of the prologue (at the end of the
1849 function), so we have to skip it to get to the first real
1850 instruction at the start of the function. */
1852 for (i = 0; i < 6; i++)
1854 if (target_read_code (pc + i, &op, 1))
1857 if (pic_pat[i] != op)
1864 if (target_read_code (pc + delta, &op, 1))
1867 if (op == 0x89) /* movl %ebx, x(%ebp) */
1869 op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order);
1871 if (op == 0x5d) /* One byte offset from %ebp. */
1873 else if (op == 0x9d) /* Four byte offset from %ebp. */
1875 else /* Unexpected instruction. */
1878 if (target_read_code (pc + delta, &op, 1))
1883 if (delta > 0 && op == 0x81
1884 && read_code_unsigned_integer (pc + delta + 1, 1, byte_order)
1891 /* If the function starts with a branch (to startup code at the end)
1892 the last instruction should bring us back to the first
1893 instruction of the real code. */
1894 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1895 pc = i386_follow_jump (gdbarch, pc);
1900 /* Check that the code pointed to by PC corresponds to a call to
1901 __main, skip it if so. Return PC otherwise. */
1904 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1906 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1909 if (target_read_code (pc, &op, 1))
1915 if (target_read_code (pc + 1, buf, sizeof buf) == 0)
1917 /* Make sure address is computed correctly as a 32bit
1918 integer even if CORE_ADDR is 64 bit wide. */
1919 struct bound_minimal_symbol s;
1920 CORE_ADDR call_dest;
1922 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1923 call_dest = call_dest & 0xffffffffU;
1924 s = lookup_minimal_symbol_by_pc (call_dest);
1925 if (s.minsym != NULL
1926 && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL
1927 && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0)
1935 /* This function is 64-bit safe. */
1938 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1942 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1943 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1947 /* Normal frames. */
1950 i386_frame_cache_1 (struct frame_info *this_frame,
1951 struct i386_frame_cache *cache)
1953 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1954 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1958 cache->pc = get_frame_func (this_frame);
1960 /* In principle, for normal frames, %ebp holds the frame pointer,
1961 which holds the base address for the current stack frame.
1962 However, for functions that don't need it, the frame pointer is
1963 optional. For these "frameless" functions the frame pointer is
1964 actually the frame pointer of the calling frame. Signal
1965 trampolines are just a special case of a "frameless" function.
1966 They (usually) share their frame pointer with the frame that was
1967 in progress when the signal occurred. */
1969 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1970 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1971 if (cache->base == 0)
1977 /* For normal frames, %eip is stored at 4(%ebp). */
1978 cache->saved_regs[I386_EIP_REGNUM] = 4;
1981 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
1984 if (cache->locals < 0)
1986 /* We didn't find a valid frame, which means that CACHE->base
1987 currently holds the frame pointer for our calling frame. If
1988 we're at the start of a function, or somewhere half-way its
1989 prologue, the function's frame probably hasn't been fully
1990 setup yet. Try to reconstruct the base address for the stack
1991 frame by looking at the stack pointer. For truly "frameless"
1992 functions this might work too. */
1994 if (cache->saved_sp_reg != -1)
1996 /* Saved stack pointer has been saved. */
1997 get_frame_register (this_frame, cache->saved_sp_reg, buf);
1998 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2000 /* We're halfway aligning the stack. */
2001 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
2002 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
2004 /* This will be added back below. */
2005 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
2007 else if (cache->pc != 0
2008 || target_read_code (get_frame_pc (this_frame), buf, 1))
2010 /* We're in a known function, but did not find a frame
2011 setup. Assume that the function does not use %ebp.
2012 Alternatively, we may have jumped to an invalid
2013 address; in that case there is definitely no new
2015 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2016 cache->base = extract_unsigned_integer (buf, 4, byte_order)
2020 /* We're in an unknown function. We could not find the start
2021 of the function to analyze the prologue; our best option is
2022 to assume a typical frame layout with the caller's %ebp
2024 cache->saved_regs[I386_EBP_REGNUM] = 0;
2027 if (cache->saved_sp_reg != -1)
2029 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2030 register may be unavailable). */
2031 if (cache->saved_sp == 0
2032 && deprecated_frame_register_read (this_frame,
2033 cache->saved_sp_reg, buf))
2034 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2036 /* Now that we have the base address for the stack frame we can
2037 calculate the value of %esp in the calling frame. */
2038 else if (cache->saved_sp == 0)
2039 cache->saved_sp = cache->base + 8;
2041 /* Adjust all the saved registers such that they contain addresses
2042 instead of offsets. */
2043 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
2044 if (cache->saved_regs[i] != -1)
2045 cache->saved_regs[i] += cache->base;
2050 static struct i386_frame_cache *
2051 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
2053 volatile struct gdb_exception ex;
2054 struct i386_frame_cache *cache;
2059 cache = i386_alloc_frame_cache ();
2060 *this_cache = cache;
2062 TRY_CATCH (ex, RETURN_MASK_ERROR)
2064 i386_frame_cache_1 (this_frame, cache);
2066 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2067 throw_exception (ex);
2073 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
2074 struct frame_id *this_id)
2076 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2079 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2080 else if (cache->base == 0)
2082 /* This marks the outermost frame. */
2086 /* See the end of i386_push_dummy_call. */
2087 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2091 static enum unwind_stop_reason
2092 i386_frame_unwind_stop_reason (struct frame_info *this_frame,
2095 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2098 return UNWIND_UNAVAILABLE;
2100 /* This marks the outermost frame. */
2101 if (cache->base == 0)
2102 return UNWIND_OUTERMOST;
2104 return UNWIND_NO_REASON;
2107 static struct value *
2108 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2111 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2113 gdb_assert (regnum >= 0);
2115 /* The System V ABI says that:
2117 "The flags register contains the system flags, such as the
2118 direction flag and the carry flag. The direction flag must be
2119 set to the forward (that is, zero) direction before entry and
2120 upon exit from a function. Other user flags have no specified
2121 role in the standard calling sequence and are not preserved."
2123 To guarantee the "upon exit" part of that statement we fake a
2124 saved flags register that has its direction flag cleared.
2126 Note that GCC doesn't seem to rely on the fact that the direction
2127 flag is cleared after a function return; it always explicitly
2128 clears the flag before operations where it matters.
2130 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2131 right thing to do. The way we fake the flags register here makes
2132 it impossible to change it. */
2134 if (regnum == I386_EFLAGS_REGNUM)
2138 val = get_frame_register_unsigned (this_frame, regnum);
2140 return frame_unwind_got_constant (this_frame, regnum, val);
2143 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
2144 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
2146 if (regnum == I386_ESP_REGNUM
2147 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1))
2149 /* If the SP has been saved, but we don't know where, then this
2150 means that SAVED_SP_REG register was found unavailable back
2151 when we built the cache. */
2152 if (cache->saved_sp == 0)
2153 return frame_unwind_got_register (this_frame, regnum,
2154 cache->saved_sp_reg);
2156 return frame_unwind_got_constant (this_frame, regnum,
2160 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2161 return frame_unwind_got_memory (this_frame, regnum,
2162 cache->saved_regs[regnum]);
2164 return frame_unwind_got_register (this_frame, regnum, regnum);
2167 static const struct frame_unwind i386_frame_unwind =
2170 i386_frame_unwind_stop_reason,
2172 i386_frame_prev_register,
2174 default_frame_sniffer
2177 /* Normal frames, but in a function epilogue. */
2179 /* The epilogue is defined here as the 'ret' instruction, which will
2180 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2181 the function's stack frame. */
2184 i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2187 struct compunit_symtab *cust;
2189 cust = find_pc_compunit_symtab (pc);
2190 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
2193 if (target_read_memory (pc, &insn, 1))
2194 return 0; /* Can't read memory at pc. */
2196 if (insn != 0xc3) /* 'ret' instruction. */
2203 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
2204 struct frame_info *this_frame,
2205 void **this_prologue_cache)
2207 if (frame_relative_level (this_frame) == 0)
2208 return i386_in_function_epilogue_p (get_frame_arch (this_frame),
2209 get_frame_pc (this_frame));
2214 static struct i386_frame_cache *
2215 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2217 volatile struct gdb_exception ex;
2218 struct i386_frame_cache *cache;
2224 cache = i386_alloc_frame_cache ();
2225 *this_cache = cache;
2227 TRY_CATCH (ex, RETURN_MASK_ERROR)
2229 cache->pc = get_frame_func (this_frame);
2231 /* At this point the stack looks as if we just entered the
2232 function, with the return address at the top of the
2234 sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM);
2235 cache->base = sp + cache->sp_offset;
2236 cache->saved_sp = cache->base + 8;
2237 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
2241 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2242 throw_exception (ex);
2247 static enum unwind_stop_reason
2248 i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2251 struct i386_frame_cache *cache =
2252 i386_epilogue_frame_cache (this_frame, this_cache);
2255 return UNWIND_UNAVAILABLE;
2257 return UNWIND_NO_REASON;
2261 i386_epilogue_frame_this_id (struct frame_info *this_frame,
2263 struct frame_id *this_id)
2265 struct i386_frame_cache *cache =
2266 i386_epilogue_frame_cache (this_frame, this_cache);
2269 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2271 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2274 static struct value *
2275 i386_epilogue_frame_prev_register (struct frame_info *this_frame,
2276 void **this_cache, int regnum)
2278 /* Make sure we've initialized the cache. */
2279 i386_epilogue_frame_cache (this_frame, this_cache);
2281 return i386_frame_prev_register (this_frame, this_cache, regnum);
2284 static const struct frame_unwind i386_epilogue_frame_unwind =
2287 i386_epilogue_frame_unwind_stop_reason,
2288 i386_epilogue_frame_this_id,
2289 i386_epilogue_frame_prev_register,
2291 i386_epilogue_frame_sniffer
2295 /* Stack-based trampolines. */
2297 /* These trampolines are used on cross x86 targets, when taking the
2298 address of a nested function. When executing these trampolines,
2299 no stack frame is set up, so we are in a similar situation as in
2300 epilogues and i386_epilogue_frame_this_id can be re-used. */
2302 /* Static chain passed in register. */
2304 struct i386_insn i386_tramp_chain_in_reg_insns[] =
2306 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2307 { 5, { 0xb8 }, { 0xfe } },
2310 { 5, { 0xe9 }, { 0xff } },
2315 /* Static chain passed on stack (when regparm=3). */
2317 struct i386_insn i386_tramp_chain_on_stack_insns[] =
2320 { 5, { 0x68 }, { 0xff } },
2323 { 5, { 0xe9 }, { 0xff } },
2328 /* Return whether PC points inside a stack trampoline. */
2331 i386_in_stack_tramp_p (CORE_ADDR pc)
2336 /* A stack trampoline is detected if no name is associated
2337 to the current pc and if it points inside a trampoline
2340 find_pc_partial_function (pc, &name, NULL, NULL);
2344 if (target_read_memory (pc, &insn, 1))
2347 if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns)
2348 && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns))
2355 i386_stack_tramp_frame_sniffer (const struct frame_unwind *self,
2356 struct frame_info *this_frame,
2359 if (frame_relative_level (this_frame) == 0)
2360 return i386_in_stack_tramp_p (get_frame_pc (this_frame));
2365 static const struct frame_unwind i386_stack_tramp_frame_unwind =
2368 i386_epilogue_frame_unwind_stop_reason,
2369 i386_epilogue_frame_this_id,
2370 i386_epilogue_frame_prev_register,
2372 i386_stack_tramp_frame_sniffer
2375 /* Generate a bytecode expression to get the value of the saved PC. */
2378 i386_gen_return_address (struct gdbarch *gdbarch,
2379 struct agent_expr *ax, struct axs_value *value,
2382 /* The following sequence assumes the traditional use of the base
2384 ax_reg (ax, I386_EBP_REGNUM);
2386 ax_simple (ax, aop_add);
2387 value->type = register_type (gdbarch, I386_EIP_REGNUM);
2388 value->kind = axs_lvalue_memory;
2392 /* Signal trampolines. */
2394 static struct i386_frame_cache *
2395 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2397 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2398 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2399 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2400 volatile struct gdb_exception ex;
2401 struct i386_frame_cache *cache;
2408 cache = i386_alloc_frame_cache ();
2410 TRY_CATCH (ex, RETURN_MASK_ERROR)
2412 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2413 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
2415 addr = tdep->sigcontext_addr (this_frame);
2416 if (tdep->sc_reg_offset)
2420 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
2422 for (i = 0; i < tdep->sc_num_regs; i++)
2423 if (tdep->sc_reg_offset[i] != -1)
2424 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2428 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
2429 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
2434 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2435 throw_exception (ex);
2437 *this_cache = cache;
2441 static enum unwind_stop_reason
2442 i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2445 struct i386_frame_cache *cache =
2446 i386_sigtramp_frame_cache (this_frame, this_cache);
2449 return UNWIND_UNAVAILABLE;
2451 return UNWIND_NO_REASON;
2455 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
2456 struct frame_id *this_id)
2458 struct i386_frame_cache *cache =
2459 i386_sigtramp_frame_cache (this_frame, this_cache);
2462 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2465 /* See the end of i386_push_dummy_call. */
2466 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
2470 static struct value *
2471 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
2472 void **this_cache, int regnum)
2474 /* Make sure we've initialized the cache. */
2475 i386_sigtramp_frame_cache (this_frame, this_cache);
2477 return i386_frame_prev_register (this_frame, this_cache, regnum);
2481 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
2482 struct frame_info *this_frame,
2483 void **this_prologue_cache)
2485 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2487 /* We shouldn't even bother if we don't have a sigcontext_addr
2489 if (tdep->sigcontext_addr == NULL)
2492 if (tdep->sigtramp_p != NULL)
2494 if (tdep->sigtramp_p (this_frame))
2498 if (tdep->sigtramp_start != 0)
2500 CORE_ADDR pc = get_frame_pc (this_frame);
2502 gdb_assert (tdep->sigtramp_end != 0);
2503 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2510 static const struct frame_unwind i386_sigtramp_frame_unwind =
2513 i386_sigtramp_frame_unwind_stop_reason,
2514 i386_sigtramp_frame_this_id,
2515 i386_sigtramp_frame_prev_register,
2517 i386_sigtramp_frame_sniffer
2522 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
2524 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2529 static const struct frame_base i386_frame_base =
2532 i386_frame_base_address,
2533 i386_frame_base_address,
2534 i386_frame_base_address
2537 static struct frame_id
2538 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2542 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
2544 /* See the end of i386_push_dummy_call. */
2545 return frame_id_build (fp + 8, get_frame_pc (this_frame));
2548 /* _Decimal128 function return values need 16-byte alignment on the
2552 i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2554 return sp & -(CORE_ADDR)16;
2558 /* Figure out where the longjmp will land. Slurp the args out of the
2559 stack. We expect the first arg to be a pointer to the jmp_buf
2560 structure from which we extract the address that we will land at.
2561 This address is copied into PC. This routine returns non-zero on
2565 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2568 CORE_ADDR sp, jb_addr;
2569 struct gdbarch *gdbarch = get_frame_arch (frame);
2570 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2571 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2573 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2574 longjmp will land. */
2575 if (jb_pc_offset == -1)
2578 get_frame_register (frame, I386_ESP_REGNUM, buf);
2579 sp = extract_unsigned_integer (buf, 4, byte_order);
2580 if (target_read_memory (sp + 4, buf, 4))
2583 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
2584 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
2587 *pc = extract_unsigned_integer (buf, 4, byte_order);
2592 /* Check whether TYPE must be 16-byte-aligned when passed as a
2593 function argument. 16-byte vectors, _Decimal128 and structures or
2594 unions containing such types must be 16-byte-aligned; other
2595 arguments are 4-byte-aligned. */
2598 i386_16_byte_align_p (struct type *type)
2600 type = check_typedef (type);
2601 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
2602 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
2603 && TYPE_LENGTH (type) == 16)
2605 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2606 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
2607 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2608 || TYPE_CODE (type) == TYPE_CODE_UNION)
2611 for (i = 0; i < TYPE_NFIELDS (type); i++)
2613 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
2620 /* Implementation for set_gdbarch_push_dummy_code. */
2623 i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
2624 struct value **args, int nargs, struct type *value_type,
2625 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
2626 struct regcache *regcache)
2628 /* Use 0xcc breakpoint - 1 byte. */
2632 /* Keep the stack aligned. */
2637 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2638 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2639 struct value **args, CORE_ADDR sp, int struct_return,
2640 CORE_ADDR struct_addr)
2642 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2648 /* Determine the total space required for arguments and struct
2649 return address in a first pass (allowing for 16-byte-aligned
2650 arguments), then push arguments in a second pass. */
2652 for (write_pass = 0; write_pass < 2; write_pass++)
2654 int args_space_used = 0;
2660 /* Push value address. */
2661 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2662 write_memory (sp, buf, 4);
2663 args_space_used += 4;
2669 for (i = 0; i < nargs; i++)
2671 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2675 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2676 args_space_used = align_up (args_space_used, 16);
2678 write_memory (sp + args_space_used,
2679 value_contents_all (args[i]), len);
2680 /* The System V ABI says that:
2682 "An argument's size is increased, if necessary, to make it a
2683 multiple of [32-bit] words. This may require tail padding,
2684 depending on the size of the argument."
2686 This makes sure the stack stays word-aligned. */
2687 args_space_used += align_up (len, 4);
2691 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2692 args_space = align_up (args_space, 16);
2693 args_space += align_up (len, 4);
2701 /* The original System V ABI only requires word alignment,
2702 but modern incarnations need 16-byte alignment in order
2703 to support SSE. Since wasting a few bytes here isn't
2704 harmful we unconditionally enforce 16-byte alignment. */
2709 /* Store return address. */
2711 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2712 write_memory (sp, buf, 4);
2714 /* Finally, update the stack pointer... */
2715 store_unsigned_integer (buf, 4, byte_order, sp);
2716 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
2718 /* ...and fake a frame pointer. */
2719 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
2721 /* MarkK wrote: This "+ 8" is all over the place:
2722 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2723 i386_dummy_id). It's there, since all frame unwinders for
2724 a given target have to agree (within a certain margin) on the
2725 definition of the stack address of a frame. Otherwise frame id
2726 comparison might not work correctly. Since DWARF2/GCC uses the
2727 stack address *before* the function call as a frame's CFA. On
2728 the i386, when %ebp is used as a frame pointer, the offset
2729 between the contents %ebp and the CFA as defined by GCC. */
2733 /* These registers are used for returning integers (and on some
2734 targets also for returning `struct' and `union' values when their
2735 size and alignment match an integer type). */
2736 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2737 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2739 /* Read, for architecture GDBARCH, a function return value of TYPE
2740 from REGCACHE, and copy that into VALBUF. */
2743 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2744 struct regcache *regcache, gdb_byte *valbuf)
2746 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2747 int len = TYPE_LENGTH (type);
2748 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2750 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2752 if (tdep->st0_regnum < 0)
2754 warning (_("Cannot find floating-point return value."));
2755 memset (valbuf, 0, len);
2759 /* Floating-point return values can be found in %st(0). Convert
2760 its contents to the desired type. This is probably not
2761 exactly how it would happen on the target itself, but it is
2762 the best we can do. */
2763 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2764 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
2768 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2769 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2771 if (len <= low_size)
2773 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2774 memcpy (valbuf, buf, len);
2776 else if (len <= (low_size + high_size))
2778 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2779 memcpy (valbuf, buf, low_size);
2780 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2781 memcpy (valbuf + low_size, buf, len - low_size);
2784 internal_error (__FILE__, __LINE__,
2785 _("Cannot extract return value of %d bytes long."),
2790 /* Write, for architecture GDBARCH, a function return value of TYPE
2791 from VALBUF into REGCACHE. */
2794 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2795 struct regcache *regcache, const gdb_byte *valbuf)
2797 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2798 int len = TYPE_LENGTH (type);
2800 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2803 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2805 if (tdep->st0_regnum < 0)
2807 warning (_("Cannot set floating-point return value."));
2811 /* Returning floating-point values is a bit tricky. Apart from
2812 storing the return value in %st(0), we have to simulate the
2813 state of the FPU at function return point. */
2815 /* Convert the value found in VALBUF to the extended
2816 floating-point format used by the FPU. This is probably
2817 not exactly how it would happen on the target itself, but
2818 it is the best we can do. */
2819 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
2820 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2822 /* Set the top of the floating-point register stack to 7. The
2823 actual value doesn't really matter, but 7 is what a normal
2824 function return would end up with if the program started out
2825 with a freshly initialized FPU. */
2826 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2828 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2830 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2831 the floating-point register stack to 7, the appropriate value
2832 for the tag word is 0x3fff. */
2833 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2837 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2838 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2840 if (len <= low_size)
2841 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2842 else if (len <= (low_size + high_size))
2844 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2845 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
2846 len - low_size, valbuf + low_size);
2849 internal_error (__FILE__, __LINE__,
2850 _("Cannot store return value of %d bytes long."), len);
2855 /* This is the variable that is set with "set struct-convention", and
2856 its legitimate values. */
2857 static const char default_struct_convention[] = "default";
2858 static const char pcc_struct_convention[] = "pcc";
2859 static const char reg_struct_convention[] = "reg";
2860 static const char *const valid_conventions[] =
2862 default_struct_convention,
2863 pcc_struct_convention,
2864 reg_struct_convention,
2867 static const char *struct_convention = default_struct_convention;
2869 /* Return non-zero if TYPE, which is assumed to be a structure,
2870 a union type, or an array type, should be returned in registers
2871 for architecture GDBARCH. */
2874 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2876 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2877 enum type_code code = TYPE_CODE (type);
2878 int len = TYPE_LENGTH (type);
2880 gdb_assert (code == TYPE_CODE_STRUCT
2881 || code == TYPE_CODE_UNION
2882 || code == TYPE_CODE_ARRAY);
2884 if (struct_convention == pcc_struct_convention
2885 || (struct_convention == default_struct_convention
2886 && tdep->struct_return == pcc_struct_return))
2889 /* Structures consisting of a single `float', `double' or 'long
2890 double' member are returned in %st(0). */
2891 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2893 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2894 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2895 return (len == 4 || len == 8 || len == 12);
2898 return (len == 1 || len == 2 || len == 4 || len == 8);
2901 /* Determine, for architecture GDBARCH, how a return value of TYPE
2902 should be returned. If it is supposed to be returned in registers,
2903 and READBUF is non-zero, read the appropriate value from REGCACHE,
2904 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2905 from WRITEBUF into REGCACHE. */
2907 static enum return_value_convention
2908 i386_return_value (struct gdbarch *gdbarch, struct value *function,
2909 struct type *type, struct regcache *regcache,
2910 gdb_byte *readbuf, const gdb_byte *writebuf)
2912 enum type_code code = TYPE_CODE (type);
2914 if (((code == TYPE_CODE_STRUCT
2915 || code == TYPE_CODE_UNION
2916 || code == TYPE_CODE_ARRAY)
2917 && !i386_reg_struct_return_p (gdbarch, type))
2918 /* Complex double and long double uses the struct return covention. */
2919 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16)
2920 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24)
2921 /* 128-bit decimal float uses the struct return convention. */
2922 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2924 /* The System V ABI says that:
2926 "A function that returns a structure or union also sets %eax
2927 to the value of the original address of the caller's area
2928 before it returns. Thus when the caller receives control
2929 again, the address of the returned object resides in register
2930 %eax and can be used to access the object."
2932 So the ABI guarantees that we can always find the return
2933 value just after the function has returned. */
2935 /* Note that the ABI doesn't mention functions returning arrays,
2936 which is something possible in certain languages such as Ada.
2937 In this case, the value is returned as if it was wrapped in
2938 a record, so the convention applied to records also applies
2945 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2946 read_memory (addr, readbuf, TYPE_LENGTH (type));
2949 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2952 /* This special case is for structures consisting of a single
2953 `float', `double' or 'long double' member. These structures are
2954 returned in %st(0). For these structures, we call ourselves
2955 recursively, changing TYPE into the type of the first member of
2956 the structure. Since that should work for all structures that
2957 have only one member, we don't bother to check the member's type
2959 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2961 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2962 return i386_return_value (gdbarch, function, type, regcache,
2967 i386_extract_return_value (gdbarch, type, regcache, readbuf);
2969 i386_store_return_value (gdbarch, type, regcache, writebuf);
2971 return RETURN_VALUE_REGISTER_CONVENTION;
2976 i387_ext_type (struct gdbarch *gdbarch)
2978 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2980 if (!tdep->i387_ext_type)
2982 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
2983 gdb_assert (tdep->i387_ext_type != NULL);
2986 return tdep->i387_ext_type;
2989 /* Construct type for pseudo BND registers. We can't use
2990 tdesc_find_type since a complement of one value has to be used
2991 to describe the upper bound. */
2993 static struct type *
2994 i386_bnd_type (struct gdbarch *gdbarch)
2996 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2999 if (!tdep->i386_bnd_type)
3001 struct type *t, *bound_t;
3002 const struct builtin_type *bt = builtin_type (gdbarch);
3004 /* The type we're building is described bellow: */
3009 void *ubound; /* One complement of raw ubound field. */
3013 t = arch_composite_type (gdbarch,
3014 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT);
3016 append_composite_type_field (t, "lbound", bt->builtin_data_ptr);
3017 append_composite_type_field (t, "ubound", bt->builtin_data_ptr);
3019 TYPE_NAME (t) = "builtin_type_bound128";
3020 tdep->i386_bnd_type = t;
3023 return tdep->i386_bnd_type;
3026 /* Construct vector type for pseudo ZMM registers. We can't use
3027 tdesc_find_type since ZMM isn't described in target description. */
3029 static struct type *
3030 i386_zmm_type (struct gdbarch *gdbarch)
3032 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3034 if (!tdep->i386_zmm_type)
3036 const struct builtin_type *bt = builtin_type (gdbarch);
3038 /* The type we're building is this: */
3040 union __gdb_builtin_type_vec512i
3042 int128_t uint128[4];
3043 int64_t v4_int64[8];
3044 int32_t v8_int32[16];
3045 int16_t v16_int16[32];
3046 int8_t v32_int8[64];
3047 double v4_double[8];
3054 t = arch_composite_type (gdbarch,
3055 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION);
3056 append_composite_type_field (t, "v16_float",
3057 init_vector_type (bt->builtin_float, 16));
3058 append_composite_type_field (t, "v8_double",
3059 init_vector_type (bt->builtin_double, 8));
3060 append_composite_type_field (t, "v64_int8",
3061 init_vector_type (bt->builtin_int8, 64));
3062 append_composite_type_field (t, "v32_int16",
3063 init_vector_type (bt->builtin_int16, 32));
3064 append_composite_type_field (t, "v16_int32",
3065 init_vector_type (bt->builtin_int32, 16));
3066 append_composite_type_field (t, "v8_int64",
3067 init_vector_type (bt->builtin_int64, 8));
3068 append_composite_type_field (t, "v4_int128",
3069 init_vector_type (bt->builtin_int128, 4));
3071 TYPE_VECTOR (t) = 1;
3072 TYPE_NAME (t) = "builtin_type_vec512i";
3073 tdep->i386_zmm_type = t;
3076 return tdep->i386_zmm_type;
3079 /* Construct vector type for pseudo YMM registers. We can't use
3080 tdesc_find_type since YMM isn't described in target description. */
3082 static struct type *
3083 i386_ymm_type (struct gdbarch *gdbarch)
3085 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3087 if (!tdep->i386_ymm_type)
3089 const struct builtin_type *bt = builtin_type (gdbarch);
3091 /* The type we're building is this: */
3093 union __gdb_builtin_type_vec256i
3095 int128_t uint128[2];
3096 int64_t v2_int64[4];
3097 int32_t v4_int32[8];
3098 int16_t v8_int16[16];
3099 int8_t v16_int8[32];
3100 double v2_double[4];
3107 t = arch_composite_type (gdbarch,
3108 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
3109 append_composite_type_field (t, "v8_float",
3110 init_vector_type (bt->builtin_float, 8));
3111 append_composite_type_field (t, "v4_double",
3112 init_vector_type (bt->builtin_double, 4));
3113 append_composite_type_field (t, "v32_int8",
3114 init_vector_type (bt->builtin_int8, 32));
3115 append_composite_type_field (t, "v16_int16",
3116 init_vector_type (bt->builtin_int16, 16));
3117 append_composite_type_field (t, "v8_int32",
3118 init_vector_type (bt->builtin_int32, 8));
3119 append_composite_type_field (t, "v4_int64",
3120 init_vector_type (bt->builtin_int64, 4));
3121 append_composite_type_field (t, "v2_int128",
3122 init_vector_type (bt->builtin_int128, 2));
3124 TYPE_VECTOR (t) = 1;
3125 TYPE_NAME (t) = "builtin_type_vec256i";
3126 tdep->i386_ymm_type = t;
3129 return tdep->i386_ymm_type;
3132 /* Construct vector type for MMX registers. */
3133 static struct type *
3134 i386_mmx_type (struct gdbarch *gdbarch)
3136 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3138 if (!tdep->i386_mmx_type)
3140 const struct builtin_type *bt = builtin_type (gdbarch);
3142 /* The type we're building is this: */
3144 union __gdb_builtin_type_vec64i
3147 int32_t v2_int32[2];
3148 int16_t v4_int16[4];
3155 t = arch_composite_type (gdbarch,
3156 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
3158 append_composite_type_field (t, "uint64", bt->builtin_int64);
3159 append_composite_type_field (t, "v2_int32",
3160 init_vector_type (bt->builtin_int32, 2));
3161 append_composite_type_field (t, "v4_int16",
3162 init_vector_type (bt->builtin_int16, 4));
3163 append_composite_type_field (t, "v8_int8",
3164 init_vector_type (bt->builtin_int8, 8));
3166 TYPE_VECTOR (t) = 1;
3167 TYPE_NAME (t) = "builtin_type_vec64i";
3168 tdep->i386_mmx_type = t;
3171 return tdep->i386_mmx_type;
3174 /* Return the GDB type object for the "standard" data type of data in
3178 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3180 if (i386_bnd_regnum_p (gdbarch, regnum))
3181 return i386_bnd_type (gdbarch);
3182 if (i386_mmx_regnum_p (gdbarch, regnum))
3183 return i386_mmx_type (gdbarch);
3184 else if (i386_ymm_regnum_p (gdbarch, regnum))
3185 return i386_ymm_type (gdbarch);
3186 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3187 return i386_ymm_type (gdbarch);
3188 else if (i386_zmm_regnum_p (gdbarch, regnum))
3189 return i386_zmm_type (gdbarch);
3192 const struct builtin_type *bt = builtin_type (gdbarch);
3193 if (i386_byte_regnum_p (gdbarch, regnum))
3194 return bt->builtin_int8;
3195 else if (i386_word_regnum_p (gdbarch, regnum))
3196 return bt->builtin_int16;
3197 else if (i386_dword_regnum_p (gdbarch, regnum))
3198 return bt->builtin_int32;
3199 else if (i386_k_regnum_p (gdbarch, regnum))
3200 return bt->builtin_int64;
3203 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3206 /* Map a cooked register onto a raw register or memory. For the i386,
3207 the MMX registers need to be mapped onto floating point registers. */
3210 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
3212 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
3217 mmxreg = regnum - tdep->mm0_regnum;
3218 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
3219 tos = (fstat >> 11) & 0x7;
3220 fpreg = (mmxreg + tos) % 8;
3222 return (I387_ST0_REGNUM (tdep) + fpreg);
3225 /* A helper function for us by i386_pseudo_register_read_value and
3226 amd64_pseudo_register_read_value. It does all the work but reads
3227 the data into an already-allocated value. */
3230 i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
3231 struct regcache *regcache,
3233 struct value *result_value)
3235 gdb_byte raw_buf[MAX_REGISTER_SIZE];
3236 enum register_status status;
3237 gdb_byte *buf = value_contents_raw (result_value);
3239 if (i386_mmx_regnum_p (gdbarch, regnum))
3241 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3243 /* Extract (always little endian). */
3244 status = regcache_raw_read (regcache, fpnum, raw_buf);
3245 if (status != REG_VALID)
3246 mark_value_bytes_unavailable (result_value, 0,
3247 TYPE_LENGTH (value_type (result_value)));
3249 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
3253 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3254 if (i386_bnd_regnum_p (gdbarch, regnum))
3256 regnum -= tdep->bnd0_regnum;
3258 /* Extract (always little endian). Read lower 128bits. */
3259 status = regcache_raw_read (regcache,
3260 I387_BND0R_REGNUM (tdep) + regnum,
3262 if (status != REG_VALID)
3263 mark_value_bytes_unavailable (result_value, 0, 16);
3266 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3267 LONGEST upper, lower;
3268 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3270 lower = extract_unsigned_integer (raw_buf, 8, byte_order);
3271 upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order);
3274 memcpy (buf, &lower, size);
3275 memcpy (buf + size, &upper, size);
3278 else if (i386_k_regnum_p (gdbarch, regnum))
3280 regnum -= tdep->k0_regnum;
3282 /* Extract (always little endian). */
3283 status = regcache_raw_read (regcache,
3284 tdep->k0_regnum + regnum,
3286 if (status != REG_VALID)
3287 mark_value_bytes_unavailable (result_value, 0, 8);
3289 memcpy (buf, raw_buf, 8);
3291 else if (i386_zmm_regnum_p (gdbarch, regnum))
3293 regnum -= tdep->zmm0_regnum;
3295 if (regnum < num_lower_zmm_regs)
3297 /* Extract (always little endian). Read lower 128bits. */
3298 status = regcache_raw_read (regcache,
3299 I387_XMM0_REGNUM (tdep) + regnum,
3301 if (status != REG_VALID)
3302 mark_value_bytes_unavailable (result_value, 0, 16);
3304 memcpy (buf, raw_buf, 16);
3306 /* Extract (always little endian). Read upper 128bits. */
3307 status = regcache_raw_read (regcache,
3308 tdep->ymm0h_regnum + regnum,
3310 if (status != REG_VALID)
3311 mark_value_bytes_unavailable (result_value, 16, 16);
3313 memcpy (buf + 16, raw_buf, 16);
3317 /* Extract (always little endian). Read lower 128bits. */
3318 status = regcache_raw_read (regcache,
3319 I387_XMM16_REGNUM (tdep) + regnum
3320 - num_lower_zmm_regs,
3322 if (status != REG_VALID)
3323 mark_value_bytes_unavailable (result_value, 0, 16);
3325 memcpy (buf, raw_buf, 16);
3327 /* Extract (always little endian). Read upper 128bits. */
3328 status = regcache_raw_read (regcache,
3329 I387_YMM16H_REGNUM (tdep) + regnum
3330 - num_lower_zmm_regs,
3332 if (status != REG_VALID)
3333 mark_value_bytes_unavailable (result_value, 16, 16);
3335 memcpy (buf + 16, raw_buf, 16);
3338 /* Read upper 256bits. */
3339 status = regcache_raw_read (regcache,
3340 tdep->zmm0h_regnum + regnum,
3342 if (status != REG_VALID)
3343 mark_value_bytes_unavailable (result_value, 32, 32);
3345 memcpy (buf + 32, raw_buf, 32);
3347 else if (i386_ymm_regnum_p (gdbarch, regnum))
3349 regnum -= tdep->ymm0_regnum;
3351 /* Extract (always little endian). Read lower 128bits. */
3352 status = regcache_raw_read (regcache,
3353 I387_XMM0_REGNUM (tdep) + regnum,
3355 if (status != REG_VALID)
3356 mark_value_bytes_unavailable (result_value, 0, 16);
3358 memcpy (buf, raw_buf, 16);
3359 /* Read upper 128bits. */
3360 status = regcache_raw_read (regcache,
3361 tdep->ymm0h_regnum + regnum,
3363 if (status != REG_VALID)
3364 mark_value_bytes_unavailable (result_value, 16, 32);
3366 memcpy (buf + 16, raw_buf, 16);
3368 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3370 regnum -= tdep->ymm16_regnum;
3371 /* Extract (always little endian). Read lower 128bits. */
3372 status = regcache_raw_read (regcache,
3373 I387_XMM16_REGNUM (tdep) + regnum,
3375 if (status != REG_VALID)
3376 mark_value_bytes_unavailable (result_value, 0, 16);
3378 memcpy (buf, raw_buf, 16);
3379 /* Read upper 128bits. */
3380 status = regcache_raw_read (regcache,
3381 tdep->ymm16h_regnum + regnum,
3383 if (status != REG_VALID)
3384 mark_value_bytes_unavailable (result_value, 16, 16);
3386 memcpy (buf + 16, raw_buf, 16);
3388 else if (i386_word_regnum_p (gdbarch, regnum))
3390 int gpnum = regnum - tdep->ax_regnum;
3392 /* Extract (always little endian). */
3393 status = regcache_raw_read (regcache, gpnum, raw_buf);
3394 if (status != REG_VALID)
3395 mark_value_bytes_unavailable (result_value, 0,
3396 TYPE_LENGTH (value_type (result_value)));
3398 memcpy (buf, raw_buf, 2);
3400 else if (i386_byte_regnum_p (gdbarch, regnum))
3402 /* Check byte pseudo registers last since this function will
3403 be called from amd64_pseudo_register_read, which handles
3404 byte pseudo registers differently. */
3405 int gpnum = regnum - tdep->al_regnum;
3407 /* Extract (always little endian). We read both lower and
3409 status = regcache_raw_read (regcache, gpnum % 4, raw_buf);
3410 if (status != REG_VALID)
3411 mark_value_bytes_unavailable (result_value, 0,
3412 TYPE_LENGTH (value_type (result_value)));
3413 else if (gpnum >= 4)
3414 memcpy (buf, raw_buf + 1, 1);
3416 memcpy (buf, raw_buf, 1);
3419 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3423 static struct value *
3424 i386_pseudo_register_read_value (struct gdbarch *gdbarch,
3425 struct regcache *regcache,
3428 struct value *result;
3430 result = allocate_value (register_type (gdbarch, regnum));
3431 VALUE_LVAL (result) = lval_register;
3432 VALUE_REGNUM (result) = regnum;
3434 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result);
3440 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3441 int regnum, const gdb_byte *buf)
3443 gdb_byte raw_buf[MAX_REGISTER_SIZE];
3445 if (i386_mmx_regnum_p (gdbarch, regnum))
3447 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3450 regcache_raw_read (regcache, fpnum, raw_buf);
3451 /* ... Modify ... (always little endian). */
3452 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
3454 regcache_raw_write (regcache, fpnum, raw_buf);
3458 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3460 if (i386_bnd_regnum_p (gdbarch, regnum))
3462 ULONGEST upper, lower;
3463 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3464 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3466 /* New values from input value. */
3467 regnum -= tdep->bnd0_regnum;
3468 lower = extract_unsigned_integer (buf, size, byte_order);
3469 upper = extract_unsigned_integer (buf + size, size, byte_order);
3471 /* Fetching register buffer. */
3472 regcache_raw_read (regcache,
3473 I387_BND0R_REGNUM (tdep) + regnum,
3478 /* Set register bits. */
3479 memcpy (raw_buf, &lower, 8);
3480 memcpy (raw_buf + 8, &upper, 8);
3483 regcache_raw_write (regcache,
3484 I387_BND0R_REGNUM (tdep) + regnum,
3487 else if (i386_k_regnum_p (gdbarch, regnum))
3489 regnum -= tdep->k0_regnum;
3491 regcache_raw_write (regcache,
3492 tdep->k0_regnum + regnum,
3495 else if (i386_zmm_regnum_p (gdbarch, regnum))
3497 regnum -= tdep->zmm0_regnum;
3499 if (regnum < num_lower_zmm_regs)
3501 /* Write lower 128bits. */
3502 regcache_raw_write (regcache,
3503 I387_XMM0_REGNUM (tdep) + regnum,
3505 /* Write upper 128bits. */
3506 regcache_raw_write (regcache,
3507 I387_YMM0_REGNUM (tdep) + regnum,
3512 /* Write lower 128bits. */
3513 regcache_raw_write (regcache,
3514 I387_XMM16_REGNUM (tdep) + regnum
3515 - num_lower_zmm_regs,
3517 /* Write upper 128bits. */
3518 regcache_raw_write (regcache,
3519 I387_YMM16H_REGNUM (tdep) + regnum
3520 - num_lower_zmm_regs,
3523 /* Write upper 256bits. */
3524 regcache_raw_write (regcache,
3525 tdep->zmm0h_regnum + regnum,
3528 else if (i386_ymm_regnum_p (gdbarch, regnum))
3530 regnum -= tdep->ymm0_regnum;
3532 /* ... Write lower 128bits. */
3533 regcache_raw_write (regcache,
3534 I387_XMM0_REGNUM (tdep) + regnum,
3536 /* ... Write upper 128bits. */
3537 regcache_raw_write (regcache,
3538 tdep->ymm0h_regnum + regnum,
3541 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3543 regnum -= tdep->ymm16_regnum;
3545 /* ... Write lower 128bits. */
3546 regcache_raw_write (regcache,
3547 I387_XMM16_REGNUM (tdep) + regnum,
3549 /* ... Write upper 128bits. */
3550 regcache_raw_write (regcache,
3551 tdep->ymm16h_regnum + regnum,
3554 else if (i386_word_regnum_p (gdbarch, regnum))
3556 int gpnum = regnum - tdep->ax_regnum;
3559 regcache_raw_read (regcache, gpnum, raw_buf);
3560 /* ... Modify ... (always little endian). */
3561 memcpy (raw_buf, buf, 2);
3563 regcache_raw_write (regcache, gpnum, raw_buf);
3565 else if (i386_byte_regnum_p (gdbarch, regnum))
3567 /* Check byte pseudo registers last since this function will
3568 be called from amd64_pseudo_register_read, which handles
3569 byte pseudo registers differently. */
3570 int gpnum = regnum - tdep->al_regnum;
3572 /* Read ... We read both lower and upper registers. */
3573 regcache_raw_read (regcache, gpnum % 4, raw_buf);
3574 /* ... Modify ... (always little endian). */
3576 memcpy (raw_buf + 1, buf, 1);
3578 memcpy (raw_buf, buf, 1);
3580 regcache_raw_write (regcache, gpnum % 4, raw_buf);
3583 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3588 /* Return the register number of the register allocated by GCC after
3589 REGNUM, or -1 if there is no such register. */
3592 i386_next_regnum (int regnum)
3594 /* GCC allocates the registers in the order:
3596 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3598 Since storing a variable in %esp doesn't make any sense we return
3599 -1 for %ebp and for %esp itself. */
3600 static int next_regnum[] =
3602 I386_EDX_REGNUM, /* Slot for %eax. */
3603 I386_EBX_REGNUM, /* Slot for %ecx. */
3604 I386_ECX_REGNUM, /* Slot for %edx. */
3605 I386_ESI_REGNUM, /* Slot for %ebx. */
3606 -1, -1, /* Slots for %esp and %ebp. */
3607 I386_EDI_REGNUM, /* Slot for %esi. */
3608 I386_EBP_REGNUM /* Slot for %edi. */
3611 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
3612 return next_regnum[regnum];
3617 /* Return nonzero if a value of type TYPE stored in register REGNUM
3618 needs any special handling. */
3621 i386_convert_register_p (struct gdbarch *gdbarch,
3622 int regnum, struct type *type)
3624 int len = TYPE_LENGTH (type);
3626 /* Values may be spread across multiple registers. Most debugging
3627 formats aren't expressive enough to specify the locations, so
3628 some heuristics is involved. Right now we only handle types that
3629 have a length that is a multiple of the word size, since GCC
3630 doesn't seem to put any other types into registers. */
3631 if (len > 4 && len % 4 == 0)
3633 int last_regnum = regnum;
3637 last_regnum = i386_next_regnum (last_regnum);
3641 if (last_regnum != -1)
3645 return i387_convert_register_p (gdbarch, regnum, type);
3648 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3649 return its contents in TO. */
3652 i386_register_to_value (struct frame_info *frame, int regnum,
3653 struct type *type, gdb_byte *to,
3654 int *optimizedp, int *unavailablep)
3656 struct gdbarch *gdbarch = get_frame_arch (frame);
3657 int len = TYPE_LENGTH (type);
3659 if (i386_fp_regnum_p (gdbarch, regnum))
3660 return i387_register_to_value (frame, regnum, type, to,
3661 optimizedp, unavailablep);
3663 /* Read a value spread across multiple registers. */
3665 gdb_assert (len > 4 && len % 4 == 0);
3669 gdb_assert (regnum != -1);
3670 gdb_assert (register_size (gdbarch, regnum) == 4);
3672 if (!get_frame_register_bytes (frame, regnum, 0,
3673 register_size (gdbarch, regnum),
3674 to, optimizedp, unavailablep))
3677 regnum = i386_next_regnum (regnum);
3682 *optimizedp = *unavailablep = 0;
3686 /* Write the contents FROM of a value of type TYPE into register
3687 REGNUM in frame FRAME. */
3690 i386_value_to_register (struct frame_info *frame, int regnum,
3691 struct type *type, const gdb_byte *from)
3693 int len = TYPE_LENGTH (type);
3695 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
3697 i387_value_to_register (frame, regnum, type, from);
3701 /* Write a value spread across multiple registers. */
3703 gdb_assert (len > 4 && len % 4 == 0);
3707 gdb_assert (regnum != -1);
3708 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
3710 put_frame_register (frame, regnum, from);
3711 regnum = i386_next_regnum (regnum);
3717 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3718 in the general-purpose register set REGSET to register cache
3719 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3722 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
3723 int regnum, const void *gregs, size_t len)
3725 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3726 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3727 const gdb_byte *regs = gregs;
3730 gdb_assert (len == tdep->sizeof_gregset);
3732 for (i = 0; i < tdep->gregset_num_regs; i++)
3734 if ((regnum == i || regnum == -1)
3735 && tdep->gregset_reg_offset[i] != -1)
3736 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
3740 /* Collect register REGNUM from the register cache REGCACHE and store
3741 it in the buffer specified by GREGS and LEN as described by the
3742 general-purpose register set REGSET. If REGNUM is -1, do this for
3743 all registers in REGSET. */
3746 i386_collect_gregset (const struct regset *regset,
3747 const struct regcache *regcache,
3748 int regnum, void *gregs, size_t len)
3750 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3751 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3752 gdb_byte *regs = gregs;
3755 gdb_assert (len == tdep->sizeof_gregset);
3757 for (i = 0; i < tdep->gregset_num_regs; i++)
3759 if ((regnum == i || regnum == -1)
3760 && tdep->gregset_reg_offset[i] != -1)
3761 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
3765 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3766 in the floating-point register set REGSET to register cache
3767 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3770 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
3771 int regnum, const void *fpregs, size_t len)
3773 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3774 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3776 if (len == I387_SIZEOF_FXSAVE)
3778 i387_supply_fxsave (regcache, regnum, fpregs);
3782 gdb_assert (len == tdep->sizeof_fpregset);
3783 i387_supply_fsave (regcache, regnum, fpregs);
3786 /* Collect register REGNUM from the register cache REGCACHE and store
3787 it in the buffer specified by FPREGS and LEN as described by the
3788 floating-point register set REGSET. If REGNUM is -1, do this for
3789 all registers in REGSET. */
3792 i386_collect_fpregset (const struct regset *regset,
3793 const struct regcache *regcache,
3794 int regnum, void *fpregs, size_t len)
3796 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3797 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3799 if (len == I387_SIZEOF_FXSAVE)
3801 i387_collect_fxsave (regcache, regnum, fpregs);
3805 gdb_assert (len == tdep->sizeof_fpregset);
3806 i387_collect_fsave (regcache, regnum, fpregs);
3809 /* Register set definitions. */
3811 const struct regset i386_gregset =
3813 NULL, i386_supply_gregset, i386_collect_gregset
3816 const struct regset i386_fpregset =
3818 NULL, i386_supply_fpregset, i386_collect_fpregset
3821 /* Default iterator over core file register note sections. */
3824 i386_iterate_over_regset_sections (struct gdbarch *gdbarch,
3825 iterate_over_regset_sections_cb *cb,
3827 const struct regcache *regcache)
3829 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3831 cb (".reg", tdep->sizeof_gregset, &i386_gregset, NULL, cb_data);
3832 if (tdep->sizeof_fpregset)
3833 cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
3837 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3840 i386_pe_skip_trampoline_code (struct frame_info *frame,
3841 CORE_ADDR pc, char *name)
3843 struct gdbarch *gdbarch = get_frame_arch (frame);
3844 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3847 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
3849 unsigned long indirect =
3850 read_memory_unsigned_integer (pc + 2, 4, byte_order);
3851 struct minimal_symbol *indsym =
3852 indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0;
3853 const char *symname = indsym ? MSYMBOL_LINKAGE_NAME (indsym) : 0;
3857 if (strncmp (symname, "__imp_", 6) == 0
3858 || strncmp (symname, "_imp_", 5) == 0)
3860 read_memory_unsigned_integer (indirect, 4, byte_order);
3863 return 0; /* Not a trampoline. */
3867 /* Return whether the THIS_FRAME corresponds to a sigtramp
3871 i386_sigtramp_p (struct frame_info *this_frame)
3873 CORE_ADDR pc = get_frame_pc (this_frame);
3876 find_pc_partial_function (pc, &name, NULL, NULL);
3877 return (name && strcmp ("_sigtramp", name) == 0);
3881 /* We have two flavours of disassembly. The machinery on this page
3882 deals with switching between those. */
3885 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
3887 gdb_assert (disassembly_flavor == att_flavor
3888 || disassembly_flavor == intel_flavor);
3890 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3891 constified, cast to prevent a compiler warning. */
3892 info->disassembler_options = (char *) disassembly_flavor;
3894 return print_insn_i386 (pc, info);
3898 /* There are a few i386 architecture variants that differ only
3899 slightly from the generic i386 target. For now, we don't give them
3900 their own source file, but include them here. As a consequence,
3901 they'll always be included. */
3903 /* System V Release 4 (SVR4). */
3905 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3909 i386_svr4_sigtramp_p (struct frame_info *this_frame)
3911 CORE_ADDR pc = get_frame_pc (this_frame);
3914 /* The origin of these symbols is currently unknown. */
3915 find_pc_partial_function (pc, &name, NULL, NULL);
3916 return (name && (strcmp ("_sigreturn", name) == 0
3917 || strcmp ("sigvechandler", name) == 0));
3920 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3921 address of the associated sigcontext (ucontext) structure. */
3924 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
3926 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3927 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3931 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
3932 sp = extract_unsigned_integer (buf, 4, byte_order);
3934 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
3939 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
3943 i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s)
3945 return (*s == '$' /* Literal number. */
3946 || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */
3947 || (*s == '(' && s[1] == '%') /* Register indirection. */
3948 || (*s == '%' && isalpha (s[1]))); /* Register access. */
3951 /* Helper function for i386_stap_parse_special_token.
3953 This function parses operands of the form `-8+3+1(%rbp)', which
3954 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
3956 Return 1 if the operand was parsed successfully, zero
3960 i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch,
3961 struct stap_parse_info *p)
3963 const char *s = p->arg;
3965 if (isdigit (*s) || *s == '-' || *s == '+')
3969 long displacements[3];
3985 if (!isdigit ((unsigned char) *s))
3988 displacements[0] = strtol (s, &endp, 10);
3991 if (*s != '+' && *s != '-')
3993 /* We are not dealing with a triplet. */
4006 if (!isdigit ((unsigned char) *s))
4009 displacements[1] = strtol (s, &endp, 10);
4012 if (*s != '+' && *s != '-')
4014 /* We are not dealing with a triplet. */
4027 if (!isdigit ((unsigned char) *s))
4030 displacements[2] = strtol (s, &endp, 10);
4033 if (*s != '(' || s[1] != '%')
4039 while (isalnum (*s))
4045 len = s - start - 1;
4046 regname = alloca (len + 1);
4048 strncpy (regname, start, len);
4049 regname[len] = '\0';
4051 if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1)
4052 error (_("Invalid register name `%s' on expression `%s'."),
4053 regname, p->saved_arg);
4055 for (i = 0; i < 3; i++)
4057 write_exp_elt_opcode (&p->pstate, OP_LONG);
4059 (&p->pstate, builtin_type (gdbarch)->builtin_long);
4060 write_exp_elt_longcst (&p->pstate, displacements[i]);
4061 write_exp_elt_opcode (&p->pstate, OP_LONG);
4063 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4066 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4069 write_exp_string (&p->pstate, str);
4070 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4072 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4073 write_exp_elt_type (&p->pstate,
4074 builtin_type (gdbarch)->builtin_data_ptr);
4075 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4077 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4078 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4079 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4081 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4082 write_exp_elt_type (&p->pstate,
4083 lookup_pointer_type (p->arg_type));
4084 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4086 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4096 /* Helper function for i386_stap_parse_special_token.
4098 This function parses operands of the form `register base +
4099 (register index * size) + offset', as represented in
4100 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4102 Return 1 if the operand was parsed successfully, zero
4106 i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch,
4107 struct stap_parse_info *p)
4109 const char *s = p->arg;
4111 if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+')
4113 int offset_minus = 0;
4122 struct stoken base_token, index_token;
4132 if (offset_minus && !isdigit (*s))
4139 offset = strtol (s, &endp, 10);
4143 if (*s != '(' || s[1] != '%')
4149 while (isalnum (*s))
4152 if (*s != ',' || s[1] != '%')
4155 len_base = s - start;
4156 base = alloca (len_base + 1);
4157 strncpy (base, start, len_base);
4158 base[len_base] = '\0';
4160 if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1)
4161 error (_("Invalid register name `%s' on expression `%s'."),
4162 base, p->saved_arg);
4167 while (isalnum (*s))
4170 len_index = s - start;
4171 index = alloca (len_index + 1);
4172 strncpy (index, start, len_index);
4173 index[len_index] = '\0';
4175 if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1)
4176 error (_("Invalid register name `%s' on expression `%s'."),
4177 index, p->saved_arg);
4179 if (*s != ',' && *s != ')')
4195 size = strtol (s, &endp, 10);
4206 write_exp_elt_opcode (&p->pstate, OP_LONG);
4207 write_exp_elt_type (&p->pstate,
4208 builtin_type (gdbarch)->builtin_long);
4209 write_exp_elt_longcst (&p->pstate, offset);
4210 write_exp_elt_opcode (&p->pstate, OP_LONG);
4212 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4215 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4216 base_token.ptr = base;
4217 base_token.length = len_base;
4218 write_exp_string (&p->pstate, base_token);
4219 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4222 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4224 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4225 index_token.ptr = index;
4226 index_token.length = len_index;
4227 write_exp_string (&p->pstate, index_token);
4228 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4232 write_exp_elt_opcode (&p->pstate, OP_LONG);
4233 write_exp_elt_type (&p->pstate,
4234 builtin_type (gdbarch)->builtin_long);
4235 write_exp_elt_longcst (&p->pstate, size);
4236 write_exp_elt_opcode (&p->pstate, OP_LONG);
4238 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4239 write_exp_elt_opcode (&p->pstate, BINOP_MUL);
4242 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4244 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4245 write_exp_elt_type (&p->pstate,
4246 lookup_pointer_type (p->arg_type));
4247 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4249 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4259 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4263 i386_stap_parse_special_token (struct gdbarch *gdbarch,
4264 struct stap_parse_info *p)
4266 /* In order to parse special tokens, we use a state-machine that go
4267 through every known token and try to get a match. */
4271 THREE_ARG_DISPLACEMENT,
4275 current_state = TRIPLET;
4277 /* The special tokens to be parsed here are:
4279 - `register base + (register index * size) + offset', as represented
4280 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4282 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4283 `*(-8 + 3 - 1 + (void *) $eax)'. */
4285 while (current_state != DONE)
4287 switch (current_state)
4290 if (i386_stap_parse_special_token_triplet (gdbarch, p))
4294 case THREE_ARG_DISPLACEMENT:
4295 if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p))
4300 /* Advancing to the next state. */
4312 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4314 static const char *const stap_integer_prefixes[] = { "$", NULL };
4315 static const char *const stap_register_prefixes[] = { "%", NULL };
4316 static const char *const stap_register_indirection_prefixes[] = { "(",
4318 static const char *const stap_register_indirection_suffixes[] = { ")",
4321 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4322 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4324 /* Registering SystemTap handlers. */
4325 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
4326 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
4327 set_gdbarch_stap_register_indirection_prefixes (gdbarch,
4328 stap_register_indirection_prefixes);
4329 set_gdbarch_stap_register_indirection_suffixes (gdbarch,
4330 stap_register_indirection_suffixes);
4331 set_gdbarch_stap_is_single_operand (gdbarch,
4332 i386_stap_is_single_operand);
4333 set_gdbarch_stap_parse_special_token (gdbarch,
4334 i386_stap_parse_special_token);
4337 /* System V Release 4 (SVR4). */
4340 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4342 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4344 /* System V Release 4 uses ELF. */
4345 i386_elf_init_abi (info, gdbarch);
4347 /* System V Release 4 has shared libraries. */
4348 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
4350 tdep->sigtramp_p = i386_svr4_sigtramp_p;
4351 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
4352 tdep->sc_pc_offset = 36 + 14 * 4;
4353 tdep->sc_sp_offset = 36 + 17 * 4;
4355 tdep->jb_pc_offset = 20;
4361 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4363 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4365 /* DJGPP doesn't have any special frames for signal handlers. */
4366 tdep->sigtramp_p = NULL;
4368 tdep->jb_pc_offset = 36;
4370 /* DJGPP does not support the SSE registers. */
4371 if (! tdesc_has_registers (info.target_desc))
4372 tdep->tdesc = tdesc_i386_mmx;
4374 /* Native compiler is GCC, which uses the SVR4 register numbering
4375 even in COFF and STABS. See the comment in i386_gdbarch_init,
4376 before the calls to set_gdbarch_stab_reg_to_regnum and
4377 set_gdbarch_sdb_reg_to_regnum. */
4378 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4379 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4381 set_gdbarch_has_dos_based_file_system (gdbarch, 1);
4385 /* i386 register groups. In addition to the normal groups, add "mmx"
4388 static struct reggroup *i386_sse_reggroup;
4389 static struct reggroup *i386_mmx_reggroup;
4392 i386_init_reggroups (void)
4394 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
4395 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
4399 i386_add_reggroups (struct gdbarch *gdbarch)
4401 reggroup_add (gdbarch, i386_sse_reggroup);
4402 reggroup_add (gdbarch, i386_mmx_reggroup);
4403 reggroup_add (gdbarch, general_reggroup);
4404 reggroup_add (gdbarch, float_reggroup);
4405 reggroup_add (gdbarch, all_reggroup);
4406 reggroup_add (gdbarch, save_reggroup);
4407 reggroup_add (gdbarch, restore_reggroup);
4408 reggroup_add (gdbarch, vector_reggroup);
4409 reggroup_add (gdbarch, system_reggroup);
4413 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
4414 struct reggroup *group)
4416 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4417 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
4418 ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p,
4419 bndr_regnum_p, bnd_regnum_p, k_regnum_p, zmm_regnum_p, zmmh_regnum_p,
4420 zmm_avx512_regnum_p, mpx_ctrl_regnum_p, xmm_avx512_regnum_p,
4421 avx512_p, avx_p, sse_p;
4423 /* Don't include pseudo registers, except for MMX, in any register
4425 if (i386_byte_regnum_p (gdbarch, regnum))
4428 if (i386_word_regnum_p (gdbarch, regnum))
4431 if (i386_dword_regnum_p (gdbarch, regnum))
4434 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
4435 if (group == i386_mmx_reggroup)
4436 return mmx_regnum_p;
4438 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
4439 xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum);
4440 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
4441 if (group == i386_sse_reggroup)
4442 return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p;
4444 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
4445 ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum);
4446 zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum);
4448 avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4449 == X86_XSTATE_AVX512_MASK);
4450 avx_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4451 == X86_XSTATE_AVX_MASK) && !avx512_p;
4452 sse_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4453 == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p;
4455 if (group == vector_reggroup)
4456 return (mmx_regnum_p
4457 || (zmm_regnum_p && avx512_p)
4458 || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p)
4459 || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p)
4462 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
4463 || i386_fpc_regnum_p (gdbarch, regnum));
4464 if (group == float_reggroup)
4467 /* For "info reg all", don't include upper YMM registers nor XMM
4468 registers when AVX is supported. */
4469 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
4470 ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum);
4471 zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum);
4472 if (group == all_reggroup
4473 && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p)
4474 || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p)
4476 || ymmh_avx512_regnum_p
4480 bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum);
4481 if (group == all_reggroup
4482 && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4483 return bnd_regnum_p;
4485 bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum);
4486 if (group == all_reggroup
4487 && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4490 mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum);
4491 if (group == all_reggroup
4492 && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4493 return mpx_ctrl_regnum_p;
4495 if (group == general_reggroup)
4496 return (!fp_regnum_p
4500 && !xmm_avx512_regnum_p
4503 && !ymm_avx512_regnum_p
4504 && !ymmh_avx512_regnum_p
4507 && !mpx_ctrl_regnum_p
4511 return default_register_reggroup_p (gdbarch, regnum, group);
4515 /* Get the ARGIth function argument for the current function. */
4518 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
4521 struct gdbarch *gdbarch = get_frame_arch (frame);
4522 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4523 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
4524 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
4527 #define PREFIX_REPZ 0x01
4528 #define PREFIX_REPNZ 0x02
4529 #define PREFIX_LOCK 0x04
4530 #define PREFIX_DATA 0x08
4531 #define PREFIX_ADDR 0x10
4543 /* i386 arith/logic operations */
4556 struct i386_record_s
4558 struct gdbarch *gdbarch;
4559 struct regcache *regcache;
4560 CORE_ADDR orig_addr;
4566 uint8_t mod, reg, rm;
4575 /* Parse the "modrm" part of the memory address irp->addr points at.
4576 Returns -1 if something goes wrong, 0 otherwise. */
4579 i386_record_modrm (struct i386_record_s *irp)
4581 struct gdbarch *gdbarch = irp->gdbarch;
4583 if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1))
4587 irp->mod = (irp->modrm >> 6) & 3;
4588 irp->reg = (irp->modrm >> 3) & 7;
4589 irp->rm = irp->modrm & 7;
4594 /* Extract the memory address that the current instruction writes to,
4595 and return it in *ADDR. Return -1 if something goes wrong. */
4598 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
4600 struct gdbarch *gdbarch = irp->gdbarch;
4601 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4606 if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM])
4613 uint8_t base = irp->rm;
4618 if (record_read_memory (gdbarch, irp->addr, &byte, 1))
4621 scale = (byte >> 6) & 3;
4622 index = ((byte >> 3) & 7) | irp->rex_x;
4630 if ((base & 7) == 5)
4633 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4636 *addr = extract_signed_integer (buf, 4, byte_order);
4637 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
4638 *addr += irp->addr + irp->rip_offset;
4642 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4645 *addr = (int8_t) buf[0];
4648 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4650 *addr = extract_signed_integer (buf, 4, byte_order);
4658 if (base == 4 && irp->popl_esp_hack)
4659 *addr += irp->popl_esp_hack;
4660 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
4663 if (irp->aflag == 2)
4668 *addr = (uint32_t) (offset64 + *addr);
4670 if (havesib && (index != 4 || scale != 0))
4672 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
4674 if (irp->aflag == 2)
4675 *addr += offset64 << scale;
4677 *addr = (uint32_t) (*addr + (offset64 << scale));
4682 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4683 address from 32-bit to 64-bit. */
4684 *addr = (uint32_t) *addr;
4695 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4698 *addr = extract_signed_integer (buf, 2, byte_order);
4704 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4707 *addr = (int8_t) buf[0];
4710 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4713 *addr = extract_signed_integer (buf, 2, byte_order);
4720 regcache_raw_read_unsigned (irp->regcache,
4721 irp->regmap[X86_RECORD_REBX_REGNUM],
4723 *addr = (uint32_t) (*addr + offset64);
4724 regcache_raw_read_unsigned (irp->regcache,
4725 irp->regmap[X86_RECORD_RESI_REGNUM],
4727 *addr = (uint32_t) (*addr + offset64);
4730 regcache_raw_read_unsigned (irp->regcache,
4731 irp->regmap[X86_RECORD_REBX_REGNUM],
4733 *addr = (uint32_t) (*addr + offset64);
4734 regcache_raw_read_unsigned (irp->regcache,
4735 irp->regmap[X86_RECORD_REDI_REGNUM],
4737 *addr = (uint32_t) (*addr + offset64);
4740 regcache_raw_read_unsigned (irp->regcache,
4741 irp->regmap[X86_RECORD_REBP_REGNUM],
4743 *addr = (uint32_t) (*addr + offset64);
4744 regcache_raw_read_unsigned (irp->regcache,
4745 irp->regmap[X86_RECORD_RESI_REGNUM],
4747 *addr = (uint32_t) (*addr + offset64);
4750 regcache_raw_read_unsigned (irp->regcache,
4751 irp->regmap[X86_RECORD_REBP_REGNUM],
4753 *addr = (uint32_t) (*addr + offset64);
4754 regcache_raw_read_unsigned (irp->regcache,
4755 irp->regmap[X86_RECORD_REDI_REGNUM],
4757 *addr = (uint32_t) (*addr + offset64);
4760 regcache_raw_read_unsigned (irp->regcache,
4761 irp->regmap[X86_RECORD_RESI_REGNUM],
4763 *addr = (uint32_t) (*addr + offset64);
4766 regcache_raw_read_unsigned (irp->regcache,
4767 irp->regmap[X86_RECORD_REDI_REGNUM],
4769 *addr = (uint32_t) (*addr + offset64);
4772 regcache_raw_read_unsigned (irp->regcache,
4773 irp->regmap[X86_RECORD_REBP_REGNUM],
4775 *addr = (uint32_t) (*addr + offset64);
4778 regcache_raw_read_unsigned (irp->regcache,
4779 irp->regmap[X86_RECORD_REBX_REGNUM],
4781 *addr = (uint32_t) (*addr + offset64);
4791 /* Record the address and contents of the memory that will be changed
4792 by the current instruction. Return -1 if something goes wrong, 0
4796 i386_record_lea_modrm (struct i386_record_s *irp)
4798 struct gdbarch *gdbarch = irp->gdbarch;
4801 if (irp->override >= 0)
4803 if (record_full_memory_query)
4807 target_terminal_ours ();
4809 Process record ignores the memory change of instruction at address %s\n\
4810 because it can't get the value of the segment register.\n\
4811 Do you want to stop the program?"),
4812 paddress (gdbarch, irp->orig_addr));
4813 target_terminal_inferior ();
4821 if (i386_record_lea_modrm_addr (irp, &addr))
4824 if (record_full_arch_list_add_mem (addr, 1 << irp->ot))
4830 /* Record the effects of a push operation. Return -1 if something
4831 goes wrong, 0 otherwise. */
4834 i386_record_push (struct i386_record_s *irp, int size)
4838 if (record_full_arch_list_add_reg (irp->regcache,
4839 irp->regmap[X86_RECORD_RESP_REGNUM]))
4841 regcache_raw_read_unsigned (irp->regcache,
4842 irp->regmap[X86_RECORD_RESP_REGNUM],
4844 if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size))
4851 /* Defines contents to record. */
4852 #define I386_SAVE_FPU_REGS 0xfffd
4853 #define I386_SAVE_FPU_ENV 0xfffe
4854 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4856 /* Record the values of the floating point registers which will be
4857 changed by the current instruction. Returns -1 if something is
4858 wrong, 0 otherwise. */
4860 static int i386_record_floats (struct gdbarch *gdbarch,
4861 struct i386_record_s *ir,
4864 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4867 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4868 happen. Currently we store st0-st7 registers, but we need not store all
4869 registers all the time, in future we use ftag register and record only
4870 those who are not marked as an empty. */
4872 if (I386_SAVE_FPU_REGS == iregnum)
4874 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
4876 if (record_full_arch_list_add_reg (ir->regcache, i))
4880 else if (I386_SAVE_FPU_ENV == iregnum)
4882 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4884 if (record_full_arch_list_add_reg (ir->regcache, i))
4888 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
4890 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4892 if (record_full_arch_list_add_reg (ir->regcache, i))
4896 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
4897 (iregnum <= I387_FOP_REGNUM (tdep)))
4899 if (record_full_arch_list_add_reg (ir->regcache,iregnum))
4904 /* Parameter error. */
4907 if(I386_SAVE_FPU_ENV != iregnum)
4909 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4911 if (record_full_arch_list_add_reg (ir->regcache, i))
4918 /* Parse the current instruction, and record the values of the
4919 registers and memory that will be changed by the current
4920 instruction. Returns -1 if something goes wrong, 0 otherwise. */
4922 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
4923 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
4926 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
4927 CORE_ADDR input_addr)
4929 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4935 gdb_byte buf[MAX_REGISTER_SIZE];
4936 struct i386_record_s ir;
4937 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4941 memset (&ir, 0, sizeof (struct i386_record_s));
4942 ir.regcache = regcache;
4943 ir.addr = input_addr;
4944 ir.orig_addr = input_addr;
4948 ir.popl_esp_hack = 0;
4949 ir.regmap = tdep->record_regmap;
4950 ir.gdbarch = gdbarch;
4952 if (record_debug > 1)
4953 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
4955 paddress (gdbarch, ir.addr));
4960 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
4963 switch (opcode8) /* Instruction prefixes */
4965 case REPE_PREFIX_OPCODE:
4966 prefixes |= PREFIX_REPZ;
4968 case REPNE_PREFIX_OPCODE:
4969 prefixes |= PREFIX_REPNZ;
4971 case LOCK_PREFIX_OPCODE:
4972 prefixes |= PREFIX_LOCK;
4974 case CS_PREFIX_OPCODE:
4975 ir.override = X86_RECORD_CS_REGNUM;
4977 case SS_PREFIX_OPCODE:
4978 ir.override = X86_RECORD_SS_REGNUM;
4980 case DS_PREFIX_OPCODE:
4981 ir.override = X86_RECORD_DS_REGNUM;
4983 case ES_PREFIX_OPCODE:
4984 ir.override = X86_RECORD_ES_REGNUM;
4986 case FS_PREFIX_OPCODE:
4987 ir.override = X86_RECORD_FS_REGNUM;
4989 case GS_PREFIX_OPCODE:
4990 ir.override = X86_RECORD_GS_REGNUM;
4992 case DATA_PREFIX_OPCODE:
4993 prefixes |= PREFIX_DATA;
4995 case ADDR_PREFIX_OPCODE:
4996 prefixes |= PREFIX_ADDR;
4998 case 0x40: /* i386 inc %eax */
4999 case 0x41: /* i386 inc %ecx */
5000 case 0x42: /* i386 inc %edx */
5001 case 0x43: /* i386 inc %ebx */
5002 case 0x44: /* i386 inc %esp */
5003 case 0x45: /* i386 inc %ebp */
5004 case 0x46: /* i386 inc %esi */
5005 case 0x47: /* i386 inc %edi */
5006 case 0x48: /* i386 dec %eax */
5007 case 0x49: /* i386 dec %ecx */
5008 case 0x4a: /* i386 dec %edx */
5009 case 0x4b: /* i386 dec %ebx */
5010 case 0x4c: /* i386 dec %esp */
5011 case 0x4d: /* i386 dec %ebp */
5012 case 0x4e: /* i386 dec %esi */
5013 case 0x4f: /* i386 dec %edi */
5014 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
5017 rex_w = (opcode8 >> 3) & 1;
5018 rex_r = (opcode8 & 0x4) << 1;
5019 ir.rex_x = (opcode8 & 0x2) << 2;
5020 ir.rex_b = (opcode8 & 0x1) << 3;
5022 else /* 32 bit target */
5031 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
5037 if (prefixes & PREFIX_DATA)
5040 if (prefixes & PREFIX_ADDR)
5042 else if (ir.regmap[X86_RECORD_R8_REGNUM])
5045 /* Now check op code. */
5046 opcode = (uint32_t) opcode8;
5051 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5054 opcode = (uint32_t) opcode8 | 0x0f00;
5058 case 0x00: /* arith & logic */
5106 if (((opcode >> 3) & 7) != OP_CMPL)
5108 if ((opcode & 1) == 0)
5111 ir.ot = ir.dflag + OT_WORD;
5113 switch ((opcode >> 1) & 3)
5115 case 0: /* OP Ev, Gv */
5116 if (i386_record_modrm (&ir))
5120 if (i386_record_lea_modrm (&ir))
5126 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5128 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5131 case 1: /* OP Gv, Ev */
5132 if (i386_record_modrm (&ir))
5135 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5137 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5139 case 2: /* OP A, Iv */
5140 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5144 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5147 case 0x80: /* GRP1 */
5151 if (i386_record_modrm (&ir))
5154 if (ir.reg != OP_CMPL)
5156 if ((opcode & 1) == 0)
5159 ir.ot = ir.dflag + OT_WORD;
5166 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5167 if (i386_record_lea_modrm (&ir))
5171 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5173 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5176 case 0x40: /* inc */
5185 case 0x48: /* dec */
5194 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7);
5195 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5198 case 0xf6: /* GRP3 */
5200 if ((opcode & 1) == 0)
5203 ir.ot = ir.dflag + OT_WORD;
5204 if (i386_record_modrm (&ir))
5207 if (ir.mod != 3 && ir.reg == 0)
5208 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5213 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5219 if (i386_record_lea_modrm (&ir))
5225 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5227 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5229 if (ir.reg == 3) /* neg */
5230 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5236 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5237 if (ir.ot != OT_BYTE)
5238 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5239 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5243 opcode = opcode << 8 | ir.modrm;
5249 case 0xfe: /* GRP4 */
5250 case 0xff: /* GRP5 */
5251 if (i386_record_modrm (&ir))
5253 if (ir.reg >= 2 && opcode == 0xfe)
5256 opcode = opcode << 8 | ir.modrm;
5263 if ((opcode & 1) == 0)
5266 ir.ot = ir.dflag + OT_WORD;
5269 if (i386_record_lea_modrm (&ir))
5275 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5277 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5279 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5282 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5284 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5286 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5289 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5290 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5292 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5296 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5299 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5301 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5306 opcode = opcode << 8 | ir.modrm;
5312 case 0x84: /* test */
5316 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5319 case 0x98: /* CWDE/CBW */
5320 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5323 case 0x99: /* CDQ/CWD */
5324 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5325 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5328 case 0x0faf: /* imul */
5331 ir.ot = ir.dflag + OT_WORD;
5332 if (i386_record_modrm (&ir))
5335 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5336 else if (opcode == 0x6b)
5339 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5341 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5342 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5345 case 0x0fc0: /* xadd */
5347 if ((opcode & 1) == 0)
5350 ir.ot = ir.dflag + OT_WORD;
5351 if (i386_record_modrm (&ir))
5356 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5358 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5359 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5361 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5365 if (i386_record_lea_modrm (&ir))
5367 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5369 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5371 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5374 case 0x0fb0: /* cmpxchg */
5376 if ((opcode & 1) == 0)
5379 ir.ot = ir.dflag + OT_WORD;
5380 if (i386_record_modrm (&ir))
5385 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5386 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5388 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5392 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5393 if (i386_record_lea_modrm (&ir))
5396 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5399 case 0x0fc7: /* cmpxchg8b */
5400 if (i386_record_modrm (&ir))
5405 opcode = opcode << 8 | ir.modrm;
5408 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5409 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5410 if (i386_record_lea_modrm (&ir))
5412 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5415 case 0x50: /* push */
5425 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5427 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5431 case 0x06: /* push es */
5432 case 0x0e: /* push cs */
5433 case 0x16: /* push ss */
5434 case 0x1e: /* push ds */
5435 if (ir.regmap[X86_RECORD_R8_REGNUM])
5440 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5444 case 0x0fa0: /* push fs */
5445 case 0x0fa8: /* push gs */
5446 if (ir.regmap[X86_RECORD_R8_REGNUM])
5451 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5455 case 0x60: /* pusha */
5456 if (ir.regmap[X86_RECORD_R8_REGNUM])
5461 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
5465 case 0x58: /* pop */
5473 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5474 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5477 case 0x61: /* popa */
5478 if (ir.regmap[X86_RECORD_R8_REGNUM])
5483 for (regnum = X86_RECORD_REAX_REGNUM;
5484 regnum <= X86_RECORD_REDI_REGNUM;
5486 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5489 case 0x8f: /* pop */
5490 if (ir.regmap[X86_RECORD_R8_REGNUM])
5491 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
5493 ir.ot = ir.dflag + OT_WORD;
5494 if (i386_record_modrm (&ir))
5497 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5500 ir.popl_esp_hack = 1 << ir.ot;
5501 if (i386_record_lea_modrm (&ir))
5504 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5507 case 0xc8: /* enter */
5508 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5509 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5511 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5515 case 0xc9: /* leave */
5516 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5517 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5520 case 0x07: /* pop es */
5521 if (ir.regmap[X86_RECORD_R8_REGNUM])
5526 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5527 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
5528 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5531 case 0x17: /* pop ss */
5532 if (ir.regmap[X86_RECORD_R8_REGNUM])
5537 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5538 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
5539 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5542 case 0x1f: /* pop ds */
5543 if (ir.regmap[X86_RECORD_R8_REGNUM])
5548 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5549 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
5550 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5553 case 0x0fa1: /* pop fs */
5554 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5555 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
5556 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5559 case 0x0fa9: /* pop gs */
5560 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5561 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
5562 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5565 case 0x88: /* mov */
5569 if ((opcode & 1) == 0)
5572 ir.ot = ir.dflag + OT_WORD;
5574 if (i386_record_modrm (&ir))
5579 if (opcode == 0xc6 || opcode == 0xc7)
5580 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5581 if (i386_record_lea_modrm (&ir))
5586 if (opcode == 0xc6 || opcode == 0xc7)
5588 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5590 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5594 case 0x8a: /* mov */
5596 if ((opcode & 1) == 0)
5599 ir.ot = ir.dflag + OT_WORD;
5600 if (i386_record_modrm (&ir))
5603 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5605 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5608 case 0x8c: /* mov seg */
5609 if (i386_record_modrm (&ir))
5614 opcode = opcode << 8 | ir.modrm;
5619 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5623 if (i386_record_lea_modrm (&ir))
5628 case 0x8e: /* mov seg */
5629 if (i386_record_modrm (&ir))
5634 regnum = X86_RECORD_ES_REGNUM;
5637 regnum = X86_RECORD_SS_REGNUM;
5640 regnum = X86_RECORD_DS_REGNUM;
5643 regnum = X86_RECORD_FS_REGNUM;
5646 regnum = X86_RECORD_GS_REGNUM;
5650 opcode = opcode << 8 | ir.modrm;
5654 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5655 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5658 case 0x0fb6: /* movzbS */
5659 case 0x0fb7: /* movzwS */
5660 case 0x0fbe: /* movsbS */
5661 case 0x0fbf: /* movswS */
5662 if (i386_record_modrm (&ir))
5664 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5667 case 0x8d: /* lea */
5668 if (i386_record_modrm (&ir))
5673 opcode = opcode << 8 | ir.modrm;
5678 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5680 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5683 case 0xa0: /* mov EAX */
5686 case 0xd7: /* xlat */
5687 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5690 case 0xa2: /* mov EAX */
5692 if (ir.override >= 0)
5694 if (record_full_memory_query)
5698 target_terminal_ours ();
5700 Process record ignores the memory change of instruction at address %s\n\
5701 because it can't get the value of the segment register.\n\
5702 Do you want to stop the program?"),
5703 paddress (gdbarch, ir.orig_addr));
5704 target_terminal_inferior ();
5711 if ((opcode & 1) == 0)
5714 ir.ot = ir.dflag + OT_WORD;
5717 if (record_read_memory (gdbarch, ir.addr, buf, 8))
5720 addr = extract_unsigned_integer (buf, 8, byte_order);
5724 if (record_read_memory (gdbarch, ir.addr, buf, 4))
5727 addr = extract_unsigned_integer (buf, 4, byte_order);
5731 if (record_read_memory (gdbarch, ir.addr, buf, 2))
5734 addr = extract_unsigned_integer (buf, 2, byte_order);
5736 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
5741 case 0xb0: /* mov R, Ib */
5749 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
5750 ? ((opcode & 0x7) | ir.rex_b)
5751 : ((opcode & 0x7) & 0x3));
5754 case 0xb8: /* mov R, Iv */
5762 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5765 case 0x91: /* xchg R, EAX */
5772 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5773 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7);
5776 case 0x86: /* xchg Ev, Gv */
5778 if ((opcode & 1) == 0)
5781 ir.ot = ir.dflag + OT_WORD;
5782 if (i386_record_modrm (&ir))
5787 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5789 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5793 if (i386_record_lea_modrm (&ir))
5797 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5799 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5802 case 0xc4: /* les Gv */
5803 case 0xc5: /* lds Gv */
5804 if (ir.regmap[X86_RECORD_R8_REGNUM])
5810 case 0x0fb2: /* lss Gv */
5811 case 0x0fb4: /* lfs Gv */
5812 case 0x0fb5: /* lgs Gv */
5813 if (i386_record_modrm (&ir))
5821 opcode = opcode << 8 | ir.modrm;
5826 case 0xc4: /* les Gv */
5827 regnum = X86_RECORD_ES_REGNUM;
5829 case 0xc5: /* lds Gv */
5830 regnum = X86_RECORD_DS_REGNUM;
5832 case 0x0fb2: /* lss Gv */
5833 regnum = X86_RECORD_SS_REGNUM;
5835 case 0x0fb4: /* lfs Gv */
5836 regnum = X86_RECORD_FS_REGNUM;
5838 case 0x0fb5: /* lgs Gv */
5839 regnum = X86_RECORD_GS_REGNUM;
5842 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5843 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5844 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5847 case 0xc0: /* shifts */
5853 if ((opcode & 1) == 0)
5856 ir.ot = ir.dflag + OT_WORD;
5857 if (i386_record_modrm (&ir))
5859 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
5861 if (i386_record_lea_modrm (&ir))
5867 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5869 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5871 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5878 if (i386_record_modrm (&ir))
5882 if (record_full_arch_list_add_reg (ir.regcache, ir.rm))
5887 if (i386_record_lea_modrm (&ir))
5892 case 0xd8: /* Floats. */
5900 if (i386_record_modrm (&ir))
5902 ir.reg |= ((opcode & 7) << 3);
5908 if (i386_record_lea_modrm_addr (&ir, &addr64))
5916 /* For fcom, ficom nothing to do. */
5922 /* For fcomp, ficomp pop FPU stack, store all. */
5923 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5950 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5951 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5952 of code, always affects st(0) register. */
5953 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
5977 /* Handling fld, fild. */
5978 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5982 switch (ir.reg >> 4)
5985 if (record_full_arch_list_add_mem (addr64, 4))
5989 if (record_full_arch_list_add_mem (addr64, 8))
5995 if (record_full_arch_list_add_mem (addr64, 2))
6001 switch (ir.reg >> 4)
6004 if (record_full_arch_list_add_mem (addr64, 4))
6006 if (3 == (ir.reg & 7))
6008 /* For fstp m32fp. */
6009 if (i386_record_floats (gdbarch, &ir,
6010 I386_SAVE_FPU_REGS))
6015 if (record_full_arch_list_add_mem (addr64, 4))
6017 if ((3 == (ir.reg & 7))
6018 || (5 == (ir.reg & 7))
6019 || (7 == (ir.reg & 7)))
6021 /* For fstp insn. */
6022 if (i386_record_floats (gdbarch, &ir,
6023 I386_SAVE_FPU_REGS))
6028 if (record_full_arch_list_add_mem (addr64, 8))
6030 if (3 == (ir.reg & 7))
6032 /* For fstp m64fp. */
6033 if (i386_record_floats (gdbarch, &ir,
6034 I386_SAVE_FPU_REGS))
6039 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
6041 /* For fistp, fbld, fild, fbstp. */
6042 if (i386_record_floats (gdbarch, &ir,
6043 I386_SAVE_FPU_REGS))
6048 if (record_full_arch_list_add_mem (addr64, 2))
6057 if (i386_record_floats (gdbarch, &ir,
6058 I386_SAVE_FPU_ENV_REG_STACK))
6063 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
6068 if (i386_record_floats (gdbarch, &ir,
6069 I386_SAVE_FPU_ENV_REG_STACK))
6075 if (record_full_arch_list_add_mem (addr64, 28))
6080 if (record_full_arch_list_add_mem (addr64, 14))
6086 if (record_full_arch_list_add_mem (addr64, 2))
6088 /* Insn fstp, fbstp. */
6089 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6094 if (record_full_arch_list_add_mem (addr64, 10))
6100 if (record_full_arch_list_add_mem (addr64, 28))
6106 if (record_full_arch_list_add_mem (addr64, 14))
6110 if (record_full_arch_list_add_mem (addr64, 80))
6113 if (i386_record_floats (gdbarch, &ir,
6114 I386_SAVE_FPU_ENV_REG_STACK))
6118 if (record_full_arch_list_add_mem (addr64, 8))
6121 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6126 opcode = opcode << 8 | ir.modrm;
6131 /* Opcode is an extension of modR/M byte. */
6137 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6141 if (0x0c == (ir.modrm >> 4))
6143 if ((ir.modrm & 0x0f) <= 7)
6145 if (i386_record_floats (gdbarch, &ir,
6146 I386_SAVE_FPU_REGS))
6151 if (i386_record_floats (gdbarch, &ir,
6152 I387_ST0_REGNUM (tdep)))
6154 /* If only st(0) is changing, then we have already
6156 if ((ir.modrm & 0x0f) - 0x08)
6158 if (i386_record_floats (gdbarch, &ir,
6159 I387_ST0_REGNUM (tdep) +
6160 ((ir.modrm & 0x0f) - 0x08)))
6178 if (i386_record_floats (gdbarch, &ir,
6179 I387_ST0_REGNUM (tdep)))
6197 if (i386_record_floats (gdbarch, &ir,
6198 I386_SAVE_FPU_REGS))
6202 if (i386_record_floats (gdbarch, &ir,
6203 I387_ST0_REGNUM (tdep)))
6205 if (i386_record_floats (gdbarch, &ir,
6206 I387_ST0_REGNUM (tdep) + 1))
6213 if (0xe9 == ir.modrm)
6215 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6218 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6220 if (i386_record_floats (gdbarch, &ir,
6221 I387_ST0_REGNUM (tdep)))
6223 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6225 if (i386_record_floats (gdbarch, &ir,
6226 I387_ST0_REGNUM (tdep) +
6230 else if ((ir.modrm & 0x0f) - 0x08)
6232 if (i386_record_floats (gdbarch, &ir,
6233 I387_ST0_REGNUM (tdep) +
6234 ((ir.modrm & 0x0f) - 0x08)))
6240 if (0xe3 == ir.modrm)
6242 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
6245 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6247 if (i386_record_floats (gdbarch, &ir,
6248 I387_ST0_REGNUM (tdep)))
6250 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6252 if (i386_record_floats (gdbarch, &ir,
6253 I387_ST0_REGNUM (tdep) +
6257 else if ((ir.modrm & 0x0f) - 0x08)
6259 if (i386_record_floats (gdbarch, &ir,
6260 I387_ST0_REGNUM (tdep) +
6261 ((ir.modrm & 0x0f) - 0x08)))
6267 if ((0x0c == ir.modrm >> 4)
6268 || (0x0d == ir.modrm >> 4)
6269 || (0x0f == ir.modrm >> 4))
6271 if ((ir.modrm & 0x0f) <= 7)
6273 if (i386_record_floats (gdbarch, &ir,
6274 I387_ST0_REGNUM (tdep) +
6280 if (i386_record_floats (gdbarch, &ir,
6281 I387_ST0_REGNUM (tdep) +
6282 ((ir.modrm & 0x0f) - 0x08)))
6288 if (0x0c == ir.modrm >> 4)
6290 if (i386_record_floats (gdbarch, &ir,
6291 I387_FTAG_REGNUM (tdep)))
6294 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6296 if ((ir.modrm & 0x0f) <= 7)
6298 if (i386_record_floats (gdbarch, &ir,
6299 I387_ST0_REGNUM (tdep) +
6305 if (i386_record_floats (gdbarch, &ir,
6306 I386_SAVE_FPU_REGS))
6312 if ((0x0c == ir.modrm >> 4)
6313 || (0x0e == ir.modrm >> 4)
6314 || (0x0f == ir.modrm >> 4)
6315 || (0xd9 == ir.modrm))
6317 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6322 if (0xe0 == ir.modrm)
6324 if (record_full_arch_list_add_reg (ir.regcache,
6328 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6330 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6338 case 0xa4: /* movsS */
6340 case 0xaa: /* stosS */
6342 case 0x6c: /* insS */
6344 regcache_raw_read_unsigned (ir.regcache,
6345 ir.regmap[X86_RECORD_RECX_REGNUM],
6351 if ((opcode & 1) == 0)
6354 ir.ot = ir.dflag + OT_WORD;
6355 regcache_raw_read_unsigned (ir.regcache,
6356 ir.regmap[X86_RECORD_REDI_REGNUM],
6359 regcache_raw_read_unsigned (ir.regcache,
6360 ir.regmap[X86_RECORD_ES_REGNUM],
6362 regcache_raw_read_unsigned (ir.regcache,
6363 ir.regmap[X86_RECORD_DS_REGNUM],
6365 if (ir.aflag && (es != ds))
6367 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6368 if (record_full_memory_query)
6372 target_terminal_ours ();
6374 Process record ignores the memory change of instruction at address %s\n\
6375 because it can't get the value of the segment register.\n\
6376 Do you want to stop the program?"),
6377 paddress (gdbarch, ir.orig_addr));
6378 target_terminal_inferior ();
6385 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
6389 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6390 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6391 if (opcode == 0xa4 || opcode == 0xa5)
6392 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6393 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6394 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6398 case 0xa6: /* cmpsS */
6400 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6401 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6402 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6403 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6404 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6407 case 0xac: /* lodsS */
6409 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6410 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6411 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6412 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6413 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6416 case 0xae: /* scasS */
6418 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6419 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6420 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6421 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6424 case 0x6e: /* outsS */
6426 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6427 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6428 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6429 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6432 case 0xe4: /* port I/O */
6436 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6437 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6447 case 0xc2: /* ret im */
6448 case 0xc3: /* ret */
6449 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6450 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6453 case 0xca: /* lret im */
6454 case 0xcb: /* lret */
6455 case 0xcf: /* iret */
6456 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6457 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6458 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6461 case 0xe8: /* call im */
6462 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6464 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6468 case 0x9a: /* lcall im */
6469 if (ir.regmap[X86_RECORD_R8_REGNUM])
6474 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6475 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6479 case 0xe9: /* jmp im */
6480 case 0xea: /* ljmp im */
6481 case 0xeb: /* jmp Jb */
6482 case 0x70: /* jcc Jb */
6498 case 0x0f80: /* jcc Jv */
6516 case 0x0f90: /* setcc Gv */
6532 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6534 if (i386_record_modrm (&ir))
6537 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
6541 if (i386_record_lea_modrm (&ir))
6546 case 0x0f40: /* cmov Gv, Ev */
6562 if (i386_record_modrm (&ir))
6565 if (ir.dflag == OT_BYTE)
6567 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
6571 case 0x9c: /* pushf */
6572 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6573 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6575 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6579 case 0x9d: /* popf */
6580 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6581 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6584 case 0x9e: /* sahf */
6585 if (ir.regmap[X86_RECORD_R8_REGNUM])
6591 case 0xf5: /* cmc */
6592 case 0xf8: /* clc */
6593 case 0xf9: /* stc */
6594 case 0xfc: /* cld */
6595 case 0xfd: /* std */
6596 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6599 case 0x9f: /* lahf */
6600 if (ir.regmap[X86_RECORD_R8_REGNUM])
6605 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6606 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6609 /* bit operations */
6610 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6611 ir.ot = ir.dflag + OT_WORD;
6612 if (i386_record_modrm (&ir))
6617 opcode = opcode << 8 | ir.modrm;
6623 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6626 if (i386_record_lea_modrm (&ir))
6630 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6633 case 0x0fa3: /* bt Gv, Ev */
6634 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6637 case 0x0fab: /* bts */
6638 case 0x0fb3: /* btr */
6639 case 0x0fbb: /* btc */
6640 ir.ot = ir.dflag + OT_WORD;
6641 if (i386_record_modrm (&ir))
6644 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6648 if (i386_record_lea_modrm_addr (&ir, &addr64))
6650 regcache_raw_read_unsigned (ir.regcache,
6651 ir.regmap[ir.reg | rex_r],
6656 addr64 += ((int16_t) addr >> 4) << 4;
6659 addr64 += ((int32_t) addr >> 5) << 5;
6662 addr64 += ((int64_t) addr >> 6) << 6;
6665 if (record_full_arch_list_add_mem (addr64, 1 << ir.ot))
6667 if (i386_record_lea_modrm (&ir))
6670 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6673 case 0x0fbc: /* bsf */
6674 case 0x0fbd: /* bsr */
6675 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6676 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6680 case 0x27: /* daa */
6681 case 0x2f: /* das */
6682 case 0x37: /* aaa */
6683 case 0x3f: /* aas */
6684 case 0xd4: /* aam */
6685 case 0xd5: /* aad */
6686 if (ir.regmap[X86_RECORD_R8_REGNUM])
6691 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6692 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6696 case 0x90: /* nop */
6697 if (prefixes & PREFIX_LOCK)
6704 case 0x9b: /* fwait */
6705 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
6707 opcode = (uint32_t) opcode8;
6713 case 0xcc: /* int3 */
6714 printf_unfiltered (_("Process record does not support instruction "
6721 case 0xcd: /* int */
6725 if (record_read_memory (gdbarch, ir.addr, &interrupt, 1))
6728 if (interrupt != 0x80
6729 || tdep->i386_intx80_record == NULL)
6731 printf_unfiltered (_("Process record does not support "
6732 "instruction int 0x%02x.\n"),
6737 ret = tdep->i386_intx80_record (ir.regcache);
6744 case 0xce: /* into */
6745 printf_unfiltered (_("Process record does not support "
6746 "instruction into.\n"));
6751 case 0xfa: /* cli */
6752 case 0xfb: /* sti */
6755 case 0x62: /* bound */
6756 printf_unfiltered (_("Process record does not support "
6757 "instruction bound.\n"));
6762 case 0x0fc8: /* bswap reg */
6770 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
6773 case 0xd6: /* salc */
6774 if (ir.regmap[X86_RECORD_R8_REGNUM])
6779 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6780 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6783 case 0xe0: /* loopnz */
6784 case 0xe1: /* loopz */
6785 case 0xe2: /* loop */
6786 case 0xe3: /* jecxz */
6787 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6788 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6791 case 0x0f30: /* wrmsr */
6792 printf_unfiltered (_("Process record does not support "
6793 "instruction wrmsr.\n"));
6798 case 0x0f32: /* rdmsr */
6799 printf_unfiltered (_("Process record does not support "
6800 "instruction rdmsr.\n"));
6805 case 0x0f31: /* rdtsc */
6806 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6807 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6810 case 0x0f34: /* sysenter */
6813 if (ir.regmap[X86_RECORD_R8_REGNUM])
6818 if (tdep->i386_sysenter_record == NULL)
6820 printf_unfiltered (_("Process record does not support "
6821 "instruction sysenter.\n"));
6825 ret = tdep->i386_sysenter_record (ir.regcache);
6831 case 0x0f35: /* sysexit */
6832 printf_unfiltered (_("Process record does not support "
6833 "instruction sysexit.\n"));
6838 case 0x0f05: /* syscall */
6841 if (tdep->i386_syscall_record == NULL)
6843 printf_unfiltered (_("Process record does not support "
6844 "instruction syscall.\n"));
6848 ret = tdep->i386_syscall_record (ir.regcache);
6854 case 0x0f07: /* sysret */
6855 printf_unfiltered (_("Process record does not support "
6856 "instruction sysret.\n"));
6861 case 0x0fa2: /* cpuid */
6862 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6863 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6864 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6865 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
6868 case 0xf4: /* hlt */
6869 printf_unfiltered (_("Process record does not support "
6870 "instruction hlt.\n"));
6876 if (i386_record_modrm (&ir))
6883 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6887 if (i386_record_lea_modrm (&ir))
6896 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6900 opcode = opcode << 8 | ir.modrm;
6907 if (i386_record_modrm (&ir))
6918 opcode = opcode << 8 | ir.modrm;
6921 if (ir.override >= 0)
6923 if (record_full_memory_query)
6927 target_terminal_ours ();
6929 Process record ignores the memory change of instruction at address %s\n\
6930 because it can't get the value of the segment register.\n\
6931 Do you want to stop the program?"),
6932 paddress (gdbarch, ir.orig_addr));
6933 target_terminal_inferior ();
6940 if (i386_record_lea_modrm_addr (&ir, &addr64))
6942 if (record_full_arch_list_add_mem (addr64, 2))
6945 if (ir.regmap[X86_RECORD_R8_REGNUM])
6947 if (record_full_arch_list_add_mem (addr64, 8))
6952 if (record_full_arch_list_add_mem (addr64, 4))
6963 case 0: /* monitor */
6966 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6970 opcode = opcode << 8 | ir.modrm;
6978 if (ir.override >= 0)
6980 if (record_full_memory_query)
6984 target_terminal_ours ();
6986 Process record ignores the memory change of instruction at address %s\n\
6987 because it can't get the value of the segment register.\n\
6988 Do you want to stop the program?"),
6989 paddress (gdbarch, ir.orig_addr));
6990 target_terminal_inferior ();
6999 if (i386_record_lea_modrm_addr (&ir, &addr64))
7001 if (record_full_arch_list_add_mem (addr64, 2))
7004 if (ir.regmap[X86_RECORD_R8_REGNUM])
7006 if (record_full_arch_list_add_mem (addr64, 8))
7011 if (record_full_arch_list_add_mem (addr64, 4))
7023 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7024 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7028 else if (ir.rm == 1)
7035 opcode = opcode << 8 | ir.modrm;
7042 if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
7048 if (i386_record_lea_modrm (&ir))
7051 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7054 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7056 case 7: /* invlpg */
7059 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
7060 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
7064 opcode = opcode << 8 | ir.modrm;
7069 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7073 opcode = opcode << 8 | ir.modrm;
7079 case 0x0f08: /* invd */
7080 case 0x0f09: /* wbinvd */
7083 case 0x63: /* arpl */
7084 if (i386_record_modrm (&ir))
7086 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
7088 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
7089 ? (ir.reg | rex_r) : ir.rm);
7093 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
7094 if (i386_record_lea_modrm (&ir))
7097 if (!ir.regmap[X86_RECORD_R8_REGNUM])
7098 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7101 case 0x0f02: /* lar */
7102 case 0x0f03: /* lsl */
7103 if (i386_record_modrm (&ir))
7105 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7106 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7110 if (i386_record_modrm (&ir))
7112 if (ir.mod == 3 && ir.reg == 3)
7115 opcode = opcode << 8 | ir.modrm;
7127 /* nop (multi byte) */
7130 case 0x0f20: /* mov reg, crN */
7131 case 0x0f22: /* mov crN, reg */
7132 if (i386_record_modrm (&ir))
7134 if ((ir.modrm & 0xc0) != 0xc0)
7137 opcode = opcode << 8 | ir.modrm;
7148 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7150 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7154 opcode = opcode << 8 | ir.modrm;
7160 case 0x0f21: /* mov reg, drN */
7161 case 0x0f23: /* mov drN, reg */
7162 if (i386_record_modrm (&ir))
7164 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
7165 || ir.reg == 5 || ir.reg >= 8)
7168 opcode = opcode << 8 | ir.modrm;
7172 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7174 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7177 case 0x0f06: /* clts */
7178 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7181 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7183 case 0x0f0d: /* 3DNow! prefetch */
7186 case 0x0f0e: /* 3DNow! femms */
7187 case 0x0f77: /* emms */
7188 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
7190 record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
7193 case 0x0f0f: /* 3DNow! data */
7194 if (i386_record_modrm (&ir))
7196 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7201 case 0x0c: /* 3DNow! pi2fw */
7202 case 0x0d: /* 3DNow! pi2fd */
7203 case 0x1c: /* 3DNow! pf2iw */
7204 case 0x1d: /* 3DNow! pf2id */
7205 case 0x8a: /* 3DNow! pfnacc */
7206 case 0x8e: /* 3DNow! pfpnacc */
7207 case 0x90: /* 3DNow! pfcmpge */
7208 case 0x94: /* 3DNow! pfmin */
7209 case 0x96: /* 3DNow! pfrcp */
7210 case 0x97: /* 3DNow! pfrsqrt */
7211 case 0x9a: /* 3DNow! pfsub */
7212 case 0x9e: /* 3DNow! pfadd */
7213 case 0xa0: /* 3DNow! pfcmpgt */
7214 case 0xa4: /* 3DNow! pfmax */
7215 case 0xa6: /* 3DNow! pfrcpit1 */
7216 case 0xa7: /* 3DNow! pfrsqit1 */
7217 case 0xaa: /* 3DNow! pfsubr */
7218 case 0xae: /* 3DNow! pfacc */
7219 case 0xb0: /* 3DNow! pfcmpeq */
7220 case 0xb4: /* 3DNow! pfmul */
7221 case 0xb6: /* 3DNow! pfrcpit2 */
7222 case 0xb7: /* 3DNow! pmulhrw */
7223 case 0xbb: /* 3DNow! pswapd */
7224 case 0xbf: /* 3DNow! pavgusb */
7225 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7226 goto no_support_3dnow_data;
7227 record_full_arch_list_add_reg (ir.regcache, ir.reg);
7231 no_support_3dnow_data:
7232 opcode = (opcode << 8) | opcode8;
7238 case 0x0faa: /* rsm */
7239 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7240 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7241 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
7242 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7243 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
7244 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
7245 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
7246 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
7247 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
7251 if (i386_record_modrm (&ir))
7255 case 0: /* fxsave */
7259 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7260 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
7262 if (record_full_arch_list_add_mem (tmpu64, 512))
7267 case 1: /* fxrstor */
7271 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7273 for (i = I387_MM0_REGNUM (tdep);
7274 i386_mmx_regnum_p (gdbarch, i); i++)
7275 record_full_arch_list_add_reg (ir.regcache, i);
7277 for (i = I387_XMM0_REGNUM (tdep);
7278 i386_xmm_regnum_p (gdbarch, i); i++)
7279 record_full_arch_list_add_reg (ir.regcache, i);
7281 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7282 record_full_arch_list_add_reg (ir.regcache,
7283 I387_MXCSR_REGNUM(tdep));
7285 for (i = I387_ST0_REGNUM (tdep);
7286 i386_fp_regnum_p (gdbarch, i); i++)
7287 record_full_arch_list_add_reg (ir.regcache, i);
7289 for (i = I387_FCTRL_REGNUM (tdep);
7290 i386_fpc_regnum_p (gdbarch, i); i++)
7291 record_full_arch_list_add_reg (ir.regcache, i);
7295 case 2: /* ldmxcsr */
7296 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7298 record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
7301 case 3: /* stmxcsr */
7303 if (i386_record_lea_modrm (&ir))
7307 case 5: /* lfence */
7308 case 6: /* mfence */
7309 case 7: /* sfence clflush */
7313 opcode = (opcode << 8) | ir.modrm;
7319 case 0x0fc3: /* movnti */
7320 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
7321 if (i386_record_modrm (&ir))
7326 if (i386_record_lea_modrm (&ir))
7330 /* Add prefix to opcode. */
7445 /* Mask out PREFIX_ADDR. */
7446 switch ((prefixes & ~PREFIX_ADDR))
7458 reswitch_prefix_add:
7466 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7469 opcode = (uint32_t) opcode8 | opcode << 8;
7470 goto reswitch_prefix_add;
7473 case 0x0f10: /* movups */
7474 case 0x660f10: /* movupd */
7475 case 0xf30f10: /* movss */
7476 case 0xf20f10: /* movsd */
7477 case 0x0f12: /* movlps */
7478 case 0x660f12: /* movlpd */
7479 case 0xf30f12: /* movsldup */
7480 case 0xf20f12: /* movddup */
7481 case 0x0f14: /* unpcklps */
7482 case 0x660f14: /* unpcklpd */
7483 case 0x0f15: /* unpckhps */
7484 case 0x660f15: /* unpckhpd */
7485 case 0x0f16: /* movhps */
7486 case 0x660f16: /* movhpd */
7487 case 0xf30f16: /* movshdup */
7488 case 0x0f28: /* movaps */
7489 case 0x660f28: /* movapd */
7490 case 0x0f2a: /* cvtpi2ps */
7491 case 0x660f2a: /* cvtpi2pd */
7492 case 0xf30f2a: /* cvtsi2ss */
7493 case 0xf20f2a: /* cvtsi2sd */
7494 case 0x0f2c: /* cvttps2pi */
7495 case 0x660f2c: /* cvttpd2pi */
7496 case 0x0f2d: /* cvtps2pi */
7497 case 0x660f2d: /* cvtpd2pi */
7498 case 0x660f3800: /* pshufb */
7499 case 0x660f3801: /* phaddw */
7500 case 0x660f3802: /* phaddd */
7501 case 0x660f3803: /* phaddsw */
7502 case 0x660f3804: /* pmaddubsw */
7503 case 0x660f3805: /* phsubw */
7504 case 0x660f3806: /* phsubd */
7505 case 0x660f3807: /* phsubsw */
7506 case 0x660f3808: /* psignb */
7507 case 0x660f3809: /* psignw */
7508 case 0x660f380a: /* psignd */
7509 case 0x660f380b: /* pmulhrsw */
7510 case 0x660f3810: /* pblendvb */
7511 case 0x660f3814: /* blendvps */
7512 case 0x660f3815: /* blendvpd */
7513 case 0x660f381c: /* pabsb */
7514 case 0x660f381d: /* pabsw */
7515 case 0x660f381e: /* pabsd */
7516 case 0x660f3820: /* pmovsxbw */
7517 case 0x660f3821: /* pmovsxbd */
7518 case 0x660f3822: /* pmovsxbq */
7519 case 0x660f3823: /* pmovsxwd */
7520 case 0x660f3824: /* pmovsxwq */
7521 case 0x660f3825: /* pmovsxdq */
7522 case 0x660f3828: /* pmuldq */
7523 case 0x660f3829: /* pcmpeqq */
7524 case 0x660f382a: /* movntdqa */
7525 case 0x660f3a08: /* roundps */
7526 case 0x660f3a09: /* roundpd */
7527 case 0x660f3a0a: /* roundss */
7528 case 0x660f3a0b: /* roundsd */
7529 case 0x660f3a0c: /* blendps */
7530 case 0x660f3a0d: /* blendpd */
7531 case 0x660f3a0e: /* pblendw */
7532 case 0x660f3a0f: /* palignr */
7533 case 0x660f3a20: /* pinsrb */
7534 case 0x660f3a21: /* insertps */
7535 case 0x660f3a22: /* pinsrd pinsrq */
7536 case 0x660f3a40: /* dpps */
7537 case 0x660f3a41: /* dppd */
7538 case 0x660f3a42: /* mpsadbw */
7539 case 0x660f3a60: /* pcmpestrm */
7540 case 0x660f3a61: /* pcmpestri */
7541 case 0x660f3a62: /* pcmpistrm */
7542 case 0x660f3a63: /* pcmpistri */
7543 case 0x0f51: /* sqrtps */
7544 case 0x660f51: /* sqrtpd */
7545 case 0xf20f51: /* sqrtsd */
7546 case 0xf30f51: /* sqrtss */
7547 case 0x0f52: /* rsqrtps */
7548 case 0xf30f52: /* rsqrtss */
7549 case 0x0f53: /* rcpps */
7550 case 0xf30f53: /* rcpss */
7551 case 0x0f54: /* andps */
7552 case 0x660f54: /* andpd */
7553 case 0x0f55: /* andnps */
7554 case 0x660f55: /* andnpd */
7555 case 0x0f56: /* orps */
7556 case 0x660f56: /* orpd */
7557 case 0x0f57: /* xorps */
7558 case 0x660f57: /* xorpd */
7559 case 0x0f58: /* addps */
7560 case 0x660f58: /* addpd */
7561 case 0xf20f58: /* addsd */
7562 case 0xf30f58: /* addss */
7563 case 0x0f59: /* mulps */
7564 case 0x660f59: /* mulpd */
7565 case 0xf20f59: /* mulsd */
7566 case 0xf30f59: /* mulss */
7567 case 0x0f5a: /* cvtps2pd */
7568 case 0x660f5a: /* cvtpd2ps */
7569 case 0xf20f5a: /* cvtsd2ss */
7570 case 0xf30f5a: /* cvtss2sd */
7571 case 0x0f5b: /* cvtdq2ps */
7572 case 0x660f5b: /* cvtps2dq */
7573 case 0xf30f5b: /* cvttps2dq */
7574 case 0x0f5c: /* subps */
7575 case 0x660f5c: /* subpd */
7576 case 0xf20f5c: /* subsd */
7577 case 0xf30f5c: /* subss */
7578 case 0x0f5d: /* minps */
7579 case 0x660f5d: /* minpd */
7580 case 0xf20f5d: /* minsd */
7581 case 0xf30f5d: /* minss */
7582 case 0x0f5e: /* divps */
7583 case 0x660f5e: /* divpd */
7584 case 0xf20f5e: /* divsd */
7585 case 0xf30f5e: /* divss */
7586 case 0x0f5f: /* maxps */
7587 case 0x660f5f: /* maxpd */
7588 case 0xf20f5f: /* maxsd */
7589 case 0xf30f5f: /* maxss */
7590 case 0x660f60: /* punpcklbw */
7591 case 0x660f61: /* punpcklwd */
7592 case 0x660f62: /* punpckldq */
7593 case 0x660f63: /* packsswb */
7594 case 0x660f64: /* pcmpgtb */
7595 case 0x660f65: /* pcmpgtw */
7596 case 0x660f66: /* pcmpgtd */
7597 case 0x660f67: /* packuswb */
7598 case 0x660f68: /* punpckhbw */
7599 case 0x660f69: /* punpckhwd */
7600 case 0x660f6a: /* punpckhdq */
7601 case 0x660f6b: /* packssdw */
7602 case 0x660f6c: /* punpcklqdq */
7603 case 0x660f6d: /* punpckhqdq */
7604 case 0x660f6e: /* movd */
7605 case 0x660f6f: /* movdqa */
7606 case 0xf30f6f: /* movdqu */
7607 case 0x660f70: /* pshufd */
7608 case 0xf20f70: /* pshuflw */
7609 case 0xf30f70: /* pshufhw */
7610 case 0x660f74: /* pcmpeqb */
7611 case 0x660f75: /* pcmpeqw */
7612 case 0x660f76: /* pcmpeqd */
7613 case 0x660f7c: /* haddpd */
7614 case 0xf20f7c: /* haddps */
7615 case 0x660f7d: /* hsubpd */
7616 case 0xf20f7d: /* hsubps */
7617 case 0xf30f7e: /* movq */
7618 case 0x0fc2: /* cmpps */
7619 case 0x660fc2: /* cmppd */
7620 case 0xf20fc2: /* cmpsd */
7621 case 0xf30fc2: /* cmpss */
7622 case 0x660fc4: /* pinsrw */
7623 case 0x0fc6: /* shufps */
7624 case 0x660fc6: /* shufpd */
7625 case 0x660fd0: /* addsubpd */
7626 case 0xf20fd0: /* addsubps */
7627 case 0x660fd1: /* psrlw */
7628 case 0x660fd2: /* psrld */
7629 case 0x660fd3: /* psrlq */
7630 case 0x660fd4: /* paddq */
7631 case 0x660fd5: /* pmullw */
7632 case 0xf30fd6: /* movq2dq */
7633 case 0x660fd8: /* psubusb */
7634 case 0x660fd9: /* psubusw */
7635 case 0x660fda: /* pminub */
7636 case 0x660fdb: /* pand */
7637 case 0x660fdc: /* paddusb */
7638 case 0x660fdd: /* paddusw */
7639 case 0x660fde: /* pmaxub */
7640 case 0x660fdf: /* pandn */
7641 case 0x660fe0: /* pavgb */
7642 case 0x660fe1: /* psraw */
7643 case 0x660fe2: /* psrad */
7644 case 0x660fe3: /* pavgw */
7645 case 0x660fe4: /* pmulhuw */
7646 case 0x660fe5: /* pmulhw */
7647 case 0x660fe6: /* cvttpd2dq */
7648 case 0xf20fe6: /* cvtpd2dq */
7649 case 0xf30fe6: /* cvtdq2pd */
7650 case 0x660fe8: /* psubsb */
7651 case 0x660fe9: /* psubsw */
7652 case 0x660fea: /* pminsw */
7653 case 0x660feb: /* por */
7654 case 0x660fec: /* paddsb */
7655 case 0x660fed: /* paddsw */
7656 case 0x660fee: /* pmaxsw */
7657 case 0x660fef: /* pxor */
7658 case 0xf20ff0: /* lddqu */
7659 case 0x660ff1: /* psllw */
7660 case 0x660ff2: /* pslld */
7661 case 0x660ff3: /* psllq */
7662 case 0x660ff4: /* pmuludq */
7663 case 0x660ff5: /* pmaddwd */
7664 case 0x660ff6: /* psadbw */
7665 case 0x660ff8: /* psubb */
7666 case 0x660ff9: /* psubw */
7667 case 0x660ffa: /* psubd */
7668 case 0x660ffb: /* psubq */
7669 case 0x660ffc: /* paddb */
7670 case 0x660ffd: /* paddw */
7671 case 0x660ffe: /* paddd */
7672 if (i386_record_modrm (&ir))
7675 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
7677 record_full_arch_list_add_reg (ir.regcache,
7678 I387_XMM0_REGNUM (tdep) + ir.reg);
7679 if ((opcode & 0xfffffffc) == 0x660f3a60)
7680 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7683 case 0x0f11: /* movups */
7684 case 0x660f11: /* movupd */
7685 case 0xf30f11: /* movss */
7686 case 0xf20f11: /* movsd */
7687 case 0x0f13: /* movlps */
7688 case 0x660f13: /* movlpd */
7689 case 0x0f17: /* movhps */
7690 case 0x660f17: /* movhpd */
7691 case 0x0f29: /* movaps */
7692 case 0x660f29: /* movapd */
7693 case 0x660f3a14: /* pextrb */
7694 case 0x660f3a15: /* pextrw */
7695 case 0x660f3a16: /* pextrd pextrq */
7696 case 0x660f3a17: /* extractps */
7697 case 0x660f7f: /* movdqa */
7698 case 0xf30f7f: /* movdqu */
7699 if (i386_record_modrm (&ir))
7703 if (opcode == 0x0f13 || opcode == 0x660f13
7704 || opcode == 0x0f17 || opcode == 0x660f17)
7707 if (!i386_xmm_regnum_p (gdbarch,
7708 I387_XMM0_REGNUM (tdep) + ir.rm))
7710 record_full_arch_list_add_reg (ir.regcache,
7711 I387_XMM0_REGNUM (tdep) + ir.rm);
7733 if (i386_record_lea_modrm (&ir))
7738 case 0x0f2b: /* movntps */
7739 case 0x660f2b: /* movntpd */
7740 case 0x0fe7: /* movntq */
7741 case 0x660fe7: /* movntdq */
7744 if (opcode == 0x0fe7)
7748 if (i386_record_lea_modrm (&ir))
7752 case 0xf30f2c: /* cvttss2si */
7753 case 0xf20f2c: /* cvttsd2si */
7754 case 0xf30f2d: /* cvtss2si */
7755 case 0xf20f2d: /* cvtsd2si */
7756 case 0xf20f38f0: /* crc32 */
7757 case 0xf20f38f1: /* crc32 */
7758 case 0x0f50: /* movmskps */
7759 case 0x660f50: /* movmskpd */
7760 case 0x0fc5: /* pextrw */
7761 case 0x660fc5: /* pextrw */
7762 case 0x0fd7: /* pmovmskb */
7763 case 0x660fd7: /* pmovmskb */
7764 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7767 case 0x0f3800: /* pshufb */
7768 case 0x0f3801: /* phaddw */
7769 case 0x0f3802: /* phaddd */
7770 case 0x0f3803: /* phaddsw */
7771 case 0x0f3804: /* pmaddubsw */
7772 case 0x0f3805: /* phsubw */
7773 case 0x0f3806: /* phsubd */
7774 case 0x0f3807: /* phsubsw */
7775 case 0x0f3808: /* psignb */
7776 case 0x0f3809: /* psignw */
7777 case 0x0f380a: /* psignd */
7778 case 0x0f380b: /* pmulhrsw */
7779 case 0x0f381c: /* pabsb */
7780 case 0x0f381d: /* pabsw */
7781 case 0x0f381e: /* pabsd */
7782 case 0x0f382b: /* packusdw */
7783 case 0x0f3830: /* pmovzxbw */
7784 case 0x0f3831: /* pmovzxbd */
7785 case 0x0f3832: /* pmovzxbq */
7786 case 0x0f3833: /* pmovzxwd */
7787 case 0x0f3834: /* pmovzxwq */
7788 case 0x0f3835: /* pmovzxdq */
7789 case 0x0f3837: /* pcmpgtq */
7790 case 0x0f3838: /* pminsb */
7791 case 0x0f3839: /* pminsd */
7792 case 0x0f383a: /* pminuw */
7793 case 0x0f383b: /* pminud */
7794 case 0x0f383c: /* pmaxsb */
7795 case 0x0f383d: /* pmaxsd */
7796 case 0x0f383e: /* pmaxuw */
7797 case 0x0f383f: /* pmaxud */
7798 case 0x0f3840: /* pmulld */
7799 case 0x0f3841: /* phminposuw */
7800 case 0x0f3a0f: /* palignr */
7801 case 0x0f60: /* punpcklbw */
7802 case 0x0f61: /* punpcklwd */
7803 case 0x0f62: /* punpckldq */
7804 case 0x0f63: /* packsswb */
7805 case 0x0f64: /* pcmpgtb */
7806 case 0x0f65: /* pcmpgtw */
7807 case 0x0f66: /* pcmpgtd */
7808 case 0x0f67: /* packuswb */
7809 case 0x0f68: /* punpckhbw */
7810 case 0x0f69: /* punpckhwd */
7811 case 0x0f6a: /* punpckhdq */
7812 case 0x0f6b: /* packssdw */
7813 case 0x0f6e: /* movd */
7814 case 0x0f6f: /* movq */
7815 case 0x0f70: /* pshufw */
7816 case 0x0f74: /* pcmpeqb */
7817 case 0x0f75: /* pcmpeqw */
7818 case 0x0f76: /* pcmpeqd */
7819 case 0x0fc4: /* pinsrw */
7820 case 0x0fd1: /* psrlw */
7821 case 0x0fd2: /* psrld */
7822 case 0x0fd3: /* psrlq */
7823 case 0x0fd4: /* paddq */
7824 case 0x0fd5: /* pmullw */
7825 case 0xf20fd6: /* movdq2q */
7826 case 0x0fd8: /* psubusb */
7827 case 0x0fd9: /* psubusw */
7828 case 0x0fda: /* pminub */
7829 case 0x0fdb: /* pand */
7830 case 0x0fdc: /* paddusb */
7831 case 0x0fdd: /* paddusw */
7832 case 0x0fde: /* pmaxub */
7833 case 0x0fdf: /* pandn */
7834 case 0x0fe0: /* pavgb */
7835 case 0x0fe1: /* psraw */
7836 case 0x0fe2: /* psrad */
7837 case 0x0fe3: /* pavgw */
7838 case 0x0fe4: /* pmulhuw */
7839 case 0x0fe5: /* pmulhw */
7840 case 0x0fe8: /* psubsb */
7841 case 0x0fe9: /* psubsw */
7842 case 0x0fea: /* pminsw */
7843 case 0x0feb: /* por */
7844 case 0x0fec: /* paddsb */
7845 case 0x0fed: /* paddsw */
7846 case 0x0fee: /* pmaxsw */
7847 case 0x0fef: /* pxor */
7848 case 0x0ff1: /* psllw */
7849 case 0x0ff2: /* pslld */
7850 case 0x0ff3: /* psllq */
7851 case 0x0ff4: /* pmuludq */
7852 case 0x0ff5: /* pmaddwd */
7853 case 0x0ff6: /* psadbw */
7854 case 0x0ff8: /* psubb */
7855 case 0x0ff9: /* psubw */
7856 case 0x0ffa: /* psubd */
7857 case 0x0ffb: /* psubq */
7858 case 0x0ffc: /* paddb */
7859 case 0x0ffd: /* paddw */
7860 case 0x0ffe: /* paddd */
7861 if (i386_record_modrm (&ir))
7863 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7865 record_full_arch_list_add_reg (ir.regcache,
7866 I387_MM0_REGNUM (tdep) + ir.reg);
7869 case 0x0f71: /* psllw */
7870 case 0x0f72: /* pslld */
7871 case 0x0f73: /* psllq */
7872 if (i386_record_modrm (&ir))
7874 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7876 record_full_arch_list_add_reg (ir.regcache,
7877 I387_MM0_REGNUM (tdep) + ir.rm);
7880 case 0x660f71: /* psllw */
7881 case 0x660f72: /* pslld */
7882 case 0x660f73: /* psllq */
7883 if (i386_record_modrm (&ir))
7886 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
7888 record_full_arch_list_add_reg (ir.regcache,
7889 I387_XMM0_REGNUM (tdep) + ir.rm);
7892 case 0x0f7e: /* movd */
7893 case 0x660f7e: /* movd */
7894 if (i386_record_modrm (&ir))
7897 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7904 if (i386_record_lea_modrm (&ir))
7909 case 0x0f7f: /* movq */
7910 if (i386_record_modrm (&ir))
7914 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7916 record_full_arch_list_add_reg (ir.regcache,
7917 I387_MM0_REGNUM (tdep) + ir.rm);
7922 if (i386_record_lea_modrm (&ir))
7927 case 0xf30fb8: /* popcnt */
7928 if (i386_record_modrm (&ir))
7930 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
7931 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7934 case 0x660fd6: /* movq */
7935 if (i386_record_modrm (&ir))
7940 if (!i386_xmm_regnum_p (gdbarch,
7941 I387_XMM0_REGNUM (tdep) + ir.rm))
7943 record_full_arch_list_add_reg (ir.regcache,
7944 I387_XMM0_REGNUM (tdep) + ir.rm);
7949 if (i386_record_lea_modrm (&ir))
7954 case 0x660f3817: /* ptest */
7955 case 0x0f2e: /* ucomiss */
7956 case 0x660f2e: /* ucomisd */
7957 case 0x0f2f: /* comiss */
7958 case 0x660f2f: /* comisd */
7959 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7962 case 0x0ff7: /* maskmovq */
7963 regcache_raw_read_unsigned (ir.regcache,
7964 ir.regmap[X86_RECORD_REDI_REGNUM],
7966 if (record_full_arch_list_add_mem (addr, 64))
7970 case 0x660ff7: /* maskmovdqu */
7971 regcache_raw_read_unsigned (ir.regcache,
7972 ir.regmap[X86_RECORD_REDI_REGNUM],
7974 if (record_full_arch_list_add_mem (addr, 128))
7989 /* In the future, maybe still need to deal with need_dasm. */
7990 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
7991 if (record_full_arch_list_add_end ())
7997 printf_unfiltered (_("Process record does not support instruction 0x%02x "
7998 "at address %s.\n"),
7999 (unsigned int) (opcode),
8000 paddress (gdbarch, ir.orig_addr));
8004 static const int i386_record_regmap[] =
8006 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
8007 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
8008 0, 0, 0, 0, 0, 0, 0, 0,
8009 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
8010 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
8013 /* Check that the given address appears suitable for a fast
8014 tracepoint, which on x86-64 means that we need an instruction of at
8015 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8016 jump and not have to worry about program jumps to an address in the
8017 middle of the tracepoint jump. On x86, it may be possible to use
8018 4-byte jumps with a 2-byte offset to a trampoline located in the
8019 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8020 of instruction to replace, and 0 if not, plus an explanatory
8024 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch,
8025 CORE_ADDR addr, int *isize, char **msg)
8028 static struct ui_file *gdb_null = NULL;
8030 /* Ask the target for the minimum instruction length supported. */
8031 jumplen = target_get_min_fast_tracepoint_insn_len ();
8035 /* If the target does not support the get_min_fast_tracepoint_insn_len
8036 operation, assume that fast tracepoints will always be implemented
8037 using 4-byte relative jumps on both x86 and x86-64. */
8040 else if (jumplen == 0)
8042 /* If the target does support get_min_fast_tracepoint_insn_len but
8043 returns zero, then the IPA has not loaded yet. In this case,
8044 we optimistically assume that truncated 2-byte relative jumps
8045 will be available on x86, and compensate later if this assumption
8046 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8047 jumps will always be used. */
8048 jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4;
8051 /* Dummy file descriptor for the disassembler. */
8053 gdb_null = ui_file_new ();
8055 /* Check for fit. */
8056 len = gdb_print_insn (gdbarch, addr, gdb_null, NULL);
8062 /* Return a bit of target-specific detail to add to the caller's
8063 generic failure message. */
8065 *msg = xstrprintf (_("; instruction is only %d bytes long, "
8066 "need at least %d bytes for the jump"),
8079 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
8080 struct tdesc_arch_data *tdesc_data)
8082 const struct target_desc *tdesc = tdep->tdesc;
8083 const struct tdesc_feature *feature_core;
8085 const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx,
8087 int i, num_regs, valid_p;
8089 if (! tdesc_has_registers (tdesc))
8092 /* Get core registers. */
8093 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
8094 if (feature_core == NULL)
8097 /* Get SSE registers. */
8098 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
8100 /* Try AVX registers. */
8101 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
8103 /* Try MPX registers. */
8104 feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx");
8106 /* Try AVX512 registers. */
8107 feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512");
8111 /* The XCR0 bits. */
8114 /* AVX512 register description requires AVX register description. */
8118 tdep->xcr0 = X86_XSTATE_MPX_AVX512_MASK;
8120 /* It may have been set by OSABI initialization function. */
8121 if (tdep->k0_regnum < 0)
8123 tdep->k_register_names = i386_k_names;
8124 tdep->k0_regnum = I386_K0_REGNUM;
8127 for (i = 0; i < I387_NUM_K_REGS; i++)
8128 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8129 tdep->k0_regnum + i,
8132 if (tdep->num_zmm_regs == 0)
8134 tdep->zmmh_register_names = i386_zmmh_names;
8135 tdep->num_zmm_regs = 8;
8136 tdep->zmm0h_regnum = I386_ZMM0H_REGNUM;
8139 for (i = 0; i < tdep->num_zmm_regs; i++)
8140 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8141 tdep->zmm0h_regnum + i,
8142 tdep->zmmh_register_names[i]);
8144 for (i = 0; i < tdep->num_xmm_avx512_regs; i++)
8145 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8146 tdep->xmm16_regnum + i,
8147 tdep->xmm_avx512_register_names[i]);
8149 for (i = 0; i < tdep->num_ymm_avx512_regs; i++)
8150 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8151 tdep->ymm16h_regnum + i,
8152 tdep->ymm16h_register_names[i]);
8156 /* AVX register description requires SSE register description. */
8160 if (!feature_avx512)
8161 tdep->xcr0 = X86_XSTATE_AVX_MASK;
8163 /* It may have been set by OSABI initialization function. */
8164 if (tdep->num_ymm_regs == 0)
8166 tdep->ymmh_register_names = i386_ymmh_names;
8167 tdep->num_ymm_regs = 8;
8168 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
8171 for (i = 0; i < tdep->num_ymm_regs; i++)
8172 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
8173 tdep->ymm0h_regnum + i,
8174 tdep->ymmh_register_names[i]);
8176 else if (feature_sse)
8177 tdep->xcr0 = X86_XSTATE_SSE_MASK;
8180 tdep->xcr0 = X86_XSTATE_X87_MASK;
8181 tdep->num_xmm_regs = 0;
8184 num_regs = tdep->num_core_regs;
8185 for (i = 0; i < num_regs; i++)
8186 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
8187 tdep->register_names[i]);
8191 /* Need to include %mxcsr, so add one. */
8192 num_regs += tdep->num_xmm_regs + 1;
8193 for (; i < num_regs; i++)
8194 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
8195 tdep->register_names[i]);
8200 tdep->xcr0 |= X86_XSTATE_MPX_MASK;
8202 if (tdep->bnd0r_regnum < 0)
8204 tdep->mpx_register_names = i386_mpx_names;
8205 tdep->bnd0r_regnum = I386_BND0R_REGNUM;
8206 tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM;
8209 for (i = 0; i < I387_NUM_MPX_REGS; i++)
8210 valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data,
8211 I387_BND0R_REGNUM (tdep) + i,
8212 tdep->mpx_register_names[i]);
8219 static struct gdbarch *
8220 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8222 struct gdbarch_tdep *tdep;
8223 struct gdbarch *gdbarch;
8224 struct tdesc_arch_data *tdesc_data;
8225 const struct target_desc *tdesc;
8233 /* If there is already a candidate, use it. */
8234 arches = gdbarch_list_lookup_by_info (arches, &info);
8236 return arches->gdbarch;
8238 /* Allocate space for the new architecture. */
8239 tdep = XCNEW (struct gdbarch_tdep);
8240 gdbarch = gdbarch_alloc (&info, tdep);
8242 /* General-purpose registers. */
8243 tdep->gregset_reg_offset = NULL;
8244 tdep->gregset_num_regs = I386_NUM_GREGS;
8245 tdep->sizeof_gregset = 0;
8247 /* Floating-point registers. */
8248 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
8249 tdep->fpregset = &i386_fpregset;
8251 /* The default settings include the FPU registers, the MMX registers
8252 and the SSE registers. This can be overridden for a specific ABI
8253 by adjusting the members `st0_regnum', `mm0_regnum' and
8254 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8255 will show up in the output of "info all-registers". */
8257 tdep->st0_regnum = I386_ST0_REGNUM;
8259 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8260 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
8262 tdep->jb_pc_offset = -1;
8263 tdep->struct_return = pcc_struct_return;
8264 tdep->sigtramp_start = 0;
8265 tdep->sigtramp_end = 0;
8266 tdep->sigtramp_p = i386_sigtramp_p;
8267 tdep->sigcontext_addr = NULL;
8268 tdep->sc_reg_offset = NULL;
8269 tdep->sc_pc_offset = -1;
8270 tdep->sc_sp_offset = -1;
8272 tdep->xsave_xcr0_offset = -1;
8274 tdep->record_regmap = i386_record_regmap;
8276 set_gdbarch_long_long_align_bit (gdbarch, 32);
8278 /* The format used for `long double' on almost all i386 targets is
8279 the i387 extended floating-point format. In fact, of all targets
8280 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8281 on having a `long double' that's not `long' at all. */
8282 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
8284 /* Although the i387 extended floating-point has only 80 significant
8285 bits, a `long double' actually takes up 96, probably to enforce
8287 set_gdbarch_long_double_bit (gdbarch, 96);
8289 /* Register numbers of various important registers. */
8290 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
8291 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
8292 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
8293 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
8295 /* NOTE: kettenis/20040418: GCC does have two possible register
8296 numbering schemes on the i386: dbx and SVR4. These schemes
8297 differ in how they number %ebp, %esp, %eflags, and the
8298 floating-point registers, and are implemented by the arrays
8299 dbx_register_map[] and svr4_dbx_register_map in
8300 gcc/config/i386.c. GCC also defines a third numbering scheme in
8301 gcc/config/i386.c, which it designates as the "default" register
8302 map used in 64bit mode. This last register numbering scheme is
8303 implemented in dbx64_register_map, and is used for AMD64; see
8306 Currently, each GCC i386 target always uses the same register
8307 numbering scheme across all its supported debugging formats
8308 i.e. SDB (COFF), stabs and DWARF 2. This is because
8309 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8310 DBX_REGISTER_NUMBER macro which is defined by each target's
8311 respective config header in a manner independent of the requested
8312 output debugging format.
8314 This does not match the arrangement below, which presumes that
8315 the SDB and stabs numbering schemes differ from the DWARF and
8316 DWARF 2 ones. The reason for this arrangement is that it is
8317 likely to get the numbering scheme for the target's
8318 default/native debug format right. For targets where GCC is the
8319 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8320 targets where the native toolchain uses a different numbering
8321 scheme for a particular debug format (stabs-in-ELF on Solaris)
8322 the defaults below will have to be overridden, like
8323 i386_elf_init_abi() does. */
8325 /* Use the dbx register numbering scheme for stabs and COFF. */
8326 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8327 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8329 /* Use the SVR4 register numbering scheme for DWARF 2. */
8330 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
8332 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8333 be in use on any of the supported i386 targets. */
8335 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
8337 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
8339 /* Call dummy code. */
8340 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
8341 set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code);
8342 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
8343 set_gdbarch_frame_align (gdbarch, i386_frame_align);
8345 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
8346 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
8347 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
8349 set_gdbarch_return_value (gdbarch, i386_return_value);
8351 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
8353 /* Stack grows downward. */
8354 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8356 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc);
8357 set_gdbarch_decr_pc_after_break (gdbarch, 1);
8358 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
8360 set_gdbarch_frame_args_skip (gdbarch, 8);
8362 set_gdbarch_print_insn (gdbarch, i386_print_insn);
8364 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
8366 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
8368 /* Add the i386 register groups. */
8369 i386_add_reggroups (gdbarch);
8370 tdep->register_reggroup_p = i386_register_reggroup_p;
8372 /* Helper for function argument information. */
8373 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
8375 /* Hook the function epilogue frame unwinder. This unwinder is
8376 appended to the list first, so that it supercedes the DWARF
8377 unwinder in function epilogues (where the DWARF unwinder
8378 currently fails). */
8379 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
8381 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8382 to the list before the prologue-based unwinders, so that DWARF
8383 CFI info will be used if it is available. */
8384 dwarf2_append_unwinders (gdbarch);
8386 frame_base_set_default (gdbarch, &i386_frame_base);
8388 /* Pseudo registers may be changed by amd64_init_abi. */
8389 set_gdbarch_pseudo_register_read_value (gdbarch,
8390 i386_pseudo_register_read_value);
8391 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
8393 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
8394 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
8396 /* Override the normal target description method to make the AVX
8397 upper halves anonymous. */
8398 set_gdbarch_register_name (gdbarch, i386_register_name);
8400 /* Even though the default ABI only includes general-purpose registers,
8401 floating-point registers and the SSE registers, we have to leave a
8402 gap for the upper AVX, MPX and AVX512 registers. */
8403 set_gdbarch_num_regs (gdbarch, I386_AVX512_NUM_REGS);
8405 /* Get the x86 target description from INFO. */
8406 tdesc = info.target_desc;
8407 if (! tdesc_has_registers (tdesc))
8409 tdep->tdesc = tdesc;
8411 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
8412 tdep->register_names = i386_register_names;
8414 /* No upper YMM registers. */
8415 tdep->ymmh_register_names = NULL;
8416 tdep->ymm0h_regnum = -1;
8418 /* No upper ZMM registers. */
8419 tdep->zmmh_register_names = NULL;
8420 tdep->zmm0h_regnum = -1;
8422 /* No high XMM registers. */
8423 tdep->xmm_avx512_register_names = NULL;
8424 tdep->xmm16_regnum = -1;
8426 /* No upper YMM16-31 registers. */
8427 tdep->ymm16h_register_names = NULL;
8428 tdep->ymm16h_regnum = -1;
8430 tdep->num_byte_regs = 8;
8431 tdep->num_word_regs = 8;
8432 tdep->num_dword_regs = 0;
8433 tdep->num_mmx_regs = 8;
8434 tdep->num_ymm_regs = 0;
8436 /* No MPX registers. */
8437 tdep->bnd0r_regnum = -1;
8438 tdep->bndcfgu_regnum = -1;
8440 /* No AVX512 registers. */
8441 tdep->k0_regnum = -1;
8442 tdep->num_zmm_regs = 0;
8443 tdep->num_ymm_avx512_regs = 0;
8444 tdep->num_xmm_avx512_regs = 0;
8446 tdesc_data = tdesc_data_alloc ();
8448 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
8450 set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address);
8452 set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call);
8453 set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret);
8454 set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump);
8456 /* Hook in ABI-specific overrides, if they have been registered. */
8457 info.tdep_info = (void *) tdesc_data;
8458 gdbarch_init_osabi (info, gdbarch);
8460 if (!i386_validate_tdesc_p (tdep, tdesc_data))
8462 tdesc_data_cleanup (tdesc_data);
8464 gdbarch_free (gdbarch);
8468 num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0);
8470 /* Wire in pseudo registers. Number of pseudo registers may be
8472 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
8473 + tdep->num_word_regs
8474 + tdep->num_dword_regs
8475 + tdep->num_mmx_regs
8476 + tdep->num_ymm_regs
8478 + tdep->num_ymm_avx512_regs
8479 + tdep->num_zmm_regs));
8481 /* Target description may be changed. */
8482 tdesc = tdep->tdesc;
8484 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
8486 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8487 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
8489 /* Make %al the first pseudo-register. */
8490 tdep->al_regnum = gdbarch_num_regs (gdbarch);
8491 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
8493 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
8494 if (tdep->num_dword_regs)
8496 /* Support dword pseudo-register if it hasn't been disabled. */
8497 tdep->eax_regnum = ymm0_regnum;
8498 ymm0_regnum += tdep->num_dword_regs;
8501 tdep->eax_regnum = -1;
8503 mm0_regnum = ymm0_regnum;
8504 if (tdep->num_ymm_regs)
8506 /* Support YMM pseudo-register if it is available. */
8507 tdep->ymm0_regnum = ymm0_regnum;
8508 mm0_regnum += tdep->num_ymm_regs;
8511 tdep->ymm0_regnum = -1;
8513 if (tdep->num_ymm_avx512_regs)
8515 /* Support YMM16-31 pseudo registers if available. */
8516 tdep->ymm16_regnum = mm0_regnum;
8517 mm0_regnum += tdep->num_ymm_avx512_regs;
8520 tdep->ymm16_regnum = -1;
8522 if (tdep->num_zmm_regs)
8524 /* Support ZMM pseudo-register if it is available. */
8525 tdep->zmm0_regnum = mm0_regnum;
8526 mm0_regnum += tdep->num_zmm_regs;
8529 tdep->zmm0_regnum = -1;
8531 bnd0_regnum = mm0_regnum;
8532 if (tdep->num_mmx_regs != 0)
8534 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8535 tdep->mm0_regnum = mm0_regnum;
8536 bnd0_regnum += tdep->num_mmx_regs;
8539 tdep->mm0_regnum = -1;
8541 if (tdep->bnd0r_regnum > 0)
8542 tdep->bnd0_regnum = bnd0_regnum;
8544 tdep-> bnd0_regnum = -1;
8546 /* Hook in the legacy prologue-based unwinders last (fallback). */
8547 frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind);
8548 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
8549 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
8551 /* If we have a register mapping, enable the generic core file
8552 support, unless it has already been enabled. */
8553 if (tdep->gregset_reg_offset
8554 && !gdbarch_iterate_over_regset_sections_p (gdbarch))
8555 set_gdbarch_iterate_over_regset_sections
8556 (gdbarch, i386_iterate_over_regset_sections);
8558 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
8559 i386_fast_tracepoint_valid_at);
8564 static enum gdb_osabi
8565 i386_coff_osabi_sniffer (bfd *abfd)
8567 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
8568 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
8569 return GDB_OSABI_GO32;
8571 return GDB_OSABI_UNKNOWN;
8575 /* Provide a prototype to silence -Wmissing-prototypes. */
8576 void _initialize_i386_tdep (void);
8579 _initialize_i386_tdep (void)
8581 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
8583 /* Add the variable that controls the disassembly flavor. */
8584 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
8585 &disassembly_flavor, _("\
8586 Set the disassembly flavor."), _("\
8587 Show the disassembly flavor."), _("\
8588 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
8590 NULL, /* FIXME: i18n: */
8591 &setlist, &showlist);
8593 /* Add the variable that controls the convention for returning
8595 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
8596 &struct_convention, _("\
8597 Set the convention for returning small structs."), _("\
8598 Show the convention for returning small structs."), _("\
8599 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
8602 NULL, /* FIXME: i18n: */
8603 &setlist, &showlist);
8605 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
8606 i386_coff_osabi_sniffer);
8608 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
8609 i386_svr4_init_abi);
8610 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
8611 i386_go32_init_abi);
8613 /* Initialize the i386-specific register groups. */
8614 i386_init_reggroups ();
8616 /* Initialize the standard target descriptions. */
8617 initialize_tdesc_i386 ();
8618 initialize_tdesc_i386_mmx ();
8619 initialize_tdesc_i386_avx ();
8620 initialize_tdesc_i386_mpx ();
8621 initialize_tdesc_i386_avx512 ();
8623 /* Tell remote stub that we support XML target description. */
8624 register_remote_support_xml ("i386");