1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
47 #include "gdb_assert.h"
48 #include "gdb_string.h"
50 #include "i386-tdep.h"
51 #include "i387-tdep.h"
58 static char *i386_register_names[] =
60 "eax", "ecx", "edx", "ebx",
61 "esp", "ebp", "esi", "edi",
62 "eip", "eflags", "cs", "ss",
63 "ds", "es", "fs", "gs",
64 "st0", "st1", "st2", "st3",
65 "st4", "st5", "st6", "st7",
66 "fctrl", "fstat", "ftag", "fiseg",
67 "fioff", "foseg", "fooff", "fop",
68 "xmm0", "xmm1", "xmm2", "xmm3",
69 "xmm4", "xmm5", "xmm6", "xmm7",
73 static const int i386_num_register_names = ARRAY_SIZE (i386_register_names);
75 /* Register names for MMX pseudo-registers. */
77 static char *i386_mmx_names[] =
79 "mm0", "mm1", "mm2", "mm3",
80 "mm4", "mm5", "mm6", "mm7"
83 static const int i386_num_mmx_regs = ARRAY_SIZE (i386_mmx_names);
86 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
88 int mm0_regnum = gdbarch_tdep (gdbarch)->mm0_regnum;
93 return (regnum >= mm0_regnum && regnum < mm0_regnum + i386_num_mmx_regs);
99 i386_sse_regnum_p (struct gdbarch *gdbarch, int regnum)
101 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
103 if (I387_NUM_XMM_REGS (tdep) == 0)
106 return (I387_XMM0_REGNUM (tdep) <= regnum
107 && regnum < I387_MXCSR_REGNUM (tdep));
111 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
113 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
115 if (I387_NUM_XMM_REGS (tdep) == 0)
118 return (regnum == I387_MXCSR_REGNUM (tdep));
124 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
126 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
128 if (I387_ST0_REGNUM (tdep) < 0)
131 return (I387_ST0_REGNUM (tdep) <= regnum
132 && regnum < I387_FCTRL_REGNUM (tdep));
136 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
138 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
140 if (I387_ST0_REGNUM (tdep) < 0)
143 return (I387_FCTRL_REGNUM (tdep) <= regnum
144 && regnum < I387_XMM0_REGNUM (tdep));
147 /* Return the name of register REGNUM. */
150 i386_register_name (struct gdbarch *gdbarch, int regnum)
152 if (i386_mmx_regnum_p (gdbarch, regnum))
153 return i386_mmx_names[regnum - I387_MM0_REGNUM (gdbarch_tdep (gdbarch))];
155 if (regnum >= 0 && regnum < i386_num_register_names)
156 return i386_register_names[regnum];
161 /* Convert a dbx register number REG to the appropriate register
162 number used by GDB. */
165 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
167 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
169 /* This implements what GCC calls the "default" register map
170 (dbx_register_map[]). */
172 if (reg >= 0 && reg <= 7)
174 /* General-purpose registers. The debug info calls %ebp
175 register 4, and %esp register 5. */
182 else if (reg >= 12 && reg <= 19)
184 /* Floating-point registers. */
185 return reg - 12 + I387_ST0_REGNUM (tdep);
187 else if (reg >= 21 && reg <= 28)
190 return reg - 21 + I387_XMM0_REGNUM (tdep);
192 else if (reg >= 29 && reg <= 36)
195 return reg - 29 + I387_MM0_REGNUM (tdep);
198 /* This will hopefully provoke a warning. */
199 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
202 /* Convert SVR4 register number REG to the appropriate register number
206 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
208 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
210 /* This implements the GCC register map that tries to be compatible
211 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
213 /* The SVR4 register numbering includes %eip and %eflags, and
214 numbers the floating point registers differently. */
215 if (reg >= 0 && reg <= 9)
217 /* General-purpose registers. */
220 else if (reg >= 11 && reg <= 18)
222 /* Floating-point registers. */
223 return reg - 11 + I387_ST0_REGNUM (tdep);
225 else if (reg >= 21 && reg <= 36)
227 /* The SSE and MMX registers have the same numbers as with dbx. */
228 return i386_dbx_reg_to_regnum (gdbarch, reg);
233 case 37: return I387_FCTRL_REGNUM (tdep);
234 case 38: return I387_FSTAT_REGNUM (tdep);
235 case 39: return I387_MXCSR_REGNUM (tdep);
236 case 40: return I386_ES_REGNUM;
237 case 41: return I386_CS_REGNUM;
238 case 42: return I386_SS_REGNUM;
239 case 43: return I386_DS_REGNUM;
240 case 44: return I386_FS_REGNUM;
241 case 45: return I386_GS_REGNUM;
244 /* This will hopefully provoke a warning. */
245 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
250 /* This is the variable that is set with "set disassembly-flavor", and
251 its legitimate values. */
252 static const char att_flavor[] = "att";
253 static const char intel_flavor[] = "intel";
254 static const char *valid_flavors[] =
260 static const char *disassembly_flavor = att_flavor;
263 /* Use the program counter to determine the contents and size of a
264 breakpoint instruction. Return a pointer to a string of bytes that
265 encode a breakpoint instruction, store the length of the string in
266 *LEN and optionally adjust *PC to point to the correct memory
267 location for inserting the breakpoint.
269 On the i386 we have a single breakpoint that fits in a single byte
270 and can be inserted anywhere.
272 This function is 64-bit safe. */
274 static const gdb_byte *
275 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
277 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */
279 *len = sizeof (break_insn);
283 /* Displaced instruction handling. */
285 /* Skip the legacy instruction prefixes in INSN.
286 Not all prefixes are valid for any particular insn
287 but we needn't care, the insn will fault if it's invalid.
288 The result is a pointer to the first opcode byte,
289 or NULL if we run off the end of the buffer. */
292 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
294 gdb_byte *end = insn + max_len;
300 case DATA_PREFIX_OPCODE:
301 case ADDR_PREFIX_OPCODE:
302 case CS_PREFIX_OPCODE:
303 case DS_PREFIX_OPCODE:
304 case ES_PREFIX_OPCODE:
305 case FS_PREFIX_OPCODE:
306 case GS_PREFIX_OPCODE:
307 case SS_PREFIX_OPCODE:
308 case LOCK_PREFIX_OPCODE:
309 case REPE_PREFIX_OPCODE:
310 case REPNE_PREFIX_OPCODE:
322 i386_absolute_jmp_p (const gdb_byte *insn)
324 /* jmp far (absolute address in operand) */
330 /* jump near, absolute indirect (/4) */
331 if ((insn[1] & 0x38) == 0x20)
334 /* jump far, absolute indirect (/5) */
335 if ((insn[1] & 0x38) == 0x28)
343 i386_absolute_call_p (const gdb_byte *insn)
345 /* call far, absolute */
351 /* Call near, absolute indirect (/2) */
352 if ((insn[1] & 0x38) == 0x10)
355 /* Call far, absolute indirect (/3) */
356 if ((insn[1] & 0x38) == 0x18)
364 i386_ret_p (const gdb_byte *insn)
368 case 0xc2: /* ret near, pop N bytes */
369 case 0xc3: /* ret near */
370 case 0xca: /* ret far, pop N bytes */
371 case 0xcb: /* ret far */
372 case 0xcf: /* iret */
381 i386_call_p (const gdb_byte *insn)
383 if (i386_absolute_call_p (insn))
386 /* call near, relative */
393 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
394 length in bytes. Otherwise, return zero. */
397 i386_syscall_p (const gdb_byte *insn, ULONGEST *lengthp)
408 /* Fix up the state of registers and memory after having single-stepped
409 a displaced instruction. */
412 i386_displaced_step_fixup (struct gdbarch *gdbarch,
413 struct displaced_step_closure *closure,
414 CORE_ADDR from, CORE_ADDR to,
415 struct regcache *regs)
417 /* The offset we applied to the instruction's address.
418 This could well be negative (when viewed as a signed 32-bit
419 value), but ULONGEST won't reflect that, so take care when
421 ULONGEST insn_offset = to - from;
423 /* Since we use simple_displaced_step_copy_insn, our closure is a
424 copy of the instruction. */
425 gdb_byte *insn = (gdb_byte *) closure;
426 /* The start of the insn, needed in case we see some prefixes. */
427 gdb_byte *insn_start = insn;
430 fprintf_unfiltered (gdb_stdlog,
431 "displaced: fixup (0x%s, 0x%s), "
432 "insn = 0x%02x 0x%02x ...\n",
433 paddr_nz (from), paddr_nz (to), insn[0], insn[1]);
435 /* The list of issues to contend with here is taken from
436 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
437 Yay for Free Software! */
439 /* Relocate the %eip, if necessary. */
441 /* The instruction recognizers we use assume any leading prefixes
442 have been skipped. */
444 /* This is the size of the buffer in closure. */
445 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
446 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
447 /* If there are too many prefixes, just ignore the insn.
448 It will fault when run. */
453 /* Except in the case of absolute or indirect jump or call
454 instructions, or a return instruction, the new eip is relative to
455 the displaced instruction; make it relative. Well, signal
456 handler returns don't need relocation either, but we use the
457 value of %eip to recognize those; see below. */
458 if (! i386_absolute_jmp_p (insn)
459 && ! i386_absolute_call_p (insn)
460 && ! i386_ret_p (insn))
465 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
467 /* A signal trampoline system call changes the %eip, resuming
468 execution of the main program after the signal handler has
469 returned. That makes them like 'return' instructions; we
470 shouldn't relocate %eip.
472 But most system calls don't, and we do need to relocate %eip.
474 Our heuristic for distinguishing these cases: if stepping
475 over the system call instruction left control directly after
476 the instruction, the we relocate --- control almost certainly
477 doesn't belong in the displaced copy. Otherwise, we assume
478 the instruction has put control where it belongs, and leave
479 it unrelocated. Goodness help us if there are PC-relative
481 if (i386_syscall_p (insn, &insn_len)
482 && orig_eip != to + (insn - insn_start) + insn_len)
485 fprintf_unfiltered (gdb_stdlog,
486 "displaced: syscall changed %%eip; "
491 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
493 /* If we just stepped over a breakpoint insn, we don't backup
494 the pc on purpose; this is to match behaviour without
497 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
500 fprintf_unfiltered (gdb_stdlog,
502 "relocated %%eip from 0x%s to 0x%s\n",
503 paddr_nz (orig_eip), paddr_nz (eip));
507 /* If the instruction was PUSHFL, then the TF bit will be set in the
508 pushed value, and should be cleared. We'll leave this for later,
509 since GDB already messes up the TF flag when stepping over a
512 /* If the instruction was a call, the return address now atop the
513 stack is the address following the copied instruction. We need
514 to make it the address following the original instruction. */
515 if (i386_call_p (insn))
519 const ULONGEST retaddr_len = 4;
521 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
522 retaddr = read_memory_unsigned_integer (esp, retaddr_len);
523 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
524 write_memory_unsigned_integer (esp, retaddr_len, retaddr);
527 fprintf_unfiltered (gdb_stdlog,
528 "displaced: relocated return addr at 0x%s "
535 #ifdef I386_REGNO_TO_SYMMETRY
536 #error "The Sequent Symmetry is no longer supported."
539 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
540 and %esp "belong" to the calling function. Therefore these
541 registers should be saved if they're going to be modified. */
543 /* The maximum number of saved registers. This should include all
544 registers mentioned above, and %eip. */
545 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
547 struct i386_frame_cache
554 /* Saved registers. */
555 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
560 /* Stack space reserved for local variables. */
564 /* Allocate and initialize a frame cache. */
566 static struct i386_frame_cache *
567 i386_alloc_frame_cache (void)
569 struct i386_frame_cache *cache;
572 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
576 cache->sp_offset = -4;
579 /* Saved registers. We initialize these to -1 since zero is a valid
580 offset (that's where %ebp is supposed to be stored). */
581 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
582 cache->saved_regs[i] = -1;
584 cache->saved_sp_reg = -1;
585 cache->pc_in_eax = 0;
587 /* Frameless until proven otherwise. */
593 /* If the instruction at PC is a jump, return the address of its
594 target. Otherwise, return PC. */
597 i386_follow_jump (CORE_ADDR pc)
603 target_read_memory (pc, &op, 1);
607 op = read_memory_unsigned_integer (pc + 1, 1);
613 /* Relative jump: if data16 == 0, disp32, else disp16. */
616 delta = read_memory_integer (pc + 2, 2);
618 /* Include the size of the jmp instruction (including the
624 delta = read_memory_integer (pc + 1, 4);
626 /* Include the size of the jmp instruction. */
631 /* Relative jump, disp8 (ignore data16). */
632 delta = read_memory_integer (pc + data16 + 1, 1);
641 /* Check whether PC points at a prologue for a function returning a
642 structure or union. If so, it updates CACHE and returns the
643 address of the first instruction after the code sequence that
644 removes the "hidden" argument from the stack or CURRENT_PC,
645 whichever is smaller. Otherwise, return PC. */
648 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
649 struct i386_frame_cache *cache)
651 /* Functions that return a structure or union start with:
654 xchgl %eax, (%esp) 0x87 0x04 0x24
655 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
657 (the System V compiler puts out the second `xchg' instruction,
658 and the assembler doesn't try to optimize it, so the 'sib' form
659 gets generated). This sequence is used to get the address of the
660 return buffer for a function that returns a structure. */
661 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
662 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
666 if (current_pc <= pc)
669 target_read_memory (pc, &op, 1);
671 if (op != 0x58) /* popl %eax */
674 target_read_memory (pc + 1, buf, 4);
675 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
678 if (current_pc == pc)
680 cache->sp_offset += 4;
684 if (current_pc == pc + 1)
686 cache->pc_in_eax = 1;
690 if (buf[1] == proto1[1])
697 i386_skip_probe (CORE_ADDR pc)
699 /* A function may start with
713 target_read_memory (pc, &op, 1);
715 if (op == 0x68 || op == 0x6a)
719 /* Skip past the `pushl' instruction; it has either a one-byte or a
720 four-byte operand, depending on the opcode. */
726 /* Read the following 8 bytes, which should be `call _probe' (6
727 bytes) followed by `addl $4,%esp' (2 bytes). */
728 read_memory (pc + delta, buf, sizeof (buf));
729 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
730 pc += delta + sizeof (buf);
736 /* GCC 4.1 and later, can put code in the prologue to realign the
737 stack pointer. Check whether PC points to such code, and update
738 CACHE accordingly. Return the first instruction after the code
739 sequence or CURRENT_PC, whichever is smaller. If we don't
740 recognize the code, return PC. */
743 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
744 struct i386_frame_cache *cache)
746 /* There are 2 code sequences to re-align stack before the frame
749 1. Use a caller-saved saved register:
755 2. Use a callee-saved saved register:
762 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
764 0x83 0xe4 0xf0 andl $-16, %esp
765 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
770 int offset, offset_and;
771 static int regnums[8] = {
772 I386_EAX_REGNUM, /* %eax */
773 I386_ECX_REGNUM, /* %ecx */
774 I386_EDX_REGNUM, /* %edx */
775 I386_EBX_REGNUM, /* %ebx */
776 I386_ESP_REGNUM, /* %esp */
777 I386_EBP_REGNUM, /* %ebp */
778 I386_ESI_REGNUM, /* %esi */
779 I386_EDI_REGNUM /* %edi */
782 if (target_read_memory (pc, buf, sizeof buf))
785 /* Check caller-saved saved register. The first instruction has
786 to be "leal 4(%esp), %reg". */
787 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
789 /* MOD must be binary 10 and R/M must be binary 100. */
790 if ((buf[1] & 0xc7) != 0x44)
793 /* REG has register number. */
794 reg = (buf[1] >> 3) & 7;
799 /* Check callee-saved saved register. The first instruction
800 has to be "pushl %reg". */
801 if ((buf[0] & 0xf8) != 0x50)
807 /* The next instruction has to be "leal 8(%esp), %reg". */
808 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
811 /* MOD must be binary 10 and R/M must be binary 100. */
812 if ((buf[2] & 0xc7) != 0x44)
815 /* REG has register number. Registers in pushl and leal have to
817 if (reg != ((buf[2] >> 3) & 7))
823 /* Rigister can't be %esp nor %ebp. */
824 if (reg == 4 || reg == 5)
827 /* The next instruction has to be "andl $-XXX, %esp". */
828 if (buf[offset + 1] != 0xe4
829 || (buf[offset] != 0x81 && buf[offset] != 0x83))
833 offset += buf[offset] == 0x81 ? 6 : 3;
835 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
836 0xfc. REG must be binary 110 and MOD must be binary 01. */
837 if (buf[offset] != 0xff
838 || buf[offset + 2] != 0xfc
839 || (buf[offset + 1] & 0xf8) != 0x70)
842 /* R/M has register. Registers in leal and pushl have to be the
844 if (reg != (buf[offset + 1] & 7))
847 if (current_pc > pc + offset_and)
848 cache->saved_sp_reg = regnums[reg];
850 return min (pc + offset + 3, current_pc);
853 /* Maximum instruction length we need to handle. */
854 #define I386_MAX_MATCHED_INSN_LEN 6
856 /* Instruction description. */
860 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
861 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
864 /* Search for the instruction at PC in the list SKIP_INSNS. Return
865 the first instruction description that matches. Otherwise, return
868 static struct i386_insn *
869 i386_match_insn (CORE_ADDR pc, struct i386_insn *skip_insns)
871 struct i386_insn *insn;
874 target_read_memory (pc, &op, 1);
876 for (insn = skip_insns; insn->len > 0; insn++)
878 if ((op & insn->mask[0]) == insn->insn[0])
880 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
881 int insn_matched = 1;
884 gdb_assert (insn->len > 1);
885 gdb_assert (insn->len <= I386_MAX_MATCHED_INSN_LEN);
887 target_read_memory (pc + 1, buf, insn->len - 1);
888 for (i = 1; i < insn->len; i++)
890 if ((buf[i - 1] & insn->mask[i]) != insn->insn[i])
902 /* Some special instructions that might be migrated by GCC into the
903 part of the prologue that sets up the new stack frame. Because the
904 stack frame hasn't been setup yet, no registers have been saved
905 yet, and only the scratch registers %eax, %ecx and %edx can be
908 struct i386_insn i386_frame_setup_skip_insns[] =
910 /* Check for `movb imm8, r' and `movl imm32, r'.
912 ??? Should we handle 16-bit operand-sizes here? */
914 /* `movb imm8, %al' and `movb imm8, %ah' */
915 /* `movb imm8, %cl' and `movb imm8, %ch' */
916 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
917 /* `movb imm8, %dl' and `movb imm8, %dh' */
918 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
919 /* `movl imm32, %eax' and `movl imm32, %ecx' */
920 { 5, { 0xb8 }, { 0xfe } },
921 /* `movl imm32, %edx' */
922 { 5, { 0xba }, { 0xff } },
924 /* Check for `mov imm32, r32'. Note that there is an alternative
925 encoding for `mov m32, %eax'.
927 ??? Should we handle SIB adressing here?
928 ??? Should we handle 16-bit operand-sizes here? */
930 /* `movl m32, %eax' */
931 { 5, { 0xa1 }, { 0xff } },
932 /* `movl m32, %eax' and `mov; m32, %ecx' */
933 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
934 /* `movl m32, %edx' */
935 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
937 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
938 Because of the symmetry, there are actually two ways to encode
939 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
940 opcode bytes 0x31 and 0x33 for `xorl'. */
942 /* `subl %eax, %eax' */
943 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
944 /* `subl %ecx, %ecx' */
945 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
946 /* `subl %edx, %edx' */
947 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
948 /* `xorl %eax, %eax' */
949 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
950 /* `xorl %ecx, %ecx' */
951 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
952 /* `xorl %edx, %edx' */
953 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
958 /* Check whether PC points to a no-op instruction. */
960 i386_skip_noop (CORE_ADDR pc)
965 target_read_memory (pc, &op, 1);
970 /* Ignore `nop' instruction. */
974 target_read_memory (pc, &op, 1);
977 /* Ignore no-op instruction `mov %edi, %edi'.
978 Microsoft system dlls often start with
979 a `mov %edi,%edi' instruction.
980 The 5 bytes before the function start are
981 filled with `nop' instructions.
982 This pattern can be used for hot-patching:
983 The `mov %edi, %edi' instruction can be replaced by a
984 near jump to the location of the 5 `nop' instructions
985 which can be replaced by a 32-bit jump to anywhere
986 in the 32-bit address space. */
990 target_read_memory (pc + 1, &op, 1);
994 target_read_memory (pc, &op, 1);
1002 /* Check whether PC points at a code that sets up a new stack frame.
1003 If so, it updates CACHE and returns the address of the first
1004 instruction after the sequence that sets up the frame or LIMIT,
1005 whichever is smaller. If we don't recognize the code, return PC. */
1008 i386_analyze_frame_setup (CORE_ADDR pc, CORE_ADDR limit,
1009 struct i386_frame_cache *cache)
1011 struct i386_insn *insn;
1018 target_read_memory (pc, &op, 1);
1020 if (op == 0x55) /* pushl %ebp */
1022 /* Take into account that we've executed the `pushl %ebp' that
1023 starts this instruction sequence. */
1024 cache->saved_regs[I386_EBP_REGNUM] = 0;
1025 cache->sp_offset += 4;
1028 /* If that's all, return now. */
1032 /* Check for some special instructions that might be migrated by
1033 GCC into the prologue and skip them. At this point in the
1034 prologue, code should only touch the scratch registers %eax,
1035 %ecx and %edx, so while the number of posibilities is sheer,
1038 Make sure we only skip these instructions if we later see the
1039 `movl %esp, %ebp' that actually sets up the frame. */
1040 while (pc + skip < limit)
1042 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1049 /* If that's all, return now. */
1050 if (limit <= pc + skip)
1053 target_read_memory (pc + skip, &op, 1);
1055 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1059 if (read_memory_unsigned_integer (pc + skip + 1, 1) != 0xec)
1063 if (read_memory_unsigned_integer (pc + skip + 1, 1) != 0xe5)
1070 /* OK, we actually have a frame. We just don't know how large
1071 it is yet. Set its size to zero. We'll adjust it if
1072 necessary. We also now commit to skipping the special
1073 instructions mentioned before. */
1077 /* If that's all, return now. */
1081 /* Check for stack adjustment
1085 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1086 reg, so we don't have to worry about a data16 prefix. */
1087 target_read_memory (pc, &op, 1);
1090 /* `subl' with 8-bit immediate. */
1091 if (read_memory_unsigned_integer (pc + 1, 1) != 0xec)
1092 /* Some instruction starting with 0x83 other than `subl'. */
1095 /* `subl' with signed 8-bit immediate (though it wouldn't
1096 make sense to be negative). */
1097 cache->locals = read_memory_integer (pc + 2, 1);
1100 else if (op == 0x81)
1102 /* Maybe it is `subl' with a 32-bit immediate. */
1103 if (read_memory_unsigned_integer (pc + 1, 1) != 0xec)
1104 /* Some instruction starting with 0x81 other than `subl'. */
1107 /* It is `subl' with a 32-bit immediate. */
1108 cache->locals = read_memory_integer (pc + 2, 4);
1113 /* Some instruction other than `subl'. */
1117 else if (op == 0xc8) /* enter */
1119 cache->locals = read_memory_unsigned_integer (pc + 1, 2);
1126 /* Check whether PC points at code that saves registers on the stack.
1127 If so, it updates CACHE and returns the address of the first
1128 instruction after the register saves or CURRENT_PC, whichever is
1129 smaller. Otherwise, return PC. */
1132 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1133 struct i386_frame_cache *cache)
1135 CORE_ADDR offset = 0;
1139 if (cache->locals > 0)
1140 offset -= cache->locals;
1141 for (i = 0; i < 8 && pc < current_pc; i++)
1143 target_read_memory (pc, &op, 1);
1144 if (op < 0x50 || op > 0x57)
1148 cache->saved_regs[op - 0x50] = offset;
1149 cache->sp_offset += 4;
1156 /* Do a full analysis of the prologue at PC and update CACHE
1157 accordingly. Bail out early if CURRENT_PC is reached. Return the
1158 address where the analysis stopped.
1160 We handle these cases:
1162 The startup sequence can be at the start of the function, or the
1163 function can start with a branch to startup code at the end.
1165 %ebp can be set up with either the 'enter' instruction, or "pushl
1166 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1167 once used in the System V compiler).
1169 Local space is allocated just below the saved %ebp by either the
1170 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1171 16-bit unsigned argument for space to allocate, and the 'addl'
1172 instruction could have either a signed byte, or 32-bit immediate.
1174 Next, the registers used by this function are pushed. With the
1175 System V compiler they will always be in the order: %edi, %esi,
1176 %ebx (and sometimes a harmless bug causes it to also save but not
1177 restore %eax); however, the code below is willing to see the pushes
1178 in any order, and will handle up to 8 of them.
1180 If the setup sequence is at the end of the function, then the next
1181 instruction will be a branch back to the start. */
1184 i386_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
1185 struct i386_frame_cache *cache)
1187 pc = i386_skip_noop (pc);
1188 pc = i386_follow_jump (pc);
1189 pc = i386_analyze_struct_return (pc, current_pc, cache);
1190 pc = i386_skip_probe (pc);
1191 pc = i386_analyze_stack_align (pc, current_pc, cache);
1192 pc = i386_analyze_frame_setup (pc, current_pc, cache);
1193 return i386_analyze_register_saves (pc, current_pc, cache);
1196 /* Return PC of first real instruction. */
1199 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1201 static gdb_byte pic_pat[6] =
1203 0xe8, 0, 0, 0, 0, /* call 0x0 */
1204 0x5b, /* popl %ebx */
1206 struct i386_frame_cache cache;
1212 pc = i386_analyze_prologue (start_pc, 0xffffffff, &cache);
1213 if (cache.locals < 0)
1216 /* Found valid frame setup. */
1218 /* The native cc on SVR4 in -K PIC mode inserts the following code
1219 to get the address of the global offset table (GOT) into register
1224 movl %ebx,x(%ebp) (optional)
1227 This code is with the rest of the prologue (at the end of the
1228 function), so we have to skip it to get to the first real
1229 instruction at the start of the function. */
1231 for (i = 0; i < 6; i++)
1233 target_read_memory (pc + i, &op, 1);
1234 if (pic_pat[i] != op)
1241 target_read_memory (pc + delta, &op, 1);
1243 if (op == 0x89) /* movl %ebx, x(%ebp) */
1245 op = read_memory_unsigned_integer (pc + delta + 1, 1);
1247 if (op == 0x5d) /* One byte offset from %ebp. */
1249 else if (op == 0x9d) /* Four byte offset from %ebp. */
1251 else /* Unexpected instruction. */
1254 target_read_memory (pc + delta, &op, 1);
1258 if (delta > 0 && op == 0x81
1259 && read_memory_unsigned_integer (pc + delta + 1, 1) == 0xc3)
1265 /* If the function starts with a branch (to startup code at the end)
1266 the last instruction should bring us back to the first
1267 instruction of the real code. */
1268 if (i386_follow_jump (start_pc) != start_pc)
1269 pc = i386_follow_jump (pc);
1274 /* Check that the code pointed to by PC corresponds to a call to
1275 __main, skip it if so. Return PC otherwise. */
1278 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1282 target_read_memory (pc, &op, 1);
1287 if (target_read_memory (pc + 1, buf, sizeof buf) == 0)
1289 /* Make sure address is computed correctly as a 32bit
1290 integer even if CORE_ADDR is 64 bit wide. */
1291 struct minimal_symbol *s;
1292 CORE_ADDR call_dest = pc + 5 + extract_signed_integer (buf, 4);
1294 call_dest = call_dest & 0xffffffffU;
1295 s = lookup_minimal_symbol_by_pc (call_dest);
1297 && SYMBOL_LINKAGE_NAME (s) != NULL
1298 && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0)
1306 /* This function is 64-bit safe. */
1309 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1313 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1314 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1318 /* Normal frames. */
1320 static struct i386_frame_cache *
1321 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
1323 struct i386_frame_cache *cache;
1330 cache = i386_alloc_frame_cache ();
1331 *this_cache = cache;
1333 /* In principle, for normal frames, %ebp holds the frame pointer,
1334 which holds the base address for the current stack frame.
1335 However, for functions that don't need it, the frame pointer is
1336 optional. For these "frameless" functions the frame pointer is
1337 actually the frame pointer of the calling frame. Signal
1338 trampolines are just a special case of a "frameless" function.
1339 They (usually) share their frame pointer with the frame that was
1340 in progress when the signal occurred. */
1342 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1343 cache->base = extract_unsigned_integer (buf, 4);
1344 if (cache->base == 0)
1347 /* For normal frames, %eip is stored at 4(%ebp). */
1348 cache->saved_regs[I386_EIP_REGNUM] = 4;
1350 cache->pc = get_frame_func (this_frame);
1352 i386_analyze_prologue (cache->pc, get_frame_pc (this_frame), cache);
1354 if (cache->saved_sp_reg != -1)
1356 /* Saved stack pointer has been saved. */
1357 get_frame_register (this_frame, cache->saved_sp_reg, buf);
1358 cache->saved_sp = extract_unsigned_integer(buf, 4);
1361 if (cache->locals < 0)
1363 /* We didn't find a valid frame, which means that CACHE->base
1364 currently holds the frame pointer for our calling frame. If
1365 we're at the start of a function, or somewhere half-way its
1366 prologue, the function's frame probably hasn't been fully
1367 setup yet. Try to reconstruct the base address for the stack
1368 frame by looking at the stack pointer. For truly "frameless"
1369 functions this might work too. */
1371 if (cache->saved_sp_reg != -1)
1373 /* We're halfway aligning the stack. */
1374 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
1375 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
1377 /* This will be added back below. */
1378 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
1382 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1383 cache->base = extract_unsigned_integer (buf, 4) + cache->sp_offset;
1387 /* Now that we have the base address for the stack frame we can
1388 calculate the value of %esp in the calling frame. */
1389 if (cache->saved_sp == 0)
1390 cache->saved_sp = cache->base + 8;
1392 /* Adjust all the saved registers such that they contain addresses
1393 instead of offsets. */
1394 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1395 if (cache->saved_regs[i] != -1)
1396 cache->saved_regs[i] += cache->base;
1402 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
1403 struct frame_id *this_id)
1405 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1407 /* This marks the outermost frame. */
1408 if (cache->base == 0)
1411 /* See the end of i386_push_dummy_call. */
1412 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
1415 static struct value *
1416 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
1419 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1421 gdb_assert (regnum >= 0);
1423 /* The System V ABI says that:
1425 "The flags register contains the system flags, such as the
1426 direction flag and the carry flag. The direction flag must be
1427 set to the forward (that is, zero) direction before entry and
1428 upon exit from a function. Other user flags have no specified
1429 role in the standard calling sequence and are not preserved."
1431 To guarantee the "upon exit" part of that statement we fake a
1432 saved flags register that has its direction flag cleared.
1434 Note that GCC doesn't seem to rely on the fact that the direction
1435 flag is cleared after a function return; it always explicitly
1436 clears the flag before operations where it matters.
1438 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1439 right thing to do. The way we fake the flags register here makes
1440 it impossible to change it. */
1442 if (regnum == I386_EFLAGS_REGNUM)
1446 val = get_frame_register_unsigned (this_frame, regnum);
1448 return frame_unwind_got_constant (this_frame, regnum, val);
1451 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
1452 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
1454 if (regnum == I386_ESP_REGNUM && cache->saved_sp)
1455 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
1457 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
1458 return frame_unwind_got_memory (this_frame, regnum,
1459 cache->saved_regs[regnum]);
1461 return frame_unwind_got_register (this_frame, regnum, regnum);
1464 static const struct frame_unwind i386_frame_unwind =
1468 i386_frame_prev_register,
1470 default_frame_sniffer
1474 /* Signal trampolines. */
1476 static struct i386_frame_cache *
1477 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
1479 struct i386_frame_cache *cache;
1480 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
1487 cache = i386_alloc_frame_cache ();
1489 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1490 cache->base = extract_unsigned_integer (buf, 4) - 4;
1492 addr = tdep->sigcontext_addr (this_frame);
1493 if (tdep->sc_reg_offset)
1497 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
1499 for (i = 0; i < tdep->sc_num_regs; i++)
1500 if (tdep->sc_reg_offset[i] != -1)
1501 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
1505 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
1506 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
1509 *this_cache = cache;
1514 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
1515 struct frame_id *this_id)
1517 struct i386_frame_cache *cache =
1518 i386_sigtramp_frame_cache (this_frame, this_cache);
1520 /* See the end of i386_push_dummy_call. */
1521 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
1524 static struct value *
1525 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
1526 void **this_cache, int regnum)
1528 /* Make sure we've initialized the cache. */
1529 i386_sigtramp_frame_cache (this_frame, this_cache);
1531 return i386_frame_prev_register (this_frame, this_cache, regnum);
1535 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
1536 struct frame_info *this_frame,
1537 void **this_prologue_cache)
1539 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
1541 /* We shouldn't even bother if we don't have a sigcontext_addr
1543 if (tdep->sigcontext_addr == NULL)
1546 if (tdep->sigtramp_p != NULL)
1548 if (tdep->sigtramp_p (this_frame))
1552 if (tdep->sigtramp_start != 0)
1554 CORE_ADDR pc = get_frame_pc (this_frame);
1556 gdb_assert (tdep->sigtramp_end != 0);
1557 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
1564 static const struct frame_unwind i386_sigtramp_frame_unwind =
1567 i386_sigtramp_frame_this_id,
1568 i386_sigtramp_frame_prev_register,
1570 i386_sigtramp_frame_sniffer
1575 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
1577 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1582 static const struct frame_base i386_frame_base =
1585 i386_frame_base_address,
1586 i386_frame_base_address,
1587 i386_frame_base_address
1590 static struct frame_id
1591 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1595 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
1597 /* See the end of i386_push_dummy_call. */
1598 return frame_id_build (fp + 8, get_frame_pc (this_frame));
1602 /* Figure out where the longjmp will land. Slurp the args out of the
1603 stack. We expect the first arg to be a pointer to the jmp_buf
1604 structure from which we extract the address that we will land at.
1605 This address is copied into PC. This routine returns non-zero on
1609 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1612 CORE_ADDR sp, jb_addr;
1613 struct gdbarch *gdbarch = get_frame_arch (frame);
1614 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
1616 /* If JB_PC_OFFSET is -1, we have no way to find out where the
1617 longjmp will land. */
1618 if (jb_pc_offset == -1)
1621 get_frame_register (frame, I386_ESP_REGNUM, buf);
1622 sp = extract_unsigned_integer (buf, 4);
1623 if (target_read_memory (sp + 4, buf, 4))
1626 jb_addr = extract_unsigned_integer (buf, 4);
1627 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
1630 *pc = extract_unsigned_integer (buf, 4);
1635 /* Check whether TYPE must be 16-byte-aligned when passed as a
1636 function argument. 16-byte vectors, _Decimal128 and structures or
1637 unions containing such types must be 16-byte-aligned; other
1638 arguments are 4-byte-aligned. */
1641 i386_16_byte_align_p (struct type *type)
1643 type = check_typedef (type);
1644 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
1645 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
1646 && TYPE_LENGTH (type) == 16)
1648 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
1649 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
1650 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1651 || TYPE_CODE (type) == TYPE_CODE_UNION)
1654 for (i = 0; i < TYPE_NFIELDS (type); i++)
1656 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
1664 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1665 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
1666 struct value **args, CORE_ADDR sp, int struct_return,
1667 CORE_ADDR struct_addr)
1674 /* Determine the total space required for arguments and struct
1675 return address in a first pass (allowing for 16-byte-aligned
1676 arguments), then push arguments in a second pass. */
1678 for (write_pass = 0; write_pass < 2; write_pass++)
1680 int args_space_used = 0;
1681 int have_16_byte_aligned_arg = 0;
1687 /* Push value address. */
1688 store_unsigned_integer (buf, 4, struct_addr);
1689 write_memory (sp, buf, 4);
1690 args_space_used += 4;
1696 for (i = 0; i < nargs; i++)
1698 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
1702 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
1703 args_space_used = align_up (args_space_used, 16);
1705 write_memory (sp + args_space_used,
1706 value_contents_all (args[i]), len);
1707 /* The System V ABI says that:
1709 "An argument's size is increased, if necessary, to make it a
1710 multiple of [32-bit] words. This may require tail padding,
1711 depending on the size of the argument."
1713 This makes sure the stack stays word-aligned. */
1714 args_space_used += align_up (len, 4);
1718 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
1720 args_space = align_up (args_space, 16);
1721 have_16_byte_aligned_arg = 1;
1723 args_space += align_up (len, 4);
1729 if (have_16_byte_aligned_arg)
1730 args_space = align_up (args_space, 16);
1735 /* Store return address. */
1737 store_unsigned_integer (buf, 4, bp_addr);
1738 write_memory (sp, buf, 4);
1740 /* Finally, update the stack pointer... */
1741 store_unsigned_integer (buf, 4, sp);
1742 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
1744 /* ...and fake a frame pointer. */
1745 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
1747 /* MarkK wrote: This "+ 8" is all over the place:
1748 (i386_frame_this_id, i386_sigtramp_frame_this_id,
1749 i386_dummy_id). It's there, since all frame unwinders for
1750 a given target have to agree (within a certain margin) on the
1751 definition of the stack address of a frame. Otherwise frame id
1752 comparison might not work correctly. Since DWARF2/GCC uses the
1753 stack address *before* the function call as a frame's CFA. On
1754 the i386, when %ebp is used as a frame pointer, the offset
1755 between the contents %ebp and the CFA as defined by GCC. */
1759 /* These registers are used for returning integers (and on some
1760 targets also for returning `struct' and `union' values when their
1761 size and alignment match an integer type). */
1762 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
1763 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
1765 /* Read, for architecture GDBARCH, a function return value of TYPE
1766 from REGCACHE, and copy that into VALBUF. */
1769 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
1770 struct regcache *regcache, gdb_byte *valbuf)
1772 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1773 int len = TYPE_LENGTH (type);
1774 gdb_byte buf[I386_MAX_REGISTER_SIZE];
1776 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1778 if (tdep->st0_regnum < 0)
1780 warning (_("Cannot find floating-point return value."));
1781 memset (valbuf, 0, len);
1785 /* Floating-point return values can be found in %st(0). Convert
1786 its contents to the desired type. This is probably not
1787 exactly how it would happen on the target itself, but it is
1788 the best we can do. */
1789 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
1790 convert_typed_floating (buf, builtin_type_i387_ext, valbuf, type);
1794 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
1795 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
1797 if (len <= low_size)
1799 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
1800 memcpy (valbuf, buf, len);
1802 else if (len <= (low_size + high_size))
1804 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
1805 memcpy (valbuf, buf, low_size);
1806 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
1807 memcpy (valbuf + low_size, buf, len - low_size);
1810 internal_error (__FILE__, __LINE__,
1811 _("Cannot extract return value of %d bytes long."), len);
1815 /* Write, for architecture GDBARCH, a function return value of TYPE
1816 from VALBUF into REGCACHE. */
1819 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
1820 struct regcache *regcache, const gdb_byte *valbuf)
1822 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1823 int len = TYPE_LENGTH (type);
1825 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1828 gdb_byte buf[I386_MAX_REGISTER_SIZE];
1830 if (tdep->st0_regnum < 0)
1832 warning (_("Cannot set floating-point return value."));
1836 /* Returning floating-point values is a bit tricky. Apart from
1837 storing the return value in %st(0), we have to simulate the
1838 state of the FPU at function return point. */
1840 /* Convert the value found in VALBUF to the extended
1841 floating-point format used by the FPU. This is probably
1842 not exactly how it would happen on the target itself, but
1843 it is the best we can do. */
1844 convert_typed_floating (valbuf, type, buf, builtin_type_i387_ext);
1845 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
1847 /* Set the top of the floating-point register stack to 7. The
1848 actual value doesn't really matter, but 7 is what a normal
1849 function return would end up with if the program started out
1850 with a freshly initialized FPU. */
1851 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
1853 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
1855 /* Mark %st(1) through %st(7) as empty. Since we set the top of
1856 the floating-point register stack to 7, the appropriate value
1857 for the tag word is 0x3fff. */
1858 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
1862 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
1863 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
1865 if (len <= low_size)
1866 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
1867 else if (len <= (low_size + high_size))
1869 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
1870 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
1871 len - low_size, valbuf + low_size);
1874 internal_error (__FILE__, __LINE__,
1875 _("Cannot store return value of %d bytes long."), len);
1880 /* This is the variable that is set with "set struct-convention", and
1881 its legitimate values. */
1882 static const char default_struct_convention[] = "default";
1883 static const char pcc_struct_convention[] = "pcc";
1884 static const char reg_struct_convention[] = "reg";
1885 static const char *valid_conventions[] =
1887 default_struct_convention,
1888 pcc_struct_convention,
1889 reg_struct_convention,
1892 static const char *struct_convention = default_struct_convention;
1894 /* Return non-zero if TYPE, which is assumed to be a structure,
1895 a union type, or an array type, should be returned in registers
1896 for architecture GDBARCH. */
1899 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
1901 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1902 enum type_code code = TYPE_CODE (type);
1903 int len = TYPE_LENGTH (type);
1905 gdb_assert (code == TYPE_CODE_STRUCT
1906 || code == TYPE_CODE_UNION
1907 || code == TYPE_CODE_ARRAY);
1909 if (struct_convention == pcc_struct_convention
1910 || (struct_convention == default_struct_convention
1911 && tdep->struct_return == pcc_struct_return))
1914 /* Structures consisting of a single `float', `double' or 'long
1915 double' member are returned in %st(0). */
1916 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
1918 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
1919 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1920 return (len == 4 || len == 8 || len == 12);
1923 return (len == 1 || len == 2 || len == 4 || len == 8);
1926 /* Determine, for architecture GDBARCH, how a return value of TYPE
1927 should be returned. If it is supposed to be returned in registers,
1928 and READBUF is non-zero, read the appropriate value from REGCACHE,
1929 and copy it into READBUF. If WRITEBUF is non-zero, write the value
1930 from WRITEBUF into REGCACHE. */
1932 static enum return_value_convention
1933 i386_return_value (struct gdbarch *gdbarch, struct type *func_type,
1934 struct type *type, struct regcache *regcache,
1935 gdb_byte *readbuf, const gdb_byte *writebuf)
1937 enum type_code code = TYPE_CODE (type);
1939 if (((code == TYPE_CODE_STRUCT
1940 || code == TYPE_CODE_UNION
1941 || code == TYPE_CODE_ARRAY)
1942 && !i386_reg_struct_return_p (gdbarch, type))
1943 /* 128-bit decimal float uses the struct return convention. */
1944 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
1946 /* The System V ABI says that:
1948 "A function that returns a structure or union also sets %eax
1949 to the value of the original address of the caller's area
1950 before it returns. Thus when the caller receives control
1951 again, the address of the returned object resides in register
1952 %eax and can be used to access the object."
1954 So the ABI guarantees that we can always find the return
1955 value just after the function has returned. */
1957 /* Note that the ABI doesn't mention functions returning arrays,
1958 which is something possible in certain languages such as Ada.
1959 In this case, the value is returned as if it was wrapped in
1960 a record, so the convention applied to records also applies
1967 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
1968 read_memory (addr, readbuf, TYPE_LENGTH (type));
1971 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
1974 /* This special case is for structures consisting of a single
1975 `float', `double' or 'long double' member. These structures are
1976 returned in %st(0). For these structures, we call ourselves
1977 recursively, changing TYPE into the type of the first member of
1978 the structure. Since that should work for all structures that
1979 have only one member, we don't bother to check the member's type
1981 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
1983 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
1984 return i386_return_value (gdbarch, func_type, type, regcache,
1989 i386_extract_return_value (gdbarch, type, regcache, readbuf);
1991 i386_store_return_value (gdbarch, type, regcache, writebuf);
1993 return RETURN_VALUE_REGISTER_CONVENTION;
1997 /* Type for %eflags. */
1998 struct type *i386_eflags_type;
2000 /* Type for %mxcsr. */
2001 struct type *i386_mxcsr_type;
2003 /* Construct types for ISA-specific registers. */
2005 i386_init_types (void)
2009 type = init_flags_type ("builtin_type_i386_eflags", 4);
2010 append_flags_type_flag (type, 0, "CF");
2011 append_flags_type_flag (type, 1, NULL);
2012 append_flags_type_flag (type, 2, "PF");
2013 append_flags_type_flag (type, 4, "AF");
2014 append_flags_type_flag (type, 6, "ZF");
2015 append_flags_type_flag (type, 7, "SF");
2016 append_flags_type_flag (type, 8, "TF");
2017 append_flags_type_flag (type, 9, "IF");
2018 append_flags_type_flag (type, 10, "DF");
2019 append_flags_type_flag (type, 11, "OF");
2020 append_flags_type_flag (type, 14, "NT");
2021 append_flags_type_flag (type, 16, "RF");
2022 append_flags_type_flag (type, 17, "VM");
2023 append_flags_type_flag (type, 18, "AC");
2024 append_flags_type_flag (type, 19, "VIF");
2025 append_flags_type_flag (type, 20, "VIP");
2026 append_flags_type_flag (type, 21, "ID");
2027 i386_eflags_type = type;
2029 type = init_flags_type ("builtin_type_i386_mxcsr", 4);
2030 append_flags_type_flag (type, 0, "IE");
2031 append_flags_type_flag (type, 1, "DE");
2032 append_flags_type_flag (type, 2, "ZE");
2033 append_flags_type_flag (type, 3, "OE");
2034 append_flags_type_flag (type, 4, "UE");
2035 append_flags_type_flag (type, 5, "PE");
2036 append_flags_type_flag (type, 6, "DAZ");
2037 append_flags_type_flag (type, 7, "IM");
2038 append_flags_type_flag (type, 8, "DM");
2039 append_flags_type_flag (type, 9, "ZM");
2040 append_flags_type_flag (type, 10, "OM");
2041 append_flags_type_flag (type, 11, "UM");
2042 append_flags_type_flag (type, 12, "PM");
2043 append_flags_type_flag (type, 15, "FZ");
2044 i386_mxcsr_type = type;
2047 /* Construct vector type for MMX registers. */
2049 i386_mmx_type (struct gdbarch *gdbarch)
2051 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2053 if (!tdep->i386_mmx_type)
2055 /* The type we're building is this: */
2057 union __gdb_builtin_type_vec64i
2060 int32_t v2_int32[2];
2061 int16_t v4_int16[4];
2068 t = init_composite_type ("__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
2069 append_composite_type_field (t, "uint64", builtin_type_int64);
2070 append_composite_type_field (t, "v2_int32",
2071 init_vector_type (builtin_type_int32, 2));
2072 append_composite_type_field (t, "v4_int16",
2073 init_vector_type (builtin_type_int16, 4));
2074 append_composite_type_field (t, "v8_int8",
2075 init_vector_type (builtin_type_int8, 8));
2077 TYPE_VECTOR (t) = 1;
2078 TYPE_NAME (t) = "builtin_type_vec64i";
2079 tdep->i386_mmx_type = t;
2082 return tdep->i386_mmx_type;
2086 i386_sse_type (struct gdbarch *gdbarch)
2088 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2090 if (!tdep->i386_sse_type)
2092 /* The type we're building is this: */
2094 union __gdb_builtin_type_vec128i
2097 int64_t v2_int64[2];
2098 int32_t v4_int32[4];
2099 int16_t v8_int16[8];
2100 int8_t v16_int8[16];
2101 double v2_double[2];
2108 t = init_composite_type ("__gdb_builtin_type_vec128i", TYPE_CODE_UNION);
2109 append_composite_type_field (t, "v4_float",
2110 init_vector_type (builtin_type (gdbarch)
2111 ->builtin_float, 4));
2112 append_composite_type_field (t, "v2_double",
2113 init_vector_type (builtin_type (gdbarch)
2114 ->builtin_double, 2));
2115 append_composite_type_field (t, "v16_int8",
2116 init_vector_type (builtin_type_int8, 16));
2117 append_composite_type_field (t, "v8_int16",
2118 init_vector_type (builtin_type_int16, 8));
2119 append_composite_type_field (t, "v4_int32",
2120 init_vector_type (builtin_type_int32, 4));
2121 append_composite_type_field (t, "v2_int64",
2122 init_vector_type (builtin_type_int64, 2));
2123 append_composite_type_field (t, "uint128", builtin_type_int128);
2125 TYPE_VECTOR (t) = 1;
2126 TYPE_NAME (t) = "builtin_type_vec128i";
2127 tdep->i386_sse_type = t;
2130 return tdep->i386_sse_type;
2133 /* Return the GDB type object for the "standard" data type of data in
2134 register REGNUM. Perhaps %esi and %edi should go here, but
2135 potentially they could be used for things other than address. */
2137 static struct type *
2138 i386_register_type (struct gdbarch *gdbarch, int regnum)
2140 if (regnum == I386_EIP_REGNUM)
2141 return builtin_type (gdbarch)->builtin_func_ptr;
2143 if (regnum == I386_EFLAGS_REGNUM)
2144 return i386_eflags_type;
2146 if (regnum == I386_EBP_REGNUM || regnum == I386_ESP_REGNUM)
2147 return builtin_type (gdbarch)->builtin_data_ptr;
2149 if (i386_fp_regnum_p (gdbarch, regnum))
2150 return builtin_type_i387_ext;
2152 if (i386_mmx_regnum_p (gdbarch, regnum))
2153 return i386_mmx_type (gdbarch);
2155 if (i386_sse_regnum_p (gdbarch, regnum))
2156 return i386_sse_type (gdbarch);
2158 if (regnum == I387_MXCSR_REGNUM (gdbarch_tdep (gdbarch)))
2159 return i386_mxcsr_type;
2161 return builtin_type (gdbarch)->builtin_int;
2164 /* Map a cooked register onto a raw register or memory. For the i386,
2165 the MMX registers need to be mapped onto floating point registers. */
2168 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
2170 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
2175 mmxreg = regnum - tdep->mm0_regnum;
2176 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2177 tos = (fstat >> 11) & 0x7;
2178 fpreg = (mmxreg + tos) % 8;
2180 return (I387_ST0_REGNUM (tdep) + fpreg);
2184 i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2185 int regnum, gdb_byte *buf)
2187 if (i386_mmx_regnum_p (gdbarch, regnum))
2189 gdb_byte mmx_buf[MAX_REGISTER_SIZE];
2190 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2192 /* Extract (always little endian). */
2193 regcache_raw_read (regcache, fpnum, mmx_buf);
2194 memcpy (buf, mmx_buf, register_size (gdbarch, regnum));
2197 regcache_raw_read (regcache, regnum, buf);
2201 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2202 int regnum, const gdb_byte *buf)
2204 if (i386_mmx_regnum_p (gdbarch, regnum))
2206 gdb_byte mmx_buf[MAX_REGISTER_SIZE];
2207 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2210 regcache_raw_read (regcache, fpnum, mmx_buf);
2211 /* ... Modify ... (always little endian). */
2212 memcpy (mmx_buf, buf, register_size (gdbarch, regnum));
2214 regcache_raw_write (regcache, fpnum, mmx_buf);
2217 regcache_raw_write (regcache, regnum, buf);
2221 /* Return the register number of the register allocated by GCC after
2222 REGNUM, or -1 if there is no such register. */
2225 i386_next_regnum (int regnum)
2227 /* GCC allocates the registers in the order:
2229 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2231 Since storing a variable in %esp doesn't make any sense we return
2232 -1 for %ebp and for %esp itself. */
2233 static int next_regnum[] =
2235 I386_EDX_REGNUM, /* Slot for %eax. */
2236 I386_EBX_REGNUM, /* Slot for %ecx. */
2237 I386_ECX_REGNUM, /* Slot for %edx. */
2238 I386_ESI_REGNUM, /* Slot for %ebx. */
2239 -1, -1, /* Slots for %esp and %ebp. */
2240 I386_EDI_REGNUM, /* Slot for %esi. */
2241 I386_EBP_REGNUM /* Slot for %edi. */
2244 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
2245 return next_regnum[regnum];
2250 /* Return nonzero if a value of type TYPE stored in register REGNUM
2251 needs any special handling. */
2254 i386_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type)
2256 int len = TYPE_LENGTH (type);
2258 /* Values may be spread across multiple registers. Most debugging
2259 formats aren't expressive enough to specify the locations, so
2260 some heuristics is involved. Right now we only handle types that
2261 have a length that is a multiple of the word size, since GCC
2262 doesn't seem to put any other types into registers. */
2263 if (len > 4 && len % 4 == 0)
2265 int last_regnum = regnum;
2269 last_regnum = i386_next_regnum (last_regnum);
2273 if (last_regnum != -1)
2277 return i387_convert_register_p (gdbarch, regnum, type);
2280 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2281 return its contents in TO. */
2284 i386_register_to_value (struct frame_info *frame, int regnum,
2285 struct type *type, gdb_byte *to)
2287 struct gdbarch *gdbarch = get_frame_arch (frame);
2288 int len = TYPE_LENGTH (type);
2290 /* FIXME: kettenis/20030609: What should we do if REGNUM isn't
2291 available in FRAME (i.e. if it wasn't saved)? */
2293 if (i386_fp_regnum_p (gdbarch, regnum))
2295 i387_register_to_value (frame, regnum, type, to);
2299 /* Read a value spread across multiple registers. */
2301 gdb_assert (len > 4 && len % 4 == 0);
2305 gdb_assert (regnum != -1);
2306 gdb_assert (register_size (gdbarch, regnum) == 4);
2308 get_frame_register (frame, regnum, to);
2309 regnum = i386_next_regnum (regnum);
2315 /* Write the contents FROM of a value of type TYPE into register
2316 REGNUM in frame FRAME. */
2319 i386_value_to_register (struct frame_info *frame, int regnum,
2320 struct type *type, const gdb_byte *from)
2322 int len = TYPE_LENGTH (type);
2324 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
2326 i387_value_to_register (frame, regnum, type, from);
2330 /* Write a value spread across multiple registers. */
2332 gdb_assert (len > 4 && len % 4 == 0);
2336 gdb_assert (regnum != -1);
2337 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
2339 put_frame_register (frame, regnum, from);
2340 regnum = i386_next_regnum (regnum);
2346 /* Supply register REGNUM from the buffer specified by GREGS and LEN
2347 in the general-purpose register set REGSET to register cache
2348 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2351 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
2352 int regnum, const void *gregs, size_t len)
2354 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2355 const gdb_byte *regs = gregs;
2358 gdb_assert (len == tdep->sizeof_gregset);
2360 for (i = 0; i < tdep->gregset_num_regs; i++)
2362 if ((regnum == i || regnum == -1)
2363 && tdep->gregset_reg_offset[i] != -1)
2364 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
2368 /* Collect register REGNUM from the register cache REGCACHE and store
2369 it in the buffer specified by GREGS and LEN as described by the
2370 general-purpose register set REGSET. If REGNUM is -1, do this for
2371 all registers in REGSET. */
2374 i386_collect_gregset (const struct regset *regset,
2375 const struct regcache *regcache,
2376 int regnum, void *gregs, size_t len)
2378 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2379 gdb_byte *regs = gregs;
2382 gdb_assert (len == tdep->sizeof_gregset);
2384 for (i = 0; i < tdep->gregset_num_regs; i++)
2386 if ((regnum == i || regnum == -1)
2387 && tdep->gregset_reg_offset[i] != -1)
2388 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
2392 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2393 in the floating-point register set REGSET to register cache
2394 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2397 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
2398 int regnum, const void *fpregs, size_t len)
2400 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2402 if (len == I387_SIZEOF_FXSAVE)
2404 i387_supply_fxsave (regcache, regnum, fpregs);
2408 gdb_assert (len == tdep->sizeof_fpregset);
2409 i387_supply_fsave (regcache, regnum, fpregs);
2412 /* Collect register REGNUM from the register cache REGCACHE and store
2413 it in the buffer specified by FPREGS and LEN as described by the
2414 floating-point register set REGSET. If REGNUM is -1, do this for
2415 all registers in REGSET. */
2418 i386_collect_fpregset (const struct regset *regset,
2419 const struct regcache *regcache,
2420 int regnum, void *fpregs, size_t len)
2422 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2424 if (len == I387_SIZEOF_FXSAVE)
2426 i387_collect_fxsave (regcache, regnum, fpregs);
2430 gdb_assert (len == tdep->sizeof_fpregset);
2431 i387_collect_fsave (regcache, regnum, fpregs);
2434 /* Return the appropriate register set for the core section identified
2435 by SECT_NAME and SECT_SIZE. */
2437 const struct regset *
2438 i386_regset_from_core_section (struct gdbarch *gdbarch,
2439 const char *sect_name, size_t sect_size)
2441 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2443 if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset)
2445 if (tdep->gregset == NULL)
2446 tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset,
2447 i386_collect_gregset);
2448 return tdep->gregset;
2451 if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
2452 || (strcmp (sect_name, ".reg-xfp") == 0
2453 && sect_size == I387_SIZEOF_FXSAVE))
2455 if (tdep->fpregset == NULL)
2456 tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset,
2457 i386_collect_fpregset);
2458 return tdep->fpregset;
2465 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
2468 i386_pe_skip_trampoline_code (CORE_ADDR pc, char *name)
2470 if (pc && read_memory_unsigned_integer (pc, 2) == 0x25ff) /* jmp *(dest) */
2472 unsigned long indirect = read_memory_unsigned_integer (pc + 2, 4);
2473 struct minimal_symbol *indsym =
2474 indirect ? lookup_minimal_symbol_by_pc (indirect) : 0;
2475 char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0;
2479 if (strncmp (symname, "__imp_", 6) == 0
2480 || strncmp (symname, "_imp_", 5) == 0)
2481 return name ? 1 : read_memory_unsigned_integer (indirect, 4);
2484 return 0; /* Not a trampoline. */
2488 /* Return whether the THIS_FRAME corresponds to a sigtramp
2492 i386_sigtramp_p (struct frame_info *this_frame)
2494 CORE_ADDR pc = get_frame_pc (this_frame);
2497 find_pc_partial_function (pc, &name, NULL, NULL);
2498 return (name && strcmp ("_sigtramp", name) == 0);
2502 /* We have two flavours of disassembly. The machinery on this page
2503 deals with switching between those. */
2506 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
2508 gdb_assert (disassembly_flavor == att_flavor
2509 || disassembly_flavor == intel_flavor);
2511 /* FIXME: kettenis/20020915: Until disassembler_options is properly
2512 constified, cast to prevent a compiler warning. */
2513 info->disassembler_options = (char *) disassembly_flavor;
2515 return print_insn_i386 (pc, info);
2519 /* There are a few i386 architecture variants that differ only
2520 slightly from the generic i386 target. For now, we don't give them
2521 their own source file, but include them here. As a consequence,
2522 they'll always be included. */
2524 /* System V Release 4 (SVR4). */
2526 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
2530 i386_svr4_sigtramp_p (struct frame_info *this_frame)
2532 CORE_ADDR pc = get_frame_pc (this_frame);
2535 /* UnixWare uses _sigacthandler. The origin of the other symbols is
2536 currently unknown. */
2537 find_pc_partial_function (pc, &name, NULL, NULL);
2538 return (name && (strcmp ("_sigreturn", name) == 0
2539 || strcmp ("_sigacthandler", name) == 0
2540 || strcmp ("sigvechandler", name) == 0));
2543 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
2544 address of the associated sigcontext (ucontext) structure. */
2547 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
2552 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2553 sp = extract_unsigned_integer (buf, 4);
2555 return read_memory_unsigned_integer (sp + 8, 4);
2562 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2564 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
2565 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
2568 /* System V Release 4 (SVR4). */
2571 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2573 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2575 /* System V Release 4 uses ELF. */
2576 i386_elf_init_abi (info, gdbarch);
2578 /* System V Release 4 has shared libraries. */
2579 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
2581 tdep->sigtramp_p = i386_svr4_sigtramp_p;
2582 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
2583 tdep->sc_pc_offset = 36 + 14 * 4;
2584 tdep->sc_sp_offset = 36 + 17 * 4;
2586 tdep->jb_pc_offset = 20;
2592 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2594 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2596 /* DJGPP doesn't have any special frames for signal handlers. */
2597 tdep->sigtramp_p = NULL;
2599 tdep->jb_pc_offset = 36;
2601 /* DJGPP does not support the SSE registers. */
2602 tdep->num_xmm_regs = 0;
2603 set_gdbarch_num_regs (gdbarch, I386_NUM_GREGS + I386_NUM_FREGS);
2605 /* Native compiler is GCC, which uses the SVR4 register numbering
2606 even in COFF and STABS. See the comment in i386_gdbarch_init,
2607 before the calls to set_gdbarch_stab_reg_to_regnum and
2608 set_gdbarch_sdb_reg_to_regnum. */
2609 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
2610 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
2614 /* i386 register groups. In addition to the normal groups, add "mmx"
2617 static struct reggroup *i386_sse_reggroup;
2618 static struct reggroup *i386_mmx_reggroup;
2621 i386_init_reggroups (void)
2623 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
2624 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
2628 i386_add_reggroups (struct gdbarch *gdbarch)
2630 reggroup_add (gdbarch, i386_sse_reggroup);
2631 reggroup_add (gdbarch, i386_mmx_reggroup);
2632 reggroup_add (gdbarch, general_reggroup);
2633 reggroup_add (gdbarch, float_reggroup);
2634 reggroup_add (gdbarch, all_reggroup);
2635 reggroup_add (gdbarch, save_reggroup);
2636 reggroup_add (gdbarch, restore_reggroup);
2637 reggroup_add (gdbarch, vector_reggroup);
2638 reggroup_add (gdbarch, system_reggroup);
2642 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2643 struct reggroup *group)
2645 int sse_regnum_p = (i386_sse_regnum_p (gdbarch, regnum)
2646 || i386_mxcsr_regnum_p (gdbarch, regnum));
2647 int fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
2648 || i386_fpc_regnum_p (gdbarch, regnum));
2649 int mmx_regnum_p = (i386_mmx_regnum_p (gdbarch, regnum));
2651 if (group == i386_mmx_reggroup)
2652 return mmx_regnum_p;
2653 if (group == i386_sse_reggroup)
2654 return sse_regnum_p;
2655 if (group == vector_reggroup)
2656 return (mmx_regnum_p || sse_regnum_p);
2657 if (group == float_reggroup)
2659 if (group == general_reggroup)
2660 return (!fp_regnum_p && !mmx_regnum_p && !sse_regnum_p);
2662 return default_register_reggroup_p (gdbarch, regnum, group);
2666 /* Get the ARGIth function argument for the current function. */
2669 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
2672 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
2673 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4);
2677 i386_skip_permanent_breakpoint (struct regcache *regcache)
2679 CORE_ADDR current_pc = regcache_read_pc (regcache);
2681 /* On i386, breakpoint is exactly 1 byte long, so we just
2682 adjust the PC in the regcache. */
2684 regcache_write_pc (regcache, current_pc);
2688 #define PREFIX_REPZ 0x01
2689 #define PREFIX_REPNZ 0x02
2690 #define PREFIX_LOCK 0x04
2691 #define PREFIX_DATA 0x08
2692 #define PREFIX_ADDR 0x10
2702 /* i386 arith/logic operations */
2715 struct i386_record_s
2717 struct regcache *regcache;
2723 uint8_t mod, reg, rm;
2727 /* Parse "modrm" part in current memory address that irp->addr point to
2728 Return -1 if something wrong. */
2731 i386_record_modrm (struct i386_record_s *irp)
2733 if (target_read_memory (irp->addr, &irp->modrm, 1))
2736 printf_unfiltered (_("Process record: error reading memory at "
2737 "addr 0x%s len = 1.\n"),
2738 paddr_nz (irp->addr));
2742 irp->mod = (irp->modrm >> 6) & 3;
2743 irp->reg = (irp->modrm >> 3) & 7;
2744 irp->rm = irp->modrm & 7;
2749 /* Get the memory address that current instruction write to and set it to
2750 the argument "addr".
2751 Return -1 if something wrong. */
2754 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint32_t * addr)
2767 uint8_t base = irp->rm;
2772 if (target_read_memory (irp->addr, &tmpu8, 1))
2775 printf_unfiltered (_("Process record: error reading memory "
2776 "at addr 0x%s len = 1.\n"),
2777 paddr_nz (irp->addr));
2781 scale = (tmpu8 >> 6) & 3;
2782 index = ((tmpu8 >> 3) & 7);
2789 if ((base & 7) == 5)
2792 if (target_read_memory (irp->addr, (gdb_byte *) addr, 4))
2795 printf_unfiltered (_("Process record: error reading "
2796 "memory at addr 0x%s len = 4.\n"),
2797 paddr_nz (irp->addr));
2808 if (target_read_memory (irp->addr, &tmpu8, 1))
2811 printf_unfiltered (_("Process record: error reading memory "
2812 "at addr 0x%s len = 1.\n"),
2813 paddr_nz (irp->addr));
2817 *addr = (int8_t) tmpu8;
2820 if (target_read_memory (irp->addr, (gdb_byte *) addr, 4))
2823 printf_unfiltered (_("Process record: error reading memory "
2824 "at addr 0x%s len = 4.\n"),
2825 paddr_nz (irp->addr));
2834 regcache_raw_read (irp->regcache, base, (gdb_byte *) & tmpu32);
2838 /* XXX: index == 4 is always invalid */
2839 if (havesib && (index != 4 || scale != 0))
2841 regcache_raw_read (irp->regcache, index, (gdb_byte *) & tmpu32);
2842 *addr += tmpu32 << scale;
2853 if (target_read_memory
2854 (irp->addr, (gdb_byte *) & tmpu16, 2))
2857 printf_unfiltered (_("Process record: error reading "
2858 "memory at addr 0x%s len = 2.\n"),
2859 paddr_nz (irp->addr));
2863 *addr = (int16_t) tmpu16;
2873 if (target_read_memory (irp->addr, &tmpu8, 1))
2876 printf_unfiltered (_("Process record: error reading memory "
2877 "at addr 0x%s len = 1.\n"),
2878 paddr_nz (irp->addr));
2882 *addr = (int8_t) tmpu8;
2885 if (target_read_memory (irp->addr, (gdb_byte *) & tmpu16, 2))
2888 printf_unfiltered (_("Process record: error reading memory "
2889 "at addr 0x%s len = 2.\n"),
2890 paddr_nz (irp->addr));
2894 *addr = (int16_t) tmpu16;
2901 regcache_raw_read (irp->regcache, I386_EBX_REGNUM,
2902 (gdb_byte *) & tmpu32);
2904 regcache_raw_read (irp->regcache, I386_ESI_REGNUM,
2905 (gdb_byte *) & tmpu32);
2909 regcache_raw_read (irp->regcache, I386_EBX_REGNUM,
2910 (gdb_byte *) & tmpu32);
2912 regcache_raw_read (irp->regcache, I386_EDI_REGNUM,
2913 (gdb_byte *) & tmpu32);
2917 regcache_raw_read (irp->regcache, I386_EBP_REGNUM,
2918 (gdb_byte *) & tmpu32);
2920 regcache_raw_read (irp->regcache, I386_ESI_REGNUM,
2921 (gdb_byte *) & tmpu32);
2925 regcache_raw_read (irp->regcache, I386_EBP_REGNUM,
2926 (gdb_byte *) & tmpu32);
2928 regcache_raw_read (irp->regcache, I386_EDI_REGNUM,
2929 (gdb_byte *) & tmpu32);
2933 regcache_raw_read (irp->regcache, I386_ESI_REGNUM,
2934 (gdb_byte *) & tmpu32);
2938 regcache_raw_read (irp->regcache, I386_EDI_REGNUM,
2939 (gdb_byte *) & tmpu32);
2943 regcache_raw_read (irp->regcache, I386_EBP_REGNUM,
2944 (gdb_byte *) & tmpu32);
2948 regcache_raw_read (irp->regcache, I386_EBX_REGNUM,
2949 (gdb_byte *) & tmpu32);
2960 /* Record the value of the memory that willbe changed in current instruction
2961 to "record_arch_list".
2962 Return -1 if something wrong. */
2965 i386_record_lea_modrm (struct i386_record_s *irp)
2972 printf_unfiltered (_("Process record ignores the memory change "
2973 "of instruction at address 0x%s because it "
2974 "can't get the value of the segment register.\n"),
2975 paddr_nz (irp->addr));
2979 if (i386_record_lea_modrm_addr (irp, &addr))
2982 if (record_arch_list_add_mem (addr, 1 << irp->ot))
2988 /* Parse the current instruction and record the values of the registers and
2989 memory that will be changed in current instruction to "record_arch_list".
2990 Return -1 if something wrong. */
2993 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
3001 struct i386_record_s ir;
3003 memset (&ir, 0, sizeof (struct i386_record_s));
3004 ir.regcache = regcache;
3009 if (record_debug > 1)
3010 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
3012 paddr_nz (ir.addr));
3017 if (target_read_memory (ir.addr, &tmpu8, 1))
3020 printf_unfiltered (_("Process record: error reading memory at "
3021 "addr 0x%s len = 1.\n"),
3022 paddr_nz (ir.addr));
3029 prefixes |= PREFIX_REPZ;
3032 prefixes |= PREFIX_REPNZ;
3035 prefixes |= PREFIX_LOCK;
3038 ir.override = I386_CS_REGNUM;
3041 ir.override = I386_SS_REGNUM;
3044 ir.override = I386_DS_REGNUM;
3047 ir.override = I386_ES_REGNUM;
3050 ir.override = I386_FS_REGNUM;
3053 ir.override = I386_GS_REGNUM;
3056 prefixes |= PREFIX_DATA;
3059 prefixes |= PREFIX_ADDR;
3067 if (prefixes & PREFIX_DATA)
3069 if (prefixes & PREFIX_ADDR)
3072 /* now check op code */
3073 opcode = (uint32_t) tmpu8;
3078 if (target_read_memory (ir.addr, &tmpu8, 1))
3081 printf_unfiltered (_("Process record: error reading memory at "
3082 "addr 0x%s len = 1.\n"),
3083 paddr_nz (ir.addr));
3087 opcode = (uint16_t) tmpu8 | 0x0f00;
3140 if (((opcode >> 3) & 7) != OP_CMPL)
3142 if ((opcode & 1) == 0)
3145 ir.ot = ir.dflag + OT_WORD;
3147 switch ((opcode >> 1) & 3)
3151 if (i386_record_modrm (&ir))
3155 if (i386_record_lea_modrm (&ir))
3160 if (ir.ot == OT_BYTE)
3162 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3168 if (i386_record_modrm (&ir))
3170 if (ir.ot == OT_BYTE)
3172 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3177 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3182 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3191 if (i386_record_modrm (&ir))
3194 if (ir.reg != OP_CMPL)
3196 if ((opcode & 1) == 0)
3199 ir.ot = ir.dflag + OT_WORD;
3203 if (i386_record_lea_modrm (&ir))
3208 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3212 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3234 if (record_arch_list_add_reg (ir.regcache, opcode & 7))
3236 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3243 if ((opcode & 1) == 0)
3246 ir.ot = ir.dflag + OT_WORD;
3247 if (i386_record_modrm (&ir))
3254 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3261 if (i386_record_lea_modrm (&ir))
3266 if (ir.ot == OT_BYTE)
3268 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3276 if (i386_record_lea_modrm (&ir))
3281 if (ir.ot == OT_BYTE)
3283 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3286 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3297 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3299 if (ir.ot != OT_BYTE)
3301 if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM))
3304 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3309 opcode = opcode << 8 | ir.modrm;
3319 if ((opcode & 1) == 0)
3322 ir.ot = ir.dflag + OT_WORD;
3323 if (i386_record_modrm (&ir))
3325 if (ir.reg >= 2 && opcode == 0xfe)
3328 opcode = opcode << 8 | ir.modrm;
3340 if (i386_record_lea_modrm (&ir))
3345 if (ir.ot == OT_BYTE)
3347 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3350 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3357 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3359 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
3360 (gdb_byte *) & tmpu32);
3361 if (record_arch_list_add_mem
3362 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1))))
3367 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3369 if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM))
3371 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
3372 (gdb_byte *) & tmpu32);
3373 if (record_arch_list_add_mem
3374 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 2)), (1 << (ir.dflag + 2))))
3384 opcode = opcode << 8 | ir.modrm;
3395 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3401 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3407 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3409 if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM))
3417 ir.ot = ir.dflag + OT_WORD;
3418 if (i386_record_modrm (&ir))
3420 if (ir.ot == OT_BYTE)
3422 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3424 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3431 if ((opcode & 1) == 0)
3434 ir.ot = ir.dflag + OT_WORD;
3435 if (i386_record_modrm (&ir))
3439 if (ir.ot == OT_BYTE)
3441 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3443 if (ir.ot == OT_BYTE)
3445 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3450 if (i386_record_lea_modrm (&ir))
3452 if (ir.ot == OT_BYTE)
3454 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3457 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3464 if ((opcode & 1) == 0)
3467 ir.ot = ir.dflag + OT_WORD;
3468 if (i386_record_modrm (&ir))
3472 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3474 if (ir.ot == OT_BYTE)
3476 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3481 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3483 if (i386_record_lea_modrm (&ir))
3486 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3492 if (i386_record_modrm (&ir))
3497 opcode = opcode << 8 | ir.modrm;
3500 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3502 if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM))
3504 if (i386_record_lea_modrm (&ir))
3506 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3533 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3535 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
3536 (gdb_byte *) & tmpu32);
3537 if (record_arch_list_add_mem
3538 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1))))
3551 ir.ot = ir.dflag + OT_WORD;
3552 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3554 if (ir.ot == OT_BYTE)
3556 if (record_arch_list_add_reg (ir.regcache, opcode & 0x7))
3562 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3564 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
3565 (gdb_byte *) & tmpu32);
3566 if (record_arch_list_add_mem
3567 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 4)), (1 << (ir.dflag + 4))))
3573 for (tmpu8 = I386_EAX_REGNUM; tmpu8 <= I386_EDI_REGNUM; tmpu8++)
3575 if (record_arch_list_add_reg (ir.regcache, tmpu8))
3582 ir.ot = ir.dflag + OT_WORD;
3583 if (i386_record_modrm (&ir))
3587 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3592 if (i386_record_lea_modrm (&ir))
3595 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3601 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3603 if (record_arch_list_add_reg (ir.regcache, I386_EBP_REGNUM))
3605 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
3606 (gdb_byte *) & tmpu32);
3607 if (record_arch_list_add_mem
3608 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1))))
3614 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3616 if (record_arch_list_add_reg (ir.regcache, I386_EBP_REGNUM))
3622 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3624 if (record_arch_list_add_reg (ir.regcache, I386_ES_REGNUM))
3630 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3632 if (record_arch_list_add_reg (ir.regcache, I386_SS_REGNUM))
3638 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3640 if (record_arch_list_add_reg (ir.regcache, I386_DS_REGNUM))
3646 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3648 if (record_arch_list_add_reg (ir.regcache, I386_FS_REGNUM))
3654 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3656 if (record_arch_list_add_reg (ir.regcache, I386_GS_REGNUM))
3665 if ((opcode & 1) == 0)
3668 ir.ot = ir.dflag + OT_WORD;
3670 if (i386_record_modrm (&ir))
3675 if (i386_record_lea_modrm (&ir))
3680 if (ir.ot == OT_BYTE)
3682 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3685 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3691 if ((opcode & 1) == 0)
3694 ir.ot = ir.dflag + OT_WORD;
3696 if (i386_record_modrm (&ir))
3699 if (ir.ot == OT_BYTE)
3701 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3704 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3710 if (i386_record_modrm (&ir))
3716 tmpu8 = I386_ES_REGNUM;
3719 tmpu8 = I386_SS_REGNUM;
3722 tmpu8 = I386_DS_REGNUM;
3725 tmpu8 = I386_FS_REGNUM;
3728 tmpu8 = I386_GS_REGNUM;
3732 opcode = opcode << 8 | ir.modrm;
3736 if (record_arch_list_add_reg (ir.regcache, tmpu8))
3739 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3745 if (i386_record_modrm (&ir))
3750 opcode = opcode << 8 | ir.modrm;
3756 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3762 if (i386_record_lea_modrm (&ir))
3766 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3778 if (i386_record_modrm (&ir))
3780 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3786 if (i386_record_modrm (&ir))
3791 opcode = opcode << 8 | ir.modrm;
3796 if (ir.ot == OT_BYTE)
3798 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3807 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3820 printf_unfiltered (_("Process record ignores the memory change "
3821 "of instruction at address 0x%s because "
3822 "it can't get the value of the segment "
3824 paddr_nz (ir.addr));
3828 if ((opcode & 1) == 0)
3831 ir.ot = ir.dflag + OT_WORD;
3834 if (target_read_memory
3835 (ir.addr, (gdb_byte *) & addr, 4))
3838 printf_unfiltered (_("Process record: error reading "
3839 "memory at addr 0x%s len = 4.\n"),
3840 paddr_nz (ir.addr));
3847 if (target_read_memory
3848 (ir.addr, (gdb_byte *) & tmpu16, 4))
3851 printf_unfiltered (_("Process record: error reading "
3852 "memory at addr 0x%s len = 4.\n"),
3853 paddr_nz (ir.addr));
3859 if (record_arch_list_add_mem (addr, 1 << ir.ot))
3874 if (record_arch_list_add_reg (ir.regcache, (opcode & 0x7) & 0x3))
3887 if (record_arch_list_add_reg (ir.regcache, opcode & 0x7))
3899 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3901 if (record_arch_list_add_reg (ir.regcache, opcode & 0x7))
3908 if ((opcode & 1) == 0)
3911 ir.ot = ir.dflag + OT_WORD;
3913 if (i386_record_modrm (&ir))
3918 if (ir.ot == OT_BYTE)
3920 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3925 if (i386_record_lea_modrm (&ir))
3929 if (ir.ot == OT_BYTE)
3931 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3945 if (i386_record_modrm (&ir))
3953 opcode = opcode << 8 | ir.modrm;
3961 tmpu8 = I386_ES_REGNUM;
3965 tmpu8 = I386_DS_REGNUM;
3969 tmpu8 = I386_SS_REGNUM;
3973 tmpu8 = I386_FS_REGNUM;
3977 tmpu8 = I386_GS_REGNUM;
3980 if (record_arch_list_add_reg (ir.regcache, tmpu8))
3983 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3994 if ((opcode & 1) == 0)
3997 ir.ot = ir.dflag + OT_WORD;
3999 if (i386_record_modrm (&ir))
4002 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
4004 if (i386_record_lea_modrm (&ir))
4009 if (ir.ot == OT_BYTE)
4011 if (record_arch_list_add_reg (ir.regcache, ir.rm))
4015 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4023 if (i386_record_modrm (&ir))
4027 if (record_arch_list_add_reg (ir.regcache, ir.rm))
4032 if (i386_record_lea_modrm (&ir))
4038 /* It just record the memory change of instrcution. */
4047 if (i386_record_modrm (&ir))
4049 ir.reg |= ((opcode & 7) << 3);
4055 if (i386_record_lea_modrm_addr (&ir, &addr))
4112 switch (ir.reg >> 4)
4115 if (record_arch_list_add_mem (addr, 4))
4119 if (record_arch_list_add_mem (addr, 8))
4124 if (record_arch_list_add_mem (addr, 2))
4130 switch (ir.reg >> 4)
4134 if (record_arch_list_add_mem (addr, 4))
4138 if (record_arch_list_add_mem (addr, 8))
4143 if (record_arch_list_add_mem (addr, 2))
4160 if (record_arch_list_add_mem (addr, 28))
4165 if (record_arch_list_add_mem (addr, 14))
4171 if (record_arch_list_add_mem (addr, 2))
4176 if (record_arch_list_add_mem (addr, 10))
4182 if (record_arch_list_add_mem (addr, 28))
4188 if (record_arch_list_add_mem (addr, 14))
4192 if (record_arch_list_add_mem (addr, 80))
4196 if (record_arch_list_add_mem (addr, 8))
4201 opcode = opcode << 8 | ir.modrm;
4221 if ((opcode & 1) == 0)
4224 ir.ot = ir.dflag + OT_WORD;
4225 if (opcode == 0xa4 || opcode == 0xa5)
4227 if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM))
4230 if (record_arch_list_add_reg (ir.regcache, I386_EDI_REGNUM))
4233 regcache_raw_read (ir.regcache, I386_EDI_REGNUM,
4234 (gdb_byte *) & addr);
4238 /* addr += ((uint32_t)read_register (I386_ES_REGNUM)) << 4; */
4240 printf_unfiltered (_("Process record ignores the memory change "
4241 "of instruction at address 0x%s because "
4242 "it can't get the value of the segment "
4244 paddr_nz (ir.addr));
4247 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
4251 regcache_raw_read (ir.regcache, I386_ECX_REGNUM,
4252 (gdb_byte *) & count);
4256 regcache_raw_read (ir.regcache, I386_EFLAGS_REGNUM,
4257 (gdb_byte *) & tmpu32);
4258 if ((tmpu32 >> 10) & 0x1)
4259 addr -= (count - 1) * (1 << ir.ot);
4263 if (record_arch_list_add_mem (addr, count * (1 << ir.ot)))
4267 if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
4274 if (record_arch_list_add_mem (addr, 1 << ir.ot))
4284 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
4286 if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM))
4288 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
4290 if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
4298 if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM))
4300 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
4302 if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
4310 if (record_arch_list_add_reg (ir.regcache, I386_EDI_REGNUM))
4312 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
4314 if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
4317 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4324 if (record_arch_list_add_reg (ir.regcache, I386_EDI_REGNUM))
4326 if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM))
4328 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
4330 if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
4333 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4342 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
4361 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
4363 if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM))
4369 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
4371 if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM))
4373 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4379 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
4381 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
4382 (gdb_byte *) & tmpu32);
4383 if (record_arch_list_add_mem
4384 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1))))
4390 if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM))
4392 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
4394 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
4395 (gdb_byte *) & tmpu32);
4396 if (record_arch_list_add_mem
4397 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 2)), (1 << (ir.dflag + 2))))
4461 if (i386_record_modrm (&ir))
4465 if (record_arch_list_add_reg (ir.regcache, ir.rm & 0x3))
4470 if (i386_record_lea_modrm (&ir))
4492 if (i386_record_modrm (&ir))
4494 if (ir.dflag == OT_BYTE)
4496 if (record_arch_list_add_reg (ir.regcache, ir.reg & 0x3))
4503 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
4505 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
4506 (gdb_byte *) & tmpu32);
4507 if (record_arch_list_add_mem
4508 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1))))
4514 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
4516 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4532 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4538 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
4542 /* bit operations */
4543 /* bt/bts/btr/btc Gv, im */
4551 ir.ot = ir.dflag + OT_WORD;
4552 if (i386_record_modrm (&ir))
4557 opcode = opcode << 8 | ir.modrm;
4565 if (i386_record_lea_modrm (&ir))
4570 if (record_arch_list_add_reg (ir.regcache, ir.rm))
4574 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4580 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4588 if (record_arch_list_add_reg (ir.regcache, ir.reg))
4590 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4607 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
4609 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4616 if (prefixes & PREFIX_LOCK)
4626 printf_unfiltered (_("Process record doesn't support instruction "
4635 printf_unfiltered (_("Process record doesn't support instruction "
4646 if (target_read_memory (ir.addr, &tmpu8, 1))
4649 printf_unfiltered (_("Process record: error reading memory "
4650 "at addr 0x%s len = 1.\n"),
4651 paddr_nz (ir.addr));
4656 || gdbarch_tdep (gdbarch)->i386_intx80_record == NULL)
4658 printf_unfiltered (_("Process record doesn't support "
4659 "instruction int 0x%02x.\n"),
4664 ret = gdbarch_tdep (gdbarch)->i386_intx80_record (ir.regcache);
4673 printf_unfiltered (_("Process record doesn't support "
4674 "instruction into.\n"));
4687 printf_unfiltered (_("Process record doesn't support "
4688 "instruction bound.\n"));
4702 if (record_arch_list_add_reg (ir.regcache, opcode & 7))
4708 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
4710 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4722 if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
4728 printf_unfiltered (_("Process record doesn't support "
4729 "instruction wrmsr.\n"));
4736 printf_unfiltered (_("Process record doesn't support "
4737 "instruction rdmsr.\n"));
4744 printf_unfiltered (_("Process record doesn't support "
4745 "instruction rdtsc.\n"));
4754 if (gdbarch_tdep (gdbarch)->i386_sysenter_record == NULL)
4756 printf_unfiltered (_("Process record doesn't support "
4757 "instruction sysenter.\n"));
4761 ret = gdbarch_tdep (gdbarch)->i386_sysenter_record (ir.regcache);
4769 printf_unfiltered (_("Process record doesn't support "
4770 "instruction sysexit.\n"));
4777 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
4779 if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
4781 if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM))
4783 if (record_arch_list_add_reg (ir.regcache, I386_EBX_REGNUM))
4789 printf_unfiltered (_("Process record doesn't support "
4790 "instruction hlt.\n"));
4796 if (i386_record_modrm (&ir))
4806 if (record_arch_list_add_reg (ir.regcache, ir.rm))
4812 if (i386_record_lea_modrm (&ir))
4825 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4830 opcode = opcode << 8 | ir.modrm;
4837 if (i386_record_modrm (&ir))
4849 opcode = opcode << 8 | ir.modrm;
4856 printf_unfiltered (_("Process record ignores the memory "
4857 "change of instruction at "
4858 "address 0x%s because it can't get "
4859 "the value of the segment "
4861 paddr_nz (ir.addr));
4865 if (i386_record_lea_modrm_addr (&ir, &addr))
4867 if (record_arch_list_add_mem (addr, 2))
4870 if (record_arch_list_add_mem (addr, 4))
4885 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4890 opcode = opcode << 8 | ir.modrm;
4901 printf_unfiltered (_("Process record ignores the memory "
4902 "change of instruction at "
4903 "address 0x%s because it can't get "
4904 "the value of the segment "
4906 paddr_nz (ir.addr));
4912 if (i386_record_lea_modrm_addr (&ir, &addr))
4914 if (record_arch_list_add_mem (addr, 2))
4917 if (record_arch_list_add_mem (addr, 4))
4932 opcode = opcode << 8 | ir.modrm;
4940 if (record_arch_list_add_reg (ir.regcache, ir.rm))
4946 if (i386_record_lea_modrm (&ir))
4964 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
4965 if (i386_record_modrm (&ir))
4969 if (i386_record_lea_modrm (&ir))
4974 if (record_arch_list_add_reg (ir.regcache, ir.rm))
4977 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4985 if (i386_record_modrm (&ir))
4987 if (record_arch_list_add_reg (ir.regcache, ir.reg))
4989 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4996 /* nop (multi byte) */
5010 if (i386_record_modrm (&ir))
5012 if ((ir.modrm & 0xc0) != 0xc0)
5015 opcode = opcode << 8 | ir.modrm;
5030 if (record_arch_list_add_reg (ir.regcache, ir.rm))
5036 opcode = opcode << 8 | ir.modrm;
5046 if (i386_record_modrm (&ir))
5048 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
5049 || ir.reg == 5 || ir.reg >= 8)
5052 opcode = opcode << 8 | ir.modrm;
5060 if (record_arch_list_add_reg (ir.regcache, ir.rm))
5069 /* MMX/SSE/SSE2/PNI support */
5081 /* In the future, Maybe still need to deal with need_dasm */
5082 if (record_arch_list_add_reg (ir.regcache, I386_EIP_REGNUM))
5084 if (record_arch_list_add_end ())
5090 printf_unfiltered (_("Process record doesn't support instruction 0x%02x "
5091 "at address 0x%s.\n"),
5092 (unsigned int) (opcode), paddr_nz (ir.addr));
5097 static struct gdbarch *
5098 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
5100 struct gdbarch_tdep *tdep;
5101 struct gdbarch *gdbarch;
5103 /* If there is already a candidate, use it. */
5104 arches = gdbarch_list_lookup_by_info (arches, &info);
5106 return arches->gdbarch;
5108 /* Allocate space for the new architecture. */
5109 tdep = XCALLOC (1, struct gdbarch_tdep);
5110 gdbarch = gdbarch_alloc (&info, tdep);
5112 /* General-purpose registers. */
5113 tdep->gregset = NULL;
5114 tdep->gregset_reg_offset = NULL;
5115 tdep->gregset_num_regs = I386_NUM_GREGS;
5116 tdep->sizeof_gregset = 0;
5118 /* Floating-point registers. */
5119 tdep->fpregset = NULL;
5120 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
5122 /* The default settings include the FPU registers, the MMX registers
5123 and the SSE registers. This can be overridden for a specific ABI
5124 by adjusting the members `st0_regnum', `mm0_regnum' and
5125 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
5126 will show up in the output of "info all-registers". Ideally we
5127 should try to autodetect whether they are available, such that we
5128 can prevent "info all-registers" from displaying registers that
5131 NOTE: kevinb/2003-07-13: ... if it's a choice between printing
5132 [the SSE registers] always (even when they don't exist) or never
5133 showing them to the user (even when they do exist), I prefer the
5134 former over the latter. */
5136 tdep->st0_regnum = I386_ST0_REGNUM;
5138 /* The MMX registers are implemented as pseudo-registers. Put off
5139 calculating the register number for %mm0 until we know the number
5140 of raw registers. */
5141 tdep->mm0_regnum = 0;
5143 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
5144 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
5146 tdep->jb_pc_offset = -1;
5147 tdep->struct_return = pcc_struct_return;
5148 tdep->sigtramp_start = 0;
5149 tdep->sigtramp_end = 0;
5150 tdep->sigtramp_p = i386_sigtramp_p;
5151 tdep->sigcontext_addr = NULL;
5152 tdep->sc_reg_offset = NULL;
5153 tdep->sc_pc_offset = -1;
5154 tdep->sc_sp_offset = -1;
5156 /* The format used for `long double' on almost all i386 targets is
5157 the i387 extended floating-point format. In fact, of all targets
5158 in the GCC 2.95 tree, only OSF/1 does it different, and insists
5159 on having a `long double' that's not `long' at all. */
5160 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
5162 /* Although the i387 extended floating-point has only 80 significant
5163 bits, a `long double' actually takes up 96, probably to enforce
5165 set_gdbarch_long_double_bit (gdbarch, 96);
5167 /* The default ABI includes general-purpose registers,
5168 floating-point registers, and the SSE registers. */
5169 set_gdbarch_num_regs (gdbarch, I386_SSE_NUM_REGS);
5170 set_gdbarch_register_name (gdbarch, i386_register_name);
5171 set_gdbarch_register_type (gdbarch, i386_register_type);
5173 /* Register numbers of various important registers. */
5174 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
5175 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
5176 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
5177 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
5179 /* NOTE: kettenis/20040418: GCC does have two possible register
5180 numbering schemes on the i386: dbx and SVR4. These schemes
5181 differ in how they number %ebp, %esp, %eflags, and the
5182 floating-point registers, and are implemented by the arrays
5183 dbx_register_map[] and svr4_dbx_register_map in
5184 gcc/config/i386.c. GCC also defines a third numbering scheme in
5185 gcc/config/i386.c, which it designates as the "default" register
5186 map used in 64bit mode. This last register numbering scheme is
5187 implemented in dbx64_register_map, and is used for AMD64; see
5190 Currently, each GCC i386 target always uses the same register
5191 numbering scheme across all its supported debugging formats
5192 i.e. SDB (COFF), stabs and DWARF 2. This is because
5193 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
5194 DBX_REGISTER_NUMBER macro which is defined by each target's
5195 respective config header in a manner independent of the requested
5196 output debugging format.
5198 This does not match the arrangement below, which presumes that
5199 the SDB and stabs numbering schemes differ from the DWARF and
5200 DWARF 2 ones. The reason for this arrangement is that it is
5201 likely to get the numbering scheme for the target's
5202 default/native debug format right. For targets where GCC is the
5203 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
5204 targets where the native toolchain uses a different numbering
5205 scheme for a particular debug format (stabs-in-ELF on Solaris)
5206 the defaults below will have to be overridden, like
5207 i386_elf_init_abi() does. */
5209 /* Use the dbx register numbering scheme for stabs and COFF. */
5210 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
5211 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
5213 /* Use the SVR4 register numbering scheme for DWARF 2. */
5214 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
5216 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
5217 be in use on any of the supported i386 targets. */
5219 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
5221 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
5223 /* Call dummy code. */
5224 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
5226 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
5227 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
5228 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
5230 set_gdbarch_return_value (gdbarch, i386_return_value);
5232 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
5234 /* Stack grows downward. */
5235 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
5237 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc);
5238 set_gdbarch_decr_pc_after_break (gdbarch, 1);
5239 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
5241 set_gdbarch_frame_args_skip (gdbarch, 8);
5243 /* Wire in the MMX registers. */
5244 set_gdbarch_num_pseudo_regs (gdbarch, i386_num_mmx_regs);
5245 set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read);
5246 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
5248 set_gdbarch_print_insn (gdbarch, i386_print_insn);
5250 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
5252 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
5254 /* Add the i386 register groups. */
5255 i386_add_reggroups (gdbarch);
5256 set_gdbarch_register_reggroup_p (gdbarch, i386_register_reggroup_p);
5258 /* Helper for function argument information. */
5259 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
5261 /* Hook in the DWARF CFI frame unwinder. */
5262 dwarf2_append_unwinders (gdbarch);
5264 frame_base_set_default (gdbarch, &i386_frame_base);
5266 /* Hook in ABI-specific overrides, if they have been registered. */
5267 gdbarch_init_osabi (info, gdbarch);
5269 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
5270 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
5272 /* If we have a register mapping, enable the generic core file
5273 support, unless it has already been enabled. */
5274 if (tdep->gregset_reg_offset
5275 && !gdbarch_regset_from_core_section_p (gdbarch))
5276 set_gdbarch_regset_from_core_section (gdbarch,
5277 i386_regset_from_core_section);
5279 /* Unless support for MMX has been disabled, make %mm0 the first
5281 if (tdep->mm0_regnum == 0)
5282 tdep->mm0_regnum = gdbarch_num_regs (gdbarch);
5284 set_gdbarch_skip_permanent_breakpoint (gdbarch,
5285 i386_skip_permanent_breakpoint);
5290 static enum gdb_osabi
5291 i386_coff_osabi_sniffer (bfd *abfd)
5293 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
5294 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
5295 return GDB_OSABI_GO32;
5297 return GDB_OSABI_UNKNOWN;
5301 /* Provide a prototype to silence -Wmissing-prototypes. */
5302 void _initialize_i386_tdep (void);
5305 _initialize_i386_tdep (void)
5307 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
5309 /* Add the variable that controls the disassembly flavor. */
5310 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
5311 &disassembly_flavor, _("\
5312 Set the disassembly flavor."), _("\
5313 Show the disassembly flavor."), _("\
5314 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
5316 NULL, /* FIXME: i18n: */
5317 &setlist, &showlist);
5319 /* Add the variable that controls the convention for returning
5321 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
5322 &struct_convention, _("\
5323 Set the convention for returning small structs."), _("\
5324 Show the convention for returning small structs."), _("\
5325 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
5328 NULL, /* FIXME: i18n: */
5329 &setlist, &showlist);
5331 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
5332 i386_coff_osabi_sniffer);
5334 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
5335 i386_svr4_init_abi);
5336 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
5337 i386_go32_init_abi);
5339 /* Initialize the i386-specific register groups & types. */
5340 i386_init_reggroups ();