1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2015 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
38 #include "reggroups.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "x86-xstate.h"
52 #include "record-full.h"
55 #include "features/i386/i386.c"
56 #include "features/i386/i386-avx.c"
57 #include "features/i386/i386-mpx.c"
58 #include "features/i386/i386-avx512.c"
59 #include "features/i386/i386-mmx.c"
64 #include "stap-probe.h"
65 #include "user-regs.h"
66 #include "cli/cli-utils.h"
67 #include "expression.h"
68 #include "parser-defs.h"
73 static const char *i386_register_names[] =
75 "eax", "ecx", "edx", "ebx",
76 "esp", "ebp", "esi", "edi",
77 "eip", "eflags", "cs", "ss",
78 "ds", "es", "fs", "gs",
79 "st0", "st1", "st2", "st3",
80 "st4", "st5", "st6", "st7",
81 "fctrl", "fstat", "ftag", "fiseg",
82 "fioff", "foseg", "fooff", "fop",
83 "xmm0", "xmm1", "xmm2", "xmm3",
84 "xmm4", "xmm5", "xmm6", "xmm7",
88 static const char *i386_zmm_names[] =
90 "zmm0", "zmm1", "zmm2", "zmm3",
91 "zmm4", "zmm5", "zmm6", "zmm7"
94 static const char *i386_zmmh_names[] =
96 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
97 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
100 static const char *i386_k_names[] =
102 "k0", "k1", "k2", "k3",
103 "k4", "k5", "k6", "k7"
106 static const char *i386_ymm_names[] =
108 "ymm0", "ymm1", "ymm2", "ymm3",
109 "ymm4", "ymm5", "ymm6", "ymm7",
112 static const char *i386_ymmh_names[] =
114 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
115 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
118 static const char *i386_mpx_names[] =
120 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
123 /* Register names for MPX pseudo-registers. */
125 static const char *i386_bnd_names[] =
127 "bnd0", "bnd1", "bnd2", "bnd3"
130 /* Register names for MMX pseudo-registers. */
132 static const char *i386_mmx_names[] =
134 "mm0", "mm1", "mm2", "mm3",
135 "mm4", "mm5", "mm6", "mm7"
138 /* Register names for byte pseudo-registers. */
140 static const char *i386_byte_names[] =
142 "al", "cl", "dl", "bl",
143 "ah", "ch", "dh", "bh"
146 /* Register names for word pseudo-registers. */
148 static const char *i386_word_names[] =
150 "ax", "cx", "dx", "bx",
154 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
155 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
156 we have 16 upper ZMM regs that have to be handled differently. */
158 const int num_lower_zmm_regs = 16;
163 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
165 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
166 int mm0_regnum = tdep->mm0_regnum;
171 regnum -= mm0_regnum;
172 return regnum >= 0 && regnum < tdep->num_mmx_regs;
178 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
180 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
182 regnum -= tdep->al_regnum;
183 return regnum >= 0 && regnum < tdep->num_byte_regs;
189 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
191 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
193 regnum -= tdep->ax_regnum;
194 return regnum >= 0 && regnum < tdep->num_word_regs;
197 /* Dword register? */
200 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
202 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
203 int eax_regnum = tdep->eax_regnum;
208 regnum -= eax_regnum;
209 return regnum >= 0 && regnum < tdep->num_dword_regs;
212 /* AVX512 register? */
215 i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum)
217 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
218 int zmm0h_regnum = tdep->zmm0h_regnum;
220 if (zmm0h_regnum < 0)
223 regnum -= zmm0h_regnum;
224 return regnum >= 0 && regnum < tdep->num_zmm_regs;
228 i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum)
230 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
231 int zmm0_regnum = tdep->zmm0_regnum;
236 regnum -= zmm0_regnum;
237 return regnum >= 0 && regnum < tdep->num_zmm_regs;
241 i386_k_regnum_p (struct gdbarch *gdbarch, int regnum)
243 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
244 int k0_regnum = tdep->k0_regnum;
250 return regnum >= 0 && regnum < I387_NUM_K_REGS;
254 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
256 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
257 int ymm0h_regnum = tdep->ymm0h_regnum;
259 if (ymm0h_regnum < 0)
262 regnum -= ymm0h_regnum;
263 return regnum >= 0 && regnum < tdep->num_ymm_regs;
269 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
271 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
272 int ymm0_regnum = tdep->ymm0_regnum;
277 regnum -= ymm0_regnum;
278 return regnum >= 0 && regnum < tdep->num_ymm_regs;
282 i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
284 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
285 int ymm16h_regnum = tdep->ymm16h_regnum;
287 if (ymm16h_regnum < 0)
290 regnum -= ymm16h_regnum;
291 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
295 i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
297 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
298 int ymm16_regnum = tdep->ymm16_regnum;
300 if (ymm16_regnum < 0)
303 regnum -= ymm16_regnum;
304 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
310 i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum)
312 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
313 int bnd0_regnum = tdep->bnd0_regnum;
318 regnum -= bnd0_regnum;
319 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
325 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
327 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
328 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
330 if (num_xmm_regs == 0)
333 regnum -= I387_XMM0_REGNUM (tdep);
334 return regnum >= 0 && regnum < num_xmm_regs;
337 /* XMM_512 register? */
340 i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
342 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
343 int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep);
345 if (num_xmm_avx512_regs == 0)
348 regnum -= I387_XMM16_REGNUM (tdep);
349 return regnum >= 0 && regnum < num_xmm_avx512_regs;
353 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
355 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
357 if (I387_NUM_XMM_REGS (tdep) == 0)
360 return (regnum == I387_MXCSR_REGNUM (tdep));
366 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
368 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
370 if (I387_ST0_REGNUM (tdep) < 0)
373 return (I387_ST0_REGNUM (tdep) <= regnum
374 && regnum < I387_FCTRL_REGNUM (tdep));
378 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
380 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
382 if (I387_ST0_REGNUM (tdep) < 0)
385 return (I387_FCTRL_REGNUM (tdep) <= regnum
386 && regnum < I387_XMM0_REGNUM (tdep));
389 /* BNDr (raw) register? */
392 i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum)
394 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
396 if (I387_BND0R_REGNUM (tdep) < 0)
399 regnum -= tdep->bnd0r_regnum;
400 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
403 /* BND control register? */
406 i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum)
408 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
410 if (I387_BNDCFGU_REGNUM (tdep) < 0)
413 regnum -= I387_BNDCFGU_REGNUM (tdep);
414 return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS;
417 /* Return the name of register REGNUM, or the empty string if it is
418 an anonymous register. */
421 i386_register_name (struct gdbarch *gdbarch, int regnum)
423 /* Hide the upper YMM registers. */
424 if (i386_ymmh_regnum_p (gdbarch, regnum))
427 /* Hide the upper YMM16-31 registers. */
428 if (i386_ymmh_avx512_regnum_p (gdbarch, regnum))
431 /* Hide the upper ZMM registers. */
432 if (i386_zmmh_regnum_p (gdbarch, regnum))
435 return tdesc_register_name (gdbarch, regnum);
438 /* Return the name of register REGNUM. */
441 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
443 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
444 if (i386_bnd_regnum_p (gdbarch, regnum))
445 return i386_bnd_names[regnum - tdep->bnd0_regnum];
446 if (i386_mmx_regnum_p (gdbarch, regnum))
447 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
448 else if (i386_ymm_regnum_p (gdbarch, regnum))
449 return i386_ymm_names[regnum - tdep->ymm0_regnum];
450 else if (i386_zmm_regnum_p (gdbarch, regnum))
451 return i386_zmm_names[regnum - tdep->zmm0_regnum];
452 else if (i386_byte_regnum_p (gdbarch, regnum))
453 return i386_byte_names[regnum - tdep->al_regnum];
454 else if (i386_word_regnum_p (gdbarch, regnum))
455 return i386_word_names[regnum - tdep->ax_regnum];
457 internal_error (__FILE__, __LINE__, _("invalid regnum"));
460 /* Convert a dbx register number REG to the appropriate register
461 number used by GDB. */
464 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
466 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
468 /* This implements what GCC calls the "default" register map
469 (dbx_register_map[]). */
471 if (reg >= 0 && reg <= 7)
473 /* General-purpose registers. The debug info calls %ebp
474 register 4, and %esp register 5. */
481 else if (reg >= 12 && reg <= 19)
483 /* Floating-point registers. */
484 return reg - 12 + I387_ST0_REGNUM (tdep);
486 else if (reg >= 21 && reg <= 28)
489 int ymm0_regnum = tdep->ymm0_regnum;
492 && i386_xmm_regnum_p (gdbarch, reg))
493 return reg - 21 + ymm0_regnum;
495 return reg - 21 + I387_XMM0_REGNUM (tdep);
497 else if (reg >= 29 && reg <= 36)
500 return reg - 29 + I387_MM0_REGNUM (tdep);
503 /* This will hopefully provoke a warning. */
504 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
507 /* Convert SVR4 register number REG to the appropriate register number
511 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
513 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
515 /* This implements the GCC register map that tries to be compatible
516 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
518 /* The SVR4 register numbering includes %eip and %eflags, and
519 numbers the floating point registers differently. */
520 if (reg >= 0 && reg <= 9)
522 /* General-purpose registers. */
525 else if (reg >= 11 && reg <= 18)
527 /* Floating-point registers. */
528 return reg - 11 + I387_ST0_REGNUM (tdep);
530 else if (reg >= 21 && reg <= 36)
532 /* The SSE and MMX registers have the same numbers as with dbx. */
533 return i386_dbx_reg_to_regnum (gdbarch, reg);
538 case 37: return I387_FCTRL_REGNUM (tdep);
539 case 38: return I387_FSTAT_REGNUM (tdep);
540 case 39: return I387_MXCSR_REGNUM (tdep);
541 case 40: return I386_ES_REGNUM;
542 case 41: return I386_CS_REGNUM;
543 case 42: return I386_SS_REGNUM;
544 case 43: return I386_DS_REGNUM;
545 case 44: return I386_FS_REGNUM;
546 case 45: return I386_GS_REGNUM;
549 /* This will hopefully provoke a warning. */
550 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
555 /* This is the variable that is set with "set disassembly-flavor", and
556 its legitimate values. */
557 static const char att_flavor[] = "att";
558 static const char intel_flavor[] = "intel";
559 static const char *const valid_flavors[] =
565 static const char *disassembly_flavor = att_flavor;
568 /* Use the program counter to determine the contents and size of a
569 breakpoint instruction. Return a pointer to a string of bytes that
570 encode a breakpoint instruction, store the length of the string in
571 *LEN and optionally adjust *PC to point to the correct memory
572 location for inserting the breakpoint.
574 On the i386 we have a single breakpoint that fits in a single byte
575 and can be inserted anywhere.
577 This function is 64-bit safe. */
579 static const gdb_byte *
580 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
582 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */
584 *len = sizeof (break_insn);
588 /* Displaced instruction handling. */
590 /* Skip the legacy instruction prefixes in INSN.
591 Not all prefixes are valid for any particular insn
592 but we needn't care, the insn will fault if it's invalid.
593 The result is a pointer to the first opcode byte,
594 or NULL if we run off the end of the buffer. */
597 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
599 gdb_byte *end = insn + max_len;
605 case DATA_PREFIX_OPCODE:
606 case ADDR_PREFIX_OPCODE:
607 case CS_PREFIX_OPCODE:
608 case DS_PREFIX_OPCODE:
609 case ES_PREFIX_OPCODE:
610 case FS_PREFIX_OPCODE:
611 case GS_PREFIX_OPCODE:
612 case SS_PREFIX_OPCODE:
613 case LOCK_PREFIX_OPCODE:
614 case REPE_PREFIX_OPCODE:
615 case REPNE_PREFIX_OPCODE:
627 i386_absolute_jmp_p (const gdb_byte *insn)
629 /* jmp far (absolute address in operand). */
635 /* jump near, absolute indirect (/4). */
636 if ((insn[1] & 0x38) == 0x20)
639 /* jump far, absolute indirect (/5). */
640 if ((insn[1] & 0x38) == 0x28)
647 /* Return non-zero if INSN is a jump, zero otherwise. */
650 i386_jmp_p (const gdb_byte *insn)
652 /* jump short, relative. */
656 /* jump near, relative. */
660 return i386_absolute_jmp_p (insn);
664 i386_absolute_call_p (const gdb_byte *insn)
666 /* call far, absolute. */
672 /* Call near, absolute indirect (/2). */
673 if ((insn[1] & 0x38) == 0x10)
676 /* Call far, absolute indirect (/3). */
677 if ((insn[1] & 0x38) == 0x18)
685 i386_ret_p (const gdb_byte *insn)
689 case 0xc2: /* ret near, pop N bytes. */
690 case 0xc3: /* ret near */
691 case 0xca: /* ret far, pop N bytes. */
692 case 0xcb: /* ret far */
693 case 0xcf: /* iret */
702 i386_call_p (const gdb_byte *insn)
704 if (i386_absolute_call_p (insn))
707 /* call near, relative. */
714 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
715 length in bytes. Otherwise, return zero. */
718 i386_syscall_p (const gdb_byte *insn, int *lengthp)
720 /* Is it 'int $0x80'? */
721 if ((insn[0] == 0xcd && insn[1] == 0x80)
722 /* Or is it 'sysenter'? */
723 || (insn[0] == 0x0f && insn[1] == 0x34)
724 /* Or is it 'syscall'? */
725 || (insn[0] == 0x0f && insn[1] == 0x05))
734 /* The gdbarch insn_is_call method. */
737 i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
739 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
741 read_code (addr, buf, I386_MAX_INSN_LEN);
742 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
744 return i386_call_p (insn);
747 /* The gdbarch insn_is_ret method. */
750 i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
752 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
754 read_code (addr, buf, I386_MAX_INSN_LEN);
755 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
757 return i386_ret_p (insn);
760 /* The gdbarch insn_is_jump method. */
763 i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
765 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
767 read_code (addr, buf, I386_MAX_INSN_LEN);
768 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
770 return i386_jmp_p (insn);
773 /* Some kernels may run one past a syscall insn, so we have to cope.
774 Otherwise this is just simple_displaced_step_copy_insn. */
776 struct displaced_step_closure *
777 i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
778 CORE_ADDR from, CORE_ADDR to,
779 struct regcache *regs)
781 size_t len = gdbarch_max_insn_length (gdbarch);
782 gdb_byte *buf = xmalloc (len);
784 read_memory (from, buf, len);
786 /* GDB may get control back after the insn after the syscall.
787 Presumably this is a kernel bug.
788 If this is a syscall, make sure there's a nop afterwards. */
793 insn = i386_skip_prefixes (buf, len);
794 if (insn != NULL && i386_syscall_p (insn, &syscall_length))
795 insn[syscall_length] = NOP_OPCODE;
798 write_memory (to, buf, len);
802 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
803 paddress (gdbarch, from), paddress (gdbarch, to));
804 displaced_step_dump_bytes (gdb_stdlog, buf, len);
807 return (struct displaced_step_closure *) buf;
810 /* Fix up the state of registers and memory after having single-stepped
811 a displaced instruction. */
814 i386_displaced_step_fixup (struct gdbarch *gdbarch,
815 struct displaced_step_closure *closure,
816 CORE_ADDR from, CORE_ADDR to,
817 struct regcache *regs)
819 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
821 /* The offset we applied to the instruction's address.
822 This could well be negative (when viewed as a signed 32-bit
823 value), but ULONGEST won't reflect that, so take care when
825 ULONGEST insn_offset = to - from;
827 /* Since we use simple_displaced_step_copy_insn, our closure is a
828 copy of the instruction. */
829 gdb_byte *insn = (gdb_byte *) closure;
830 /* The start of the insn, needed in case we see some prefixes. */
831 gdb_byte *insn_start = insn;
834 fprintf_unfiltered (gdb_stdlog,
835 "displaced: fixup (%s, %s), "
836 "insn = 0x%02x 0x%02x ...\n",
837 paddress (gdbarch, from), paddress (gdbarch, to),
840 /* The list of issues to contend with here is taken from
841 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
842 Yay for Free Software! */
844 /* Relocate the %eip, if necessary. */
846 /* The instruction recognizers we use assume any leading prefixes
847 have been skipped. */
849 /* This is the size of the buffer in closure. */
850 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
851 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
852 /* If there are too many prefixes, just ignore the insn.
853 It will fault when run. */
858 /* Except in the case of absolute or indirect jump or call
859 instructions, or a return instruction, the new eip is relative to
860 the displaced instruction; make it relative. Well, signal
861 handler returns don't need relocation either, but we use the
862 value of %eip to recognize those; see below. */
863 if (! i386_absolute_jmp_p (insn)
864 && ! i386_absolute_call_p (insn)
865 && ! i386_ret_p (insn))
870 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
872 /* A signal trampoline system call changes the %eip, resuming
873 execution of the main program after the signal handler has
874 returned. That makes them like 'return' instructions; we
875 shouldn't relocate %eip.
877 But most system calls don't, and we do need to relocate %eip.
879 Our heuristic for distinguishing these cases: if stepping
880 over the system call instruction left control directly after
881 the instruction, the we relocate --- control almost certainly
882 doesn't belong in the displaced copy. Otherwise, we assume
883 the instruction has put control where it belongs, and leave
884 it unrelocated. Goodness help us if there are PC-relative
886 if (i386_syscall_p (insn, &insn_len)
887 && orig_eip != to + (insn - insn_start) + insn_len
888 /* GDB can get control back after the insn after the syscall.
889 Presumably this is a kernel bug.
890 i386_displaced_step_copy_insn ensures its a nop,
891 we add one to the length for it. */
892 && orig_eip != to + (insn - insn_start) + insn_len + 1)
895 fprintf_unfiltered (gdb_stdlog,
896 "displaced: syscall changed %%eip; "
901 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
903 /* If we just stepped over a breakpoint insn, we don't backup
904 the pc on purpose; this is to match behaviour without
907 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
910 fprintf_unfiltered (gdb_stdlog,
912 "relocated %%eip from %s to %s\n",
913 paddress (gdbarch, orig_eip),
914 paddress (gdbarch, eip));
918 /* If the instruction was PUSHFL, then the TF bit will be set in the
919 pushed value, and should be cleared. We'll leave this for later,
920 since GDB already messes up the TF flag when stepping over a
923 /* If the instruction was a call, the return address now atop the
924 stack is the address following the copied instruction. We need
925 to make it the address following the original instruction. */
926 if (i386_call_p (insn))
930 const ULONGEST retaddr_len = 4;
932 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
933 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
934 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
935 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
938 fprintf_unfiltered (gdb_stdlog,
939 "displaced: relocated return addr at %s to %s\n",
940 paddress (gdbarch, esp),
941 paddress (gdbarch, retaddr));
946 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
948 target_write_memory (*to, buf, len);
953 i386_relocate_instruction (struct gdbarch *gdbarch,
954 CORE_ADDR *to, CORE_ADDR oldloc)
956 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
957 gdb_byte buf[I386_MAX_INSN_LEN];
958 int offset = 0, rel32, newrel;
960 gdb_byte *insn = buf;
962 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
964 insn_length = gdb_buffered_insn_length (gdbarch, insn,
965 I386_MAX_INSN_LEN, oldloc);
967 /* Get past the prefixes. */
968 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
970 /* Adjust calls with 32-bit relative addresses as push/jump, with
971 the address pushed being the location where the original call in
972 the user program would return to. */
975 gdb_byte push_buf[16];
976 unsigned int ret_addr;
978 /* Where "ret" in the original code will return to. */
979 ret_addr = oldloc + insn_length;
980 push_buf[0] = 0x68; /* pushq $... */
981 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
983 append_insns (to, 5, push_buf);
985 /* Convert the relative call to a relative jump. */
988 /* Adjust the destination offset. */
989 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
990 newrel = (oldloc - *to) + rel32;
991 store_signed_integer (insn + 1, 4, byte_order, newrel);
994 fprintf_unfiltered (gdb_stdlog,
995 "Adjusted insn rel32=%s at %s to"
997 hex_string (rel32), paddress (gdbarch, oldloc),
998 hex_string (newrel), paddress (gdbarch, *to));
1000 /* Write the adjusted jump into its displaced location. */
1001 append_insns (to, 5, insn);
1005 /* Adjust jumps with 32-bit relative addresses. Calls are already
1007 if (insn[0] == 0xe9)
1009 /* Adjust conditional jumps. */
1010 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1015 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1016 newrel = (oldloc - *to) + rel32;
1017 store_signed_integer (insn + offset, 4, byte_order, newrel);
1018 if (debug_displaced)
1019 fprintf_unfiltered (gdb_stdlog,
1020 "Adjusted insn rel32=%s at %s to"
1021 " rel32=%s at %s\n",
1022 hex_string (rel32), paddress (gdbarch, oldloc),
1023 hex_string (newrel), paddress (gdbarch, *to));
1026 /* Write the adjusted instructions into their displaced
1028 append_insns (to, insn_length, buf);
1032 #ifdef I386_REGNO_TO_SYMMETRY
1033 #error "The Sequent Symmetry is no longer supported."
1036 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1037 and %esp "belong" to the calling function. Therefore these
1038 registers should be saved if they're going to be modified. */
1040 /* The maximum number of saved registers. This should include all
1041 registers mentioned above, and %eip. */
1042 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1044 struct i386_frame_cache
1052 /* Saved registers. */
1053 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
1058 /* Stack space reserved for local variables. */
1062 /* Allocate and initialize a frame cache. */
1064 static struct i386_frame_cache *
1065 i386_alloc_frame_cache (void)
1067 struct i386_frame_cache *cache;
1070 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
1075 cache->sp_offset = -4;
1078 /* Saved registers. We initialize these to -1 since zero is a valid
1079 offset (that's where %ebp is supposed to be stored). */
1080 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1081 cache->saved_regs[i] = -1;
1082 cache->saved_sp = 0;
1083 cache->saved_sp_reg = -1;
1084 cache->pc_in_eax = 0;
1086 /* Frameless until proven otherwise. */
1092 /* If the instruction at PC is a jump, return the address of its
1093 target. Otherwise, return PC. */
1096 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
1098 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1103 if (target_read_code (pc, &op, 1))
1110 op = read_code_unsigned_integer (pc + 1, 1, byte_order);
1116 /* Relative jump: if data16 == 0, disp32, else disp16. */
1119 delta = read_memory_integer (pc + 2, 2, byte_order);
1121 /* Include the size of the jmp instruction (including the
1127 delta = read_memory_integer (pc + 1, 4, byte_order);
1129 /* Include the size of the jmp instruction. */
1134 /* Relative jump, disp8 (ignore data16). */
1135 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
1137 delta += data16 + 2;
1144 /* Check whether PC points at a prologue for a function returning a
1145 structure or union. If so, it updates CACHE and returns the
1146 address of the first instruction after the code sequence that
1147 removes the "hidden" argument from the stack or CURRENT_PC,
1148 whichever is smaller. Otherwise, return PC. */
1151 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
1152 struct i386_frame_cache *cache)
1154 /* Functions that return a structure or union start with:
1157 xchgl %eax, (%esp) 0x87 0x04 0x24
1158 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1160 (the System V compiler puts out the second `xchg' instruction,
1161 and the assembler doesn't try to optimize it, so the 'sib' form
1162 gets generated). This sequence is used to get the address of the
1163 return buffer for a function that returns a structure. */
1164 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
1165 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
1169 if (current_pc <= pc)
1172 if (target_read_code (pc, &op, 1))
1175 if (op != 0x58) /* popl %eax */
1178 if (target_read_code (pc + 1, buf, 4))
1181 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
1184 if (current_pc == pc)
1186 cache->sp_offset += 4;
1190 if (current_pc == pc + 1)
1192 cache->pc_in_eax = 1;
1196 if (buf[1] == proto1[1])
1203 i386_skip_probe (CORE_ADDR pc)
1205 /* A function may start with
1219 if (target_read_code (pc, &op, 1))
1222 if (op == 0x68 || op == 0x6a)
1226 /* Skip past the `pushl' instruction; it has either a one-byte or a
1227 four-byte operand, depending on the opcode. */
1233 /* Read the following 8 bytes, which should be `call _probe' (6
1234 bytes) followed by `addl $4,%esp' (2 bytes). */
1235 read_memory (pc + delta, buf, sizeof (buf));
1236 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
1237 pc += delta + sizeof (buf);
1243 /* GCC 4.1 and later, can put code in the prologue to realign the
1244 stack pointer. Check whether PC points to such code, and update
1245 CACHE accordingly. Return the first instruction after the code
1246 sequence or CURRENT_PC, whichever is smaller. If we don't
1247 recognize the code, return PC. */
1250 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1251 struct i386_frame_cache *cache)
1253 /* There are 2 code sequences to re-align stack before the frame
1256 1. Use a caller-saved saved register:
1262 2. Use a callee-saved saved register:
1269 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1271 0x83 0xe4 0xf0 andl $-16, %esp
1272 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1277 int offset, offset_and;
1278 static int regnums[8] = {
1279 I386_EAX_REGNUM, /* %eax */
1280 I386_ECX_REGNUM, /* %ecx */
1281 I386_EDX_REGNUM, /* %edx */
1282 I386_EBX_REGNUM, /* %ebx */
1283 I386_ESP_REGNUM, /* %esp */
1284 I386_EBP_REGNUM, /* %ebp */
1285 I386_ESI_REGNUM, /* %esi */
1286 I386_EDI_REGNUM /* %edi */
1289 if (target_read_code (pc, buf, sizeof buf))
1292 /* Check caller-saved saved register. The first instruction has
1293 to be "leal 4(%esp), %reg". */
1294 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1296 /* MOD must be binary 10 and R/M must be binary 100. */
1297 if ((buf[1] & 0xc7) != 0x44)
1300 /* REG has register number. */
1301 reg = (buf[1] >> 3) & 7;
1306 /* Check callee-saved saved register. The first instruction
1307 has to be "pushl %reg". */
1308 if ((buf[0] & 0xf8) != 0x50)
1314 /* The next instruction has to be "leal 8(%esp), %reg". */
1315 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1318 /* MOD must be binary 10 and R/M must be binary 100. */
1319 if ((buf[2] & 0xc7) != 0x44)
1322 /* REG has register number. Registers in pushl and leal have to
1324 if (reg != ((buf[2] >> 3) & 7))
1330 /* Rigister can't be %esp nor %ebp. */
1331 if (reg == 4 || reg == 5)
1334 /* The next instruction has to be "andl $-XXX, %esp". */
1335 if (buf[offset + 1] != 0xe4
1336 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1339 offset_and = offset;
1340 offset += buf[offset] == 0x81 ? 6 : 3;
1342 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1343 0xfc. REG must be binary 110 and MOD must be binary 01. */
1344 if (buf[offset] != 0xff
1345 || buf[offset + 2] != 0xfc
1346 || (buf[offset + 1] & 0xf8) != 0x70)
1349 /* R/M has register. Registers in leal and pushl have to be the
1351 if (reg != (buf[offset + 1] & 7))
1354 if (current_pc > pc + offset_and)
1355 cache->saved_sp_reg = regnums[reg];
1357 return min (pc + offset + 3, current_pc);
1360 /* Maximum instruction length we need to handle. */
1361 #define I386_MAX_MATCHED_INSN_LEN 6
1363 /* Instruction description. */
1367 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
1368 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
1371 /* Return whether instruction at PC matches PATTERN. */
1374 i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern)
1378 if (target_read_code (pc, &op, 1))
1381 if ((op & pattern.mask[0]) == pattern.insn[0])
1383 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1384 int insn_matched = 1;
1387 gdb_assert (pattern.len > 1);
1388 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN);
1390 if (target_read_code (pc + 1, buf, pattern.len - 1))
1393 for (i = 1; i < pattern.len; i++)
1395 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i])
1398 return insn_matched;
1403 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1404 the first instruction description that matches. Otherwise, return
1407 static struct i386_insn *
1408 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns)
1410 struct i386_insn *pattern;
1412 for (pattern = insn_patterns; pattern->len > 0; pattern++)
1414 if (i386_match_pattern (pc, *pattern))
1421 /* Return whether PC points inside a sequence of instructions that
1422 matches INSN_PATTERNS. */
1425 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns)
1427 CORE_ADDR current_pc;
1429 struct i386_insn *insn;
1431 insn = i386_match_insn (pc, insn_patterns);
1436 ix = insn - insn_patterns;
1437 for (i = ix - 1; i >= 0; i--)
1439 current_pc -= insn_patterns[i].len;
1441 if (!i386_match_pattern (current_pc, insn_patterns[i]))
1445 current_pc = pc + insn->len;
1446 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++)
1448 if (!i386_match_pattern (current_pc, *insn))
1451 current_pc += insn->len;
1457 /* Some special instructions that might be migrated by GCC into the
1458 part of the prologue that sets up the new stack frame. Because the
1459 stack frame hasn't been setup yet, no registers have been saved
1460 yet, and only the scratch registers %eax, %ecx and %edx can be
1463 struct i386_insn i386_frame_setup_skip_insns[] =
1465 /* Check for `movb imm8, r' and `movl imm32, r'.
1467 ??? Should we handle 16-bit operand-sizes here? */
1469 /* `movb imm8, %al' and `movb imm8, %ah' */
1470 /* `movb imm8, %cl' and `movb imm8, %ch' */
1471 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1472 /* `movb imm8, %dl' and `movb imm8, %dh' */
1473 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1474 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1475 { 5, { 0xb8 }, { 0xfe } },
1476 /* `movl imm32, %edx' */
1477 { 5, { 0xba }, { 0xff } },
1479 /* Check for `mov imm32, r32'. Note that there is an alternative
1480 encoding for `mov m32, %eax'.
1482 ??? Should we handle SIB adressing here?
1483 ??? Should we handle 16-bit operand-sizes here? */
1485 /* `movl m32, %eax' */
1486 { 5, { 0xa1 }, { 0xff } },
1487 /* `movl m32, %eax' and `mov; m32, %ecx' */
1488 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1489 /* `movl m32, %edx' */
1490 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1492 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1493 Because of the symmetry, there are actually two ways to encode
1494 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1495 opcode bytes 0x31 and 0x33 for `xorl'. */
1497 /* `subl %eax, %eax' */
1498 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1499 /* `subl %ecx, %ecx' */
1500 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1501 /* `subl %edx, %edx' */
1502 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1503 /* `xorl %eax, %eax' */
1504 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1505 /* `xorl %ecx, %ecx' */
1506 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1507 /* `xorl %edx, %edx' */
1508 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1513 /* Check whether PC points to a no-op instruction. */
1515 i386_skip_noop (CORE_ADDR pc)
1520 if (target_read_code (pc, &op, 1))
1526 /* Ignore `nop' instruction. */
1530 if (target_read_code (pc, &op, 1))
1534 /* Ignore no-op instruction `mov %edi, %edi'.
1535 Microsoft system dlls often start with
1536 a `mov %edi,%edi' instruction.
1537 The 5 bytes before the function start are
1538 filled with `nop' instructions.
1539 This pattern can be used for hot-patching:
1540 The `mov %edi, %edi' instruction can be replaced by a
1541 near jump to the location of the 5 `nop' instructions
1542 which can be replaced by a 32-bit jump to anywhere
1543 in the 32-bit address space. */
1545 else if (op == 0x8b)
1547 if (target_read_code (pc + 1, &op, 1))
1553 if (target_read_code (pc, &op, 1))
1563 /* Check whether PC points at a code that sets up a new stack frame.
1564 If so, it updates CACHE and returns the address of the first
1565 instruction after the sequence that sets up the frame or LIMIT,
1566 whichever is smaller. If we don't recognize the code, return PC. */
1569 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1570 CORE_ADDR pc, CORE_ADDR limit,
1571 struct i386_frame_cache *cache)
1573 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1574 struct i386_insn *insn;
1581 if (target_read_code (pc, &op, 1))
1584 if (op == 0x55) /* pushl %ebp */
1586 /* Take into account that we've executed the `pushl %ebp' that
1587 starts this instruction sequence. */
1588 cache->saved_regs[I386_EBP_REGNUM] = 0;
1589 cache->sp_offset += 4;
1592 /* If that's all, return now. */
1596 /* Check for some special instructions that might be migrated by
1597 GCC into the prologue and skip them. At this point in the
1598 prologue, code should only touch the scratch registers %eax,
1599 %ecx and %edx, so while the number of posibilities is sheer,
1602 Make sure we only skip these instructions if we later see the
1603 `movl %esp, %ebp' that actually sets up the frame. */
1604 while (pc + skip < limit)
1606 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1613 /* If that's all, return now. */
1614 if (limit <= pc + skip)
1617 if (target_read_code (pc + skip, &op, 1))
1620 /* The i386 prologue looks like
1626 and a different prologue can be generated for atom.
1630 lea -0x10(%esp),%esp
1632 We handle both of them here. */
1636 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1638 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1644 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1649 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1650 if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order)
1659 /* OK, we actually have a frame. We just don't know how large
1660 it is yet. Set its size to zero. We'll adjust it if
1661 necessary. We also now commit to skipping the special
1662 instructions mentioned before. */
1665 /* If that's all, return now. */
1669 /* Check for stack adjustment
1675 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1676 reg, so we don't have to worry about a data16 prefix. */
1677 if (target_read_code (pc, &op, 1))
1681 /* `subl' with 8-bit immediate. */
1682 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1683 /* Some instruction starting with 0x83 other than `subl'. */
1686 /* `subl' with signed 8-bit immediate (though it wouldn't
1687 make sense to be negative). */
1688 cache->locals = read_code_integer (pc + 2, 1, byte_order);
1691 else if (op == 0x81)
1693 /* Maybe it is `subl' with a 32-bit immediate. */
1694 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1695 /* Some instruction starting with 0x81 other than `subl'. */
1698 /* It is `subl' with a 32-bit immediate. */
1699 cache->locals = read_code_integer (pc + 2, 4, byte_order);
1702 else if (op == 0x8d)
1704 /* The ModR/M byte is 0x64. */
1705 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64)
1707 /* 'lea' with 8-bit displacement. */
1708 cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order);
1713 /* Some instruction other than `subl' nor 'lea'. */
1717 else if (op == 0xc8) /* enter */
1719 cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order);
1726 /* Check whether PC points at code that saves registers on the stack.
1727 If so, it updates CACHE and returns the address of the first
1728 instruction after the register saves or CURRENT_PC, whichever is
1729 smaller. Otherwise, return PC. */
1732 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1733 struct i386_frame_cache *cache)
1735 CORE_ADDR offset = 0;
1739 if (cache->locals > 0)
1740 offset -= cache->locals;
1741 for (i = 0; i < 8 && pc < current_pc; i++)
1743 if (target_read_code (pc, &op, 1))
1745 if (op < 0x50 || op > 0x57)
1749 cache->saved_regs[op - 0x50] = offset;
1750 cache->sp_offset += 4;
1757 /* Do a full analysis of the prologue at PC and update CACHE
1758 accordingly. Bail out early if CURRENT_PC is reached. Return the
1759 address where the analysis stopped.
1761 We handle these cases:
1763 The startup sequence can be at the start of the function, or the
1764 function can start with a branch to startup code at the end.
1766 %ebp can be set up with either the 'enter' instruction, or "pushl
1767 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1768 once used in the System V compiler).
1770 Local space is allocated just below the saved %ebp by either the
1771 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1772 16-bit unsigned argument for space to allocate, and the 'addl'
1773 instruction could have either a signed byte, or 32-bit immediate.
1775 Next, the registers used by this function are pushed. With the
1776 System V compiler they will always be in the order: %edi, %esi,
1777 %ebx (and sometimes a harmless bug causes it to also save but not
1778 restore %eax); however, the code below is willing to see the pushes
1779 in any order, and will handle up to 8 of them.
1781 If the setup sequence is at the end of the function, then the next
1782 instruction will be a branch back to the start. */
1785 i386_analyze_prologue (struct gdbarch *gdbarch,
1786 CORE_ADDR pc, CORE_ADDR current_pc,
1787 struct i386_frame_cache *cache)
1789 pc = i386_skip_noop (pc);
1790 pc = i386_follow_jump (gdbarch, pc);
1791 pc = i386_analyze_struct_return (pc, current_pc, cache);
1792 pc = i386_skip_probe (pc);
1793 pc = i386_analyze_stack_align (pc, current_pc, cache);
1794 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1795 return i386_analyze_register_saves (pc, current_pc, cache);
1798 /* Return PC of first real instruction. */
1801 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1803 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1805 static gdb_byte pic_pat[6] =
1807 0xe8, 0, 0, 0, 0, /* call 0x0 */
1808 0x5b, /* popl %ebx */
1810 struct i386_frame_cache cache;
1814 CORE_ADDR func_addr;
1816 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
1818 CORE_ADDR post_prologue_pc
1819 = skip_prologue_using_sal (gdbarch, func_addr);
1820 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
1822 /* Clang always emits a line note before the prologue and another
1823 one after. We trust clang to emit usable line notes. */
1824 if (post_prologue_pc
1826 && COMPUNIT_PRODUCER (cust) != NULL
1827 && strncmp (COMPUNIT_PRODUCER (cust), "clang ",
1828 sizeof ("clang ") - 1) == 0))
1829 return max (start_pc, post_prologue_pc);
1833 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1834 if (cache.locals < 0)
1837 /* Found valid frame setup. */
1839 /* The native cc on SVR4 in -K PIC mode inserts the following code
1840 to get the address of the global offset table (GOT) into register
1845 movl %ebx,x(%ebp) (optional)
1848 This code is with the rest of the prologue (at the end of the
1849 function), so we have to skip it to get to the first real
1850 instruction at the start of the function. */
1852 for (i = 0; i < 6; i++)
1854 if (target_read_code (pc + i, &op, 1))
1857 if (pic_pat[i] != op)
1864 if (target_read_code (pc + delta, &op, 1))
1867 if (op == 0x89) /* movl %ebx, x(%ebp) */
1869 op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order);
1871 if (op == 0x5d) /* One byte offset from %ebp. */
1873 else if (op == 0x9d) /* Four byte offset from %ebp. */
1875 else /* Unexpected instruction. */
1878 if (target_read_code (pc + delta, &op, 1))
1883 if (delta > 0 && op == 0x81
1884 && read_code_unsigned_integer (pc + delta + 1, 1, byte_order)
1891 /* If the function starts with a branch (to startup code at the end)
1892 the last instruction should bring us back to the first
1893 instruction of the real code. */
1894 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1895 pc = i386_follow_jump (gdbarch, pc);
1900 /* Check that the code pointed to by PC corresponds to a call to
1901 __main, skip it if so. Return PC otherwise. */
1904 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1906 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1909 if (target_read_code (pc, &op, 1))
1915 if (target_read_code (pc + 1, buf, sizeof buf) == 0)
1917 /* Make sure address is computed correctly as a 32bit
1918 integer even if CORE_ADDR is 64 bit wide. */
1919 struct bound_minimal_symbol s;
1920 CORE_ADDR call_dest;
1922 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1923 call_dest = call_dest & 0xffffffffU;
1924 s = lookup_minimal_symbol_by_pc (call_dest);
1925 if (s.minsym != NULL
1926 && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL
1927 && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0)
1935 /* This function is 64-bit safe. */
1938 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1942 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1943 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1947 /* Normal frames. */
1950 i386_frame_cache_1 (struct frame_info *this_frame,
1951 struct i386_frame_cache *cache)
1953 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1954 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1958 cache->pc = get_frame_func (this_frame);
1960 /* In principle, for normal frames, %ebp holds the frame pointer,
1961 which holds the base address for the current stack frame.
1962 However, for functions that don't need it, the frame pointer is
1963 optional. For these "frameless" functions the frame pointer is
1964 actually the frame pointer of the calling frame. Signal
1965 trampolines are just a special case of a "frameless" function.
1966 They (usually) share their frame pointer with the frame that was
1967 in progress when the signal occurred. */
1969 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1970 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1971 if (cache->base == 0)
1977 /* For normal frames, %eip is stored at 4(%ebp). */
1978 cache->saved_regs[I386_EIP_REGNUM] = 4;
1981 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
1984 if (cache->locals < 0)
1986 /* We didn't find a valid frame, which means that CACHE->base
1987 currently holds the frame pointer for our calling frame. If
1988 we're at the start of a function, or somewhere half-way its
1989 prologue, the function's frame probably hasn't been fully
1990 setup yet. Try to reconstruct the base address for the stack
1991 frame by looking at the stack pointer. For truly "frameless"
1992 functions this might work too. */
1994 if (cache->saved_sp_reg != -1)
1996 /* Saved stack pointer has been saved. */
1997 get_frame_register (this_frame, cache->saved_sp_reg, buf);
1998 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2000 /* We're halfway aligning the stack. */
2001 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
2002 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
2004 /* This will be added back below. */
2005 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
2007 else if (cache->pc != 0
2008 || target_read_code (get_frame_pc (this_frame), buf, 1))
2010 /* We're in a known function, but did not find a frame
2011 setup. Assume that the function does not use %ebp.
2012 Alternatively, we may have jumped to an invalid
2013 address; in that case there is definitely no new
2015 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2016 cache->base = extract_unsigned_integer (buf, 4, byte_order)
2020 /* We're in an unknown function. We could not find the start
2021 of the function to analyze the prologue; our best option is
2022 to assume a typical frame layout with the caller's %ebp
2024 cache->saved_regs[I386_EBP_REGNUM] = 0;
2027 if (cache->saved_sp_reg != -1)
2029 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2030 register may be unavailable). */
2031 if (cache->saved_sp == 0
2032 && deprecated_frame_register_read (this_frame,
2033 cache->saved_sp_reg, buf))
2034 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2036 /* Now that we have the base address for the stack frame we can
2037 calculate the value of %esp in the calling frame. */
2038 else if (cache->saved_sp == 0)
2039 cache->saved_sp = cache->base + 8;
2041 /* Adjust all the saved registers such that they contain addresses
2042 instead of offsets. */
2043 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
2044 if (cache->saved_regs[i] != -1)
2045 cache->saved_regs[i] += cache->base;
2050 static struct i386_frame_cache *
2051 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
2053 volatile struct gdb_exception ex;
2054 struct i386_frame_cache *cache;
2059 cache = i386_alloc_frame_cache ();
2060 *this_cache = cache;
2062 TRY_CATCH (ex, RETURN_MASK_ERROR)
2064 i386_frame_cache_1 (this_frame, cache);
2066 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2067 throw_exception (ex);
2073 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
2074 struct frame_id *this_id)
2076 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2079 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2080 else if (cache->base == 0)
2082 /* This marks the outermost frame. */
2086 /* See the end of i386_push_dummy_call. */
2087 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2091 static enum unwind_stop_reason
2092 i386_frame_unwind_stop_reason (struct frame_info *this_frame,
2095 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2098 return UNWIND_UNAVAILABLE;
2100 /* This marks the outermost frame. */
2101 if (cache->base == 0)
2102 return UNWIND_OUTERMOST;
2104 return UNWIND_NO_REASON;
2107 static struct value *
2108 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2111 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2113 gdb_assert (regnum >= 0);
2115 /* The System V ABI says that:
2117 "The flags register contains the system flags, such as the
2118 direction flag and the carry flag. The direction flag must be
2119 set to the forward (that is, zero) direction before entry and
2120 upon exit from a function. Other user flags have no specified
2121 role in the standard calling sequence and are not preserved."
2123 To guarantee the "upon exit" part of that statement we fake a
2124 saved flags register that has its direction flag cleared.
2126 Note that GCC doesn't seem to rely on the fact that the direction
2127 flag is cleared after a function return; it always explicitly
2128 clears the flag before operations where it matters.
2130 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2131 right thing to do. The way we fake the flags register here makes
2132 it impossible to change it. */
2134 if (regnum == I386_EFLAGS_REGNUM)
2138 val = get_frame_register_unsigned (this_frame, regnum);
2140 return frame_unwind_got_constant (this_frame, regnum, val);
2143 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
2144 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
2146 if (regnum == I386_ESP_REGNUM
2147 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1))
2149 /* If the SP has been saved, but we don't know where, then this
2150 means that SAVED_SP_REG register was found unavailable back
2151 when we built the cache. */
2152 if (cache->saved_sp == 0)
2153 return frame_unwind_got_register (this_frame, regnum,
2154 cache->saved_sp_reg);
2156 return frame_unwind_got_constant (this_frame, regnum,
2160 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2161 return frame_unwind_got_memory (this_frame, regnum,
2162 cache->saved_regs[regnum]);
2164 return frame_unwind_got_register (this_frame, regnum, regnum);
2167 static const struct frame_unwind i386_frame_unwind =
2170 i386_frame_unwind_stop_reason,
2172 i386_frame_prev_register,
2174 default_frame_sniffer
2177 /* Normal frames, but in a function epilogue. */
2179 /* The epilogue is defined here as the 'ret' instruction, which will
2180 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2181 the function's stack frame. */
2184 i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2187 struct compunit_symtab *cust;
2189 cust = find_pc_compunit_symtab (pc);
2190 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
2193 if (target_read_memory (pc, &insn, 1))
2194 return 0; /* Can't read memory at pc. */
2196 if (insn != 0xc3) /* 'ret' instruction. */
2203 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
2204 struct frame_info *this_frame,
2205 void **this_prologue_cache)
2207 if (frame_relative_level (this_frame) == 0)
2208 return i386_in_function_epilogue_p (get_frame_arch (this_frame),
2209 get_frame_pc (this_frame));
2214 static struct i386_frame_cache *
2215 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2217 volatile struct gdb_exception ex;
2218 struct i386_frame_cache *cache;
2224 cache = i386_alloc_frame_cache ();
2225 *this_cache = cache;
2227 TRY_CATCH (ex, RETURN_MASK_ERROR)
2229 cache->pc = get_frame_func (this_frame);
2231 /* At this point the stack looks as if we just entered the
2232 function, with the return address at the top of the
2234 sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM);
2235 cache->base = sp + cache->sp_offset;
2236 cache->saved_sp = cache->base + 8;
2237 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
2241 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2242 throw_exception (ex);
2247 static enum unwind_stop_reason
2248 i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2251 struct i386_frame_cache *cache =
2252 i386_epilogue_frame_cache (this_frame, this_cache);
2255 return UNWIND_UNAVAILABLE;
2257 return UNWIND_NO_REASON;
2261 i386_epilogue_frame_this_id (struct frame_info *this_frame,
2263 struct frame_id *this_id)
2265 struct i386_frame_cache *cache =
2266 i386_epilogue_frame_cache (this_frame, this_cache);
2269 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2271 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2274 static struct value *
2275 i386_epilogue_frame_prev_register (struct frame_info *this_frame,
2276 void **this_cache, int regnum)
2278 /* Make sure we've initialized the cache. */
2279 i386_epilogue_frame_cache (this_frame, this_cache);
2281 return i386_frame_prev_register (this_frame, this_cache, regnum);
2284 static const struct frame_unwind i386_epilogue_frame_unwind =
2287 i386_epilogue_frame_unwind_stop_reason,
2288 i386_epilogue_frame_this_id,
2289 i386_epilogue_frame_prev_register,
2291 i386_epilogue_frame_sniffer
2295 /* Stack-based trampolines. */
2297 /* These trampolines are used on cross x86 targets, when taking the
2298 address of a nested function. When executing these trampolines,
2299 no stack frame is set up, so we are in a similar situation as in
2300 epilogues and i386_epilogue_frame_this_id can be re-used. */
2302 /* Static chain passed in register. */
2304 struct i386_insn i386_tramp_chain_in_reg_insns[] =
2306 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2307 { 5, { 0xb8 }, { 0xfe } },
2310 { 5, { 0xe9 }, { 0xff } },
2315 /* Static chain passed on stack (when regparm=3). */
2317 struct i386_insn i386_tramp_chain_on_stack_insns[] =
2320 { 5, { 0x68 }, { 0xff } },
2323 { 5, { 0xe9 }, { 0xff } },
2328 /* Return whether PC points inside a stack trampoline. */
2331 i386_in_stack_tramp_p (CORE_ADDR pc)
2336 /* A stack trampoline is detected if no name is associated
2337 to the current pc and if it points inside a trampoline
2340 find_pc_partial_function (pc, &name, NULL, NULL);
2344 if (target_read_memory (pc, &insn, 1))
2347 if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns)
2348 && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns))
2355 i386_stack_tramp_frame_sniffer (const struct frame_unwind *self,
2356 struct frame_info *this_frame,
2359 if (frame_relative_level (this_frame) == 0)
2360 return i386_in_stack_tramp_p (get_frame_pc (this_frame));
2365 static const struct frame_unwind i386_stack_tramp_frame_unwind =
2368 i386_epilogue_frame_unwind_stop_reason,
2369 i386_epilogue_frame_this_id,
2370 i386_epilogue_frame_prev_register,
2372 i386_stack_tramp_frame_sniffer
2375 /* Generate a bytecode expression to get the value of the saved PC. */
2378 i386_gen_return_address (struct gdbarch *gdbarch,
2379 struct agent_expr *ax, struct axs_value *value,
2382 /* The following sequence assumes the traditional use of the base
2384 ax_reg (ax, I386_EBP_REGNUM);
2386 ax_simple (ax, aop_add);
2387 value->type = register_type (gdbarch, I386_EIP_REGNUM);
2388 value->kind = axs_lvalue_memory;
2392 /* Signal trampolines. */
2394 static struct i386_frame_cache *
2395 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2397 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2398 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2399 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2400 volatile struct gdb_exception ex;
2401 struct i386_frame_cache *cache;
2408 cache = i386_alloc_frame_cache ();
2410 TRY_CATCH (ex, RETURN_MASK_ERROR)
2412 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2413 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
2415 addr = tdep->sigcontext_addr (this_frame);
2416 if (tdep->sc_reg_offset)
2420 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
2422 for (i = 0; i < tdep->sc_num_regs; i++)
2423 if (tdep->sc_reg_offset[i] != -1)
2424 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2428 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
2429 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
2434 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2435 throw_exception (ex);
2437 *this_cache = cache;
2441 static enum unwind_stop_reason
2442 i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2445 struct i386_frame_cache *cache =
2446 i386_sigtramp_frame_cache (this_frame, this_cache);
2449 return UNWIND_UNAVAILABLE;
2451 return UNWIND_NO_REASON;
2455 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
2456 struct frame_id *this_id)
2458 struct i386_frame_cache *cache =
2459 i386_sigtramp_frame_cache (this_frame, this_cache);
2462 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2465 /* See the end of i386_push_dummy_call. */
2466 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
2470 static struct value *
2471 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
2472 void **this_cache, int regnum)
2474 /* Make sure we've initialized the cache. */
2475 i386_sigtramp_frame_cache (this_frame, this_cache);
2477 return i386_frame_prev_register (this_frame, this_cache, regnum);
2481 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
2482 struct frame_info *this_frame,
2483 void **this_prologue_cache)
2485 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2487 /* We shouldn't even bother if we don't have a sigcontext_addr
2489 if (tdep->sigcontext_addr == NULL)
2492 if (tdep->sigtramp_p != NULL)
2494 if (tdep->sigtramp_p (this_frame))
2498 if (tdep->sigtramp_start != 0)
2500 CORE_ADDR pc = get_frame_pc (this_frame);
2502 gdb_assert (tdep->sigtramp_end != 0);
2503 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2510 static const struct frame_unwind i386_sigtramp_frame_unwind =
2513 i386_sigtramp_frame_unwind_stop_reason,
2514 i386_sigtramp_frame_this_id,
2515 i386_sigtramp_frame_prev_register,
2517 i386_sigtramp_frame_sniffer
2522 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
2524 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2529 static const struct frame_base i386_frame_base =
2532 i386_frame_base_address,
2533 i386_frame_base_address,
2534 i386_frame_base_address
2537 static struct frame_id
2538 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2542 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
2544 /* See the end of i386_push_dummy_call. */
2545 return frame_id_build (fp + 8, get_frame_pc (this_frame));
2548 /* _Decimal128 function return values need 16-byte alignment on the
2552 i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2554 return sp & -(CORE_ADDR)16;
2558 /* Figure out where the longjmp will land. Slurp the args out of the
2559 stack. We expect the first arg to be a pointer to the jmp_buf
2560 structure from which we extract the address that we will land at.
2561 This address is copied into PC. This routine returns non-zero on
2565 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2568 CORE_ADDR sp, jb_addr;
2569 struct gdbarch *gdbarch = get_frame_arch (frame);
2570 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2571 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2573 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2574 longjmp will land. */
2575 if (jb_pc_offset == -1)
2578 get_frame_register (frame, I386_ESP_REGNUM, buf);
2579 sp = extract_unsigned_integer (buf, 4, byte_order);
2580 if (target_read_memory (sp + 4, buf, 4))
2583 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
2584 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
2587 *pc = extract_unsigned_integer (buf, 4, byte_order);
2592 /* Check whether TYPE must be 16-byte-aligned when passed as a
2593 function argument. 16-byte vectors, _Decimal128 and structures or
2594 unions containing such types must be 16-byte-aligned; other
2595 arguments are 4-byte-aligned. */
2598 i386_16_byte_align_p (struct type *type)
2600 type = check_typedef (type);
2601 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
2602 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
2603 && TYPE_LENGTH (type) == 16)
2605 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2606 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
2607 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2608 || TYPE_CODE (type) == TYPE_CODE_UNION)
2611 for (i = 0; i < TYPE_NFIELDS (type); i++)
2613 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
2620 /* Implementation for set_gdbarch_push_dummy_code. */
2623 i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
2624 struct value **args, int nargs, struct type *value_type,
2625 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
2626 struct regcache *regcache)
2628 /* Use 0xcc breakpoint - 1 byte. */
2632 /* Keep the stack aligned. */
2637 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2638 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2639 struct value **args, CORE_ADDR sp, int struct_return,
2640 CORE_ADDR struct_addr)
2642 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2648 /* Determine the total space required for arguments and struct
2649 return address in a first pass (allowing for 16-byte-aligned
2650 arguments), then push arguments in a second pass. */
2652 for (write_pass = 0; write_pass < 2; write_pass++)
2654 int args_space_used = 0;
2660 /* Push value address. */
2661 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2662 write_memory (sp, buf, 4);
2663 args_space_used += 4;
2669 for (i = 0; i < nargs; i++)
2671 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2675 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2676 args_space_used = align_up (args_space_used, 16);
2678 write_memory (sp + args_space_used,
2679 value_contents_all (args[i]), len);
2680 /* The System V ABI says that:
2682 "An argument's size is increased, if necessary, to make it a
2683 multiple of [32-bit] words. This may require tail padding,
2684 depending on the size of the argument."
2686 This makes sure the stack stays word-aligned. */
2687 args_space_used += align_up (len, 4);
2691 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2692 args_space = align_up (args_space, 16);
2693 args_space += align_up (len, 4);
2701 /* The original System V ABI only requires word alignment,
2702 but modern incarnations need 16-byte alignment in order
2703 to support SSE. Since wasting a few bytes here isn't
2704 harmful we unconditionally enforce 16-byte alignment. */
2709 /* Store return address. */
2711 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2712 write_memory (sp, buf, 4);
2714 /* Finally, update the stack pointer... */
2715 store_unsigned_integer (buf, 4, byte_order, sp);
2716 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
2718 /* ...and fake a frame pointer. */
2719 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
2721 /* MarkK wrote: This "+ 8" is all over the place:
2722 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2723 i386_dummy_id). It's there, since all frame unwinders for
2724 a given target have to agree (within a certain margin) on the
2725 definition of the stack address of a frame. Otherwise frame id
2726 comparison might not work correctly. Since DWARF2/GCC uses the
2727 stack address *before* the function call as a frame's CFA. On
2728 the i386, when %ebp is used as a frame pointer, the offset
2729 between the contents %ebp and the CFA as defined by GCC. */
2733 /* These registers are used for returning integers (and on some
2734 targets also for returning `struct' and `union' values when their
2735 size and alignment match an integer type). */
2736 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2737 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2739 /* Read, for architecture GDBARCH, a function return value of TYPE
2740 from REGCACHE, and copy that into VALBUF. */
2743 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2744 struct regcache *regcache, gdb_byte *valbuf)
2746 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2747 int len = TYPE_LENGTH (type);
2748 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2750 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2752 if (tdep->st0_regnum < 0)
2754 warning (_("Cannot find floating-point return value."));
2755 memset (valbuf, 0, len);
2759 /* Floating-point return values can be found in %st(0). Convert
2760 its contents to the desired type. This is probably not
2761 exactly how it would happen on the target itself, but it is
2762 the best we can do. */
2763 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2764 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
2768 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2769 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2771 if (len <= low_size)
2773 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2774 memcpy (valbuf, buf, len);
2776 else if (len <= (low_size + high_size))
2778 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2779 memcpy (valbuf, buf, low_size);
2780 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2781 memcpy (valbuf + low_size, buf, len - low_size);
2784 internal_error (__FILE__, __LINE__,
2785 _("Cannot extract return value of %d bytes long."),
2790 /* Write, for architecture GDBARCH, a function return value of TYPE
2791 from VALBUF into REGCACHE. */
2794 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2795 struct regcache *regcache, const gdb_byte *valbuf)
2797 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2798 int len = TYPE_LENGTH (type);
2800 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2803 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2805 if (tdep->st0_regnum < 0)
2807 warning (_("Cannot set floating-point return value."));
2811 /* Returning floating-point values is a bit tricky. Apart from
2812 storing the return value in %st(0), we have to simulate the
2813 state of the FPU at function return point. */
2815 /* Convert the value found in VALBUF to the extended
2816 floating-point format used by the FPU. This is probably
2817 not exactly how it would happen on the target itself, but
2818 it is the best we can do. */
2819 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
2820 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2822 /* Set the top of the floating-point register stack to 7. The
2823 actual value doesn't really matter, but 7 is what a normal
2824 function return would end up with if the program started out
2825 with a freshly initialized FPU. */
2826 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2828 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2830 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2831 the floating-point register stack to 7, the appropriate value
2832 for the tag word is 0x3fff. */
2833 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2837 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2838 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2840 if (len <= low_size)
2841 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2842 else if (len <= (low_size + high_size))
2844 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2845 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
2846 len - low_size, valbuf + low_size);
2849 internal_error (__FILE__, __LINE__,
2850 _("Cannot store return value of %d bytes long."), len);
2855 /* This is the variable that is set with "set struct-convention", and
2856 its legitimate values. */
2857 static const char default_struct_convention[] = "default";
2858 static const char pcc_struct_convention[] = "pcc";
2859 static const char reg_struct_convention[] = "reg";
2860 static const char *const valid_conventions[] =
2862 default_struct_convention,
2863 pcc_struct_convention,
2864 reg_struct_convention,
2867 static const char *struct_convention = default_struct_convention;
2869 /* Return non-zero if TYPE, which is assumed to be a structure,
2870 a union type, or an array type, should be returned in registers
2871 for architecture GDBARCH. */
2874 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2876 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2877 enum type_code code = TYPE_CODE (type);
2878 int len = TYPE_LENGTH (type);
2880 gdb_assert (code == TYPE_CODE_STRUCT
2881 || code == TYPE_CODE_UNION
2882 || code == TYPE_CODE_ARRAY);
2884 if (struct_convention == pcc_struct_convention
2885 || (struct_convention == default_struct_convention
2886 && tdep->struct_return == pcc_struct_return))
2889 /* Structures consisting of a single `float', `double' or 'long
2890 double' member are returned in %st(0). */
2891 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2893 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2894 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2895 return (len == 4 || len == 8 || len == 12);
2898 return (len == 1 || len == 2 || len == 4 || len == 8);
2901 /* Determine, for architecture GDBARCH, how a return value of TYPE
2902 should be returned. If it is supposed to be returned in registers,
2903 and READBUF is non-zero, read the appropriate value from REGCACHE,
2904 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2905 from WRITEBUF into REGCACHE. */
2907 static enum return_value_convention
2908 i386_return_value (struct gdbarch *gdbarch, struct value *function,
2909 struct type *type, struct regcache *regcache,
2910 gdb_byte *readbuf, const gdb_byte *writebuf)
2912 enum type_code code = TYPE_CODE (type);
2914 if (((code == TYPE_CODE_STRUCT
2915 || code == TYPE_CODE_UNION
2916 || code == TYPE_CODE_ARRAY)
2917 && !i386_reg_struct_return_p (gdbarch, type))
2918 /* Complex double and long double uses the struct return covention. */
2919 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16)
2920 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24)
2921 /* 128-bit decimal float uses the struct return convention. */
2922 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2924 /* The System V ABI says that:
2926 "A function that returns a structure or union also sets %eax
2927 to the value of the original address of the caller's area
2928 before it returns. Thus when the caller receives control
2929 again, the address of the returned object resides in register
2930 %eax and can be used to access the object."
2932 So the ABI guarantees that we can always find the return
2933 value just after the function has returned. */
2935 /* Note that the ABI doesn't mention functions returning arrays,
2936 which is something possible in certain languages such as Ada.
2937 In this case, the value is returned as if it was wrapped in
2938 a record, so the convention applied to records also applies
2945 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2946 read_memory (addr, readbuf, TYPE_LENGTH (type));
2949 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2952 /* This special case is for structures consisting of a single
2953 `float', `double' or 'long double' member. These structures are
2954 returned in %st(0). For these structures, we call ourselves
2955 recursively, changing TYPE into the type of the first member of
2956 the structure. Since that should work for all structures that
2957 have only one member, we don't bother to check the member's type
2959 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2961 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2962 return i386_return_value (gdbarch, function, type, regcache,
2967 i386_extract_return_value (gdbarch, type, regcache, readbuf);
2969 i386_store_return_value (gdbarch, type, regcache, writebuf);
2971 return RETURN_VALUE_REGISTER_CONVENTION;
2976 i387_ext_type (struct gdbarch *gdbarch)
2978 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2980 if (!tdep->i387_ext_type)
2982 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
2983 gdb_assert (tdep->i387_ext_type != NULL);
2986 return tdep->i387_ext_type;
2989 /* Construct type for pseudo BND registers. We can't use
2990 tdesc_find_type since a complement of one value has to be used
2991 to describe the upper bound. */
2993 static struct type *
2994 i386_bnd_type (struct gdbarch *gdbarch)
2996 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2999 if (!tdep->i386_bnd_type)
3001 struct type *t, *bound_t;
3002 const struct builtin_type *bt = builtin_type (gdbarch);
3004 /* The type we're building is described bellow: */
3009 void *ubound; /* One complement of raw ubound field. */
3013 t = arch_composite_type (gdbarch,
3014 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT);
3016 append_composite_type_field (t, "lbound", bt->builtin_data_ptr);
3017 append_composite_type_field (t, "ubound", bt->builtin_data_ptr);
3019 TYPE_NAME (t) = "builtin_type_bound128";
3020 tdep->i386_bnd_type = t;
3023 return tdep->i386_bnd_type;
3026 /* Construct vector type for pseudo ZMM registers. We can't use
3027 tdesc_find_type since ZMM isn't described in target description. */
3029 static struct type *
3030 i386_zmm_type (struct gdbarch *gdbarch)
3032 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3034 if (!tdep->i386_zmm_type)
3036 const struct builtin_type *bt = builtin_type (gdbarch);
3038 /* The type we're building is this: */
3040 union __gdb_builtin_type_vec512i
3042 int128_t uint128[4];
3043 int64_t v4_int64[8];
3044 int32_t v8_int32[16];
3045 int16_t v16_int16[32];
3046 int8_t v32_int8[64];
3047 double v4_double[8];
3054 t = arch_composite_type (gdbarch,
3055 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION);
3056 append_composite_type_field (t, "v16_float",
3057 init_vector_type (bt->builtin_float, 16));
3058 append_composite_type_field (t, "v8_double",
3059 init_vector_type (bt->builtin_double, 8));
3060 append_composite_type_field (t, "v64_int8",
3061 init_vector_type (bt->builtin_int8, 64));
3062 append_composite_type_field (t, "v32_int16",
3063 init_vector_type (bt->builtin_int16, 32));
3064 append_composite_type_field (t, "v16_int32",
3065 init_vector_type (bt->builtin_int32, 16));
3066 append_composite_type_field (t, "v8_int64",
3067 init_vector_type (bt->builtin_int64, 8));
3068 append_composite_type_field (t, "v4_int128",
3069 init_vector_type (bt->builtin_int128, 4));
3071 TYPE_VECTOR (t) = 1;
3072 TYPE_NAME (t) = "builtin_type_vec512i";
3073 tdep->i386_zmm_type = t;
3076 return tdep->i386_zmm_type;
3079 /* Construct vector type for pseudo YMM registers. We can't use
3080 tdesc_find_type since YMM isn't described in target description. */
3082 static struct type *
3083 i386_ymm_type (struct gdbarch *gdbarch)
3085 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3087 if (!tdep->i386_ymm_type)
3089 const struct builtin_type *bt = builtin_type (gdbarch);
3091 /* The type we're building is this: */
3093 union __gdb_builtin_type_vec256i
3095 int128_t uint128[2];
3096 int64_t v2_int64[4];
3097 int32_t v4_int32[8];
3098 int16_t v8_int16[16];
3099 int8_t v16_int8[32];
3100 double v2_double[4];
3107 t = arch_composite_type (gdbarch,
3108 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
3109 append_composite_type_field (t, "v8_float",
3110 init_vector_type (bt->builtin_float, 8));
3111 append_composite_type_field (t, "v4_double",
3112 init_vector_type (bt->builtin_double, 4));
3113 append_composite_type_field (t, "v32_int8",
3114 init_vector_type (bt->builtin_int8, 32));
3115 append_composite_type_field (t, "v16_int16",
3116 init_vector_type (bt->builtin_int16, 16));
3117 append_composite_type_field (t, "v8_int32",
3118 init_vector_type (bt->builtin_int32, 8));
3119 append_composite_type_field (t, "v4_int64",
3120 init_vector_type (bt->builtin_int64, 4));
3121 append_composite_type_field (t, "v2_int128",
3122 init_vector_type (bt->builtin_int128, 2));
3124 TYPE_VECTOR (t) = 1;
3125 TYPE_NAME (t) = "builtin_type_vec256i";
3126 tdep->i386_ymm_type = t;
3129 return tdep->i386_ymm_type;
3132 /* Construct vector type for MMX registers. */
3133 static struct type *
3134 i386_mmx_type (struct gdbarch *gdbarch)
3136 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3138 if (!tdep->i386_mmx_type)
3140 const struct builtin_type *bt = builtin_type (gdbarch);
3142 /* The type we're building is this: */
3144 union __gdb_builtin_type_vec64i
3147 int32_t v2_int32[2];
3148 int16_t v4_int16[4];
3155 t = arch_composite_type (gdbarch,
3156 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
3158 append_composite_type_field (t, "uint64", bt->builtin_int64);
3159 append_composite_type_field (t, "v2_int32",
3160 init_vector_type (bt->builtin_int32, 2));
3161 append_composite_type_field (t, "v4_int16",
3162 init_vector_type (bt->builtin_int16, 4));
3163 append_composite_type_field (t, "v8_int8",
3164 init_vector_type (bt->builtin_int8, 8));
3166 TYPE_VECTOR (t) = 1;
3167 TYPE_NAME (t) = "builtin_type_vec64i";
3168 tdep->i386_mmx_type = t;
3171 return tdep->i386_mmx_type;
3174 /* Return the GDB type object for the "standard" data type of data in
3178 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3180 if (i386_bnd_regnum_p (gdbarch, regnum))
3181 return i386_bnd_type (gdbarch);
3182 if (i386_mmx_regnum_p (gdbarch, regnum))
3183 return i386_mmx_type (gdbarch);
3184 else if (i386_ymm_regnum_p (gdbarch, regnum))
3185 return i386_ymm_type (gdbarch);
3186 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3187 return i386_ymm_type (gdbarch);
3188 else if (i386_zmm_regnum_p (gdbarch, regnum))
3189 return i386_zmm_type (gdbarch);
3192 const struct builtin_type *bt = builtin_type (gdbarch);
3193 if (i386_byte_regnum_p (gdbarch, regnum))
3194 return bt->builtin_int8;
3195 else if (i386_word_regnum_p (gdbarch, regnum))
3196 return bt->builtin_int16;
3197 else if (i386_dword_regnum_p (gdbarch, regnum))
3198 return bt->builtin_int32;
3199 else if (i386_k_regnum_p (gdbarch, regnum))
3200 return bt->builtin_int64;
3203 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3206 /* Map a cooked register onto a raw register or memory. For the i386,
3207 the MMX registers need to be mapped onto floating point registers. */
3210 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
3212 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
3217 mmxreg = regnum - tdep->mm0_regnum;
3218 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
3219 tos = (fstat >> 11) & 0x7;
3220 fpreg = (mmxreg + tos) % 8;
3222 return (I387_ST0_REGNUM (tdep) + fpreg);
3225 /* A helper function for us by i386_pseudo_register_read_value and
3226 amd64_pseudo_register_read_value. It does all the work but reads
3227 the data into an already-allocated value. */
3230 i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
3231 struct regcache *regcache,
3233 struct value *result_value)
3235 gdb_byte raw_buf[MAX_REGISTER_SIZE];
3236 enum register_status status;
3237 gdb_byte *buf = value_contents_raw (result_value);
3239 if (i386_mmx_regnum_p (gdbarch, regnum))
3241 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3243 /* Extract (always little endian). */
3244 status = regcache_raw_read (regcache, fpnum, raw_buf);
3245 if (status != REG_VALID)
3246 mark_value_bytes_unavailable (result_value, 0,
3247 TYPE_LENGTH (value_type (result_value)));
3249 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
3253 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3254 if (i386_bnd_regnum_p (gdbarch, regnum))
3256 regnum -= tdep->bnd0_regnum;
3258 /* Extract (always little endian). Read lower 128bits. */
3259 status = regcache_raw_read (regcache,
3260 I387_BND0R_REGNUM (tdep) + regnum,
3262 if (status != REG_VALID)
3263 mark_value_bytes_unavailable (result_value, 0, 16);
3266 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3267 LONGEST upper, lower;
3268 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3270 lower = extract_unsigned_integer (raw_buf, 8, byte_order);
3271 upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order);
3274 memcpy (buf, &lower, size);
3275 memcpy (buf + size, &upper, size);
3278 else if (i386_k_regnum_p (gdbarch, regnum))
3280 regnum -= tdep->k0_regnum;
3282 /* Extract (always little endian). */
3283 status = regcache_raw_read (regcache,
3284 tdep->k0_regnum + regnum,
3286 if (status != REG_VALID)
3287 mark_value_bytes_unavailable (result_value, 0, 8);
3289 memcpy (buf, raw_buf, 8);
3291 else if (i386_zmm_regnum_p (gdbarch, regnum))
3293 regnum -= tdep->zmm0_regnum;
3295 if (regnum < num_lower_zmm_regs)
3297 /* Extract (always little endian). Read lower 128bits. */
3298 status = regcache_raw_read (regcache,
3299 I387_XMM0_REGNUM (tdep) + regnum,
3301 if (status != REG_VALID)
3302 mark_value_bytes_unavailable (result_value, 0, 16);
3304 memcpy (buf, raw_buf, 16);
3306 /* Extract (always little endian). Read upper 128bits. */
3307 status = regcache_raw_read (regcache,
3308 tdep->ymm0h_regnum + regnum,
3310 if (status != REG_VALID)
3311 mark_value_bytes_unavailable (result_value, 16, 16);
3313 memcpy (buf + 16, raw_buf, 16);
3317 /* Extract (always little endian). Read lower 128bits. */
3318 status = regcache_raw_read (regcache,
3319 I387_XMM16_REGNUM (tdep) + regnum
3320 - num_lower_zmm_regs,
3322 if (status != REG_VALID)
3323 mark_value_bytes_unavailable (result_value, 0, 16);
3325 memcpy (buf, raw_buf, 16);
3327 /* Extract (always little endian). Read upper 128bits. */
3328 status = regcache_raw_read (regcache,
3329 I387_YMM16H_REGNUM (tdep) + regnum
3330 - num_lower_zmm_regs,
3332 if (status != REG_VALID)
3333 mark_value_bytes_unavailable (result_value, 16, 16);
3335 memcpy (buf + 16, raw_buf, 16);
3338 /* Read upper 256bits. */
3339 status = regcache_raw_read (regcache,
3340 tdep->zmm0h_regnum + regnum,
3342 if (status != REG_VALID)
3343 mark_value_bytes_unavailable (result_value, 32, 32);
3345 memcpy (buf + 32, raw_buf, 32);
3347 else if (i386_ymm_regnum_p (gdbarch, regnum))
3349 regnum -= tdep->ymm0_regnum;
3351 /* Extract (always little endian). Read lower 128bits. */
3352 status = regcache_raw_read (regcache,
3353 I387_XMM0_REGNUM (tdep) + regnum,
3355 if (status != REG_VALID)
3356 mark_value_bytes_unavailable (result_value, 0, 16);
3358 memcpy (buf, raw_buf, 16);
3359 /* Read upper 128bits. */
3360 status = regcache_raw_read (regcache,
3361 tdep->ymm0h_regnum + regnum,
3363 if (status != REG_VALID)
3364 mark_value_bytes_unavailable (result_value, 16, 32);
3366 memcpy (buf + 16, raw_buf, 16);
3368 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3370 regnum -= tdep->ymm16_regnum;
3371 /* Extract (always little endian). Read lower 128bits. */
3372 status = regcache_raw_read (regcache,
3373 I387_XMM16_REGNUM (tdep) + regnum,
3375 if (status != REG_VALID)
3376 mark_value_bytes_unavailable (result_value, 0, 16);
3378 memcpy (buf, raw_buf, 16);
3379 /* Read upper 128bits. */
3380 status = regcache_raw_read (regcache,
3381 tdep->ymm16h_regnum + regnum,
3383 if (status != REG_VALID)
3384 mark_value_bytes_unavailable (result_value, 16, 16);
3386 memcpy (buf + 16, raw_buf, 16);
3388 else if (i386_word_regnum_p (gdbarch, regnum))
3390 int gpnum = regnum - tdep->ax_regnum;
3392 /* Extract (always little endian). */
3393 status = regcache_raw_read (regcache, gpnum, raw_buf);
3394 if (status != REG_VALID)
3395 mark_value_bytes_unavailable (result_value, 0,
3396 TYPE_LENGTH (value_type (result_value)));
3398 memcpy (buf, raw_buf, 2);
3400 else if (i386_byte_regnum_p (gdbarch, regnum))
3402 /* Check byte pseudo registers last since this function will
3403 be called from amd64_pseudo_register_read, which handles
3404 byte pseudo registers differently. */
3405 int gpnum = regnum - tdep->al_regnum;
3407 /* Extract (always little endian). We read both lower and
3409 status = regcache_raw_read (regcache, gpnum % 4, raw_buf);
3410 if (status != REG_VALID)
3411 mark_value_bytes_unavailable (result_value, 0,
3412 TYPE_LENGTH (value_type (result_value)));
3413 else if (gpnum >= 4)
3414 memcpy (buf, raw_buf + 1, 1);
3416 memcpy (buf, raw_buf, 1);
3419 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3423 static struct value *
3424 i386_pseudo_register_read_value (struct gdbarch *gdbarch,
3425 struct regcache *regcache,
3428 struct value *result;
3430 result = allocate_value (register_type (gdbarch, regnum));
3431 VALUE_LVAL (result) = lval_register;
3432 VALUE_REGNUM (result) = regnum;
3434 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result);
3440 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3441 int regnum, const gdb_byte *buf)
3443 gdb_byte raw_buf[MAX_REGISTER_SIZE];
3445 if (i386_mmx_regnum_p (gdbarch, regnum))
3447 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3450 regcache_raw_read (regcache, fpnum, raw_buf);
3451 /* ... Modify ... (always little endian). */
3452 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
3454 regcache_raw_write (regcache, fpnum, raw_buf);
3458 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3460 if (i386_bnd_regnum_p (gdbarch, regnum))
3462 ULONGEST upper, lower;
3463 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3464 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3466 /* New values from input value. */
3467 regnum -= tdep->bnd0_regnum;
3468 lower = extract_unsigned_integer (buf, size, byte_order);
3469 upper = extract_unsigned_integer (buf + size, size, byte_order);
3471 /* Fetching register buffer. */
3472 regcache_raw_read (regcache,
3473 I387_BND0R_REGNUM (tdep) + regnum,
3478 /* Set register bits. */
3479 memcpy (raw_buf, &lower, 8);
3480 memcpy (raw_buf + 8, &upper, 8);
3483 regcache_raw_write (regcache,
3484 I387_BND0R_REGNUM (tdep) + regnum,
3487 else if (i386_k_regnum_p (gdbarch, regnum))
3489 regnum -= tdep->k0_regnum;
3491 regcache_raw_write (regcache,
3492 tdep->k0_regnum + regnum,
3495 else if (i386_zmm_regnum_p (gdbarch, regnum))
3497 regnum -= tdep->zmm0_regnum;
3499 if (regnum < num_lower_zmm_regs)
3501 /* Write lower 128bits. */
3502 regcache_raw_write (regcache,
3503 I387_XMM0_REGNUM (tdep) + regnum,
3505 /* Write upper 128bits. */
3506 regcache_raw_write (regcache,
3507 I387_YMM0_REGNUM (tdep) + regnum,
3512 /* Write lower 128bits. */
3513 regcache_raw_write (regcache,
3514 I387_XMM16_REGNUM (tdep) + regnum
3515 - num_lower_zmm_regs,
3517 /* Write upper 128bits. */
3518 regcache_raw_write (regcache,
3519 I387_YMM16H_REGNUM (tdep) + regnum
3520 - num_lower_zmm_regs,
3523 /* Write upper 256bits. */
3524 regcache_raw_write (regcache,
3525 tdep->zmm0h_regnum + regnum,
3528 else if (i386_ymm_regnum_p (gdbarch, regnum))
3530 regnum -= tdep->ymm0_regnum;
3532 /* ... Write lower 128bits. */
3533 regcache_raw_write (regcache,
3534 I387_XMM0_REGNUM (tdep) + regnum,
3536 /* ... Write upper 128bits. */
3537 regcache_raw_write (regcache,
3538 tdep->ymm0h_regnum + regnum,
3541 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3543 regnum -= tdep->ymm16_regnum;
3545 /* ... Write lower 128bits. */
3546 regcache_raw_write (regcache,
3547 I387_XMM16_REGNUM (tdep) + regnum,
3549 /* ... Write upper 128bits. */
3550 regcache_raw_write (regcache,
3551 tdep->ymm16h_regnum + regnum,
3554 else if (i386_word_regnum_p (gdbarch, regnum))
3556 int gpnum = regnum - tdep->ax_regnum;
3559 regcache_raw_read (regcache, gpnum, raw_buf);
3560 /* ... Modify ... (always little endian). */
3561 memcpy (raw_buf, buf, 2);
3563 regcache_raw_write (regcache, gpnum, raw_buf);
3565 else if (i386_byte_regnum_p (gdbarch, regnum))
3567 /* Check byte pseudo registers last since this function will
3568 be called from amd64_pseudo_register_read, which handles
3569 byte pseudo registers differently. */
3570 int gpnum = regnum - tdep->al_regnum;
3572 /* Read ... We read both lower and upper registers. */
3573 regcache_raw_read (regcache, gpnum % 4, raw_buf);
3574 /* ... Modify ... (always little endian). */
3576 memcpy (raw_buf + 1, buf, 1);
3578 memcpy (raw_buf, buf, 1);
3580 regcache_raw_write (regcache, gpnum % 4, raw_buf);
3583 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3588 /* Return the register number of the register allocated by GCC after
3589 REGNUM, or -1 if there is no such register. */
3592 i386_next_regnum (int regnum)
3594 /* GCC allocates the registers in the order:
3596 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3598 Since storing a variable in %esp doesn't make any sense we return
3599 -1 for %ebp and for %esp itself. */
3600 static int next_regnum[] =
3602 I386_EDX_REGNUM, /* Slot for %eax. */
3603 I386_EBX_REGNUM, /* Slot for %ecx. */
3604 I386_ECX_REGNUM, /* Slot for %edx. */
3605 I386_ESI_REGNUM, /* Slot for %ebx. */
3606 -1, -1, /* Slots for %esp and %ebp. */
3607 I386_EDI_REGNUM, /* Slot for %esi. */
3608 I386_EBP_REGNUM /* Slot for %edi. */
3611 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
3612 return next_regnum[regnum];
3617 /* Return nonzero if a value of type TYPE stored in register REGNUM
3618 needs any special handling. */
3621 i386_convert_register_p (struct gdbarch *gdbarch,
3622 int regnum, struct type *type)
3624 int len = TYPE_LENGTH (type);
3626 /* Values may be spread across multiple registers. Most debugging
3627 formats aren't expressive enough to specify the locations, so
3628 some heuristics is involved. Right now we only handle types that
3629 have a length that is a multiple of the word size, since GCC
3630 doesn't seem to put any other types into registers. */
3631 if (len > 4 && len % 4 == 0)
3633 int last_regnum = regnum;
3637 last_regnum = i386_next_regnum (last_regnum);
3641 if (last_regnum != -1)
3645 return i387_convert_register_p (gdbarch, regnum, type);
3648 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3649 return its contents in TO. */
3652 i386_register_to_value (struct frame_info *frame, int regnum,
3653 struct type *type, gdb_byte *to,
3654 int *optimizedp, int *unavailablep)
3656 struct gdbarch *gdbarch = get_frame_arch (frame);
3657 int len = TYPE_LENGTH (type);
3659 if (i386_fp_regnum_p (gdbarch, regnum))
3660 return i387_register_to_value (frame, regnum, type, to,
3661 optimizedp, unavailablep);
3663 /* Read a value spread across multiple registers. */
3665 gdb_assert (len > 4 && len % 4 == 0);
3669 gdb_assert (regnum != -1);
3670 gdb_assert (register_size (gdbarch, regnum) == 4);
3672 if (!get_frame_register_bytes (frame, regnum, 0,
3673 register_size (gdbarch, regnum),
3674 to, optimizedp, unavailablep))
3677 regnum = i386_next_regnum (regnum);
3682 *optimizedp = *unavailablep = 0;
3686 /* Write the contents FROM of a value of type TYPE into register
3687 REGNUM in frame FRAME. */
3690 i386_value_to_register (struct frame_info *frame, int regnum,
3691 struct type *type, const gdb_byte *from)
3693 int len = TYPE_LENGTH (type);
3695 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
3697 i387_value_to_register (frame, regnum, type, from);
3701 /* Write a value spread across multiple registers. */
3703 gdb_assert (len > 4 && len % 4 == 0);
3707 gdb_assert (regnum != -1);
3708 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
3710 put_frame_register (frame, regnum, from);
3711 regnum = i386_next_regnum (regnum);
3717 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3718 in the general-purpose register set REGSET to register cache
3719 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3722 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
3723 int regnum, const void *gregs, size_t len)
3725 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3726 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3727 const gdb_byte *regs = gregs;
3730 gdb_assert (len == tdep->sizeof_gregset);
3732 for (i = 0; i < tdep->gregset_num_regs; i++)
3734 if ((regnum == i || regnum == -1)
3735 && tdep->gregset_reg_offset[i] != -1)
3736 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
3740 /* Collect register REGNUM from the register cache REGCACHE and store
3741 it in the buffer specified by GREGS and LEN as described by the
3742 general-purpose register set REGSET. If REGNUM is -1, do this for
3743 all registers in REGSET. */
3746 i386_collect_gregset (const struct regset *regset,
3747 const struct regcache *regcache,
3748 int regnum, void *gregs, size_t len)
3750 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3751 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3752 gdb_byte *regs = gregs;
3755 gdb_assert (len == tdep->sizeof_gregset);
3757 for (i = 0; i < tdep->gregset_num_regs; i++)
3759 if ((regnum == i || regnum == -1)
3760 && tdep->gregset_reg_offset[i] != -1)
3761 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
3765 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3766 in the floating-point register set REGSET to register cache
3767 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3770 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
3771 int regnum, const void *fpregs, size_t len)
3773 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3774 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3776 if (len == I387_SIZEOF_FXSAVE)
3778 i387_supply_fxsave (regcache, regnum, fpregs);
3782 gdb_assert (len == tdep->sizeof_fpregset);
3783 i387_supply_fsave (regcache, regnum, fpregs);
3786 /* Collect register REGNUM from the register cache REGCACHE and store
3787 it in the buffer specified by FPREGS and LEN as described by the
3788 floating-point register set REGSET. If REGNUM is -1, do this for
3789 all registers in REGSET. */
3792 i386_collect_fpregset (const struct regset *regset,
3793 const struct regcache *regcache,
3794 int regnum, void *fpregs, size_t len)
3796 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3797 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3799 if (len == I387_SIZEOF_FXSAVE)
3801 i387_collect_fxsave (regcache, regnum, fpregs);
3805 gdb_assert (len == tdep->sizeof_fpregset);
3806 i387_collect_fsave (regcache, regnum, fpregs);
3809 /* Register set definitions. */
3811 const struct regset i386_gregset =
3813 NULL, i386_supply_gregset, i386_collect_gregset
3816 const struct regset i386_fpregset =
3818 NULL, i386_supply_fpregset, i386_collect_fpregset
3821 /* Default iterator over core file register note sections. */
3824 i386_iterate_over_regset_sections (struct gdbarch *gdbarch,
3825 iterate_over_regset_sections_cb *cb,
3827 const struct regcache *regcache)
3829 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3831 cb (".reg", tdep->sizeof_gregset, &i386_gregset, NULL, cb_data);
3832 if (tdep->sizeof_fpregset)
3833 cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
3837 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3840 i386_pe_skip_trampoline_code (struct frame_info *frame,
3841 CORE_ADDR pc, char *name)
3843 struct gdbarch *gdbarch = get_frame_arch (frame);
3844 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3847 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
3849 unsigned long indirect =
3850 read_memory_unsigned_integer (pc + 2, 4, byte_order);
3851 struct minimal_symbol *indsym =
3852 indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0;
3853 const char *symname = indsym ? MSYMBOL_LINKAGE_NAME (indsym) : 0;
3857 if (strncmp (symname, "__imp_", 6) == 0
3858 || strncmp (symname, "_imp_", 5) == 0)
3860 read_memory_unsigned_integer (indirect, 4, byte_order);
3863 return 0; /* Not a trampoline. */
3867 /* Return whether the THIS_FRAME corresponds to a sigtramp
3871 i386_sigtramp_p (struct frame_info *this_frame)
3873 CORE_ADDR pc = get_frame_pc (this_frame);
3876 find_pc_partial_function (pc, &name, NULL, NULL);
3877 return (name && strcmp ("_sigtramp", name) == 0);
3881 /* We have two flavours of disassembly. The machinery on this page
3882 deals with switching between those. */
3885 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
3887 gdb_assert (disassembly_flavor == att_flavor
3888 || disassembly_flavor == intel_flavor);
3890 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3891 constified, cast to prevent a compiler warning. */
3892 info->disassembler_options = (char *) disassembly_flavor;
3894 return print_insn_i386 (pc, info);
3898 /* There are a few i386 architecture variants that differ only
3899 slightly from the generic i386 target. For now, we don't give them
3900 their own source file, but include them here. As a consequence,
3901 they'll always be included. */
3903 /* System V Release 4 (SVR4). */
3905 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3909 i386_svr4_sigtramp_p (struct frame_info *this_frame)
3911 CORE_ADDR pc = get_frame_pc (this_frame);
3914 /* The origin of these symbols is currently unknown. */
3915 find_pc_partial_function (pc, &name, NULL, NULL);
3916 return (name && (strcmp ("_sigreturn", name) == 0
3917 || strcmp ("sigvechandler", name) == 0));
3920 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3921 address of the associated sigcontext (ucontext) structure. */
3924 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
3926 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3927 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3931 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
3932 sp = extract_unsigned_integer (buf, 4, byte_order);
3934 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
3939 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
3943 i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s)
3945 return (*s == '$' /* Literal number. */
3946 || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */
3947 || (*s == '(' && s[1] == '%') /* Register indirection. */
3948 || (*s == '%' && isalpha (s[1]))); /* Register access. */
3951 /* Helper function for i386_stap_parse_special_token.
3953 This function parses operands of the form `-8+3+1(%rbp)', which
3954 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
3956 Return 1 if the operand was parsed successfully, zero
3960 i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch,
3961 struct stap_parse_info *p)
3963 const char *s = p->arg;
3965 if (isdigit (*s) || *s == '-' || *s == '+')
3969 long displacements[3];
3985 if (!isdigit ((unsigned char) *s))
3988 displacements[0] = strtol (s, &endp, 10);
3991 if (*s != '+' && *s != '-')
3993 /* We are not dealing with a triplet. */
4006 if (!isdigit ((unsigned char) *s))
4009 displacements[1] = strtol (s, &endp, 10);
4012 if (*s != '+' && *s != '-')
4014 /* We are not dealing with a triplet. */
4027 if (!isdigit ((unsigned char) *s))
4030 displacements[2] = strtol (s, &endp, 10);
4033 if (*s != '(' || s[1] != '%')
4039 while (isalnum (*s))
4045 len = s - start - 1;
4046 regname = alloca (len + 1);
4048 strncpy (regname, start, len);
4049 regname[len] = '\0';
4051 if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1)
4052 error (_("Invalid register name `%s' on expression `%s'."),
4053 regname, p->saved_arg);
4055 for (i = 0; i < 3; i++)
4057 write_exp_elt_opcode (&p->pstate, OP_LONG);
4059 (&p->pstate, builtin_type (gdbarch)->builtin_long);
4060 write_exp_elt_longcst (&p->pstate, displacements[i]);
4061 write_exp_elt_opcode (&p->pstate, OP_LONG);
4063 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4066 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4069 write_exp_string (&p->pstate, str);
4070 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4072 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4073 write_exp_elt_type (&p->pstate,
4074 builtin_type (gdbarch)->builtin_data_ptr);
4075 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4077 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4078 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4079 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4081 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4082 write_exp_elt_type (&p->pstate,
4083 lookup_pointer_type (p->arg_type));
4084 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4086 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4096 /* Helper function for i386_stap_parse_special_token.
4098 This function parses operands of the form `register base +
4099 (register index * size) + offset', as represented in
4100 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4102 Return 1 if the operand was parsed successfully, zero
4106 i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch,
4107 struct stap_parse_info *p)
4109 const char *s = p->arg;
4111 if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+')
4113 int offset_minus = 0;
4122 struct stoken base_token, index_token;
4132 if (offset_minus && !isdigit (*s))
4139 offset = strtol (s, &endp, 10);
4143 if (*s != '(' || s[1] != '%')
4149 while (isalnum (*s))
4152 if (*s != ',' || s[1] != '%')
4155 len_base = s - start;
4156 base = alloca (len_base + 1);
4157 strncpy (base, start, len_base);
4158 base[len_base] = '\0';
4160 if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1)
4161 error (_("Invalid register name `%s' on expression `%s'."),
4162 base, p->saved_arg);
4167 while (isalnum (*s))
4170 len_index = s - start;
4171 index = alloca (len_index + 1);
4172 strncpy (index, start, len_index);
4173 index[len_index] = '\0';
4175 if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1)
4176 error (_("Invalid register name `%s' on expression `%s'."),
4177 index, p->saved_arg);
4179 if (*s != ',' && *s != ')')
4195 size = strtol (s, &endp, 10);
4206 write_exp_elt_opcode (&p->pstate, OP_LONG);
4207 write_exp_elt_type (&p->pstate,
4208 builtin_type (gdbarch)->builtin_long);
4209 write_exp_elt_longcst (&p->pstate, offset);
4210 write_exp_elt_opcode (&p->pstate, OP_LONG);
4212 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4215 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4216 base_token.ptr = base;
4217 base_token.length = len_base;
4218 write_exp_string (&p->pstate, base_token);
4219 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4222 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4224 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4225 index_token.ptr = index;
4226 index_token.length = len_index;
4227 write_exp_string (&p->pstate, index_token);
4228 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4232 write_exp_elt_opcode (&p->pstate, OP_LONG);
4233 write_exp_elt_type (&p->pstate,
4234 builtin_type (gdbarch)->builtin_long);
4235 write_exp_elt_longcst (&p->pstate, size);
4236 write_exp_elt_opcode (&p->pstate, OP_LONG);
4238 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4239 write_exp_elt_opcode (&p->pstate, BINOP_MUL);
4242 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4244 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4245 write_exp_elt_type (&p->pstate,
4246 lookup_pointer_type (p->arg_type));
4247 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4249 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4259 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4263 i386_stap_parse_special_token (struct gdbarch *gdbarch,
4264 struct stap_parse_info *p)
4266 /* In order to parse special tokens, we use a state-machine that go
4267 through every known token and try to get a match. */
4271 THREE_ARG_DISPLACEMENT,
4275 current_state = TRIPLET;
4277 /* The special tokens to be parsed here are:
4279 - `register base + (register index * size) + offset', as represented
4280 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4282 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4283 `*(-8 + 3 - 1 + (void *) $eax)'. */
4285 while (current_state != DONE)
4287 switch (current_state)
4290 if (i386_stap_parse_special_token_triplet (gdbarch, p))
4294 case THREE_ARG_DISPLACEMENT:
4295 if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p))
4300 /* Advancing to the next state. */
4309 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always
4310 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */
4313 i386_gnu_triplet_regexp (struct gdbarch *gdbarch)
4315 return "(x86_64|i.86)";
4323 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4325 static const char *const stap_integer_prefixes[] = { "$", NULL };
4326 static const char *const stap_register_prefixes[] = { "%", NULL };
4327 static const char *const stap_register_indirection_prefixes[] = { "(",
4329 static const char *const stap_register_indirection_suffixes[] = { ")",
4332 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4333 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4335 /* Registering SystemTap handlers. */
4336 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
4337 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
4338 set_gdbarch_stap_register_indirection_prefixes (gdbarch,
4339 stap_register_indirection_prefixes);
4340 set_gdbarch_stap_register_indirection_suffixes (gdbarch,
4341 stap_register_indirection_suffixes);
4342 set_gdbarch_stap_is_single_operand (gdbarch,
4343 i386_stap_is_single_operand);
4344 set_gdbarch_stap_parse_special_token (gdbarch,
4345 i386_stap_parse_special_token);
4347 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
4350 /* System V Release 4 (SVR4). */
4353 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4355 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4357 /* System V Release 4 uses ELF. */
4358 i386_elf_init_abi (info, gdbarch);
4360 /* System V Release 4 has shared libraries. */
4361 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
4363 tdep->sigtramp_p = i386_svr4_sigtramp_p;
4364 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
4365 tdep->sc_pc_offset = 36 + 14 * 4;
4366 tdep->sc_sp_offset = 36 + 17 * 4;
4368 tdep->jb_pc_offset = 20;
4374 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4376 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4378 /* DJGPP doesn't have any special frames for signal handlers. */
4379 tdep->sigtramp_p = NULL;
4381 tdep->jb_pc_offset = 36;
4383 /* DJGPP does not support the SSE registers. */
4384 if (! tdesc_has_registers (info.target_desc))
4385 tdep->tdesc = tdesc_i386_mmx;
4387 /* Native compiler is GCC, which uses the SVR4 register numbering
4388 even in COFF and STABS. See the comment in i386_gdbarch_init,
4389 before the calls to set_gdbarch_stab_reg_to_regnum and
4390 set_gdbarch_sdb_reg_to_regnum. */
4391 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4392 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4394 set_gdbarch_has_dos_based_file_system (gdbarch, 1);
4396 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
4400 /* i386 register groups. In addition to the normal groups, add "mmx"
4403 static struct reggroup *i386_sse_reggroup;
4404 static struct reggroup *i386_mmx_reggroup;
4407 i386_init_reggroups (void)
4409 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
4410 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
4414 i386_add_reggroups (struct gdbarch *gdbarch)
4416 reggroup_add (gdbarch, i386_sse_reggroup);
4417 reggroup_add (gdbarch, i386_mmx_reggroup);
4418 reggroup_add (gdbarch, general_reggroup);
4419 reggroup_add (gdbarch, float_reggroup);
4420 reggroup_add (gdbarch, all_reggroup);
4421 reggroup_add (gdbarch, save_reggroup);
4422 reggroup_add (gdbarch, restore_reggroup);
4423 reggroup_add (gdbarch, vector_reggroup);
4424 reggroup_add (gdbarch, system_reggroup);
4428 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
4429 struct reggroup *group)
4431 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4432 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
4433 ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p,
4434 bndr_regnum_p, bnd_regnum_p, k_regnum_p, zmm_regnum_p, zmmh_regnum_p,
4435 zmm_avx512_regnum_p, mpx_ctrl_regnum_p, xmm_avx512_regnum_p,
4436 avx512_p, avx_p, sse_p;
4438 /* Don't include pseudo registers, except for MMX, in any register
4440 if (i386_byte_regnum_p (gdbarch, regnum))
4443 if (i386_word_regnum_p (gdbarch, regnum))
4446 if (i386_dword_regnum_p (gdbarch, regnum))
4449 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
4450 if (group == i386_mmx_reggroup)
4451 return mmx_regnum_p;
4453 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
4454 xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum);
4455 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
4456 if (group == i386_sse_reggroup)
4457 return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p;
4459 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
4460 ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum);
4461 zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum);
4463 avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4464 == X86_XSTATE_AVX512_MASK);
4465 avx_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4466 == X86_XSTATE_AVX_MASK) && !avx512_p;
4467 sse_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4468 == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p;
4470 if (group == vector_reggroup)
4471 return (mmx_regnum_p
4472 || (zmm_regnum_p && avx512_p)
4473 || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p)
4474 || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p)
4477 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
4478 || i386_fpc_regnum_p (gdbarch, regnum));
4479 if (group == float_reggroup)
4482 /* For "info reg all", don't include upper YMM registers nor XMM
4483 registers when AVX is supported. */
4484 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
4485 ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum);
4486 zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum);
4487 if (group == all_reggroup
4488 && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p)
4489 || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p)
4491 || ymmh_avx512_regnum_p
4495 bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum);
4496 if (group == all_reggroup
4497 && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4498 return bnd_regnum_p;
4500 bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum);
4501 if (group == all_reggroup
4502 && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4505 mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum);
4506 if (group == all_reggroup
4507 && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4508 return mpx_ctrl_regnum_p;
4510 if (group == general_reggroup)
4511 return (!fp_regnum_p
4515 && !xmm_avx512_regnum_p
4518 && !ymm_avx512_regnum_p
4519 && !ymmh_avx512_regnum_p
4522 && !mpx_ctrl_regnum_p
4526 return default_register_reggroup_p (gdbarch, regnum, group);
4530 /* Get the ARGIth function argument for the current function. */
4533 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
4536 struct gdbarch *gdbarch = get_frame_arch (frame);
4537 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4538 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
4539 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
4542 #define PREFIX_REPZ 0x01
4543 #define PREFIX_REPNZ 0x02
4544 #define PREFIX_LOCK 0x04
4545 #define PREFIX_DATA 0x08
4546 #define PREFIX_ADDR 0x10
4558 /* i386 arith/logic operations */
4571 struct i386_record_s
4573 struct gdbarch *gdbarch;
4574 struct regcache *regcache;
4575 CORE_ADDR orig_addr;
4581 uint8_t mod, reg, rm;
4590 /* Parse the "modrm" part of the memory address irp->addr points at.
4591 Returns -1 if something goes wrong, 0 otherwise. */
4594 i386_record_modrm (struct i386_record_s *irp)
4596 struct gdbarch *gdbarch = irp->gdbarch;
4598 if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1))
4602 irp->mod = (irp->modrm >> 6) & 3;
4603 irp->reg = (irp->modrm >> 3) & 7;
4604 irp->rm = irp->modrm & 7;
4609 /* Extract the memory address that the current instruction writes to,
4610 and return it in *ADDR. Return -1 if something goes wrong. */
4613 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
4615 struct gdbarch *gdbarch = irp->gdbarch;
4616 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4621 if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM])
4628 uint8_t base = irp->rm;
4633 if (record_read_memory (gdbarch, irp->addr, &byte, 1))
4636 scale = (byte >> 6) & 3;
4637 index = ((byte >> 3) & 7) | irp->rex_x;
4645 if ((base & 7) == 5)
4648 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4651 *addr = extract_signed_integer (buf, 4, byte_order);
4652 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
4653 *addr += irp->addr + irp->rip_offset;
4657 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4660 *addr = (int8_t) buf[0];
4663 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4665 *addr = extract_signed_integer (buf, 4, byte_order);
4673 if (base == 4 && irp->popl_esp_hack)
4674 *addr += irp->popl_esp_hack;
4675 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
4678 if (irp->aflag == 2)
4683 *addr = (uint32_t) (offset64 + *addr);
4685 if (havesib && (index != 4 || scale != 0))
4687 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
4689 if (irp->aflag == 2)
4690 *addr += offset64 << scale;
4692 *addr = (uint32_t) (*addr + (offset64 << scale));
4697 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4698 address from 32-bit to 64-bit. */
4699 *addr = (uint32_t) *addr;
4710 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4713 *addr = extract_signed_integer (buf, 2, byte_order);
4719 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4722 *addr = (int8_t) buf[0];
4725 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4728 *addr = extract_signed_integer (buf, 2, byte_order);
4735 regcache_raw_read_unsigned (irp->regcache,
4736 irp->regmap[X86_RECORD_REBX_REGNUM],
4738 *addr = (uint32_t) (*addr + offset64);
4739 regcache_raw_read_unsigned (irp->regcache,
4740 irp->regmap[X86_RECORD_RESI_REGNUM],
4742 *addr = (uint32_t) (*addr + offset64);
4745 regcache_raw_read_unsigned (irp->regcache,
4746 irp->regmap[X86_RECORD_REBX_REGNUM],
4748 *addr = (uint32_t) (*addr + offset64);
4749 regcache_raw_read_unsigned (irp->regcache,
4750 irp->regmap[X86_RECORD_REDI_REGNUM],
4752 *addr = (uint32_t) (*addr + offset64);
4755 regcache_raw_read_unsigned (irp->regcache,
4756 irp->regmap[X86_RECORD_REBP_REGNUM],
4758 *addr = (uint32_t) (*addr + offset64);
4759 regcache_raw_read_unsigned (irp->regcache,
4760 irp->regmap[X86_RECORD_RESI_REGNUM],
4762 *addr = (uint32_t) (*addr + offset64);
4765 regcache_raw_read_unsigned (irp->regcache,
4766 irp->regmap[X86_RECORD_REBP_REGNUM],
4768 *addr = (uint32_t) (*addr + offset64);
4769 regcache_raw_read_unsigned (irp->regcache,
4770 irp->regmap[X86_RECORD_REDI_REGNUM],
4772 *addr = (uint32_t) (*addr + offset64);
4775 regcache_raw_read_unsigned (irp->regcache,
4776 irp->regmap[X86_RECORD_RESI_REGNUM],
4778 *addr = (uint32_t) (*addr + offset64);
4781 regcache_raw_read_unsigned (irp->regcache,
4782 irp->regmap[X86_RECORD_REDI_REGNUM],
4784 *addr = (uint32_t) (*addr + offset64);
4787 regcache_raw_read_unsigned (irp->regcache,
4788 irp->regmap[X86_RECORD_REBP_REGNUM],
4790 *addr = (uint32_t) (*addr + offset64);
4793 regcache_raw_read_unsigned (irp->regcache,
4794 irp->regmap[X86_RECORD_REBX_REGNUM],
4796 *addr = (uint32_t) (*addr + offset64);
4806 /* Record the address and contents of the memory that will be changed
4807 by the current instruction. Return -1 if something goes wrong, 0
4811 i386_record_lea_modrm (struct i386_record_s *irp)
4813 struct gdbarch *gdbarch = irp->gdbarch;
4816 if (irp->override >= 0)
4818 if (record_full_memory_query)
4822 target_terminal_ours ();
4824 Process record ignores the memory change of instruction at address %s\n\
4825 because it can't get the value of the segment register.\n\
4826 Do you want to stop the program?"),
4827 paddress (gdbarch, irp->orig_addr));
4828 target_terminal_inferior ();
4836 if (i386_record_lea_modrm_addr (irp, &addr))
4839 if (record_full_arch_list_add_mem (addr, 1 << irp->ot))
4845 /* Record the effects of a push operation. Return -1 if something
4846 goes wrong, 0 otherwise. */
4849 i386_record_push (struct i386_record_s *irp, int size)
4853 if (record_full_arch_list_add_reg (irp->regcache,
4854 irp->regmap[X86_RECORD_RESP_REGNUM]))
4856 regcache_raw_read_unsigned (irp->regcache,
4857 irp->regmap[X86_RECORD_RESP_REGNUM],
4859 if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size))
4866 /* Defines contents to record. */
4867 #define I386_SAVE_FPU_REGS 0xfffd
4868 #define I386_SAVE_FPU_ENV 0xfffe
4869 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4871 /* Record the values of the floating point registers which will be
4872 changed by the current instruction. Returns -1 if something is
4873 wrong, 0 otherwise. */
4875 static int i386_record_floats (struct gdbarch *gdbarch,
4876 struct i386_record_s *ir,
4879 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4882 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4883 happen. Currently we store st0-st7 registers, but we need not store all
4884 registers all the time, in future we use ftag register and record only
4885 those who are not marked as an empty. */
4887 if (I386_SAVE_FPU_REGS == iregnum)
4889 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
4891 if (record_full_arch_list_add_reg (ir->regcache, i))
4895 else if (I386_SAVE_FPU_ENV == iregnum)
4897 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4899 if (record_full_arch_list_add_reg (ir->regcache, i))
4903 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
4905 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4907 if (record_full_arch_list_add_reg (ir->regcache, i))
4911 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
4912 (iregnum <= I387_FOP_REGNUM (tdep)))
4914 if (record_full_arch_list_add_reg (ir->regcache,iregnum))
4919 /* Parameter error. */
4922 if(I386_SAVE_FPU_ENV != iregnum)
4924 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4926 if (record_full_arch_list_add_reg (ir->regcache, i))
4933 /* Parse the current instruction, and record the values of the
4934 registers and memory that will be changed by the current
4935 instruction. Returns -1 if something goes wrong, 0 otherwise. */
4937 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
4938 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
4941 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
4942 CORE_ADDR input_addr)
4944 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4950 gdb_byte buf[MAX_REGISTER_SIZE];
4951 struct i386_record_s ir;
4952 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4956 memset (&ir, 0, sizeof (struct i386_record_s));
4957 ir.regcache = regcache;
4958 ir.addr = input_addr;
4959 ir.orig_addr = input_addr;
4963 ir.popl_esp_hack = 0;
4964 ir.regmap = tdep->record_regmap;
4965 ir.gdbarch = gdbarch;
4967 if (record_debug > 1)
4968 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
4970 paddress (gdbarch, ir.addr));
4975 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
4978 switch (opcode8) /* Instruction prefixes */
4980 case REPE_PREFIX_OPCODE:
4981 prefixes |= PREFIX_REPZ;
4983 case REPNE_PREFIX_OPCODE:
4984 prefixes |= PREFIX_REPNZ;
4986 case LOCK_PREFIX_OPCODE:
4987 prefixes |= PREFIX_LOCK;
4989 case CS_PREFIX_OPCODE:
4990 ir.override = X86_RECORD_CS_REGNUM;
4992 case SS_PREFIX_OPCODE:
4993 ir.override = X86_RECORD_SS_REGNUM;
4995 case DS_PREFIX_OPCODE:
4996 ir.override = X86_RECORD_DS_REGNUM;
4998 case ES_PREFIX_OPCODE:
4999 ir.override = X86_RECORD_ES_REGNUM;
5001 case FS_PREFIX_OPCODE:
5002 ir.override = X86_RECORD_FS_REGNUM;
5004 case GS_PREFIX_OPCODE:
5005 ir.override = X86_RECORD_GS_REGNUM;
5007 case DATA_PREFIX_OPCODE:
5008 prefixes |= PREFIX_DATA;
5010 case ADDR_PREFIX_OPCODE:
5011 prefixes |= PREFIX_ADDR;
5013 case 0x40: /* i386 inc %eax */
5014 case 0x41: /* i386 inc %ecx */
5015 case 0x42: /* i386 inc %edx */
5016 case 0x43: /* i386 inc %ebx */
5017 case 0x44: /* i386 inc %esp */
5018 case 0x45: /* i386 inc %ebp */
5019 case 0x46: /* i386 inc %esi */
5020 case 0x47: /* i386 inc %edi */
5021 case 0x48: /* i386 dec %eax */
5022 case 0x49: /* i386 dec %ecx */
5023 case 0x4a: /* i386 dec %edx */
5024 case 0x4b: /* i386 dec %ebx */
5025 case 0x4c: /* i386 dec %esp */
5026 case 0x4d: /* i386 dec %ebp */
5027 case 0x4e: /* i386 dec %esi */
5028 case 0x4f: /* i386 dec %edi */
5029 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
5032 rex_w = (opcode8 >> 3) & 1;
5033 rex_r = (opcode8 & 0x4) << 1;
5034 ir.rex_x = (opcode8 & 0x2) << 2;
5035 ir.rex_b = (opcode8 & 0x1) << 3;
5037 else /* 32 bit target */
5046 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
5052 if (prefixes & PREFIX_DATA)
5055 if (prefixes & PREFIX_ADDR)
5057 else if (ir.regmap[X86_RECORD_R8_REGNUM])
5060 /* Now check op code. */
5061 opcode = (uint32_t) opcode8;
5066 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5069 opcode = (uint32_t) opcode8 | 0x0f00;
5073 case 0x00: /* arith & logic */
5121 if (((opcode >> 3) & 7) != OP_CMPL)
5123 if ((opcode & 1) == 0)
5126 ir.ot = ir.dflag + OT_WORD;
5128 switch ((opcode >> 1) & 3)
5130 case 0: /* OP Ev, Gv */
5131 if (i386_record_modrm (&ir))
5135 if (i386_record_lea_modrm (&ir))
5141 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5143 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5146 case 1: /* OP Gv, Ev */
5147 if (i386_record_modrm (&ir))
5150 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5152 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5154 case 2: /* OP A, Iv */
5155 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5159 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5162 case 0x80: /* GRP1 */
5166 if (i386_record_modrm (&ir))
5169 if (ir.reg != OP_CMPL)
5171 if ((opcode & 1) == 0)
5174 ir.ot = ir.dflag + OT_WORD;
5181 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5182 if (i386_record_lea_modrm (&ir))
5186 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5188 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5191 case 0x40: /* inc */
5200 case 0x48: /* dec */
5209 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7);
5210 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5213 case 0xf6: /* GRP3 */
5215 if ((opcode & 1) == 0)
5218 ir.ot = ir.dflag + OT_WORD;
5219 if (i386_record_modrm (&ir))
5222 if (ir.mod != 3 && ir.reg == 0)
5223 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5228 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5234 if (i386_record_lea_modrm (&ir))
5240 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5242 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5244 if (ir.reg == 3) /* neg */
5245 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5251 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5252 if (ir.ot != OT_BYTE)
5253 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5254 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5258 opcode = opcode << 8 | ir.modrm;
5264 case 0xfe: /* GRP4 */
5265 case 0xff: /* GRP5 */
5266 if (i386_record_modrm (&ir))
5268 if (ir.reg >= 2 && opcode == 0xfe)
5271 opcode = opcode << 8 | ir.modrm;
5278 if ((opcode & 1) == 0)
5281 ir.ot = ir.dflag + OT_WORD;
5284 if (i386_record_lea_modrm (&ir))
5290 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5292 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5294 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5297 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5299 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5301 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5304 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5305 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5307 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5311 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5314 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5316 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5321 opcode = opcode << 8 | ir.modrm;
5327 case 0x84: /* test */
5331 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5334 case 0x98: /* CWDE/CBW */
5335 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5338 case 0x99: /* CDQ/CWD */
5339 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5340 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5343 case 0x0faf: /* imul */
5346 ir.ot = ir.dflag + OT_WORD;
5347 if (i386_record_modrm (&ir))
5350 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5351 else if (opcode == 0x6b)
5354 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5356 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5357 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5360 case 0x0fc0: /* xadd */
5362 if ((opcode & 1) == 0)
5365 ir.ot = ir.dflag + OT_WORD;
5366 if (i386_record_modrm (&ir))
5371 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5373 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5374 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5376 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5380 if (i386_record_lea_modrm (&ir))
5382 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5384 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5386 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5389 case 0x0fb0: /* cmpxchg */
5391 if ((opcode & 1) == 0)
5394 ir.ot = ir.dflag + OT_WORD;
5395 if (i386_record_modrm (&ir))
5400 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5401 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5403 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5407 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5408 if (i386_record_lea_modrm (&ir))
5411 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5414 case 0x0fc7: /* cmpxchg8b */
5415 if (i386_record_modrm (&ir))
5420 opcode = opcode << 8 | ir.modrm;
5423 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5424 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5425 if (i386_record_lea_modrm (&ir))
5427 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5430 case 0x50: /* push */
5440 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5442 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5446 case 0x06: /* push es */
5447 case 0x0e: /* push cs */
5448 case 0x16: /* push ss */
5449 case 0x1e: /* push ds */
5450 if (ir.regmap[X86_RECORD_R8_REGNUM])
5455 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5459 case 0x0fa0: /* push fs */
5460 case 0x0fa8: /* push gs */
5461 if (ir.regmap[X86_RECORD_R8_REGNUM])
5466 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5470 case 0x60: /* pusha */
5471 if (ir.regmap[X86_RECORD_R8_REGNUM])
5476 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
5480 case 0x58: /* pop */
5488 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5489 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5492 case 0x61: /* popa */
5493 if (ir.regmap[X86_RECORD_R8_REGNUM])
5498 for (regnum = X86_RECORD_REAX_REGNUM;
5499 regnum <= X86_RECORD_REDI_REGNUM;
5501 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5504 case 0x8f: /* pop */
5505 if (ir.regmap[X86_RECORD_R8_REGNUM])
5506 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
5508 ir.ot = ir.dflag + OT_WORD;
5509 if (i386_record_modrm (&ir))
5512 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5515 ir.popl_esp_hack = 1 << ir.ot;
5516 if (i386_record_lea_modrm (&ir))
5519 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5522 case 0xc8: /* enter */
5523 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5524 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5526 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5530 case 0xc9: /* leave */
5531 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5532 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5535 case 0x07: /* pop es */
5536 if (ir.regmap[X86_RECORD_R8_REGNUM])
5541 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5542 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
5543 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5546 case 0x17: /* pop ss */
5547 if (ir.regmap[X86_RECORD_R8_REGNUM])
5552 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5553 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
5554 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5557 case 0x1f: /* pop ds */
5558 if (ir.regmap[X86_RECORD_R8_REGNUM])
5563 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5564 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
5565 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5568 case 0x0fa1: /* pop fs */
5569 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5570 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
5571 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5574 case 0x0fa9: /* pop gs */
5575 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5576 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
5577 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5580 case 0x88: /* mov */
5584 if ((opcode & 1) == 0)
5587 ir.ot = ir.dflag + OT_WORD;
5589 if (i386_record_modrm (&ir))
5594 if (opcode == 0xc6 || opcode == 0xc7)
5595 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5596 if (i386_record_lea_modrm (&ir))
5601 if (opcode == 0xc6 || opcode == 0xc7)
5603 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5605 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5609 case 0x8a: /* mov */
5611 if ((opcode & 1) == 0)
5614 ir.ot = ir.dflag + OT_WORD;
5615 if (i386_record_modrm (&ir))
5618 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5620 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5623 case 0x8c: /* mov seg */
5624 if (i386_record_modrm (&ir))
5629 opcode = opcode << 8 | ir.modrm;
5634 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5638 if (i386_record_lea_modrm (&ir))
5643 case 0x8e: /* mov seg */
5644 if (i386_record_modrm (&ir))
5649 regnum = X86_RECORD_ES_REGNUM;
5652 regnum = X86_RECORD_SS_REGNUM;
5655 regnum = X86_RECORD_DS_REGNUM;
5658 regnum = X86_RECORD_FS_REGNUM;
5661 regnum = X86_RECORD_GS_REGNUM;
5665 opcode = opcode << 8 | ir.modrm;
5669 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5670 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5673 case 0x0fb6: /* movzbS */
5674 case 0x0fb7: /* movzwS */
5675 case 0x0fbe: /* movsbS */
5676 case 0x0fbf: /* movswS */
5677 if (i386_record_modrm (&ir))
5679 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5682 case 0x8d: /* lea */
5683 if (i386_record_modrm (&ir))
5688 opcode = opcode << 8 | ir.modrm;
5693 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5695 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5698 case 0xa0: /* mov EAX */
5701 case 0xd7: /* xlat */
5702 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5705 case 0xa2: /* mov EAX */
5707 if (ir.override >= 0)
5709 if (record_full_memory_query)
5713 target_terminal_ours ();
5715 Process record ignores the memory change of instruction at address %s\n\
5716 because it can't get the value of the segment register.\n\
5717 Do you want to stop the program?"),
5718 paddress (gdbarch, ir.orig_addr));
5719 target_terminal_inferior ();
5726 if ((opcode & 1) == 0)
5729 ir.ot = ir.dflag + OT_WORD;
5732 if (record_read_memory (gdbarch, ir.addr, buf, 8))
5735 addr = extract_unsigned_integer (buf, 8, byte_order);
5739 if (record_read_memory (gdbarch, ir.addr, buf, 4))
5742 addr = extract_unsigned_integer (buf, 4, byte_order);
5746 if (record_read_memory (gdbarch, ir.addr, buf, 2))
5749 addr = extract_unsigned_integer (buf, 2, byte_order);
5751 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
5756 case 0xb0: /* mov R, Ib */
5764 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
5765 ? ((opcode & 0x7) | ir.rex_b)
5766 : ((opcode & 0x7) & 0x3));
5769 case 0xb8: /* mov R, Iv */
5777 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5780 case 0x91: /* xchg R, EAX */
5787 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5788 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7);
5791 case 0x86: /* xchg Ev, Gv */
5793 if ((opcode & 1) == 0)
5796 ir.ot = ir.dflag + OT_WORD;
5797 if (i386_record_modrm (&ir))
5802 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5804 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5808 if (i386_record_lea_modrm (&ir))
5812 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5814 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5817 case 0xc4: /* les Gv */
5818 case 0xc5: /* lds Gv */
5819 if (ir.regmap[X86_RECORD_R8_REGNUM])
5825 case 0x0fb2: /* lss Gv */
5826 case 0x0fb4: /* lfs Gv */
5827 case 0x0fb5: /* lgs Gv */
5828 if (i386_record_modrm (&ir))
5836 opcode = opcode << 8 | ir.modrm;
5841 case 0xc4: /* les Gv */
5842 regnum = X86_RECORD_ES_REGNUM;
5844 case 0xc5: /* lds Gv */
5845 regnum = X86_RECORD_DS_REGNUM;
5847 case 0x0fb2: /* lss Gv */
5848 regnum = X86_RECORD_SS_REGNUM;
5850 case 0x0fb4: /* lfs Gv */
5851 regnum = X86_RECORD_FS_REGNUM;
5853 case 0x0fb5: /* lgs Gv */
5854 regnum = X86_RECORD_GS_REGNUM;
5857 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5858 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5859 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5862 case 0xc0: /* shifts */
5868 if ((opcode & 1) == 0)
5871 ir.ot = ir.dflag + OT_WORD;
5872 if (i386_record_modrm (&ir))
5874 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
5876 if (i386_record_lea_modrm (&ir))
5882 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5884 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5886 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5893 if (i386_record_modrm (&ir))
5897 if (record_full_arch_list_add_reg (ir.regcache, ir.rm))
5902 if (i386_record_lea_modrm (&ir))
5907 case 0xd8: /* Floats. */
5915 if (i386_record_modrm (&ir))
5917 ir.reg |= ((opcode & 7) << 3);
5923 if (i386_record_lea_modrm_addr (&ir, &addr64))
5931 /* For fcom, ficom nothing to do. */
5937 /* For fcomp, ficomp pop FPU stack, store all. */
5938 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5965 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5966 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5967 of code, always affects st(0) register. */
5968 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
5992 /* Handling fld, fild. */
5993 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5997 switch (ir.reg >> 4)
6000 if (record_full_arch_list_add_mem (addr64, 4))
6004 if (record_full_arch_list_add_mem (addr64, 8))
6010 if (record_full_arch_list_add_mem (addr64, 2))
6016 switch (ir.reg >> 4)
6019 if (record_full_arch_list_add_mem (addr64, 4))
6021 if (3 == (ir.reg & 7))
6023 /* For fstp m32fp. */
6024 if (i386_record_floats (gdbarch, &ir,
6025 I386_SAVE_FPU_REGS))
6030 if (record_full_arch_list_add_mem (addr64, 4))
6032 if ((3 == (ir.reg & 7))
6033 || (5 == (ir.reg & 7))
6034 || (7 == (ir.reg & 7)))
6036 /* For fstp insn. */
6037 if (i386_record_floats (gdbarch, &ir,
6038 I386_SAVE_FPU_REGS))
6043 if (record_full_arch_list_add_mem (addr64, 8))
6045 if (3 == (ir.reg & 7))
6047 /* For fstp m64fp. */
6048 if (i386_record_floats (gdbarch, &ir,
6049 I386_SAVE_FPU_REGS))
6054 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
6056 /* For fistp, fbld, fild, fbstp. */
6057 if (i386_record_floats (gdbarch, &ir,
6058 I386_SAVE_FPU_REGS))
6063 if (record_full_arch_list_add_mem (addr64, 2))
6072 if (i386_record_floats (gdbarch, &ir,
6073 I386_SAVE_FPU_ENV_REG_STACK))
6078 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
6083 if (i386_record_floats (gdbarch, &ir,
6084 I386_SAVE_FPU_ENV_REG_STACK))
6090 if (record_full_arch_list_add_mem (addr64, 28))
6095 if (record_full_arch_list_add_mem (addr64, 14))
6101 if (record_full_arch_list_add_mem (addr64, 2))
6103 /* Insn fstp, fbstp. */
6104 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6109 if (record_full_arch_list_add_mem (addr64, 10))
6115 if (record_full_arch_list_add_mem (addr64, 28))
6121 if (record_full_arch_list_add_mem (addr64, 14))
6125 if (record_full_arch_list_add_mem (addr64, 80))
6128 if (i386_record_floats (gdbarch, &ir,
6129 I386_SAVE_FPU_ENV_REG_STACK))
6133 if (record_full_arch_list_add_mem (addr64, 8))
6136 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6141 opcode = opcode << 8 | ir.modrm;
6146 /* Opcode is an extension of modR/M byte. */
6152 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6156 if (0x0c == (ir.modrm >> 4))
6158 if ((ir.modrm & 0x0f) <= 7)
6160 if (i386_record_floats (gdbarch, &ir,
6161 I386_SAVE_FPU_REGS))
6166 if (i386_record_floats (gdbarch, &ir,
6167 I387_ST0_REGNUM (tdep)))
6169 /* If only st(0) is changing, then we have already
6171 if ((ir.modrm & 0x0f) - 0x08)
6173 if (i386_record_floats (gdbarch, &ir,
6174 I387_ST0_REGNUM (tdep) +
6175 ((ir.modrm & 0x0f) - 0x08)))
6193 if (i386_record_floats (gdbarch, &ir,
6194 I387_ST0_REGNUM (tdep)))
6212 if (i386_record_floats (gdbarch, &ir,
6213 I386_SAVE_FPU_REGS))
6217 if (i386_record_floats (gdbarch, &ir,
6218 I387_ST0_REGNUM (tdep)))
6220 if (i386_record_floats (gdbarch, &ir,
6221 I387_ST0_REGNUM (tdep) + 1))
6228 if (0xe9 == ir.modrm)
6230 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6233 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6235 if (i386_record_floats (gdbarch, &ir,
6236 I387_ST0_REGNUM (tdep)))
6238 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6240 if (i386_record_floats (gdbarch, &ir,
6241 I387_ST0_REGNUM (tdep) +
6245 else if ((ir.modrm & 0x0f) - 0x08)
6247 if (i386_record_floats (gdbarch, &ir,
6248 I387_ST0_REGNUM (tdep) +
6249 ((ir.modrm & 0x0f) - 0x08)))
6255 if (0xe3 == ir.modrm)
6257 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
6260 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6262 if (i386_record_floats (gdbarch, &ir,
6263 I387_ST0_REGNUM (tdep)))
6265 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6267 if (i386_record_floats (gdbarch, &ir,
6268 I387_ST0_REGNUM (tdep) +
6272 else if ((ir.modrm & 0x0f) - 0x08)
6274 if (i386_record_floats (gdbarch, &ir,
6275 I387_ST0_REGNUM (tdep) +
6276 ((ir.modrm & 0x0f) - 0x08)))
6282 if ((0x0c == ir.modrm >> 4)
6283 || (0x0d == ir.modrm >> 4)
6284 || (0x0f == ir.modrm >> 4))
6286 if ((ir.modrm & 0x0f) <= 7)
6288 if (i386_record_floats (gdbarch, &ir,
6289 I387_ST0_REGNUM (tdep) +
6295 if (i386_record_floats (gdbarch, &ir,
6296 I387_ST0_REGNUM (tdep) +
6297 ((ir.modrm & 0x0f) - 0x08)))
6303 if (0x0c == ir.modrm >> 4)
6305 if (i386_record_floats (gdbarch, &ir,
6306 I387_FTAG_REGNUM (tdep)))
6309 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6311 if ((ir.modrm & 0x0f) <= 7)
6313 if (i386_record_floats (gdbarch, &ir,
6314 I387_ST0_REGNUM (tdep) +
6320 if (i386_record_floats (gdbarch, &ir,
6321 I386_SAVE_FPU_REGS))
6327 if ((0x0c == ir.modrm >> 4)
6328 || (0x0e == ir.modrm >> 4)
6329 || (0x0f == ir.modrm >> 4)
6330 || (0xd9 == ir.modrm))
6332 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6337 if (0xe0 == ir.modrm)
6339 if (record_full_arch_list_add_reg (ir.regcache,
6343 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6345 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6353 case 0xa4: /* movsS */
6355 case 0xaa: /* stosS */
6357 case 0x6c: /* insS */
6359 regcache_raw_read_unsigned (ir.regcache,
6360 ir.regmap[X86_RECORD_RECX_REGNUM],
6366 if ((opcode & 1) == 0)
6369 ir.ot = ir.dflag + OT_WORD;
6370 regcache_raw_read_unsigned (ir.regcache,
6371 ir.regmap[X86_RECORD_REDI_REGNUM],
6374 regcache_raw_read_unsigned (ir.regcache,
6375 ir.regmap[X86_RECORD_ES_REGNUM],
6377 regcache_raw_read_unsigned (ir.regcache,
6378 ir.regmap[X86_RECORD_DS_REGNUM],
6380 if (ir.aflag && (es != ds))
6382 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6383 if (record_full_memory_query)
6387 target_terminal_ours ();
6389 Process record ignores the memory change of instruction at address %s\n\
6390 because it can't get the value of the segment register.\n\
6391 Do you want to stop the program?"),
6392 paddress (gdbarch, ir.orig_addr));
6393 target_terminal_inferior ();
6400 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
6404 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6405 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6406 if (opcode == 0xa4 || opcode == 0xa5)
6407 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6408 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6409 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6413 case 0xa6: /* cmpsS */
6415 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6416 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6417 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6418 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6419 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6422 case 0xac: /* lodsS */
6424 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6425 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6426 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6427 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6428 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6431 case 0xae: /* scasS */
6433 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6434 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6435 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6436 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6439 case 0x6e: /* outsS */
6441 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6442 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6443 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6444 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6447 case 0xe4: /* port I/O */
6451 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6452 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6462 case 0xc2: /* ret im */
6463 case 0xc3: /* ret */
6464 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6465 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6468 case 0xca: /* lret im */
6469 case 0xcb: /* lret */
6470 case 0xcf: /* iret */
6471 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6472 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6473 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6476 case 0xe8: /* call im */
6477 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6479 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6483 case 0x9a: /* lcall im */
6484 if (ir.regmap[X86_RECORD_R8_REGNUM])
6489 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6490 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6494 case 0xe9: /* jmp im */
6495 case 0xea: /* ljmp im */
6496 case 0xeb: /* jmp Jb */
6497 case 0x70: /* jcc Jb */
6513 case 0x0f80: /* jcc Jv */
6531 case 0x0f90: /* setcc Gv */
6547 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6549 if (i386_record_modrm (&ir))
6552 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
6556 if (i386_record_lea_modrm (&ir))
6561 case 0x0f40: /* cmov Gv, Ev */
6577 if (i386_record_modrm (&ir))
6580 if (ir.dflag == OT_BYTE)
6582 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
6586 case 0x9c: /* pushf */
6587 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6588 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6590 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6594 case 0x9d: /* popf */
6595 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6596 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6599 case 0x9e: /* sahf */
6600 if (ir.regmap[X86_RECORD_R8_REGNUM])
6606 case 0xf5: /* cmc */
6607 case 0xf8: /* clc */
6608 case 0xf9: /* stc */
6609 case 0xfc: /* cld */
6610 case 0xfd: /* std */
6611 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6614 case 0x9f: /* lahf */
6615 if (ir.regmap[X86_RECORD_R8_REGNUM])
6620 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6621 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6624 /* bit operations */
6625 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6626 ir.ot = ir.dflag + OT_WORD;
6627 if (i386_record_modrm (&ir))
6632 opcode = opcode << 8 | ir.modrm;
6638 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6641 if (i386_record_lea_modrm (&ir))
6645 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6648 case 0x0fa3: /* bt Gv, Ev */
6649 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6652 case 0x0fab: /* bts */
6653 case 0x0fb3: /* btr */
6654 case 0x0fbb: /* btc */
6655 ir.ot = ir.dflag + OT_WORD;
6656 if (i386_record_modrm (&ir))
6659 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6663 if (i386_record_lea_modrm_addr (&ir, &addr64))
6665 regcache_raw_read_unsigned (ir.regcache,
6666 ir.regmap[ir.reg | rex_r],
6671 addr64 += ((int16_t) addr >> 4) << 4;
6674 addr64 += ((int32_t) addr >> 5) << 5;
6677 addr64 += ((int64_t) addr >> 6) << 6;
6680 if (record_full_arch_list_add_mem (addr64, 1 << ir.ot))
6682 if (i386_record_lea_modrm (&ir))
6685 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6688 case 0x0fbc: /* bsf */
6689 case 0x0fbd: /* bsr */
6690 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6691 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6695 case 0x27: /* daa */
6696 case 0x2f: /* das */
6697 case 0x37: /* aaa */
6698 case 0x3f: /* aas */
6699 case 0xd4: /* aam */
6700 case 0xd5: /* aad */
6701 if (ir.regmap[X86_RECORD_R8_REGNUM])
6706 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6707 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6711 case 0x90: /* nop */
6712 if (prefixes & PREFIX_LOCK)
6719 case 0x9b: /* fwait */
6720 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
6722 opcode = (uint32_t) opcode8;
6728 case 0xcc: /* int3 */
6729 printf_unfiltered (_("Process record does not support instruction "
6736 case 0xcd: /* int */
6740 if (record_read_memory (gdbarch, ir.addr, &interrupt, 1))
6743 if (interrupt != 0x80
6744 || tdep->i386_intx80_record == NULL)
6746 printf_unfiltered (_("Process record does not support "
6747 "instruction int 0x%02x.\n"),
6752 ret = tdep->i386_intx80_record (ir.regcache);
6759 case 0xce: /* into */
6760 printf_unfiltered (_("Process record does not support "
6761 "instruction into.\n"));
6766 case 0xfa: /* cli */
6767 case 0xfb: /* sti */
6770 case 0x62: /* bound */
6771 printf_unfiltered (_("Process record does not support "
6772 "instruction bound.\n"));
6777 case 0x0fc8: /* bswap reg */
6785 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
6788 case 0xd6: /* salc */
6789 if (ir.regmap[X86_RECORD_R8_REGNUM])
6794 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6795 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6798 case 0xe0: /* loopnz */
6799 case 0xe1: /* loopz */
6800 case 0xe2: /* loop */
6801 case 0xe3: /* jecxz */
6802 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6803 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6806 case 0x0f30: /* wrmsr */
6807 printf_unfiltered (_("Process record does not support "
6808 "instruction wrmsr.\n"));
6813 case 0x0f32: /* rdmsr */
6814 printf_unfiltered (_("Process record does not support "
6815 "instruction rdmsr.\n"));
6820 case 0x0f31: /* rdtsc */
6821 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6822 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6825 case 0x0f34: /* sysenter */
6828 if (ir.regmap[X86_RECORD_R8_REGNUM])
6833 if (tdep->i386_sysenter_record == NULL)
6835 printf_unfiltered (_("Process record does not support "
6836 "instruction sysenter.\n"));
6840 ret = tdep->i386_sysenter_record (ir.regcache);
6846 case 0x0f35: /* sysexit */
6847 printf_unfiltered (_("Process record does not support "
6848 "instruction sysexit.\n"));
6853 case 0x0f05: /* syscall */
6856 if (tdep->i386_syscall_record == NULL)
6858 printf_unfiltered (_("Process record does not support "
6859 "instruction syscall.\n"));
6863 ret = tdep->i386_syscall_record (ir.regcache);
6869 case 0x0f07: /* sysret */
6870 printf_unfiltered (_("Process record does not support "
6871 "instruction sysret.\n"));
6876 case 0x0fa2: /* cpuid */
6877 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6878 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6879 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6880 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
6883 case 0xf4: /* hlt */
6884 printf_unfiltered (_("Process record does not support "
6885 "instruction hlt.\n"));
6891 if (i386_record_modrm (&ir))
6898 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6902 if (i386_record_lea_modrm (&ir))
6911 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6915 opcode = opcode << 8 | ir.modrm;
6922 if (i386_record_modrm (&ir))
6933 opcode = opcode << 8 | ir.modrm;
6936 if (ir.override >= 0)
6938 if (record_full_memory_query)
6942 target_terminal_ours ();
6944 Process record ignores the memory change of instruction at address %s\n\
6945 because it can't get the value of the segment register.\n\
6946 Do you want to stop the program?"),
6947 paddress (gdbarch, ir.orig_addr));
6948 target_terminal_inferior ();
6955 if (i386_record_lea_modrm_addr (&ir, &addr64))
6957 if (record_full_arch_list_add_mem (addr64, 2))
6960 if (ir.regmap[X86_RECORD_R8_REGNUM])
6962 if (record_full_arch_list_add_mem (addr64, 8))
6967 if (record_full_arch_list_add_mem (addr64, 4))
6978 case 0: /* monitor */
6981 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6985 opcode = opcode << 8 | ir.modrm;
6993 if (ir.override >= 0)
6995 if (record_full_memory_query)
6999 target_terminal_ours ();
7001 Process record ignores the memory change of instruction at address %s\n\
7002 because it can't get the value of the segment register.\n\
7003 Do you want to stop the program?"),
7004 paddress (gdbarch, ir.orig_addr));
7005 target_terminal_inferior ();
7014 if (i386_record_lea_modrm_addr (&ir, &addr64))
7016 if (record_full_arch_list_add_mem (addr64, 2))
7019 if (ir.regmap[X86_RECORD_R8_REGNUM])
7021 if (record_full_arch_list_add_mem (addr64, 8))
7026 if (record_full_arch_list_add_mem (addr64, 4))
7038 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7039 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7043 else if (ir.rm == 1)
7050 opcode = opcode << 8 | ir.modrm;
7057 if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
7063 if (i386_record_lea_modrm (&ir))
7066 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7069 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7071 case 7: /* invlpg */
7074 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
7075 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
7079 opcode = opcode << 8 | ir.modrm;
7084 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7088 opcode = opcode << 8 | ir.modrm;
7094 case 0x0f08: /* invd */
7095 case 0x0f09: /* wbinvd */
7098 case 0x63: /* arpl */
7099 if (i386_record_modrm (&ir))
7101 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
7103 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
7104 ? (ir.reg | rex_r) : ir.rm);
7108 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
7109 if (i386_record_lea_modrm (&ir))
7112 if (!ir.regmap[X86_RECORD_R8_REGNUM])
7113 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7116 case 0x0f02: /* lar */
7117 case 0x0f03: /* lsl */
7118 if (i386_record_modrm (&ir))
7120 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7121 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7125 if (i386_record_modrm (&ir))
7127 if (ir.mod == 3 && ir.reg == 3)
7130 opcode = opcode << 8 | ir.modrm;
7142 /* nop (multi byte) */
7145 case 0x0f20: /* mov reg, crN */
7146 case 0x0f22: /* mov crN, reg */
7147 if (i386_record_modrm (&ir))
7149 if ((ir.modrm & 0xc0) != 0xc0)
7152 opcode = opcode << 8 | ir.modrm;
7163 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7165 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7169 opcode = opcode << 8 | ir.modrm;
7175 case 0x0f21: /* mov reg, drN */
7176 case 0x0f23: /* mov drN, reg */
7177 if (i386_record_modrm (&ir))
7179 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
7180 || ir.reg == 5 || ir.reg >= 8)
7183 opcode = opcode << 8 | ir.modrm;
7187 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7189 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7192 case 0x0f06: /* clts */
7193 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7196 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7198 case 0x0f0d: /* 3DNow! prefetch */
7201 case 0x0f0e: /* 3DNow! femms */
7202 case 0x0f77: /* emms */
7203 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
7205 record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
7208 case 0x0f0f: /* 3DNow! data */
7209 if (i386_record_modrm (&ir))
7211 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7216 case 0x0c: /* 3DNow! pi2fw */
7217 case 0x0d: /* 3DNow! pi2fd */
7218 case 0x1c: /* 3DNow! pf2iw */
7219 case 0x1d: /* 3DNow! pf2id */
7220 case 0x8a: /* 3DNow! pfnacc */
7221 case 0x8e: /* 3DNow! pfpnacc */
7222 case 0x90: /* 3DNow! pfcmpge */
7223 case 0x94: /* 3DNow! pfmin */
7224 case 0x96: /* 3DNow! pfrcp */
7225 case 0x97: /* 3DNow! pfrsqrt */
7226 case 0x9a: /* 3DNow! pfsub */
7227 case 0x9e: /* 3DNow! pfadd */
7228 case 0xa0: /* 3DNow! pfcmpgt */
7229 case 0xa4: /* 3DNow! pfmax */
7230 case 0xa6: /* 3DNow! pfrcpit1 */
7231 case 0xa7: /* 3DNow! pfrsqit1 */
7232 case 0xaa: /* 3DNow! pfsubr */
7233 case 0xae: /* 3DNow! pfacc */
7234 case 0xb0: /* 3DNow! pfcmpeq */
7235 case 0xb4: /* 3DNow! pfmul */
7236 case 0xb6: /* 3DNow! pfrcpit2 */
7237 case 0xb7: /* 3DNow! pmulhrw */
7238 case 0xbb: /* 3DNow! pswapd */
7239 case 0xbf: /* 3DNow! pavgusb */
7240 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7241 goto no_support_3dnow_data;
7242 record_full_arch_list_add_reg (ir.regcache, ir.reg);
7246 no_support_3dnow_data:
7247 opcode = (opcode << 8) | opcode8;
7253 case 0x0faa: /* rsm */
7254 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7255 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7256 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
7257 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7258 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
7259 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
7260 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
7261 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
7262 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
7266 if (i386_record_modrm (&ir))
7270 case 0: /* fxsave */
7274 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7275 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
7277 if (record_full_arch_list_add_mem (tmpu64, 512))
7282 case 1: /* fxrstor */
7286 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7288 for (i = I387_MM0_REGNUM (tdep);
7289 i386_mmx_regnum_p (gdbarch, i); i++)
7290 record_full_arch_list_add_reg (ir.regcache, i);
7292 for (i = I387_XMM0_REGNUM (tdep);
7293 i386_xmm_regnum_p (gdbarch, i); i++)
7294 record_full_arch_list_add_reg (ir.regcache, i);
7296 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7297 record_full_arch_list_add_reg (ir.regcache,
7298 I387_MXCSR_REGNUM(tdep));
7300 for (i = I387_ST0_REGNUM (tdep);
7301 i386_fp_regnum_p (gdbarch, i); i++)
7302 record_full_arch_list_add_reg (ir.regcache, i);
7304 for (i = I387_FCTRL_REGNUM (tdep);
7305 i386_fpc_regnum_p (gdbarch, i); i++)
7306 record_full_arch_list_add_reg (ir.regcache, i);
7310 case 2: /* ldmxcsr */
7311 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7313 record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
7316 case 3: /* stmxcsr */
7318 if (i386_record_lea_modrm (&ir))
7322 case 5: /* lfence */
7323 case 6: /* mfence */
7324 case 7: /* sfence clflush */
7328 opcode = (opcode << 8) | ir.modrm;
7334 case 0x0fc3: /* movnti */
7335 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
7336 if (i386_record_modrm (&ir))
7341 if (i386_record_lea_modrm (&ir))
7345 /* Add prefix to opcode. */
7460 /* Mask out PREFIX_ADDR. */
7461 switch ((prefixes & ~PREFIX_ADDR))
7473 reswitch_prefix_add:
7481 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7484 opcode = (uint32_t) opcode8 | opcode << 8;
7485 goto reswitch_prefix_add;
7488 case 0x0f10: /* movups */
7489 case 0x660f10: /* movupd */
7490 case 0xf30f10: /* movss */
7491 case 0xf20f10: /* movsd */
7492 case 0x0f12: /* movlps */
7493 case 0x660f12: /* movlpd */
7494 case 0xf30f12: /* movsldup */
7495 case 0xf20f12: /* movddup */
7496 case 0x0f14: /* unpcklps */
7497 case 0x660f14: /* unpcklpd */
7498 case 0x0f15: /* unpckhps */
7499 case 0x660f15: /* unpckhpd */
7500 case 0x0f16: /* movhps */
7501 case 0x660f16: /* movhpd */
7502 case 0xf30f16: /* movshdup */
7503 case 0x0f28: /* movaps */
7504 case 0x660f28: /* movapd */
7505 case 0x0f2a: /* cvtpi2ps */
7506 case 0x660f2a: /* cvtpi2pd */
7507 case 0xf30f2a: /* cvtsi2ss */
7508 case 0xf20f2a: /* cvtsi2sd */
7509 case 0x0f2c: /* cvttps2pi */
7510 case 0x660f2c: /* cvttpd2pi */
7511 case 0x0f2d: /* cvtps2pi */
7512 case 0x660f2d: /* cvtpd2pi */
7513 case 0x660f3800: /* pshufb */
7514 case 0x660f3801: /* phaddw */
7515 case 0x660f3802: /* phaddd */
7516 case 0x660f3803: /* phaddsw */
7517 case 0x660f3804: /* pmaddubsw */
7518 case 0x660f3805: /* phsubw */
7519 case 0x660f3806: /* phsubd */
7520 case 0x660f3807: /* phsubsw */
7521 case 0x660f3808: /* psignb */
7522 case 0x660f3809: /* psignw */
7523 case 0x660f380a: /* psignd */
7524 case 0x660f380b: /* pmulhrsw */
7525 case 0x660f3810: /* pblendvb */
7526 case 0x660f3814: /* blendvps */
7527 case 0x660f3815: /* blendvpd */
7528 case 0x660f381c: /* pabsb */
7529 case 0x660f381d: /* pabsw */
7530 case 0x660f381e: /* pabsd */
7531 case 0x660f3820: /* pmovsxbw */
7532 case 0x660f3821: /* pmovsxbd */
7533 case 0x660f3822: /* pmovsxbq */
7534 case 0x660f3823: /* pmovsxwd */
7535 case 0x660f3824: /* pmovsxwq */
7536 case 0x660f3825: /* pmovsxdq */
7537 case 0x660f3828: /* pmuldq */
7538 case 0x660f3829: /* pcmpeqq */
7539 case 0x660f382a: /* movntdqa */
7540 case 0x660f3a08: /* roundps */
7541 case 0x660f3a09: /* roundpd */
7542 case 0x660f3a0a: /* roundss */
7543 case 0x660f3a0b: /* roundsd */
7544 case 0x660f3a0c: /* blendps */
7545 case 0x660f3a0d: /* blendpd */
7546 case 0x660f3a0e: /* pblendw */
7547 case 0x660f3a0f: /* palignr */
7548 case 0x660f3a20: /* pinsrb */
7549 case 0x660f3a21: /* insertps */
7550 case 0x660f3a22: /* pinsrd pinsrq */
7551 case 0x660f3a40: /* dpps */
7552 case 0x660f3a41: /* dppd */
7553 case 0x660f3a42: /* mpsadbw */
7554 case 0x660f3a60: /* pcmpestrm */
7555 case 0x660f3a61: /* pcmpestri */
7556 case 0x660f3a62: /* pcmpistrm */
7557 case 0x660f3a63: /* pcmpistri */
7558 case 0x0f51: /* sqrtps */
7559 case 0x660f51: /* sqrtpd */
7560 case 0xf20f51: /* sqrtsd */
7561 case 0xf30f51: /* sqrtss */
7562 case 0x0f52: /* rsqrtps */
7563 case 0xf30f52: /* rsqrtss */
7564 case 0x0f53: /* rcpps */
7565 case 0xf30f53: /* rcpss */
7566 case 0x0f54: /* andps */
7567 case 0x660f54: /* andpd */
7568 case 0x0f55: /* andnps */
7569 case 0x660f55: /* andnpd */
7570 case 0x0f56: /* orps */
7571 case 0x660f56: /* orpd */
7572 case 0x0f57: /* xorps */
7573 case 0x660f57: /* xorpd */
7574 case 0x0f58: /* addps */
7575 case 0x660f58: /* addpd */
7576 case 0xf20f58: /* addsd */
7577 case 0xf30f58: /* addss */
7578 case 0x0f59: /* mulps */
7579 case 0x660f59: /* mulpd */
7580 case 0xf20f59: /* mulsd */
7581 case 0xf30f59: /* mulss */
7582 case 0x0f5a: /* cvtps2pd */
7583 case 0x660f5a: /* cvtpd2ps */
7584 case 0xf20f5a: /* cvtsd2ss */
7585 case 0xf30f5a: /* cvtss2sd */
7586 case 0x0f5b: /* cvtdq2ps */
7587 case 0x660f5b: /* cvtps2dq */
7588 case 0xf30f5b: /* cvttps2dq */
7589 case 0x0f5c: /* subps */
7590 case 0x660f5c: /* subpd */
7591 case 0xf20f5c: /* subsd */
7592 case 0xf30f5c: /* subss */
7593 case 0x0f5d: /* minps */
7594 case 0x660f5d: /* minpd */
7595 case 0xf20f5d: /* minsd */
7596 case 0xf30f5d: /* minss */
7597 case 0x0f5e: /* divps */
7598 case 0x660f5e: /* divpd */
7599 case 0xf20f5e: /* divsd */
7600 case 0xf30f5e: /* divss */
7601 case 0x0f5f: /* maxps */
7602 case 0x660f5f: /* maxpd */
7603 case 0xf20f5f: /* maxsd */
7604 case 0xf30f5f: /* maxss */
7605 case 0x660f60: /* punpcklbw */
7606 case 0x660f61: /* punpcklwd */
7607 case 0x660f62: /* punpckldq */
7608 case 0x660f63: /* packsswb */
7609 case 0x660f64: /* pcmpgtb */
7610 case 0x660f65: /* pcmpgtw */
7611 case 0x660f66: /* pcmpgtd */
7612 case 0x660f67: /* packuswb */
7613 case 0x660f68: /* punpckhbw */
7614 case 0x660f69: /* punpckhwd */
7615 case 0x660f6a: /* punpckhdq */
7616 case 0x660f6b: /* packssdw */
7617 case 0x660f6c: /* punpcklqdq */
7618 case 0x660f6d: /* punpckhqdq */
7619 case 0x660f6e: /* movd */
7620 case 0x660f6f: /* movdqa */
7621 case 0xf30f6f: /* movdqu */
7622 case 0x660f70: /* pshufd */
7623 case 0xf20f70: /* pshuflw */
7624 case 0xf30f70: /* pshufhw */
7625 case 0x660f74: /* pcmpeqb */
7626 case 0x660f75: /* pcmpeqw */
7627 case 0x660f76: /* pcmpeqd */
7628 case 0x660f7c: /* haddpd */
7629 case 0xf20f7c: /* haddps */
7630 case 0x660f7d: /* hsubpd */
7631 case 0xf20f7d: /* hsubps */
7632 case 0xf30f7e: /* movq */
7633 case 0x0fc2: /* cmpps */
7634 case 0x660fc2: /* cmppd */
7635 case 0xf20fc2: /* cmpsd */
7636 case 0xf30fc2: /* cmpss */
7637 case 0x660fc4: /* pinsrw */
7638 case 0x0fc6: /* shufps */
7639 case 0x660fc6: /* shufpd */
7640 case 0x660fd0: /* addsubpd */
7641 case 0xf20fd0: /* addsubps */
7642 case 0x660fd1: /* psrlw */
7643 case 0x660fd2: /* psrld */
7644 case 0x660fd3: /* psrlq */
7645 case 0x660fd4: /* paddq */
7646 case 0x660fd5: /* pmullw */
7647 case 0xf30fd6: /* movq2dq */
7648 case 0x660fd8: /* psubusb */
7649 case 0x660fd9: /* psubusw */
7650 case 0x660fda: /* pminub */
7651 case 0x660fdb: /* pand */
7652 case 0x660fdc: /* paddusb */
7653 case 0x660fdd: /* paddusw */
7654 case 0x660fde: /* pmaxub */
7655 case 0x660fdf: /* pandn */
7656 case 0x660fe0: /* pavgb */
7657 case 0x660fe1: /* psraw */
7658 case 0x660fe2: /* psrad */
7659 case 0x660fe3: /* pavgw */
7660 case 0x660fe4: /* pmulhuw */
7661 case 0x660fe5: /* pmulhw */
7662 case 0x660fe6: /* cvttpd2dq */
7663 case 0xf20fe6: /* cvtpd2dq */
7664 case 0xf30fe6: /* cvtdq2pd */
7665 case 0x660fe8: /* psubsb */
7666 case 0x660fe9: /* psubsw */
7667 case 0x660fea: /* pminsw */
7668 case 0x660feb: /* por */
7669 case 0x660fec: /* paddsb */
7670 case 0x660fed: /* paddsw */
7671 case 0x660fee: /* pmaxsw */
7672 case 0x660fef: /* pxor */
7673 case 0xf20ff0: /* lddqu */
7674 case 0x660ff1: /* psllw */
7675 case 0x660ff2: /* pslld */
7676 case 0x660ff3: /* psllq */
7677 case 0x660ff4: /* pmuludq */
7678 case 0x660ff5: /* pmaddwd */
7679 case 0x660ff6: /* psadbw */
7680 case 0x660ff8: /* psubb */
7681 case 0x660ff9: /* psubw */
7682 case 0x660ffa: /* psubd */
7683 case 0x660ffb: /* psubq */
7684 case 0x660ffc: /* paddb */
7685 case 0x660ffd: /* paddw */
7686 case 0x660ffe: /* paddd */
7687 if (i386_record_modrm (&ir))
7690 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
7692 record_full_arch_list_add_reg (ir.regcache,
7693 I387_XMM0_REGNUM (tdep) + ir.reg);
7694 if ((opcode & 0xfffffffc) == 0x660f3a60)
7695 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7698 case 0x0f11: /* movups */
7699 case 0x660f11: /* movupd */
7700 case 0xf30f11: /* movss */
7701 case 0xf20f11: /* movsd */
7702 case 0x0f13: /* movlps */
7703 case 0x660f13: /* movlpd */
7704 case 0x0f17: /* movhps */
7705 case 0x660f17: /* movhpd */
7706 case 0x0f29: /* movaps */
7707 case 0x660f29: /* movapd */
7708 case 0x660f3a14: /* pextrb */
7709 case 0x660f3a15: /* pextrw */
7710 case 0x660f3a16: /* pextrd pextrq */
7711 case 0x660f3a17: /* extractps */
7712 case 0x660f7f: /* movdqa */
7713 case 0xf30f7f: /* movdqu */
7714 if (i386_record_modrm (&ir))
7718 if (opcode == 0x0f13 || opcode == 0x660f13
7719 || opcode == 0x0f17 || opcode == 0x660f17)
7722 if (!i386_xmm_regnum_p (gdbarch,
7723 I387_XMM0_REGNUM (tdep) + ir.rm))
7725 record_full_arch_list_add_reg (ir.regcache,
7726 I387_XMM0_REGNUM (tdep) + ir.rm);
7748 if (i386_record_lea_modrm (&ir))
7753 case 0x0f2b: /* movntps */
7754 case 0x660f2b: /* movntpd */
7755 case 0x0fe7: /* movntq */
7756 case 0x660fe7: /* movntdq */
7759 if (opcode == 0x0fe7)
7763 if (i386_record_lea_modrm (&ir))
7767 case 0xf30f2c: /* cvttss2si */
7768 case 0xf20f2c: /* cvttsd2si */
7769 case 0xf30f2d: /* cvtss2si */
7770 case 0xf20f2d: /* cvtsd2si */
7771 case 0xf20f38f0: /* crc32 */
7772 case 0xf20f38f1: /* crc32 */
7773 case 0x0f50: /* movmskps */
7774 case 0x660f50: /* movmskpd */
7775 case 0x0fc5: /* pextrw */
7776 case 0x660fc5: /* pextrw */
7777 case 0x0fd7: /* pmovmskb */
7778 case 0x660fd7: /* pmovmskb */
7779 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7782 case 0x0f3800: /* pshufb */
7783 case 0x0f3801: /* phaddw */
7784 case 0x0f3802: /* phaddd */
7785 case 0x0f3803: /* phaddsw */
7786 case 0x0f3804: /* pmaddubsw */
7787 case 0x0f3805: /* phsubw */
7788 case 0x0f3806: /* phsubd */
7789 case 0x0f3807: /* phsubsw */
7790 case 0x0f3808: /* psignb */
7791 case 0x0f3809: /* psignw */
7792 case 0x0f380a: /* psignd */
7793 case 0x0f380b: /* pmulhrsw */
7794 case 0x0f381c: /* pabsb */
7795 case 0x0f381d: /* pabsw */
7796 case 0x0f381e: /* pabsd */
7797 case 0x0f382b: /* packusdw */
7798 case 0x0f3830: /* pmovzxbw */
7799 case 0x0f3831: /* pmovzxbd */
7800 case 0x0f3832: /* pmovzxbq */
7801 case 0x0f3833: /* pmovzxwd */
7802 case 0x0f3834: /* pmovzxwq */
7803 case 0x0f3835: /* pmovzxdq */
7804 case 0x0f3837: /* pcmpgtq */
7805 case 0x0f3838: /* pminsb */
7806 case 0x0f3839: /* pminsd */
7807 case 0x0f383a: /* pminuw */
7808 case 0x0f383b: /* pminud */
7809 case 0x0f383c: /* pmaxsb */
7810 case 0x0f383d: /* pmaxsd */
7811 case 0x0f383e: /* pmaxuw */
7812 case 0x0f383f: /* pmaxud */
7813 case 0x0f3840: /* pmulld */
7814 case 0x0f3841: /* phminposuw */
7815 case 0x0f3a0f: /* palignr */
7816 case 0x0f60: /* punpcklbw */
7817 case 0x0f61: /* punpcklwd */
7818 case 0x0f62: /* punpckldq */
7819 case 0x0f63: /* packsswb */
7820 case 0x0f64: /* pcmpgtb */
7821 case 0x0f65: /* pcmpgtw */
7822 case 0x0f66: /* pcmpgtd */
7823 case 0x0f67: /* packuswb */
7824 case 0x0f68: /* punpckhbw */
7825 case 0x0f69: /* punpckhwd */
7826 case 0x0f6a: /* punpckhdq */
7827 case 0x0f6b: /* packssdw */
7828 case 0x0f6e: /* movd */
7829 case 0x0f6f: /* movq */
7830 case 0x0f70: /* pshufw */
7831 case 0x0f74: /* pcmpeqb */
7832 case 0x0f75: /* pcmpeqw */
7833 case 0x0f76: /* pcmpeqd */
7834 case 0x0fc4: /* pinsrw */
7835 case 0x0fd1: /* psrlw */
7836 case 0x0fd2: /* psrld */
7837 case 0x0fd3: /* psrlq */
7838 case 0x0fd4: /* paddq */
7839 case 0x0fd5: /* pmullw */
7840 case 0xf20fd6: /* movdq2q */
7841 case 0x0fd8: /* psubusb */
7842 case 0x0fd9: /* psubusw */
7843 case 0x0fda: /* pminub */
7844 case 0x0fdb: /* pand */
7845 case 0x0fdc: /* paddusb */
7846 case 0x0fdd: /* paddusw */
7847 case 0x0fde: /* pmaxub */
7848 case 0x0fdf: /* pandn */
7849 case 0x0fe0: /* pavgb */
7850 case 0x0fe1: /* psraw */
7851 case 0x0fe2: /* psrad */
7852 case 0x0fe3: /* pavgw */
7853 case 0x0fe4: /* pmulhuw */
7854 case 0x0fe5: /* pmulhw */
7855 case 0x0fe8: /* psubsb */
7856 case 0x0fe9: /* psubsw */
7857 case 0x0fea: /* pminsw */
7858 case 0x0feb: /* por */
7859 case 0x0fec: /* paddsb */
7860 case 0x0fed: /* paddsw */
7861 case 0x0fee: /* pmaxsw */
7862 case 0x0fef: /* pxor */
7863 case 0x0ff1: /* psllw */
7864 case 0x0ff2: /* pslld */
7865 case 0x0ff3: /* psllq */
7866 case 0x0ff4: /* pmuludq */
7867 case 0x0ff5: /* pmaddwd */
7868 case 0x0ff6: /* psadbw */
7869 case 0x0ff8: /* psubb */
7870 case 0x0ff9: /* psubw */
7871 case 0x0ffa: /* psubd */
7872 case 0x0ffb: /* psubq */
7873 case 0x0ffc: /* paddb */
7874 case 0x0ffd: /* paddw */
7875 case 0x0ffe: /* paddd */
7876 if (i386_record_modrm (&ir))
7878 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7880 record_full_arch_list_add_reg (ir.regcache,
7881 I387_MM0_REGNUM (tdep) + ir.reg);
7884 case 0x0f71: /* psllw */
7885 case 0x0f72: /* pslld */
7886 case 0x0f73: /* psllq */
7887 if (i386_record_modrm (&ir))
7889 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7891 record_full_arch_list_add_reg (ir.regcache,
7892 I387_MM0_REGNUM (tdep) + ir.rm);
7895 case 0x660f71: /* psllw */
7896 case 0x660f72: /* pslld */
7897 case 0x660f73: /* psllq */
7898 if (i386_record_modrm (&ir))
7901 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
7903 record_full_arch_list_add_reg (ir.regcache,
7904 I387_XMM0_REGNUM (tdep) + ir.rm);
7907 case 0x0f7e: /* movd */
7908 case 0x660f7e: /* movd */
7909 if (i386_record_modrm (&ir))
7912 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7919 if (i386_record_lea_modrm (&ir))
7924 case 0x0f7f: /* movq */
7925 if (i386_record_modrm (&ir))
7929 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7931 record_full_arch_list_add_reg (ir.regcache,
7932 I387_MM0_REGNUM (tdep) + ir.rm);
7937 if (i386_record_lea_modrm (&ir))
7942 case 0xf30fb8: /* popcnt */
7943 if (i386_record_modrm (&ir))
7945 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
7946 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7949 case 0x660fd6: /* movq */
7950 if (i386_record_modrm (&ir))
7955 if (!i386_xmm_regnum_p (gdbarch,
7956 I387_XMM0_REGNUM (tdep) + ir.rm))
7958 record_full_arch_list_add_reg (ir.regcache,
7959 I387_XMM0_REGNUM (tdep) + ir.rm);
7964 if (i386_record_lea_modrm (&ir))
7969 case 0x660f3817: /* ptest */
7970 case 0x0f2e: /* ucomiss */
7971 case 0x660f2e: /* ucomisd */
7972 case 0x0f2f: /* comiss */
7973 case 0x660f2f: /* comisd */
7974 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7977 case 0x0ff7: /* maskmovq */
7978 regcache_raw_read_unsigned (ir.regcache,
7979 ir.regmap[X86_RECORD_REDI_REGNUM],
7981 if (record_full_arch_list_add_mem (addr, 64))
7985 case 0x660ff7: /* maskmovdqu */
7986 regcache_raw_read_unsigned (ir.regcache,
7987 ir.regmap[X86_RECORD_REDI_REGNUM],
7989 if (record_full_arch_list_add_mem (addr, 128))
8004 /* In the future, maybe still need to deal with need_dasm. */
8005 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
8006 if (record_full_arch_list_add_end ())
8012 printf_unfiltered (_("Process record does not support instruction 0x%02x "
8013 "at address %s.\n"),
8014 (unsigned int) (opcode),
8015 paddress (gdbarch, ir.orig_addr));
8019 static const int i386_record_regmap[] =
8021 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
8022 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
8023 0, 0, 0, 0, 0, 0, 0, 0,
8024 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
8025 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
8028 /* Check that the given address appears suitable for a fast
8029 tracepoint, which on x86-64 means that we need an instruction of at
8030 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8031 jump and not have to worry about program jumps to an address in the
8032 middle of the tracepoint jump. On x86, it may be possible to use
8033 4-byte jumps with a 2-byte offset to a trampoline located in the
8034 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8035 of instruction to replace, and 0 if not, plus an explanatory
8039 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch,
8040 CORE_ADDR addr, int *isize, char **msg)
8043 static struct ui_file *gdb_null = NULL;
8045 /* Ask the target for the minimum instruction length supported. */
8046 jumplen = target_get_min_fast_tracepoint_insn_len ();
8050 /* If the target does not support the get_min_fast_tracepoint_insn_len
8051 operation, assume that fast tracepoints will always be implemented
8052 using 4-byte relative jumps on both x86 and x86-64. */
8055 else if (jumplen == 0)
8057 /* If the target does support get_min_fast_tracepoint_insn_len but
8058 returns zero, then the IPA has not loaded yet. In this case,
8059 we optimistically assume that truncated 2-byte relative jumps
8060 will be available on x86, and compensate later if this assumption
8061 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8062 jumps will always be used. */
8063 jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4;
8066 /* Dummy file descriptor for the disassembler. */
8068 gdb_null = ui_file_new ();
8070 /* Check for fit. */
8071 len = gdb_print_insn (gdbarch, addr, gdb_null, NULL);
8077 /* Return a bit of target-specific detail to add to the caller's
8078 generic failure message. */
8080 *msg = xstrprintf (_("; instruction is only %d bytes long, "
8081 "need at least %d bytes for the jump"),
8094 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
8095 struct tdesc_arch_data *tdesc_data)
8097 const struct target_desc *tdesc = tdep->tdesc;
8098 const struct tdesc_feature *feature_core;
8100 const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx,
8102 int i, num_regs, valid_p;
8104 if (! tdesc_has_registers (tdesc))
8107 /* Get core registers. */
8108 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
8109 if (feature_core == NULL)
8112 /* Get SSE registers. */
8113 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
8115 /* Try AVX registers. */
8116 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
8118 /* Try MPX registers. */
8119 feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx");
8121 /* Try AVX512 registers. */
8122 feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512");
8126 /* The XCR0 bits. */
8129 /* AVX512 register description requires AVX register description. */
8133 tdep->xcr0 = X86_XSTATE_MPX_AVX512_MASK;
8135 /* It may have been set by OSABI initialization function. */
8136 if (tdep->k0_regnum < 0)
8138 tdep->k_register_names = i386_k_names;
8139 tdep->k0_regnum = I386_K0_REGNUM;
8142 for (i = 0; i < I387_NUM_K_REGS; i++)
8143 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8144 tdep->k0_regnum + i,
8147 if (tdep->num_zmm_regs == 0)
8149 tdep->zmmh_register_names = i386_zmmh_names;
8150 tdep->num_zmm_regs = 8;
8151 tdep->zmm0h_regnum = I386_ZMM0H_REGNUM;
8154 for (i = 0; i < tdep->num_zmm_regs; i++)
8155 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8156 tdep->zmm0h_regnum + i,
8157 tdep->zmmh_register_names[i]);
8159 for (i = 0; i < tdep->num_xmm_avx512_regs; i++)
8160 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8161 tdep->xmm16_regnum + i,
8162 tdep->xmm_avx512_register_names[i]);
8164 for (i = 0; i < tdep->num_ymm_avx512_regs; i++)
8165 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8166 tdep->ymm16h_regnum + i,
8167 tdep->ymm16h_register_names[i]);
8171 /* AVX register description requires SSE register description. */
8175 if (!feature_avx512)
8176 tdep->xcr0 = X86_XSTATE_AVX_MASK;
8178 /* It may have been set by OSABI initialization function. */
8179 if (tdep->num_ymm_regs == 0)
8181 tdep->ymmh_register_names = i386_ymmh_names;
8182 tdep->num_ymm_regs = 8;
8183 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
8186 for (i = 0; i < tdep->num_ymm_regs; i++)
8187 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
8188 tdep->ymm0h_regnum + i,
8189 tdep->ymmh_register_names[i]);
8191 else if (feature_sse)
8192 tdep->xcr0 = X86_XSTATE_SSE_MASK;
8195 tdep->xcr0 = X86_XSTATE_X87_MASK;
8196 tdep->num_xmm_regs = 0;
8199 num_regs = tdep->num_core_regs;
8200 for (i = 0; i < num_regs; i++)
8201 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
8202 tdep->register_names[i]);
8206 /* Need to include %mxcsr, so add one. */
8207 num_regs += tdep->num_xmm_regs + 1;
8208 for (; i < num_regs; i++)
8209 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
8210 tdep->register_names[i]);
8215 tdep->xcr0 |= X86_XSTATE_MPX_MASK;
8217 if (tdep->bnd0r_regnum < 0)
8219 tdep->mpx_register_names = i386_mpx_names;
8220 tdep->bnd0r_regnum = I386_BND0R_REGNUM;
8221 tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM;
8224 for (i = 0; i < I387_NUM_MPX_REGS; i++)
8225 valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data,
8226 I387_BND0R_REGNUM (tdep) + i,
8227 tdep->mpx_register_names[i]);
8234 static struct gdbarch *
8235 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8237 struct gdbarch_tdep *tdep;
8238 struct gdbarch *gdbarch;
8239 struct tdesc_arch_data *tdesc_data;
8240 const struct target_desc *tdesc;
8248 /* If there is already a candidate, use it. */
8249 arches = gdbarch_list_lookup_by_info (arches, &info);
8251 return arches->gdbarch;
8253 /* Allocate space for the new architecture. */
8254 tdep = XCNEW (struct gdbarch_tdep);
8255 gdbarch = gdbarch_alloc (&info, tdep);
8257 /* General-purpose registers. */
8258 tdep->gregset_reg_offset = NULL;
8259 tdep->gregset_num_regs = I386_NUM_GREGS;
8260 tdep->sizeof_gregset = 0;
8262 /* Floating-point registers. */
8263 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
8264 tdep->fpregset = &i386_fpregset;
8266 /* The default settings include the FPU registers, the MMX registers
8267 and the SSE registers. This can be overridden for a specific ABI
8268 by adjusting the members `st0_regnum', `mm0_regnum' and
8269 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8270 will show up in the output of "info all-registers". */
8272 tdep->st0_regnum = I386_ST0_REGNUM;
8274 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8275 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
8277 tdep->jb_pc_offset = -1;
8278 tdep->struct_return = pcc_struct_return;
8279 tdep->sigtramp_start = 0;
8280 tdep->sigtramp_end = 0;
8281 tdep->sigtramp_p = i386_sigtramp_p;
8282 tdep->sigcontext_addr = NULL;
8283 tdep->sc_reg_offset = NULL;
8284 tdep->sc_pc_offset = -1;
8285 tdep->sc_sp_offset = -1;
8287 tdep->xsave_xcr0_offset = -1;
8289 tdep->record_regmap = i386_record_regmap;
8291 set_gdbarch_long_long_align_bit (gdbarch, 32);
8293 /* The format used for `long double' on almost all i386 targets is
8294 the i387 extended floating-point format. In fact, of all targets
8295 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8296 on having a `long double' that's not `long' at all. */
8297 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
8299 /* Although the i387 extended floating-point has only 80 significant
8300 bits, a `long double' actually takes up 96, probably to enforce
8302 set_gdbarch_long_double_bit (gdbarch, 96);
8304 /* Register numbers of various important registers. */
8305 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
8306 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
8307 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
8308 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
8310 /* NOTE: kettenis/20040418: GCC does have two possible register
8311 numbering schemes on the i386: dbx and SVR4. These schemes
8312 differ in how they number %ebp, %esp, %eflags, and the
8313 floating-point registers, and are implemented by the arrays
8314 dbx_register_map[] and svr4_dbx_register_map in
8315 gcc/config/i386.c. GCC also defines a third numbering scheme in
8316 gcc/config/i386.c, which it designates as the "default" register
8317 map used in 64bit mode. This last register numbering scheme is
8318 implemented in dbx64_register_map, and is used for AMD64; see
8321 Currently, each GCC i386 target always uses the same register
8322 numbering scheme across all its supported debugging formats
8323 i.e. SDB (COFF), stabs and DWARF 2. This is because
8324 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8325 DBX_REGISTER_NUMBER macro which is defined by each target's
8326 respective config header in a manner independent of the requested
8327 output debugging format.
8329 This does not match the arrangement below, which presumes that
8330 the SDB and stabs numbering schemes differ from the DWARF and
8331 DWARF 2 ones. The reason for this arrangement is that it is
8332 likely to get the numbering scheme for the target's
8333 default/native debug format right. For targets where GCC is the
8334 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8335 targets where the native toolchain uses a different numbering
8336 scheme for a particular debug format (stabs-in-ELF on Solaris)
8337 the defaults below will have to be overridden, like
8338 i386_elf_init_abi() does. */
8340 /* Use the dbx register numbering scheme for stabs and COFF. */
8341 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8342 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8344 /* Use the SVR4 register numbering scheme for DWARF 2. */
8345 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
8347 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8348 be in use on any of the supported i386 targets. */
8350 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
8352 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
8354 /* Call dummy code. */
8355 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
8356 set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code);
8357 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
8358 set_gdbarch_frame_align (gdbarch, i386_frame_align);
8360 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
8361 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
8362 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
8364 set_gdbarch_return_value (gdbarch, i386_return_value);
8366 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
8368 /* Stack grows downward. */
8369 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8371 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc);
8372 set_gdbarch_decr_pc_after_break (gdbarch, 1);
8373 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
8375 set_gdbarch_frame_args_skip (gdbarch, 8);
8377 set_gdbarch_print_insn (gdbarch, i386_print_insn);
8379 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
8381 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
8383 /* Add the i386 register groups. */
8384 i386_add_reggroups (gdbarch);
8385 tdep->register_reggroup_p = i386_register_reggroup_p;
8387 /* Helper for function argument information. */
8388 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
8390 /* Hook the function epilogue frame unwinder. This unwinder is
8391 appended to the list first, so that it supercedes the DWARF
8392 unwinder in function epilogues (where the DWARF unwinder
8393 currently fails). */
8394 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
8396 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8397 to the list before the prologue-based unwinders, so that DWARF
8398 CFI info will be used if it is available. */
8399 dwarf2_append_unwinders (gdbarch);
8401 frame_base_set_default (gdbarch, &i386_frame_base);
8403 /* Pseudo registers may be changed by amd64_init_abi. */
8404 set_gdbarch_pseudo_register_read_value (gdbarch,
8405 i386_pseudo_register_read_value);
8406 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
8408 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
8409 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
8411 /* Override the normal target description method to make the AVX
8412 upper halves anonymous. */
8413 set_gdbarch_register_name (gdbarch, i386_register_name);
8415 /* Even though the default ABI only includes general-purpose registers,
8416 floating-point registers and the SSE registers, we have to leave a
8417 gap for the upper AVX, MPX and AVX512 registers. */
8418 set_gdbarch_num_regs (gdbarch, I386_AVX512_NUM_REGS);
8420 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
8422 /* Get the x86 target description from INFO. */
8423 tdesc = info.target_desc;
8424 if (! tdesc_has_registers (tdesc))
8426 tdep->tdesc = tdesc;
8428 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
8429 tdep->register_names = i386_register_names;
8431 /* No upper YMM registers. */
8432 tdep->ymmh_register_names = NULL;
8433 tdep->ymm0h_regnum = -1;
8435 /* No upper ZMM registers. */
8436 tdep->zmmh_register_names = NULL;
8437 tdep->zmm0h_regnum = -1;
8439 /* No high XMM registers. */
8440 tdep->xmm_avx512_register_names = NULL;
8441 tdep->xmm16_regnum = -1;
8443 /* No upper YMM16-31 registers. */
8444 tdep->ymm16h_register_names = NULL;
8445 tdep->ymm16h_regnum = -1;
8447 tdep->num_byte_regs = 8;
8448 tdep->num_word_regs = 8;
8449 tdep->num_dword_regs = 0;
8450 tdep->num_mmx_regs = 8;
8451 tdep->num_ymm_regs = 0;
8453 /* No MPX registers. */
8454 tdep->bnd0r_regnum = -1;
8455 tdep->bndcfgu_regnum = -1;
8457 /* No AVX512 registers. */
8458 tdep->k0_regnum = -1;
8459 tdep->num_zmm_regs = 0;
8460 tdep->num_ymm_avx512_regs = 0;
8461 tdep->num_xmm_avx512_regs = 0;
8463 tdesc_data = tdesc_data_alloc ();
8465 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
8467 set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address);
8469 set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call);
8470 set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret);
8471 set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump);
8473 /* Hook in ABI-specific overrides, if they have been registered. */
8474 info.tdep_info = (void *) tdesc_data;
8475 gdbarch_init_osabi (info, gdbarch);
8477 if (!i386_validate_tdesc_p (tdep, tdesc_data))
8479 tdesc_data_cleanup (tdesc_data);
8481 gdbarch_free (gdbarch);
8485 num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0);
8487 /* Wire in pseudo registers. Number of pseudo registers may be
8489 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
8490 + tdep->num_word_regs
8491 + tdep->num_dword_regs
8492 + tdep->num_mmx_regs
8493 + tdep->num_ymm_regs
8495 + tdep->num_ymm_avx512_regs
8496 + tdep->num_zmm_regs));
8498 /* Target description may be changed. */
8499 tdesc = tdep->tdesc;
8501 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
8503 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8504 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
8506 /* Make %al the first pseudo-register. */
8507 tdep->al_regnum = gdbarch_num_regs (gdbarch);
8508 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
8510 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
8511 if (tdep->num_dword_regs)
8513 /* Support dword pseudo-register if it hasn't been disabled. */
8514 tdep->eax_regnum = ymm0_regnum;
8515 ymm0_regnum += tdep->num_dword_regs;
8518 tdep->eax_regnum = -1;
8520 mm0_regnum = ymm0_regnum;
8521 if (tdep->num_ymm_regs)
8523 /* Support YMM pseudo-register if it is available. */
8524 tdep->ymm0_regnum = ymm0_regnum;
8525 mm0_regnum += tdep->num_ymm_regs;
8528 tdep->ymm0_regnum = -1;
8530 if (tdep->num_ymm_avx512_regs)
8532 /* Support YMM16-31 pseudo registers if available. */
8533 tdep->ymm16_regnum = mm0_regnum;
8534 mm0_regnum += tdep->num_ymm_avx512_regs;
8537 tdep->ymm16_regnum = -1;
8539 if (tdep->num_zmm_regs)
8541 /* Support ZMM pseudo-register if it is available. */
8542 tdep->zmm0_regnum = mm0_regnum;
8543 mm0_regnum += tdep->num_zmm_regs;
8546 tdep->zmm0_regnum = -1;
8548 bnd0_regnum = mm0_regnum;
8549 if (tdep->num_mmx_regs != 0)
8551 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8552 tdep->mm0_regnum = mm0_regnum;
8553 bnd0_regnum += tdep->num_mmx_regs;
8556 tdep->mm0_regnum = -1;
8558 if (tdep->bnd0r_regnum > 0)
8559 tdep->bnd0_regnum = bnd0_regnum;
8561 tdep-> bnd0_regnum = -1;
8563 /* Hook in the legacy prologue-based unwinders last (fallback). */
8564 frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind);
8565 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
8566 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
8568 /* If we have a register mapping, enable the generic core file
8569 support, unless it has already been enabled. */
8570 if (tdep->gregset_reg_offset
8571 && !gdbarch_iterate_over_regset_sections_p (gdbarch))
8572 set_gdbarch_iterate_over_regset_sections
8573 (gdbarch, i386_iterate_over_regset_sections);
8575 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
8576 i386_fast_tracepoint_valid_at);
8581 static enum gdb_osabi
8582 i386_coff_osabi_sniffer (bfd *abfd)
8584 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
8585 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
8586 return GDB_OSABI_GO32;
8588 return GDB_OSABI_UNKNOWN;
8592 /* Provide a prototype to silence -Wmissing-prototypes. */
8593 void _initialize_i386_tdep (void);
8596 _initialize_i386_tdep (void)
8598 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
8600 /* Add the variable that controls the disassembly flavor. */
8601 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
8602 &disassembly_flavor, _("\
8603 Set the disassembly flavor."), _("\
8604 Show the disassembly flavor."), _("\
8605 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
8607 NULL, /* FIXME: i18n: */
8608 &setlist, &showlist);
8610 /* Add the variable that controls the convention for returning
8612 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
8613 &struct_convention, _("\
8614 Set the convention for returning small structs."), _("\
8615 Show the convention for returning small structs."), _("\
8616 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
8619 NULL, /* FIXME: i18n: */
8620 &setlist, &showlist);
8622 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
8623 i386_coff_osabi_sniffer);
8625 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
8626 i386_svr4_init_abi);
8627 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
8628 i386_go32_init_abi);
8630 /* Initialize the i386-specific register groups. */
8631 i386_init_reggroups ();
8633 /* Initialize the standard target descriptions. */
8634 initialize_tdesc_i386 ();
8635 initialize_tdesc_i386_mmx ();
8636 initialize_tdesc_i386_avx ();
8637 initialize_tdesc_i386_mpx ();
8638 initialize_tdesc_i386_avx512 ();
8640 /* Tell remote stub that we support XML target description. */
8641 register_remote_support_xml ("i386");