1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
37 #include "reggroups.h"
46 #include "exceptions.h"
47 #include "gdb_assert.h"
48 #include "gdb_string.h"
50 #include "i386-tdep.h"
51 #include "i387-tdep.h"
52 #include "i386-xstate.h"
57 #include "features/i386/i386.c"
58 #include "features/i386/i386-avx.c"
59 #include "features/i386/i386-mmx.c"
64 #include "stap-probe.h"
65 #include "user-regs.h"
66 #include "cli/cli-utils.h"
67 #include "expression.h"
68 #include "parser-defs.h"
73 static const char *i386_register_names[] =
75 "eax", "ecx", "edx", "ebx",
76 "esp", "ebp", "esi", "edi",
77 "eip", "eflags", "cs", "ss",
78 "ds", "es", "fs", "gs",
79 "st0", "st1", "st2", "st3",
80 "st4", "st5", "st6", "st7",
81 "fctrl", "fstat", "ftag", "fiseg",
82 "fioff", "foseg", "fooff", "fop",
83 "xmm0", "xmm1", "xmm2", "xmm3",
84 "xmm4", "xmm5", "xmm6", "xmm7",
88 static const char *i386_ymm_names[] =
90 "ymm0", "ymm1", "ymm2", "ymm3",
91 "ymm4", "ymm5", "ymm6", "ymm7",
94 static const char *i386_ymmh_names[] =
96 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
97 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
100 /* Register names for MMX pseudo-registers. */
102 static const char *i386_mmx_names[] =
104 "mm0", "mm1", "mm2", "mm3",
105 "mm4", "mm5", "mm6", "mm7"
108 /* Register names for byte pseudo-registers. */
110 static const char *i386_byte_names[] =
112 "al", "cl", "dl", "bl",
113 "ah", "ch", "dh", "bh"
116 /* Register names for word pseudo-registers. */
118 static const char *i386_word_names[] =
120 "ax", "cx", "dx", "bx",
127 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
129 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
130 int mm0_regnum = tdep->mm0_regnum;
135 regnum -= mm0_regnum;
136 return regnum >= 0 && regnum < tdep->num_mmx_regs;
142 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
144 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
146 regnum -= tdep->al_regnum;
147 return regnum >= 0 && regnum < tdep->num_byte_regs;
153 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
155 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
157 regnum -= tdep->ax_regnum;
158 return regnum >= 0 && regnum < tdep->num_word_regs;
161 /* Dword register? */
164 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
166 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
167 int eax_regnum = tdep->eax_regnum;
172 regnum -= eax_regnum;
173 return regnum >= 0 && regnum < tdep->num_dword_regs;
177 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
179 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
180 int ymm0h_regnum = tdep->ymm0h_regnum;
182 if (ymm0h_regnum < 0)
185 regnum -= ymm0h_regnum;
186 return regnum >= 0 && regnum < tdep->num_ymm_regs;
192 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
194 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
195 int ymm0_regnum = tdep->ymm0_regnum;
200 regnum -= ymm0_regnum;
201 return regnum >= 0 && regnum < tdep->num_ymm_regs;
207 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
209 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
210 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
212 if (num_xmm_regs == 0)
215 regnum -= I387_XMM0_REGNUM (tdep);
216 return regnum >= 0 && regnum < num_xmm_regs;
220 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
222 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
224 if (I387_NUM_XMM_REGS (tdep) == 0)
227 return (regnum == I387_MXCSR_REGNUM (tdep));
233 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
235 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
237 if (I387_ST0_REGNUM (tdep) < 0)
240 return (I387_ST0_REGNUM (tdep) <= regnum
241 && regnum < I387_FCTRL_REGNUM (tdep));
245 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
247 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
249 if (I387_ST0_REGNUM (tdep) < 0)
252 return (I387_FCTRL_REGNUM (tdep) <= regnum
253 && regnum < I387_XMM0_REGNUM (tdep));
256 /* Return the name of register REGNUM, or the empty string if it is
257 an anonymous register. */
260 i386_register_name (struct gdbarch *gdbarch, int regnum)
262 /* Hide the upper YMM registers. */
263 if (i386_ymmh_regnum_p (gdbarch, regnum))
266 return tdesc_register_name (gdbarch, regnum);
269 /* Return the name of register REGNUM. */
272 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
274 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
275 if (i386_mmx_regnum_p (gdbarch, regnum))
276 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
277 else if (i386_ymm_regnum_p (gdbarch, regnum))
278 return i386_ymm_names[regnum - tdep->ymm0_regnum];
279 else if (i386_byte_regnum_p (gdbarch, regnum))
280 return i386_byte_names[regnum - tdep->al_regnum];
281 else if (i386_word_regnum_p (gdbarch, regnum))
282 return i386_word_names[regnum - tdep->ax_regnum];
284 internal_error (__FILE__, __LINE__, _("invalid regnum"));
287 /* Convert a dbx register number REG to the appropriate register
288 number used by GDB. */
291 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
293 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
295 /* This implements what GCC calls the "default" register map
296 (dbx_register_map[]). */
298 if (reg >= 0 && reg <= 7)
300 /* General-purpose registers. The debug info calls %ebp
301 register 4, and %esp register 5. */
308 else if (reg >= 12 && reg <= 19)
310 /* Floating-point registers. */
311 return reg - 12 + I387_ST0_REGNUM (tdep);
313 else if (reg >= 21 && reg <= 28)
316 int ymm0_regnum = tdep->ymm0_regnum;
319 && i386_xmm_regnum_p (gdbarch, reg))
320 return reg - 21 + ymm0_regnum;
322 return reg - 21 + I387_XMM0_REGNUM (tdep);
324 else if (reg >= 29 && reg <= 36)
327 return reg - 29 + I387_MM0_REGNUM (tdep);
330 /* This will hopefully provoke a warning. */
331 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
334 /* Convert SVR4 register number REG to the appropriate register number
338 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
340 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
342 /* This implements the GCC register map that tries to be compatible
343 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
345 /* The SVR4 register numbering includes %eip and %eflags, and
346 numbers the floating point registers differently. */
347 if (reg >= 0 && reg <= 9)
349 /* General-purpose registers. */
352 else if (reg >= 11 && reg <= 18)
354 /* Floating-point registers. */
355 return reg - 11 + I387_ST0_REGNUM (tdep);
357 else if (reg >= 21 && reg <= 36)
359 /* The SSE and MMX registers have the same numbers as with dbx. */
360 return i386_dbx_reg_to_regnum (gdbarch, reg);
365 case 37: return I387_FCTRL_REGNUM (tdep);
366 case 38: return I387_FSTAT_REGNUM (tdep);
367 case 39: return I387_MXCSR_REGNUM (tdep);
368 case 40: return I386_ES_REGNUM;
369 case 41: return I386_CS_REGNUM;
370 case 42: return I386_SS_REGNUM;
371 case 43: return I386_DS_REGNUM;
372 case 44: return I386_FS_REGNUM;
373 case 45: return I386_GS_REGNUM;
376 /* This will hopefully provoke a warning. */
377 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
382 /* This is the variable that is set with "set disassembly-flavor", and
383 its legitimate values. */
384 static const char att_flavor[] = "att";
385 static const char intel_flavor[] = "intel";
386 static const char *const valid_flavors[] =
392 static const char *disassembly_flavor = att_flavor;
395 /* Use the program counter to determine the contents and size of a
396 breakpoint instruction. Return a pointer to a string of bytes that
397 encode a breakpoint instruction, store the length of the string in
398 *LEN and optionally adjust *PC to point to the correct memory
399 location for inserting the breakpoint.
401 On the i386 we have a single breakpoint that fits in a single byte
402 and can be inserted anywhere.
404 This function is 64-bit safe. */
406 static const gdb_byte *
407 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
409 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */
411 *len = sizeof (break_insn);
415 /* Displaced instruction handling. */
417 /* Skip the legacy instruction prefixes in INSN.
418 Not all prefixes are valid for any particular insn
419 but we needn't care, the insn will fault if it's invalid.
420 The result is a pointer to the first opcode byte,
421 or NULL if we run off the end of the buffer. */
424 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
426 gdb_byte *end = insn + max_len;
432 case DATA_PREFIX_OPCODE:
433 case ADDR_PREFIX_OPCODE:
434 case CS_PREFIX_OPCODE:
435 case DS_PREFIX_OPCODE:
436 case ES_PREFIX_OPCODE:
437 case FS_PREFIX_OPCODE:
438 case GS_PREFIX_OPCODE:
439 case SS_PREFIX_OPCODE:
440 case LOCK_PREFIX_OPCODE:
441 case REPE_PREFIX_OPCODE:
442 case REPNE_PREFIX_OPCODE:
454 i386_absolute_jmp_p (const gdb_byte *insn)
456 /* jmp far (absolute address in operand). */
462 /* jump near, absolute indirect (/4). */
463 if ((insn[1] & 0x38) == 0x20)
466 /* jump far, absolute indirect (/5). */
467 if ((insn[1] & 0x38) == 0x28)
475 i386_absolute_call_p (const gdb_byte *insn)
477 /* call far, absolute. */
483 /* Call near, absolute indirect (/2). */
484 if ((insn[1] & 0x38) == 0x10)
487 /* Call far, absolute indirect (/3). */
488 if ((insn[1] & 0x38) == 0x18)
496 i386_ret_p (const gdb_byte *insn)
500 case 0xc2: /* ret near, pop N bytes. */
501 case 0xc3: /* ret near */
502 case 0xca: /* ret far, pop N bytes. */
503 case 0xcb: /* ret far */
504 case 0xcf: /* iret */
513 i386_call_p (const gdb_byte *insn)
515 if (i386_absolute_call_p (insn))
518 /* call near, relative. */
525 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
526 length in bytes. Otherwise, return zero. */
529 i386_syscall_p (const gdb_byte *insn, int *lengthp)
531 /* Is it 'int $0x80'? */
532 if ((insn[0] == 0xcd && insn[1] == 0x80)
533 /* Or is it 'sysenter'? */
534 || (insn[0] == 0x0f && insn[1] == 0x34)
535 /* Or is it 'syscall'? */
536 || (insn[0] == 0x0f && insn[1] == 0x05))
545 /* Some kernels may run one past a syscall insn, so we have to cope.
546 Otherwise this is just simple_displaced_step_copy_insn. */
548 struct displaced_step_closure *
549 i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
550 CORE_ADDR from, CORE_ADDR to,
551 struct regcache *regs)
553 size_t len = gdbarch_max_insn_length (gdbarch);
554 gdb_byte *buf = xmalloc (len);
556 read_memory (from, buf, len);
558 /* GDB may get control back after the insn after the syscall.
559 Presumably this is a kernel bug.
560 If this is a syscall, make sure there's a nop afterwards. */
565 insn = i386_skip_prefixes (buf, len);
566 if (insn != NULL && i386_syscall_p (insn, &syscall_length))
567 insn[syscall_length] = NOP_OPCODE;
570 write_memory (to, buf, len);
574 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
575 paddress (gdbarch, from), paddress (gdbarch, to));
576 displaced_step_dump_bytes (gdb_stdlog, buf, len);
579 return (struct displaced_step_closure *) buf;
582 /* Fix up the state of registers and memory after having single-stepped
583 a displaced instruction. */
586 i386_displaced_step_fixup (struct gdbarch *gdbarch,
587 struct displaced_step_closure *closure,
588 CORE_ADDR from, CORE_ADDR to,
589 struct regcache *regs)
591 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
593 /* The offset we applied to the instruction's address.
594 This could well be negative (when viewed as a signed 32-bit
595 value), but ULONGEST won't reflect that, so take care when
597 ULONGEST insn_offset = to - from;
599 /* Since we use simple_displaced_step_copy_insn, our closure is a
600 copy of the instruction. */
601 gdb_byte *insn = (gdb_byte *) closure;
602 /* The start of the insn, needed in case we see some prefixes. */
603 gdb_byte *insn_start = insn;
606 fprintf_unfiltered (gdb_stdlog,
607 "displaced: fixup (%s, %s), "
608 "insn = 0x%02x 0x%02x ...\n",
609 paddress (gdbarch, from), paddress (gdbarch, to),
612 /* The list of issues to contend with here is taken from
613 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
614 Yay for Free Software! */
616 /* Relocate the %eip, if necessary. */
618 /* The instruction recognizers we use assume any leading prefixes
619 have been skipped. */
621 /* This is the size of the buffer in closure. */
622 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
623 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
624 /* If there are too many prefixes, just ignore the insn.
625 It will fault when run. */
630 /* Except in the case of absolute or indirect jump or call
631 instructions, or a return instruction, the new eip is relative to
632 the displaced instruction; make it relative. Well, signal
633 handler returns don't need relocation either, but we use the
634 value of %eip to recognize those; see below. */
635 if (! i386_absolute_jmp_p (insn)
636 && ! i386_absolute_call_p (insn)
637 && ! i386_ret_p (insn))
642 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
644 /* A signal trampoline system call changes the %eip, resuming
645 execution of the main program after the signal handler has
646 returned. That makes them like 'return' instructions; we
647 shouldn't relocate %eip.
649 But most system calls don't, and we do need to relocate %eip.
651 Our heuristic for distinguishing these cases: if stepping
652 over the system call instruction left control directly after
653 the instruction, the we relocate --- control almost certainly
654 doesn't belong in the displaced copy. Otherwise, we assume
655 the instruction has put control where it belongs, and leave
656 it unrelocated. Goodness help us if there are PC-relative
658 if (i386_syscall_p (insn, &insn_len)
659 && orig_eip != to + (insn - insn_start) + insn_len
660 /* GDB can get control back after the insn after the syscall.
661 Presumably this is a kernel bug.
662 i386_displaced_step_copy_insn ensures its a nop,
663 we add one to the length for it. */
664 && orig_eip != to + (insn - insn_start) + insn_len + 1)
667 fprintf_unfiltered (gdb_stdlog,
668 "displaced: syscall changed %%eip; "
673 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
675 /* If we just stepped over a breakpoint insn, we don't backup
676 the pc on purpose; this is to match behaviour without
679 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
682 fprintf_unfiltered (gdb_stdlog,
684 "relocated %%eip from %s to %s\n",
685 paddress (gdbarch, orig_eip),
686 paddress (gdbarch, eip));
690 /* If the instruction was PUSHFL, then the TF bit will be set in the
691 pushed value, and should be cleared. We'll leave this for later,
692 since GDB already messes up the TF flag when stepping over a
695 /* If the instruction was a call, the return address now atop the
696 stack is the address following the copied instruction. We need
697 to make it the address following the original instruction. */
698 if (i386_call_p (insn))
702 const ULONGEST retaddr_len = 4;
704 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
705 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
706 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
707 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
710 fprintf_unfiltered (gdb_stdlog,
711 "displaced: relocated return addr at %s to %s\n",
712 paddress (gdbarch, esp),
713 paddress (gdbarch, retaddr));
718 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
720 target_write_memory (*to, buf, len);
725 i386_relocate_instruction (struct gdbarch *gdbarch,
726 CORE_ADDR *to, CORE_ADDR oldloc)
728 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
729 gdb_byte buf[I386_MAX_INSN_LEN];
730 int offset = 0, rel32, newrel;
732 gdb_byte *insn = buf;
734 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
736 insn_length = gdb_buffered_insn_length (gdbarch, insn,
737 I386_MAX_INSN_LEN, oldloc);
739 /* Get past the prefixes. */
740 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
742 /* Adjust calls with 32-bit relative addresses as push/jump, with
743 the address pushed being the location where the original call in
744 the user program would return to. */
747 gdb_byte push_buf[16];
748 unsigned int ret_addr;
750 /* Where "ret" in the original code will return to. */
751 ret_addr = oldloc + insn_length;
752 push_buf[0] = 0x68; /* pushq $... */
753 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
755 append_insns (to, 5, push_buf);
757 /* Convert the relative call to a relative jump. */
760 /* Adjust the destination offset. */
761 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
762 newrel = (oldloc - *to) + rel32;
763 store_signed_integer (insn + 1, 4, byte_order, newrel);
766 fprintf_unfiltered (gdb_stdlog,
767 "Adjusted insn rel32=%s at %s to"
769 hex_string (rel32), paddress (gdbarch, oldloc),
770 hex_string (newrel), paddress (gdbarch, *to));
772 /* Write the adjusted jump into its displaced location. */
773 append_insns (to, 5, insn);
777 /* Adjust jumps with 32-bit relative addresses. Calls are already
781 /* Adjust conditional jumps. */
782 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
787 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
788 newrel = (oldloc - *to) + rel32;
789 store_signed_integer (insn + offset, 4, byte_order, newrel);
791 fprintf_unfiltered (gdb_stdlog,
792 "Adjusted insn rel32=%s at %s to"
794 hex_string (rel32), paddress (gdbarch, oldloc),
795 hex_string (newrel), paddress (gdbarch, *to));
798 /* Write the adjusted instructions into their displaced
800 append_insns (to, insn_length, buf);
804 #ifdef I386_REGNO_TO_SYMMETRY
805 #error "The Sequent Symmetry is no longer supported."
808 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
809 and %esp "belong" to the calling function. Therefore these
810 registers should be saved if they're going to be modified. */
812 /* The maximum number of saved registers. This should include all
813 registers mentioned above, and %eip. */
814 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
816 struct i386_frame_cache
824 /* Saved registers. */
825 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
830 /* Stack space reserved for local variables. */
834 /* Allocate and initialize a frame cache. */
836 static struct i386_frame_cache *
837 i386_alloc_frame_cache (void)
839 struct i386_frame_cache *cache;
842 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
847 cache->sp_offset = -4;
850 /* Saved registers. We initialize these to -1 since zero is a valid
851 offset (that's where %ebp is supposed to be stored). */
852 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
853 cache->saved_regs[i] = -1;
855 cache->saved_sp_reg = -1;
856 cache->pc_in_eax = 0;
858 /* Frameless until proven otherwise. */
864 /* If the instruction at PC is a jump, return the address of its
865 target. Otherwise, return PC. */
868 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
870 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
875 if (target_read_memory (pc, &op, 1))
881 op = read_memory_unsigned_integer (pc + 1, 1, byte_order);
887 /* Relative jump: if data16 == 0, disp32, else disp16. */
890 delta = read_memory_integer (pc + 2, 2, byte_order);
892 /* Include the size of the jmp instruction (including the
898 delta = read_memory_integer (pc + 1, 4, byte_order);
900 /* Include the size of the jmp instruction. */
905 /* Relative jump, disp8 (ignore data16). */
906 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
915 /* Check whether PC points at a prologue for a function returning a
916 structure or union. If so, it updates CACHE and returns the
917 address of the first instruction after the code sequence that
918 removes the "hidden" argument from the stack or CURRENT_PC,
919 whichever is smaller. Otherwise, return PC. */
922 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
923 struct i386_frame_cache *cache)
925 /* Functions that return a structure or union start with:
928 xchgl %eax, (%esp) 0x87 0x04 0x24
929 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
931 (the System V compiler puts out the second `xchg' instruction,
932 and the assembler doesn't try to optimize it, so the 'sib' form
933 gets generated). This sequence is used to get the address of the
934 return buffer for a function that returns a structure. */
935 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
936 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
940 if (current_pc <= pc)
943 if (target_read_memory (pc, &op, 1))
946 if (op != 0x58) /* popl %eax */
949 if (target_read_memory (pc + 1, buf, 4))
952 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
955 if (current_pc == pc)
957 cache->sp_offset += 4;
961 if (current_pc == pc + 1)
963 cache->pc_in_eax = 1;
967 if (buf[1] == proto1[1])
974 i386_skip_probe (CORE_ADDR pc)
976 /* A function may start with
990 if (target_read_memory (pc, &op, 1))
993 if (op == 0x68 || op == 0x6a)
997 /* Skip past the `pushl' instruction; it has either a one-byte or a
998 four-byte operand, depending on the opcode. */
1004 /* Read the following 8 bytes, which should be `call _probe' (6
1005 bytes) followed by `addl $4,%esp' (2 bytes). */
1006 read_memory (pc + delta, buf, sizeof (buf));
1007 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
1008 pc += delta + sizeof (buf);
1014 /* GCC 4.1 and later, can put code in the prologue to realign the
1015 stack pointer. Check whether PC points to such code, and update
1016 CACHE accordingly. Return the first instruction after the code
1017 sequence or CURRENT_PC, whichever is smaller. If we don't
1018 recognize the code, return PC. */
1021 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1022 struct i386_frame_cache *cache)
1024 /* There are 2 code sequences to re-align stack before the frame
1027 1. Use a caller-saved saved register:
1033 2. Use a callee-saved saved register:
1040 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1042 0x83 0xe4 0xf0 andl $-16, %esp
1043 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1048 int offset, offset_and;
1049 static int regnums[8] = {
1050 I386_EAX_REGNUM, /* %eax */
1051 I386_ECX_REGNUM, /* %ecx */
1052 I386_EDX_REGNUM, /* %edx */
1053 I386_EBX_REGNUM, /* %ebx */
1054 I386_ESP_REGNUM, /* %esp */
1055 I386_EBP_REGNUM, /* %ebp */
1056 I386_ESI_REGNUM, /* %esi */
1057 I386_EDI_REGNUM /* %edi */
1060 if (target_read_memory (pc, buf, sizeof buf))
1063 /* Check caller-saved saved register. The first instruction has
1064 to be "leal 4(%esp), %reg". */
1065 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1067 /* MOD must be binary 10 and R/M must be binary 100. */
1068 if ((buf[1] & 0xc7) != 0x44)
1071 /* REG has register number. */
1072 reg = (buf[1] >> 3) & 7;
1077 /* Check callee-saved saved register. The first instruction
1078 has to be "pushl %reg". */
1079 if ((buf[0] & 0xf8) != 0x50)
1085 /* The next instruction has to be "leal 8(%esp), %reg". */
1086 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1089 /* MOD must be binary 10 and R/M must be binary 100. */
1090 if ((buf[2] & 0xc7) != 0x44)
1093 /* REG has register number. Registers in pushl and leal have to
1095 if (reg != ((buf[2] >> 3) & 7))
1101 /* Rigister can't be %esp nor %ebp. */
1102 if (reg == 4 || reg == 5)
1105 /* The next instruction has to be "andl $-XXX, %esp". */
1106 if (buf[offset + 1] != 0xe4
1107 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1110 offset_and = offset;
1111 offset += buf[offset] == 0x81 ? 6 : 3;
1113 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1114 0xfc. REG must be binary 110 and MOD must be binary 01. */
1115 if (buf[offset] != 0xff
1116 || buf[offset + 2] != 0xfc
1117 || (buf[offset + 1] & 0xf8) != 0x70)
1120 /* R/M has register. Registers in leal and pushl have to be the
1122 if (reg != (buf[offset + 1] & 7))
1125 if (current_pc > pc + offset_and)
1126 cache->saved_sp_reg = regnums[reg];
1128 return min (pc + offset + 3, current_pc);
1131 /* Maximum instruction length we need to handle. */
1132 #define I386_MAX_MATCHED_INSN_LEN 6
1134 /* Instruction description. */
1138 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
1139 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
1142 /* Return whether instruction at PC matches PATTERN. */
1145 i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern)
1149 if (target_read_memory (pc, &op, 1))
1152 if ((op & pattern.mask[0]) == pattern.insn[0])
1154 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1155 int insn_matched = 1;
1158 gdb_assert (pattern.len > 1);
1159 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN);
1161 if (target_read_memory (pc + 1, buf, pattern.len - 1))
1164 for (i = 1; i < pattern.len; i++)
1166 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i])
1169 return insn_matched;
1174 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1175 the first instruction description that matches. Otherwise, return
1178 static struct i386_insn *
1179 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns)
1181 struct i386_insn *pattern;
1183 for (pattern = insn_patterns; pattern->len > 0; pattern++)
1185 if (i386_match_pattern (pc, *pattern))
1192 /* Return whether PC points inside a sequence of instructions that
1193 matches INSN_PATTERNS. */
1196 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns)
1198 CORE_ADDR current_pc;
1200 struct i386_insn *insn;
1202 insn = i386_match_insn (pc, insn_patterns);
1207 ix = insn - insn_patterns;
1208 for (i = ix - 1; i >= 0; i--)
1210 current_pc -= insn_patterns[i].len;
1212 if (!i386_match_pattern (current_pc, insn_patterns[i]))
1216 current_pc = pc + insn->len;
1217 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++)
1219 if (!i386_match_pattern (current_pc, *insn))
1222 current_pc += insn->len;
1228 /* Some special instructions that might be migrated by GCC into the
1229 part of the prologue that sets up the new stack frame. Because the
1230 stack frame hasn't been setup yet, no registers have been saved
1231 yet, and only the scratch registers %eax, %ecx and %edx can be
1234 struct i386_insn i386_frame_setup_skip_insns[] =
1236 /* Check for `movb imm8, r' and `movl imm32, r'.
1238 ??? Should we handle 16-bit operand-sizes here? */
1240 /* `movb imm8, %al' and `movb imm8, %ah' */
1241 /* `movb imm8, %cl' and `movb imm8, %ch' */
1242 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1243 /* `movb imm8, %dl' and `movb imm8, %dh' */
1244 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1245 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1246 { 5, { 0xb8 }, { 0xfe } },
1247 /* `movl imm32, %edx' */
1248 { 5, { 0xba }, { 0xff } },
1250 /* Check for `mov imm32, r32'. Note that there is an alternative
1251 encoding for `mov m32, %eax'.
1253 ??? Should we handle SIB adressing here?
1254 ??? Should we handle 16-bit operand-sizes here? */
1256 /* `movl m32, %eax' */
1257 { 5, { 0xa1 }, { 0xff } },
1258 /* `movl m32, %eax' and `mov; m32, %ecx' */
1259 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1260 /* `movl m32, %edx' */
1261 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1263 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1264 Because of the symmetry, there are actually two ways to encode
1265 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1266 opcode bytes 0x31 and 0x33 for `xorl'. */
1268 /* `subl %eax, %eax' */
1269 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1270 /* `subl %ecx, %ecx' */
1271 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1272 /* `subl %edx, %edx' */
1273 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1274 /* `xorl %eax, %eax' */
1275 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1276 /* `xorl %ecx, %ecx' */
1277 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1278 /* `xorl %edx, %edx' */
1279 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1284 /* Check whether PC points to a no-op instruction. */
1286 i386_skip_noop (CORE_ADDR pc)
1291 if (target_read_memory (pc, &op, 1))
1297 /* Ignore `nop' instruction. */
1301 if (target_read_memory (pc, &op, 1))
1305 /* Ignore no-op instruction `mov %edi, %edi'.
1306 Microsoft system dlls often start with
1307 a `mov %edi,%edi' instruction.
1308 The 5 bytes before the function start are
1309 filled with `nop' instructions.
1310 This pattern can be used for hot-patching:
1311 The `mov %edi, %edi' instruction can be replaced by a
1312 near jump to the location of the 5 `nop' instructions
1313 which can be replaced by a 32-bit jump to anywhere
1314 in the 32-bit address space. */
1316 else if (op == 0x8b)
1318 if (target_read_memory (pc + 1, &op, 1))
1324 if (target_read_memory (pc, &op, 1))
1334 /* Check whether PC points at a code that sets up a new stack frame.
1335 If so, it updates CACHE and returns the address of the first
1336 instruction after the sequence that sets up the frame or LIMIT,
1337 whichever is smaller. If we don't recognize the code, return PC. */
1340 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1341 CORE_ADDR pc, CORE_ADDR limit,
1342 struct i386_frame_cache *cache)
1344 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1345 struct i386_insn *insn;
1352 if (target_read_memory (pc, &op, 1))
1355 if (op == 0x55) /* pushl %ebp */
1357 /* Take into account that we've executed the `pushl %ebp' that
1358 starts this instruction sequence. */
1359 cache->saved_regs[I386_EBP_REGNUM] = 0;
1360 cache->sp_offset += 4;
1363 /* If that's all, return now. */
1367 /* Check for some special instructions that might be migrated by
1368 GCC into the prologue and skip them. At this point in the
1369 prologue, code should only touch the scratch registers %eax,
1370 %ecx and %edx, so while the number of posibilities is sheer,
1373 Make sure we only skip these instructions if we later see the
1374 `movl %esp, %ebp' that actually sets up the frame. */
1375 while (pc + skip < limit)
1377 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1384 /* If that's all, return now. */
1385 if (limit <= pc + skip)
1388 if (target_read_memory (pc + skip, &op, 1))
1391 /* The i386 prologue looks like
1397 and a different prologue can be generated for atom.
1401 lea -0x10(%esp),%esp
1403 We handle both of them here. */
1407 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1409 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1415 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1420 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1421 if (read_memory_unsigned_integer (pc + skip + 1, 2, byte_order)
1430 /* OK, we actually have a frame. We just don't know how large
1431 it is yet. Set its size to zero. We'll adjust it if
1432 necessary. We also now commit to skipping the special
1433 instructions mentioned before. */
1436 /* If that's all, return now. */
1440 /* Check for stack adjustment
1446 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1447 reg, so we don't have to worry about a data16 prefix. */
1448 if (target_read_memory (pc, &op, 1))
1452 /* `subl' with 8-bit immediate. */
1453 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1454 /* Some instruction starting with 0x83 other than `subl'. */
1457 /* `subl' with signed 8-bit immediate (though it wouldn't
1458 make sense to be negative). */
1459 cache->locals = read_memory_integer (pc + 2, 1, byte_order);
1462 else if (op == 0x81)
1464 /* Maybe it is `subl' with a 32-bit immediate. */
1465 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1466 /* Some instruction starting with 0x81 other than `subl'. */
1469 /* It is `subl' with a 32-bit immediate. */
1470 cache->locals = read_memory_integer (pc + 2, 4, byte_order);
1473 else if (op == 0x8d)
1475 /* The ModR/M byte is 0x64. */
1476 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0x64)
1478 /* 'lea' with 8-bit displacement. */
1479 cache->locals = -1 * read_memory_integer (pc + 3, 1, byte_order);
1484 /* Some instruction other than `subl' nor 'lea'. */
1488 else if (op == 0xc8) /* enter */
1490 cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order);
1497 /* Check whether PC points at code that saves registers on the stack.
1498 If so, it updates CACHE and returns the address of the first
1499 instruction after the register saves or CURRENT_PC, whichever is
1500 smaller. Otherwise, return PC. */
1503 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1504 struct i386_frame_cache *cache)
1506 CORE_ADDR offset = 0;
1510 if (cache->locals > 0)
1511 offset -= cache->locals;
1512 for (i = 0; i < 8 && pc < current_pc; i++)
1514 if (target_read_memory (pc, &op, 1))
1516 if (op < 0x50 || op > 0x57)
1520 cache->saved_regs[op - 0x50] = offset;
1521 cache->sp_offset += 4;
1528 /* Do a full analysis of the prologue at PC and update CACHE
1529 accordingly. Bail out early if CURRENT_PC is reached. Return the
1530 address where the analysis stopped.
1532 We handle these cases:
1534 The startup sequence can be at the start of the function, or the
1535 function can start with a branch to startup code at the end.
1537 %ebp can be set up with either the 'enter' instruction, or "pushl
1538 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1539 once used in the System V compiler).
1541 Local space is allocated just below the saved %ebp by either the
1542 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1543 16-bit unsigned argument for space to allocate, and the 'addl'
1544 instruction could have either a signed byte, or 32-bit immediate.
1546 Next, the registers used by this function are pushed. With the
1547 System V compiler they will always be in the order: %edi, %esi,
1548 %ebx (and sometimes a harmless bug causes it to also save but not
1549 restore %eax); however, the code below is willing to see the pushes
1550 in any order, and will handle up to 8 of them.
1552 If the setup sequence is at the end of the function, then the next
1553 instruction will be a branch back to the start. */
1556 i386_analyze_prologue (struct gdbarch *gdbarch,
1557 CORE_ADDR pc, CORE_ADDR current_pc,
1558 struct i386_frame_cache *cache)
1560 pc = i386_skip_noop (pc);
1561 pc = i386_follow_jump (gdbarch, pc);
1562 pc = i386_analyze_struct_return (pc, current_pc, cache);
1563 pc = i386_skip_probe (pc);
1564 pc = i386_analyze_stack_align (pc, current_pc, cache);
1565 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1566 return i386_analyze_register_saves (pc, current_pc, cache);
1569 /* Return PC of first real instruction. */
1572 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1574 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1576 static gdb_byte pic_pat[6] =
1578 0xe8, 0, 0, 0, 0, /* call 0x0 */
1579 0x5b, /* popl %ebx */
1581 struct i386_frame_cache cache;
1587 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1588 if (cache.locals < 0)
1591 /* Found valid frame setup. */
1593 /* The native cc on SVR4 in -K PIC mode inserts the following code
1594 to get the address of the global offset table (GOT) into register
1599 movl %ebx,x(%ebp) (optional)
1602 This code is with the rest of the prologue (at the end of the
1603 function), so we have to skip it to get to the first real
1604 instruction at the start of the function. */
1606 for (i = 0; i < 6; i++)
1608 if (target_read_memory (pc + i, &op, 1))
1611 if (pic_pat[i] != op)
1618 if (target_read_memory (pc + delta, &op, 1))
1621 if (op == 0x89) /* movl %ebx, x(%ebp) */
1623 op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order);
1625 if (op == 0x5d) /* One byte offset from %ebp. */
1627 else if (op == 0x9d) /* Four byte offset from %ebp. */
1629 else /* Unexpected instruction. */
1632 if (target_read_memory (pc + delta, &op, 1))
1637 if (delta > 0 && op == 0x81
1638 && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order)
1645 /* If the function starts with a branch (to startup code at the end)
1646 the last instruction should bring us back to the first
1647 instruction of the real code. */
1648 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1649 pc = i386_follow_jump (gdbarch, pc);
1654 /* Check that the code pointed to by PC corresponds to a call to
1655 __main, skip it if so. Return PC otherwise. */
1658 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1660 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1663 if (target_read_memory (pc, &op, 1))
1669 if (target_read_memory (pc + 1, buf, sizeof buf) == 0)
1671 /* Make sure address is computed correctly as a 32bit
1672 integer even if CORE_ADDR is 64 bit wide. */
1673 struct minimal_symbol *s;
1674 CORE_ADDR call_dest;
1676 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1677 call_dest = call_dest & 0xffffffffU;
1678 s = lookup_minimal_symbol_by_pc (call_dest);
1680 && SYMBOL_LINKAGE_NAME (s) != NULL
1681 && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0)
1689 /* This function is 64-bit safe. */
1692 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1696 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1697 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1701 /* Normal frames. */
1704 i386_frame_cache_1 (struct frame_info *this_frame,
1705 struct i386_frame_cache *cache)
1707 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1708 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1712 cache->pc = get_frame_func (this_frame);
1714 /* In principle, for normal frames, %ebp holds the frame pointer,
1715 which holds the base address for the current stack frame.
1716 However, for functions that don't need it, the frame pointer is
1717 optional. For these "frameless" functions the frame pointer is
1718 actually the frame pointer of the calling frame. Signal
1719 trampolines are just a special case of a "frameless" function.
1720 They (usually) share their frame pointer with the frame that was
1721 in progress when the signal occurred. */
1723 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1724 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1725 if (cache->base == 0)
1731 /* For normal frames, %eip is stored at 4(%ebp). */
1732 cache->saved_regs[I386_EIP_REGNUM] = 4;
1735 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
1738 if (cache->locals < 0)
1740 /* We didn't find a valid frame, which means that CACHE->base
1741 currently holds the frame pointer for our calling frame. If
1742 we're at the start of a function, or somewhere half-way its
1743 prologue, the function's frame probably hasn't been fully
1744 setup yet. Try to reconstruct the base address for the stack
1745 frame by looking at the stack pointer. For truly "frameless"
1746 functions this might work too. */
1748 if (cache->saved_sp_reg != -1)
1750 /* Saved stack pointer has been saved. */
1751 get_frame_register (this_frame, cache->saved_sp_reg, buf);
1752 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
1754 /* We're halfway aligning the stack. */
1755 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
1756 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
1758 /* This will be added back below. */
1759 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
1761 else if (cache->pc != 0
1762 || target_read_memory (get_frame_pc (this_frame), buf, 1))
1764 /* We're in a known function, but did not find a frame
1765 setup. Assume that the function does not use %ebp.
1766 Alternatively, we may have jumped to an invalid
1767 address; in that case there is definitely no new
1769 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1770 cache->base = extract_unsigned_integer (buf, 4, byte_order)
1774 /* We're in an unknown function. We could not find the start
1775 of the function to analyze the prologue; our best option is
1776 to assume a typical frame layout with the caller's %ebp
1778 cache->saved_regs[I386_EBP_REGNUM] = 0;
1781 if (cache->saved_sp_reg != -1)
1783 /* Saved stack pointer has been saved (but the SAVED_SP_REG
1784 register may be unavailable). */
1785 if (cache->saved_sp == 0
1786 && frame_register_read (this_frame, cache->saved_sp_reg, buf))
1787 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
1789 /* Now that we have the base address for the stack frame we can
1790 calculate the value of %esp in the calling frame. */
1791 else if (cache->saved_sp == 0)
1792 cache->saved_sp = cache->base + 8;
1794 /* Adjust all the saved registers such that they contain addresses
1795 instead of offsets. */
1796 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1797 if (cache->saved_regs[i] != -1)
1798 cache->saved_regs[i] += cache->base;
1803 static struct i386_frame_cache *
1804 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
1806 volatile struct gdb_exception ex;
1807 struct i386_frame_cache *cache;
1812 cache = i386_alloc_frame_cache ();
1813 *this_cache = cache;
1815 TRY_CATCH (ex, RETURN_MASK_ERROR)
1817 i386_frame_cache_1 (this_frame, cache);
1819 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
1820 throw_exception (ex);
1826 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
1827 struct frame_id *this_id)
1829 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1831 /* This marks the outermost frame. */
1832 if (cache->base == 0)
1835 /* See the end of i386_push_dummy_call. */
1836 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
1839 static enum unwind_stop_reason
1840 i386_frame_unwind_stop_reason (struct frame_info *this_frame,
1843 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1846 return UNWIND_UNAVAILABLE;
1848 /* This marks the outermost frame. */
1849 if (cache->base == 0)
1850 return UNWIND_OUTERMOST;
1852 return UNWIND_NO_REASON;
1855 static struct value *
1856 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
1859 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1861 gdb_assert (regnum >= 0);
1863 /* The System V ABI says that:
1865 "The flags register contains the system flags, such as the
1866 direction flag and the carry flag. The direction flag must be
1867 set to the forward (that is, zero) direction before entry and
1868 upon exit from a function. Other user flags have no specified
1869 role in the standard calling sequence and are not preserved."
1871 To guarantee the "upon exit" part of that statement we fake a
1872 saved flags register that has its direction flag cleared.
1874 Note that GCC doesn't seem to rely on the fact that the direction
1875 flag is cleared after a function return; it always explicitly
1876 clears the flag before operations where it matters.
1878 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1879 right thing to do. The way we fake the flags register here makes
1880 it impossible to change it. */
1882 if (regnum == I386_EFLAGS_REGNUM)
1886 val = get_frame_register_unsigned (this_frame, regnum);
1888 return frame_unwind_got_constant (this_frame, regnum, val);
1891 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
1892 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
1894 if (regnum == I386_ESP_REGNUM
1895 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1))
1897 /* If the SP has been saved, but we don't know where, then this
1898 means that SAVED_SP_REG register was found unavailable back
1899 when we built the cache. */
1900 if (cache->saved_sp == 0)
1901 return frame_unwind_got_register (this_frame, regnum,
1902 cache->saved_sp_reg);
1904 return frame_unwind_got_constant (this_frame, regnum,
1908 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
1909 return frame_unwind_got_memory (this_frame, regnum,
1910 cache->saved_regs[regnum]);
1912 return frame_unwind_got_register (this_frame, regnum, regnum);
1915 static const struct frame_unwind i386_frame_unwind =
1918 i386_frame_unwind_stop_reason,
1920 i386_frame_prev_register,
1922 default_frame_sniffer
1925 /* Normal frames, but in a function epilogue. */
1927 /* The epilogue is defined here as the 'ret' instruction, which will
1928 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1929 the function's stack frame. */
1932 i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1935 struct symtab *symtab;
1937 symtab = find_pc_symtab (pc);
1938 if (symtab && symtab->epilogue_unwind_valid)
1941 if (target_read_memory (pc, &insn, 1))
1942 return 0; /* Can't read memory at pc. */
1944 if (insn != 0xc3) /* 'ret' instruction. */
1951 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
1952 struct frame_info *this_frame,
1953 void **this_prologue_cache)
1955 if (frame_relative_level (this_frame) == 0)
1956 return i386_in_function_epilogue_p (get_frame_arch (this_frame),
1957 get_frame_pc (this_frame));
1962 static struct i386_frame_cache *
1963 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
1965 volatile struct gdb_exception ex;
1966 struct i386_frame_cache *cache;
1972 cache = i386_alloc_frame_cache ();
1973 *this_cache = cache;
1975 TRY_CATCH (ex, RETURN_MASK_ERROR)
1977 cache->pc = get_frame_func (this_frame);
1979 /* At this point the stack looks as if we just entered the
1980 function, with the return address at the top of the
1982 sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM);
1983 cache->base = sp + cache->sp_offset;
1984 cache->saved_sp = cache->base + 8;
1985 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
1989 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
1990 throw_exception (ex);
1995 static enum unwind_stop_reason
1996 i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
1999 struct i386_frame_cache *cache =
2000 i386_epilogue_frame_cache (this_frame, this_cache);
2003 return UNWIND_UNAVAILABLE;
2005 return UNWIND_NO_REASON;
2009 i386_epilogue_frame_this_id (struct frame_info *this_frame,
2011 struct frame_id *this_id)
2013 struct i386_frame_cache *cache =
2014 i386_epilogue_frame_cache (this_frame, this_cache);
2019 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2022 static struct value *
2023 i386_epilogue_frame_prev_register (struct frame_info *this_frame,
2024 void **this_cache, int regnum)
2026 /* Make sure we've initialized the cache. */
2027 i386_epilogue_frame_cache (this_frame, this_cache);
2029 return i386_frame_prev_register (this_frame, this_cache, regnum);
2032 static const struct frame_unwind i386_epilogue_frame_unwind =
2035 i386_epilogue_frame_unwind_stop_reason,
2036 i386_epilogue_frame_this_id,
2037 i386_epilogue_frame_prev_register,
2039 i386_epilogue_frame_sniffer
2043 /* Stack-based trampolines. */
2045 /* These trampolines are used on cross x86 targets, when taking the
2046 address of a nested function. When executing these trampolines,
2047 no stack frame is set up, so we are in a similar situation as in
2048 epilogues and i386_epilogue_frame_this_id can be re-used. */
2050 /* Static chain passed in register. */
2052 struct i386_insn i386_tramp_chain_in_reg_insns[] =
2054 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2055 { 5, { 0xb8 }, { 0xfe } },
2058 { 5, { 0xe9 }, { 0xff } },
2063 /* Static chain passed on stack (when regparm=3). */
2065 struct i386_insn i386_tramp_chain_on_stack_insns[] =
2068 { 5, { 0x68 }, { 0xff } },
2071 { 5, { 0xe9 }, { 0xff } },
2076 /* Return whether PC points inside a stack trampoline. */
2079 i386_in_stack_tramp_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2084 /* A stack trampoline is detected if no name is associated
2085 to the current pc and if it points inside a trampoline
2088 find_pc_partial_function (pc, &name, NULL, NULL);
2092 if (target_read_memory (pc, &insn, 1))
2095 if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns)
2096 && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns))
2103 i386_stack_tramp_frame_sniffer (const struct frame_unwind *self,
2104 struct frame_info *this_frame,
2107 if (frame_relative_level (this_frame) == 0)
2108 return i386_in_stack_tramp_p (get_frame_arch (this_frame),
2109 get_frame_pc (this_frame));
2114 static const struct frame_unwind i386_stack_tramp_frame_unwind =
2117 i386_epilogue_frame_unwind_stop_reason,
2118 i386_epilogue_frame_this_id,
2119 i386_epilogue_frame_prev_register,
2121 i386_stack_tramp_frame_sniffer
2124 /* Generate a bytecode expression to get the value of the saved PC. */
2127 i386_gen_return_address (struct gdbarch *gdbarch,
2128 struct agent_expr *ax, struct axs_value *value,
2131 /* The following sequence assumes the traditional use of the base
2133 ax_reg (ax, I386_EBP_REGNUM);
2135 ax_simple (ax, aop_add);
2136 value->type = register_type (gdbarch, I386_EIP_REGNUM);
2137 value->kind = axs_lvalue_memory;
2141 /* Signal trampolines. */
2143 static struct i386_frame_cache *
2144 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2146 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2147 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2148 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2149 volatile struct gdb_exception ex;
2150 struct i386_frame_cache *cache;
2157 cache = i386_alloc_frame_cache ();
2159 TRY_CATCH (ex, RETURN_MASK_ERROR)
2161 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2162 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
2164 addr = tdep->sigcontext_addr (this_frame);
2165 if (tdep->sc_reg_offset)
2169 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
2171 for (i = 0; i < tdep->sc_num_regs; i++)
2172 if (tdep->sc_reg_offset[i] != -1)
2173 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2177 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
2178 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
2183 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2184 throw_exception (ex);
2186 *this_cache = cache;
2190 static enum unwind_stop_reason
2191 i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2194 struct i386_frame_cache *cache =
2195 i386_sigtramp_frame_cache (this_frame, this_cache);
2198 return UNWIND_UNAVAILABLE;
2200 return UNWIND_NO_REASON;
2204 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
2205 struct frame_id *this_id)
2207 struct i386_frame_cache *cache =
2208 i386_sigtramp_frame_cache (this_frame, this_cache);
2213 /* See the end of i386_push_dummy_call. */
2214 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
2217 static struct value *
2218 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
2219 void **this_cache, int regnum)
2221 /* Make sure we've initialized the cache. */
2222 i386_sigtramp_frame_cache (this_frame, this_cache);
2224 return i386_frame_prev_register (this_frame, this_cache, regnum);
2228 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
2229 struct frame_info *this_frame,
2230 void **this_prologue_cache)
2232 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2234 /* We shouldn't even bother if we don't have a sigcontext_addr
2236 if (tdep->sigcontext_addr == NULL)
2239 if (tdep->sigtramp_p != NULL)
2241 if (tdep->sigtramp_p (this_frame))
2245 if (tdep->sigtramp_start != 0)
2247 CORE_ADDR pc = get_frame_pc (this_frame);
2249 gdb_assert (tdep->sigtramp_end != 0);
2250 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2257 static const struct frame_unwind i386_sigtramp_frame_unwind =
2260 i386_sigtramp_frame_unwind_stop_reason,
2261 i386_sigtramp_frame_this_id,
2262 i386_sigtramp_frame_prev_register,
2264 i386_sigtramp_frame_sniffer
2269 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
2271 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2276 static const struct frame_base i386_frame_base =
2279 i386_frame_base_address,
2280 i386_frame_base_address,
2281 i386_frame_base_address
2284 static struct frame_id
2285 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2289 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
2291 /* See the end of i386_push_dummy_call. */
2292 return frame_id_build (fp + 8, get_frame_pc (this_frame));
2295 /* _Decimal128 function return values need 16-byte alignment on the
2299 i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2301 return sp & -(CORE_ADDR)16;
2305 /* Figure out where the longjmp will land. Slurp the args out of the
2306 stack. We expect the first arg to be a pointer to the jmp_buf
2307 structure from which we extract the address that we will land at.
2308 This address is copied into PC. This routine returns non-zero on
2312 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2315 CORE_ADDR sp, jb_addr;
2316 struct gdbarch *gdbarch = get_frame_arch (frame);
2317 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2318 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2320 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2321 longjmp will land. */
2322 if (jb_pc_offset == -1)
2325 get_frame_register (frame, I386_ESP_REGNUM, buf);
2326 sp = extract_unsigned_integer (buf, 4, byte_order);
2327 if (target_read_memory (sp + 4, buf, 4))
2330 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
2331 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
2334 *pc = extract_unsigned_integer (buf, 4, byte_order);
2339 /* Check whether TYPE must be 16-byte-aligned when passed as a
2340 function argument. 16-byte vectors, _Decimal128 and structures or
2341 unions containing such types must be 16-byte-aligned; other
2342 arguments are 4-byte-aligned. */
2345 i386_16_byte_align_p (struct type *type)
2347 type = check_typedef (type);
2348 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
2349 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
2350 && TYPE_LENGTH (type) == 16)
2352 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2353 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
2354 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2355 || TYPE_CODE (type) == TYPE_CODE_UNION)
2358 for (i = 0; i < TYPE_NFIELDS (type); i++)
2360 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
2367 /* Implementation for set_gdbarch_push_dummy_code. */
2370 i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
2371 struct value **args, int nargs, struct type *value_type,
2372 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
2373 struct regcache *regcache)
2375 /* Use 0xcc breakpoint - 1 byte. */
2379 /* Keep the stack aligned. */
2384 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2385 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2386 struct value **args, CORE_ADDR sp, int struct_return,
2387 CORE_ADDR struct_addr)
2389 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2395 /* Determine the total space required for arguments and struct
2396 return address in a first pass (allowing for 16-byte-aligned
2397 arguments), then push arguments in a second pass. */
2399 for (write_pass = 0; write_pass < 2; write_pass++)
2401 int args_space_used = 0;
2407 /* Push value address. */
2408 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2409 write_memory (sp, buf, 4);
2410 args_space_used += 4;
2416 for (i = 0; i < nargs; i++)
2418 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2422 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2423 args_space_used = align_up (args_space_used, 16);
2425 write_memory (sp + args_space_used,
2426 value_contents_all (args[i]), len);
2427 /* The System V ABI says that:
2429 "An argument's size is increased, if necessary, to make it a
2430 multiple of [32-bit] words. This may require tail padding,
2431 depending on the size of the argument."
2433 This makes sure the stack stays word-aligned. */
2434 args_space_used += align_up (len, 4);
2438 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2439 args_space = align_up (args_space, 16);
2440 args_space += align_up (len, 4);
2448 /* The original System V ABI only requires word alignment,
2449 but modern incarnations need 16-byte alignment in order
2450 to support SSE. Since wasting a few bytes here isn't
2451 harmful we unconditionally enforce 16-byte alignment. */
2456 /* Store return address. */
2458 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2459 write_memory (sp, buf, 4);
2461 /* Finally, update the stack pointer... */
2462 store_unsigned_integer (buf, 4, byte_order, sp);
2463 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
2465 /* ...and fake a frame pointer. */
2466 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
2468 /* MarkK wrote: This "+ 8" is all over the place:
2469 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2470 i386_dummy_id). It's there, since all frame unwinders for
2471 a given target have to agree (within a certain margin) on the
2472 definition of the stack address of a frame. Otherwise frame id
2473 comparison might not work correctly. Since DWARF2/GCC uses the
2474 stack address *before* the function call as a frame's CFA. On
2475 the i386, when %ebp is used as a frame pointer, the offset
2476 between the contents %ebp and the CFA as defined by GCC. */
2480 /* These registers are used for returning integers (and on some
2481 targets also for returning `struct' and `union' values when their
2482 size and alignment match an integer type). */
2483 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2484 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2486 /* Read, for architecture GDBARCH, a function return value of TYPE
2487 from REGCACHE, and copy that into VALBUF. */
2490 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2491 struct regcache *regcache, gdb_byte *valbuf)
2493 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2494 int len = TYPE_LENGTH (type);
2495 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2497 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2499 if (tdep->st0_regnum < 0)
2501 warning (_("Cannot find floating-point return value."));
2502 memset (valbuf, 0, len);
2506 /* Floating-point return values can be found in %st(0). Convert
2507 its contents to the desired type. This is probably not
2508 exactly how it would happen on the target itself, but it is
2509 the best we can do. */
2510 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2511 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
2515 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2516 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2518 if (len <= low_size)
2520 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2521 memcpy (valbuf, buf, len);
2523 else if (len <= (low_size + high_size))
2525 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2526 memcpy (valbuf, buf, low_size);
2527 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2528 memcpy (valbuf + low_size, buf, len - low_size);
2531 internal_error (__FILE__, __LINE__,
2532 _("Cannot extract return value of %d bytes long."),
2537 /* Write, for architecture GDBARCH, a function return value of TYPE
2538 from VALBUF into REGCACHE. */
2541 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2542 struct regcache *regcache, const gdb_byte *valbuf)
2544 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2545 int len = TYPE_LENGTH (type);
2547 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2550 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2552 if (tdep->st0_regnum < 0)
2554 warning (_("Cannot set floating-point return value."));
2558 /* Returning floating-point values is a bit tricky. Apart from
2559 storing the return value in %st(0), we have to simulate the
2560 state of the FPU at function return point. */
2562 /* Convert the value found in VALBUF to the extended
2563 floating-point format used by the FPU. This is probably
2564 not exactly how it would happen on the target itself, but
2565 it is the best we can do. */
2566 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
2567 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2569 /* Set the top of the floating-point register stack to 7. The
2570 actual value doesn't really matter, but 7 is what a normal
2571 function return would end up with if the program started out
2572 with a freshly initialized FPU. */
2573 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2575 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2577 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2578 the floating-point register stack to 7, the appropriate value
2579 for the tag word is 0x3fff. */
2580 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2584 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2585 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2587 if (len <= low_size)
2588 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2589 else if (len <= (low_size + high_size))
2591 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2592 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
2593 len - low_size, valbuf + low_size);
2596 internal_error (__FILE__, __LINE__,
2597 _("Cannot store return value of %d bytes long."), len);
2602 /* This is the variable that is set with "set struct-convention", and
2603 its legitimate values. */
2604 static const char default_struct_convention[] = "default";
2605 static const char pcc_struct_convention[] = "pcc";
2606 static const char reg_struct_convention[] = "reg";
2607 static const char *const valid_conventions[] =
2609 default_struct_convention,
2610 pcc_struct_convention,
2611 reg_struct_convention,
2614 static const char *struct_convention = default_struct_convention;
2616 /* Return non-zero if TYPE, which is assumed to be a structure,
2617 a union type, or an array type, should be returned in registers
2618 for architecture GDBARCH. */
2621 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2623 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2624 enum type_code code = TYPE_CODE (type);
2625 int len = TYPE_LENGTH (type);
2627 gdb_assert (code == TYPE_CODE_STRUCT
2628 || code == TYPE_CODE_UNION
2629 || code == TYPE_CODE_ARRAY);
2631 if (struct_convention == pcc_struct_convention
2632 || (struct_convention == default_struct_convention
2633 && tdep->struct_return == pcc_struct_return))
2636 /* Structures consisting of a single `float', `double' or 'long
2637 double' member are returned in %st(0). */
2638 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2640 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2641 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2642 return (len == 4 || len == 8 || len == 12);
2645 return (len == 1 || len == 2 || len == 4 || len == 8);
2648 /* Determine, for architecture GDBARCH, how a return value of TYPE
2649 should be returned. If it is supposed to be returned in registers,
2650 and READBUF is non-zero, read the appropriate value from REGCACHE,
2651 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2652 from WRITEBUF into REGCACHE. */
2654 static enum return_value_convention
2655 i386_return_value (struct gdbarch *gdbarch, struct value *function,
2656 struct type *type, struct regcache *regcache,
2657 gdb_byte *readbuf, const gdb_byte *writebuf)
2659 enum type_code code = TYPE_CODE (type);
2661 if (((code == TYPE_CODE_STRUCT
2662 || code == TYPE_CODE_UNION
2663 || code == TYPE_CODE_ARRAY)
2664 && !i386_reg_struct_return_p (gdbarch, type))
2665 /* Complex double and long double uses the struct return covention. */
2666 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16)
2667 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24)
2668 /* 128-bit decimal float uses the struct return convention. */
2669 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2671 /* The System V ABI says that:
2673 "A function that returns a structure or union also sets %eax
2674 to the value of the original address of the caller's area
2675 before it returns. Thus when the caller receives control
2676 again, the address of the returned object resides in register
2677 %eax and can be used to access the object."
2679 So the ABI guarantees that we can always find the return
2680 value just after the function has returned. */
2682 /* Note that the ABI doesn't mention functions returning arrays,
2683 which is something possible in certain languages such as Ada.
2684 In this case, the value is returned as if it was wrapped in
2685 a record, so the convention applied to records also applies
2692 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2693 read_memory (addr, readbuf, TYPE_LENGTH (type));
2696 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2699 /* This special case is for structures consisting of a single
2700 `float', `double' or 'long double' member. These structures are
2701 returned in %st(0). For these structures, we call ourselves
2702 recursively, changing TYPE into the type of the first member of
2703 the structure. Since that should work for all structures that
2704 have only one member, we don't bother to check the member's type
2706 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2708 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2709 return i386_return_value (gdbarch, function, type, regcache,
2714 i386_extract_return_value (gdbarch, type, regcache, readbuf);
2716 i386_store_return_value (gdbarch, type, regcache, writebuf);
2718 return RETURN_VALUE_REGISTER_CONVENTION;
2723 i387_ext_type (struct gdbarch *gdbarch)
2725 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2727 if (!tdep->i387_ext_type)
2729 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
2730 gdb_assert (tdep->i387_ext_type != NULL);
2733 return tdep->i387_ext_type;
2736 /* Construct vector type for pseudo YMM registers. We can't use
2737 tdesc_find_type since YMM isn't described in target description. */
2739 static struct type *
2740 i386_ymm_type (struct gdbarch *gdbarch)
2742 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2744 if (!tdep->i386_ymm_type)
2746 const struct builtin_type *bt = builtin_type (gdbarch);
2748 /* The type we're building is this: */
2750 union __gdb_builtin_type_vec256i
2752 int128_t uint128[2];
2753 int64_t v2_int64[4];
2754 int32_t v4_int32[8];
2755 int16_t v8_int16[16];
2756 int8_t v16_int8[32];
2757 double v2_double[4];
2764 t = arch_composite_type (gdbarch,
2765 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
2766 append_composite_type_field (t, "v8_float",
2767 init_vector_type (bt->builtin_float, 8));
2768 append_composite_type_field (t, "v4_double",
2769 init_vector_type (bt->builtin_double, 4));
2770 append_composite_type_field (t, "v32_int8",
2771 init_vector_type (bt->builtin_int8, 32));
2772 append_composite_type_field (t, "v16_int16",
2773 init_vector_type (bt->builtin_int16, 16));
2774 append_composite_type_field (t, "v8_int32",
2775 init_vector_type (bt->builtin_int32, 8));
2776 append_composite_type_field (t, "v4_int64",
2777 init_vector_type (bt->builtin_int64, 4));
2778 append_composite_type_field (t, "v2_int128",
2779 init_vector_type (bt->builtin_int128, 2));
2781 TYPE_VECTOR (t) = 1;
2782 TYPE_NAME (t) = "builtin_type_vec256i";
2783 tdep->i386_ymm_type = t;
2786 return tdep->i386_ymm_type;
2789 /* Construct vector type for MMX registers. */
2790 static struct type *
2791 i386_mmx_type (struct gdbarch *gdbarch)
2793 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2795 if (!tdep->i386_mmx_type)
2797 const struct builtin_type *bt = builtin_type (gdbarch);
2799 /* The type we're building is this: */
2801 union __gdb_builtin_type_vec64i
2804 int32_t v2_int32[2];
2805 int16_t v4_int16[4];
2812 t = arch_composite_type (gdbarch,
2813 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
2815 append_composite_type_field (t, "uint64", bt->builtin_int64);
2816 append_composite_type_field (t, "v2_int32",
2817 init_vector_type (bt->builtin_int32, 2));
2818 append_composite_type_field (t, "v4_int16",
2819 init_vector_type (bt->builtin_int16, 4));
2820 append_composite_type_field (t, "v8_int8",
2821 init_vector_type (bt->builtin_int8, 8));
2823 TYPE_VECTOR (t) = 1;
2824 TYPE_NAME (t) = "builtin_type_vec64i";
2825 tdep->i386_mmx_type = t;
2828 return tdep->i386_mmx_type;
2831 /* Return the GDB type object for the "standard" data type of data in
2835 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2837 if (i386_mmx_regnum_p (gdbarch, regnum))
2838 return i386_mmx_type (gdbarch);
2839 else if (i386_ymm_regnum_p (gdbarch, regnum))
2840 return i386_ymm_type (gdbarch);
2843 const struct builtin_type *bt = builtin_type (gdbarch);
2844 if (i386_byte_regnum_p (gdbarch, regnum))
2845 return bt->builtin_int8;
2846 else if (i386_word_regnum_p (gdbarch, regnum))
2847 return bt->builtin_int16;
2848 else if (i386_dword_regnum_p (gdbarch, regnum))
2849 return bt->builtin_int32;
2852 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2855 /* Map a cooked register onto a raw register or memory. For the i386,
2856 the MMX registers need to be mapped onto floating point registers. */
2859 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
2861 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
2866 mmxreg = regnum - tdep->mm0_regnum;
2867 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2868 tos = (fstat >> 11) & 0x7;
2869 fpreg = (mmxreg + tos) % 8;
2871 return (I387_ST0_REGNUM (tdep) + fpreg);
2874 /* A helper function for us by i386_pseudo_register_read_value and
2875 amd64_pseudo_register_read_value. It does all the work but reads
2876 the data into an already-allocated value. */
2879 i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
2880 struct regcache *regcache,
2882 struct value *result_value)
2884 gdb_byte raw_buf[MAX_REGISTER_SIZE];
2885 enum register_status status;
2886 gdb_byte *buf = value_contents_raw (result_value);
2888 if (i386_mmx_regnum_p (gdbarch, regnum))
2890 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2892 /* Extract (always little endian). */
2893 status = regcache_raw_read (regcache, fpnum, raw_buf);
2894 if (status != REG_VALID)
2895 mark_value_bytes_unavailable (result_value, 0,
2896 TYPE_LENGTH (value_type (result_value)));
2898 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
2902 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2904 if (i386_ymm_regnum_p (gdbarch, regnum))
2906 regnum -= tdep->ymm0_regnum;
2908 /* Extract (always little endian). Read lower 128bits. */
2909 status = regcache_raw_read (regcache,
2910 I387_XMM0_REGNUM (tdep) + regnum,
2912 if (status != REG_VALID)
2913 mark_value_bytes_unavailable (result_value, 0, 16);
2915 memcpy (buf, raw_buf, 16);
2916 /* Read upper 128bits. */
2917 status = regcache_raw_read (regcache,
2918 tdep->ymm0h_regnum + regnum,
2920 if (status != REG_VALID)
2921 mark_value_bytes_unavailable (result_value, 16, 32);
2923 memcpy (buf + 16, raw_buf, 16);
2925 else if (i386_word_regnum_p (gdbarch, regnum))
2927 int gpnum = regnum - tdep->ax_regnum;
2929 /* Extract (always little endian). */
2930 status = regcache_raw_read (regcache, gpnum, raw_buf);
2931 if (status != REG_VALID)
2932 mark_value_bytes_unavailable (result_value, 0,
2933 TYPE_LENGTH (value_type (result_value)));
2935 memcpy (buf, raw_buf, 2);
2937 else if (i386_byte_regnum_p (gdbarch, regnum))
2939 /* Check byte pseudo registers last since this function will
2940 be called from amd64_pseudo_register_read, which handles
2941 byte pseudo registers differently. */
2942 int gpnum = regnum - tdep->al_regnum;
2944 /* Extract (always little endian). We read both lower and
2946 status = regcache_raw_read (regcache, gpnum % 4, raw_buf);
2947 if (status != REG_VALID)
2948 mark_value_bytes_unavailable (result_value, 0,
2949 TYPE_LENGTH (value_type (result_value)));
2950 else if (gpnum >= 4)
2951 memcpy (buf, raw_buf + 1, 1);
2953 memcpy (buf, raw_buf, 1);
2956 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2960 static struct value *
2961 i386_pseudo_register_read_value (struct gdbarch *gdbarch,
2962 struct regcache *regcache,
2965 struct value *result;
2967 result = allocate_value (register_type (gdbarch, regnum));
2968 VALUE_LVAL (result) = lval_register;
2969 VALUE_REGNUM (result) = regnum;
2971 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result);
2977 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2978 int regnum, const gdb_byte *buf)
2980 gdb_byte raw_buf[MAX_REGISTER_SIZE];
2982 if (i386_mmx_regnum_p (gdbarch, regnum))
2984 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2987 regcache_raw_read (regcache, fpnum, raw_buf);
2988 /* ... Modify ... (always little endian). */
2989 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
2991 regcache_raw_write (regcache, fpnum, raw_buf);
2995 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2997 if (i386_ymm_regnum_p (gdbarch, regnum))
2999 regnum -= tdep->ymm0_regnum;
3001 /* ... Write lower 128bits. */
3002 regcache_raw_write (regcache,
3003 I387_XMM0_REGNUM (tdep) + regnum,
3005 /* ... Write upper 128bits. */
3006 regcache_raw_write (regcache,
3007 tdep->ymm0h_regnum + regnum,
3010 else if (i386_word_regnum_p (gdbarch, regnum))
3012 int gpnum = regnum - tdep->ax_regnum;
3015 regcache_raw_read (regcache, gpnum, raw_buf);
3016 /* ... Modify ... (always little endian). */
3017 memcpy (raw_buf, buf, 2);
3019 regcache_raw_write (regcache, gpnum, raw_buf);
3021 else if (i386_byte_regnum_p (gdbarch, regnum))
3023 /* Check byte pseudo registers last since this function will
3024 be called from amd64_pseudo_register_read, which handles
3025 byte pseudo registers differently. */
3026 int gpnum = regnum - tdep->al_regnum;
3028 /* Read ... We read both lower and upper registers. */
3029 regcache_raw_read (regcache, gpnum % 4, raw_buf);
3030 /* ... Modify ... (always little endian). */
3032 memcpy (raw_buf + 1, buf, 1);
3034 memcpy (raw_buf, buf, 1);
3036 regcache_raw_write (regcache, gpnum % 4, raw_buf);
3039 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3044 /* Return the register number of the register allocated by GCC after
3045 REGNUM, or -1 if there is no such register. */
3048 i386_next_regnum (int regnum)
3050 /* GCC allocates the registers in the order:
3052 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3054 Since storing a variable in %esp doesn't make any sense we return
3055 -1 for %ebp and for %esp itself. */
3056 static int next_regnum[] =
3058 I386_EDX_REGNUM, /* Slot for %eax. */
3059 I386_EBX_REGNUM, /* Slot for %ecx. */
3060 I386_ECX_REGNUM, /* Slot for %edx. */
3061 I386_ESI_REGNUM, /* Slot for %ebx. */
3062 -1, -1, /* Slots for %esp and %ebp. */
3063 I386_EDI_REGNUM, /* Slot for %esi. */
3064 I386_EBP_REGNUM /* Slot for %edi. */
3067 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
3068 return next_regnum[regnum];
3073 /* Return nonzero if a value of type TYPE stored in register REGNUM
3074 needs any special handling. */
3077 i386_convert_register_p (struct gdbarch *gdbarch,
3078 int regnum, struct type *type)
3080 int len = TYPE_LENGTH (type);
3082 /* Values may be spread across multiple registers. Most debugging
3083 formats aren't expressive enough to specify the locations, so
3084 some heuristics is involved. Right now we only handle types that
3085 have a length that is a multiple of the word size, since GCC
3086 doesn't seem to put any other types into registers. */
3087 if (len > 4 && len % 4 == 0)
3089 int last_regnum = regnum;
3093 last_regnum = i386_next_regnum (last_regnum);
3097 if (last_regnum != -1)
3101 return i387_convert_register_p (gdbarch, regnum, type);
3104 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3105 return its contents in TO. */
3108 i386_register_to_value (struct frame_info *frame, int regnum,
3109 struct type *type, gdb_byte *to,
3110 int *optimizedp, int *unavailablep)
3112 struct gdbarch *gdbarch = get_frame_arch (frame);
3113 int len = TYPE_LENGTH (type);
3115 if (i386_fp_regnum_p (gdbarch, regnum))
3116 return i387_register_to_value (frame, regnum, type, to,
3117 optimizedp, unavailablep);
3119 /* Read a value spread across multiple registers. */
3121 gdb_assert (len > 4 && len % 4 == 0);
3125 gdb_assert (regnum != -1);
3126 gdb_assert (register_size (gdbarch, regnum) == 4);
3128 if (!get_frame_register_bytes (frame, regnum, 0,
3129 register_size (gdbarch, regnum),
3130 to, optimizedp, unavailablep))
3133 regnum = i386_next_regnum (regnum);
3138 *optimizedp = *unavailablep = 0;
3142 /* Write the contents FROM of a value of type TYPE into register
3143 REGNUM in frame FRAME. */
3146 i386_value_to_register (struct frame_info *frame, int regnum,
3147 struct type *type, const gdb_byte *from)
3149 int len = TYPE_LENGTH (type);
3151 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
3153 i387_value_to_register (frame, regnum, type, from);
3157 /* Write a value spread across multiple registers. */
3159 gdb_assert (len > 4 && len % 4 == 0);
3163 gdb_assert (regnum != -1);
3164 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
3166 put_frame_register (frame, regnum, from);
3167 regnum = i386_next_regnum (regnum);
3173 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3174 in the general-purpose register set REGSET to register cache
3175 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3178 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
3179 int regnum, const void *gregs, size_t len)
3181 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3182 const gdb_byte *regs = gregs;
3185 gdb_assert (len == tdep->sizeof_gregset);
3187 for (i = 0; i < tdep->gregset_num_regs; i++)
3189 if ((regnum == i || regnum == -1)
3190 && tdep->gregset_reg_offset[i] != -1)
3191 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
3195 /* Collect register REGNUM from the register cache REGCACHE and store
3196 it in the buffer specified by GREGS and LEN as described by the
3197 general-purpose register set REGSET. If REGNUM is -1, do this for
3198 all registers in REGSET. */
3201 i386_collect_gregset (const struct regset *regset,
3202 const struct regcache *regcache,
3203 int regnum, void *gregs, size_t len)
3205 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3206 gdb_byte *regs = gregs;
3209 gdb_assert (len == tdep->sizeof_gregset);
3211 for (i = 0; i < tdep->gregset_num_regs; i++)
3213 if ((regnum == i || regnum == -1)
3214 && tdep->gregset_reg_offset[i] != -1)
3215 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
3219 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3220 in the floating-point register set REGSET to register cache
3221 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3224 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
3225 int regnum, const void *fpregs, size_t len)
3227 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3229 if (len == I387_SIZEOF_FXSAVE)
3231 i387_supply_fxsave (regcache, regnum, fpregs);
3235 gdb_assert (len == tdep->sizeof_fpregset);
3236 i387_supply_fsave (regcache, regnum, fpregs);
3239 /* Collect register REGNUM from the register cache REGCACHE and store
3240 it in the buffer specified by FPREGS and LEN as described by the
3241 floating-point register set REGSET. If REGNUM is -1, do this for
3242 all registers in REGSET. */
3245 i386_collect_fpregset (const struct regset *regset,
3246 const struct regcache *regcache,
3247 int regnum, void *fpregs, size_t len)
3249 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3251 if (len == I387_SIZEOF_FXSAVE)
3253 i387_collect_fxsave (regcache, regnum, fpregs);
3257 gdb_assert (len == tdep->sizeof_fpregset);
3258 i387_collect_fsave (regcache, regnum, fpregs);
3261 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
3264 i386_supply_xstateregset (const struct regset *regset,
3265 struct regcache *regcache, int regnum,
3266 const void *xstateregs, size_t len)
3268 i387_supply_xsave (regcache, regnum, xstateregs);
3271 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
3274 i386_collect_xstateregset (const struct regset *regset,
3275 const struct regcache *regcache,
3276 int regnum, void *xstateregs, size_t len)
3278 i387_collect_xsave (regcache, regnum, xstateregs, 1);
3281 /* Return the appropriate register set for the core section identified
3282 by SECT_NAME and SECT_SIZE. */
3284 const struct regset *
3285 i386_regset_from_core_section (struct gdbarch *gdbarch,
3286 const char *sect_name, size_t sect_size)
3288 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3290 if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset)
3292 if (tdep->gregset == NULL)
3293 tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset,
3294 i386_collect_gregset);
3295 return tdep->gregset;
3298 if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
3299 || (strcmp (sect_name, ".reg-xfp") == 0
3300 && sect_size == I387_SIZEOF_FXSAVE))
3302 if (tdep->fpregset == NULL)
3303 tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset,
3304 i386_collect_fpregset);
3305 return tdep->fpregset;
3308 if (strcmp (sect_name, ".reg-xstate") == 0)
3310 if (tdep->xstateregset == NULL)
3311 tdep->xstateregset = regset_alloc (gdbarch,
3312 i386_supply_xstateregset,
3313 i386_collect_xstateregset);
3315 return tdep->xstateregset;
3322 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3325 i386_pe_skip_trampoline_code (struct frame_info *frame,
3326 CORE_ADDR pc, char *name)
3328 struct gdbarch *gdbarch = get_frame_arch (frame);
3329 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3332 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
3334 unsigned long indirect =
3335 read_memory_unsigned_integer (pc + 2, 4, byte_order);
3336 struct minimal_symbol *indsym =
3337 indirect ? lookup_minimal_symbol_by_pc (indirect) : 0;
3338 const char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0;
3342 if (strncmp (symname, "__imp_", 6) == 0
3343 || strncmp (symname, "_imp_", 5) == 0)
3345 read_memory_unsigned_integer (indirect, 4, byte_order);
3348 return 0; /* Not a trampoline. */
3352 /* Return whether the THIS_FRAME corresponds to a sigtramp
3356 i386_sigtramp_p (struct frame_info *this_frame)
3358 CORE_ADDR pc = get_frame_pc (this_frame);
3361 find_pc_partial_function (pc, &name, NULL, NULL);
3362 return (name && strcmp ("_sigtramp", name) == 0);
3366 /* We have two flavours of disassembly. The machinery on this page
3367 deals with switching between those. */
3370 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
3372 gdb_assert (disassembly_flavor == att_flavor
3373 || disassembly_flavor == intel_flavor);
3375 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3376 constified, cast to prevent a compiler warning. */
3377 info->disassembler_options = (char *) disassembly_flavor;
3379 return print_insn_i386 (pc, info);
3383 /* There are a few i386 architecture variants that differ only
3384 slightly from the generic i386 target. For now, we don't give them
3385 their own source file, but include them here. As a consequence,
3386 they'll always be included. */
3388 /* System V Release 4 (SVR4). */
3390 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3394 i386_svr4_sigtramp_p (struct frame_info *this_frame)
3396 CORE_ADDR pc = get_frame_pc (this_frame);
3399 /* UnixWare uses _sigacthandler. The origin of the other symbols is
3400 currently unknown. */
3401 find_pc_partial_function (pc, &name, NULL, NULL);
3402 return (name && (strcmp ("_sigreturn", name) == 0
3403 || strcmp ("_sigacthandler", name) == 0
3404 || strcmp ("sigvechandler", name) == 0));
3407 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3408 address of the associated sigcontext (ucontext) structure. */
3411 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
3413 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3414 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3418 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
3419 sp = extract_unsigned_integer (buf, 4, byte_order);
3421 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
3426 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
3430 i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s)
3432 return (*s == '$' /* Literal number. */
3433 || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */
3434 || (*s == '(' && s[1] == '%') /* Register indirection. */
3435 || (*s == '%' && isalpha (s[1]))); /* Register access. */
3438 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
3442 i386_stap_parse_special_token (struct gdbarch *gdbarch,
3443 struct stap_parse_info *p)
3445 /* In order to parse special tokens, we use a state-machine that go
3446 through every known token and try to get a match. */
3450 THREE_ARG_DISPLACEMENT,
3454 current_state = TRIPLET;
3456 /* The special tokens to be parsed here are:
3458 - `register base + (register index * size) + offset', as represented
3459 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
3461 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
3462 `*(-8 + 3 - 1 + (void *) $eax)'. */
3464 while (current_state != DONE)
3466 const char *s = p->arg;
3468 switch (current_state)
3472 if (isdigit (*s) || *s == '-' || *s == '+')
3476 long displacements[3];
3491 displacements[0] = strtol (s, (char **) &s, 10);
3493 if (*s != '+' && *s != '-')
3495 /* We are not dealing with a triplet. */
3508 displacements[1] = strtol (s, (char **) &s, 10);
3510 if (*s != '+' && *s != '-')
3512 /* We are not dealing with a triplet. */
3525 displacements[2] = strtol (s, (char **) &s, 10);
3527 if (*s != '(' || s[1] != '%')
3533 while (isalnum (*s))
3540 regname = alloca (len + 1);
3542 strncpy (regname, start, len);
3543 regname[len] = '\0';
3545 if (user_reg_map_name_to_regnum (gdbarch,
3546 regname, len) == -1)
3547 error (_("Invalid register name `%s' "
3548 "on expression `%s'."),
3549 regname, p->saved_arg);
3551 for (i = 0; i < 3; i++)
3553 write_exp_elt_opcode (OP_LONG);
3555 (builtin_type (gdbarch)->builtin_long);
3556 write_exp_elt_longcst (displacements[i]);
3557 write_exp_elt_opcode (OP_LONG);
3559 write_exp_elt_opcode (UNOP_NEG);
3562 write_exp_elt_opcode (OP_REGISTER);
3565 write_exp_string (str);
3566 write_exp_elt_opcode (OP_REGISTER);
3568 write_exp_elt_opcode (UNOP_CAST);
3569 write_exp_elt_type (builtin_type (gdbarch)->builtin_data_ptr);
3570 write_exp_elt_opcode (UNOP_CAST);
3572 write_exp_elt_opcode (BINOP_ADD);
3573 write_exp_elt_opcode (BINOP_ADD);
3574 write_exp_elt_opcode (BINOP_ADD);
3576 write_exp_elt_opcode (UNOP_CAST);
3577 write_exp_elt_type (lookup_pointer_type (p->arg_type));
3578 write_exp_elt_opcode (UNOP_CAST);
3580 write_exp_elt_opcode (UNOP_IND);
3588 case THREE_ARG_DISPLACEMENT:
3590 if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+')
3592 int offset_minus = 0;
3601 struct stoken base_token, index_token;
3611 if (offset_minus && !isdigit (*s))
3615 offset = strtol (s, (char **) &s, 10);
3617 if (*s != '(' || s[1] != '%')
3623 while (isalnum (*s))
3626 if (*s != ',' || s[1] != '%')
3629 len_base = s - start;
3630 base = alloca (len_base + 1);
3631 strncpy (base, start, len_base);
3632 base[len_base] = '\0';
3634 if (user_reg_map_name_to_regnum (gdbarch,
3635 base, len_base) == -1)
3636 error (_("Invalid register name `%s' "
3637 "on expression `%s'."),
3638 base, p->saved_arg);
3643 while (isalnum (*s))
3646 len_index = s - start;
3647 index = alloca (len_index + 1);
3648 strncpy (index, start, len_index);
3649 index[len_index] = '\0';
3651 if (user_reg_map_name_to_regnum (gdbarch,
3652 index, len_index) == -1)
3653 error (_("Invalid register name `%s' "
3654 "on expression `%s'."),
3655 index, p->saved_arg);
3657 if (*s != ',' && *s != ')')
3671 size = strtol (s, (char **) &s, 10);
3681 write_exp_elt_opcode (OP_LONG);
3683 (builtin_type (gdbarch)->builtin_long);
3684 write_exp_elt_longcst (offset);
3685 write_exp_elt_opcode (OP_LONG);
3687 write_exp_elt_opcode (UNOP_NEG);
3690 write_exp_elt_opcode (OP_REGISTER);
3691 base_token.ptr = base;
3692 base_token.length = len_base;
3693 write_exp_string (base_token);
3694 write_exp_elt_opcode (OP_REGISTER);
3697 write_exp_elt_opcode (BINOP_ADD);
3699 write_exp_elt_opcode (OP_REGISTER);
3700 index_token.ptr = index;
3701 index_token.length = len_index;
3702 write_exp_string (index_token);
3703 write_exp_elt_opcode (OP_REGISTER);
3707 write_exp_elt_opcode (OP_LONG);
3709 (builtin_type (gdbarch)->builtin_long);
3710 write_exp_elt_longcst (size);
3711 write_exp_elt_opcode (OP_LONG);
3713 write_exp_elt_opcode (UNOP_NEG);
3714 write_exp_elt_opcode (BINOP_MUL);
3717 write_exp_elt_opcode (BINOP_ADD);
3719 write_exp_elt_opcode (UNOP_CAST);
3720 write_exp_elt_type (lookup_pointer_type (p->arg_type));
3721 write_exp_elt_opcode (UNOP_CAST);
3723 write_exp_elt_opcode (UNOP_IND);
3733 /* Advancing to the next state. */
3745 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3747 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3748 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3750 /* Registering SystemTap handlers. */
3751 set_gdbarch_stap_integer_prefix (gdbarch, "$");
3752 set_gdbarch_stap_register_prefix (gdbarch, "%");
3753 set_gdbarch_stap_register_indirection_prefix (gdbarch, "(");
3754 set_gdbarch_stap_register_indirection_suffix (gdbarch, ")");
3755 set_gdbarch_stap_is_single_operand (gdbarch,
3756 i386_stap_is_single_operand);
3757 set_gdbarch_stap_parse_special_token (gdbarch,
3758 i386_stap_parse_special_token);
3761 /* System V Release 4 (SVR4). */
3764 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3766 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3768 /* System V Release 4 uses ELF. */
3769 i386_elf_init_abi (info, gdbarch);
3771 /* System V Release 4 has shared libraries. */
3772 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
3774 tdep->sigtramp_p = i386_svr4_sigtramp_p;
3775 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
3776 tdep->sc_pc_offset = 36 + 14 * 4;
3777 tdep->sc_sp_offset = 36 + 17 * 4;
3779 tdep->jb_pc_offset = 20;
3785 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3787 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3789 /* DJGPP doesn't have any special frames for signal handlers. */
3790 tdep->sigtramp_p = NULL;
3792 tdep->jb_pc_offset = 36;
3794 /* DJGPP does not support the SSE registers. */
3795 if (! tdesc_has_registers (info.target_desc))
3796 tdep->tdesc = tdesc_i386_mmx;
3798 /* Native compiler is GCC, which uses the SVR4 register numbering
3799 even in COFF and STABS. See the comment in i386_gdbarch_init,
3800 before the calls to set_gdbarch_stab_reg_to_regnum and
3801 set_gdbarch_sdb_reg_to_regnum. */
3802 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3803 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3805 set_gdbarch_has_dos_based_file_system (gdbarch, 1);
3809 /* i386 register groups. In addition to the normal groups, add "mmx"
3812 static struct reggroup *i386_sse_reggroup;
3813 static struct reggroup *i386_mmx_reggroup;
3816 i386_init_reggroups (void)
3818 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
3819 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
3823 i386_add_reggroups (struct gdbarch *gdbarch)
3825 reggroup_add (gdbarch, i386_sse_reggroup);
3826 reggroup_add (gdbarch, i386_mmx_reggroup);
3827 reggroup_add (gdbarch, general_reggroup);
3828 reggroup_add (gdbarch, float_reggroup);
3829 reggroup_add (gdbarch, all_reggroup);
3830 reggroup_add (gdbarch, save_reggroup);
3831 reggroup_add (gdbarch, restore_reggroup);
3832 reggroup_add (gdbarch, vector_reggroup);
3833 reggroup_add (gdbarch, system_reggroup);
3837 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
3838 struct reggroup *group)
3840 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3841 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
3842 ymm_regnum_p, ymmh_regnum_p;
3844 /* Don't include pseudo registers, except for MMX, in any register
3846 if (i386_byte_regnum_p (gdbarch, regnum))
3849 if (i386_word_regnum_p (gdbarch, regnum))
3852 if (i386_dword_regnum_p (gdbarch, regnum))
3855 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
3856 if (group == i386_mmx_reggroup)
3857 return mmx_regnum_p;
3859 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
3860 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
3861 if (group == i386_sse_reggroup)
3862 return xmm_regnum_p || mxcsr_regnum_p;
3864 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
3865 if (group == vector_reggroup)
3866 return (mmx_regnum_p
3870 && ((tdep->xcr0 & I386_XSTATE_AVX_MASK)
3871 == I386_XSTATE_SSE_MASK)));
3873 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
3874 || i386_fpc_regnum_p (gdbarch, regnum));
3875 if (group == float_reggroup)
3878 /* For "info reg all", don't include upper YMM registers nor XMM
3879 registers when AVX is supported. */
3880 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
3881 if (group == all_reggroup
3883 && (tdep->xcr0 & I386_XSTATE_AVX))
3887 if (group == general_reggroup)
3888 return (!fp_regnum_p
3895 return default_register_reggroup_p (gdbarch, regnum, group);
3899 /* Get the ARGIth function argument for the current function. */
3902 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
3905 struct gdbarch *gdbarch = get_frame_arch (frame);
3906 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3907 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
3908 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
3912 i386_skip_permanent_breakpoint (struct regcache *regcache)
3914 CORE_ADDR current_pc = regcache_read_pc (regcache);
3916 /* On i386, breakpoint is exactly 1 byte long, so we just
3917 adjust the PC in the regcache. */
3919 regcache_write_pc (regcache, current_pc);
3923 #define PREFIX_REPZ 0x01
3924 #define PREFIX_REPNZ 0x02
3925 #define PREFIX_LOCK 0x04
3926 #define PREFIX_DATA 0x08
3927 #define PREFIX_ADDR 0x10
3939 /* i386 arith/logic operations */
3952 struct i386_record_s
3954 struct gdbarch *gdbarch;
3955 struct regcache *regcache;
3956 CORE_ADDR orig_addr;
3962 uint8_t mod, reg, rm;
3971 /* Parse the "modrm" part of the memory address irp->addr points at.
3972 Returns -1 if something goes wrong, 0 otherwise. */
3975 i386_record_modrm (struct i386_record_s *irp)
3977 struct gdbarch *gdbarch = irp->gdbarch;
3979 if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1))
3983 irp->mod = (irp->modrm >> 6) & 3;
3984 irp->reg = (irp->modrm >> 3) & 7;
3985 irp->rm = irp->modrm & 7;
3990 /* Extract the memory address that the current instruction writes to,
3991 and return it in *ADDR. Return -1 if something goes wrong. */
3994 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
3996 struct gdbarch *gdbarch = irp->gdbarch;
3997 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4009 uint8_t base = irp->rm;
4014 if (record_read_memory (gdbarch, irp->addr, &byte, 1))
4017 scale = (byte >> 6) & 3;
4018 index = ((byte >> 3) & 7) | irp->rex_x;
4026 if ((base & 7) == 5)
4029 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4032 *addr = extract_signed_integer (buf, 4, byte_order);
4033 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
4034 *addr += irp->addr + irp->rip_offset;
4038 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4041 *addr = (int8_t) buf[0];
4044 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4046 *addr = extract_signed_integer (buf, 4, byte_order);
4054 if (base == 4 && irp->popl_esp_hack)
4055 *addr += irp->popl_esp_hack;
4056 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
4059 if (irp->aflag == 2)
4064 *addr = (uint32_t) (offset64 + *addr);
4066 if (havesib && (index != 4 || scale != 0))
4068 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
4070 if (irp->aflag == 2)
4071 *addr += offset64 << scale;
4073 *addr = (uint32_t) (*addr + (offset64 << scale));
4084 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4087 *addr = extract_signed_integer (buf, 2, byte_order);
4093 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4096 *addr = (int8_t) buf[0];
4099 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4102 *addr = extract_signed_integer (buf, 2, byte_order);
4109 regcache_raw_read_unsigned (irp->regcache,
4110 irp->regmap[X86_RECORD_REBX_REGNUM],
4112 *addr = (uint32_t) (*addr + offset64);
4113 regcache_raw_read_unsigned (irp->regcache,
4114 irp->regmap[X86_RECORD_RESI_REGNUM],
4116 *addr = (uint32_t) (*addr + offset64);
4119 regcache_raw_read_unsigned (irp->regcache,
4120 irp->regmap[X86_RECORD_REBX_REGNUM],
4122 *addr = (uint32_t) (*addr + offset64);
4123 regcache_raw_read_unsigned (irp->regcache,
4124 irp->regmap[X86_RECORD_REDI_REGNUM],
4126 *addr = (uint32_t) (*addr + offset64);
4129 regcache_raw_read_unsigned (irp->regcache,
4130 irp->regmap[X86_RECORD_REBP_REGNUM],
4132 *addr = (uint32_t) (*addr + offset64);
4133 regcache_raw_read_unsigned (irp->regcache,
4134 irp->regmap[X86_RECORD_RESI_REGNUM],
4136 *addr = (uint32_t) (*addr + offset64);
4139 regcache_raw_read_unsigned (irp->regcache,
4140 irp->regmap[X86_RECORD_REBP_REGNUM],
4142 *addr = (uint32_t) (*addr + offset64);
4143 regcache_raw_read_unsigned (irp->regcache,
4144 irp->regmap[X86_RECORD_REDI_REGNUM],
4146 *addr = (uint32_t) (*addr + offset64);
4149 regcache_raw_read_unsigned (irp->regcache,
4150 irp->regmap[X86_RECORD_RESI_REGNUM],
4152 *addr = (uint32_t) (*addr + offset64);
4155 regcache_raw_read_unsigned (irp->regcache,
4156 irp->regmap[X86_RECORD_REDI_REGNUM],
4158 *addr = (uint32_t) (*addr + offset64);
4161 regcache_raw_read_unsigned (irp->regcache,
4162 irp->regmap[X86_RECORD_REBP_REGNUM],
4164 *addr = (uint32_t) (*addr + offset64);
4167 regcache_raw_read_unsigned (irp->regcache,
4168 irp->regmap[X86_RECORD_REBX_REGNUM],
4170 *addr = (uint32_t) (*addr + offset64);
4180 /* Record the address and contents of the memory that will be changed
4181 by the current instruction. Return -1 if something goes wrong, 0
4185 i386_record_lea_modrm (struct i386_record_s *irp)
4187 struct gdbarch *gdbarch = irp->gdbarch;
4190 if (irp->override >= 0)
4192 if (record_memory_query)
4196 target_terminal_ours ();
4198 Process record ignores the memory change of instruction at address %s\n\
4199 because it can't get the value of the segment register.\n\
4200 Do you want to stop the program?"),
4201 paddress (gdbarch, irp->orig_addr));
4202 target_terminal_inferior ();
4210 if (i386_record_lea_modrm_addr (irp, &addr))
4213 if (record_arch_list_add_mem (addr, 1 << irp->ot))
4219 /* Record the effects of a push operation. Return -1 if something
4220 goes wrong, 0 otherwise. */
4223 i386_record_push (struct i386_record_s *irp, int size)
4227 if (record_arch_list_add_reg (irp->regcache,
4228 irp->regmap[X86_RECORD_RESP_REGNUM]))
4230 regcache_raw_read_unsigned (irp->regcache,
4231 irp->regmap[X86_RECORD_RESP_REGNUM],
4233 if (record_arch_list_add_mem ((CORE_ADDR) addr - size, size))
4240 /* Defines contents to record. */
4241 #define I386_SAVE_FPU_REGS 0xfffd
4242 #define I386_SAVE_FPU_ENV 0xfffe
4243 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4245 /* Record the values of the floating point registers which will be
4246 changed by the current instruction. Returns -1 if something is
4247 wrong, 0 otherwise. */
4249 static int i386_record_floats (struct gdbarch *gdbarch,
4250 struct i386_record_s *ir,
4253 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4256 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4257 happen. Currently we store st0-st7 registers, but we need not store all
4258 registers all the time, in future we use ftag register and record only
4259 those who are not marked as an empty. */
4261 if (I386_SAVE_FPU_REGS == iregnum)
4263 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
4265 if (record_arch_list_add_reg (ir->regcache, i))
4269 else if (I386_SAVE_FPU_ENV == iregnum)
4271 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4273 if (record_arch_list_add_reg (ir->regcache, i))
4277 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
4279 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4281 if (record_arch_list_add_reg (ir->regcache, i))
4285 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
4286 (iregnum <= I387_FOP_REGNUM (tdep)))
4288 if (record_arch_list_add_reg (ir->regcache,iregnum))
4293 /* Parameter error. */
4296 if(I386_SAVE_FPU_ENV != iregnum)
4298 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4300 if (record_arch_list_add_reg (ir->regcache, i))
4307 /* Parse the current instruction, and record the values of the
4308 registers and memory that will be changed by the current
4309 instruction. Returns -1 if something goes wrong, 0 otherwise. */
4311 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
4312 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
4315 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
4316 CORE_ADDR input_addr)
4318 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4324 gdb_byte buf[MAX_REGISTER_SIZE];
4325 struct i386_record_s ir;
4326 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4331 memset (&ir, 0, sizeof (struct i386_record_s));
4332 ir.regcache = regcache;
4333 ir.addr = input_addr;
4334 ir.orig_addr = input_addr;
4338 ir.popl_esp_hack = 0;
4339 ir.regmap = tdep->record_regmap;
4340 ir.gdbarch = gdbarch;
4342 if (record_debug > 1)
4343 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
4345 paddress (gdbarch, ir.addr));
4350 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
4353 switch (opcode8) /* Instruction prefixes */
4355 case REPE_PREFIX_OPCODE:
4356 prefixes |= PREFIX_REPZ;
4358 case REPNE_PREFIX_OPCODE:
4359 prefixes |= PREFIX_REPNZ;
4361 case LOCK_PREFIX_OPCODE:
4362 prefixes |= PREFIX_LOCK;
4364 case CS_PREFIX_OPCODE:
4365 ir.override = X86_RECORD_CS_REGNUM;
4367 case SS_PREFIX_OPCODE:
4368 ir.override = X86_RECORD_SS_REGNUM;
4370 case DS_PREFIX_OPCODE:
4371 ir.override = X86_RECORD_DS_REGNUM;
4373 case ES_PREFIX_OPCODE:
4374 ir.override = X86_RECORD_ES_REGNUM;
4376 case FS_PREFIX_OPCODE:
4377 ir.override = X86_RECORD_FS_REGNUM;
4379 case GS_PREFIX_OPCODE:
4380 ir.override = X86_RECORD_GS_REGNUM;
4382 case DATA_PREFIX_OPCODE:
4383 prefixes |= PREFIX_DATA;
4385 case ADDR_PREFIX_OPCODE:
4386 prefixes |= PREFIX_ADDR;
4388 case 0x40: /* i386 inc %eax */
4389 case 0x41: /* i386 inc %ecx */
4390 case 0x42: /* i386 inc %edx */
4391 case 0x43: /* i386 inc %ebx */
4392 case 0x44: /* i386 inc %esp */
4393 case 0x45: /* i386 inc %ebp */
4394 case 0x46: /* i386 inc %esi */
4395 case 0x47: /* i386 inc %edi */
4396 case 0x48: /* i386 dec %eax */
4397 case 0x49: /* i386 dec %ecx */
4398 case 0x4a: /* i386 dec %edx */
4399 case 0x4b: /* i386 dec %ebx */
4400 case 0x4c: /* i386 dec %esp */
4401 case 0x4d: /* i386 dec %ebp */
4402 case 0x4e: /* i386 dec %esi */
4403 case 0x4f: /* i386 dec %edi */
4404 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
4408 rex_w = (opcode8 >> 3) & 1;
4409 rex_r = (opcode8 & 0x4) << 1;
4410 ir.rex_x = (opcode8 & 0x2) << 2;
4411 ir.rex_b = (opcode8 & 0x1) << 3;
4413 else /* 32 bit target */
4422 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
4428 if (prefixes & PREFIX_DATA)
4431 if (prefixes & PREFIX_ADDR)
4433 else if (ir.regmap[X86_RECORD_R8_REGNUM])
4436 /* Now check op code. */
4437 opcode = (uint32_t) opcode8;
4442 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
4445 opcode = (uint32_t) opcode8 | 0x0f00;
4449 case 0x00: /* arith & logic */
4497 if (((opcode >> 3) & 7) != OP_CMPL)
4499 if ((opcode & 1) == 0)
4502 ir.ot = ir.dflag + OT_WORD;
4504 switch ((opcode >> 1) & 3)
4506 case 0: /* OP Ev, Gv */
4507 if (i386_record_modrm (&ir))
4511 if (i386_record_lea_modrm (&ir))
4517 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4519 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4522 case 1: /* OP Gv, Ev */
4523 if (i386_record_modrm (&ir))
4526 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4528 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4530 case 2: /* OP A, Iv */
4531 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4535 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4538 case 0x80: /* GRP1 */
4542 if (i386_record_modrm (&ir))
4545 if (ir.reg != OP_CMPL)
4547 if ((opcode & 1) == 0)
4550 ir.ot = ir.dflag + OT_WORD;
4557 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4558 if (i386_record_lea_modrm (&ir))
4562 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
4564 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4567 case 0x40: /* inc */
4576 case 0x48: /* dec */
4585 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7);
4586 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4589 case 0xf6: /* GRP3 */
4591 if ((opcode & 1) == 0)
4594 ir.ot = ir.dflag + OT_WORD;
4595 if (i386_record_modrm (&ir))
4598 if (ir.mod != 3 && ir.reg == 0)
4599 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4604 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4610 if (i386_record_lea_modrm (&ir))
4616 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4618 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4620 if (ir.reg == 3) /* neg */
4621 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4627 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4628 if (ir.ot != OT_BYTE)
4629 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
4630 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4634 opcode = opcode << 8 | ir.modrm;
4640 case 0xfe: /* GRP4 */
4641 case 0xff: /* GRP5 */
4642 if (i386_record_modrm (&ir))
4644 if (ir.reg >= 2 && opcode == 0xfe)
4647 opcode = opcode << 8 | ir.modrm;
4654 if ((opcode & 1) == 0)
4657 ir.ot = ir.dflag + OT_WORD;
4660 if (i386_record_lea_modrm (&ir))
4666 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4668 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4670 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4673 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4675 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4677 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4680 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
4681 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4683 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4687 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4690 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4692 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4697 opcode = opcode << 8 | ir.modrm;
4703 case 0x84: /* test */
4707 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4710 case 0x98: /* CWDE/CBW */
4711 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4714 case 0x99: /* CDQ/CWD */
4715 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4716 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
4719 case 0x0faf: /* imul */
4722 ir.ot = ir.dflag + OT_WORD;
4723 if (i386_record_modrm (&ir))
4726 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4727 else if (opcode == 0x6b)
4730 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4732 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4733 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4736 case 0x0fc0: /* xadd */
4738 if ((opcode & 1) == 0)
4741 ir.ot = ir.dflag + OT_WORD;
4742 if (i386_record_modrm (&ir))
4747 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4749 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4750 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4752 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4756 if (i386_record_lea_modrm (&ir))
4758 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4760 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4762 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4765 case 0x0fb0: /* cmpxchg */
4767 if ((opcode & 1) == 0)
4770 ir.ot = ir.dflag + OT_WORD;
4771 if (i386_record_modrm (&ir))
4776 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4777 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4779 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4783 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4784 if (i386_record_lea_modrm (&ir))
4787 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4790 case 0x0fc7: /* cmpxchg8b */
4791 if (i386_record_modrm (&ir))
4796 opcode = opcode << 8 | ir.modrm;
4799 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4800 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
4801 if (i386_record_lea_modrm (&ir))
4803 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4806 case 0x50: /* push */
4816 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4818 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4822 case 0x06: /* push es */
4823 case 0x0e: /* push cs */
4824 case 0x16: /* push ss */
4825 case 0x1e: /* push ds */
4826 if (ir.regmap[X86_RECORD_R8_REGNUM])
4831 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4835 case 0x0fa0: /* push fs */
4836 case 0x0fa8: /* push gs */
4837 if (ir.regmap[X86_RECORD_R8_REGNUM])
4842 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4846 case 0x60: /* pusha */
4847 if (ir.regmap[X86_RECORD_R8_REGNUM])
4852 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
4856 case 0x58: /* pop */
4864 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4865 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
4868 case 0x61: /* popa */
4869 if (ir.regmap[X86_RECORD_R8_REGNUM])
4874 for (regnum = X86_RECORD_REAX_REGNUM;
4875 regnum <= X86_RECORD_REDI_REGNUM;
4877 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
4880 case 0x8f: /* pop */
4881 if (ir.regmap[X86_RECORD_R8_REGNUM])
4882 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
4884 ir.ot = ir.dflag + OT_WORD;
4885 if (i386_record_modrm (&ir))
4888 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
4891 ir.popl_esp_hack = 1 << ir.ot;
4892 if (i386_record_lea_modrm (&ir))
4895 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4898 case 0xc8: /* enter */
4899 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
4900 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4902 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4906 case 0xc9: /* leave */
4907 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4908 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
4911 case 0x07: /* pop es */
4912 if (ir.regmap[X86_RECORD_R8_REGNUM])
4917 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4918 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
4919 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4922 case 0x17: /* pop ss */
4923 if (ir.regmap[X86_RECORD_R8_REGNUM])
4928 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4929 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
4930 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4933 case 0x1f: /* pop ds */
4934 if (ir.regmap[X86_RECORD_R8_REGNUM])
4939 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4940 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
4941 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4944 case 0x0fa1: /* pop fs */
4945 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4946 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
4947 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4950 case 0x0fa9: /* pop gs */
4951 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4952 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
4953 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4956 case 0x88: /* mov */
4960 if ((opcode & 1) == 0)
4963 ir.ot = ir.dflag + OT_WORD;
4965 if (i386_record_modrm (&ir))
4970 if (opcode == 0xc6 || opcode == 0xc7)
4971 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4972 if (i386_record_lea_modrm (&ir))
4977 if (opcode == 0xc6 || opcode == 0xc7)
4979 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4981 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4985 case 0x8a: /* mov */
4987 if ((opcode & 1) == 0)
4990 ir.ot = ir.dflag + OT_WORD;
4991 if (i386_record_modrm (&ir))
4994 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4996 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4999 case 0x8c: /* mov seg */
5000 if (i386_record_modrm (&ir))
5005 opcode = opcode << 8 | ir.modrm;
5010 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
5014 if (i386_record_lea_modrm (&ir))
5019 case 0x8e: /* mov seg */
5020 if (i386_record_modrm (&ir))
5025 regnum = X86_RECORD_ES_REGNUM;
5028 regnum = X86_RECORD_SS_REGNUM;
5031 regnum = X86_RECORD_DS_REGNUM;
5034 regnum = X86_RECORD_FS_REGNUM;
5037 regnum = X86_RECORD_GS_REGNUM;
5041 opcode = opcode << 8 | ir.modrm;
5045 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
5046 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5049 case 0x0fb6: /* movzbS */
5050 case 0x0fb7: /* movzwS */
5051 case 0x0fbe: /* movsbS */
5052 case 0x0fbf: /* movswS */
5053 if (i386_record_modrm (&ir))
5055 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5058 case 0x8d: /* lea */
5059 if (i386_record_modrm (&ir))
5064 opcode = opcode << 8 | ir.modrm;
5069 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5071 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
5074 case 0xa0: /* mov EAX */
5077 case 0xd7: /* xlat */
5078 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5081 case 0xa2: /* mov EAX */
5083 if (ir.override >= 0)
5085 if (record_memory_query)
5089 target_terminal_ours ();
5091 Process record ignores the memory change of instruction at address %s\n\
5092 because it can't get the value of the segment register.\n\
5093 Do you want to stop the program?"),
5094 paddress (gdbarch, ir.orig_addr));
5095 target_terminal_inferior ();
5102 if ((opcode & 1) == 0)
5105 ir.ot = ir.dflag + OT_WORD;
5108 if (record_read_memory (gdbarch, ir.addr, buf, 8))
5111 addr = extract_unsigned_integer (buf, 8, byte_order);
5115 if (record_read_memory (gdbarch, ir.addr, buf, 4))
5118 addr = extract_unsigned_integer (buf, 4, byte_order);
5122 if (record_read_memory (gdbarch, ir.addr, buf, 2))
5125 addr = extract_unsigned_integer (buf, 2, byte_order);
5127 if (record_arch_list_add_mem (addr, 1 << ir.ot))
5132 case 0xb0: /* mov R, Ib */
5140 I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
5141 ? ((opcode & 0x7) | ir.rex_b)
5142 : ((opcode & 0x7) & 0x3));
5145 case 0xb8: /* mov R, Iv */
5153 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5156 case 0x91: /* xchg R, EAX */
5163 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5164 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7);
5167 case 0x86: /* xchg Ev, Gv */
5169 if ((opcode & 1) == 0)
5172 ir.ot = ir.dflag + OT_WORD;
5173 if (i386_record_modrm (&ir))
5178 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5180 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
5184 if (i386_record_lea_modrm (&ir))
5188 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5190 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
5193 case 0xc4: /* les Gv */
5194 case 0xc5: /* lds Gv */
5195 if (ir.regmap[X86_RECORD_R8_REGNUM])
5201 case 0x0fb2: /* lss Gv */
5202 case 0x0fb4: /* lfs Gv */
5203 case 0x0fb5: /* lgs Gv */
5204 if (i386_record_modrm (&ir))
5212 opcode = opcode << 8 | ir.modrm;
5217 case 0xc4: /* les Gv */
5218 regnum = X86_RECORD_ES_REGNUM;
5220 case 0xc5: /* lds Gv */
5221 regnum = X86_RECORD_DS_REGNUM;
5223 case 0x0fb2: /* lss Gv */
5224 regnum = X86_RECORD_SS_REGNUM;
5226 case 0x0fb4: /* lfs Gv */
5227 regnum = X86_RECORD_FS_REGNUM;
5229 case 0x0fb5: /* lgs Gv */
5230 regnum = X86_RECORD_GS_REGNUM;
5233 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
5234 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5235 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5238 case 0xc0: /* shifts */
5244 if ((opcode & 1) == 0)
5247 ir.ot = ir.dflag + OT_WORD;
5248 if (i386_record_modrm (&ir))
5250 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
5252 if (i386_record_lea_modrm (&ir))
5258 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5260 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
5262 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5269 if (i386_record_modrm (&ir))
5273 if (record_arch_list_add_reg (ir.regcache, ir.rm))
5278 if (i386_record_lea_modrm (&ir))
5283 case 0xd8: /* Floats. */
5291 if (i386_record_modrm (&ir))
5293 ir.reg |= ((opcode & 7) << 3);
5299 if (i386_record_lea_modrm_addr (&ir, &addr64))
5307 /* For fcom, ficom nothing to do. */
5313 /* For fcomp, ficomp pop FPU stack, store all. */
5314 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5341 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5342 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5343 of code, always affects st(0) register. */
5344 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
5368 /* Handling fld, fild. */
5369 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5373 switch (ir.reg >> 4)
5376 if (record_arch_list_add_mem (addr64, 4))
5380 if (record_arch_list_add_mem (addr64, 8))
5386 if (record_arch_list_add_mem (addr64, 2))
5392 switch (ir.reg >> 4)
5395 if (record_arch_list_add_mem (addr64, 4))
5397 if (3 == (ir.reg & 7))
5399 /* For fstp m32fp. */
5400 if (i386_record_floats (gdbarch, &ir,
5401 I386_SAVE_FPU_REGS))
5406 if (record_arch_list_add_mem (addr64, 4))
5408 if ((3 == (ir.reg & 7))
5409 || (5 == (ir.reg & 7))
5410 || (7 == (ir.reg & 7)))
5412 /* For fstp insn. */
5413 if (i386_record_floats (gdbarch, &ir,
5414 I386_SAVE_FPU_REGS))
5419 if (record_arch_list_add_mem (addr64, 8))
5421 if (3 == (ir.reg & 7))
5423 /* For fstp m64fp. */
5424 if (i386_record_floats (gdbarch, &ir,
5425 I386_SAVE_FPU_REGS))
5430 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
5432 /* For fistp, fbld, fild, fbstp. */
5433 if (i386_record_floats (gdbarch, &ir,
5434 I386_SAVE_FPU_REGS))
5439 if (record_arch_list_add_mem (addr64, 2))
5448 if (i386_record_floats (gdbarch, &ir,
5449 I386_SAVE_FPU_ENV_REG_STACK))
5454 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
5459 if (i386_record_floats (gdbarch, &ir,
5460 I386_SAVE_FPU_ENV_REG_STACK))
5466 if (record_arch_list_add_mem (addr64, 28))
5471 if (record_arch_list_add_mem (addr64, 14))
5477 if (record_arch_list_add_mem (addr64, 2))
5479 /* Insn fstp, fbstp. */
5480 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5485 if (record_arch_list_add_mem (addr64, 10))
5491 if (record_arch_list_add_mem (addr64, 28))
5497 if (record_arch_list_add_mem (addr64, 14))
5501 if (record_arch_list_add_mem (addr64, 80))
5504 if (i386_record_floats (gdbarch, &ir,
5505 I386_SAVE_FPU_ENV_REG_STACK))
5509 if (record_arch_list_add_mem (addr64, 8))
5512 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5517 opcode = opcode << 8 | ir.modrm;
5522 /* Opcode is an extension of modR/M byte. */
5528 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
5532 if (0x0c == (ir.modrm >> 4))
5534 if ((ir.modrm & 0x0f) <= 7)
5536 if (i386_record_floats (gdbarch, &ir,
5537 I386_SAVE_FPU_REGS))
5542 if (i386_record_floats (gdbarch, &ir,
5543 I387_ST0_REGNUM (tdep)))
5545 /* If only st(0) is changing, then we have already
5547 if ((ir.modrm & 0x0f) - 0x08)
5549 if (i386_record_floats (gdbarch, &ir,
5550 I387_ST0_REGNUM (tdep) +
5551 ((ir.modrm & 0x0f) - 0x08)))
5569 if (i386_record_floats (gdbarch, &ir,
5570 I387_ST0_REGNUM (tdep)))
5588 if (i386_record_floats (gdbarch, &ir,
5589 I386_SAVE_FPU_REGS))
5593 if (i386_record_floats (gdbarch, &ir,
5594 I387_ST0_REGNUM (tdep)))
5596 if (i386_record_floats (gdbarch, &ir,
5597 I387_ST0_REGNUM (tdep) + 1))
5604 if (0xe9 == ir.modrm)
5606 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5609 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
5611 if (i386_record_floats (gdbarch, &ir,
5612 I387_ST0_REGNUM (tdep)))
5614 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
5616 if (i386_record_floats (gdbarch, &ir,
5617 I387_ST0_REGNUM (tdep) +
5621 else if ((ir.modrm & 0x0f) - 0x08)
5623 if (i386_record_floats (gdbarch, &ir,
5624 I387_ST0_REGNUM (tdep) +
5625 ((ir.modrm & 0x0f) - 0x08)))
5631 if (0xe3 == ir.modrm)
5633 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
5636 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
5638 if (i386_record_floats (gdbarch, &ir,
5639 I387_ST0_REGNUM (tdep)))
5641 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
5643 if (i386_record_floats (gdbarch, &ir,
5644 I387_ST0_REGNUM (tdep) +
5648 else if ((ir.modrm & 0x0f) - 0x08)
5650 if (i386_record_floats (gdbarch, &ir,
5651 I387_ST0_REGNUM (tdep) +
5652 ((ir.modrm & 0x0f) - 0x08)))
5658 if ((0x0c == ir.modrm >> 4)
5659 || (0x0d == ir.modrm >> 4)
5660 || (0x0f == ir.modrm >> 4))
5662 if ((ir.modrm & 0x0f) <= 7)
5664 if (i386_record_floats (gdbarch, &ir,
5665 I387_ST0_REGNUM (tdep) +
5671 if (i386_record_floats (gdbarch, &ir,
5672 I387_ST0_REGNUM (tdep) +
5673 ((ir.modrm & 0x0f) - 0x08)))
5679 if (0x0c == ir.modrm >> 4)
5681 if (i386_record_floats (gdbarch, &ir,
5682 I387_FTAG_REGNUM (tdep)))
5685 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
5687 if ((ir.modrm & 0x0f) <= 7)
5689 if (i386_record_floats (gdbarch, &ir,
5690 I387_ST0_REGNUM (tdep) +
5696 if (i386_record_floats (gdbarch, &ir,
5697 I386_SAVE_FPU_REGS))
5703 if ((0x0c == ir.modrm >> 4)
5704 || (0x0e == ir.modrm >> 4)
5705 || (0x0f == ir.modrm >> 4)
5706 || (0xd9 == ir.modrm))
5708 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5713 if (0xe0 == ir.modrm)
5715 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
5718 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
5720 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5728 case 0xa4: /* movsS */
5730 case 0xaa: /* stosS */
5732 case 0x6c: /* insS */
5734 regcache_raw_read_unsigned (ir.regcache,
5735 ir.regmap[X86_RECORD_RECX_REGNUM],
5741 if ((opcode & 1) == 0)
5744 ir.ot = ir.dflag + OT_WORD;
5745 regcache_raw_read_unsigned (ir.regcache,
5746 ir.regmap[X86_RECORD_REDI_REGNUM],
5749 regcache_raw_read_unsigned (ir.regcache,
5750 ir.regmap[X86_RECORD_ES_REGNUM],
5752 regcache_raw_read_unsigned (ir.regcache,
5753 ir.regmap[X86_RECORD_DS_REGNUM],
5755 if (ir.aflag && (es != ds))
5757 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5758 if (record_memory_query)
5762 target_terminal_ours ();
5764 Process record ignores the memory change of instruction at address %s\n\
5765 because it can't get the value of the segment register.\n\
5766 Do you want to stop the program?"),
5767 paddress (gdbarch, ir.orig_addr));
5768 target_terminal_inferior ();
5775 if (record_arch_list_add_mem (addr, 1 << ir.ot))
5779 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5780 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5781 if (opcode == 0xa4 || opcode == 0xa5)
5782 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5783 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5784 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5788 case 0xa6: /* cmpsS */
5790 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5791 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5792 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5793 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5794 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5797 case 0xac: /* lodsS */
5799 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5800 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5801 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5802 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5803 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5806 case 0xae: /* scasS */
5808 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5809 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5810 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5811 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5814 case 0x6e: /* outsS */
5816 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5817 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5818 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5819 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5822 case 0xe4: /* port I/O */
5826 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5827 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5837 case 0xc2: /* ret im */
5838 case 0xc3: /* ret */
5839 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5840 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5843 case 0xca: /* lret im */
5844 case 0xcb: /* lret */
5845 case 0xcf: /* iret */
5846 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5847 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5848 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5851 case 0xe8: /* call im */
5852 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5854 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5858 case 0x9a: /* lcall im */
5859 if (ir.regmap[X86_RECORD_R8_REGNUM])
5864 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5865 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5869 case 0xe9: /* jmp im */
5870 case 0xea: /* ljmp im */
5871 case 0xeb: /* jmp Jb */
5872 case 0x70: /* jcc Jb */
5888 case 0x0f80: /* jcc Jv */
5906 case 0x0f90: /* setcc Gv */
5922 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5924 if (i386_record_modrm (&ir))
5927 I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
5931 if (i386_record_lea_modrm (&ir))
5936 case 0x0f40: /* cmov Gv, Ev */
5952 if (i386_record_modrm (&ir))
5955 if (ir.dflag == OT_BYTE)
5957 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
5961 case 0x9c: /* pushf */
5962 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5963 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5965 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5969 case 0x9d: /* popf */
5970 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5971 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5974 case 0x9e: /* sahf */
5975 if (ir.regmap[X86_RECORD_R8_REGNUM])
5981 case 0xf5: /* cmc */
5982 case 0xf8: /* clc */
5983 case 0xf9: /* stc */
5984 case 0xfc: /* cld */
5985 case 0xfd: /* std */
5986 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5989 case 0x9f: /* lahf */
5990 if (ir.regmap[X86_RECORD_R8_REGNUM])
5995 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5996 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5999 /* bit operations */
6000 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6001 ir.ot = ir.dflag + OT_WORD;
6002 if (i386_record_modrm (&ir))
6007 opcode = opcode << 8 | ir.modrm;
6013 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6016 if (i386_record_lea_modrm (&ir))
6020 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6023 case 0x0fa3: /* bt Gv, Ev */
6024 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6027 case 0x0fab: /* bts */
6028 case 0x0fb3: /* btr */
6029 case 0x0fbb: /* btc */
6030 ir.ot = ir.dflag + OT_WORD;
6031 if (i386_record_modrm (&ir))
6034 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6038 if (i386_record_lea_modrm_addr (&ir, &addr64))
6040 regcache_raw_read_unsigned (ir.regcache,
6041 ir.regmap[ir.reg | rex_r],
6046 addr64 += ((int16_t) addr >> 4) << 4;
6049 addr64 += ((int32_t) addr >> 5) << 5;
6052 addr64 += ((int64_t) addr >> 6) << 6;
6055 if (record_arch_list_add_mem (addr64, 1 << ir.ot))
6057 if (i386_record_lea_modrm (&ir))
6060 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6063 case 0x0fbc: /* bsf */
6064 case 0x0fbd: /* bsr */
6065 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6066 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6070 case 0x27: /* daa */
6071 case 0x2f: /* das */
6072 case 0x37: /* aaa */
6073 case 0x3f: /* aas */
6074 case 0xd4: /* aam */
6075 case 0xd5: /* aad */
6076 if (ir.regmap[X86_RECORD_R8_REGNUM])
6081 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6082 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6086 case 0x90: /* nop */
6087 if (prefixes & PREFIX_LOCK)
6094 case 0x9b: /* fwait */
6095 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
6097 opcode = (uint32_t) opcode8;
6103 case 0xcc: /* int3 */
6104 printf_unfiltered (_("Process record does not support instruction "
6111 case 0xcd: /* int */
6115 if (record_read_memory (gdbarch, ir.addr, &interrupt, 1))
6118 if (interrupt != 0x80
6119 || tdep->i386_intx80_record == NULL)
6121 printf_unfiltered (_("Process record does not support "
6122 "instruction int 0x%02x.\n"),
6127 ret = tdep->i386_intx80_record (ir.regcache);
6134 case 0xce: /* into */
6135 printf_unfiltered (_("Process record does not support "
6136 "instruction into.\n"));
6141 case 0xfa: /* cli */
6142 case 0xfb: /* sti */
6145 case 0x62: /* bound */
6146 printf_unfiltered (_("Process record does not support "
6147 "instruction bound.\n"));
6152 case 0x0fc8: /* bswap reg */
6160 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
6163 case 0xd6: /* salc */
6164 if (ir.regmap[X86_RECORD_R8_REGNUM])
6169 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6170 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6173 case 0xe0: /* loopnz */
6174 case 0xe1: /* loopz */
6175 case 0xe2: /* loop */
6176 case 0xe3: /* jecxz */
6177 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6178 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6181 case 0x0f30: /* wrmsr */
6182 printf_unfiltered (_("Process record does not support "
6183 "instruction wrmsr.\n"));
6188 case 0x0f32: /* rdmsr */
6189 printf_unfiltered (_("Process record does not support "
6190 "instruction rdmsr.\n"));
6195 case 0x0f31: /* rdtsc */
6196 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6197 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6200 case 0x0f34: /* sysenter */
6203 if (ir.regmap[X86_RECORD_R8_REGNUM])
6208 if (tdep->i386_sysenter_record == NULL)
6210 printf_unfiltered (_("Process record does not support "
6211 "instruction sysenter.\n"));
6215 ret = tdep->i386_sysenter_record (ir.regcache);
6221 case 0x0f35: /* sysexit */
6222 printf_unfiltered (_("Process record does not support "
6223 "instruction sysexit.\n"));
6228 case 0x0f05: /* syscall */
6231 if (tdep->i386_syscall_record == NULL)
6233 printf_unfiltered (_("Process record does not support "
6234 "instruction syscall.\n"));
6238 ret = tdep->i386_syscall_record (ir.regcache);
6244 case 0x0f07: /* sysret */
6245 printf_unfiltered (_("Process record does not support "
6246 "instruction sysret.\n"));
6251 case 0x0fa2: /* cpuid */
6252 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6253 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6254 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6255 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
6258 case 0xf4: /* hlt */
6259 printf_unfiltered (_("Process record does not support "
6260 "instruction hlt.\n"));
6266 if (i386_record_modrm (&ir))
6273 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6277 if (i386_record_lea_modrm (&ir))
6286 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6290 opcode = opcode << 8 | ir.modrm;
6297 if (i386_record_modrm (&ir))
6308 opcode = opcode << 8 | ir.modrm;
6311 if (ir.override >= 0)
6313 if (record_memory_query)
6317 target_terminal_ours ();
6319 Process record ignores the memory change of instruction at address %s\n\
6320 because it can't get the value of the segment register.\n\
6321 Do you want to stop the program?"),
6322 paddress (gdbarch, ir.orig_addr));
6323 target_terminal_inferior ();
6330 if (i386_record_lea_modrm_addr (&ir, &addr64))
6332 if (record_arch_list_add_mem (addr64, 2))
6335 if (ir.regmap[X86_RECORD_R8_REGNUM])
6337 if (record_arch_list_add_mem (addr64, 8))
6342 if (record_arch_list_add_mem (addr64, 4))
6353 case 0: /* monitor */
6356 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6360 opcode = opcode << 8 | ir.modrm;
6368 if (ir.override >= 0)
6370 if (record_memory_query)
6374 target_terminal_ours ();
6376 Process record ignores the memory change of instruction at address %s\n\
6377 because it can't get the value of the segment register.\n\
6378 Do you want to stop the program?"),
6379 paddress (gdbarch, ir.orig_addr));
6380 target_terminal_inferior ();
6389 if (i386_record_lea_modrm_addr (&ir, &addr64))
6391 if (record_arch_list_add_mem (addr64, 2))
6394 if (ir.regmap[X86_RECORD_R8_REGNUM])
6396 if (record_arch_list_add_mem (addr64, 8))
6401 if (record_arch_list_add_mem (addr64, 4))
6413 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6414 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6418 else if (ir.rm == 1)
6425 opcode = opcode << 8 | ir.modrm;
6432 if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
6438 if (i386_record_lea_modrm (&ir))
6441 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6444 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6446 case 7: /* invlpg */
6449 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
6450 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
6454 opcode = opcode << 8 | ir.modrm;
6459 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6463 opcode = opcode << 8 | ir.modrm;
6469 case 0x0f08: /* invd */
6470 case 0x0f09: /* wbinvd */
6473 case 0x63: /* arpl */
6474 if (i386_record_modrm (&ir))
6476 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
6478 I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
6479 ? (ir.reg | rex_r) : ir.rm);
6483 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
6484 if (i386_record_lea_modrm (&ir))
6487 if (!ir.regmap[X86_RECORD_R8_REGNUM])
6488 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6491 case 0x0f02: /* lar */
6492 case 0x0f03: /* lsl */
6493 if (i386_record_modrm (&ir))
6495 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6496 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6500 if (i386_record_modrm (&ir))
6502 if (ir.mod == 3 && ir.reg == 3)
6505 opcode = opcode << 8 | ir.modrm;
6517 /* nop (multi byte) */
6520 case 0x0f20: /* mov reg, crN */
6521 case 0x0f22: /* mov crN, reg */
6522 if (i386_record_modrm (&ir))
6524 if ((ir.modrm & 0xc0) != 0xc0)
6527 opcode = opcode << 8 | ir.modrm;
6538 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6540 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6544 opcode = opcode << 8 | ir.modrm;
6550 case 0x0f21: /* mov reg, drN */
6551 case 0x0f23: /* mov drN, reg */
6552 if (i386_record_modrm (&ir))
6554 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
6555 || ir.reg == 5 || ir.reg >= 8)
6558 opcode = opcode << 8 | ir.modrm;
6562 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6564 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6567 case 0x0f06: /* clts */
6568 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6571 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
6573 case 0x0f0d: /* 3DNow! prefetch */
6576 case 0x0f0e: /* 3DNow! femms */
6577 case 0x0f77: /* emms */
6578 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
6580 record_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
6583 case 0x0f0f: /* 3DNow! data */
6584 if (i386_record_modrm (&ir))
6586 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
6591 case 0x0c: /* 3DNow! pi2fw */
6592 case 0x0d: /* 3DNow! pi2fd */
6593 case 0x1c: /* 3DNow! pf2iw */
6594 case 0x1d: /* 3DNow! pf2id */
6595 case 0x8a: /* 3DNow! pfnacc */
6596 case 0x8e: /* 3DNow! pfpnacc */
6597 case 0x90: /* 3DNow! pfcmpge */
6598 case 0x94: /* 3DNow! pfmin */
6599 case 0x96: /* 3DNow! pfrcp */
6600 case 0x97: /* 3DNow! pfrsqrt */
6601 case 0x9a: /* 3DNow! pfsub */
6602 case 0x9e: /* 3DNow! pfadd */
6603 case 0xa0: /* 3DNow! pfcmpgt */
6604 case 0xa4: /* 3DNow! pfmax */
6605 case 0xa6: /* 3DNow! pfrcpit1 */
6606 case 0xa7: /* 3DNow! pfrsqit1 */
6607 case 0xaa: /* 3DNow! pfsubr */
6608 case 0xae: /* 3DNow! pfacc */
6609 case 0xb0: /* 3DNow! pfcmpeq */
6610 case 0xb4: /* 3DNow! pfmul */
6611 case 0xb6: /* 3DNow! pfrcpit2 */
6612 case 0xb7: /* 3DNow! pmulhrw */
6613 case 0xbb: /* 3DNow! pswapd */
6614 case 0xbf: /* 3DNow! pavgusb */
6615 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
6616 goto no_support_3dnow_data;
6617 record_arch_list_add_reg (ir.regcache, ir.reg);
6621 no_support_3dnow_data:
6622 opcode = (opcode << 8) | opcode8;
6628 case 0x0faa: /* rsm */
6629 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6630 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6631 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6632 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6633 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
6634 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6635 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
6636 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6637 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6641 if (i386_record_modrm (&ir))
6645 case 0: /* fxsave */
6649 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6650 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
6652 if (record_arch_list_add_mem (tmpu64, 512))
6657 case 1: /* fxrstor */
6661 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6663 for (i = I387_MM0_REGNUM (tdep);
6664 i386_mmx_regnum_p (gdbarch, i); i++)
6665 record_arch_list_add_reg (ir.regcache, i);
6667 for (i = I387_XMM0_REGNUM (tdep);
6668 i386_xmm_regnum_p (gdbarch, i); i++)
6669 record_arch_list_add_reg (ir.regcache, i);
6671 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
6672 record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
6674 for (i = I387_ST0_REGNUM (tdep);
6675 i386_fp_regnum_p (gdbarch, i); i++)
6676 record_arch_list_add_reg (ir.regcache, i);
6678 for (i = I387_FCTRL_REGNUM (tdep);
6679 i386_fpc_regnum_p (gdbarch, i); i++)
6680 record_arch_list_add_reg (ir.regcache, i);
6684 case 2: /* ldmxcsr */
6685 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
6687 record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
6690 case 3: /* stmxcsr */
6692 if (i386_record_lea_modrm (&ir))
6696 case 5: /* lfence */
6697 case 6: /* mfence */
6698 case 7: /* sfence clflush */
6702 opcode = (opcode << 8) | ir.modrm;
6708 case 0x0fc3: /* movnti */
6709 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
6710 if (i386_record_modrm (&ir))
6715 if (i386_record_lea_modrm (&ir))
6719 /* Add prefix to opcode. */
6846 reswitch_prefix_add:
6854 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
6857 opcode = (uint32_t) opcode8 | opcode << 8;
6858 goto reswitch_prefix_add;
6861 case 0x0f10: /* movups */
6862 case 0x660f10: /* movupd */
6863 case 0xf30f10: /* movss */
6864 case 0xf20f10: /* movsd */
6865 case 0x0f12: /* movlps */
6866 case 0x660f12: /* movlpd */
6867 case 0xf30f12: /* movsldup */
6868 case 0xf20f12: /* movddup */
6869 case 0x0f14: /* unpcklps */
6870 case 0x660f14: /* unpcklpd */
6871 case 0x0f15: /* unpckhps */
6872 case 0x660f15: /* unpckhpd */
6873 case 0x0f16: /* movhps */
6874 case 0x660f16: /* movhpd */
6875 case 0xf30f16: /* movshdup */
6876 case 0x0f28: /* movaps */
6877 case 0x660f28: /* movapd */
6878 case 0x0f2a: /* cvtpi2ps */
6879 case 0x660f2a: /* cvtpi2pd */
6880 case 0xf30f2a: /* cvtsi2ss */
6881 case 0xf20f2a: /* cvtsi2sd */
6882 case 0x0f2c: /* cvttps2pi */
6883 case 0x660f2c: /* cvttpd2pi */
6884 case 0x0f2d: /* cvtps2pi */
6885 case 0x660f2d: /* cvtpd2pi */
6886 case 0x660f3800: /* pshufb */
6887 case 0x660f3801: /* phaddw */
6888 case 0x660f3802: /* phaddd */
6889 case 0x660f3803: /* phaddsw */
6890 case 0x660f3804: /* pmaddubsw */
6891 case 0x660f3805: /* phsubw */
6892 case 0x660f3806: /* phsubd */
6893 case 0x660f3807: /* phsubsw */
6894 case 0x660f3808: /* psignb */
6895 case 0x660f3809: /* psignw */
6896 case 0x660f380a: /* psignd */
6897 case 0x660f380b: /* pmulhrsw */
6898 case 0x660f3810: /* pblendvb */
6899 case 0x660f3814: /* blendvps */
6900 case 0x660f3815: /* blendvpd */
6901 case 0x660f381c: /* pabsb */
6902 case 0x660f381d: /* pabsw */
6903 case 0x660f381e: /* pabsd */
6904 case 0x660f3820: /* pmovsxbw */
6905 case 0x660f3821: /* pmovsxbd */
6906 case 0x660f3822: /* pmovsxbq */
6907 case 0x660f3823: /* pmovsxwd */
6908 case 0x660f3824: /* pmovsxwq */
6909 case 0x660f3825: /* pmovsxdq */
6910 case 0x660f3828: /* pmuldq */
6911 case 0x660f3829: /* pcmpeqq */
6912 case 0x660f382a: /* movntdqa */
6913 case 0x660f3a08: /* roundps */
6914 case 0x660f3a09: /* roundpd */
6915 case 0x660f3a0a: /* roundss */
6916 case 0x660f3a0b: /* roundsd */
6917 case 0x660f3a0c: /* blendps */
6918 case 0x660f3a0d: /* blendpd */
6919 case 0x660f3a0e: /* pblendw */
6920 case 0x660f3a0f: /* palignr */
6921 case 0x660f3a20: /* pinsrb */
6922 case 0x660f3a21: /* insertps */
6923 case 0x660f3a22: /* pinsrd pinsrq */
6924 case 0x660f3a40: /* dpps */
6925 case 0x660f3a41: /* dppd */
6926 case 0x660f3a42: /* mpsadbw */
6927 case 0x660f3a60: /* pcmpestrm */
6928 case 0x660f3a61: /* pcmpestri */
6929 case 0x660f3a62: /* pcmpistrm */
6930 case 0x660f3a63: /* pcmpistri */
6931 case 0x0f51: /* sqrtps */
6932 case 0x660f51: /* sqrtpd */
6933 case 0xf20f51: /* sqrtsd */
6934 case 0xf30f51: /* sqrtss */
6935 case 0x0f52: /* rsqrtps */
6936 case 0xf30f52: /* rsqrtss */
6937 case 0x0f53: /* rcpps */
6938 case 0xf30f53: /* rcpss */
6939 case 0x0f54: /* andps */
6940 case 0x660f54: /* andpd */
6941 case 0x0f55: /* andnps */
6942 case 0x660f55: /* andnpd */
6943 case 0x0f56: /* orps */
6944 case 0x660f56: /* orpd */
6945 case 0x0f57: /* xorps */
6946 case 0x660f57: /* xorpd */
6947 case 0x0f58: /* addps */
6948 case 0x660f58: /* addpd */
6949 case 0xf20f58: /* addsd */
6950 case 0xf30f58: /* addss */
6951 case 0x0f59: /* mulps */
6952 case 0x660f59: /* mulpd */
6953 case 0xf20f59: /* mulsd */
6954 case 0xf30f59: /* mulss */
6955 case 0x0f5a: /* cvtps2pd */
6956 case 0x660f5a: /* cvtpd2ps */
6957 case 0xf20f5a: /* cvtsd2ss */
6958 case 0xf30f5a: /* cvtss2sd */
6959 case 0x0f5b: /* cvtdq2ps */
6960 case 0x660f5b: /* cvtps2dq */
6961 case 0xf30f5b: /* cvttps2dq */
6962 case 0x0f5c: /* subps */
6963 case 0x660f5c: /* subpd */
6964 case 0xf20f5c: /* subsd */
6965 case 0xf30f5c: /* subss */
6966 case 0x0f5d: /* minps */
6967 case 0x660f5d: /* minpd */
6968 case 0xf20f5d: /* minsd */
6969 case 0xf30f5d: /* minss */
6970 case 0x0f5e: /* divps */
6971 case 0x660f5e: /* divpd */
6972 case 0xf20f5e: /* divsd */
6973 case 0xf30f5e: /* divss */
6974 case 0x0f5f: /* maxps */
6975 case 0x660f5f: /* maxpd */
6976 case 0xf20f5f: /* maxsd */
6977 case 0xf30f5f: /* maxss */
6978 case 0x660f60: /* punpcklbw */
6979 case 0x660f61: /* punpcklwd */
6980 case 0x660f62: /* punpckldq */
6981 case 0x660f63: /* packsswb */
6982 case 0x660f64: /* pcmpgtb */
6983 case 0x660f65: /* pcmpgtw */
6984 case 0x660f66: /* pcmpgtd */
6985 case 0x660f67: /* packuswb */
6986 case 0x660f68: /* punpckhbw */
6987 case 0x660f69: /* punpckhwd */
6988 case 0x660f6a: /* punpckhdq */
6989 case 0x660f6b: /* packssdw */
6990 case 0x660f6c: /* punpcklqdq */
6991 case 0x660f6d: /* punpckhqdq */
6992 case 0x660f6e: /* movd */
6993 case 0x660f6f: /* movdqa */
6994 case 0xf30f6f: /* movdqu */
6995 case 0x660f70: /* pshufd */
6996 case 0xf20f70: /* pshuflw */
6997 case 0xf30f70: /* pshufhw */
6998 case 0x660f74: /* pcmpeqb */
6999 case 0x660f75: /* pcmpeqw */
7000 case 0x660f76: /* pcmpeqd */
7001 case 0x660f7c: /* haddpd */
7002 case 0xf20f7c: /* haddps */
7003 case 0x660f7d: /* hsubpd */
7004 case 0xf20f7d: /* hsubps */
7005 case 0xf30f7e: /* movq */
7006 case 0x0fc2: /* cmpps */
7007 case 0x660fc2: /* cmppd */
7008 case 0xf20fc2: /* cmpsd */
7009 case 0xf30fc2: /* cmpss */
7010 case 0x660fc4: /* pinsrw */
7011 case 0x0fc6: /* shufps */
7012 case 0x660fc6: /* shufpd */
7013 case 0x660fd0: /* addsubpd */
7014 case 0xf20fd0: /* addsubps */
7015 case 0x660fd1: /* psrlw */
7016 case 0x660fd2: /* psrld */
7017 case 0x660fd3: /* psrlq */
7018 case 0x660fd4: /* paddq */
7019 case 0x660fd5: /* pmullw */
7020 case 0xf30fd6: /* movq2dq */
7021 case 0x660fd8: /* psubusb */
7022 case 0x660fd9: /* psubusw */
7023 case 0x660fda: /* pminub */
7024 case 0x660fdb: /* pand */
7025 case 0x660fdc: /* paddusb */
7026 case 0x660fdd: /* paddusw */
7027 case 0x660fde: /* pmaxub */
7028 case 0x660fdf: /* pandn */
7029 case 0x660fe0: /* pavgb */
7030 case 0x660fe1: /* psraw */
7031 case 0x660fe2: /* psrad */
7032 case 0x660fe3: /* pavgw */
7033 case 0x660fe4: /* pmulhuw */
7034 case 0x660fe5: /* pmulhw */
7035 case 0x660fe6: /* cvttpd2dq */
7036 case 0xf20fe6: /* cvtpd2dq */
7037 case 0xf30fe6: /* cvtdq2pd */
7038 case 0x660fe8: /* psubsb */
7039 case 0x660fe9: /* psubsw */
7040 case 0x660fea: /* pminsw */
7041 case 0x660feb: /* por */
7042 case 0x660fec: /* paddsb */
7043 case 0x660fed: /* paddsw */
7044 case 0x660fee: /* pmaxsw */
7045 case 0x660fef: /* pxor */
7046 case 0xf20ff0: /* lddqu */
7047 case 0x660ff1: /* psllw */
7048 case 0x660ff2: /* pslld */
7049 case 0x660ff3: /* psllq */
7050 case 0x660ff4: /* pmuludq */
7051 case 0x660ff5: /* pmaddwd */
7052 case 0x660ff6: /* psadbw */
7053 case 0x660ff8: /* psubb */
7054 case 0x660ff9: /* psubw */
7055 case 0x660ffa: /* psubd */
7056 case 0x660ffb: /* psubq */
7057 case 0x660ffc: /* paddb */
7058 case 0x660ffd: /* paddw */
7059 case 0x660ffe: /* paddd */
7060 if (i386_record_modrm (&ir))
7063 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
7065 record_arch_list_add_reg (ir.regcache,
7066 I387_XMM0_REGNUM (tdep) + ir.reg);
7067 if ((opcode & 0xfffffffc) == 0x660f3a60)
7068 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7071 case 0x0f11: /* movups */
7072 case 0x660f11: /* movupd */
7073 case 0xf30f11: /* movss */
7074 case 0xf20f11: /* movsd */
7075 case 0x0f13: /* movlps */
7076 case 0x660f13: /* movlpd */
7077 case 0x0f17: /* movhps */
7078 case 0x660f17: /* movhpd */
7079 case 0x0f29: /* movaps */
7080 case 0x660f29: /* movapd */
7081 case 0x660f3a14: /* pextrb */
7082 case 0x660f3a15: /* pextrw */
7083 case 0x660f3a16: /* pextrd pextrq */
7084 case 0x660f3a17: /* extractps */
7085 case 0x660f7f: /* movdqa */
7086 case 0xf30f7f: /* movdqu */
7087 if (i386_record_modrm (&ir))
7091 if (opcode == 0x0f13 || opcode == 0x660f13
7092 || opcode == 0x0f17 || opcode == 0x660f17)
7095 if (!i386_xmm_regnum_p (gdbarch,
7096 I387_XMM0_REGNUM (tdep) + ir.rm))
7098 record_arch_list_add_reg (ir.regcache,
7099 I387_XMM0_REGNUM (tdep) + ir.rm);
7121 if (i386_record_lea_modrm (&ir))
7126 case 0x0f2b: /* movntps */
7127 case 0x660f2b: /* movntpd */
7128 case 0x0fe7: /* movntq */
7129 case 0x660fe7: /* movntdq */
7132 if (opcode == 0x0fe7)
7136 if (i386_record_lea_modrm (&ir))
7140 case 0xf30f2c: /* cvttss2si */
7141 case 0xf20f2c: /* cvttsd2si */
7142 case 0xf30f2d: /* cvtss2si */
7143 case 0xf20f2d: /* cvtsd2si */
7144 case 0xf20f38f0: /* crc32 */
7145 case 0xf20f38f1: /* crc32 */
7146 case 0x0f50: /* movmskps */
7147 case 0x660f50: /* movmskpd */
7148 case 0x0fc5: /* pextrw */
7149 case 0x660fc5: /* pextrw */
7150 case 0x0fd7: /* pmovmskb */
7151 case 0x660fd7: /* pmovmskb */
7152 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7155 case 0x0f3800: /* pshufb */
7156 case 0x0f3801: /* phaddw */
7157 case 0x0f3802: /* phaddd */
7158 case 0x0f3803: /* phaddsw */
7159 case 0x0f3804: /* pmaddubsw */
7160 case 0x0f3805: /* phsubw */
7161 case 0x0f3806: /* phsubd */
7162 case 0x0f3807: /* phsubsw */
7163 case 0x0f3808: /* psignb */
7164 case 0x0f3809: /* psignw */
7165 case 0x0f380a: /* psignd */
7166 case 0x0f380b: /* pmulhrsw */
7167 case 0x0f381c: /* pabsb */
7168 case 0x0f381d: /* pabsw */
7169 case 0x0f381e: /* pabsd */
7170 case 0x0f382b: /* packusdw */
7171 case 0x0f3830: /* pmovzxbw */
7172 case 0x0f3831: /* pmovzxbd */
7173 case 0x0f3832: /* pmovzxbq */
7174 case 0x0f3833: /* pmovzxwd */
7175 case 0x0f3834: /* pmovzxwq */
7176 case 0x0f3835: /* pmovzxdq */
7177 case 0x0f3837: /* pcmpgtq */
7178 case 0x0f3838: /* pminsb */
7179 case 0x0f3839: /* pminsd */
7180 case 0x0f383a: /* pminuw */
7181 case 0x0f383b: /* pminud */
7182 case 0x0f383c: /* pmaxsb */
7183 case 0x0f383d: /* pmaxsd */
7184 case 0x0f383e: /* pmaxuw */
7185 case 0x0f383f: /* pmaxud */
7186 case 0x0f3840: /* pmulld */
7187 case 0x0f3841: /* phminposuw */
7188 case 0x0f3a0f: /* palignr */
7189 case 0x0f60: /* punpcklbw */
7190 case 0x0f61: /* punpcklwd */
7191 case 0x0f62: /* punpckldq */
7192 case 0x0f63: /* packsswb */
7193 case 0x0f64: /* pcmpgtb */
7194 case 0x0f65: /* pcmpgtw */
7195 case 0x0f66: /* pcmpgtd */
7196 case 0x0f67: /* packuswb */
7197 case 0x0f68: /* punpckhbw */
7198 case 0x0f69: /* punpckhwd */
7199 case 0x0f6a: /* punpckhdq */
7200 case 0x0f6b: /* packssdw */
7201 case 0x0f6e: /* movd */
7202 case 0x0f6f: /* movq */
7203 case 0x0f70: /* pshufw */
7204 case 0x0f74: /* pcmpeqb */
7205 case 0x0f75: /* pcmpeqw */
7206 case 0x0f76: /* pcmpeqd */
7207 case 0x0fc4: /* pinsrw */
7208 case 0x0fd1: /* psrlw */
7209 case 0x0fd2: /* psrld */
7210 case 0x0fd3: /* psrlq */
7211 case 0x0fd4: /* paddq */
7212 case 0x0fd5: /* pmullw */
7213 case 0xf20fd6: /* movdq2q */
7214 case 0x0fd8: /* psubusb */
7215 case 0x0fd9: /* psubusw */
7216 case 0x0fda: /* pminub */
7217 case 0x0fdb: /* pand */
7218 case 0x0fdc: /* paddusb */
7219 case 0x0fdd: /* paddusw */
7220 case 0x0fde: /* pmaxub */
7221 case 0x0fdf: /* pandn */
7222 case 0x0fe0: /* pavgb */
7223 case 0x0fe1: /* psraw */
7224 case 0x0fe2: /* psrad */
7225 case 0x0fe3: /* pavgw */
7226 case 0x0fe4: /* pmulhuw */
7227 case 0x0fe5: /* pmulhw */
7228 case 0x0fe8: /* psubsb */
7229 case 0x0fe9: /* psubsw */
7230 case 0x0fea: /* pminsw */
7231 case 0x0feb: /* por */
7232 case 0x0fec: /* paddsb */
7233 case 0x0fed: /* paddsw */
7234 case 0x0fee: /* pmaxsw */
7235 case 0x0fef: /* pxor */
7236 case 0x0ff1: /* psllw */
7237 case 0x0ff2: /* pslld */
7238 case 0x0ff3: /* psllq */
7239 case 0x0ff4: /* pmuludq */
7240 case 0x0ff5: /* pmaddwd */
7241 case 0x0ff6: /* psadbw */
7242 case 0x0ff8: /* psubb */
7243 case 0x0ff9: /* psubw */
7244 case 0x0ffa: /* psubd */
7245 case 0x0ffb: /* psubq */
7246 case 0x0ffc: /* paddb */
7247 case 0x0ffd: /* paddw */
7248 case 0x0ffe: /* paddd */
7249 if (i386_record_modrm (&ir))
7251 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7253 record_arch_list_add_reg (ir.regcache,
7254 I387_MM0_REGNUM (tdep) + ir.reg);
7257 case 0x0f71: /* psllw */
7258 case 0x0f72: /* pslld */
7259 case 0x0f73: /* psllq */
7260 if (i386_record_modrm (&ir))
7262 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7264 record_arch_list_add_reg (ir.regcache,
7265 I387_MM0_REGNUM (tdep) + ir.rm);
7268 case 0x660f71: /* psllw */
7269 case 0x660f72: /* pslld */
7270 case 0x660f73: /* psllq */
7271 if (i386_record_modrm (&ir))
7274 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
7276 record_arch_list_add_reg (ir.regcache,
7277 I387_XMM0_REGNUM (tdep) + ir.rm);
7280 case 0x0f7e: /* movd */
7281 case 0x660f7e: /* movd */
7282 if (i386_record_modrm (&ir))
7285 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7292 if (i386_record_lea_modrm (&ir))
7297 case 0x0f7f: /* movq */
7298 if (i386_record_modrm (&ir))
7302 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7304 record_arch_list_add_reg (ir.regcache,
7305 I387_MM0_REGNUM (tdep) + ir.rm);
7310 if (i386_record_lea_modrm (&ir))
7315 case 0xf30fb8: /* popcnt */
7316 if (i386_record_modrm (&ir))
7318 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
7319 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7322 case 0x660fd6: /* movq */
7323 if (i386_record_modrm (&ir))
7328 if (!i386_xmm_regnum_p (gdbarch,
7329 I387_XMM0_REGNUM (tdep) + ir.rm))
7331 record_arch_list_add_reg (ir.regcache,
7332 I387_XMM0_REGNUM (tdep) + ir.rm);
7337 if (i386_record_lea_modrm (&ir))
7342 case 0x660f3817: /* ptest */
7343 case 0x0f2e: /* ucomiss */
7344 case 0x660f2e: /* ucomisd */
7345 case 0x0f2f: /* comiss */
7346 case 0x660f2f: /* comisd */
7347 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7350 case 0x0ff7: /* maskmovq */
7351 regcache_raw_read_unsigned (ir.regcache,
7352 ir.regmap[X86_RECORD_REDI_REGNUM],
7354 if (record_arch_list_add_mem (addr, 64))
7358 case 0x660ff7: /* maskmovdqu */
7359 regcache_raw_read_unsigned (ir.regcache,
7360 ir.regmap[X86_RECORD_REDI_REGNUM],
7362 if (record_arch_list_add_mem (addr, 128))
7377 /* In the future, maybe still need to deal with need_dasm. */
7378 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
7379 if (record_arch_list_add_end ())
7385 printf_unfiltered (_("Process record does not support instruction 0x%02x "
7386 "at address %s.\n"),
7387 (unsigned int) (opcode),
7388 paddress (gdbarch, ir.orig_addr));
7392 static const int i386_record_regmap[] =
7394 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
7395 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
7396 0, 0, 0, 0, 0, 0, 0, 0,
7397 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
7398 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
7401 /* Check that the given address appears suitable for a fast
7402 tracepoint, which on x86-64 means that we need an instruction of at
7403 least 5 bytes, so that we can overwrite it with a 4-byte-offset
7404 jump and not have to worry about program jumps to an address in the
7405 middle of the tracepoint jump. On x86, it may be possible to use
7406 4-byte jumps with a 2-byte offset to a trampoline located in the
7407 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
7408 of instruction to replace, and 0 if not, plus an explanatory
7412 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch,
7413 CORE_ADDR addr, int *isize, char **msg)
7416 static struct ui_file *gdb_null = NULL;
7418 /* Ask the target for the minimum instruction length supported. */
7419 jumplen = target_get_min_fast_tracepoint_insn_len ();
7423 /* If the target does not support the get_min_fast_tracepoint_insn_len
7424 operation, assume that fast tracepoints will always be implemented
7425 using 4-byte relative jumps on both x86 and x86-64. */
7428 else if (jumplen == 0)
7430 /* If the target does support get_min_fast_tracepoint_insn_len but
7431 returns zero, then the IPA has not loaded yet. In this case,
7432 we optimistically assume that truncated 2-byte relative jumps
7433 will be available on x86, and compensate later if this assumption
7434 turns out to be incorrect. On x86-64 architectures, 4-byte relative
7435 jumps will always be used. */
7436 jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4;
7439 /* Dummy file descriptor for the disassembler. */
7441 gdb_null = ui_file_new ();
7443 /* Check for fit. */
7444 len = gdb_print_insn (gdbarch, addr, gdb_null, NULL);
7450 /* Return a bit of target-specific detail to add to the caller's
7451 generic failure message. */
7453 *msg = xstrprintf (_("; instruction is only %d bytes long, "
7454 "need at least %d bytes for the jump"),
7467 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
7468 struct tdesc_arch_data *tdesc_data)
7470 const struct target_desc *tdesc = tdep->tdesc;
7471 const struct tdesc_feature *feature_core;
7472 const struct tdesc_feature *feature_sse, *feature_avx;
7473 int i, num_regs, valid_p;
7475 if (! tdesc_has_registers (tdesc))
7478 /* Get core registers. */
7479 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
7480 if (feature_core == NULL)
7483 /* Get SSE registers. */
7484 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
7486 /* Try AVX registers. */
7487 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
7491 /* The XCR0 bits. */
7494 /* AVX register description requires SSE register description. */
7498 tdep->xcr0 = I386_XSTATE_AVX_MASK;
7500 /* It may have been set by OSABI initialization function. */
7501 if (tdep->num_ymm_regs == 0)
7503 tdep->ymmh_register_names = i386_ymmh_names;
7504 tdep->num_ymm_regs = 8;
7505 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
7508 for (i = 0; i < tdep->num_ymm_regs; i++)
7509 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
7510 tdep->ymm0h_regnum + i,
7511 tdep->ymmh_register_names[i]);
7513 else if (feature_sse)
7514 tdep->xcr0 = I386_XSTATE_SSE_MASK;
7517 tdep->xcr0 = I386_XSTATE_X87_MASK;
7518 tdep->num_xmm_regs = 0;
7521 num_regs = tdep->num_core_regs;
7522 for (i = 0; i < num_regs; i++)
7523 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
7524 tdep->register_names[i]);
7528 /* Need to include %mxcsr, so add one. */
7529 num_regs += tdep->num_xmm_regs + 1;
7530 for (; i < num_regs; i++)
7531 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
7532 tdep->register_names[i]);
7539 static struct gdbarch *
7540 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
7542 struct gdbarch_tdep *tdep;
7543 struct gdbarch *gdbarch;
7544 struct tdesc_arch_data *tdesc_data;
7545 const struct target_desc *tdesc;
7549 /* If there is already a candidate, use it. */
7550 arches = gdbarch_list_lookup_by_info (arches, &info);
7552 return arches->gdbarch;
7554 /* Allocate space for the new architecture. */
7555 tdep = XCALLOC (1, struct gdbarch_tdep);
7556 gdbarch = gdbarch_alloc (&info, tdep);
7558 /* General-purpose registers. */
7559 tdep->gregset = NULL;
7560 tdep->gregset_reg_offset = NULL;
7561 tdep->gregset_num_regs = I386_NUM_GREGS;
7562 tdep->sizeof_gregset = 0;
7564 /* Floating-point registers. */
7565 tdep->fpregset = NULL;
7566 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
7568 tdep->xstateregset = NULL;
7570 /* The default settings include the FPU registers, the MMX registers
7571 and the SSE registers. This can be overridden for a specific ABI
7572 by adjusting the members `st0_regnum', `mm0_regnum' and
7573 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
7574 will show up in the output of "info all-registers". */
7576 tdep->st0_regnum = I386_ST0_REGNUM;
7578 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
7579 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
7581 tdep->jb_pc_offset = -1;
7582 tdep->struct_return = pcc_struct_return;
7583 tdep->sigtramp_start = 0;
7584 tdep->sigtramp_end = 0;
7585 tdep->sigtramp_p = i386_sigtramp_p;
7586 tdep->sigcontext_addr = NULL;
7587 tdep->sc_reg_offset = NULL;
7588 tdep->sc_pc_offset = -1;
7589 tdep->sc_sp_offset = -1;
7591 tdep->xsave_xcr0_offset = -1;
7593 tdep->record_regmap = i386_record_regmap;
7595 set_gdbarch_long_long_align_bit (gdbarch, 32);
7597 /* The format used for `long double' on almost all i386 targets is
7598 the i387 extended floating-point format. In fact, of all targets
7599 in the GCC 2.95 tree, only OSF/1 does it different, and insists
7600 on having a `long double' that's not `long' at all. */
7601 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
7603 /* Although the i387 extended floating-point has only 80 significant
7604 bits, a `long double' actually takes up 96, probably to enforce
7606 set_gdbarch_long_double_bit (gdbarch, 96);
7608 /* Register numbers of various important registers. */
7609 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
7610 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
7611 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
7612 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
7614 /* NOTE: kettenis/20040418: GCC does have two possible register
7615 numbering schemes on the i386: dbx and SVR4. These schemes
7616 differ in how they number %ebp, %esp, %eflags, and the
7617 floating-point registers, and are implemented by the arrays
7618 dbx_register_map[] and svr4_dbx_register_map in
7619 gcc/config/i386.c. GCC also defines a third numbering scheme in
7620 gcc/config/i386.c, which it designates as the "default" register
7621 map used in 64bit mode. This last register numbering scheme is
7622 implemented in dbx64_register_map, and is used for AMD64; see
7625 Currently, each GCC i386 target always uses the same register
7626 numbering scheme across all its supported debugging formats
7627 i.e. SDB (COFF), stabs and DWARF 2. This is because
7628 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7629 DBX_REGISTER_NUMBER macro which is defined by each target's
7630 respective config header in a manner independent of the requested
7631 output debugging format.
7633 This does not match the arrangement below, which presumes that
7634 the SDB and stabs numbering schemes differ from the DWARF and
7635 DWARF 2 ones. The reason for this arrangement is that it is
7636 likely to get the numbering scheme for the target's
7637 default/native debug format right. For targets where GCC is the
7638 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7639 targets where the native toolchain uses a different numbering
7640 scheme for a particular debug format (stabs-in-ELF on Solaris)
7641 the defaults below will have to be overridden, like
7642 i386_elf_init_abi() does. */
7644 /* Use the dbx register numbering scheme for stabs and COFF. */
7645 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
7646 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
7648 /* Use the SVR4 register numbering scheme for DWARF 2. */
7649 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
7651 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7652 be in use on any of the supported i386 targets. */
7654 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
7656 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
7658 /* Call dummy code. */
7659 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
7660 set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code);
7661 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
7662 set_gdbarch_frame_align (gdbarch, i386_frame_align);
7664 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
7665 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
7666 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
7668 set_gdbarch_return_value (gdbarch, i386_return_value);
7670 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
7672 /* Stack grows downward. */
7673 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
7675 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc);
7676 set_gdbarch_decr_pc_after_break (gdbarch, 1);
7677 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
7679 set_gdbarch_frame_args_skip (gdbarch, 8);
7681 set_gdbarch_print_insn (gdbarch, i386_print_insn);
7683 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
7685 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
7687 /* Add the i386 register groups. */
7688 i386_add_reggroups (gdbarch);
7689 tdep->register_reggroup_p = i386_register_reggroup_p;
7691 /* Helper for function argument information. */
7692 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
7694 /* Hook the function epilogue frame unwinder. This unwinder is
7695 appended to the list first, so that it supercedes the DWARF
7696 unwinder in function epilogues (where the DWARF unwinder
7697 currently fails). */
7698 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
7700 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7701 to the list before the prologue-based unwinders, so that DWARF
7702 CFI info will be used if it is available. */
7703 dwarf2_append_unwinders (gdbarch);
7705 frame_base_set_default (gdbarch, &i386_frame_base);
7707 /* Pseudo registers may be changed by amd64_init_abi. */
7708 set_gdbarch_pseudo_register_read_value (gdbarch,
7709 i386_pseudo_register_read_value);
7710 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
7712 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
7713 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
7715 /* Override the normal target description method to make the AVX
7716 upper halves anonymous. */
7717 set_gdbarch_register_name (gdbarch, i386_register_name);
7719 /* Even though the default ABI only includes general-purpose registers,
7720 floating-point registers and the SSE registers, we have to leave a
7721 gap for the upper AVX registers. */
7722 set_gdbarch_num_regs (gdbarch, I386_AVX_NUM_REGS);
7724 /* Get the x86 target description from INFO. */
7725 tdesc = info.target_desc;
7726 if (! tdesc_has_registers (tdesc))
7728 tdep->tdesc = tdesc;
7730 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
7731 tdep->register_names = i386_register_names;
7733 /* No upper YMM registers. */
7734 tdep->ymmh_register_names = NULL;
7735 tdep->ymm0h_regnum = -1;
7737 tdep->num_byte_regs = 8;
7738 tdep->num_word_regs = 8;
7739 tdep->num_dword_regs = 0;
7740 tdep->num_mmx_regs = 8;
7741 tdep->num_ymm_regs = 0;
7743 tdesc_data = tdesc_data_alloc ();
7745 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
7747 set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address);
7749 /* Hook in ABI-specific overrides, if they have been registered. */
7750 info.tdep_info = (void *) tdesc_data;
7751 gdbarch_init_osabi (info, gdbarch);
7753 if (!i386_validate_tdesc_p (tdep, tdesc_data))
7755 tdesc_data_cleanup (tdesc_data);
7757 gdbarch_free (gdbarch);
7761 /* Wire in pseudo registers. Number of pseudo registers may be
7763 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
7764 + tdep->num_word_regs
7765 + tdep->num_dword_regs
7766 + tdep->num_mmx_regs
7767 + tdep->num_ymm_regs));
7769 /* Target description may be changed. */
7770 tdesc = tdep->tdesc;
7772 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
7774 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7775 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
7777 /* Make %al the first pseudo-register. */
7778 tdep->al_regnum = gdbarch_num_regs (gdbarch);
7779 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
7781 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
7782 if (tdep->num_dword_regs)
7784 /* Support dword pseudo-register if it hasn't been disabled. */
7785 tdep->eax_regnum = ymm0_regnum;
7786 ymm0_regnum += tdep->num_dword_regs;
7789 tdep->eax_regnum = -1;
7791 mm0_regnum = ymm0_regnum;
7792 if (tdep->num_ymm_regs)
7794 /* Support YMM pseudo-register if it is available. */
7795 tdep->ymm0_regnum = ymm0_regnum;
7796 mm0_regnum += tdep->num_ymm_regs;
7799 tdep->ymm0_regnum = -1;
7801 if (tdep->num_mmx_regs != 0)
7803 /* Support MMX pseudo-register if MMX hasn't been disabled. */
7804 tdep->mm0_regnum = mm0_regnum;
7807 tdep->mm0_regnum = -1;
7809 /* Hook in the legacy prologue-based unwinders last (fallback). */
7810 frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind);
7811 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
7812 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
7814 /* If we have a register mapping, enable the generic core file
7815 support, unless it has already been enabled. */
7816 if (tdep->gregset_reg_offset
7817 && !gdbarch_regset_from_core_section_p (gdbarch))
7818 set_gdbarch_regset_from_core_section (gdbarch,
7819 i386_regset_from_core_section);
7821 set_gdbarch_skip_permanent_breakpoint (gdbarch,
7822 i386_skip_permanent_breakpoint);
7824 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
7825 i386_fast_tracepoint_valid_at);
7830 static enum gdb_osabi
7831 i386_coff_osabi_sniffer (bfd *abfd)
7833 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
7834 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
7835 return GDB_OSABI_GO32;
7837 return GDB_OSABI_UNKNOWN;
7841 /* Provide a prototype to silence -Wmissing-prototypes. */
7842 void _initialize_i386_tdep (void);
7845 _initialize_i386_tdep (void)
7847 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
7849 /* Add the variable that controls the disassembly flavor. */
7850 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
7851 &disassembly_flavor, _("\
7852 Set the disassembly flavor."), _("\
7853 Show the disassembly flavor."), _("\
7854 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7856 NULL, /* FIXME: i18n: */
7857 &setlist, &showlist);
7859 /* Add the variable that controls the convention for returning
7861 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
7862 &struct_convention, _("\
7863 Set the convention for returning small structs."), _("\
7864 Show the convention for returning small structs."), _("\
7865 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7868 NULL, /* FIXME: i18n: */
7869 &setlist, &showlist);
7871 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
7872 i386_coff_osabi_sniffer);
7874 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
7875 i386_svr4_init_abi);
7876 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
7877 i386_go32_init_abi);
7879 /* Initialize the i386-specific register groups. */
7880 i386_init_reggroups ();
7882 /* Initialize the standard target descriptions. */
7883 initialize_tdesc_i386 ();
7884 initialize_tdesc_i386_mmx ();
7885 initialize_tdesc_i386_avx ();
7887 /* Tell remote stub that we support XML target description. */
7888 register_remote_support_xml ("i386");