1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2014 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
37 #include "reggroups.h"
46 #include "exceptions.h"
47 #include "gdb_assert.h"
50 #include "i386-tdep.h"
51 #include "i387-tdep.h"
52 #include "i386-xstate.h"
55 #include "record-full.h"
58 #include "features/i386/i386.c"
59 #include "features/i386/i386-avx.c"
60 #include "features/i386/i386-mpx.c"
61 #include "features/i386/i386-avx512.c"
62 #include "features/i386/i386-mmx.c"
67 #include "stap-probe.h"
68 #include "user-regs.h"
69 #include "cli/cli-utils.h"
70 #include "expression.h"
71 #include "parser-defs.h"
76 static const char *i386_register_names[] =
78 "eax", "ecx", "edx", "ebx",
79 "esp", "ebp", "esi", "edi",
80 "eip", "eflags", "cs", "ss",
81 "ds", "es", "fs", "gs",
82 "st0", "st1", "st2", "st3",
83 "st4", "st5", "st6", "st7",
84 "fctrl", "fstat", "ftag", "fiseg",
85 "fioff", "foseg", "fooff", "fop",
86 "xmm0", "xmm1", "xmm2", "xmm3",
87 "xmm4", "xmm5", "xmm6", "xmm7",
91 static const char *i386_zmm_names[] =
93 "zmm0", "zmm1", "zmm2", "zmm3",
94 "zmm4", "zmm5", "zmm6", "zmm7"
97 static const char *i386_zmmh_names[] =
99 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
100 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
103 static const char *i386_k_names[] =
105 "k0", "k1", "k2", "k3",
106 "k4", "k5", "k6", "k7"
109 static const char *i386_ymm_names[] =
111 "ymm0", "ymm1", "ymm2", "ymm3",
112 "ymm4", "ymm5", "ymm6", "ymm7",
115 static const char *i386_ymmh_names[] =
117 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
118 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
121 static const char *i386_mpx_names[] =
123 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
126 /* Register names for MPX pseudo-registers. */
128 static const char *i386_bnd_names[] =
130 "bnd0", "bnd1", "bnd2", "bnd3"
133 /* Register names for MMX pseudo-registers. */
135 static const char *i386_mmx_names[] =
137 "mm0", "mm1", "mm2", "mm3",
138 "mm4", "mm5", "mm6", "mm7"
141 /* Register names for byte pseudo-registers. */
143 static const char *i386_byte_names[] =
145 "al", "cl", "dl", "bl",
146 "ah", "ch", "dh", "bh"
149 /* Register names for word pseudo-registers. */
151 static const char *i386_word_names[] =
153 "ax", "cx", "dx", "bx",
157 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
158 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
159 we have 16 upper ZMM regs that have to be handled differently. */
161 const int num_lower_zmm_regs = 16;
166 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
168 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
169 int mm0_regnum = tdep->mm0_regnum;
174 regnum -= mm0_regnum;
175 return regnum >= 0 && regnum < tdep->num_mmx_regs;
181 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
183 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
185 regnum -= tdep->al_regnum;
186 return regnum >= 0 && regnum < tdep->num_byte_regs;
192 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
194 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
196 regnum -= tdep->ax_regnum;
197 return regnum >= 0 && regnum < tdep->num_word_regs;
200 /* Dword register? */
203 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
205 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
206 int eax_regnum = tdep->eax_regnum;
211 regnum -= eax_regnum;
212 return regnum >= 0 && regnum < tdep->num_dword_regs;
215 /* AVX512 register? */
218 i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum)
220 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
221 int zmm0h_regnum = tdep->zmm0h_regnum;
223 if (zmm0h_regnum < 0)
226 regnum -= zmm0h_regnum;
227 return regnum >= 0 && regnum < tdep->num_zmm_regs;
231 i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum)
233 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
234 int zmm0_regnum = tdep->zmm0_regnum;
239 regnum -= zmm0_regnum;
240 return regnum >= 0 && regnum < tdep->num_zmm_regs;
244 i386_k_regnum_p (struct gdbarch *gdbarch, int regnum)
246 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
247 int k0_regnum = tdep->k0_regnum;
253 return regnum >= 0 && regnum < I387_NUM_K_REGS;
257 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
259 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
260 int ymm0h_regnum = tdep->ymm0h_regnum;
262 if (ymm0h_regnum < 0)
265 regnum -= ymm0h_regnum;
266 return regnum >= 0 && regnum < tdep->num_ymm_regs;
272 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
274 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
275 int ymm0_regnum = tdep->ymm0_regnum;
280 regnum -= ymm0_regnum;
281 return regnum >= 0 && regnum < tdep->num_ymm_regs;
285 i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
287 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
288 int ymm16h_regnum = tdep->ymm16h_regnum;
290 if (ymm16h_regnum < 0)
293 regnum -= ymm16h_regnum;
294 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
298 i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
300 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
301 int ymm16_regnum = tdep->ymm16_regnum;
303 if (ymm16_regnum < 0)
306 regnum -= ymm16_regnum;
307 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
313 i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum)
315 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
316 int bnd0_regnum = tdep->bnd0_regnum;
321 regnum -= bnd0_regnum;
322 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
328 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
330 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
331 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
333 if (num_xmm_regs == 0)
336 regnum -= I387_XMM0_REGNUM (tdep);
337 return regnum >= 0 && regnum < num_xmm_regs;
340 /* XMM_512 register? */
343 i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
345 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
346 int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep);
348 if (num_xmm_avx512_regs == 0)
351 regnum -= I387_XMM16_REGNUM (tdep);
352 return regnum >= 0 && regnum < num_xmm_avx512_regs;
356 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
358 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
360 if (I387_NUM_XMM_REGS (tdep) == 0)
363 return (regnum == I387_MXCSR_REGNUM (tdep));
369 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
371 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
373 if (I387_ST0_REGNUM (tdep) < 0)
376 return (I387_ST0_REGNUM (tdep) <= regnum
377 && regnum < I387_FCTRL_REGNUM (tdep));
381 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
383 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
385 if (I387_ST0_REGNUM (tdep) < 0)
388 return (I387_FCTRL_REGNUM (tdep) <= regnum
389 && regnum < I387_XMM0_REGNUM (tdep));
392 /* BNDr (raw) register? */
395 i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum)
397 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
399 if (I387_BND0R_REGNUM (tdep) < 0)
402 regnum -= tdep->bnd0r_regnum;
403 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
406 /* BND control register? */
409 i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum)
411 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
413 if (I387_BNDCFGU_REGNUM (tdep) < 0)
416 regnum -= I387_BNDCFGU_REGNUM (tdep);
417 return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS;
420 /* Return the name of register REGNUM, or the empty string if it is
421 an anonymous register. */
424 i386_register_name (struct gdbarch *gdbarch, int regnum)
426 /* Hide the upper YMM registers. */
427 if (i386_ymmh_regnum_p (gdbarch, regnum))
430 /* Hide the upper YMM16-31 registers. */
431 if (i386_ymmh_avx512_regnum_p (gdbarch, regnum))
434 /* Hide the upper ZMM registers. */
435 if (i386_zmmh_regnum_p (gdbarch, regnum))
438 return tdesc_register_name (gdbarch, regnum);
441 /* Return the name of register REGNUM. */
444 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
446 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
447 if (i386_bnd_regnum_p (gdbarch, regnum))
448 return i386_bnd_names[regnum - tdep->bnd0_regnum];
449 if (i386_mmx_regnum_p (gdbarch, regnum))
450 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
451 else if (i386_ymm_regnum_p (gdbarch, regnum))
452 return i386_ymm_names[regnum - tdep->ymm0_regnum];
453 else if (i386_zmm_regnum_p (gdbarch, regnum))
454 return i386_zmm_names[regnum - tdep->zmm0_regnum];
455 else if (i386_byte_regnum_p (gdbarch, regnum))
456 return i386_byte_names[regnum - tdep->al_regnum];
457 else if (i386_word_regnum_p (gdbarch, regnum))
458 return i386_word_names[regnum - tdep->ax_regnum];
460 internal_error (__FILE__, __LINE__, _("invalid regnum"));
463 /* Convert a dbx register number REG to the appropriate register
464 number used by GDB. */
467 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
469 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
471 /* This implements what GCC calls the "default" register map
472 (dbx_register_map[]). */
474 if (reg >= 0 && reg <= 7)
476 /* General-purpose registers. The debug info calls %ebp
477 register 4, and %esp register 5. */
484 else if (reg >= 12 && reg <= 19)
486 /* Floating-point registers. */
487 return reg - 12 + I387_ST0_REGNUM (tdep);
489 else if (reg >= 21 && reg <= 28)
492 int ymm0_regnum = tdep->ymm0_regnum;
495 && i386_xmm_regnum_p (gdbarch, reg))
496 return reg - 21 + ymm0_regnum;
498 return reg - 21 + I387_XMM0_REGNUM (tdep);
500 else if (reg >= 29 && reg <= 36)
503 return reg - 29 + I387_MM0_REGNUM (tdep);
506 /* This will hopefully provoke a warning. */
507 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
510 /* Convert SVR4 register number REG to the appropriate register number
514 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
516 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
518 /* This implements the GCC register map that tries to be compatible
519 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
521 /* The SVR4 register numbering includes %eip and %eflags, and
522 numbers the floating point registers differently. */
523 if (reg >= 0 && reg <= 9)
525 /* General-purpose registers. */
528 else if (reg >= 11 && reg <= 18)
530 /* Floating-point registers. */
531 return reg - 11 + I387_ST0_REGNUM (tdep);
533 else if (reg >= 21 && reg <= 36)
535 /* The SSE and MMX registers have the same numbers as with dbx. */
536 return i386_dbx_reg_to_regnum (gdbarch, reg);
541 case 37: return I387_FCTRL_REGNUM (tdep);
542 case 38: return I387_FSTAT_REGNUM (tdep);
543 case 39: return I387_MXCSR_REGNUM (tdep);
544 case 40: return I386_ES_REGNUM;
545 case 41: return I386_CS_REGNUM;
546 case 42: return I386_SS_REGNUM;
547 case 43: return I386_DS_REGNUM;
548 case 44: return I386_FS_REGNUM;
549 case 45: return I386_GS_REGNUM;
552 /* This will hopefully provoke a warning. */
553 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
558 /* This is the variable that is set with "set disassembly-flavor", and
559 its legitimate values. */
560 static const char att_flavor[] = "att";
561 static const char intel_flavor[] = "intel";
562 static const char *const valid_flavors[] =
568 static const char *disassembly_flavor = att_flavor;
571 /* Use the program counter to determine the contents and size of a
572 breakpoint instruction. Return a pointer to a string of bytes that
573 encode a breakpoint instruction, store the length of the string in
574 *LEN and optionally adjust *PC to point to the correct memory
575 location for inserting the breakpoint.
577 On the i386 we have a single breakpoint that fits in a single byte
578 and can be inserted anywhere.
580 This function is 64-bit safe. */
582 static const gdb_byte *
583 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
585 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */
587 *len = sizeof (break_insn);
591 /* Displaced instruction handling. */
593 /* Skip the legacy instruction prefixes in INSN.
594 Not all prefixes are valid for any particular insn
595 but we needn't care, the insn will fault if it's invalid.
596 The result is a pointer to the first opcode byte,
597 or NULL if we run off the end of the buffer. */
600 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
602 gdb_byte *end = insn + max_len;
608 case DATA_PREFIX_OPCODE:
609 case ADDR_PREFIX_OPCODE:
610 case CS_PREFIX_OPCODE:
611 case DS_PREFIX_OPCODE:
612 case ES_PREFIX_OPCODE:
613 case FS_PREFIX_OPCODE:
614 case GS_PREFIX_OPCODE:
615 case SS_PREFIX_OPCODE:
616 case LOCK_PREFIX_OPCODE:
617 case REPE_PREFIX_OPCODE:
618 case REPNE_PREFIX_OPCODE:
630 i386_absolute_jmp_p (const gdb_byte *insn)
632 /* jmp far (absolute address in operand). */
638 /* jump near, absolute indirect (/4). */
639 if ((insn[1] & 0x38) == 0x20)
642 /* jump far, absolute indirect (/5). */
643 if ((insn[1] & 0x38) == 0x28)
650 /* Return non-zero if INSN is a jump, zero otherwise. */
653 i386_jmp_p (const gdb_byte *insn)
655 /* jump short, relative. */
659 /* jump near, relative. */
663 return i386_absolute_jmp_p (insn);
667 i386_absolute_call_p (const gdb_byte *insn)
669 /* call far, absolute. */
675 /* Call near, absolute indirect (/2). */
676 if ((insn[1] & 0x38) == 0x10)
679 /* Call far, absolute indirect (/3). */
680 if ((insn[1] & 0x38) == 0x18)
688 i386_ret_p (const gdb_byte *insn)
692 case 0xc2: /* ret near, pop N bytes. */
693 case 0xc3: /* ret near */
694 case 0xca: /* ret far, pop N bytes. */
695 case 0xcb: /* ret far */
696 case 0xcf: /* iret */
705 i386_call_p (const gdb_byte *insn)
707 if (i386_absolute_call_p (insn))
710 /* call near, relative. */
717 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
718 length in bytes. Otherwise, return zero. */
721 i386_syscall_p (const gdb_byte *insn, int *lengthp)
723 /* Is it 'int $0x80'? */
724 if ((insn[0] == 0xcd && insn[1] == 0x80)
725 /* Or is it 'sysenter'? */
726 || (insn[0] == 0x0f && insn[1] == 0x34)
727 /* Or is it 'syscall'? */
728 || (insn[0] == 0x0f && insn[1] == 0x05))
737 /* The gdbarch insn_is_call method. */
740 i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
742 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
744 read_code (addr, buf, I386_MAX_INSN_LEN);
745 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
747 return i386_call_p (insn);
750 /* The gdbarch insn_is_ret method. */
753 i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
755 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
757 read_code (addr, buf, I386_MAX_INSN_LEN);
758 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
760 return i386_ret_p (insn);
763 /* The gdbarch insn_is_jump method. */
766 i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
768 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
770 read_code (addr, buf, I386_MAX_INSN_LEN);
771 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
773 return i386_jmp_p (insn);
776 /* Some kernels may run one past a syscall insn, so we have to cope.
777 Otherwise this is just simple_displaced_step_copy_insn. */
779 struct displaced_step_closure *
780 i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
781 CORE_ADDR from, CORE_ADDR to,
782 struct regcache *regs)
784 size_t len = gdbarch_max_insn_length (gdbarch);
785 gdb_byte *buf = xmalloc (len);
787 read_memory (from, buf, len);
789 /* GDB may get control back after the insn after the syscall.
790 Presumably this is a kernel bug.
791 If this is a syscall, make sure there's a nop afterwards. */
796 insn = i386_skip_prefixes (buf, len);
797 if (insn != NULL && i386_syscall_p (insn, &syscall_length))
798 insn[syscall_length] = NOP_OPCODE;
801 write_memory (to, buf, len);
805 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
806 paddress (gdbarch, from), paddress (gdbarch, to));
807 displaced_step_dump_bytes (gdb_stdlog, buf, len);
810 return (struct displaced_step_closure *) buf;
813 /* Fix up the state of registers and memory after having single-stepped
814 a displaced instruction. */
817 i386_displaced_step_fixup (struct gdbarch *gdbarch,
818 struct displaced_step_closure *closure,
819 CORE_ADDR from, CORE_ADDR to,
820 struct regcache *regs)
822 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
824 /* The offset we applied to the instruction's address.
825 This could well be negative (when viewed as a signed 32-bit
826 value), but ULONGEST won't reflect that, so take care when
828 ULONGEST insn_offset = to - from;
830 /* Since we use simple_displaced_step_copy_insn, our closure is a
831 copy of the instruction. */
832 gdb_byte *insn = (gdb_byte *) closure;
833 /* The start of the insn, needed in case we see some prefixes. */
834 gdb_byte *insn_start = insn;
837 fprintf_unfiltered (gdb_stdlog,
838 "displaced: fixup (%s, %s), "
839 "insn = 0x%02x 0x%02x ...\n",
840 paddress (gdbarch, from), paddress (gdbarch, to),
843 /* The list of issues to contend with here is taken from
844 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
845 Yay for Free Software! */
847 /* Relocate the %eip, if necessary. */
849 /* The instruction recognizers we use assume any leading prefixes
850 have been skipped. */
852 /* This is the size of the buffer in closure. */
853 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
854 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
855 /* If there are too many prefixes, just ignore the insn.
856 It will fault when run. */
861 /* Except in the case of absolute or indirect jump or call
862 instructions, or a return instruction, the new eip is relative to
863 the displaced instruction; make it relative. Well, signal
864 handler returns don't need relocation either, but we use the
865 value of %eip to recognize those; see below. */
866 if (! i386_absolute_jmp_p (insn)
867 && ! i386_absolute_call_p (insn)
868 && ! i386_ret_p (insn))
873 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
875 /* A signal trampoline system call changes the %eip, resuming
876 execution of the main program after the signal handler has
877 returned. That makes them like 'return' instructions; we
878 shouldn't relocate %eip.
880 But most system calls don't, and we do need to relocate %eip.
882 Our heuristic for distinguishing these cases: if stepping
883 over the system call instruction left control directly after
884 the instruction, the we relocate --- control almost certainly
885 doesn't belong in the displaced copy. Otherwise, we assume
886 the instruction has put control where it belongs, and leave
887 it unrelocated. Goodness help us if there are PC-relative
889 if (i386_syscall_p (insn, &insn_len)
890 && orig_eip != to + (insn - insn_start) + insn_len
891 /* GDB can get control back after the insn after the syscall.
892 Presumably this is a kernel bug.
893 i386_displaced_step_copy_insn ensures its a nop,
894 we add one to the length for it. */
895 && orig_eip != to + (insn - insn_start) + insn_len + 1)
898 fprintf_unfiltered (gdb_stdlog,
899 "displaced: syscall changed %%eip; "
904 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
906 /* If we just stepped over a breakpoint insn, we don't backup
907 the pc on purpose; this is to match behaviour without
910 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
913 fprintf_unfiltered (gdb_stdlog,
915 "relocated %%eip from %s to %s\n",
916 paddress (gdbarch, orig_eip),
917 paddress (gdbarch, eip));
921 /* If the instruction was PUSHFL, then the TF bit will be set in the
922 pushed value, and should be cleared. We'll leave this for later,
923 since GDB already messes up the TF flag when stepping over a
926 /* If the instruction was a call, the return address now atop the
927 stack is the address following the copied instruction. We need
928 to make it the address following the original instruction. */
929 if (i386_call_p (insn))
933 const ULONGEST retaddr_len = 4;
935 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
936 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
937 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
938 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
941 fprintf_unfiltered (gdb_stdlog,
942 "displaced: relocated return addr at %s to %s\n",
943 paddress (gdbarch, esp),
944 paddress (gdbarch, retaddr));
949 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
951 target_write_memory (*to, buf, len);
956 i386_relocate_instruction (struct gdbarch *gdbarch,
957 CORE_ADDR *to, CORE_ADDR oldloc)
959 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
960 gdb_byte buf[I386_MAX_INSN_LEN];
961 int offset = 0, rel32, newrel;
963 gdb_byte *insn = buf;
965 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
967 insn_length = gdb_buffered_insn_length (gdbarch, insn,
968 I386_MAX_INSN_LEN, oldloc);
970 /* Get past the prefixes. */
971 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
973 /* Adjust calls with 32-bit relative addresses as push/jump, with
974 the address pushed being the location where the original call in
975 the user program would return to. */
978 gdb_byte push_buf[16];
979 unsigned int ret_addr;
981 /* Where "ret" in the original code will return to. */
982 ret_addr = oldloc + insn_length;
983 push_buf[0] = 0x68; /* pushq $... */
984 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
986 append_insns (to, 5, push_buf);
988 /* Convert the relative call to a relative jump. */
991 /* Adjust the destination offset. */
992 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
993 newrel = (oldloc - *to) + rel32;
994 store_signed_integer (insn + 1, 4, byte_order, newrel);
997 fprintf_unfiltered (gdb_stdlog,
998 "Adjusted insn rel32=%s at %s to"
1000 hex_string (rel32), paddress (gdbarch, oldloc),
1001 hex_string (newrel), paddress (gdbarch, *to));
1003 /* Write the adjusted jump into its displaced location. */
1004 append_insns (to, 5, insn);
1008 /* Adjust jumps with 32-bit relative addresses. Calls are already
1010 if (insn[0] == 0xe9)
1012 /* Adjust conditional jumps. */
1013 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1018 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1019 newrel = (oldloc - *to) + rel32;
1020 store_signed_integer (insn + offset, 4, byte_order, newrel);
1021 if (debug_displaced)
1022 fprintf_unfiltered (gdb_stdlog,
1023 "Adjusted insn rel32=%s at %s to"
1024 " rel32=%s at %s\n",
1025 hex_string (rel32), paddress (gdbarch, oldloc),
1026 hex_string (newrel), paddress (gdbarch, *to));
1029 /* Write the adjusted instructions into their displaced
1031 append_insns (to, insn_length, buf);
1035 #ifdef I386_REGNO_TO_SYMMETRY
1036 #error "The Sequent Symmetry is no longer supported."
1039 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1040 and %esp "belong" to the calling function. Therefore these
1041 registers should be saved if they're going to be modified. */
1043 /* The maximum number of saved registers. This should include all
1044 registers mentioned above, and %eip. */
1045 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1047 struct i386_frame_cache
1055 /* Saved registers. */
1056 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
1061 /* Stack space reserved for local variables. */
1065 /* Allocate and initialize a frame cache. */
1067 static struct i386_frame_cache *
1068 i386_alloc_frame_cache (void)
1070 struct i386_frame_cache *cache;
1073 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
1078 cache->sp_offset = -4;
1081 /* Saved registers. We initialize these to -1 since zero is a valid
1082 offset (that's where %ebp is supposed to be stored). */
1083 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1084 cache->saved_regs[i] = -1;
1085 cache->saved_sp = 0;
1086 cache->saved_sp_reg = -1;
1087 cache->pc_in_eax = 0;
1089 /* Frameless until proven otherwise. */
1095 /* If the instruction at PC is a jump, return the address of its
1096 target. Otherwise, return PC. */
1099 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
1101 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1106 if (target_read_code (pc, &op, 1))
1113 op = read_code_unsigned_integer (pc + 1, 1, byte_order);
1119 /* Relative jump: if data16 == 0, disp32, else disp16. */
1122 delta = read_memory_integer (pc + 2, 2, byte_order);
1124 /* Include the size of the jmp instruction (including the
1130 delta = read_memory_integer (pc + 1, 4, byte_order);
1132 /* Include the size of the jmp instruction. */
1137 /* Relative jump, disp8 (ignore data16). */
1138 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
1140 delta += data16 + 2;
1147 /* Check whether PC points at a prologue for a function returning a
1148 structure or union. If so, it updates CACHE and returns the
1149 address of the first instruction after the code sequence that
1150 removes the "hidden" argument from the stack or CURRENT_PC,
1151 whichever is smaller. Otherwise, return PC. */
1154 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
1155 struct i386_frame_cache *cache)
1157 /* Functions that return a structure or union start with:
1160 xchgl %eax, (%esp) 0x87 0x04 0x24
1161 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1163 (the System V compiler puts out the second `xchg' instruction,
1164 and the assembler doesn't try to optimize it, so the 'sib' form
1165 gets generated). This sequence is used to get the address of the
1166 return buffer for a function that returns a structure. */
1167 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
1168 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
1172 if (current_pc <= pc)
1175 if (target_read_code (pc, &op, 1))
1178 if (op != 0x58) /* popl %eax */
1181 if (target_read_code (pc + 1, buf, 4))
1184 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
1187 if (current_pc == pc)
1189 cache->sp_offset += 4;
1193 if (current_pc == pc + 1)
1195 cache->pc_in_eax = 1;
1199 if (buf[1] == proto1[1])
1206 i386_skip_probe (CORE_ADDR pc)
1208 /* A function may start with
1222 if (target_read_code (pc, &op, 1))
1225 if (op == 0x68 || op == 0x6a)
1229 /* Skip past the `pushl' instruction; it has either a one-byte or a
1230 four-byte operand, depending on the opcode. */
1236 /* Read the following 8 bytes, which should be `call _probe' (6
1237 bytes) followed by `addl $4,%esp' (2 bytes). */
1238 read_memory (pc + delta, buf, sizeof (buf));
1239 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
1240 pc += delta + sizeof (buf);
1246 /* GCC 4.1 and later, can put code in the prologue to realign the
1247 stack pointer. Check whether PC points to such code, and update
1248 CACHE accordingly. Return the first instruction after the code
1249 sequence or CURRENT_PC, whichever is smaller. If we don't
1250 recognize the code, return PC. */
1253 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1254 struct i386_frame_cache *cache)
1256 /* There are 2 code sequences to re-align stack before the frame
1259 1. Use a caller-saved saved register:
1265 2. Use a callee-saved saved register:
1272 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1274 0x83 0xe4 0xf0 andl $-16, %esp
1275 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1280 int offset, offset_and;
1281 static int regnums[8] = {
1282 I386_EAX_REGNUM, /* %eax */
1283 I386_ECX_REGNUM, /* %ecx */
1284 I386_EDX_REGNUM, /* %edx */
1285 I386_EBX_REGNUM, /* %ebx */
1286 I386_ESP_REGNUM, /* %esp */
1287 I386_EBP_REGNUM, /* %ebp */
1288 I386_ESI_REGNUM, /* %esi */
1289 I386_EDI_REGNUM /* %edi */
1292 if (target_read_code (pc, buf, sizeof buf))
1295 /* Check caller-saved saved register. The first instruction has
1296 to be "leal 4(%esp), %reg". */
1297 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1299 /* MOD must be binary 10 and R/M must be binary 100. */
1300 if ((buf[1] & 0xc7) != 0x44)
1303 /* REG has register number. */
1304 reg = (buf[1] >> 3) & 7;
1309 /* Check callee-saved saved register. The first instruction
1310 has to be "pushl %reg". */
1311 if ((buf[0] & 0xf8) != 0x50)
1317 /* The next instruction has to be "leal 8(%esp), %reg". */
1318 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1321 /* MOD must be binary 10 and R/M must be binary 100. */
1322 if ((buf[2] & 0xc7) != 0x44)
1325 /* REG has register number. Registers in pushl and leal have to
1327 if (reg != ((buf[2] >> 3) & 7))
1333 /* Rigister can't be %esp nor %ebp. */
1334 if (reg == 4 || reg == 5)
1337 /* The next instruction has to be "andl $-XXX, %esp". */
1338 if (buf[offset + 1] != 0xe4
1339 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1342 offset_and = offset;
1343 offset += buf[offset] == 0x81 ? 6 : 3;
1345 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1346 0xfc. REG must be binary 110 and MOD must be binary 01. */
1347 if (buf[offset] != 0xff
1348 || buf[offset + 2] != 0xfc
1349 || (buf[offset + 1] & 0xf8) != 0x70)
1352 /* R/M has register. Registers in leal and pushl have to be the
1354 if (reg != (buf[offset + 1] & 7))
1357 if (current_pc > pc + offset_and)
1358 cache->saved_sp_reg = regnums[reg];
1360 return min (pc + offset + 3, current_pc);
1363 /* Maximum instruction length we need to handle. */
1364 #define I386_MAX_MATCHED_INSN_LEN 6
1366 /* Instruction description. */
1370 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
1371 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
1374 /* Return whether instruction at PC matches PATTERN. */
1377 i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern)
1381 if (target_read_code (pc, &op, 1))
1384 if ((op & pattern.mask[0]) == pattern.insn[0])
1386 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1387 int insn_matched = 1;
1390 gdb_assert (pattern.len > 1);
1391 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN);
1393 if (target_read_code (pc + 1, buf, pattern.len - 1))
1396 for (i = 1; i < pattern.len; i++)
1398 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i])
1401 return insn_matched;
1406 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1407 the first instruction description that matches. Otherwise, return
1410 static struct i386_insn *
1411 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns)
1413 struct i386_insn *pattern;
1415 for (pattern = insn_patterns; pattern->len > 0; pattern++)
1417 if (i386_match_pattern (pc, *pattern))
1424 /* Return whether PC points inside a sequence of instructions that
1425 matches INSN_PATTERNS. */
1428 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns)
1430 CORE_ADDR current_pc;
1432 struct i386_insn *insn;
1434 insn = i386_match_insn (pc, insn_patterns);
1439 ix = insn - insn_patterns;
1440 for (i = ix - 1; i >= 0; i--)
1442 current_pc -= insn_patterns[i].len;
1444 if (!i386_match_pattern (current_pc, insn_patterns[i]))
1448 current_pc = pc + insn->len;
1449 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++)
1451 if (!i386_match_pattern (current_pc, *insn))
1454 current_pc += insn->len;
1460 /* Some special instructions that might be migrated by GCC into the
1461 part of the prologue that sets up the new stack frame. Because the
1462 stack frame hasn't been setup yet, no registers have been saved
1463 yet, and only the scratch registers %eax, %ecx and %edx can be
1466 struct i386_insn i386_frame_setup_skip_insns[] =
1468 /* Check for `movb imm8, r' and `movl imm32, r'.
1470 ??? Should we handle 16-bit operand-sizes here? */
1472 /* `movb imm8, %al' and `movb imm8, %ah' */
1473 /* `movb imm8, %cl' and `movb imm8, %ch' */
1474 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1475 /* `movb imm8, %dl' and `movb imm8, %dh' */
1476 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1477 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1478 { 5, { 0xb8 }, { 0xfe } },
1479 /* `movl imm32, %edx' */
1480 { 5, { 0xba }, { 0xff } },
1482 /* Check for `mov imm32, r32'. Note that there is an alternative
1483 encoding for `mov m32, %eax'.
1485 ??? Should we handle SIB adressing here?
1486 ??? Should we handle 16-bit operand-sizes here? */
1488 /* `movl m32, %eax' */
1489 { 5, { 0xa1 }, { 0xff } },
1490 /* `movl m32, %eax' and `mov; m32, %ecx' */
1491 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1492 /* `movl m32, %edx' */
1493 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1495 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1496 Because of the symmetry, there are actually two ways to encode
1497 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1498 opcode bytes 0x31 and 0x33 for `xorl'. */
1500 /* `subl %eax, %eax' */
1501 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1502 /* `subl %ecx, %ecx' */
1503 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1504 /* `subl %edx, %edx' */
1505 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1506 /* `xorl %eax, %eax' */
1507 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1508 /* `xorl %ecx, %ecx' */
1509 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1510 /* `xorl %edx, %edx' */
1511 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1516 /* Check whether PC points to a no-op instruction. */
1518 i386_skip_noop (CORE_ADDR pc)
1523 if (target_read_code (pc, &op, 1))
1529 /* Ignore `nop' instruction. */
1533 if (target_read_code (pc, &op, 1))
1537 /* Ignore no-op instruction `mov %edi, %edi'.
1538 Microsoft system dlls often start with
1539 a `mov %edi,%edi' instruction.
1540 The 5 bytes before the function start are
1541 filled with `nop' instructions.
1542 This pattern can be used for hot-patching:
1543 The `mov %edi, %edi' instruction can be replaced by a
1544 near jump to the location of the 5 `nop' instructions
1545 which can be replaced by a 32-bit jump to anywhere
1546 in the 32-bit address space. */
1548 else if (op == 0x8b)
1550 if (target_read_code (pc + 1, &op, 1))
1556 if (target_read_code (pc, &op, 1))
1566 /* Check whether PC points at a code that sets up a new stack frame.
1567 If so, it updates CACHE and returns the address of the first
1568 instruction after the sequence that sets up the frame or LIMIT,
1569 whichever is smaller. If we don't recognize the code, return PC. */
1572 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1573 CORE_ADDR pc, CORE_ADDR limit,
1574 struct i386_frame_cache *cache)
1576 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1577 struct i386_insn *insn;
1584 if (target_read_code (pc, &op, 1))
1587 if (op == 0x55) /* pushl %ebp */
1589 /* Take into account that we've executed the `pushl %ebp' that
1590 starts this instruction sequence. */
1591 cache->saved_regs[I386_EBP_REGNUM] = 0;
1592 cache->sp_offset += 4;
1595 /* If that's all, return now. */
1599 /* Check for some special instructions that might be migrated by
1600 GCC into the prologue and skip them. At this point in the
1601 prologue, code should only touch the scratch registers %eax,
1602 %ecx and %edx, so while the number of posibilities is sheer,
1605 Make sure we only skip these instructions if we later see the
1606 `movl %esp, %ebp' that actually sets up the frame. */
1607 while (pc + skip < limit)
1609 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1616 /* If that's all, return now. */
1617 if (limit <= pc + skip)
1620 if (target_read_code (pc + skip, &op, 1))
1623 /* The i386 prologue looks like
1629 and a different prologue can be generated for atom.
1633 lea -0x10(%esp),%esp
1635 We handle both of them here. */
1639 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1641 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1647 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1652 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1653 if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order)
1662 /* OK, we actually have a frame. We just don't know how large
1663 it is yet. Set its size to zero. We'll adjust it if
1664 necessary. We also now commit to skipping the special
1665 instructions mentioned before. */
1668 /* If that's all, return now. */
1672 /* Check for stack adjustment
1678 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1679 reg, so we don't have to worry about a data16 prefix. */
1680 if (target_read_code (pc, &op, 1))
1684 /* `subl' with 8-bit immediate. */
1685 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1686 /* Some instruction starting with 0x83 other than `subl'. */
1689 /* `subl' with signed 8-bit immediate (though it wouldn't
1690 make sense to be negative). */
1691 cache->locals = read_code_integer (pc + 2, 1, byte_order);
1694 else if (op == 0x81)
1696 /* Maybe it is `subl' with a 32-bit immediate. */
1697 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1698 /* Some instruction starting with 0x81 other than `subl'. */
1701 /* It is `subl' with a 32-bit immediate. */
1702 cache->locals = read_code_integer (pc + 2, 4, byte_order);
1705 else if (op == 0x8d)
1707 /* The ModR/M byte is 0x64. */
1708 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64)
1710 /* 'lea' with 8-bit displacement. */
1711 cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order);
1716 /* Some instruction other than `subl' nor 'lea'. */
1720 else if (op == 0xc8) /* enter */
1722 cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order);
1729 /* Check whether PC points at code that saves registers on the stack.
1730 If so, it updates CACHE and returns the address of the first
1731 instruction after the register saves or CURRENT_PC, whichever is
1732 smaller. Otherwise, return PC. */
1735 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1736 struct i386_frame_cache *cache)
1738 CORE_ADDR offset = 0;
1742 if (cache->locals > 0)
1743 offset -= cache->locals;
1744 for (i = 0; i < 8 && pc < current_pc; i++)
1746 if (target_read_code (pc, &op, 1))
1748 if (op < 0x50 || op > 0x57)
1752 cache->saved_regs[op - 0x50] = offset;
1753 cache->sp_offset += 4;
1760 /* Do a full analysis of the prologue at PC and update CACHE
1761 accordingly. Bail out early if CURRENT_PC is reached. Return the
1762 address where the analysis stopped.
1764 We handle these cases:
1766 The startup sequence can be at the start of the function, or the
1767 function can start with a branch to startup code at the end.
1769 %ebp can be set up with either the 'enter' instruction, or "pushl
1770 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1771 once used in the System V compiler).
1773 Local space is allocated just below the saved %ebp by either the
1774 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1775 16-bit unsigned argument for space to allocate, and the 'addl'
1776 instruction could have either a signed byte, or 32-bit immediate.
1778 Next, the registers used by this function are pushed. With the
1779 System V compiler they will always be in the order: %edi, %esi,
1780 %ebx (and sometimes a harmless bug causes it to also save but not
1781 restore %eax); however, the code below is willing to see the pushes
1782 in any order, and will handle up to 8 of them.
1784 If the setup sequence is at the end of the function, then the next
1785 instruction will be a branch back to the start. */
1788 i386_analyze_prologue (struct gdbarch *gdbarch,
1789 CORE_ADDR pc, CORE_ADDR current_pc,
1790 struct i386_frame_cache *cache)
1792 pc = i386_skip_noop (pc);
1793 pc = i386_follow_jump (gdbarch, pc);
1794 pc = i386_analyze_struct_return (pc, current_pc, cache);
1795 pc = i386_skip_probe (pc);
1796 pc = i386_analyze_stack_align (pc, current_pc, cache);
1797 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1798 return i386_analyze_register_saves (pc, current_pc, cache);
1801 /* Return PC of first real instruction. */
1804 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1806 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1808 static gdb_byte pic_pat[6] =
1810 0xe8, 0, 0, 0, 0, /* call 0x0 */
1811 0x5b, /* popl %ebx */
1813 struct i386_frame_cache cache;
1817 CORE_ADDR func_addr;
1819 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
1821 CORE_ADDR post_prologue_pc
1822 = skip_prologue_using_sal (gdbarch, func_addr);
1823 struct symtab *s = find_pc_symtab (func_addr);
1825 /* Clang always emits a line note before the prologue and another
1826 one after. We trust clang to emit usable line notes. */
1827 if (post_prologue_pc
1829 && s->producer != NULL
1830 && strncmp (s->producer, "clang ", sizeof ("clang ") - 1) == 0))
1831 return max (start_pc, post_prologue_pc);
1835 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1836 if (cache.locals < 0)
1839 /* Found valid frame setup. */
1841 /* The native cc on SVR4 in -K PIC mode inserts the following code
1842 to get the address of the global offset table (GOT) into register
1847 movl %ebx,x(%ebp) (optional)
1850 This code is with the rest of the prologue (at the end of the
1851 function), so we have to skip it to get to the first real
1852 instruction at the start of the function. */
1854 for (i = 0; i < 6; i++)
1856 if (target_read_code (pc + i, &op, 1))
1859 if (pic_pat[i] != op)
1866 if (target_read_code (pc + delta, &op, 1))
1869 if (op == 0x89) /* movl %ebx, x(%ebp) */
1871 op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order);
1873 if (op == 0x5d) /* One byte offset from %ebp. */
1875 else if (op == 0x9d) /* Four byte offset from %ebp. */
1877 else /* Unexpected instruction. */
1880 if (target_read_code (pc + delta, &op, 1))
1885 if (delta > 0 && op == 0x81
1886 && read_code_unsigned_integer (pc + delta + 1, 1, byte_order)
1893 /* If the function starts with a branch (to startup code at the end)
1894 the last instruction should bring us back to the first
1895 instruction of the real code. */
1896 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1897 pc = i386_follow_jump (gdbarch, pc);
1902 /* Check that the code pointed to by PC corresponds to a call to
1903 __main, skip it if so. Return PC otherwise. */
1906 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1908 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1911 if (target_read_code (pc, &op, 1))
1917 if (target_read_code (pc + 1, buf, sizeof buf) == 0)
1919 /* Make sure address is computed correctly as a 32bit
1920 integer even if CORE_ADDR is 64 bit wide. */
1921 struct bound_minimal_symbol s;
1922 CORE_ADDR call_dest;
1924 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1925 call_dest = call_dest & 0xffffffffU;
1926 s = lookup_minimal_symbol_by_pc (call_dest);
1927 if (s.minsym != NULL
1928 && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL
1929 && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0)
1937 /* This function is 64-bit safe. */
1940 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1944 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1945 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1949 /* Normal frames. */
1952 i386_frame_cache_1 (struct frame_info *this_frame,
1953 struct i386_frame_cache *cache)
1955 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1956 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1960 cache->pc = get_frame_func (this_frame);
1962 /* In principle, for normal frames, %ebp holds the frame pointer,
1963 which holds the base address for the current stack frame.
1964 However, for functions that don't need it, the frame pointer is
1965 optional. For these "frameless" functions the frame pointer is
1966 actually the frame pointer of the calling frame. Signal
1967 trampolines are just a special case of a "frameless" function.
1968 They (usually) share their frame pointer with the frame that was
1969 in progress when the signal occurred. */
1971 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1972 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1973 if (cache->base == 0)
1979 /* For normal frames, %eip is stored at 4(%ebp). */
1980 cache->saved_regs[I386_EIP_REGNUM] = 4;
1983 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
1986 if (cache->locals < 0)
1988 /* We didn't find a valid frame, which means that CACHE->base
1989 currently holds the frame pointer for our calling frame. If
1990 we're at the start of a function, or somewhere half-way its
1991 prologue, the function's frame probably hasn't been fully
1992 setup yet. Try to reconstruct the base address for the stack
1993 frame by looking at the stack pointer. For truly "frameless"
1994 functions this might work too. */
1996 if (cache->saved_sp_reg != -1)
1998 /* Saved stack pointer has been saved. */
1999 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2000 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2002 /* We're halfway aligning the stack. */
2003 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
2004 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
2006 /* This will be added back below. */
2007 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
2009 else if (cache->pc != 0
2010 || target_read_code (get_frame_pc (this_frame), buf, 1))
2012 /* We're in a known function, but did not find a frame
2013 setup. Assume that the function does not use %ebp.
2014 Alternatively, we may have jumped to an invalid
2015 address; in that case there is definitely no new
2017 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2018 cache->base = extract_unsigned_integer (buf, 4, byte_order)
2022 /* We're in an unknown function. We could not find the start
2023 of the function to analyze the prologue; our best option is
2024 to assume a typical frame layout with the caller's %ebp
2026 cache->saved_regs[I386_EBP_REGNUM] = 0;
2029 if (cache->saved_sp_reg != -1)
2031 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2032 register may be unavailable). */
2033 if (cache->saved_sp == 0
2034 && deprecated_frame_register_read (this_frame,
2035 cache->saved_sp_reg, buf))
2036 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2038 /* Now that we have the base address for the stack frame we can
2039 calculate the value of %esp in the calling frame. */
2040 else if (cache->saved_sp == 0)
2041 cache->saved_sp = cache->base + 8;
2043 /* Adjust all the saved registers such that they contain addresses
2044 instead of offsets. */
2045 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
2046 if (cache->saved_regs[i] != -1)
2047 cache->saved_regs[i] += cache->base;
2052 static struct i386_frame_cache *
2053 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
2055 volatile struct gdb_exception ex;
2056 struct i386_frame_cache *cache;
2061 cache = i386_alloc_frame_cache ();
2062 *this_cache = cache;
2064 TRY_CATCH (ex, RETURN_MASK_ERROR)
2066 i386_frame_cache_1 (this_frame, cache);
2068 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2069 throw_exception (ex);
2075 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
2076 struct frame_id *this_id)
2078 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2081 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2082 else if (cache->base == 0)
2084 /* This marks the outermost frame. */
2088 /* See the end of i386_push_dummy_call. */
2089 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2093 static enum unwind_stop_reason
2094 i386_frame_unwind_stop_reason (struct frame_info *this_frame,
2097 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2100 return UNWIND_UNAVAILABLE;
2102 /* This marks the outermost frame. */
2103 if (cache->base == 0)
2104 return UNWIND_OUTERMOST;
2106 return UNWIND_NO_REASON;
2109 static struct value *
2110 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2113 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2115 gdb_assert (regnum >= 0);
2117 /* The System V ABI says that:
2119 "The flags register contains the system flags, such as the
2120 direction flag and the carry flag. The direction flag must be
2121 set to the forward (that is, zero) direction before entry and
2122 upon exit from a function. Other user flags have no specified
2123 role in the standard calling sequence and are not preserved."
2125 To guarantee the "upon exit" part of that statement we fake a
2126 saved flags register that has its direction flag cleared.
2128 Note that GCC doesn't seem to rely on the fact that the direction
2129 flag is cleared after a function return; it always explicitly
2130 clears the flag before operations where it matters.
2132 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2133 right thing to do. The way we fake the flags register here makes
2134 it impossible to change it. */
2136 if (regnum == I386_EFLAGS_REGNUM)
2140 val = get_frame_register_unsigned (this_frame, regnum);
2142 return frame_unwind_got_constant (this_frame, regnum, val);
2145 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
2146 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
2148 if (regnum == I386_ESP_REGNUM
2149 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1))
2151 /* If the SP has been saved, but we don't know where, then this
2152 means that SAVED_SP_REG register was found unavailable back
2153 when we built the cache. */
2154 if (cache->saved_sp == 0)
2155 return frame_unwind_got_register (this_frame, regnum,
2156 cache->saved_sp_reg);
2158 return frame_unwind_got_constant (this_frame, regnum,
2162 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2163 return frame_unwind_got_memory (this_frame, regnum,
2164 cache->saved_regs[regnum]);
2166 return frame_unwind_got_register (this_frame, regnum, regnum);
2169 static const struct frame_unwind i386_frame_unwind =
2172 i386_frame_unwind_stop_reason,
2174 i386_frame_prev_register,
2176 default_frame_sniffer
2179 /* Normal frames, but in a function epilogue. */
2181 /* The epilogue is defined here as the 'ret' instruction, which will
2182 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2183 the function's stack frame. */
2186 i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2189 struct symtab *symtab;
2191 symtab = find_pc_symtab (pc);
2192 if (symtab && symtab->epilogue_unwind_valid)
2195 if (target_read_memory (pc, &insn, 1))
2196 return 0; /* Can't read memory at pc. */
2198 if (insn != 0xc3) /* 'ret' instruction. */
2205 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
2206 struct frame_info *this_frame,
2207 void **this_prologue_cache)
2209 if (frame_relative_level (this_frame) == 0)
2210 return i386_in_function_epilogue_p (get_frame_arch (this_frame),
2211 get_frame_pc (this_frame));
2216 static struct i386_frame_cache *
2217 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2219 volatile struct gdb_exception ex;
2220 struct i386_frame_cache *cache;
2226 cache = i386_alloc_frame_cache ();
2227 *this_cache = cache;
2229 TRY_CATCH (ex, RETURN_MASK_ERROR)
2231 cache->pc = get_frame_func (this_frame);
2233 /* At this point the stack looks as if we just entered the
2234 function, with the return address at the top of the
2236 sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM);
2237 cache->base = sp + cache->sp_offset;
2238 cache->saved_sp = cache->base + 8;
2239 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
2243 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2244 throw_exception (ex);
2249 static enum unwind_stop_reason
2250 i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2253 struct i386_frame_cache *cache =
2254 i386_epilogue_frame_cache (this_frame, this_cache);
2257 return UNWIND_UNAVAILABLE;
2259 return UNWIND_NO_REASON;
2263 i386_epilogue_frame_this_id (struct frame_info *this_frame,
2265 struct frame_id *this_id)
2267 struct i386_frame_cache *cache =
2268 i386_epilogue_frame_cache (this_frame, this_cache);
2271 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2273 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2276 static struct value *
2277 i386_epilogue_frame_prev_register (struct frame_info *this_frame,
2278 void **this_cache, int regnum)
2280 /* Make sure we've initialized the cache. */
2281 i386_epilogue_frame_cache (this_frame, this_cache);
2283 return i386_frame_prev_register (this_frame, this_cache, regnum);
2286 static const struct frame_unwind i386_epilogue_frame_unwind =
2289 i386_epilogue_frame_unwind_stop_reason,
2290 i386_epilogue_frame_this_id,
2291 i386_epilogue_frame_prev_register,
2293 i386_epilogue_frame_sniffer
2297 /* Stack-based trampolines. */
2299 /* These trampolines are used on cross x86 targets, when taking the
2300 address of a nested function. When executing these trampolines,
2301 no stack frame is set up, so we are in a similar situation as in
2302 epilogues and i386_epilogue_frame_this_id can be re-used. */
2304 /* Static chain passed in register. */
2306 struct i386_insn i386_tramp_chain_in_reg_insns[] =
2308 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2309 { 5, { 0xb8 }, { 0xfe } },
2312 { 5, { 0xe9 }, { 0xff } },
2317 /* Static chain passed on stack (when regparm=3). */
2319 struct i386_insn i386_tramp_chain_on_stack_insns[] =
2322 { 5, { 0x68 }, { 0xff } },
2325 { 5, { 0xe9 }, { 0xff } },
2330 /* Return whether PC points inside a stack trampoline. */
2333 i386_in_stack_tramp_p (CORE_ADDR pc)
2338 /* A stack trampoline is detected if no name is associated
2339 to the current pc and if it points inside a trampoline
2342 find_pc_partial_function (pc, &name, NULL, NULL);
2346 if (target_read_memory (pc, &insn, 1))
2349 if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns)
2350 && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns))
2357 i386_stack_tramp_frame_sniffer (const struct frame_unwind *self,
2358 struct frame_info *this_frame,
2361 if (frame_relative_level (this_frame) == 0)
2362 return i386_in_stack_tramp_p (get_frame_pc (this_frame));
2367 static const struct frame_unwind i386_stack_tramp_frame_unwind =
2370 i386_epilogue_frame_unwind_stop_reason,
2371 i386_epilogue_frame_this_id,
2372 i386_epilogue_frame_prev_register,
2374 i386_stack_tramp_frame_sniffer
2377 /* Generate a bytecode expression to get the value of the saved PC. */
2380 i386_gen_return_address (struct gdbarch *gdbarch,
2381 struct agent_expr *ax, struct axs_value *value,
2384 /* The following sequence assumes the traditional use of the base
2386 ax_reg (ax, I386_EBP_REGNUM);
2388 ax_simple (ax, aop_add);
2389 value->type = register_type (gdbarch, I386_EIP_REGNUM);
2390 value->kind = axs_lvalue_memory;
2394 /* Signal trampolines. */
2396 static struct i386_frame_cache *
2397 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2399 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2400 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2401 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2402 volatile struct gdb_exception ex;
2403 struct i386_frame_cache *cache;
2410 cache = i386_alloc_frame_cache ();
2412 TRY_CATCH (ex, RETURN_MASK_ERROR)
2414 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2415 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
2417 addr = tdep->sigcontext_addr (this_frame);
2418 if (tdep->sc_reg_offset)
2422 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
2424 for (i = 0; i < tdep->sc_num_regs; i++)
2425 if (tdep->sc_reg_offset[i] != -1)
2426 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2430 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
2431 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
2436 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2437 throw_exception (ex);
2439 *this_cache = cache;
2443 static enum unwind_stop_reason
2444 i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2447 struct i386_frame_cache *cache =
2448 i386_sigtramp_frame_cache (this_frame, this_cache);
2451 return UNWIND_UNAVAILABLE;
2453 return UNWIND_NO_REASON;
2457 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
2458 struct frame_id *this_id)
2460 struct i386_frame_cache *cache =
2461 i386_sigtramp_frame_cache (this_frame, this_cache);
2464 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2467 /* See the end of i386_push_dummy_call. */
2468 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
2472 static struct value *
2473 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
2474 void **this_cache, int regnum)
2476 /* Make sure we've initialized the cache. */
2477 i386_sigtramp_frame_cache (this_frame, this_cache);
2479 return i386_frame_prev_register (this_frame, this_cache, regnum);
2483 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
2484 struct frame_info *this_frame,
2485 void **this_prologue_cache)
2487 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2489 /* We shouldn't even bother if we don't have a sigcontext_addr
2491 if (tdep->sigcontext_addr == NULL)
2494 if (tdep->sigtramp_p != NULL)
2496 if (tdep->sigtramp_p (this_frame))
2500 if (tdep->sigtramp_start != 0)
2502 CORE_ADDR pc = get_frame_pc (this_frame);
2504 gdb_assert (tdep->sigtramp_end != 0);
2505 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2512 static const struct frame_unwind i386_sigtramp_frame_unwind =
2515 i386_sigtramp_frame_unwind_stop_reason,
2516 i386_sigtramp_frame_this_id,
2517 i386_sigtramp_frame_prev_register,
2519 i386_sigtramp_frame_sniffer
2524 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
2526 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2531 static const struct frame_base i386_frame_base =
2534 i386_frame_base_address,
2535 i386_frame_base_address,
2536 i386_frame_base_address
2539 static struct frame_id
2540 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2544 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
2546 /* See the end of i386_push_dummy_call. */
2547 return frame_id_build (fp + 8, get_frame_pc (this_frame));
2550 /* _Decimal128 function return values need 16-byte alignment on the
2554 i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2556 return sp & -(CORE_ADDR)16;
2560 /* Figure out where the longjmp will land. Slurp the args out of the
2561 stack. We expect the first arg to be a pointer to the jmp_buf
2562 structure from which we extract the address that we will land at.
2563 This address is copied into PC. This routine returns non-zero on
2567 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2570 CORE_ADDR sp, jb_addr;
2571 struct gdbarch *gdbarch = get_frame_arch (frame);
2572 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2573 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2575 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2576 longjmp will land. */
2577 if (jb_pc_offset == -1)
2580 get_frame_register (frame, I386_ESP_REGNUM, buf);
2581 sp = extract_unsigned_integer (buf, 4, byte_order);
2582 if (target_read_memory (sp + 4, buf, 4))
2585 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
2586 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
2589 *pc = extract_unsigned_integer (buf, 4, byte_order);
2594 /* Check whether TYPE must be 16-byte-aligned when passed as a
2595 function argument. 16-byte vectors, _Decimal128 and structures or
2596 unions containing such types must be 16-byte-aligned; other
2597 arguments are 4-byte-aligned. */
2600 i386_16_byte_align_p (struct type *type)
2602 type = check_typedef (type);
2603 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
2604 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
2605 && TYPE_LENGTH (type) == 16)
2607 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2608 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
2609 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2610 || TYPE_CODE (type) == TYPE_CODE_UNION)
2613 for (i = 0; i < TYPE_NFIELDS (type); i++)
2615 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
2622 /* Implementation for set_gdbarch_push_dummy_code. */
2625 i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
2626 struct value **args, int nargs, struct type *value_type,
2627 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
2628 struct regcache *regcache)
2630 /* Use 0xcc breakpoint - 1 byte. */
2634 /* Keep the stack aligned. */
2639 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2640 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2641 struct value **args, CORE_ADDR sp, int struct_return,
2642 CORE_ADDR struct_addr)
2644 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2650 /* Determine the total space required for arguments and struct
2651 return address in a first pass (allowing for 16-byte-aligned
2652 arguments), then push arguments in a second pass. */
2654 for (write_pass = 0; write_pass < 2; write_pass++)
2656 int args_space_used = 0;
2662 /* Push value address. */
2663 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2664 write_memory (sp, buf, 4);
2665 args_space_used += 4;
2671 for (i = 0; i < nargs; i++)
2673 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2677 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2678 args_space_used = align_up (args_space_used, 16);
2680 write_memory (sp + args_space_used,
2681 value_contents_all (args[i]), len);
2682 /* The System V ABI says that:
2684 "An argument's size is increased, if necessary, to make it a
2685 multiple of [32-bit] words. This may require tail padding,
2686 depending on the size of the argument."
2688 This makes sure the stack stays word-aligned. */
2689 args_space_used += align_up (len, 4);
2693 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2694 args_space = align_up (args_space, 16);
2695 args_space += align_up (len, 4);
2703 /* The original System V ABI only requires word alignment,
2704 but modern incarnations need 16-byte alignment in order
2705 to support SSE. Since wasting a few bytes here isn't
2706 harmful we unconditionally enforce 16-byte alignment. */
2711 /* Store return address. */
2713 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2714 write_memory (sp, buf, 4);
2716 /* Finally, update the stack pointer... */
2717 store_unsigned_integer (buf, 4, byte_order, sp);
2718 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
2720 /* ...and fake a frame pointer. */
2721 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
2723 /* MarkK wrote: This "+ 8" is all over the place:
2724 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2725 i386_dummy_id). It's there, since all frame unwinders for
2726 a given target have to agree (within a certain margin) on the
2727 definition of the stack address of a frame. Otherwise frame id
2728 comparison might not work correctly. Since DWARF2/GCC uses the
2729 stack address *before* the function call as a frame's CFA. On
2730 the i386, when %ebp is used as a frame pointer, the offset
2731 between the contents %ebp and the CFA as defined by GCC. */
2735 /* These registers are used for returning integers (and on some
2736 targets also for returning `struct' and `union' values when their
2737 size and alignment match an integer type). */
2738 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2739 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2741 /* Read, for architecture GDBARCH, a function return value of TYPE
2742 from REGCACHE, and copy that into VALBUF. */
2745 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2746 struct regcache *regcache, gdb_byte *valbuf)
2748 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2749 int len = TYPE_LENGTH (type);
2750 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2752 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2754 if (tdep->st0_regnum < 0)
2756 warning (_("Cannot find floating-point return value."));
2757 memset (valbuf, 0, len);
2761 /* Floating-point return values can be found in %st(0). Convert
2762 its contents to the desired type. This is probably not
2763 exactly how it would happen on the target itself, but it is
2764 the best we can do. */
2765 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2766 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
2770 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2771 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2773 if (len <= low_size)
2775 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2776 memcpy (valbuf, buf, len);
2778 else if (len <= (low_size + high_size))
2780 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2781 memcpy (valbuf, buf, low_size);
2782 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2783 memcpy (valbuf + low_size, buf, len - low_size);
2786 internal_error (__FILE__, __LINE__,
2787 _("Cannot extract return value of %d bytes long."),
2792 /* Write, for architecture GDBARCH, a function return value of TYPE
2793 from VALBUF into REGCACHE. */
2796 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2797 struct regcache *regcache, const gdb_byte *valbuf)
2799 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2800 int len = TYPE_LENGTH (type);
2802 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2805 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2807 if (tdep->st0_regnum < 0)
2809 warning (_("Cannot set floating-point return value."));
2813 /* Returning floating-point values is a bit tricky. Apart from
2814 storing the return value in %st(0), we have to simulate the
2815 state of the FPU at function return point. */
2817 /* Convert the value found in VALBUF to the extended
2818 floating-point format used by the FPU. This is probably
2819 not exactly how it would happen on the target itself, but
2820 it is the best we can do. */
2821 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
2822 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2824 /* Set the top of the floating-point register stack to 7. The
2825 actual value doesn't really matter, but 7 is what a normal
2826 function return would end up with if the program started out
2827 with a freshly initialized FPU. */
2828 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2830 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2832 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2833 the floating-point register stack to 7, the appropriate value
2834 for the tag word is 0x3fff. */
2835 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2839 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2840 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2842 if (len <= low_size)
2843 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2844 else if (len <= (low_size + high_size))
2846 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2847 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
2848 len - low_size, valbuf + low_size);
2851 internal_error (__FILE__, __LINE__,
2852 _("Cannot store return value of %d bytes long."), len);
2857 /* This is the variable that is set with "set struct-convention", and
2858 its legitimate values. */
2859 static const char default_struct_convention[] = "default";
2860 static const char pcc_struct_convention[] = "pcc";
2861 static const char reg_struct_convention[] = "reg";
2862 static const char *const valid_conventions[] =
2864 default_struct_convention,
2865 pcc_struct_convention,
2866 reg_struct_convention,
2869 static const char *struct_convention = default_struct_convention;
2871 /* Return non-zero if TYPE, which is assumed to be a structure,
2872 a union type, or an array type, should be returned in registers
2873 for architecture GDBARCH. */
2876 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2878 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2879 enum type_code code = TYPE_CODE (type);
2880 int len = TYPE_LENGTH (type);
2882 gdb_assert (code == TYPE_CODE_STRUCT
2883 || code == TYPE_CODE_UNION
2884 || code == TYPE_CODE_ARRAY);
2886 if (struct_convention == pcc_struct_convention
2887 || (struct_convention == default_struct_convention
2888 && tdep->struct_return == pcc_struct_return))
2891 /* Structures consisting of a single `float', `double' or 'long
2892 double' member are returned in %st(0). */
2893 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2895 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2896 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2897 return (len == 4 || len == 8 || len == 12);
2900 return (len == 1 || len == 2 || len == 4 || len == 8);
2903 /* Determine, for architecture GDBARCH, how a return value of TYPE
2904 should be returned. If it is supposed to be returned in registers,
2905 and READBUF is non-zero, read the appropriate value from REGCACHE,
2906 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2907 from WRITEBUF into REGCACHE. */
2909 static enum return_value_convention
2910 i386_return_value (struct gdbarch *gdbarch, struct value *function,
2911 struct type *type, struct regcache *regcache,
2912 gdb_byte *readbuf, const gdb_byte *writebuf)
2914 enum type_code code = TYPE_CODE (type);
2916 if (((code == TYPE_CODE_STRUCT
2917 || code == TYPE_CODE_UNION
2918 || code == TYPE_CODE_ARRAY)
2919 && !i386_reg_struct_return_p (gdbarch, type))
2920 /* Complex double and long double uses the struct return covention. */
2921 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16)
2922 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24)
2923 /* 128-bit decimal float uses the struct return convention. */
2924 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2926 /* The System V ABI says that:
2928 "A function that returns a structure or union also sets %eax
2929 to the value of the original address of the caller's area
2930 before it returns. Thus when the caller receives control
2931 again, the address of the returned object resides in register
2932 %eax and can be used to access the object."
2934 So the ABI guarantees that we can always find the return
2935 value just after the function has returned. */
2937 /* Note that the ABI doesn't mention functions returning arrays,
2938 which is something possible in certain languages such as Ada.
2939 In this case, the value is returned as if it was wrapped in
2940 a record, so the convention applied to records also applies
2947 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2948 read_memory (addr, readbuf, TYPE_LENGTH (type));
2951 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2954 /* This special case is for structures consisting of a single
2955 `float', `double' or 'long double' member. These structures are
2956 returned in %st(0). For these structures, we call ourselves
2957 recursively, changing TYPE into the type of the first member of
2958 the structure. Since that should work for all structures that
2959 have only one member, we don't bother to check the member's type
2961 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2963 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2964 return i386_return_value (gdbarch, function, type, regcache,
2969 i386_extract_return_value (gdbarch, type, regcache, readbuf);
2971 i386_store_return_value (gdbarch, type, regcache, writebuf);
2973 return RETURN_VALUE_REGISTER_CONVENTION;
2978 i387_ext_type (struct gdbarch *gdbarch)
2980 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2982 if (!tdep->i387_ext_type)
2984 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
2985 gdb_assert (tdep->i387_ext_type != NULL);
2988 return tdep->i387_ext_type;
2991 /* Construct type for pseudo BND registers. We can't use
2992 tdesc_find_type since a complement of one value has to be used
2993 to describe the upper bound. */
2995 static struct type *
2996 i386_bnd_type (struct gdbarch *gdbarch)
2998 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3001 if (!tdep->i386_bnd_type)
3003 struct type *t, *bound_t;
3004 const struct builtin_type *bt = builtin_type (gdbarch);
3006 /* The type we're building is described bellow: */
3011 void *ubound; /* One complement of raw ubound field. */
3015 t = arch_composite_type (gdbarch,
3016 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT);
3018 append_composite_type_field (t, "lbound", bt->builtin_data_ptr);
3019 append_composite_type_field (t, "ubound", bt->builtin_data_ptr);
3021 TYPE_NAME (t) = "builtin_type_bound128";
3022 tdep->i386_bnd_type = t;
3025 return tdep->i386_bnd_type;
3028 /* Construct vector type for pseudo ZMM registers. We can't use
3029 tdesc_find_type since ZMM isn't described in target description. */
3031 static struct type *
3032 i386_zmm_type (struct gdbarch *gdbarch)
3034 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3036 if (!tdep->i386_zmm_type)
3038 const struct builtin_type *bt = builtin_type (gdbarch);
3040 /* The type we're building is this: */
3042 union __gdb_builtin_type_vec512i
3044 int128_t uint128[4];
3045 int64_t v4_int64[8];
3046 int32_t v8_int32[16];
3047 int16_t v16_int16[32];
3048 int8_t v32_int8[64];
3049 double v4_double[8];
3056 t = arch_composite_type (gdbarch,
3057 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION);
3058 append_composite_type_field (t, "v16_float",
3059 init_vector_type (bt->builtin_float, 16));
3060 append_composite_type_field (t, "v8_double",
3061 init_vector_type (bt->builtin_double, 8));
3062 append_composite_type_field (t, "v64_int8",
3063 init_vector_type (bt->builtin_int8, 64));
3064 append_composite_type_field (t, "v32_int16",
3065 init_vector_type (bt->builtin_int16, 32));
3066 append_composite_type_field (t, "v16_int32",
3067 init_vector_type (bt->builtin_int32, 16));
3068 append_composite_type_field (t, "v8_int64",
3069 init_vector_type (bt->builtin_int64, 8));
3070 append_composite_type_field (t, "v4_int128",
3071 init_vector_type (bt->builtin_int128, 4));
3073 TYPE_VECTOR (t) = 1;
3074 TYPE_NAME (t) = "builtin_type_vec512i";
3075 tdep->i386_zmm_type = t;
3078 return tdep->i386_zmm_type;
3081 /* Construct vector type for pseudo YMM registers. We can't use
3082 tdesc_find_type since YMM isn't described in target description. */
3084 static struct type *
3085 i386_ymm_type (struct gdbarch *gdbarch)
3087 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3089 if (!tdep->i386_ymm_type)
3091 const struct builtin_type *bt = builtin_type (gdbarch);
3093 /* The type we're building is this: */
3095 union __gdb_builtin_type_vec256i
3097 int128_t uint128[2];
3098 int64_t v2_int64[4];
3099 int32_t v4_int32[8];
3100 int16_t v8_int16[16];
3101 int8_t v16_int8[32];
3102 double v2_double[4];
3109 t = arch_composite_type (gdbarch,
3110 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
3111 append_composite_type_field (t, "v8_float",
3112 init_vector_type (bt->builtin_float, 8));
3113 append_composite_type_field (t, "v4_double",
3114 init_vector_type (bt->builtin_double, 4));
3115 append_composite_type_field (t, "v32_int8",
3116 init_vector_type (bt->builtin_int8, 32));
3117 append_composite_type_field (t, "v16_int16",
3118 init_vector_type (bt->builtin_int16, 16));
3119 append_composite_type_field (t, "v8_int32",
3120 init_vector_type (bt->builtin_int32, 8));
3121 append_composite_type_field (t, "v4_int64",
3122 init_vector_type (bt->builtin_int64, 4));
3123 append_composite_type_field (t, "v2_int128",
3124 init_vector_type (bt->builtin_int128, 2));
3126 TYPE_VECTOR (t) = 1;
3127 TYPE_NAME (t) = "builtin_type_vec256i";
3128 tdep->i386_ymm_type = t;
3131 return tdep->i386_ymm_type;
3134 /* Construct vector type for MMX registers. */
3135 static struct type *
3136 i386_mmx_type (struct gdbarch *gdbarch)
3138 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3140 if (!tdep->i386_mmx_type)
3142 const struct builtin_type *bt = builtin_type (gdbarch);
3144 /* The type we're building is this: */
3146 union __gdb_builtin_type_vec64i
3149 int32_t v2_int32[2];
3150 int16_t v4_int16[4];
3157 t = arch_composite_type (gdbarch,
3158 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
3160 append_composite_type_field (t, "uint64", bt->builtin_int64);
3161 append_composite_type_field (t, "v2_int32",
3162 init_vector_type (bt->builtin_int32, 2));
3163 append_composite_type_field (t, "v4_int16",
3164 init_vector_type (bt->builtin_int16, 4));
3165 append_composite_type_field (t, "v8_int8",
3166 init_vector_type (bt->builtin_int8, 8));
3168 TYPE_VECTOR (t) = 1;
3169 TYPE_NAME (t) = "builtin_type_vec64i";
3170 tdep->i386_mmx_type = t;
3173 return tdep->i386_mmx_type;
3176 /* Return the GDB type object for the "standard" data type of data in
3180 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3182 if (i386_bnd_regnum_p (gdbarch, regnum))
3183 return i386_bnd_type (gdbarch);
3184 if (i386_mmx_regnum_p (gdbarch, regnum))
3185 return i386_mmx_type (gdbarch);
3186 else if (i386_ymm_regnum_p (gdbarch, regnum))
3187 return i386_ymm_type (gdbarch);
3188 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3189 return i386_ymm_type (gdbarch);
3190 else if (i386_zmm_regnum_p (gdbarch, regnum))
3191 return i386_zmm_type (gdbarch);
3194 const struct builtin_type *bt = builtin_type (gdbarch);
3195 if (i386_byte_regnum_p (gdbarch, regnum))
3196 return bt->builtin_int8;
3197 else if (i386_word_regnum_p (gdbarch, regnum))
3198 return bt->builtin_int16;
3199 else if (i386_dword_regnum_p (gdbarch, regnum))
3200 return bt->builtin_int32;
3201 else if (i386_k_regnum_p (gdbarch, regnum))
3202 return bt->builtin_int64;
3205 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3208 /* Map a cooked register onto a raw register or memory. For the i386,
3209 the MMX registers need to be mapped onto floating point registers. */
3212 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
3214 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
3219 mmxreg = regnum - tdep->mm0_regnum;
3220 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
3221 tos = (fstat >> 11) & 0x7;
3222 fpreg = (mmxreg + tos) % 8;
3224 return (I387_ST0_REGNUM (tdep) + fpreg);
3227 /* A helper function for us by i386_pseudo_register_read_value and
3228 amd64_pseudo_register_read_value. It does all the work but reads
3229 the data into an already-allocated value. */
3232 i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
3233 struct regcache *regcache,
3235 struct value *result_value)
3237 gdb_byte raw_buf[MAX_REGISTER_SIZE];
3238 enum register_status status;
3239 gdb_byte *buf = value_contents_raw (result_value);
3241 if (i386_mmx_regnum_p (gdbarch, regnum))
3243 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3245 /* Extract (always little endian). */
3246 status = regcache_raw_read (regcache, fpnum, raw_buf);
3247 if (status != REG_VALID)
3248 mark_value_bytes_unavailable (result_value, 0,
3249 TYPE_LENGTH (value_type (result_value)));
3251 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
3255 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3256 if (i386_bnd_regnum_p (gdbarch, regnum))
3258 regnum -= tdep->bnd0_regnum;
3260 /* Extract (always little endian). Read lower 128bits. */
3261 status = regcache_raw_read (regcache,
3262 I387_BND0R_REGNUM (tdep) + regnum,
3264 if (status != REG_VALID)
3265 mark_value_bytes_unavailable (result_value, 0, 16);
3268 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3269 LONGEST upper, lower;
3270 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3272 lower = extract_unsigned_integer (raw_buf, 8, byte_order);
3273 upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order);
3276 memcpy (buf, &lower, size);
3277 memcpy (buf + size, &upper, size);
3280 else if (i386_k_regnum_p (gdbarch, regnum))
3282 regnum -= tdep->k0_regnum;
3284 /* Extract (always little endian). */
3285 status = regcache_raw_read (regcache,
3286 tdep->k0_regnum + regnum,
3288 if (status != REG_VALID)
3289 mark_value_bytes_unavailable (result_value, 0, 8);
3291 memcpy (buf, raw_buf, 8);
3293 else if (i386_zmm_regnum_p (gdbarch, regnum))
3295 regnum -= tdep->zmm0_regnum;
3297 if (regnum < num_lower_zmm_regs)
3299 /* Extract (always little endian). Read lower 128bits. */
3300 status = regcache_raw_read (regcache,
3301 I387_XMM0_REGNUM (tdep) + regnum,
3303 if (status != REG_VALID)
3304 mark_value_bytes_unavailable (result_value, 0, 16);
3306 memcpy (buf, raw_buf, 16);
3308 /* Extract (always little endian). Read upper 128bits. */
3309 status = regcache_raw_read (regcache,
3310 tdep->ymm0h_regnum + regnum,
3312 if (status != REG_VALID)
3313 mark_value_bytes_unavailable (result_value, 16, 16);
3315 memcpy (buf + 16, raw_buf, 16);
3319 /* Extract (always little endian). Read lower 128bits. */
3320 status = regcache_raw_read (regcache,
3321 I387_XMM16_REGNUM (tdep) + regnum
3322 - num_lower_zmm_regs,
3324 if (status != REG_VALID)
3325 mark_value_bytes_unavailable (result_value, 0, 16);
3327 memcpy (buf, raw_buf, 16);
3329 /* Extract (always little endian). Read upper 128bits. */
3330 status = regcache_raw_read (regcache,
3331 I387_YMM16H_REGNUM (tdep) + regnum
3332 - num_lower_zmm_regs,
3334 if (status != REG_VALID)
3335 mark_value_bytes_unavailable (result_value, 16, 16);
3337 memcpy (buf + 16, raw_buf, 16);
3340 /* Read upper 256bits. */
3341 status = regcache_raw_read (regcache,
3342 tdep->zmm0h_regnum + regnum,
3344 if (status != REG_VALID)
3345 mark_value_bytes_unavailable (result_value, 32, 32);
3347 memcpy (buf + 32, raw_buf, 32);
3349 else if (i386_ymm_regnum_p (gdbarch, regnum))
3351 regnum -= tdep->ymm0_regnum;
3353 /* Extract (always little endian). Read lower 128bits. */
3354 status = regcache_raw_read (regcache,
3355 I387_XMM0_REGNUM (tdep) + regnum,
3357 if (status != REG_VALID)
3358 mark_value_bytes_unavailable (result_value, 0, 16);
3360 memcpy (buf, raw_buf, 16);
3361 /* Read upper 128bits. */
3362 status = regcache_raw_read (regcache,
3363 tdep->ymm0h_regnum + regnum,
3365 if (status != REG_VALID)
3366 mark_value_bytes_unavailable (result_value, 16, 32);
3368 memcpy (buf + 16, raw_buf, 16);
3370 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3372 regnum -= tdep->ymm16_regnum;
3373 /* Extract (always little endian). Read lower 128bits. */
3374 status = regcache_raw_read (regcache,
3375 I387_XMM16_REGNUM (tdep) + regnum,
3377 if (status != REG_VALID)
3378 mark_value_bytes_unavailable (result_value, 0, 16);
3380 memcpy (buf, raw_buf, 16);
3381 /* Read upper 128bits. */
3382 status = regcache_raw_read (regcache,
3383 tdep->ymm16h_regnum + regnum,
3385 if (status != REG_VALID)
3386 mark_value_bytes_unavailable (result_value, 16, 16);
3388 memcpy (buf + 16, raw_buf, 16);
3390 else if (i386_word_regnum_p (gdbarch, regnum))
3392 int gpnum = regnum - tdep->ax_regnum;
3394 /* Extract (always little endian). */
3395 status = regcache_raw_read (regcache, gpnum, raw_buf);
3396 if (status != REG_VALID)
3397 mark_value_bytes_unavailable (result_value, 0,
3398 TYPE_LENGTH (value_type (result_value)));
3400 memcpy (buf, raw_buf, 2);
3402 else if (i386_byte_regnum_p (gdbarch, regnum))
3404 /* Check byte pseudo registers last since this function will
3405 be called from amd64_pseudo_register_read, which handles
3406 byte pseudo registers differently. */
3407 int gpnum = regnum - tdep->al_regnum;
3409 /* Extract (always little endian). We read both lower and
3411 status = regcache_raw_read (regcache, gpnum % 4, raw_buf);
3412 if (status != REG_VALID)
3413 mark_value_bytes_unavailable (result_value, 0,
3414 TYPE_LENGTH (value_type (result_value)));
3415 else if (gpnum >= 4)
3416 memcpy (buf, raw_buf + 1, 1);
3418 memcpy (buf, raw_buf, 1);
3421 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3425 static struct value *
3426 i386_pseudo_register_read_value (struct gdbarch *gdbarch,
3427 struct regcache *regcache,
3430 struct value *result;
3432 result = allocate_value (register_type (gdbarch, regnum));
3433 VALUE_LVAL (result) = lval_register;
3434 VALUE_REGNUM (result) = regnum;
3436 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result);
3442 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3443 int regnum, const gdb_byte *buf)
3445 gdb_byte raw_buf[MAX_REGISTER_SIZE];
3447 if (i386_mmx_regnum_p (gdbarch, regnum))
3449 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3452 regcache_raw_read (regcache, fpnum, raw_buf);
3453 /* ... Modify ... (always little endian). */
3454 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
3456 regcache_raw_write (regcache, fpnum, raw_buf);
3460 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3462 if (i386_bnd_regnum_p (gdbarch, regnum))
3464 ULONGEST upper, lower;
3465 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3466 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3468 /* New values from input value. */
3469 regnum -= tdep->bnd0_regnum;
3470 lower = extract_unsigned_integer (buf, size, byte_order);
3471 upper = extract_unsigned_integer (buf + size, size, byte_order);
3473 /* Fetching register buffer. */
3474 regcache_raw_read (regcache,
3475 I387_BND0R_REGNUM (tdep) + regnum,
3480 /* Set register bits. */
3481 memcpy (raw_buf, &lower, 8);
3482 memcpy (raw_buf + 8, &upper, 8);
3485 regcache_raw_write (regcache,
3486 I387_BND0R_REGNUM (tdep) + regnum,
3489 else if (i386_k_regnum_p (gdbarch, regnum))
3491 regnum -= tdep->k0_regnum;
3493 regcache_raw_write (regcache,
3494 tdep->k0_regnum + regnum,
3497 else if (i386_zmm_regnum_p (gdbarch, regnum))
3499 regnum -= tdep->zmm0_regnum;
3501 if (regnum < num_lower_zmm_regs)
3503 /* Write lower 128bits. */
3504 regcache_raw_write (regcache,
3505 I387_XMM0_REGNUM (tdep) + regnum,
3507 /* Write upper 128bits. */
3508 regcache_raw_write (regcache,
3509 I387_YMM0_REGNUM (tdep) + regnum,
3514 /* Write lower 128bits. */
3515 regcache_raw_write (regcache,
3516 I387_XMM16_REGNUM (tdep) + regnum
3517 - num_lower_zmm_regs,
3519 /* Write upper 128bits. */
3520 regcache_raw_write (regcache,
3521 I387_YMM16H_REGNUM (tdep) + regnum
3522 - num_lower_zmm_regs,
3525 /* Write upper 256bits. */
3526 regcache_raw_write (regcache,
3527 tdep->zmm0h_regnum + regnum,
3530 else if (i386_ymm_regnum_p (gdbarch, regnum))
3532 regnum -= tdep->ymm0_regnum;
3534 /* ... Write lower 128bits. */
3535 regcache_raw_write (regcache,
3536 I387_XMM0_REGNUM (tdep) + regnum,
3538 /* ... Write upper 128bits. */
3539 regcache_raw_write (regcache,
3540 tdep->ymm0h_regnum + regnum,
3543 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3545 regnum -= tdep->ymm16_regnum;
3547 /* ... Write lower 128bits. */
3548 regcache_raw_write (regcache,
3549 I387_XMM16_REGNUM (tdep) + regnum,
3551 /* ... Write upper 128bits. */
3552 regcache_raw_write (regcache,
3553 tdep->ymm16h_regnum + regnum,
3556 else if (i386_word_regnum_p (gdbarch, regnum))
3558 int gpnum = regnum - tdep->ax_regnum;
3561 regcache_raw_read (regcache, gpnum, raw_buf);
3562 /* ... Modify ... (always little endian). */
3563 memcpy (raw_buf, buf, 2);
3565 regcache_raw_write (regcache, gpnum, raw_buf);
3567 else if (i386_byte_regnum_p (gdbarch, regnum))
3569 /* Check byte pseudo registers last since this function will
3570 be called from amd64_pseudo_register_read, which handles
3571 byte pseudo registers differently. */
3572 int gpnum = regnum - tdep->al_regnum;
3574 /* Read ... We read both lower and upper registers. */
3575 regcache_raw_read (regcache, gpnum % 4, raw_buf);
3576 /* ... Modify ... (always little endian). */
3578 memcpy (raw_buf + 1, buf, 1);
3580 memcpy (raw_buf, buf, 1);
3582 regcache_raw_write (regcache, gpnum % 4, raw_buf);
3585 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3590 /* Return the register number of the register allocated by GCC after
3591 REGNUM, or -1 if there is no such register. */
3594 i386_next_regnum (int regnum)
3596 /* GCC allocates the registers in the order:
3598 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3600 Since storing a variable in %esp doesn't make any sense we return
3601 -1 for %ebp and for %esp itself. */
3602 static int next_regnum[] =
3604 I386_EDX_REGNUM, /* Slot for %eax. */
3605 I386_EBX_REGNUM, /* Slot for %ecx. */
3606 I386_ECX_REGNUM, /* Slot for %edx. */
3607 I386_ESI_REGNUM, /* Slot for %ebx. */
3608 -1, -1, /* Slots for %esp and %ebp. */
3609 I386_EDI_REGNUM, /* Slot for %esi. */
3610 I386_EBP_REGNUM /* Slot for %edi. */
3613 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
3614 return next_regnum[regnum];
3619 /* Return nonzero if a value of type TYPE stored in register REGNUM
3620 needs any special handling. */
3623 i386_convert_register_p (struct gdbarch *gdbarch,
3624 int regnum, struct type *type)
3626 int len = TYPE_LENGTH (type);
3628 /* Values may be spread across multiple registers. Most debugging
3629 formats aren't expressive enough to specify the locations, so
3630 some heuristics is involved. Right now we only handle types that
3631 have a length that is a multiple of the word size, since GCC
3632 doesn't seem to put any other types into registers. */
3633 if (len > 4 && len % 4 == 0)
3635 int last_regnum = regnum;
3639 last_regnum = i386_next_regnum (last_regnum);
3643 if (last_regnum != -1)
3647 return i387_convert_register_p (gdbarch, regnum, type);
3650 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3651 return its contents in TO. */
3654 i386_register_to_value (struct frame_info *frame, int regnum,
3655 struct type *type, gdb_byte *to,
3656 int *optimizedp, int *unavailablep)
3658 struct gdbarch *gdbarch = get_frame_arch (frame);
3659 int len = TYPE_LENGTH (type);
3661 if (i386_fp_regnum_p (gdbarch, regnum))
3662 return i387_register_to_value (frame, regnum, type, to,
3663 optimizedp, unavailablep);
3665 /* Read a value spread across multiple registers. */
3667 gdb_assert (len > 4 && len % 4 == 0);
3671 gdb_assert (regnum != -1);
3672 gdb_assert (register_size (gdbarch, regnum) == 4);
3674 if (!get_frame_register_bytes (frame, regnum, 0,
3675 register_size (gdbarch, regnum),
3676 to, optimizedp, unavailablep))
3679 regnum = i386_next_regnum (regnum);
3684 *optimizedp = *unavailablep = 0;
3688 /* Write the contents FROM of a value of type TYPE into register
3689 REGNUM in frame FRAME. */
3692 i386_value_to_register (struct frame_info *frame, int regnum,
3693 struct type *type, const gdb_byte *from)
3695 int len = TYPE_LENGTH (type);
3697 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
3699 i387_value_to_register (frame, regnum, type, from);
3703 /* Write a value spread across multiple registers. */
3705 gdb_assert (len > 4 && len % 4 == 0);
3709 gdb_assert (regnum != -1);
3710 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
3712 put_frame_register (frame, regnum, from);
3713 regnum = i386_next_regnum (regnum);
3719 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3720 in the general-purpose register set REGSET to register cache
3721 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3724 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
3725 int regnum, const void *gregs, size_t len)
3727 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3728 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3729 const gdb_byte *regs = gregs;
3732 gdb_assert (len == tdep->sizeof_gregset);
3734 for (i = 0; i < tdep->gregset_num_regs; i++)
3736 if ((regnum == i || regnum == -1)
3737 && tdep->gregset_reg_offset[i] != -1)
3738 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
3742 /* Collect register REGNUM from the register cache REGCACHE and store
3743 it in the buffer specified by GREGS and LEN as described by the
3744 general-purpose register set REGSET. If REGNUM is -1, do this for
3745 all registers in REGSET. */
3748 i386_collect_gregset (const struct regset *regset,
3749 const struct regcache *regcache,
3750 int regnum, void *gregs, size_t len)
3752 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3753 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3754 gdb_byte *regs = gregs;
3757 gdb_assert (len == tdep->sizeof_gregset);
3759 for (i = 0; i < tdep->gregset_num_regs; i++)
3761 if ((regnum == i || regnum == -1)
3762 && tdep->gregset_reg_offset[i] != -1)
3763 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
3767 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3768 in the floating-point register set REGSET to register cache
3769 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3772 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
3773 int regnum, const void *fpregs, size_t len)
3775 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3776 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3778 if (len == I387_SIZEOF_FXSAVE)
3780 i387_supply_fxsave (regcache, regnum, fpregs);
3784 gdb_assert (len == tdep->sizeof_fpregset);
3785 i387_supply_fsave (regcache, regnum, fpregs);
3788 /* Collect register REGNUM from the register cache REGCACHE and store
3789 it in the buffer specified by FPREGS and LEN as described by the
3790 floating-point register set REGSET. If REGNUM is -1, do this for
3791 all registers in REGSET. */
3794 i386_collect_fpregset (const struct regset *regset,
3795 const struct regcache *regcache,
3796 int regnum, void *fpregs, size_t len)
3798 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3799 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3801 if (len == I387_SIZEOF_FXSAVE)
3803 i387_collect_fxsave (regcache, regnum, fpregs);
3807 gdb_assert (len == tdep->sizeof_fpregset);
3808 i387_collect_fsave (regcache, regnum, fpregs);
3811 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
3814 i386_supply_xstateregset (const struct regset *regset,
3815 struct regcache *regcache, int regnum,
3816 const void *xstateregs, size_t len)
3818 i387_supply_xsave (regcache, regnum, xstateregs);
3821 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
3824 i386_collect_xstateregset (const struct regset *regset,
3825 const struct regcache *regcache,
3826 int regnum, void *xstateregs, size_t len)
3828 i387_collect_xsave (regcache, regnum, xstateregs, 1);
3831 /* Return the appropriate register set for the core section identified
3832 by SECT_NAME and SECT_SIZE. */
3834 const struct regset *
3835 i386_regset_from_core_section (struct gdbarch *gdbarch,
3836 const char *sect_name, size_t sect_size)
3838 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3840 if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset)
3842 if (tdep->gregset == NULL)
3843 tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset,
3844 i386_collect_gregset);
3845 return tdep->gregset;
3848 if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
3849 || (strcmp (sect_name, ".reg-xfp") == 0
3850 && sect_size == I387_SIZEOF_FXSAVE))
3852 if (tdep->fpregset == NULL)
3853 tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset,
3854 i386_collect_fpregset);
3855 return tdep->fpregset;
3858 if (strcmp (sect_name, ".reg-xstate") == 0)
3860 if (tdep->xstateregset == NULL)
3861 tdep->xstateregset = regset_alloc (gdbarch,
3862 i386_supply_xstateregset,
3863 i386_collect_xstateregset);
3865 return tdep->xstateregset;
3872 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3875 i386_pe_skip_trampoline_code (struct frame_info *frame,
3876 CORE_ADDR pc, char *name)
3878 struct gdbarch *gdbarch = get_frame_arch (frame);
3879 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3882 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
3884 unsigned long indirect =
3885 read_memory_unsigned_integer (pc + 2, 4, byte_order);
3886 struct minimal_symbol *indsym =
3887 indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0;
3888 const char *symname = indsym ? MSYMBOL_LINKAGE_NAME (indsym) : 0;
3892 if (strncmp (symname, "__imp_", 6) == 0
3893 || strncmp (symname, "_imp_", 5) == 0)
3895 read_memory_unsigned_integer (indirect, 4, byte_order);
3898 return 0; /* Not a trampoline. */
3902 /* Return whether the THIS_FRAME corresponds to a sigtramp
3906 i386_sigtramp_p (struct frame_info *this_frame)
3908 CORE_ADDR pc = get_frame_pc (this_frame);
3911 find_pc_partial_function (pc, &name, NULL, NULL);
3912 return (name && strcmp ("_sigtramp", name) == 0);
3916 /* We have two flavours of disassembly. The machinery on this page
3917 deals with switching between those. */
3920 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
3922 gdb_assert (disassembly_flavor == att_flavor
3923 || disassembly_flavor == intel_flavor);
3925 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3926 constified, cast to prevent a compiler warning. */
3927 info->disassembler_options = (char *) disassembly_flavor;
3929 return print_insn_i386 (pc, info);
3933 /* There are a few i386 architecture variants that differ only
3934 slightly from the generic i386 target. For now, we don't give them
3935 their own source file, but include them here. As a consequence,
3936 they'll always be included. */
3938 /* System V Release 4 (SVR4). */
3940 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3944 i386_svr4_sigtramp_p (struct frame_info *this_frame)
3946 CORE_ADDR pc = get_frame_pc (this_frame);
3949 /* The origin of these symbols is currently unknown. */
3950 find_pc_partial_function (pc, &name, NULL, NULL);
3951 return (name && (strcmp ("_sigreturn", name) == 0
3952 || strcmp ("sigvechandler", name) == 0));
3955 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3956 address of the associated sigcontext (ucontext) structure. */
3959 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
3961 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3962 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3966 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
3967 sp = extract_unsigned_integer (buf, 4, byte_order);
3969 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
3974 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
3978 i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s)
3980 return (*s == '$' /* Literal number. */
3981 || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */
3982 || (*s == '(' && s[1] == '%') /* Register indirection. */
3983 || (*s == '%' && isalpha (s[1]))); /* Register access. */
3986 /* Helper function for i386_stap_parse_special_token.
3988 This function parses operands of the form `-8+3+1(%rbp)', which
3989 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
3991 Return 1 if the operand was parsed successfully, zero
3995 i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch,
3996 struct stap_parse_info *p)
3998 const char *s = p->arg;
4000 if (isdigit (*s) || *s == '-' || *s == '+')
4004 long displacements[3];
4020 if (!isdigit ((unsigned char) *s))
4023 displacements[0] = strtol (s, &endp, 10);
4026 if (*s != '+' && *s != '-')
4028 /* We are not dealing with a triplet. */
4041 if (!isdigit ((unsigned char) *s))
4044 displacements[1] = strtol (s, &endp, 10);
4047 if (*s != '+' && *s != '-')
4049 /* We are not dealing with a triplet. */
4062 if (!isdigit ((unsigned char) *s))
4065 displacements[2] = strtol (s, &endp, 10);
4068 if (*s != '(' || s[1] != '%')
4074 while (isalnum (*s))
4080 len = s - start - 1;
4081 regname = alloca (len + 1);
4083 strncpy (regname, start, len);
4084 regname[len] = '\0';
4086 if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1)
4087 error (_("Invalid register name `%s' on expression `%s'."),
4088 regname, p->saved_arg);
4090 for (i = 0; i < 3; i++)
4092 write_exp_elt_opcode (&p->pstate, OP_LONG);
4094 (&p->pstate, builtin_type (gdbarch)->builtin_long);
4095 write_exp_elt_longcst (&p->pstate, displacements[i]);
4096 write_exp_elt_opcode (&p->pstate, OP_LONG);
4098 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4101 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4104 write_exp_string (&p->pstate, str);
4105 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4107 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4108 write_exp_elt_type (&p->pstate,
4109 builtin_type (gdbarch)->builtin_data_ptr);
4110 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4112 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4113 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4114 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4116 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4117 write_exp_elt_type (&p->pstate,
4118 lookup_pointer_type (p->arg_type));
4119 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4121 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4131 /* Helper function for i386_stap_parse_special_token.
4133 This function parses operands of the form `register base +
4134 (register index * size) + offset', as represented in
4135 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4137 Return 1 if the operand was parsed successfully, zero
4141 i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch,
4142 struct stap_parse_info *p)
4144 const char *s = p->arg;
4146 if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+')
4148 int offset_minus = 0;
4157 struct stoken base_token, index_token;
4167 if (offset_minus && !isdigit (*s))
4174 offset = strtol (s, &endp, 10);
4178 if (*s != '(' || s[1] != '%')
4184 while (isalnum (*s))
4187 if (*s != ',' || s[1] != '%')
4190 len_base = s - start;
4191 base = alloca (len_base + 1);
4192 strncpy (base, start, len_base);
4193 base[len_base] = '\0';
4195 if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1)
4196 error (_("Invalid register name `%s' on expression `%s'."),
4197 base, p->saved_arg);
4202 while (isalnum (*s))
4205 len_index = s - start;
4206 index = alloca (len_index + 1);
4207 strncpy (index, start, len_index);
4208 index[len_index] = '\0';
4210 if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1)
4211 error (_("Invalid register name `%s' on expression `%s'."),
4212 index, p->saved_arg);
4214 if (*s != ',' && *s != ')')
4230 size = strtol (s, &endp, 10);
4241 write_exp_elt_opcode (&p->pstate, OP_LONG);
4242 write_exp_elt_type (&p->pstate,
4243 builtin_type (gdbarch)->builtin_long);
4244 write_exp_elt_longcst (&p->pstate, offset);
4245 write_exp_elt_opcode (&p->pstate, OP_LONG);
4247 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4250 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4251 base_token.ptr = base;
4252 base_token.length = len_base;
4253 write_exp_string (&p->pstate, base_token);
4254 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4257 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4259 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4260 index_token.ptr = index;
4261 index_token.length = len_index;
4262 write_exp_string (&p->pstate, index_token);
4263 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4267 write_exp_elt_opcode (&p->pstate, OP_LONG);
4268 write_exp_elt_type (&p->pstate,
4269 builtin_type (gdbarch)->builtin_long);
4270 write_exp_elt_longcst (&p->pstate, size);
4271 write_exp_elt_opcode (&p->pstate, OP_LONG);
4273 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4274 write_exp_elt_opcode (&p->pstate, BINOP_MUL);
4277 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4279 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4280 write_exp_elt_type (&p->pstate,
4281 lookup_pointer_type (p->arg_type));
4282 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4284 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4294 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4298 i386_stap_parse_special_token (struct gdbarch *gdbarch,
4299 struct stap_parse_info *p)
4301 /* In order to parse special tokens, we use a state-machine that go
4302 through every known token and try to get a match. */
4306 THREE_ARG_DISPLACEMENT,
4310 current_state = TRIPLET;
4312 /* The special tokens to be parsed here are:
4314 - `register base + (register index * size) + offset', as represented
4315 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4317 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4318 `*(-8 + 3 - 1 + (void *) $eax)'. */
4320 while (current_state != DONE)
4322 switch (current_state)
4325 if (i386_stap_parse_special_token_triplet (gdbarch, p))
4329 case THREE_ARG_DISPLACEMENT:
4330 if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p))
4335 /* Advancing to the next state. */
4347 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4349 static const char *const stap_integer_prefixes[] = { "$", NULL };
4350 static const char *const stap_register_prefixes[] = { "%", NULL };
4351 static const char *const stap_register_indirection_prefixes[] = { "(",
4353 static const char *const stap_register_indirection_suffixes[] = { ")",
4356 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4357 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4359 /* Registering SystemTap handlers. */
4360 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
4361 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
4362 set_gdbarch_stap_register_indirection_prefixes (gdbarch,
4363 stap_register_indirection_prefixes);
4364 set_gdbarch_stap_register_indirection_suffixes (gdbarch,
4365 stap_register_indirection_suffixes);
4366 set_gdbarch_stap_is_single_operand (gdbarch,
4367 i386_stap_is_single_operand);
4368 set_gdbarch_stap_parse_special_token (gdbarch,
4369 i386_stap_parse_special_token);
4372 /* System V Release 4 (SVR4). */
4375 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4377 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4379 /* System V Release 4 uses ELF. */
4380 i386_elf_init_abi (info, gdbarch);
4382 /* System V Release 4 has shared libraries. */
4383 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
4385 tdep->sigtramp_p = i386_svr4_sigtramp_p;
4386 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
4387 tdep->sc_pc_offset = 36 + 14 * 4;
4388 tdep->sc_sp_offset = 36 + 17 * 4;
4390 tdep->jb_pc_offset = 20;
4396 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4398 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4400 /* DJGPP doesn't have any special frames for signal handlers. */
4401 tdep->sigtramp_p = NULL;
4403 tdep->jb_pc_offset = 36;
4405 /* DJGPP does not support the SSE registers. */
4406 if (! tdesc_has_registers (info.target_desc))
4407 tdep->tdesc = tdesc_i386_mmx;
4409 /* Native compiler is GCC, which uses the SVR4 register numbering
4410 even in COFF and STABS. See the comment in i386_gdbarch_init,
4411 before the calls to set_gdbarch_stab_reg_to_regnum and
4412 set_gdbarch_sdb_reg_to_regnum. */
4413 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4414 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4416 set_gdbarch_has_dos_based_file_system (gdbarch, 1);
4420 /* i386 register groups. In addition to the normal groups, add "mmx"
4423 static struct reggroup *i386_sse_reggroup;
4424 static struct reggroup *i386_mmx_reggroup;
4427 i386_init_reggroups (void)
4429 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
4430 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
4434 i386_add_reggroups (struct gdbarch *gdbarch)
4436 reggroup_add (gdbarch, i386_sse_reggroup);
4437 reggroup_add (gdbarch, i386_mmx_reggroup);
4438 reggroup_add (gdbarch, general_reggroup);
4439 reggroup_add (gdbarch, float_reggroup);
4440 reggroup_add (gdbarch, all_reggroup);
4441 reggroup_add (gdbarch, save_reggroup);
4442 reggroup_add (gdbarch, restore_reggroup);
4443 reggroup_add (gdbarch, vector_reggroup);
4444 reggroup_add (gdbarch, system_reggroup);
4448 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
4449 struct reggroup *group)
4451 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4452 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
4453 ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p,
4454 bndr_regnum_p, bnd_regnum_p, k_regnum_p, zmm_regnum_p, zmmh_regnum_p,
4455 zmm_avx512_regnum_p, mpx_ctrl_regnum_p, xmm_avx512_regnum_p,
4456 avx512_p, avx_p, sse_p;
4458 /* Don't include pseudo registers, except for MMX, in any register
4460 if (i386_byte_regnum_p (gdbarch, regnum))
4463 if (i386_word_regnum_p (gdbarch, regnum))
4466 if (i386_dword_regnum_p (gdbarch, regnum))
4469 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
4470 if (group == i386_mmx_reggroup)
4471 return mmx_regnum_p;
4473 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
4474 xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum);
4475 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
4476 if (group == i386_sse_reggroup)
4477 return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p;
4479 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
4480 ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum);
4481 zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum);
4483 avx512_p = ((tdep->xcr0 & I386_XSTATE_AVX512_MASK)
4484 == I386_XSTATE_AVX512_MASK);
4485 avx_p = ((tdep->xcr0 & I386_XSTATE_AVX512_MASK)
4486 == I386_XSTATE_AVX_MASK) && !avx512_p;
4487 sse_p = ((tdep->xcr0 & I386_XSTATE_AVX512_MASK)
4488 == I386_XSTATE_SSE_MASK) && !avx512_p && ! avx_p;
4490 if (group == vector_reggroup)
4491 return (mmx_regnum_p
4492 || (zmm_regnum_p && avx512_p)
4493 || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p)
4494 || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p)
4497 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
4498 || i386_fpc_regnum_p (gdbarch, regnum));
4499 if (group == float_reggroup)
4502 /* For "info reg all", don't include upper YMM registers nor XMM
4503 registers when AVX is supported. */
4504 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
4505 ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum);
4506 zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum);
4507 if (group == all_reggroup
4508 && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p)
4509 || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p)
4511 || ymmh_avx512_regnum_p
4515 bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum);
4516 if (group == all_reggroup
4517 && ((bnd_regnum_p && (tdep->xcr0 & I386_XSTATE_MPX_MASK))))
4518 return bnd_regnum_p;
4520 bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum);
4521 if (group == all_reggroup
4522 && ((bndr_regnum_p && (tdep->xcr0 & I386_XSTATE_MPX_MASK))))
4525 mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum);
4526 if (group == all_reggroup
4527 && ((mpx_ctrl_regnum_p && (tdep->xcr0 & I386_XSTATE_MPX_MASK))))
4528 return mpx_ctrl_regnum_p;
4530 if (group == general_reggroup)
4531 return (!fp_regnum_p
4535 && !xmm_avx512_regnum_p
4538 && !ymm_avx512_regnum_p
4539 && !ymmh_avx512_regnum_p
4542 && !mpx_ctrl_regnum_p
4546 return default_register_reggroup_p (gdbarch, regnum, group);
4550 /* Get the ARGIth function argument for the current function. */
4553 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
4556 struct gdbarch *gdbarch = get_frame_arch (frame);
4557 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4558 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
4559 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
4563 i386_skip_permanent_breakpoint (struct regcache *regcache)
4565 CORE_ADDR current_pc = regcache_read_pc (regcache);
4567 /* On i386, breakpoint is exactly 1 byte long, so we just
4568 adjust the PC in the regcache. */
4570 regcache_write_pc (regcache, current_pc);
4574 #define PREFIX_REPZ 0x01
4575 #define PREFIX_REPNZ 0x02
4576 #define PREFIX_LOCK 0x04
4577 #define PREFIX_DATA 0x08
4578 #define PREFIX_ADDR 0x10
4590 /* i386 arith/logic operations */
4603 struct i386_record_s
4605 struct gdbarch *gdbarch;
4606 struct regcache *regcache;
4607 CORE_ADDR orig_addr;
4613 uint8_t mod, reg, rm;
4622 /* Parse the "modrm" part of the memory address irp->addr points at.
4623 Returns -1 if something goes wrong, 0 otherwise. */
4626 i386_record_modrm (struct i386_record_s *irp)
4628 struct gdbarch *gdbarch = irp->gdbarch;
4630 if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1))
4634 irp->mod = (irp->modrm >> 6) & 3;
4635 irp->reg = (irp->modrm >> 3) & 7;
4636 irp->rm = irp->modrm & 7;
4641 /* Extract the memory address that the current instruction writes to,
4642 and return it in *ADDR. Return -1 if something goes wrong. */
4645 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
4647 struct gdbarch *gdbarch = irp->gdbarch;
4648 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4653 if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM])
4660 uint8_t base = irp->rm;
4665 if (record_read_memory (gdbarch, irp->addr, &byte, 1))
4668 scale = (byte >> 6) & 3;
4669 index = ((byte >> 3) & 7) | irp->rex_x;
4677 if ((base & 7) == 5)
4680 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4683 *addr = extract_signed_integer (buf, 4, byte_order);
4684 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
4685 *addr += irp->addr + irp->rip_offset;
4689 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4692 *addr = (int8_t) buf[0];
4695 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4697 *addr = extract_signed_integer (buf, 4, byte_order);
4705 if (base == 4 && irp->popl_esp_hack)
4706 *addr += irp->popl_esp_hack;
4707 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
4710 if (irp->aflag == 2)
4715 *addr = (uint32_t) (offset64 + *addr);
4717 if (havesib && (index != 4 || scale != 0))
4719 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
4721 if (irp->aflag == 2)
4722 *addr += offset64 << scale;
4724 *addr = (uint32_t) (*addr + (offset64 << scale));
4729 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4730 address from 32-bit to 64-bit. */
4731 *addr = (uint32_t) *addr;
4742 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4745 *addr = extract_signed_integer (buf, 2, byte_order);
4751 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4754 *addr = (int8_t) buf[0];
4757 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4760 *addr = extract_signed_integer (buf, 2, byte_order);
4767 regcache_raw_read_unsigned (irp->regcache,
4768 irp->regmap[X86_RECORD_REBX_REGNUM],
4770 *addr = (uint32_t) (*addr + offset64);
4771 regcache_raw_read_unsigned (irp->regcache,
4772 irp->regmap[X86_RECORD_RESI_REGNUM],
4774 *addr = (uint32_t) (*addr + offset64);
4777 regcache_raw_read_unsigned (irp->regcache,
4778 irp->regmap[X86_RECORD_REBX_REGNUM],
4780 *addr = (uint32_t) (*addr + offset64);
4781 regcache_raw_read_unsigned (irp->regcache,
4782 irp->regmap[X86_RECORD_REDI_REGNUM],
4784 *addr = (uint32_t) (*addr + offset64);
4787 regcache_raw_read_unsigned (irp->regcache,
4788 irp->regmap[X86_RECORD_REBP_REGNUM],
4790 *addr = (uint32_t) (*addr + offset64);
4791 regcache_raw_read_unsigned (irp->regcache,
4792 irp->regmap[X86_RECORD_RESI_REGNUM],
4794 *addr = (uint32_t) (*addr + offset64);
4797 regcache_raw_read_unsigned (irp->regcache,
4798 irp->regmap[X86_RECORD_REBP_REGNUM],
4800 *addr = (uint32_t) (*addr + offset64);
4801 regcache_raw_read_unsigned (irp->regcache,
4802 irp->regmap[X86_RECORD_REDI_REGNUM],
4804 *addr = (uint32_t) (*addr + offset64);
4807 regcache_raw_read_unsigned (irp->regcache,
4808 irp->regmap[X86_RECORD_RESI_REGNUM],
4810 *addr = (uint32_t) (*addr + offset64);
4813 regcache_raw_read_unsigned (irp->regcache,
4814 irp->regmap[X86_RECORD_REDI_REGNUM],
4816 *addr = (uint32_t) (*addr + offset64);
4819 regcache_raw_read_unsigned (irp->regcache,
4820 irp->regmap[X86_RECORD_REBP_REGNUM],
4822 *addr = (uint32_t) (*addr + offset64);
4825 regcache_raw_read_unsigned (irp->regcache,
4826 irp->regmap[X86_RECORD_REBX_REGNUM],
4828 *addr = (uint32_t) (*addr + offset64);
4838 /* Record the address and contents of the memory that will be changed
4839 by the current instruction. Return -1 if something goes wrong, 0
4843 i386_record_lea_modrm (struct i386_record_s *irp)
4845 struct gdbarch *gdbarch = irp->gdbarch;
4848 if (irp->override >= 0)
4850 if (record_full_memory_query)
4854 target_terminal_ours ();
4856 Process record ignores the memory change of instruction at address %s\n\
4857 because it can't get the value of the segment register.\n\
4858 Do you want to stop the program?"),
4859 paddress (gdbarch, irp->orig_addr));
4860 target_terminal_inferior ();
4868 if (i386_record_lea_modrm_addr (irp, &addr))
4871 if (record_full_arch_list_add_mem (addr, 1 << irp->ot))
4877 /* Record the effects of a push operation. Return -1 if something
4878 goes wrong, 0 otherwise. */
4881 i386_record_push (struct i386_record_s *irp, int size)
4885 if (record_full_arch_list_add_reg (irp->regcache,
4886 irp->regmap[X86_RECORD_RESP_REGNUM]))
4888 regcache_raw_read_unsigned (irp->regcache,
4889 irp->regmap[X86_RECORD_RESP_REGNUM],
4891 if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size))
4898 /* Defines contents to record. */
4899 #define I386_SAVE_FPU_REGS 0xfffd
4900 #define I386_SAVE_FPU_ENV 0xfffe
4901 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4903 /* Record the values of the floating point registers which will be
4904 changed by the current instruction. Returns -1 if something is
4905 wrong, 0 otherwise. */
4907 static int i386_record_floats (struct gdbarch *gdbarch,
4908 struct i386_record_s *ir,
4911 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4914 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4915 happen. Currently we store st0-st7 registers, but we need not store all
4916 registers all the time, in future we use ftag register and record only
4917 those who are not marked as an empty. */
4919 if (I386_SAVE_FPU_REGS == iregnum)
4921 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
4923 if (record_full_arch_list_add_reg (ir->regcache, i))
4927 else if (I386_SAVE_FPU_ENV == iregnum)
4929 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4931 if (record_full_arch_list_add_reg (ir->regcache, i))
4935 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
4937 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4939 if (record_full_arch_list_add_reg (ir->regcache, i))
4943 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
4944 (iregnum <= I387_FOP_REGNUM (tdep)))
4946 if (record_full_arch_list_add_reg (ir->regcache,iregnum))
4951 /* Parameter error. */
4954 if(I386_SAVE_FPU_ENV != iregnum)
4956 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4958 if (record_full_arch_list_add_reg (ir->regcache, i))
4965 /* Parse the current instruction, and record the values of the
4966 registers and memory that will be changed by the current
4967 instruction. Returns -1 if something goes wrong, 0 otherwise. */
4969 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
4970 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
4973 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
4974 CORE_ADDR input_addr)
4976 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4982 gdb_byte buf[MAX_REGISTER_SIZE];
4983 struct i386_record_s ir;
4984 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4988 memset (&ir, 0, sizeof (struct i386_record_s));
4989 ir.regcache = regcache;
4990 ir.addr = input_addr;
4991 ir.orig_addr = input_addr;
4995 ir.popl_esp_hack = 0;
4996 ir.regmap = tdep->record_regmap;
4997 ir.gdbarch = gdbarch;
4999 if (record_debug > 1)
5000 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
5002 paddress (gdbarch, ir.addr));
5007 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5010 switch (opcode8) /* Instruction prefixes */
5012 case REPE_PREFIX_OPCODE:
5013 prefixes |= PREFIX_REPZ;
5015 case REPNE_PREFIX_OPCODE:
5016 prefixes |= PREFIX_REPNZ;
5018 case LOCK_PREFIX_OPCODE:
5019 prefixes |= PREFIX_LOCK;
5021 case CS_PREFIX_OPCODE:
5022 ir.override = X86_RECORD_CS_REGNUM;
5024 case SS_PREFIX_OPCODE:
5025 ir.override = X86_RECORD_SS_REGNUM;
5027 case DS_PREFIX_OPCODE:
5028 ir.override = X86_RECORD_DS_REGNUM;
5030 case ES_PREFIX_OPCODE:
5031 ir.override = X86_RECORD_ES_REGNUM;
5033 case FS_PREFIX_OPCODE:
5034 ir.override = X86_RECORD_FS_REGNUM;
5036 case GS_PREFIX_OPCODE:
5037 ir.override = X86_RECORD_GS_REGNUM;
5039 case DATA_PREFIX_OPCODE:
5040 prefixes |= PREFIX_DATA;
5042 case ADDR_PREFIX_OPCODE:
5043 prefixes |= PREFIX_ADDR;
5045 case 0x40: /* i386 inc %eax */
5046 case 0x41: /* i386 inc %ecx */
5047 case 0x42: /* i386 inc %edx */
5048 case 0x43: /* i386 inc %ebx */
5049 case 0x44: /* i386 inc %esp */
5050 case 0x45: /* i386 inc %ebp */
5051 case 0x46: /* i386 inc %esi */
5052 case 0x47: /* i386 inc %edi */
5053 case 0x48: /* i386 dec %eax */
5054 case 0x49: /* i386 dec %ecx */
5055 case 0x4a: /* i386 dec %edx */
5056 case 0x4b: /* i386 dec %ebx */
5057 case 0x4c: /* i386 dec %esp */
5058 case 0x4d: /* i386 dec %ebp */
5059 case 0x4e: /* i386 dec %esi */
5060 case 0x4f: /* i386 dec %edi */
5061 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
5064 rex_w = (opcode8 >> 3) & 1;
5065 rex_r = (opcode8 & 0x4) << 1;
5066 ir.rex_x = (opcode8 & 0x2) << 2;
5067 ir.rex_b = (opcode8 & 0x1) << 3;
5069 else /* 32 bit target */
5078 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
5084 if (prefixes & PREFIX_DATA)
5087 if (prefixes & PREFIX_ADDR)
5089 else if (ir.regmap[X86_RECORD_R8_REGNUM])
5092 /* Now check op code. */
5093 opcode = (uint32_t) opcode8;
5098 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5101 opcode = (uint32_t) opcode8 | 0x0f00;
5105 case 0x00: /* arith & logic */
5153 if (((opcode >> 3) & 7) != OP_CMPL)
5155 if ((opcode & 1) == 0)
5158 ir.ot = ir.dflag + OT_WORD;
5160 switch ((opcode >> 1) & 3)
5162 case 0: /* OP Ev, Gv */
5163 if (i386_record_modrm (&ir))
5167 if (i386_record_lea_modrm (&ir))
5173 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5175 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5178 case 1: /* OP Gv, Ev */
5179 if (i386_record_modrm (&ir))
5182 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5184 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5186 case 2: /* OP A, Iv */
5187 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5191 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5194 case 0x80: /* GRP1 */
5198 if (i386_record_modrm (&ir))
5201 if (ir.reg != OP_CMPL)
5203 if ((opcode & 1) == 0)
5206 ir.ot = ir.dflag + OT_WORD;
5213 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5214 if (i386_record_lea_modrm (&ir))
5218 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5220 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5223 case 0x40: /* inc */
5232 case 0x48: /* dec */
5241 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7);
5242 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5245 case 0xf6: /* GRP3 */
5247 if ((opcode & 1) == 0)
5250 ir.ot = ir.dflag + OT_WORD;
5251 if (i386_record_modrm (&ir))
5254 if (ir.mod != 3 && ir.reg == 0)
5255 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5260 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5266 if (i386_record_lea_modrm (&ir))
5272 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5274 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5276 if (ir.reg == 3) /* neg */
5277 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5283 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5284 if (ir.ot != OT_BYTE)
5285 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5286 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5290 opcode = opcode << 8 | ir.modrm;
5296 case 0xfe: /* GRP4 */
5297 case 0xff: /* GRP5 */
5298 if (i386_record_modrm (&ir))
5300 if (ir.reg >= 2 && opcode == 0xfe)
5303 opcode = opcode << 8 | ir.modrm;
5310 if ((opcode & 1) == 0)
5313 ir.ot = ir.dflag + OT_WORD;
5316 if (i386_record_lea_modrm (&ir))
5322 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5324 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5326 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5329 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5331 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5333 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5336 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5337 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5339 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5343 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5346 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5348 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5353 opcode = opcode << 8 | ir.modrm;
5359 case 0x84: /* test */
5363 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5366 case 0x98: /* CWDE/CBW */
5367 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5370 case 0x99: /* CDQ/CWD */
5371 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5372 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5375 case 0x0faf: /* imul */
5378 ir.ot = ir.dflag + OT_WORD;
5379 if (i386_record_modrm (&ir))
5382 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5383 else if (opcode == 0x6b)
5386 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5388 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5389 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5392 case 0x0fc0: /* xadd */
5394 if ((opcode & 1) == 0)
5397 ir.ot = ir.dflag + OT_WORD;
5398 if (i386_record_modrm (&ir))
5403 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5405 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5406 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5408 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5412 if (i386_record_lea_modrm (&ir))
5414 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5416 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5418 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5421 case 0x0fb0: /* cmpxchg */
5423 if ((opcode & 1) == 0)
5426 ir.ot = ir.dflag + OT_WORD;
5427 if (i386_record_modrm (&ir))
5432 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5433 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5435 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5439 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5440 if (i386_record_lea_modrm (&ir))
5443 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5446 case 0x0fc7: /* cmpxchg8b */
5447 if (i386_record_modrm (&ir))
5452 opcode = opcode << 8 | ir.modrm;
5455 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5456 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5457 if (i386_record_lea_modrm (&ir))
5459 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5462 case 0x50: /* push */
5472 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5474 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5478 case 0x06: /* push es */
5479 case 0x0e: /* push cs */
5480 case 0x16: /* push ss */
5481 case 0x1e: /* push ds */
5482 if (ir.regmap[X86_RECORD_R8_REGNUM])
5487 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5491 case 0x0fa0: /* push fs */
5492 case 0x0fa8: /* push gs */
5493 if (ir.regmap[X86_RECORD_R8_REGNUM])
5498 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5502 case 0x60: /* pusha */
5503 if (ir.regmap[X86_RECORD_R8_REGNUM])
5508 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
5512 case 0x58: /* pop */
5520 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5521 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5524 case 0x61: /* popa */
5525 if (ir.regmap[X86_RECORD_R8_REGNUM])
5530 for (regnum = X86_RECORD_REAX_REGNUM;
5531 regnum <= X86_RECORD_REDI_REGNUM;
5533 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5536 case 0x8f: /* pop */
5537 if (ir.regmap[X86_RECORD_R8_REGNUM])
5538 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
5540 ir.ot = ir.dflag + OT_WORD;
5541 if (i386_record_modrm (&ir))
5544 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5547 ir.popl_esp_hack = 1 << ir.ot;
5548 if (i386_record_lea_modrm (&ir))
5551 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5554 case 0xc8: /* enter */
5555 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5556 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5558 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5562 case 0xc9: /* leave */
5563 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5564 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5567 case 0x07: /* pop es */
5568 if (ir.regmap[X86_RECORD_R8_REGNUM])
5573 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5574 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
5575 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5578 case 0x17: /* pop ss */
5579 if (ir.regmap[X86_RECORD_R8_REGNUM])
5584 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5585 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
5586 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5589 case 0x1f: /* pop ds */
5590 if (ir.regmap[X86_RECORD_R8_REGNUM])
5595 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5596 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
5597 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5600 case 0x0fa1: /* pop fs */
5601 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5602 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
5603 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5606 case 0x0fa9: /* pop gs */
5607 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5608 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
5609 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5612 case 0x88: /* mov */
5616 if ((opcode & 1) == 0)
5619 ir.ot = ir.dflag + OT_WORD;
5621 if (i386_record_modrm (&ir))
5626 if (opcode == 0xc6 || opcode == 0xc7)
5627 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5628 if (i386_record_lea_modrm (&ir))
5633 if (opcode == 0xc6 || opcode == 0xc7)
5635 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5637 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5641 case 0x8a: /* mov */
5643 if ((opcode & 1) == 0)
5646 ir.ot = ir.dflag + OT_WORD;
5647 if (i386_record_modrm (&ir))
5650 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5652 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5655 case 0x8c: /* mov seg */
5656 if (i386_record_modrm (&ir))
5661 opcode = opcode << 8 | ir.modrm;
5666 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5670 if (i386_record_lea_modrm (&ir))
5675 case 0x8e: /* mov seg */
5676 if (i386_record_modrm (&ir))
5681 regnum = X86_RECORD_ES_REGNUM;
5684 regnum = X86_RECORD_SS_REGNUM;
5687 regnum = X86_RECORD_DS_REGNUM;
5690 regnum = X86_RECORD_FS_REGNUM;
5693 regnum = X86_RECORD_GS_REGNUM;
5697 opcode = opcode << 8 | ir.modrm;
5701 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5702 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5705 case 0x0fb6: /* movzbS */
5706 case 0x0fb7: /* movzwS */
5707 case 0x0fbe: /* movsbS */
5708 case 0x0fbf: /* movswS */
5709 if (i386_record_modrm (&ir))
5711 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5714 case 0x8d: /* lea */
5715 if (i386_record_modrm (&ir))
5720 opcode = opcode << 8 | ir.modrm;
5725 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5727 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5730 case 0xa0: /* mov EAX */
5733 case 0xd7: /* xlat */
5734 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5737 case 0xa2: /* mov EAX */
5739 if (ir.override >= 0)
5741 if (record_full_memory_query)
5745 target_terminal_ours ();
5747 Process record ignores the memory change of instruction at address %s\n\
5748 because it can't get the value of the segment register.\n\
5749 Do you want to stop the program?"),
5750 paddress (gdbarch, ir.orig_addr));
5751 target_terminal_inferior ();
5758 if ((opcode & 1) == 0)
5761 ir.ot = ir.dflag + OT_WORD;
5764 if (record_read_memory (gdbarch, ir.addr, buf, 8))
5767 addr = extract_unsigned_integer (buf, 8, byte_order);
5771 if (record_read_memory (gdbarch, ir.addr, buf, 4))
5774 addr = extract_unsigned_integer (buf, 4, byte_order);
5778 if (record_read_memory (gdbarch, ir.addr, buf, 2))
5781 addr = extract_unsigned_integer (buf, 2, byte_order);
5783 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
5788 case 0xb0: /* mov R, Ib */
5796 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
5797 ? ((opcode & 0x7) | ir.rex_b)
5798 : ((opcode & 0x7) & 0x3));
5801 case 0xb8: /* mov R, Iv */
5809 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5812 case 0x91: /* xchg R, EAX */
5819 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5820 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7);
5823 case 0x86: /* xchg Ev, Gv */
5825 if ((opcode & 1) == 0)
5828 ir.ot = ir.dflag + OT_WORD;
5829 if (i386_record_modrm (&ir))
5834 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5836 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5840 if (i386_record_lea_modrm (&ir))
5844 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5846 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5849 case 0xc4: /* les Gv */
5850 case 0xc5: /* lds Gv */
5851 if (ir.regmap[X86_RECORD_R8_REGNUM])
5857 case 0x0fb2: /* lss Gv */
5858 case 0x0fb4: /* lfs Gv */
5859 case 0x0fb5: /* lgs Gv */
5860 if (i386_record_modrm (&ir))
5868 opcode = opcode << 8 | ir.modrm;
5873 case 0xc4: /* les Gv */
5874 regnum = X86_RECORD_ES_REGNUM;
5876 case 0xc5: /* lds Gv */
5877 regnum = X86_RECORD_DS_REGNUM;
5879 case 0x0fb2: /* lss Gv */
5880 regnum = X86_RECORD_SS_REGNUM;
5882 case 0x0fb4: /* lfs Gv */
5883 regnum = X86_RECORD_FS_REGNUM;
5885 case 0x0fb5: /* lgs Gv */
5886 regnum = X86_RECORD_GS_REGNUM;
5889 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5890 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5891 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5894 case 0xc0: /* shifts */
5900 if ((opcode & 1) == 0)
5903 ir.ot = ir.dflag + OT_WORD;
5904 if (i386_record_modrm (&ir))
5906 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
5908 if (i386_record_lea_modrm (&ir))
5914 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5916 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5918 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5925 if (i386_record_modrm (&ir))
5929 if (record_full_arch_list_add_reg (ir.regcache, ir.rm))
5934 if (i386_record_lea_modrm (&ir))
5939 case 0xd8: /* Floats. */
5947 if (i386_record_modrm (&ir))
5949 ir.reg |= ((opcode & 7) << 3);
5955 if (i386_record_lea_modrm_addr (&ir, &addr64))
5963 /* For fcom, ficom nothing to do. */
5969 /* For fcomp, ficomp pop FPU stack, store all. */
5970 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5997 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5998 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5999 of code, always affects st(0) register. */
6000 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6024 /* Handling fld, fild. */
6025 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6029 switch (ir.reg >> 4)
6032 if (record_full_arch_list_add_mem (addr64, 4))
6036 if (record_full_arch_list_add_mem (addr64, 8))
6042 if (record_full_arch_list_add_mem (addr64, 2))
6048 switch (ir.reg >> 4)
6051 if (record_full_arch_list_add_mem (addr64, 4))
6053 if (3 == (ir.reg & 7))
6055 /* For fstp m32fp. */
6056 if (i386_record_floats (gdbarch, &ir,
6057 I386_SAVE_FPU_REGS))
6062 if (record_full_arch_list_add_mem (addr64, 4))
6064 if ((3 == (ir.reg & 7))
6065 || (5 == (ir.reg & 7))
6066 || (7 == (ir.reg & 7)))
6068 /* For fstp insn. */
6069 if (i386_record_floats (gdbarch, &ir,
6070 I386_SAVE_FPU_REGS))
6075 if (record_full_arch_list_add_mem (addr64, 8))
6077 if (3 == (ir.reg & 7))
6079 /* For fstp m64fp. */
6080 if (i386_record_floats (gdbarch, &ir,
6081 I386_SAVE_FPU_REGS))
6086 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
6088 /* For fistp, fbld, fild, fbstp. */
6089 if (i386_record_floats (gdbarch, &ir,
6090 I386_SAVE_FPU_REGS))
6095 if (record_full_arch_list_add_mem (addr64, 2))
6104 if (i386_record_floats (gdbarch, &ir,
6105 I386_SAVE_FPU_ENV_REG_STACK))
6110 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
6115 if (i386_record_floats (gdbarch, &ir,
6116 I386_SAVE_FPU_ENV_REG_STACK))
6122 if (record_full_arch_list_add_mem (addr64, 28))
6127 if (record_full_arch_list_add_mem (addr64, 14))
6133 if (record_full_arch_list_add_mem (addr64, 2))
6135 /* Insn fstp, fbstp. */
6136 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6141 if (record_full_arch_list_add_mem (addr64, 10))
6147 if (record_full_arch_list_add_mem (addr64, 28))
6153 if (record_full_arch_list_add_mem (addr64, 14))
6157 if (record_full_arch_list_add_mem (addr64, 80))
6160 if (i386_record_floats (gdbarch, &ir,
6161 I386_SAVE_FPU_ENV_REG_STACK))
6165 if (record_full_arch_list_add_mem (addr64, 8))
6168 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6173 opcode = opcode << 8 | ir.modrm;
6178 /* Opcode is an extension of modR/M byte. */
6184 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6188 if (0x0c == (ir.modrm >> 4))
6190 if ((ir.modrm & 0x0f) <= 7)
6192 if (i386_record_floats (gdbarch, &ir,
6193 I386_SAVE_FPU_REGS))
6198 if (i386_record_floats (gdbarch, &ir,
6199 I387_ST0_REGNUM (tdep)))
6201 /* If only st(0) is changing, then we have already
6203 if ((ir.modrm & 0x0f) - 0x08)
6205 if (i386_record_floats (gdbarch, &ir,
6206 I387_ST0_REGNUM (tdep) +
6207 ((ir.modrm & 0x0f) - 0x08)))
6225 if (i386_record_floats (gdbarch, &ir,
6226 I387_ST0_REGNUM (tdep)))
6244 if (i386_record_floats (gdbarch, &ir,
6245 I386_SAVE_FPU_REGS))
6249 if (i386_record_floats (gdbarch, &ir,
6250 I387_ST0_REGNUM (tdep)))
6252 if (i386_record_floats (gdbarch, &ir,
6253 I387_ST0_REGNUM (tdep) + 1))
6260 if (0xe9 == ir.modrm)
6262 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6265 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6267 if (i386_record_floats (gdbarch, &ir,
6268 I387_ST0_REGNUM (tdep)))
6270 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6272 if (i386_record_floats (gdbarch, &ir,
6273 I387_ST0_REGNUM (tdep) +
6277 else if ((ir.modrm & 0x0f) - 0x08)
6279 if (i386_record_floats (gdbarch, &ir,
6280 I387_ST0_REGNUM (tdep) +
6281 ((ir.modrm & 0x0f) - 0x08)))
6287 if (0xe3 == ir.modrm)
6289 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
6292 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6294 if (i386_record_floats (gdbarch, &ir,
6295 I387_ST0_REGNUM (tdep)))
6297 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6299 if (i386_record_floats (gdbarch, &ir,
6300 I387_ST0_REGNUM (tdep) +
6304 else if ((ir.modrm & 0x0f) - 0x08)
6306 if (i386_record_floats (gdbarch, &ir,
6307 I387_ST0_REGNUM (tdep) +
6308 ((ir.modrm & 0x0f) - 0x08)))
6314 if ((0x0c == ir.modrm >> 4)
6315 || (0x0d == ir.modrm >> 4)
6316 || (0x0f == ir.modrm >> 4))
6318 if ((ir.modrm & 0x0f) <= 7)
6320 if (i386_record_floats (gdbarch, &ir,
6321 I387_ST0_REGNUM (tdep) +
6327 if (i386_record_floats (gdbarch, &ir,
6328 I387_ST0_REGNUM (tdep) +
6329 ((ir.modrm & 0x0f) - 0x08)))
6335 if (0x0c == ir.modrm >> 4)
6337 if (i386_record_floats (gdbarch, &ir,
6338 I387_FTAG_REGNUM (tdep)))
6341 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6343 if ((ir.modrm & 0x0f) <= 7)
6345 if (i386_record_floats (gdbarch, &ir,
6346 I387_ST0_REGNUM (tdep) +
6352 if (i386_record_floats (gdbarch, &ir,
6353 I386_SAVE_FPU_REGS))
6359 if ((0x0c == ir.modrm >> 4)
6360 || (0x0e == ir.modrm >> 4)
6361 || (0x0f == ir.modrm >> 4)
6362 || (0xd9 == ir.modrm))
6364 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6369 if (0xe0 == ir.modrm)
6371 if (record_full_arch_list_add_reg (ir.regcache,
6375 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6377 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6385 case 0xa4: /* movsS */
6387 case 0xaa: /* stosS */
6389 case 0x6c: /* insS */
6391 regcache_raw_read_unsigned (ir.regcache,
6392 ir.regmap[X86_RECORD_RECX_REGNUM],
6398 if ((opcode & 1) == 0)
6401 ir.ot = ir.dflag + OT_WORD;
6402 regcache_raw_read_unsigned (ir.regcache,
6403 ir.regmap[X86_RECORD_REDI_REGNUM],
6406 regcache_raw_read_unsigned (ir.regcache,
6407 ir.regmap[X86_RECORD_ES_REGNUM],
6409 regcache_raw_read_unsigned (ir.regcache,
6410 ir.regmap[X86_RECORD_DS_REGNUM],
6412 if (ir.aflag && (es != ds))
6414 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6415 if (record_full_memory_query)
6419 target_terminal_ours ();
6421 Process record ignores the memory change of instruction at address %s\n\
6422 because it can't get the value of the segment register.\n\
6423 Do you want to stop the program?"),
6424 paddress (gdbarch, ir.orig_addr));
6425 target_terminal_inferior ();
6432 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
6436 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6437 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6438 if (opcode == 0xa4 || opcode == 0xa5)
6439 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6440 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6441 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6445 case 0xa6: /* cmpsS */
6447 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6448 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6449 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6450 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6451 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6454 case 0xac: /* lodsS */
6456 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6457 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6458 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6459 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6460 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6463 case 0xae: /* scasS */
6465 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6466 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6467 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6468 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6471 case 0x6e: /* outsS */
6473 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6474 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6475 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6476 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6479 case 0xe4: /* port I/O */
6483 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6484 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6494 case 0xc2: /* ret im */
6495 case 0xc3: /* ret */
6496 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6497 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6500 case 0xca: /* lret im */
6501 case 0xcb: /* lret */
6502 case 0xcf: /* iret */
6503 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6504 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6505 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6508 case 0xe8: /* call im */
6509 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6511 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6515 case 0x9a: /* lcall im */
6516 if (ir.regmap[X86_RECORD_R8_REGNUM])
6521 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6522 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6526 case 0xe9: /* jmp im */
6527 case 0xea: /* ljmp im */
6528 case 0xeb: /* jmp Jb */
6529 case 0x70: /* jcc Jb */
6545 case 0x0f80: /* jcc Jv */
6563 case 0x0f90: /* setcc Gv */
6579 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6581 if (i386_record_modrm (&ir))
6584 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
6588 if (i386_record_lea_modrm (&ir))
6593 case 0x0f40: /* cmov Gv, Ev */
6609 if (i386_record_modrm (&ir))
6612 if (ir.dflag == OT_BYTE)
6614 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
6618 case 0x9c: /* pushf */
6619 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6620 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6622 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6626 case 0x9d: /* popf */
6627 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6628 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6631 case 0x9e: /* sahf */
6632 if (ir.regmap[X86_RECORD_R8_REGNUM])
6638 case 0xf5: /* cmc */
6639 case 0xf8: /* clc */
6640 case 0xf9: /* stc */
6641 case 0xfc: /* cld */
6642 case 0xfd: /* std */
6643 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6646 case 0x9f: /* lahf */
6647 if (ir.regmap[X86_RECORD_R8_REGNUM])
6652 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6653 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6656 /* bit operations */
6657 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6658 ir.ot = ir.dflag + OT_WORD;
6659 if (i386_record_modrm (&ir))
6664 opcode = opcode << 8 | ir.modrm;
6670 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6673 if (i386_record_lea_modrm (&ir))
6677 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6680 case 0x0fa3: /* bt Gv, Ev */
6681 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6684 case 0x0fab: /* bts */
6685 case 0x0fb3: /* btr */
6686 case 0x0fbb: /* btc */
6687 ir.ot = ir.dflag + OT_WORD;
6688 if (i386_record_modrm (&ir))
6691 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6695 if (i386_record_lea_modrm_addr (&ir, &addr64))
6697 regcache_raw_read_unsigned (ir.regcache,
6698 ir.regmap[ir.reg | rex_r],
6703 addr64 += ((int16_t) addr >> 4) << 4;
6706 addr64 += ((int32_t) addr >> 5) << 5;
6709 addr64 += ((int64_t) addr >> 6) << 6;
6712 if (record_full_arch_list_add_mem (addr64, 1 << ir.ot))
6714 if (i386_record_lea_modrm (&ir))
6717 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6720 case 0x0fbc: /* bsf */
6721 case 0x0fbd: /* bsr */
6722 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6723 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6727 case 0x27: /* daa */
6728 case 0x2f: /* das */
6729 case 0x37: /* aaa */
6730 case 0x3f: /* aas */
6731 case 0xd4: /* aam */
6732 case 0xd5: /* aad */
6733 if (ir.regmap[X86_RECORD_R8_REGNUM])
6738 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6739 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6743 case 0x90: /* nop */
6744 if (prefixes & PREFIX_LOCK)
6751 case 0x9b: /* fwait */
6752 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
6754 opcode = (uint32_t) opcode8;
6760 case 0xcc: /* int3 */
6761 printf_unfiltered (_("Process record does not support instruction "
6768 case 0xcd: /* int */
6772 if (record_read_memory (gdbarch, ir.addr, &interrupt, 1))
6775 if (interrupt != 0x80
6776 || tdep->i386_intx80_record == NULL)
6778 printf_unfiltered (_("Process record does not support "
6779 "instruction int 0x%02x.\n"),
6784 ret = tdep->i386_intx80_record (ir.regcache);
6791 case 0xce: /* into */
6792 printf_unfiltered (_("Process record does not support "
6793 "instruction into.\n"));
6798 case 0xfa: /* cli */
6799 case 0xfb: /* sti */
6802 case 0x62: /* bound */
6803 printf_unfiltered (_("Process record does not support "
6804 "instruction bound.\n"));
6809 case 0x0fc8: /* bswap reg */
6817 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
6820 case 0xd6: /* salc */
6821 if (ir.regmap[X86_RECORD_R8_REGNUM])
6826 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6827 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6830 case 0xe0: /* loopnz */
6831 case 0xe1: /* loopz */
6832 case 0xe2: /* loop */
6833 case 0xe3: /* jecxz */
6834 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6835 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6838 case 0x0f30: /* wrmsr */
6839 printf_unfiltered (_("Process record does not support "
6840 "instruction wrmsr.\n"));
6845 case 0x0f32: /* rdmsr */
6846 printf_unfiltered (_("Process record does not support "
6847 "instruction rdmsr.\n"));
6852 case 0x0f31: /* rdtsc */
6853 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6854 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6857 case 0x0f34: /* sysenter */
6860 if (ir.regmap[X86_RECORD_R8_REGNUM])
6865 if (tdep->i386_sysenter_record == NULL)
6867 printf_unfiltered (_("Process record does not support "
6868 "instruction sysenter.\n"));
6872 ret = tdep->i386_sysenter_record (ir.regcache);
6878 case 0x0f35: /* sysexit */
6879 printf_unfiltered (_("Process record does not support "
6880 "instruction sysexit.\n"));
6885 case 0x0f05: /* syscall */
6888 if (tdep->i386_syscall_record == NULL)
6890 printf_unfiltered (_("Process record does not support "
6891 "instruction syscall.\n"));
6895 ret = tdep->i386_syscall_record (ir.regcache);
6901 case 0x0f07: /* sysret */
6902 printf_unfiltered (_("Process record does not support "
6903 "instruction sysret.\n"));
6908 case 0x0fa2: /* cpuid */
6909 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6910 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6911 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6912 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
6915 case 0xf4: /* hlt */
6916 printf_unfiltered (_("Process record does not support "
6917 "instruction hlt.\n"));
6923 if (i386_record_modrm (&ir))
6930 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6934 if (i386_record_lea_modrm (&ir))
6943 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6947 opcode = opcode << 8 | ir.modrm;
6954 if (i386_record_modrm (&ir))
6965 opcode = opcode << 8 | ir.modrm;
6968 if (ir.override >= 0)
6970 if (record_full_memory_query)
6974 target_terminal_ours ();
6976 Process record ignores the memory change of instruction at address %s\n\
6977 because it can't get the value of the segment register.\n\
6978 Do you want to stop the program?"),
6979 paddress (gdbarch, ir.orig_addr));
6980 target_terminal_inferior ();
6987 if (i386_record_lea_modrm_addr (&ir, &addr64))
6989 if (record_full_arch_list_add_mem (addr64, 2))
6992 if (ir.regmap[X86_RECORD_R8_REGNUM])
6994 if (record_full_arch_list_add_mem (addr64, 8))
6999 if (record_full_arch_list_add_mem (addr64, 4))
7010 case 0: /* monitor */
7013 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7017 opcode = opcode << 8 | ir.modrm;
7025 if (ir.override >= 0)
7027 if (record_full_memory_query)
7031 target_terminal_ours ();
7033 Process record ignores the memory change of instruction at address %s\n\
7034 because it can't get the value of the segment register.\n\
7035 Do you want to stop the program?"),
7036 paddress (gdbarch, ir.orig_addr));
7037 target_terminal_inferior ();
7046 if (i386_record_lea_modrm_addr (&ir, &addr64))
7048 if (record_full_arch_list_add_mem (addr64, 2))
7051 if (ir.regmap[X86_RECORD_R8_REGNUM])
7053 if (record_full_arch_list_add_mem (addr64, 8))
7058 if (record_full_arch_list_add_mem (addr64, 4))
7070 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7071 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7075 else if (ir.rm == 1)
7082 opcode = opcode << 8 | ir.modrm;
7089 if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
7095 if (i386_record_lea_modrm (&ir))
7098 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7101 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7103 case 7: /* invlpg */
7106 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
7107 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
7111 opcode = opcode << 8 | ir.modrm;
7116 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7120 opcode = opcode << 8 | ir.modrm;
7126 case 0x0f08: /* invd */
7127 case 0x0f09: /* wbinvd */
7130 case 0x63: /* arpl */
7131 if (i386_record_modrm (&ir))
7133 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
7135 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
7136 ? (ir.reg | rex_r) : ir.rm);
7140 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
7141 if (i386_record_lea_modrm (&ir))
7144 if (!ir.regmap[X86_RECORD_R8_REGNUM])
7145 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7148 case 0x0f02: /* lar */
7149 case 0x0f03: /* lsl */
7150 if (i386_record_modrm (&ir))
7152 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7153 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7157 if (i386_record_modrm (&ir))
7159 if (ir.mod == 3 && ir.reg == 3)
7162 opcode = opcode << 8 | ir.modrm;
7174 /* nop (multi byte) */
7177 case 0x0f20: /* mov reg, crN */
7178 case 0x0f22: /* mov crN, reg */
7179 if (i386_record_modrm (&ir))
7181 if ((ir.modrm & 0xc0) != 0xc0)
7184 opcode = opcode << 8 | ir.modrm;
7195 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7197 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7201 opcode = opcode << 8 | ir.modrm;
7207 case 0x0f21: /* mov reg, drN */
7208 case 0x0f23: /* mov drN, reg */
7209 if (i386_record_modrm (&ir))
7211 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
7212 || ir.reg == 5 || ir.reg >= 8)
7215 opcode = opcode << 8 | ir.modrm;
7219 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7221 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7224 case 0x0f06: /* clts */
7225 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7228 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7230 case 0x0f0d: /* 3DNow! prefetch */
7233 case 0x0f0e: /* 3DNow! femms */
7234 case 0x0f77: /* emms */
7235 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
7237 record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
7240 case 0x0f0f: /* 3DNow! data */
7241 if (i386_record_modrm (&ir))
7243 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7248 case 0x0c: /* 3DNow! pi2fw */
7249 case 0x0d: /* 3DNow! pi2fd */
7250 case 0x1c: /* 3DNow! pf2iw */
7251 case 0x1d: /* 3DNow! pf2id */
7252 case 0x8a: /* 3DNow! pfnacc */
7253 case 0x8e: /* 3DNow! pfpnacc */
7254 case 0x90: /* 3DNow! pfcmpge */
7255 case 0x94: /* 3DNow! pfmin */
7256 case 0x96: /* 3DNow! pfrcp */
7257 case 0x97: /* 3DNow! pfrsqrt */
7258 case 0x9a: /* 3DNow! pfsub */
7259 case 0x9e: /* 3DNow! pfadd */
7260 case 0xa0: /* 3DNow! pfcmpgt */
7261 case 0xa4: /* 3DNow! pfmax */
7262 case 0xa6: /* 3DNow! pfrcpit1 */
7263 case 0xa7: /* 3DNow! pfrsqit1 */
7264 case 0xaa: /* 3DNow! pfsubr */
7265 case 0xae: /* 3DNow! pfacc */
7266 case 0xb0: /* 3DNow! pfcmpeq */
7267 case 0xb4: /* 3DNow! pfmul */
7268 case 0xb6: /* 3DNow! pfrcpit2 */
7269 case 0xb7: /* 3DNow! pmulhrw */
7270 case 0xbb: /* 3DNow! pswapd */
7271 case 0xbf: /* 3DNow! pavgusb */
7272 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7273 goto no_support_3dnow_data;
7274 record_full_arch_list_add_reg (ir.regcache, ir.reg);
7278 no_support_3dnow_data:
7279 opcode = (opcode << 8) | opcode8;
7285 case 0x0faa: /* rsm */
7286 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7287 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7288 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
7289 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7290 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
7291 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
7292 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
7293 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
7294 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
7298 if (i386_record_modrm (&ir))
7302 case 0: /* fxsave */
7306 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7307 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
7309 if (record_full_arch_list_add_mem (tmpu64, 512))
7314 case 1: /* fxrstor */
7318 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7320 for (i = I387_MM0_REGNUM (tdep);
7321 i386_mmx_regnum_p (gdbarch, i); i++)
7322 record_full_arch_list_add_reg (ir.regcache, i);
7324 for (i = I387_XMM0_REGNUM (tdep);
7325 i386_xmm_regnum_p (gdbarch, i); i++)
7326 record_full_arch_list_add_reg (ir.regcache, i);
7328 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7329 record_full_arch_list_add_reg (ir.regcache,
7330 I387_MXCSR_REGNUM(tdep));
7332 for (i = I387_ST0_REGNUM (tdep);
7333 i386_fp_regnum_p (gdbarch, i); i++)
7334 record_full_arch_list_add_reg (ir.regcache, i);
7336 for (i = I387_FCTRL_REGNUM (tdep);
7337 i386_fpc_regnum_p (gdbarch, i); i++)
7338 record_full_arch_list_add_reg (ir.regcache, i);
7342 case 2: /* ldmxcsr */
7343 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7345 record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
7348 case 3: /* stmxcsr */
7350 if (i386_record_lea_modrm (&ir))
7354 case 5: /* lfence */
7355 case 6: /* mfence */
7356 case 7: /* sfence clflush */
7360 opcode = (opcode << 8) | ir.modrm;
7366 case 0x0fc3: /* movnti */
7367 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
7368 if (i386_record_modrm (&ir))
7373 if (i386_record_lea_modrm (&ir))
7377 /* Add prefix to opcode. */
7492 /* Mask out PREFIX_ADDR. */
7493 switch ((prefixes & ~PREFIX_ADDR))
7505 reswitch_prefix_add:
7513 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7516 opcode = (uint32_t) opcode8 | opcode << 8;
7517 goto reswitch_prefix_add;
7520 case 0x0f10: /* movups */
7521 case 0x660f10: /* movupd */
7522 case 0xf30f10: /* movss */
7523 case 0xf20f10: /* movsd */
7524 case 0x0f12: /* movlps */
7525 case 0x660f12: /* movlpd */
7526 case 0xf30f12: /* movsldup */
7527 case 0xf20f12: /* movddup */
7528 case 0x0f14: /* unpcklps */
7529 case 0x660f14: /* unpcklpd */
7530 case 0x0f15: /* unpckhps */
7531 case 0x660f15: /* unpckhpd */
7532 case 0x0f16: /* movhps */
7533 case 0x660f16: /* movhpd */
7534 case 0xf30f16: /* movshdup */
7535 case 0x0f28: /* movaps */
7536 case 0x660f28: /* movapd */
7537 case 0x0f2a: /* cvtpi2ps */
7538 case 0x660f2a: /* cvtpi2pd */
7539 case 0xf30f2a: /* cvtsi2ss */
7540 case 0xf20f2a: /* cvtsi2sd */
7541 case 0x0f2c: /* cvttps2pi */
7542 case 0x660f2c: /* cvttpd2pi */
7543 case 0x0f2d: /* cvtps2pi */
7544 case 0x660f2d: /* cvtpd2pi */
7545 case 0x660f3800: /* pshufb */
7546 case 0x660f3801: /* phaddw */
7547 case 0x660f3802: /* phaddd */
7548 case 0x660f3803: /* phaddsw */
7549 case 0x660f3804: /* pmaddubsw */
7550 case 0x660f3805: /* phsubw */
7551 case 0x660f3806: /* phsubd */
7552 case 0x660f3807: /* phsubsw */
7553 case 0x660f3808: /* psignb */
7554 case 0x660f3809: /* psignw */
7555 case 0x660f380a: /* psignd */
7556 case 0x660f380b: /* pmulhrsw */
7557 case 0x660f3810: /* pblendvb */
7558 case 0x660f3814: /* blendvps */
7559 case 0x660f3815: /* blendvpd */
7560 case 0x660f381c: /* pabsb */
7561 case 0x660f381d: /* pabsw */
7562 case 0x660f381e: /* pabsd */
7563 case 0x660f3820: /* pmovsxbw */
7564 case 0x660f3821: /* pmovsxbd */
7565 case 0x660f3822: /* pmovsxbq */
7566 case 0x660f3823: /* pmovsxwd */
7567 case 0x660f3824: /* pmovsxwq */
7568 case 0x660f3825: /* pmovsxdq */
7569 case 0x660f3828: /* pmuldq */
7570 case 0x660f3829: /* pcmpeqq */
7571 case 0x660f382a: /* movntdqa */
7572 case 0x660f3a08: /* roundps */
7573 case 0x660f3a09: /* roundpd */
7574 case 0x660f3a0a: /* roundss */
7575 case 0x660f3a0b: /* roundsd */
7576 case 0x660f3a0c: /* blendps */
7577 case 0x660f3a0d: /* blendpd */
7578 case 0x660f3a0e: /* pblendw */
7579 case 0x660f3a0f: /* palignr */
7580 case 0x660f3a20: /* pinsrb */
7581 case 0x660f3a21: /* insertps */
7582 case 0x660f3a22: /* pinsrd pinsrq */
7583 case 0x660f3a40: /* dpps */
7584 case 0x660f3a41: /* dppd */
7585 case 0x660f3a42: /* mpsadbw */
7586 case 0x660f3a60: /* pcmpestrm */
7587 case 0x660f3a61: /* pcmpestri */
7588 case 0x660f3a62: /* pcmpistrm */
7589 case 0x660f3a63: /* pcmpistri */
7590 case 0x0f51: /* sqrtps */
7591 case 0x660f51: /* sqrtpd */
7592 case 0xf20f51: /* sqrtsd */
7593 case 0xf30f51: /* sqrtss */
7594 case 0x0f52: /* rsqrtps */
7595 case 0xf30f52: /* rsqrtss */
7596 case 0x0f53: /* rcpps */
7597 case 0xf30f53: /* rcpss */
7598 case 0x0f54: /* andps */
7599 case 0x660f54: /* andpd */
7600 case 0x0f55: /* andnps */
7601 case 0x660f55: /* andnpd */
7602 case 0x0f56: /* orps */
7603 case 0x660f56: /* orpd */
7604 case 0x0f57: /* xorps */
7605 case 0x660f57: /* xorpd */
7606 case 0x0f58: /* addps */
7607 case 0x660f58: /* addpd */
7608 case 0xf20f58: /* addsd */
7609 case 0xf30f58: /* addss */
7610 case 0x0f59: /* mulps */
7611 case 0x660f59: /* mulpd */
7612 case 0xf20f59: /* mulsd */
7613 case 0xf30f59: /* mulss */
7614 case 0x0f5a: /* cvtps2pd */
7615 case 0x660f5a: /* cvtpd2ps */
7616 case 0xf20f5a: /* cvtsd2ss */
7617 case 0xf30f5a: /* cvtss2sd */
7618 case 0x0f5b: /* cvtdq2ps */
7619 case 0x660f5b: /* cvtps2dq */
7620 case 0xf30f5b: /* cvttps2dq */
7621 case 0x0f5c: /* subps */
7622 case 0x660f5c: /* subpd */
7623 case 0xf20f5c: /* subsd */
7624 case 0xf30f5c: /* subss */
7625 case 0x0f5d: /* minps */
7626 case 0x660f5d: /* minpd */
7627 case 0xf20f5d: /* minsd */
7628 case 0xf30f5d: /* minss */
7629 case 0x0f5e: /* divps */
7630 case 0x660f5e: /* divpd */
7631 case 0xf20f5e: /* divsd */
7632 case 0xf30f5e: /* divss */
7633 case 0x0f5f: /* maxps */
7634 case 0x660f5f: /* maxpd */
7635 case 0xf20f5f: /* maxsd */
7636 case 0xf30f5f: /* maxss */
7637 case 0x660f60: /* punpcklbw */
7638 case 0x660f61: /* punpcklwd */
7639 case 0x660f62: /* punpckldq */
7640 case 0x660f63: /* packsswb */
7641 case 0x660f64: /* pcmpgtb */
7642 case 0x660f65: /* pcmpgtw */
7643 case 0x660f66: /* pcmpgtd */
7644 case 0x660f67: /* packuswb */
7645 case 0x660f68: /* punpckhbw */
7646 case 0x660f69: /* punpckhwd */
7647 case 0x660f6a: /* punpckhdq */
7648 case 0x660f6b: /* packssdw */
7649 case 0x660f6c: /* punpcklqdq */
7650 case 0x660f6d: /* punpckhqdq */
7651 case 0x660f6e: /* movd */
7652 case 0x660f6f: /* movdqa */
7653 case 0xf30f6f: /* movdqu */
7654 case 0x660f70: /* pshufd */
7655 case 0xf20f70: /* pshuflw */
7656 case 0xf30f70: /* pshufhw */
7657 case 0x660f74: /* pcmpeqb */
7658 case 0x660f75: /* pcmpeqw */
7659 case 0x660f76: /* pcmpeqd */
7660 case 0x660f7c: /* haddpd */
7661 case 0xf20f7c: /* haddps */
7662 case 0x660f7d: /* hsubpd */
7663 case 0xf20f7d: /* hsubps */
7664 case 0xf30f7e: /* movq */
7665 case 0x0fc2: /* cmpps */
7666 case 0x660fc2: /* cmppd */
7667 case 0xf20fc2: /* cmpsd */
7668 case 0xf30fc2: /* cmpss */
7669 case 0x660fc4: /* pinsrw */
7670 case 0x0fc6: /* shufps */
7671 case 0x660fc6: /* shufpd */
7672 case 0x660fd0: /* addsubpd */
7673 case 0xf20fd0: /* addsubps */
7674 case 0x660fd1: /* psrlw */
7675 case 0x660fd2: /* psrld */
7676 case 0x660fd3: /* psrlq */
7677 case 0x660fd4: /* paddq */
7678 case 0x660fd5: /* pmullw */
7679 case 0xf30fd6: /* movq2dq */
7680 case 0x660fd8: /* psubusb */
7681 case 0x660fd9: /* psubusw */
7682 case 0x660fda: /* pminub */
7683 case 0x660fdb: /* pand */
7684 case 0x660fdc: /* paddusb */
7685 case 0x660fdd: /* paddusw */
7686 case 0x660fde: /* pmaxub */
7687 case 0x660fdf: /* pandn */
7688 case 0x660fe0: /* pavgb */
7689 case 0x660fe1: /* psraw */
7690 case 0x660fe2: /* psrad */
7691 case 0x660fe3: /* pavgw */
7692 case 0x660fe4: /* pmulhuw */
7693 case 0x660fe5: /* pmulhw */
7694 case 0x660fe6: /* cvttpd2dq */
7695 case 0xf20fe6: /* cvtpd2dq */
7696 case 0xf30fe6: /* cvtdq2pd */
7697 case 0x660fe8: /* psubsb */
7698 case 0x660fe9: /* psubsw */
7699 case 0x660fea: /* pminsw */
7700 case 0x660feb: /* por */
7701 case 0x660fec: /* paddsb */
7702 case 0x660fed: /* paddsw */
7703 case 0x660fee: /* pmaxsw */
7704 case 0x660fef: /* pxor */
7705 case 0xf20ff0: /* lddqu */
7706 case 0x660ff1: /* psllw */
7707 case 0x660ff2: /* pslld */
7708 case 0x660ff3: /* psllq */
7709 case 0x660ff4: /* pmuludq */
7710 case 0x660ff5: /* pmaddwd */
7711 case 0x660ff6: /* psadbw */
7712 case 0x660ff8: /* psubb */
7713 case 0x660ff9: /* psubw */
7714 case 0x660ffa: /* psubd */
7715 case 0x660ffb: /* psubq */
7716 case 0x660ffc: /* paddb */
7717 case 0x660ffd: /* paddw */
7718 case 0x660ffe: /* paddd */
7719 if (i386_record_modrm (&ir))
7722 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
7724 record_full_arch_list_add_reg (ir.regcache,
7725 I387_XMM0_REGNUM (tdep) + ir.reg);
7726 if ((opcode & 0xfffffffc) == 0x660f3a60)
7727 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7730 case 0x0f11: /* movups */
7731 case 0x660f11: /* movupd */
7732 case 0xf30f11: /* movss */
7733 case 0xf20f11: /* movsd */
7734 case 0x0f13: /* movlps */
7735 case 0x660f13: /* movlpd */
7736 case 0x0f17: /* movhps */
7737 case 0x660f17: /* movhpd */
7738 case 0x0f29: /* movaps */
7739 case 0x660f29: /* movapd */
7740 case 0x660f3a14: /* pextrb */
7741 case 0x660f3a15: /* pextrw */
7742 case 0x660f3a16: /* pextrd pextrq */
7743 case 0x660f3a17: /* extractps */
7744 case 0x660f7f: /* movdqa */
7745 case 0xf30f7f: /* movdqu */
7746 if (i386_record_modrm (&ir))
7750 if (opcode == 0x0f13 || opcode == 0x660f13
7751 || opcode == 0x0f17 || opcode == 0x660f17)
7754 if (!i386_xmm_regnum_p (gdbarch,
7755 I387_XMM0_REGNUM (tdep) + ir.rm))
7757 record_full_arch_list_add_reg (ir.regcache,
7758 I387_XMM0_REGNUM (tdep) + ir.rm);
7780 if (i386_record_lea_modrm (&ir))
7785 case 0x0f2b: /* movntps */
7786 case 0x660f2b: /* movntpd */
7787 case 0x0fe7: /* movntq */
7788 case 0x660fe7: /* movntdq */
7791 if (opcode == 0x0fe7)
7795 if (i386_record_lea_modrm (&ir))
7799 case 0xf30f2c: /* cvttss2si */
7800 case 0xf20f2c: /* cvttsd2si */
7801 case 0xf30f2d: /* cvtss2si */
7802 case 0xf20f2d: /* cvtsd2si */
7803 case 0xf20f38f0: /* crc32 */
7804 case 0xf20f38f1: /* crc32 */
7805 case 0x0f50: /* movmskps */
7806 case 0x660f50: /* movmskpd */
7807 case 0x0fc5: /* pextrw */
7808 case 0x660fc5: /* pextrw */
7809 case 0x0fd7: /* pmovmskb */
7810 case 0x660fd7: /* pmovmskb */
7811 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7814 case 0x0f3800: /* pshufb */
7815 case 0x0f3801: /* phaddw */
7816 case 0x0f3802: /* phaddd */
7817 case 0x0f3803: /* phaddsw */
7818 case 0x0f3804: /* pmaddubsw */
7819 case 0x0f3805: /* phsubw */
7820 case 0x0f3806: /* phsubd */
7821 case 0x0f3807: /* phsubsw */
7822 case 0x0f3808: /* psignb */
7823 case 0x0f3809: /* psignw */
7824 case 0x0f380a: /* psignd */
7825 case 0x0f380b: /* pmulhrsw */
7826 case 0x0f381c: /* pabsb */
7827 case 0x0f381d: /* pabsw */
7828 case 0x0f381e: /* pabsd */
7829 case 0x0f382b: /* packusdw */
7830 case 0x0f3830: /* pmovzxbw */
7831 case 0x0f3831: /* pmovzxbd */
7832 case 0x0f3832: /* pmovzxbq */
7833 case 0x0f3833: /* pmovzxwd */
7834 case 0x0f3834: /* pmovzxwq */
7835 case 0x0f3835: /* pmovzxdq */
7836 case 0x0f3837: /* pcmpgtq */
7837 case 0x0f3838: /* pminsb */
7838 case 0x0f3839: /* pminsd */
7839 case 0x0f383a: /* pminuw */
7840 case 0x0f383b: /* pminud */
7841 case 0x0f383c: /* pmaxsb */
7842 case 0x0f383d: /* pmaxsd */
7843 case 0x0f383e: /* pmaxuw */
7844 case 0x0f383f: /* pmaxud */
7845 case 0x0f3840: /* pmulld */
7846 case 0x0f3841: /* phminposuw */
7847 case 0x0f3a0f: /* palignr */
7848 case 0x0f60: /* punpcklbw */
7849 case 0x0f61: /* punpcklwd */
7850 case 0x0f62: /* punpckldq */
7851 case 0x0f63: /* packsswb */
7852 case 0x0f64: /* pcmpgtb */
7853 case 0x0f65: /* pcmpgtw */
7854 case 0x0f66: /* pcmpgtd */
7855 case 0x0f67: /* packuswb */
7856 case 0x0f68: /* punpckhbw */
7857 case 0x0f69: /* punpckhwd */
7858 case 0x0f6a: /* punpckhdq */
7859 case 0x0f6b: /* packssdw */
7860 case 0x0f6e: /* movd */
7861 case 0x0f6f: /* movq */
7862 case 0x0f70: /* pshufw */
7863 case 0x0f74: /* pcmpeqb */
7864 case 0x0f75: /* pcmpeqw */
7865 case 0x0f76: /* pcmpeqd */
7866 case 0x0fc4: /* pinsrw */
7867 case 0x0fd1: /* psrlw */
7868 case 0x0fd2: /* psrld */
7869 case 0x0fd3: /* psrlq */
7870 case 0x0fd4: /* paddq */
7871 case 0x0fd5: /* pmullw */
7872 case 0xf20fd6: /* movdq2q */
7873 case 0x0fd8: /* psubusb */
7874 case 0x0fd9: /* psubusw */
7875 case 0x0fda: /* pminub */
7876 case 0x0fdb: /* pand */
7877 case 0x0fdc: /* paddusb */
7878 case 0x0fdd: /* paddusw */
7879 case 0x0fde: /* pmaxub */
7880 case 0x0fdf: /* pandn */
7881 case 0x0fe0: /* pavgb */
7882 case 0x0fe1: /* psraw */
7883 case 0x0fe2: /* psrad */
7884 case 0x0fe3: /* pavgw */
7885 case 0x0fe4: /* pmulhuw */
7886 case 0x0fe5: /* pmulhw */
7887 case 0x0fe8: /* psubsb */
7888 case 0x0fe9: /* psubsw */
7889 case 0x0fea: /* pminsw */
7890 case 0x0feb: /* por */
7891 case 0x0fec: /* paddsb */
7892 case 0x0fed: /* paddsw */
7893 case 0x0fee: /* pmaxsw */
7894 case 0x0fef: /* pxor */
7895 case 0x0ff1: /* psllw */
7896 case 0x0ff2: /* pslld */
7897 case 0x0ff3: /* psllq */
7898 case 0x0ff4: /* pmuludq */
7899 case 0x0ff5: /* pmaddwd */
7900 case 0x0ff6: /* psadbw */
7901 case 0x0ff8: /* psubb */
7902 case 0x0ff9: /* psubw */
7903 case 0x0ffa: /* psubd */
7904 case 0x0ffb: /* psubq */
7905 case 0x0ffc: /* paddb */
7906 case 0x0ffd: /* paddw */
7907 case 0x0ffe: /* paddd */
7908 if (i386_record_modrm (&ir))
7910 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7912 record_full_arch_list_add_reg (ir.regcache,
7913 I387_MM0_REGNUM (tdep) + ir.reg);
7916 case 0x0f71: /* psllw */
7917 case 0x0f72: /* pslld */
7918 case 0x0f73: /* psllq */
7919 if (i386_record_modrm (&ir))
7921 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7923 record_full_arch_list_add_reg (ir.regcache,
7924 I387_MM0_REGNUM (tdep) + ir.rm);
7927 case 0x660f71: /* psllw */
7928 case 0x660f72: /* pslld */
7929 case 0x660f73: /* psllq */
7930 if (i386_record_modrm (&ir))
7933 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
7935 record_full_arch_list_add_reg (ir.regcache,
7936 I387_XMM0_REGNUM (tdep) + ir.rm);
7939 case 0x0f7e: /* movd */
7940 case 0x660f7e: /* movd */
7941 if (i386_record_modrm (&ir))
7944 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7951 if (i386_record_lea_modrm (&ir))
7956 case 0x0f7f: /* movq */
7957 if (i386_record_modrm (&ir))
7961 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7963 record_full_arch_list_add_reg (ir.regcache,
7964 I387_MM0_REGNUM (tdep) + ir.rm);
7969 if (i386_record_lea_modrm (&ir))
7974 case 0xf30fb8: /* popcnt */
7975 if (i386_record_modrm (&ir))
7977 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
7978 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7981 case 0x660fd6: /* movq */
7982 if (i386_record_modrm (&ir))
7987 if (!i386_xmm_regnum_p (gdbarch,
7988 I387_XMM0_REGNUM (tdep) + ir.rm))
7990 record_full_arch_list_add_reg (ir.regcache,
7991 I387_XMM0_REGNUM (tdep) + ir.rm);
7996 if (i386_record_lea_modrm (&ir))
8001 case 0x660f3817: /* ptest */
8002 case 0x0f2e: /* ucomiss */
8003 case 0x660f2e: /* ucomisd */
8004 case 0x0f2f: /* comiss */
8005 case 0x660f2f: /* comisd */
8006 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
8009 case 0x0ff7: /* maskmovq */
8010 regcache_raw_read_unsigned (ir.regcache,
8011 ir.regmap[X86_RECORD_REDI_REGNUM],
8013 if (record_full_arch_list_add_mem (addr, 64))
8017 case 0x660ff7: /* maskmovdqu */
8018 regcache_raw_read_unsigned (ir.regcache,
8019 ir.regmap[X86_RECORD_REDI_REGNUM],
8021 if (record_full_arch_list_add_mem (addr, 128))
8036 /* In the future, maybe still need to deal with need_dasm. */
8037 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
8038 if (record_full_arch_list_add_end ())
8044 printf_unfiltered (_("Process record does not support instruction 0x%02x "
8045 "at address %s.\n"),
8046 (unsigned int) (opcode),
8047 paddress (gdbarch, ir.orig_addr));
8051 static const int i386_record_regmap[] =
8053 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
8054 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
8055 0, 0, 0, 0, 0, 0, 0, 0,
8056 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
8057 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
8060 /* Check that the given address appears suitable for a fast
8061 tracepoint, which on x86-64 means that we need an instruction of at
8062 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8063 jump and not have to worry about program jumps to an address in the
8064 middle of the tracepoint jump. On x86, it may be possible to use
8065 4-byte jumps with a 2-byte offset to a trampoline located in the
8066 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8067 of instruction to replace, and 0 if not, plus an explanatory
8071 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch,
8072 CORE_ADDR addr, int *isize, char **msg)
8075 static struct ui_file *gdb_null = NULL;
8077 /* Ask the target for the minimum instruction length supported. */
8078 jumplen = target_get_min_fast_tracepoint_insn_len ();
8082 /* If the target does not support the get_min_fast_tracepoint_insn_len
8083 operation, assume that fast tracepoints will always be implemented
8084 using 4-byte relative jumps on both x86 and x86-64. */
8087 else if (jumplen == 0)
8089 /* If the target does support get_min_fast_tracepoint_insn_len but
8090 returns zero, then the IPA has not loaded yet. In this case,
8091 we optimistically assume that truncated 2-byte relative jumps
8092 will be available on x86, and compensate later if this assumption
8093 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8094 jumps will always be used. */
8095 jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4;
8098 /* Dummy file descriptor for the disassembler. */
8100 gdb_null = ui_file_new ();
8102 /* Check for fit. */
8103 len = gdb_print_insn (gdbarch, addr, gdb_null, NULL);
8109 /* Return a bit of target-specific detail to add to the caller's
8110 generic failure message. */
8112 *msg = xstrprintf (_("; instruction is only %d bytes long, "
8113 "need at least %d bytes for the jump"),
8126 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
8127 struct tdesc_arch_data *tdesc_data)
8129 const struct target_desc *tdesc = tdep->tdesc;
8130 const struct tdesc_feature *feature_core;
8132 const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx,
8134 int i, num_regs, valid_p;
8136 if (! tdesc_has_registers (tdesc))
8139 /* Get core registers. */
8140 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
8141 if (feature_core == NULL)
8144 /* Get SSE registers. */
8145 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
8147 /* Try AVX registers. */
8148 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
8150 /* Try MPX registers. */
8151 feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx");
8153 /* Try AVX512 registers. */
8154 feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512");
8158 /* The XCR0 bits. */
8161 /* AVX512 register description requires AVX register description. */
8165 tdep->xcr0 = I386_XSTATE_MPX_AVX512_MASK;
8167 /* It may have been set by OSABI initialization function. */
8168 if (tdep->k0_regnum < 0)
8170 tdep->k_register_names = i386_k_names;
8171 tdep->k0_regnum = I386_K0_REGNUM;
8174 for (i = 0; i < I387_NUM_K_REGS; i++)
8175 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8176 tdep->k0_regnum + i,
8179 if (tdep->num_zmm_regs == 0)
8181 tdep->zmmh_register_names = i386_zmmh_names;
8182 tdep->num_zmm_regs = 8;
8183 tdep->zmm0h_regnum = I386_ZMM0H_REGNUM;
8186 for (i = 0; i < tdep->num_zmm_regs; i++)
8187 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8188 tdep->zmm0h_regnum + i,
8189 tdep->zmmh_register_names[i]);
8191 for (i = 0; i < tdep->num_xmm_avx512_regs; i++)
8192 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8193 tdep->xmm16_regnum + i,
8194 tdep->xmm_avx512_register_names[i]);
8196 for (i = 0; i < tdep->num_ymm_avx512_regs; i++)
8197 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8198 tdep->ymm16h_regnum + i,
8199 tdep->ymm16h_register_names[i]);
8203 /* AVX register description requires SSE register description. */
8207 if (!feature_avx512)
8208 tdep->xcr0 = I386_XSTATE_AVX_MASK;
8210 /* It may have been set by OSABI initialization function. */
8211 if (tdep->num_ymm_regs == 0)
8213 tdep->ymmh_register_names = i386_ymmh_names;
8214 tdep->num_ymm_regs = 8;
8215 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
8218 for (i = 0; i < tdep->num_ymm_regs; i++)
8219 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
8220 tdep->ymm0h_regnum + i,
8221 tdep->ymmh_register_names[i]);
8223 else if (feature_sse)
8224 tdep->xcr0 = I386_XSTATE_SSE_MASK;
8227 tdep->xcr0 = I386_XSTATE_X87_MASK;
8228 tdep->num_xmm_regs = 0;
8231 num_regs = tdep->num_core_regs;
8232 for (i = 0; i < num_regs; i++)
8233 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
8234 tdep->register_names[i]);
8238 /* Need to include %mxcsr, so add one. */
8239 num_regs += tdep->num_xmm_regs + 1;
8240 for (; i < num_regs; i++)
8241 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
8242 tdep->register_names[i]);
8247 tdep->xcr0 |= I386_XSTATE_MPX_MASK;
8249 if (tdep->bnd0r_regnum < 0)
8251 tdep->mpx_register_names = i386_mpx_names;
8252 tdep->bnd0r_regnum = I386_BND0R_REGNUM;
8253 tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM;
8256 for (i = 0; i < I387_NUM_MPX_REGS; i++)
8257 valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data,
8258 I387_BND0R_REGNUM (tdep) + i,
8259 tdep->mpx_register_names[i]);
8266 static struct gdbarch *
8267 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8269 struct gdbarch_tdep *tdep;
8270 struct gdbarch *gdbarch;
8271 struct tdesc_arch_data *tdesc_data;
8272 const struct target_desc *tdesc;
8280 /* If there is already a candidate, use it. */
8281 arches = gdbarch_list_lookup_by_info (arches, &info);
8283 return arches->gdbarch;
8285 /* Allocate space for the new architecture. */
8286 tdep = XCNEW (struct gdbarch_tdep);
8287 gdbarch = gdbarch_alloc (&info, tdep);
8289 /* General-purpose registers. */
8290 tdep->gregset = NULL;
8291 tdep->gregset_reg_offset = NULL;
8292 tdep->gregset_num_regs = I386_NUM_GREGS;
8293 tdep->sizeof_gregset = 0;
8295 /* Floating-point registers. */
8296 tdep->fpregset = NULL;
8297 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
8299 tdep->xstateregset = NULL;
8301 /* The default settings include the FPU registers, the MMX registers
8302 and the SSE registers. This can be overridden for a specific ABI
8303 by adjusting the members `st0_regnum', `mm0_regnum' and
8304 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8305 will show up in the output of "info all-registers". */
8307 tdep->st0_regnum = I386_ST0_REGNUM;
8309 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8310 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
8312 tdep->jb_pc_offset = -1;
8313 tdep->struct_return = pcc_struct_return;
8314 tdep->sigtramp_start = 0;
8315 tdep->sigtramp_end = 0;
8316 tdep->sigtramp_p = i386_sigtramp_p;
8317 tdep->sigcontext_addr = NULL;
8318 tdep->sc_reg_offset = NULL;
8319 tdep->sc_pc_offset = -1;
8320 tdep->sc_sp_offset = -1;
8322 tdep->xsave_xcr0_offset = -1;
8324 tdep->record_regmap = i386_record_regmap;
8326 set_gdbarch_long_long_align_bit (gdbarch, 32);
8328 /* The format used for `long double' on almost all i386 targets is
8329 the i387 extended floating-point format. In fact, of all targets
8330 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8331 on having a `long double' that's not `long' at all. */
8332 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
8334 /* Although the i387 extended floating-point has only 80 significant
8335 bits, a `long double' actually takes up 96, probably to enforce
8337 set_gdbarch_long_double_bit (gdbarch, 96);
8339 /* Register numbers of various important registers. */
8340 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
8341 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
8342 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
8343 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
8345 /* NOTE: kettenis/20040418: GCC does have two possible register
8346 numbering schemes on the i386: dbx and SVR4. These schemes
8347 differ in how they number %ebp, %esp, %eflags, and the
8348 floating-point registers, and are implemented by the arrays
8349 dbx_register_map[] and svr4_dbx_register_map in
8350 gcc/config/i386.c. GCC also defines a third numbering scheme in
8351 gcc/config/i386.c, which it designates as the "default" register
8352 map used in 64bit mode. This last register numbering scheme is
8353 implemented in dbx64_register_map, and is used for AMD64; see
8356 Currently, each GCC i386 target always uses the same register
8357 numbering scheme across all its supported debugging formats
8358 i.e. SDB (COFF), stabs and DWARF 2. This is because
8359 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8360 DBX_REGISTER_NUMBER macro which is defined by each target's
8361 respective config header in a manner independent of the requested
8362 output debugging format.
8364 This does not match the arrangement below, which presumes that
8365 the SDB and stabs numbering schemes differ from the DWARF and
8366 DWARF 2 ones. The reason for this arrangement is that it is
8367 likely to get the numbering scheme for the target's
8368 default/native debug format right. For targets where GCC is the
8369 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8370 targets where the native toolchain uses a different numbering
8371 scheme for a particular debug format (stabs-in-ELF on Solaris)
8372 the defaults below will have to be overridden, like
8373 i386_elf_init_abi() does. */
8375 /* Use the dbx register numbering scheme for stabs and COFF. */
8376 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8377 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8379 /* Use the SVR4 register numbering scheme for DWARF 2. */
8380 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
8382 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8383 be in use on any of the supported i386 targets. */
8385 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
8387 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
8389 /* Call dummy code. */
8390 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
8391 set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code);
8392 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
8393 set_gdbarch_frame_align (gdbarch, i386_frame_align);
8395 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
8396 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
8397 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
8399 set_gdbarch_return_value (gdbarch, i386_return_value);
8401 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
8403 /* Stack grows downward. */
8404 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8406 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc);
8407 set_gdbarch_decr_pc_after_break (gdbarch, 1);
8408 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
8410 set_gdbarch_frame_args_skip (gdbarch, 8);
8412 set_gdbarch_print_insn (gdbarch, i386_print_insn);
8414 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
8416 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
8418 /* Add the i386 register groups. */
8419 i386_add_reggroups (gdbarch);
8420 tdep->register_reggroup_p = i386_register_reggroup_p;
8422 /* Helper for function argument information. */
8423 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
8425 /* Hook the function epilogue frame unwinder. This unwinder is
8426 appended to the list first, so that it supercedes the DWARF
8427 unwinder in function epilogues (where the DWARF unwinder
8428 currently fails). */
8429 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
8431 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8432 to the list before the prologue-based unwinders, so that DWARF
8433 CFI info will be used if it is available. */
8434 dwarf2_append_unwinders (gdbarch);
8436 frame_base_set_default (gdbarch, &i386_frame_base);
8438 /* Pseudo registers may be changed by amd64_init_abi. */
8439 set_gdbarch_pseudo_register_read_value (gdbarch,
8440 i386_pseudo_register_read_value);
8441 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
8443 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
8444 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
8446 /* Override the normal target description method to make the AVX
8447 upper halves anonymous. */
8448 set_gdbarch_register_name (gdbarch, i386_register_name);
8450 /* Even though the default ABI only includes general-purpose registers,
8451 floating-point registers and the SSE registers, we have to leave a
8452 gap for the upper AVX, MPX and AVX512 registers. */
8453 set_gdbarch_num_regs (gdbarch, I386_AVX512_NUM_REGS);
8455 /* Get the x86 target description from INFO. */
8456 tdesc = info.target_desc;
8457 if (! tdesc_has_registers (tdesc))
8459 tdep->tdesc = tdesc;
8461 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
8462 tdep->register_names = i386_register_names;
8464 /* No upper YMM registers. */
8465 tdep->ymmh_register_names = NULL;
8466 tdep->ymm0h_regnum = -1;
8468 /* No upper ZMM registers. */
8469 tdep->zmmh_register_names = NULL;
8470 tdep->zmm0h_regnum = -1;
8472 /* No high XMM registers. */
8473 tdep->xmm_avx512_register_names = NULL;
8474 tdep->xmm16_regnum = -1;
8476 /* No upper YMM16-31 registers. */
8477 tdep->ymm16h_register_names = NULL;
8478 tdep->ymm16h_regnum = -1;
8480 tdep->num_byte_regs = 8;
8481 tdep->num_word_regs = 8;
8482 tdep->num_dword_regs = 0;
8483 tdep->num_mmx_regs = 8;
8484 tdep->num_ymm_regs = 0;
8486 /* No MPX registers. */
8487 tdep->bnd0r_regnum = -1;
8488 tdep->bndcfgu_regnum = -1;
8490 /* No AVX512 registers. */
8491 tdep->k0_regnum = -1;
8492 tdep->num_zmm_regs = 0;
8493 tdep->num_ymm_avx512_regs = 0;
8494 tdep->num_xmm_avx512_regs = 0;
8496 tdesc_data = tdesc_data_alloc ();
8498 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
8500 set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address);
8502 set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call);
8503 set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret);
8504 set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump);
8506 /* Hook in ABI-specific overrides, if they have been registered. */
8507 info.tdep_info = (void *) tdesc_data;
8508 gdbarch_init_osabi (info, gdbarch);
8510 if (!i386_validate_tdesc_p (tdep, tdesc_data))
8512 tdesc_data_cleanup (tdesc_data);
8514 gdbarch_free (gdbarch);
8518 num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0);
8520 /* Wire in pseudo registers. Number of pseudo registers may be
8522 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
8523 + tdep->num_word_regs
8524 + tdep->num_dword_regs
8525 + tdep->num_mmx_regs
8526 + tdep->num_ymm_regs
8528 + tdep->num_ymm_avx512_regs
8529 + tdep->num_zmm_regs));
8531 /* Target description may be changed. */
8532 tdesc = tdep->tdesc;
8534 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
8536 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8537 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
8539 /* Make %al the first pseudo-register. */
8540 tdep->al_regnum = gdbarch_num_regs (gdbarch);
8541 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
8543 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
8544 if (tdep->num_dword_regs)
8546 /* Support dword pseudo-register if it hasn't been disabled. */
8547 tdep->eax_regnum = ymm0_regnum;
8548 ymm0_regnum += tdep->num_dword_regs;
8551 tdep->eax_regnum = -1;
8553 mm0_regnum = ymm0_regnum;
8554 if (tdep->num_ymm_regs)
8556 /* Support YMM pseudo-register if it is available. */
8557 tdep->ymm0_regnum = ymm0_regnum;
8558 mm0_regnum += tdep->num_ymm_regs;
8561 tdep->ymm0_regnum = -1;
8563 if (tdep->num_ymm_avx512_regs)
8565 /* Support YMM16-31 pseudo registers if available. */
8566 tdep->ymm16_regnum = mm0_regnum;
8567 mm0_regnum += tdep->num_ymm_avx512_regs;
8570 tdep->ymm16_regnum = -1;
8572 if (tdep->num_zmm_regs)
8574 /* Support ZMM pseudo-register if it is available. */
8575 tdep->zmm0_regnum = mm0_regnum;
8576 mm0_regnum += tdep->num_zmm_regs;
8579 tdep->zmm0_regnum = -1;
8581 bnd0_regnum = mm0_regnum;
8582 if (tdep->num_mmx_regs != 0)
8584 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8585 tdep->mm0_regnum = mm0_regnum;
8586 bnd0_regnum += tdep->num_mmx_regs;
8589 tdep->mm0_regnum = -1;
8591 if (tdep->bnd0r_regnum > 0)
8592 tdep->bnd0_regnum = bnd0_regnum;
8594 tdep-> bnd0_regnum = -1;
8596 /* Hook in the legacy prologue-based unwinders last (fallback). */
8597 frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind);
8598 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
8599 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
8601 /* If we have a register mapping, enable the generic core file
8602 support, unless it has already been enabled. */
8603 if (tdep->gregset_reg_offset
8604 && !gdbarch_regset_from_core_section_p (gdbarch))
8605 set_gdbarch_regset_from_core_section (gdbarch,
8606 i386_regset_from_core_section);
8608 set_gdbarch_skip_permanent_breakpoint (gdbarch,
8609 i386_skip_permanent_breakpoint);
8611 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
8612 i386_fast_tracepoint_valid_at);
8617 static enum gdb_osabi
8618 i386_coff_osabi_sniffer (bfd *abfd)
8620 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
8621 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
8622 return GDB_OSABI_GO32;
8624 return GDB_OSABI_UNKNOWN;
8628 /* Provide a prototype to silence -Wmissing-prototypes. */
8629 void _initialize_i386_tdep (void);
8632 _initialize_i386_tdep (void)
8634 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
8636 /* Add the variable that controls the disassembly flavor. */
8637 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
8638 &disassembly_flavor, _("\
8639 Set the disassembly flavor."), _("\
8640 Show the disassembly flavor."), _("\
8641 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
8643 NULL, /* FIXME: i18n: */
8644 &setlist, &showlist);
8646 /* Add the variable that controls the convention for returning
8648 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
8649 &struct_convention, _("\
8650 Set the convention for returning small structs."), _("\
8651 Show the convention for returning small structs."), _("\
8652 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
8655 NULL, /* FIXME: i18n: */
8656 &setlist, &showlist);
8658 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
8659 i386_coff_osabi_sniffer);
8661 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
8662 i386_svr4_init_abi);
8663 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
8664 i386_go32_init_abi);
8666 /* Initialize the i386-specific register groups. */
8667 i386_init_reggroups ();
8669 /* Initialize the standard target descriptions. */
8670 initialize_tdesc_i386 ();
8671 initialize_tdesc_i386_mmx ();
8672 initialize_tdesc_i386_avx ();
8673 initialize_tdesc_i386_mpx ();
8674 initialize_tdesc_i386_avx512 ();
8676 /* Tell remote stub that we support XML target description. */
8677 register_remote_support_xml ("i386");