1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010, 2011 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
49 #include "gdb_assert.h"
50 #include "gdb_string.h"
52 #include "i386-tdep.h"
53 #include "i387-tdep.h"
54 #include "i386-xstate.h"
59 #include "features/i386/i386.c"
60 #include "features/i386/i386-avx.c"
61 #include "features/i386/i386-mmx.c"
65 static const char *i386_register_names[] =
67 "eax", "ecx", "edx", "ebx",
68 "esp", "ebp", "esi", "edi",
69 "eip", "eflags", "cs", "ss",
70 "ds", "es", "fs", "gs",
71 "st0", "st1", "st2", "st3",
72 "st4", "st5", "st6", "st7",
73 "fctrl", "fstat", "ftag", "fiseg",
74 "fioff", "foseg", "fooff", "fop",
75 "xmm0", "xmm1", "xmm2", "xmm3",
76 "xmm4", "xmm5", "xmm6", "xmm7",
80 static const char *i386_ymm_names[] =
82 "ymm0", "ymm1", "ymm2", "ymm3",
83 "ymm4", "ymm5", "ymm6", "ymm7",
86 static const char *i386_ymmh_names[] =
88 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
89 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
92 /* Register names for MMX pseudo-registers. */
94 static const char *i386_mmx_names[] =
96 "mm0", "mm1", "mm2", "mm3",
97 "mm4", "mm5", "mm6", "mm7"
100 /* Register names for byte pseudo-registers. */
102 static const char *i386_byte_names[] =
104 "al", "cl", "dl", "bl",
105 "ah", "ch", "dh", "bh"
108 /* Register names for word pseudo-registers. */
110 static const char *i386_word_names[] =
112 "ax", "cx", "dx", "bx",
119 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
121 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
122 int mm0_regnum = tdep->mm0_regnum;
127 regnum -= mm0_regnum;
128 return regnum >= 0 && regnum < tdep->num_mmx_regs;
134 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
136 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
138 regnum -= tdep->al_regnum;
139 return regnum >= 0 && regnum < tdep->num_byte_regs;
145 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
147 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
149 regnum -= tdep->ax_regnum;
150 return regnum >= 0 && regnum < tdep->num_word_regs;
153 /* Dword register? */
156 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
158 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
159 int eax_regnum = tdep->eax_regnum;
164 regnum -= eax_regnum;
165 return regnum >= 0 && regnum < tdep->num_dword_regs;
169 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
171 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
172 int ymm0h_regnum = tdep->ymm0h_regnum;
174 if (ymm0h_regnum < 0)
177 regnum -= ymm0h_regnum;
178 return regnum >= 0 && regnum < tdep->num_ymm_regs;
184 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
186 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
187 int ymm0_regnum = tdep->ymm0_regnum;
192 regnum -= ymm0_regnum;
193 return regnum >= 0 && regnum < tdep->num_ymm_regs;
199 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
201 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
202 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
204 if (num_xmm_regs == 0)
207 regnum -= I387_XMM0_REGNUM (tdep);
208 return regnum >= 0 && regnum < num_xmm_regs;
212 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
214 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
216 if (I387_NUM_XMM_REGS (tdep) == 0)
219 return (regnum == I387_MXCSR_REGNUM (tdep));
225 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
227 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
229 if (I387_ST0_REGNUM (tdep) < 0)
232 return (I387_ST0_REGNUM (tdep) <= regnum
233 && regnum < I387_FCTRL_REGNUM (tdep));
237 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
239 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
241 if (I387_ST0_REGNUM (tdep) < 0)
244 return (I387_FCTRL_REGNUM (tdep) <= regnum
245 && regnum < I387_XMM0_REGNUM (tdep));
248 /* Return the name of register REGNUM, or the empty string if it is
249 an anonymous register. */
252 i386_register_name (struct gdbarch *gdbarch, int regnum)
254 /* Hide the upper YMM registers. */
255 if (i386_ymmh_regnum_p (gdbarch, regnum))
258 return tdesc_register_name (gdbarch, regnum);
261 /* Return the name of register REGNUM. */
264 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
266 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
267 if (i386_mmx_regnum_p (gdbarch, regnum))
268 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
269 else if (i386_ymm_regnum_p (gdbarch, regnum))
270 return i386_ymm_names[regnum - tdep->ymm0_regnum];
271 else if (i386_byte_regnum_p (gdbarch, regnum))
272 return i386_byte_names[regnum - tdep->al_regnum];
273 else if (i386_word_regnum_p (gdbarch, regnum))
274 return i386_word_names[regnum - tdep->ax_regnum];
276 internal_error (__FILE__, __LINE__, _("invalid regnum"));
279 /* Convert a dbx register number REG to the appropriate register
280 number used by GDB. */
283 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
285 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
287 /* This implements what GCC calls the "default" register map
288 (dbx_register_map[]). */
290 if (reg >= 0 && reg <= 7)
292 /* General-purpose registers. The debug info calls %ebp
293 register 4, and %esp register 5. */
300 else if (reg >= 12 && reg <= 19)
302 /* Floating-point registers. */
303 return reg - 12 + I387_ST0_REGNUM (tdep);
305 else if (reg >= 21 && reg <= 28)
308 int ymm0_regnum = tdep->ymm0_regnum;
311 && i386_xmm_regnum_p (gdbarch, reg))
312 return reg - 21 + ymm0_regnum;
314 return reg - 21 + I387_XMM0_REGNUM (tdep);
316 else if (reg >= 29 && reg <= 36)
319 return reg - 29 + I387_MM0_REGNUM (tdep);
322 /* This will hopefully provoke a warning. */
323 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
326 /* Convert SVR4 register number REG to the appropriate register number
330 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
332 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
334 /* This implements the GCC register map that tries to be compatible
335 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
337 /* The SVR4 register numbering includes %eip and %eflags, and
338 numbers the floating point registers differently. */
339 if (reg >= 0 && reg <= 9)
341 /* General-purpose registers. */
344 else if (reg >= 11 && reg <= 18)
346 /* Floating-point registers. */
347 return reg - 11 + I387_ST0_REGNUM (tdep);
349 else if (reg >= 21 && reg <= 36)
351 /* The SSE and MMX registers have the same numbers as with dbx. */
352 return i386_dbx_reg_to_regnum (gdbarch, reg);
357 case 37: return I387_FCTRL_REGNUM (tdep);
358 case 38: return I387_FSTAT_REGNUM (tdep);
359 case 39: return I387_MXCSR_REGNUM (tdep);
360 case 40: return I386_ES_REGNUM;
361 case 41: return I386_CS_REGNUM;
362 case 42: return I386_SS_REGNUM;
363 case 43: return I386_DS_REGNUM;
364 case 44: return I386_FS_REGNUM;
365 case 45: return I386_GS_REGNUM;
368 /* This will hopefully provoke a warning. */
369 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
374 /* This is the variable that is set with "set disassembly-flavor", and
375 its legitimate values. */
376 static const char att_flavor[] = "att";
377 static const char intel_flavor[] = "intel";
378 static const char *valid_flavors[] =
384 static const char *disassembly_flavor = att_flavor;
387 /* Use the program counter to determine the contents and size of a
388 breakpoint instruction. Return a pointer to a string of bytes that
389 encode a breakpoint instruction, store the length of the string in
390 *LEN and optionally adjust *PC to point to the correct memory
391 location for inserting the breakpoint.
393 On the i386 we have a single breakpoint that fits in a single byte
394 and can be inserted anywhere.
396 This function is 64-bit safe. */
398 static const gdb_byte *
399 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
401 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */
403 *len = sizeof (break_insn);
407 /* Displaced instruction handling. */
409 /* Skip the legacy instruction prefixes in INSN.
410 Not all prefixes are valid for any particular insn
411 but we needn't care, the insn will fault if it's invalid.
412 The result is a pointer to the first opcode byte,
413 or NULL if we run off the end of the buffer. */
416 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
418 gdb_byte *end = insn + max_len;
424 case DATA_PREFIX_OPCODE:
425 case ADDR_PREFIX_OPCODE:
426 case CS_PREFIX_OPCODE:
427 case DS_PREFIX_OPCODE:
428 case ES_PREFIX_OPCODE:
429 case FS_PREFIX_OPCODE:
430 case GS_PREFIX_OPCODE:
431 case SS_PREFIX_OPCODE:
432 case LOCK_PREFIX_OPCODE:
433 case REPE_PREFIX_OPCODE:
434 case REPNE_PREFIX_OPCODE:
446 i386_absolute_jmp_p (const gdb_byte *insn)
448 /* jmp far (absolute address in operand). */
454 /* jump near, absolute indirect (/4). */
455 if ((insn[1] & 0x38) == 0x20)
458 /* jump far, absolute indirect (/5). */
459 if ((insn[1] & 0x38) == 0x28)
467 i386_absolute_call_p (const gdb_byte *insn)
469 /* call far, absolute. */
475 /* Call near, absolute indirect (/2). */
476 if ((insn[1] & 0x38) == 0x10)
479 /* Call far, absolute indirect (/3). */
480 if ((insn[1] & 0x38) == 0x18)
488 i386_ret_p (const gdb_byte *insn)
492 case 0xc2: /* ret near, pop N bytes. */
493 case 0xc3: /* ret near */
494 case 0xca: /* ret far, pop N bytes. */
495 case 0xcb: /* ret far */
496 case 0xcf: /* iret */
505 i386_call_p (const gdb_byte *insn)
507 if (i386_absolute_call_p (insn))
510 /* call near, relative. */
517 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
518 length in bytes. Otherwise, return zero. */
521 i386_syscall_p (const gdb_byte *insn, int *lengthp)
532 /* Some kernels may run one past a syscall insn, so we have to cope.
533 Otherwise this is just simple_displaced_step_copy_insn. */
535 struct displaced_step_closure *
536 i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
537 CORE_ADDR from, CORE_ADDR to,
538 struct regcache *regs)
540 size_t len = gdbarch_max_insn_length (gdbarch);
541 gdb_byte *buf = xmalloc (len);
543 read_memory (from, buf, len);
545 /* GDB may get control back after the insn after the syscall.
546 Presumably this is a kernel bug.
547 If this is a syscall, make sure there's a nop afterwards. */
552 insn = i386_skip_prefixes (buf, len);
553 if (insn != NULL && i386_syscall_p (insn, &syscall_length))
554 insn[syscall_length] = NOP_OPCODE;
557 write_memory (to, buf, len);
561 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
562 paddress (gdbarch, from), paddress (gdbarch, to));
563 displaced_step_dump_bytes (gdb_stdlog, buf, len);
566 return (struct displaced_step_closure *) buf;
569 /* Fix up the state of registers and memory after having single-stepped
570 a displaced instruction. */
573 i386_displaced_step_fixup (struct gdbarch *gdbarch,
574 struct displaced_step_closure *closure,
575 CORE_ADDR from, CORE_ADDR to,
576 struct regcache *regs)
578 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
580 /* The offset we applied to the instruction's address.
581 This could well be negative (when viewed as a signed 32-bit
582 value), but ULONGEST won't reflect that, so take care when
584 ULONGEST insn_offset = to - from;
586 /* Since we use simple_displaced_step_copy_insn, our closure is a
587 copy of the instruction. */
588 gdb_byte *insn = (gdb_byte *) closure;
589 /* The start of the insn, needed in case we see some prefixes. */
590 gdb_byte *insn_start = insn;
593 fprintf_unfiltered (gdb_stdlog,
594 "displaced: fixup (%s, %s), "
595 "insn = 0x%02x 0x%02x ...\n",
596 paddress (gdbarch, from), paddress (gdbarch, to),
599 /* The list of issues to contend with here is taken from
600 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
601 Yay for Free Software! */
603 /* Relocate the %eip, if necessary. */
605 /* The instruction recognizers we use assume any leading prefixes
606 have been skipped. */
608 /* This is the size of the buffer in closure. */
609 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
610 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
611 /* If there are too many prefixes, just ignore the insn.
612 It will fault when run. */
617 /* Except in the case of absolute or indirect jump or call
618 instructions, or a return instruction, the new eip is relative to
619 the displaced instruction; make it relative. Well, signal
620 handler returns don't need relocation either, but we use the
621 value of %eip to recognize those; see below. */
622 if (! i386_absolute_jmp_p (insn)
623 && ! i386_absolute_call_p (insn)
624 && ! i386_ret_p (insn))
629 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
631 /* A signal trampoline system call changes the %eip, resuming
632 execution of the main program after the signal handler has
633 returned. That makes them like 'return' instructions; we
634 shouldn't relocate %eip.
636 But most system calls don't, and we do need to relocate %eip.
638 Our heuristic for distinguishing these cases: if stepping
639 over the system call instruction left control directly after
640 the instruction, the we relocate --- control almost certainly
641 doesn't belong in the displaced copy. Otherwise, we assume
642 the instruction has put control where it belongs, and leave
643 it unrelocated. Goodness help us if there are PC-relative
645 if (i386_syscall_p (insn, &insn_len)
646 && orig_eip != to + (insn - insn_start) + insn_len
647 /* GDB can get control back after the insn after the syscall.
648 Presumably this is a kernel bug.
649 i386_displaced_step_copy_insn ensures its a nop,
650 we add one to the length for it. */
651 && orig_eip != to + (insn - insn_start) + insn_len + 1)
654 fprintf_unfiltered (gdb_stdlog,
655 "displaced: syscall changed %%eip; "
660 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
662 /* If we just stepped over a breakpoint insn, we don't backup
663 the pc on purpose; this is to match behaviour without
666 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
669 fprintf_unfiltered (gdb_stdlog,
671 "relocated %%eip from %s to %s\n",
672 paddress (gdbarch, orig_eip),
673 paddress (gdbarch, eip));
677 /* If the instruction was PUSHFL, then the TF bit will be set in the
678 pushed value, and should be cleared. We'll leave this for later,
679 since GDB already messes up the TF flag when stepping over a
682 /* If the instruction was a call, the return address now atop the
683 stack is the address following the copied instruction. We need
684 to make it the address following the original instruction. */
685 if (i386_call_p (insn))
689 const ULONGEST retaddr_len = 4;
691 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
692 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
693 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
694 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
697 fprintf_unfiltered (gdb_stdlog,
698 "displaced: relocated return addr at %s to %s\n",
699 paddress (gdbarch, esp),
700 paddress (gdbarch, retaddr));
705 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
707 target_write_memory (*to, buf, len);
712 i386_relocate_instruction (struct gdbarch *gdbarch,
713 CORE_ADDR *to, CORE_ADDR oldloc)
715 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
716 gdb_byte buf[I386_MAX_INSN_LEN];
717 int offset = 0, rel32, newrel;
719 gdb_byte *insn = buf;
721 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
723 insn_length = gdb_buffered_insn_length (gdbarch, insn,
724 I386_MAX_INSN_LEN, oldloc);
726 /* Get past the prefixes. */
727 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
729 /* Adjust calls with 32-bit relative addresses as push/jump, with
730 the address pushed being the location where the original call in
731 the user program would return to. */
734 gdb_byte push_buf[16];
735 unsigned int ret_addr;
737 /* Where "ret" in the original code will return to. */
738 ret_addr = oldloc + insn_length;
739 push_buf[0] = 0x68; /* pushq $... */
740 memcpy (&push_buf[1], &ret_addr, 4);
742 append_insns (to, 5, push_buf);
744 /* Convert the relative call to a relative jump. */
747 /* Adjust the destination offset. */
748 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
749 newrel = (oldloc - *to) + rel32;
750 store_signed_integer (insn + 1, 4, byte_order, newrel);
753 fprintf_unfiltered (gdb_stdlog,
754 "Adjusted insn rel32=%s at %s to"
756 hex_string (rel32), paddress (gdbarch, oldloc),
757 hex_string (newrel), paddress (gdbarch, *to));
759 /* Write the adjusted jump into its displaced location. */
760 append_insns (to, 5, insn);
764 /* Adjust jumps with 32-bit relative addresses. Calls are already
768 /* Adjust conditional jumps. */
769 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
774 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
775 newrel = (oldloc - *to) + rel32;
776 store_signed_integer (insn + offset, 4, byte_order, newrel);
778 fprintf_unfiltered (gdb_stdlog,
779 "Adjusted insn rel32=%s at %s to"
781 hex_string (rel32), paddress (gdbarch, oldloc),
782 hex_string (newrel), paddress (gdbarch, *to));
785 /* Write the adjusted instructions into their displaced
787 append_insns (to, insn_length, buf);
791 #ifdef I386_REGNO_TO_SYMMETRY
792 #error "The Sequent Symmetry is no longer supported."
795 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
796 and %esp "belong" to the calling function. Therefore these
797 registers should be saved if they're going to be modified. */
799 /* The maximum number of saved registers. This should include all
800 registers mentioned above, and %eip. */
801 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
803 struct i386_frame_cache
810 /* Saved registers. */
811 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
816 /* Stack space reserved for local variables. */
820 /* Allocate and initialize a frame cache. */
822 static struct i386_frame_cache *
823 i386_alloc_frame_cache (void)
825 struct i386_frame_cache *cache;
828 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
832 cache->sp_offset = -4;
835 /* Saved registers. We initialize these to -1 since zero is a valid
836 offset (that's where %ebp is supposed to be stored). */
837 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
838 cache->saved_regs[i] = -1;
840 cache->saved_sp_reg = -1;
841 cache->pc_in_eax = 0;
843 /* Frameless until proven otherwise. */
849 /* If the instruction at PC is a jump, return the address of its
850 target. Otherwise, return PC. */
853 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
855 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
860 if (target_read_memory (pc, &op, 1))
866 op = read_memory_unsigned_integer (pc + 1, 1, byte_order);
872 /* Relative jump: if data16 == 0, disp32, else disp16. */
875 delta = read_memory_integer (pc + 2, 2, byte_order);
877 /* Include the size of the jmp instruction (including the
883 delta = read_memory_integer (pc + 1, 4, byte_order);
885 /* Include the size of the jmp instruction. */
890 /* Relative jump, disp8 (ignore data16). */
891 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
900 /* Check whether PC points at a prologue for a function returning a
901 structure or union. If so, it updates CACHE and returns the
902 address of the first instruction after the code sequence that
903 removes the "hidden" argument from the stack or CURRENT_PC,
904 whichever is smaller. Otherwise, return PC. */
907 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
908 struct i386_frame_cache *cache)
910 /* Functions that return a structure or union start with:
913 xchgl %eax, (%esp) 0x87 0x04 0x24
914 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
916 (the System V compiler puts out the second `xchg' instruction,
917 and the assembler doesn't try to optimize it, so the 'sib' form
918 gets generated). This sequence is used to get the address of the
919 return buffer for a function that returns a structure. */
920 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
921 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
925 if (current_pc <= pc)
928 if (target_read_memory (pc, &op, 1))
931 if (op != 0x58) /* popl %eax */
934 if (target_read_memory (pc + 1, buf, 4))
937 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
940 if (current_pc == pc)
942 cache->sp_offset += 4;
946 if (current_pc == pc + 1)
948 cache->pc_in_eax = 1;
952 if (buf[1] == proto1[1])
959 i386_skip_probe (CORE_ADDR pc)
961 /* A function may start with
975 if (target_read_memory (pc, &op, 1))
978 if (op == 0x68 || op == 0x6a)
982 /* Skip past the `pushl' instruction; it has either a one-byte or a
983 four-byte operand, depending on the opcode. */
989 /* Read the following 8 bytes, which should be `call _probe' (6
990 bytes) followed by `addl $4,%esp' (2 bytes). */
991 read_memory (pc + delta, buf, sizeof (buf));
992 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
993 pc += delta + sizeof (buf);
999 /* GCC 4.1 and later, can put code in the prologue to realign the
1000 stack pointer. Check whether PC points to such code, and update
1001 CACHE accordingly. Return the first instruction after the code
1002 sequence or CURRENT_PC, whichever is smaller. If we don't
1003 recognize the code, return PC. */
1006 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1007 struct i386_frame_cache *cache)
1009 /* There are 2 code sequences to re-align stack before the frame
1012 1. Use a caller-saved saved register:
1018 2. Use a callee-saved saved register:
1025 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1027 0x83 0xe4 0xf0 andl $-16, %esp
1028 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1033 int offset, offset_and;
1034 static int regnums[8] = {
1035 I386_EAX_REGNUM, /* %eax */
1036 I386_ECX_REGNUM, /* %ecx */
1037 I386_EDX_REGNUM, /* %edx */
1038 I386_EBX_REGNUM, /* %ebx */
1039 I386_ESP_REGNUM, /* %esp */
1040 I386_EBP_REGNUM, /* %ebp */
1041 I386_ESI_REGNUM, /* %esi */
1042 I386_EDI_REGNUM /* %edi */
1045 if (target_read_memory (pc, buf, sizeof buf))
1048 /* Check caller-saved saved register. The first instruction has
1049 to be "leal 4(%esp), %reg". */
1050 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1052 /* MOD must be binary 10 and R/M must be binary 100. */
1053 if ((buf[1] & 0xc7) != 0x44)
1056 /* REG has register number. */
1057 reg = (buf[1] >> 3) & 7;
1062 /* Check callee-saved saved register. The first instruction
1063 has to be "pushl %reg". */
1064 if ((buf[0] & 0xf8) != 0x50)
1070 /* The next instruction has to be "leal 8(%esp), %reg". */
1071 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1074 /* MOD must be binary 10 and R/M must be binary 100. */
1075 if ((buf[2] & 0xc7) != 0x44)
1078 /* REG has register number. Registers in pushl and leal have to
1080 if (reg != ((buf[2] >> 3) & 7))
1086 /* Rigister can't be %esp nor %ebp. */
1087 if (reg == 4 || reg == 5)
1090 /* The next instruction has to be "andl $-XXX, %esp". */
1091 if (buf[offset + 1] != 0xe4
1092 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1095 offset_and = offset;
1096 offset += buf[offset] == 0x81 ? 6 : 3;
1098 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1099 0xfc. REG must be binary 110 and MOD must be binary 01. */
1100 if (buf[offset] != 0xff
1101 || buf[offset + 2] != 0xfc
1102 || (buf[offset + 1] & 0xf8) != 0x70)
1105 /* R/M has register. Registers in leal and pushl have to be the
1107 if (reg != (buf[offset + 1] & 7))
1110 if (current_pc > pc + offset_and)
1111 cache->saved_sp_reg = regnums[reg];
1113 return min (pc + offset + 3, current_pc);
1116 /* Maximum instruction length we need to handle. */
1117 #define I386_MAX_MATCHED_INSN_LEN 6
1119 /* Instruction description. */
1123 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
1124 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
1127 /* Search for the instruction at PC in the list SKIP_INSNS. Return
1128 the first instruction description that matches. Otherwise, return
1131 static struct i386_insn *
1132 i386_match_insn (CORE_ADDR pc, struct i386_insn *skip_insns)
1134 struct i386_insn *insn;
1137 if (target_read_memory (pc, &op, 1))
1140 for (insn = skip_insns; insn->len > 0; insn++)
1142 if ((op & insn->mask[0]) == insn->insn[0])
1144 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1145 int insn_matched = 1;
1148 gdb_assert (insn->len > 1);
1149 gdb_assert (insn->len <= I386_MAX_MATCHED_INSN_LEN);
1151 if (target_read_memory (pc + 1, buf, insn->len - 1))
1154 for (i = 1; i < insn->len; i++)
1156 if ((buf[i - 1] & insn->mask[i]) != insn->insn[i])
1168 /* Some special instructions that might be migrated by GCC into the
1169 part of the prologue that sets up the new stack frame. Because the
1170 stack frame hasn't been setup yet, no registers have been saved
1171 yet, and only the scratch registers %eax, %ecx and %edx can be
1174 struct i386_insn i386_frame_setup_skip_insns[] =
1176 /* Check for `movb imm8, r' and `movl imm32, r'.
1178 ??? Should we handle 16-bit operand-sizes here? */
1180 /* `movb imm8, %al' and `movb imm8, %ah' */
1181 /* `movb imm8, %cl' and `movb imm8, %ch' */
1182 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1183 /* `movb imm8, %dl' and `movb imm8, %dh' */
1184 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1185 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1186 { 5, { 0xb8 }, { 0xfe } },
1187 /* `movl imm32, %edx' */
1188 { 5, { 0xba }, { 0xff } },
1190 /* Check for `mov imm32, r32'. Note that there is an alternative
1191 encoding for `mov m32, %eax'.
1193 ??? Should we handle SIB adressing here?
1194 ??? Should we handle 16-bit operand-sizes here? */
1196 /* `movl m32, %eax' */
1197 { 5, { 0xa1 }, { 0xff } },
1198 /* `movl m32, %eax' and `mov; m32, %ecx' */
1199 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1200 /* `movl m32, %edx' */
1201 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1203 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1204 Because of the symmetry, there are actually two ways to encode
1205 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1206 opcode bytes 0x31 and 0x33 for `xorl'. */
1208 /* `subl %eax, %eax' */
1209 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1210 /* `subl %ecx, %ecx' */
1211 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1212 /* `subl %edx, %edx' */
1213 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1214 /* `xorl %eax, %eax' */
1215 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1216 /* `xorl %ecx, %ecx' */
1217 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1218 /* `xorl %edx, %edx' */
1219 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1224 /* Check whether PC points to a no-op instruction. */
1226 i386_skip_noop (CORE_ADDR pc)
1231 if (target_read_memory (pc, &op, 1))
1237 /* Ignore `nop' instruction. */
1241 if (target_read_memory (pc, &op, 1))
1245 /* Ignore no-op instruction `mov %edi, %edi'.
1246 Microsoft system dlls often start with
1247 a `mov %edi,%edi' instruction.
1248 The 5 bytes before the function start are
1249 filled with `nop' instructions.
1250 This pattern can be used for hot-patching:
1251 The `mov %edi, %edi' instruction can be replaced by a
1252 near jump to the location of the 5 `nop' instructions
1253 which can be replaced by a 32-bit jump to anywhere
1254 in the 32-bit address space. */
1256 else if (op == 0x8b)
1258 if (target_read_memory (pc + 1, &op, 1))
1264 if (target_read_memory (pc, &op, 1))
1274 /* Check whether PC points at a code that sets up a new stack frame.
1275 If so, it updates CACHE and returns the address of the first
1276 instruction after the sequence that sets up the frame or LIMIT,
1277 whichever is smaller. If we don't recognize the code, return PC. */
1280 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1281 CORE_ADDR pc, CORE_ADDR limit,
1282 struct i386_frame_cache *cache)
1284 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1285 struct i386_insn *insn;
1292 if (target_read_memory (pc, &op, 1))
1295 if (op == 0x55) /* pushl %ebp */
1297 /* Take into account that we've executed the `pushl %ebp' that
1298 starts this instruction sequence. */
1299 cache->saved_regs[I386_EBP_REGNUM] = 0;
1300 cache->sp_offset += 4;
1303 /* If that's all, return now. */
1307 /* Check for some special instructions that might be migrated by
1308 GCC into the prologue and skip them. At this point in the
1309 prologue, code should only touch the scratch registers %eax,
1310 %ecx and %edx, so while the number of posibilities is sheer,
1313 Make sure we only skip these instructions if we later see the
1314 `movl %esp, %ebp' that actually sets up the frame. */
1315 while (pc + skip < limit)
1317 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1324 /* If that's all, return now. */
1325 if (limit <= pc + skip)
1328 if (target_read_memory (pc + skip, &op, 1))
1331 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1335 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1340 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1348 /* OK, we actually have a frame. We just don't know how large
1349 it is yet. Set its size to zero. We'll adjust it if
1350 necessary. We also now commit to skipping the special
1351 instructions mentioned before. */
1355 /* If that's all, return now. */
1359 /* Check for stack adjustment
1363 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1364 reg, so we don't have to worry about a data16 prefix. */
1365 if (target_read_memory (pc, &op, 1))
1369 /* `subl' with 8-bit immediate. */
1370 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1371 /* Some instruction starting with 0x83 other than `subl'. */
1374 /* `subl' with signed 8-bit immediate (though it wouldn't
1375 make sense to be negative). */
1376 cache->locals = read_memory_integer (pc + 2, 1, byte_order);
1379 else if (op == 0x81)
1381 /* Maybe it is `subl' with a 32-bit immediate. */
1382 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1383 /* Some instruction starting with 0x81 other than `subl'. */
1386 /* It is `subl' with a 32-bit immediate. */
1387 cache->locals = read_memory_integer (pc + 2, 4, byte_order);
1392 /* Some instruction other than `subl'. */
1396 else if (op == 0xc8) /* enter */
1398 cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order);
1405 /* Check whether PC points at code that saves registers on the stack.
1406 If so, it updates CACHE and returns the address of the first
1407 instruction after the register saves or CURRENT_PC, whichever is
1408 smaller. Otherwise, return PC. */
1411 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1412 struct i386_frame_cache *cache)
1414 CORE_ADDR offset = 0;
1418 if (cache->locals > 0)
1419 offset -= cache->locals;
1420 for (i = 0; i < 8 && pc < current_pc; i++)
1422 if (target_read_memory (pc, &op, 1))
1424 if (op < 0x50 || op > 0x57)
1428 cache->saved_regs[op - 0x50] = offset;
1429 cache->sp_offset += 4;
1436 /* Do a full analysis of the prologue at PC and update CACHE
1437 accordingly. Bail out early if CURRENT_PC is reached. Return the
1438 address where the analysis stopped.
1440 We handle these cases:
1442 The startup sequence can be at the start of the function, or the
1443 function can start with a branch to startup code at the end.
1445 %ebp can be set up with either the 'enter' instruction, or "pushl
1446 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1447 once used in the System V compiler).
1449 Local space is allocated just below the saved %ebp by either the
1450 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1451 16-bit unsigned argument for space to allocate, and the 'addl'
1452 instruction could have either a signed byte, or 32-bit immediate.
1454 Next, the registers used by this function are pushed. With the
1455 System V compiler they will always be in the order: %edi, %esi,
1456 %ebx (and sometimes a harmless bug causes it to also save but not
1457 restore %eax); however, the code below is willing to see the pushes
1458 in any order, and will handle up to 8 of them.
1460 If the setup sequence is at the end of the function, then the next
1461 instruction will be a branch back to the start. */
1464 i386_analyze_prologue (struct gdbarch *gdbarch,
1465 CORE_ADDR pc, CORE_ADDR current_pc,
1466 struct i386_frame_cache *cache)
1468 pc = i386_skip_noop (pc);
1469 pc = i386_follow_jump (gdbarch, pc);
1470 pc = i386_analyze_struct_return (pc, current_pc, cache);
1471 pc = i386_skip_probe (pc);
1472 pc = i386_analyze_stack_align (pc, current_pc, cache);
1473 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1474 return i386_analyze_register_saves (pc, current_pc, cache);
1477 /* Return PC of first real instruction. */
1480 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1482 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1484 static gdb_byte pic_pat[6] =
1486 0xe8, 0, 0, 0, 0, /* call 0x0 */
1487 0x5b, /* popl %ebx */
1489 struct i386_frame_cache cache;
1495 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1496 if (cache.locals < 0)
1499 /* Found valid frame setup. */
1501 /* The native cc on SVR4 in -K PIC mode inserts the following code
1502 to get the address of the global offset table (GOT) into register
1507 movl %ebx,x(%ebp) (optional)
1510 This code is with the rest of the prologue (at the end of the
1511 function), so we have to skip it to get to the first real
1512 instruction at the start of the function. */
1514 for (i = 0; i < 6; i++)
1516 if (target_read_memory (pc + i, &op, 1))
1519 if (pic_pat[i] != op)
1526 if (target_read_memory (pc + delta, &op, 1))
1529 if (op == 0x89) /* movl %ebx, x(%ebp) */
1531 op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order);
1533 if (op == 0x5d) /* One byte offset from %ebp. */
1535 else if (op == 0x9d) /* Four byte offset from %ebp. */
1537 else /* Unexpected instruction. */
1540 if (target_read_memory (pc + delta, &op, 1))
1545 if (delta > 0 && op == 0x81
1546 && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order)
1553 /* If the function starts with a branch (to startup code at the end)
1554 the last instruction should bring us back to the first
1555 instruction of the real code. */
1556 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1557 pc = i386_follow_jump (gdbarch, pc);
1562 /* Check that the code pointed to by PC corresponds to a call to
1563 __main, skip it if so. Return PC otherwise. */
1566 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1568 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1571 if (target_read_memory (pc, &op, 1))
1577 if (target_read_memory (pc + 1, buf, sizeof buf) == 0)
1579 /* Make sure address is computed correctly as a 32bit
1580 integer even if CORE_ADDR is 64 bit wide. */
1581 struct minimal_symbol *s;
1582 CORE_ADDR call_dest;
1584 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1585 call_dest = call_dest & 0xffffffffU;
1586 s = lookup_minimal_symbol_by_pc (call_dest);
1588 && SYMBOL_LINKAGE_NAME (s) != NULL
1589 && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0)
1597 /* This function is 64-bit safe. */
1600 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1604 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1605 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1609 /* Normal frames. */
1611 static struct i386_frame_cache *
1612 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
1614 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1615 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1616 struct i386_frame_cache *cache;
1623 cache = i386_alloc_frame_cache ();
1624 *this_cache = cache;
1626 /* In principle, for normal frames, %ebp holds the frame pointer,
1627 which holds the base address for the current stack frame.
1628 However, for functions that don't need it, the frame pointer is
1629 optional. For these "frameless" functions the frame pointer is
1630 actually the frame pointer of the calling frame. Signal
1631 trampolines are just a special case of a "frameless" function.
1632 They (usually) share their frame pointer with the frame that was
1633 in progress when the signal occurred. */
1635 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1636 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1637 if (cache->base == 0)
1640 /* For normal frames, %eip is stored at 4(%ebp). */
1641 cache->saved_regs[I386_EIP_REGNUM] = 4;
1643 cache->pc = get_frame_func (this_frame);
1645 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
1648 if (cache->saved_sp_reg != -1)
1650 /* Saved stack pointer has been saved. */
1651 get_frame_register (this_frame, cache->saved_sp_reg, buf);
1652 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
1655 if (cache->locals < 0)
1657 /* We didn't find a valid frame, which means that CACHE->base
1658 currently holds the frame pointer for our calling frame. If
1659 we're at the start of a function, or somewhere half-way its
1660 prologue, the function's frame probably hasn't been fully
1661 setup yet. Try to reconstruct the base address for the stack
1662 frame by looking at the stack pointer. For truly "frameless"
1663 functions this might work too. */
1665 if (cache->saved_sp_reg != -1)
1667 /* We're halfway aligning the stack. */
1668 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
1669 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
1671 /* This will be added back below. */
1672 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
1674 else if (cache->pc != 0
1675 || target_read_memory (get_frame_pc (this_frame), buf, 1))
1677 /* We're in a known function, but did not find a frame
1678 setup. Assume that the function does not use %ebp.
1679 Alternatively, we may have jumped to an invalid
1680 address; in that case there is definitely no new
1682 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1683 cache->base = extract_unsigned_integer (buf, 4, byte_order)
1687 /* We're in an unknown function. We could not find the start
1688 of the function to analyze the prologue; our best option is
1689 to assume a typical frame layout with the caller's %ebp
1691 cache->saved_regs[I386_EBP_REGNUM] = 0;
1694 /* Now that we have the base address for the stack frame we can
1695 calculate the value of %esp in the calling frame. */
1696 if (cache->saved_sp == 0)
1697 cache->saved_sp = cache->base + 8;
1699 /* Adjust all the saved registers such that they contain addresses
1700 instead of offsets. */
1701 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1702 if (cache->saved_regs[i] != -1)
1703 cache->saved_regs[i] += cache->base;
1709 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
1710 struct frame_id *this_id)
1712 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1714 /* This marks the outermost frame. */
1715 if (cache->base == 0)
1718 /* See the end of i386_push_dummy_call. */
1719 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
1722 static struct value *
1723 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
1726 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1728 gdb_assert (regnum >= 0);
1730 /* The System V ABI says that:
1732 "The flags register contains the system flags, such as the
1733 direction flag and the carry flag. The direction flag must be
1734 set to the forward (that is, zero) direction before entry and
1735 upon exit from a function. Other user flags have no specified
1736 role in the standard calling sequence and are not preserved."
1738 To guarantee the "upon exit" part of that statement we fake a
1739 saved flags register that has its direction flag cleared.
1741 Note that GCC doesn't seem to rely on the fact that the direction
1742 flag is cleared after a function return; it always explicitly
1743 clears the flag before operations where it matters.
1745 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1746 right thing to do. The way we fake the flags register here makes
1747 it impossible to change it. */
1749 if (regnum == I386_EFLAGS_REGNUM)
1753 val = get_frame_register_unsigned (this_frame, regnum);
1755 return frame_unwind_got_constant (this_frame, regnum, val);
1758 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
1759 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
1761 if (regnum == I386_ESP_REGNUM && cache->saved_sp)
1762 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
1764 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
1765 return frame_unwind_got_memory (this_frame, regnum,
1766 cache->saved_regs[regnum]);
1768 return frame_unwind_got_register (this_frame, regnum, regnum);
1771 static const struct frame_unwind i386_frame_unwind =
1775 i386_frame_prev_register,
1777 default_frame_sniffer
1780 /* Normal frames, but in a function epilogue. */
1782 /* The epilogue is defined here as the 'ret' instruction, which will
1783 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1784 the function's stack frame. */
1787 i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1791 if (target_read_memory (pc, &insn, 1))
1792 return 0; /* Can't read memory at pc. */
1794 if (insn != 0xc3) /* 'ret' instruction. */
1801 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
1802 struct frame_info *this_frame,
1803 void **this_prologue_cache)
1805 if (frame_relative_level (this_frame) == 0)
1806 return i386_in_function_epilogue_p (get_frame_arch (this_frame),
1807 get_frame_pc (this_frame));
1812 static struct i386_frame_cache *
1813 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
1815 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1816 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1817 struct i386_frame_cache *cache;
1823 cache = i386_alloc_frame_cache ();
1824 *this_cache = cache;
1826 /* Cache base will be %esp plus cache->sp_offset (-4). */
1827 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1828 cache->base = extract_unsigned_integer (buf, 4,
1829 byte_order) + cache->sp_offset;
1831 /* Cache pc will be the frame func. */
1832 cache->pc = get_frame_pc (this_frame);
1834 /* The saved %esp will be at cache->base plus 8. */
1835 cache->saved_sp = cache->base + 8;
1837 /* The saved %eip will be at cache->base plus 4. */
1838 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
1844 i386_epilogue_frame_this_id (struct frame_info *this_frame,
1846 struct frame_id *this_id)
1848 struct i386_frame_cache *cache = i386_epilogue_frame_cache (this_frame,
1851 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
1854 static const struct frame_unwind i386_epilogue_frame_unwind =
1857 i386_epilogue_frame_this_id,
1858 i386_frame_prev_register,
1860 i386_epilogue_frame_sniffer
1864 /* Signal trampolines. */
1866 static struct i386_frame_cache *
1867 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
1869 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1870 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1871 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1872 struct i386_frame_cache *cache;
1879 cache = i386_alloc_frame_cache ();
1881 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1882 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
1884 addr = tdep->sigcontext_addr (this_frame);
1885 if (tdep->sc_reg_offset)
1889 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
1891 for (i = 0; i < tdep->sc_num_regs; i++)
1892 if (tdep->sc_reg_offset[i] != -1)
1893 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
1897 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
1898 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
1901 *this_cache = cache;
1906 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
1907 struct frame_id *this_id)
1909 struct i386_frame_cache *cache =
1910 i386_sigtramp_frame_cache (this_frame, this_cache);
1912 /* See the end of i386_push_dummy_call. */
1913 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
1916 static struct value *
1917 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
1918 void **this_cache, int regnum)
1920 /* Make sure we've initialized the cache. */
1921 i386_sigtramp_frame_cache (this_frame, this_cache);
1923 return i386_frame_prev_register (this_frame, this_cache, regnum);
1927 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
1928 struct frame_info *this_frame,
1929 void **this_prologue_cache)
1931 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
1933 /* We shouldn't even bother if we don't have a sigcontext_addr
1935 if (tdep->sigcontext_addr == NULL)
1938 if (tdep->sigtramp_p != NULL)
1940 if (tdep->sigtramp_p (this_frame))
1944 if (tdep->sigtramp_start != 0)
1946 CORE_ADDR pc = get_frame_pc (this_frame);
1948 gdb_assert (tdep->sigtramp_end != 0);
1949 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
1956 static const struct frame_unwind i386_sigtramp_frame_unwind =
1959 i386_sigtramp_frame_this_id,
1960 i386_sigtramp_frame_prev_register,
1962 i386_sigtramp_frame_sniffer
1967 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
1969 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1974 static const struct frame_base i386_frame_base =
1977 i386_frame_base_address,
1978 i386_frame_base_address,
1979 i386_frame_base_address
1982 static struct frame_id
1983 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1987 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
1989 /* See the end of i386_push_dummy_call. */
1990 return frame_id_build (fp + 8, get_frame_pc (this_frame));
1994 /* Figure out where the longjmp will land. Slurp the args out of the
1995 stack. We expect the first arg to be a pointer to the jmp_buf
1996 structure from which we extract the address that we will land at.
1997 This address is copied into PC. This routine returns non-zero on
2001 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2004 CORE_ADDR sp, jb_addr;
2005 struct gdbarch *gdbarch = get_frame_arch (frame);
2006 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2007 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2009 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2010 longjmp will land. */
2011 if (jb_pc_offset == -1)
2014 get_frame_register (frame, I386_ESP_REGNUM, buf);
2015 sp = extract_unsigned_integer (buf, 4, byte_order);
2016 if (target_read_memory (sp + 4, buf, 4))
2019 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
2020 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
2023 *pc = extract_unsigned_integer (buf, 4, byte_order);
2028 /* Check whether TYPE must be 16-byte-aligned when passed as a
2029 function argument. 16-byte vectors, _Decimal128 and structures or
2030 unions containing such types must be 16-byte-aligned; other
2031 arguments are 4-byte-aligned. */
2034 i386_16_byte_align_p (struct type *type)
2036 type = check_typedef (type);
2037 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
2038 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
2039 && TYPE_LENGTH (type) == 16)
2041 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2042 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
2043 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2044 || TYPE_CODE (type) == TYPE_CODE_UNION)
2047 for (i = 0; i < TYPE_NFIELDS (type); i++)
2049 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
2057 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2058 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2059 struct value **args, CORE_ADDR sp, int struct_return,
2060 CORE_ADDR struct_addr)
2062 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2068 /* Determine the total space required for arguments and struct
2069 return address in a first pass (allowing for 16-byte-aligned
2070 arguments), then push arguments in a second pass. */
2072 for (write_pass = 0; write_pass < 2; write_pass++)
2074 int args_space_used = 0;
2075 int have_16_byte_aligned_arg = 0;
2081 /* Push value address. */
2082 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2083 write_memory (sp, buf, 4);
2084 args_space_used += 4;
2090 for (i = 0; i < nargs; i++)
2092 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2096 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2097 args_space_used = align_up (args_space_used, 16);
2099 write_memory (sp + args_space_used,
2100 value_contents_all (args[i]), len);
2101 /* The System V ABI says that:
2103 "An argument's size is increased, if necessary, to make it a
2104 multiple of [32-bit] words. This may require tail padding,
2105 depending on the size of the argument."
2107 This makes sure the stack stays word-aligned. */
2108 args_space_used += align_up (len, 4);
2112 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2114 args_space = align_up (args_space, 16);
2115 have_16_byte_aligned_arg = 1;
2117 args_space += align_up (len, 4);
2123 if (have_16_byte_aligned_arg)
2124 args_space = align_up (args_space, 16);
2129 /* Store return address. */
2131 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2132 write_memory (sp, buf, 4);
2134 /* Finally, update the stack pointer... */
2135 store_unsigned_integer (buf, 4, byte_order, sp);
2136 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
2138 /* ...and fake a frame pointer. */
2139 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
2141 /* MarkK wrote: This "+ 8" is all over the place:
2142 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2143 i386_dummy_id). It's there, since all frame unwinders for
2144 a given target have to agree (within a certain margin) on the
2145 definition of the stack address of a frame. Otherwise frame id
2146 comparison might not work correctly. Since DWARF2/GCC uses the
2147 stack address *before* the function call as a frame's CFA. On
2148 the i386, when %ebp is used as a frame pointer, the offset
2149 between the contents %ebp and the CFA as defined by GCC. */
2153 /* These registers are used for returning integers (and on some
2154 targets also for returning `struct' and `union' values when their
2155 size and alignment match an integer type). */
2156 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2157 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2159 /* Read, for architecture GDBARCH, a function return value of TYPE
2160 from REGCACHE, and copy that into VALBUF. */
2163 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2164 struct regcache *regcache, gdb_byte *valbuf)
2166 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2167 int len = TYPE_LENGTH (type);
2168 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2170 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2172 if (tdep->st0_regnum < 0)
2174 warning (_("Cannot find floating-point return value."));
2175 memset (valbuf, 0, len);
2179 /* Floating-point return values can be found in %st(0). Convert
2180 its contents to the desired type. This is probably not
2181 exactly how it would happen on the target itself, but it is
2182 the best we can do. */
2183 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2184 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
2188 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2189 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2191 if (len <= low_size)
2193 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2194 memcpy (valbuf, buf, len);
2196 else if (len <= (low_size + high_size))
2198 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2199 memcpy (valbuf, buf, low_size);
2200 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2201 memcpy (valbuf + low_size, buf, len - low_size);
2204 internal_error (__FILE__, __LINE__,
2205 _("Cannot extract return value of %d bytes long."),
2210 /* Write, for architecture GDBARCH, a function return value of TYPE
2211 from VALBUF into REGCACHE. */
2214 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2215 struct regcache *regcache, const gdb_byte *valbuf)
2217 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2218 int len = TYPE_LENGTH (type);
2220 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2223 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2225 if (tdep->st0_regnum < 0)
2227 warning (_("Cannot set floating-point return value."));
2231 /* Returning floating-point values is a bit tricky. Apart from
2232 storing the return value in %st(0), we have to simulate the
2233 state of the FPU at function return point. */
2235 /* Convert the value found in VALBUF to the extended
2236 floating-point format used by the FPU. This is probably
2237 not exactly how it would happen on the target itself, but
2238 it is the best we can do. */
2239 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
2240 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2242 /* Set the top of the floating-point register stack to 7. The
2243 actual value doesn't really matter, but 7 is what a normal
2244 function return would end up with if the program started out
2245 with a freshly initialized FPU. */
2246 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2248 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2250 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2251 the floating-point register stack to 7, the appropriate value
2252 for the tag word is 0x3fff. */
2253 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2257 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2258 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2260 if (len <= low_size)
2261 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2262 else if (len <= (low_size + high_size))
2264 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2265 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
2266 len - low_size, valbuf + low_size);
2269 internal_error (__FILE__, __LINE__,
2270 _("Cannot store return value of %d bytes long."), len);
2275 /* This is the variable that is set with "set struct-convention", and
2276 its legitimate values. */
2277 static const char default_struct_convention[] = "default";
2278 static const char pcc_struct_convention[] = "pcc";
2279 static const char reg_struct_convention[] = "reg";
2280 static const char *valid_conventions[] =
2282 default_struct_convention,
2283 pcc_struct_convention,
2284 reg_struct_convention,
2287 static const char *struct_convention = default_struct_convention;
2289 /* Return non-zero if TYPE, which is assumed to be a structure,
2290 a union type, or an array type, should be returned in registers
2291 for architecture GDBARCH. */
2294 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2296 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2297 enum type_code code = TYPE_CODE (type);
2298 int len = TYPE_LENGTH (type);
2300 gdb_assert (code == TYPE_CODE_STRUCT
2301 || code == TYPE_CODE_UNION
2302 || code == TYPE_CODE_ARRAY);
2304 if (struct_convention == pcc_struct_convention
2305 || (struct_convention == default_struct_convention
2306 && tdep->struct_return == pcc_struct_return))
2309 /* Structures consisting of a single `float', `double' or 'long
2310 double' member are returned in %st(0). */
2311 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2313 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2314 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2315 return (len == 4 || len == 8 || len == 12);
2318 return (len == 1 || len == 2 || len == 4 || len == 8);
2321 /* Determine, for architecture GDBARCH, how a return value of TYPE
2322 should be returned. If it is supposed to be returned in registers,
2323 and READBUF is non-zero, read the appropriate value from REGCACHE,
2324 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2325 from WRITEBUF into REGCACHE. */
2327 static enum return_value_convention
2328 i386_return_value (struct gdbarch *gdbarch, struct type *func_type,
2329 struct type *type, struct regcache *regcache,
2330 gdb_byte *readbuf, const gdb_byte *writebuf)
2332 enum type_code code = TYPE_CODE (type);
2334 if (((code == TYPE_CODE_STRUCT
2335 || code == TYPE_CODE_UNION
2336 || code == TYPE_CODE_ARRAY)
2337 && !i386_reg_struct_return_p (gdbarch, type))
2338 /* 128-bit decimal float uses the struct return convention. */
2339 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2341 /* The System V ABI says that:
2343 "A function that returns a structure or union also sets %eax
2344 to the value of the original address of the caller's area
2345 before it returns. Thus when the caller receives control
2346 again, the address of the returned object resides in register
2347 %eax and can be used to access the object."
2349 So the ABI guarantees that we can always find the return
2350 value just after the function has returned. */
2352 /* Note that the ABI doesn't mention functions returning arrays,
2353 which is something possible in certain languages such as Ada.
2354 In this case, the value is returned as if it was wrapped in
2355 a record, so the convention applied to records also applies
2362 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2363 read_memory (addr, readbuf, TYPE_LENGTH (type));
2366 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2369 /* This special case is for structures consisting of a single
2370 `float', `double' or 'long double' member. These structures are
2371 returned in %st(0). For these structures, we call ourselves
2372 recursively, changing TYPE into the type of the first member of
2373 the structure. Since that should work for all structures that
2374 have only one member, we don't bother to check the member's type
2376 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2378 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2379 return i386_return_value (gdbarch, func_type, type, regcache,
2384 i386_extract_return_value (gdbarch, type, regcache, readbuf);
2386 i386_store_return_value (gdbarch, type, regcache, writebuf);
2388 return RETURN_VALUE_REGISTER_CONVENTION;
2393 i387_ext_type (struct gdbarch *gdbarch)
2395 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2397 if (!tdep->i387_ext_type)
2399 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
2400 gdb_assert (tdep->i387_ext_type != NULL);
2403 return tdep->i387_ext_type;
2406 /* Construct vector type for pseudo YMM registers. We can't use
2407 tdesc_find_type since YMM isn't described in target description. */
2409 static struct type *
2410 i386_ymm_type (struct gdbarch *gdbarch)
2412 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2414 if (!tdep->i386_ymm_type)
2416 const struct builtin_type *bt = builtin_type (gdbarch);
2418 /* The type we're building is this: */
2420 union __gdb_builtin_type_vec256i
2422 int128_t uint128[2];
2423 int64_t v2_int64[4];
2424 int32_t v4_int32[8];
2425 int16_t v8_int16[16];
2426 int8_t v16_int8[32];
2427 double v2_double[4];
2434 t = arch_composite_type (gdbarch,
2435 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
2436 append_composite_type_field (t, "v8_float",
2437 init_vector_type (bt->builtin_float, 8));
2438 append_composite_type_field (t, "v4_double",
2439 init_vector_type (bt->builtin_double, 4));
2440 append_composite_type_field (t, "v32_int8",
2441 init_vector_type (bt->builtin_int8, 32));
2442 append_composite_type_field (t, "v16_int16",
2443 init_vector_type (bt->builtin_int16, 16));
2444 append_composite_type_field (t, "v8_int32",
2445 init_vector_type (bt->builtin_int32, 8));
2446 append_composite_type_field (t, "v4_int64",
2447 init_vector_type (bt->builtin_int64, 4));
2448 append_composite_type_field (t, "v2_int128",
2449 init_vector_type (bt->builtin_int128, 2));
2451 TYPE_VECTOR (t) = 1;
2452 TYPE_NAME (t) = "builtin_type_vec256i";
2453 tdep->i386_ymm_type = t;
2456 return tdep->i386_ymm_type;
2459 /* Construct vector type for MMX registers. */
2460 static struct type *
2461 i386_mmx_type (struct gdbarch *gdbarch)
2463 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2465 if (!tdep->i386_mmx_type)
2467 const struct builtin_type *bt = builtin_type (gdbarch);
2469 /* The type we're building is this: */
2471 union __gdb_builtin_type_vec64i
2474 int32_t v2_int32[2];
2475 int16_t v4_int16[4];
2482 t = arch_composite_type (gdbarch,
2483 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
2485 append_composite_type_field (t, "uint64", bt->builtin_int64);
2486 append_composite_type_field (t, "v2_int32",
2487 init_vector_type (bt->builtin_int32, 2));
2488 append_composite_type_field (t, "v4_int16",
2489 init_vector_type (bt->builtin_int16, 4));
2490 append_composite_type_field (t, "v8_int8",
2491 init_vector_type (bt->builtin_int8, 8));
2493 TYPE_VECTOR (t) = 1;
2494 TYPE_NAME (t) = "builtin_type_vec64i";
2495 tdep->i386_mmx_type = t;
2498 return tdep->i386_mmx_type;
2501 /* Return the GDB type object for the "standard" data type of data in
2504 static struct type *
2505 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2507 if (i386_mmx_regnum_p (gdbarch, regnum))
2508 return i386_mmx_type (gdbarch);
2509 else if (i386_ymm_regnum_p (gdbarch, regnum))
2510 return i386_ymm_type (gdbarch);
2513 const struct builtin_type *bt = builtin_type (gdbarch);
2514 if (i386_byte_regnum_p (gdbarch, regnum))
2515 return bt->builtin_int8;
2516 else if (i386_word_regnum_p (gdbarch, regnum))
2517 return bt->builtin_int16;
2518 else if (i386_dword_regnum_p (gdbarch, regnum))
2519 return bt->builtin_int32;
2522 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2525 /* Map a cooked register onto a raw register or memory. For the i386,
2526 the MMX registers need to be mapped onto floating point registers. */
2529 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
2531 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
2536 mmxreg = regnum - tdep->mm0_regnum;
2537 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2538 tos = (fstat >> 11) & 0x7;
2539 fpreg = (mmxreg + tos) % 8;
2541 return (I387_ST0_REGNUM (tdep) + fpreg);
2544 enum register_status
2545 i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2546 int regnum, gdb_byte *buf)
2548 gdb_byte raw_buf[MAX_REGISTER_SIZE];
2549 enum register_status status;
2551 if (i386_mmx_regnum_p (gdbarch, regnum))
2553 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2555 /* Extract (always little endian). */
2556 status = regcache_raw_read (regcache, fpnum, raw_buf);
2557 if (status != REG_VALID)
2559 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
2563 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2565 if (i386_ymm_regnum_p (gdbarch, regnum))
2567 regnum -= tdep->ymm0_regnum;
2569 /* Extract (always little endian). Read lower 128bits. */
2570 status = regcache_raw_read (regcache,
2571 I387_XMM0_REGNUM (tdep) + regnum,
2573 if (status != REG_VALID)
2575 memcpy (buf, raw_buf, 16);
2576 /* Read upper 128bits. */
2577 status = regcache_raw_read (regcache,
2578 tdep->ymm0h_regnum + regnum,
2580 if (status != REG_VALID)
2582 memcpy (buf + 16, raw_buf, 16);
2584 else if (i386_word_regnum_p (gdbarch, regnum))
2586 int gpnum = regnum - tdep->ax_regnum;
2588 /* Extract (always little endian). */
2589 status = regcache_raw_read (regcache, gpnum, raw_buf);
2590 if (status != REG_VALID)
2592 memcpy (buf, raw_buf, 2);
2594 else if (i386_byte_regnum_p (gdbarch, regnum))
2596 /* Check byte pseudo registers last since this function will
2597 be called from amd64_pseudo_register_read, which handles
2598 byte pseudo registers differently. */
2599 int gpnum = regnum - tdep->al_regnum;
2601 /* Extract (always little endian). We read both lower and
2603 status = regcache_raw_read (regcache, gpnum % 4, raw_buf);
2604 if (status != REG_VALID)
2607 memcpy (buf, raw_buf + 1, 1);
2609 memcpy (buf, raw_buf, 1);
2612 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2619 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2620 int regnum, const gdb_byte *buf)
2622 gdb_byte raw_buf[MAX_REGISTER_SIZE];
2624 if (i386_mmx_regnum_p (gdbarch, regnum))
2626 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2629 regcache_raw_read (regcache, fpnum, raw_buf);
2630 /* ... Modify ... (always little endian). */
2631 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
2633 regcache_raw_write (regcache, fpnum, raw_buf);
2637 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2639 if (i386_ymm_regnum_p (gdbarch, regnum))
2641 regnum -= tdep->ymm0_regnum;
2643 /* ... Write lower 128bits. */
2644 regcache_raw_write (regcache,
2645 I387_XMM0_REGNUM (tdep) + regnum,
2647 /* ... Write upper 128bits. */
2648 regcache_raw_write (regcache,
2649 tdep->ymm0h_regnum + regnum,
2652 else if (i386_word_regnum_p (gdbarch, regnum))
2654 int gpnum = regnum - tdep->ax_regnum;
2657 regcache_raw_read (regcache, gpnum, raw_buf);
2658 /* ... Modify ... (always little endian). */
2659 memcpy (raw_buf, buf, 2);
2661 regcache_raw_write (regcache, gpnum, raw_buf);
2663 else if (i386_byte_regnum_p (gdbarch, regnum))
2665 /* Check byte pseudo registers last since this function will
2666 be called from amd64_pseudo_register_read, which handles
2667 byte pseudo registers differently. */
2668 int gpnum = regnum - tdep->al_regnum;
2670 /* Read ... We read both lower and upper registers. */
2671 regcache_raw_read (regcache, gpnum % 4, raw_buf);
2672 /* ... Modify ... (always little endian). */
2674 memcpy (raw_buf + 1, buf, 1);
2676 memcpy (raw_buf, buf, 1);
2678 regcache_raw_write (regcache, gpnum % 4, raw_buf);
2681 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2686 /* Return the register number of the register allocated by GCC after
2687 REGNUM, or -1 if there is no such register. */
2690 i386_next_regnum (int regnum)
2692 /* GCC allocates the registers in the order:
2694 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2696 Since storing a variable in %esp doesn't make any sense we return
2697 -1 for %ebp and for %esp itself. */
2698 static int next_regnum[] =
2700 I386_EDX_REGNUM, /* Slot for %eax. */
2701 I386_EBX_REGNUM, /* Slot for %ecx. */
2702 I386_ECX_REGNUM, /* Slot for %edx. */
2703 I386_ESI_REGNUM, /* Slot for %ebx. */
2704 -1, -1, /* Slots for %esp and %ebp. */
2705 I386_EDI_REGNUM, /* Slot for %esi. */
2706 I386_EBP_REGNUM /* Slot for %edi. */
2709 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
2710 return next_regnum[regnum];
2715 /* Return nonzero if a value of type TYPE stored in register REGNUM
2716 needs any special handling. */
2719 i386_convert_register_p (struct gdbarch *gdbarch,
2720 int regnum, struct type *type)
2722 int len = TYPE_LENGTH (type);
2724 /* Values may be spread across multiple registers. Most debugging
2725 formats aren't expressive enough to specify the locations, so
2726 some heuristics is involved. Right now we only handle types that
2727 have a length that is a multiple of the word size, since GCC
2728 doesn't seem to put any other types into registers. */
2729 if (len > 4 && len % 4 == 0)
2731 int last_regnum = regnum;
2735 last_regnum = i386_next_regnum (last_regnum);
2739 if (last_regnum != -1)
2743 return i387_convert_register_p (gdbarch, regnum, type);
2746 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2747 return its contents in TO. */
2750 i386_register_to_value (struct frame_info *frame, int regnum,
2751 struct type *type, gdb_byte *to)
2753 struct gdbarch *gdbarch = get_frame_arch (frame);
2754 int len = TYPE_LENGTH (type);
2756 /* FIXME: kettenis/20030609: What should we do if REGNUM isn't
2757 available in FRAME (i.e. if it wasn't saved)? */
2759 if (i386_fp_regnum_p (gdbarch, regnum))
2761 i387_register_to_value (frame, regnum, type, to);
2765 /* Read a value spread across multiple registers. */
2767 gdb_assert (len > 4 && len % 4 == 0);
2771 gdb_assert (regnum != -1);
2772 gdb_assert (register_size (gdbarch, regnum) == 4);
2774 get_frame_register (frame, regnum, to);
2775 regnum = i386_next_regnum (regnum);
2781 /* Write the contents FROM of a value of type TYPE into register
2782 REGNUM in frame FRAME. */
2785 i386_value_to_register (struct frame_info *frame, int regnum,
2786 struct type *type, const gdb_byte *from)
2788 int len = TYPE_LENGTH (type);
2790 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
2792 i387_value_to_register (frame, regnum, type, from);
2796 /* Write a value spread across multiple registers. */
2798 gdb_assert (len > 4 && len % 4 == 0);
2802 gdb_assert (regnum != -1);
2803 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
2805 put_frame_register (frame, regnum, from);
2806 regnum = i386_next_regnum (regnum);
2812 /* Supply register REGNUM from the buffer specified by GREGS and LEN
2813 in the general-purpose register set REGSET to register cache
2814 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2817 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
2818 int regnum, const void *gregs, size_t len)
2820 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2821 const gdb_byte *regs = gregs;
2824 gdb_assert (len == tdep->sizeof_gregset);
2826 for (i = 0; i < tdep->gregset_num_regs; i++)
2828 if ((regnum == i || regnum == -1)
2829 && tdep->gregset_reg_offset[i] != -1)
2830 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
2834 /* Collect register REGNUM from the register cache REGCACHE and store
2835 it in the buffer specified by GREGS and LEN as described by the
2836 general-purpose register set REGSET. If REGNUM is -1, do this for
2837 all registers in REGSET. */
2840 i386_collect_gregset (const struct regset *regset,
2841 const struct regcache *regcache,
2842 int regnum, void *gregs, size_t len)
2844 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2845 gdb_byte *regs = gregs;
2848 gdb_assert (len == tdep->sizeof_gregset);
2850 for (i = 0; i < tdep->gregset_num_regs; i++)
2852 if ((regnum == i || regnum == -1)
2853 && tdep->gregset_reg_offset[i] != -1)
2854 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
2858 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2859 in the floating-point register set REGSET to register cache
2860 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2863 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
2864 int regnum, const void *fpregs, size_t len)
2866 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2868 if (len == I387_SIZEOF_FXSAVE)
2870 i387_supply_fxsave (regcache, regnum, fpregs);
2874 gdb_assert (len == tdep->sizeof_fpregset);
2875 i387_supply_fsave (regcache, regnum, fpregs);
2878 /* Collect register REGNUM from the register cache REGCACHE and store
2879 it in the buffer specified by FPREGS and LEN as described by the
2880 floating-point register set REGSET. If REGNUM is -1, do this for
2881 all registers in REGSET. */
2884 i386_collect_fpregset (const struct regset *regset,
2885 const struct regcache *regcache,
2886 int regnum, void *fpregs, size_t len)
2888 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2890 if (len == I387_SIZEOF_FXSAVE)
2892 i387_collect_fxsave (regcache, regnum, fpregs);
2896 gdb_assert (len == tdep->sizeof_fpregset);
2897 i387_collect_fsave (regcache, regnum, fpregs);
2900 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
2903 i386_supply_xstateregset (const struct regset *regset,
2904 struct regcache *regcache, int regnum,
2905 const void *xstateregs, size_t len)
2907 i387_supply_xsave (regcache, regnum, xstateregs);
2910 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
2913 i386_collect_xstateregset (const struct regset *regset,
2914 const struct regcache *regcache,
2915 int regnum, void *xstateregs, size_t len)
2917 i387_collect_xsave (regcache, regnum, xstateregs, 1);
2920 /* Return the appropriate register set for the core section identified
2921 by SECT_NAME and SECT_SIZE. */
2923 const struct regset *
2924 i386_regset_from_core_section (struct gdbarch *gdbarch,
2925 const char *sect_name, size_t sect_size)
2927 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2929 if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset)
2931 if (tdep->gregset == NULL)
2932 tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset,
2933 i386_collect_gregset);
2934 return tdep->gregset;
2937 if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
2938 || (strcmp (sect_name, ".reg-xfp") == 0
2939 && sect_size == I387_SIZEOF_FXSAVE))
2941 if (tdep->fpregset == NULL)
2942 tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset,
2943 i386_collect_fpregset);
2944 return tdep->fpregset;
2947 if (strcmp (sect_name, ".reg-xstate") == 0)
2949 if (tdep->xstateregset == NULL)
2950 tdep->xstateregset = regset_alloc (gdbarch,
2951 i386_supply_xstateregset,
2952 i386_collect_xstateregset);
2954 return tdep->xstateregset;
2961 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
2964 i386_pe_skip_trampoline_code (struct frame_info *frame,
2965 CORE_ADDR pc, char *name)
2967 struct gdbarch *gdbarch = get_frame_arch (frame);
2968 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2971 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
2973 unsigned long indirect =
2974 read_memory_unsigned_integer (pc + 2, 4, byte_order);
2975 struct minimal_symbol *indsym =
2976 indirect ? lookup_minimal_symbol_by_pc (indirect) : 0;
2977 char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0;
2981 if (strncmp (symname, "__imp_", 6) == 0
2982 || strncmp (symname, "_imp_", 5) == 0)
2984 read_memory_unsigned_integer (indirect, 4, byte_order);
2987 return 0; /* Not a trampoline. */
2991 /* Return whether the THIS_FRAME corresponds to a sigtramp
2995 i386_sigtramp_p (struct frame_info *this_frame)
2997 CORE_ADDR pc = get_frame_pc (this_frame);
3000 find_pc_partial_function (pc, &name, NULL, NULL);
3001 return (name && strcmp ("_sigtramp", name) == 0);
3005 /* We have two flavours of disassembly. The machinery on this page
3006 deals with switching between those. */
3009 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
3011 gdb_assert (disassembly_flavor == att_flavor
3012 || disassembly_flavor == intel_flavor);
3014 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3015 constified, cast to prevent a compiler warning. */
3016 info->disassembler_options = (char *) disassembly_flavor;
3018 return print_insn_i386 (pc, info);
3022 /* There are a few i386 architecture variants that differ only
3023 slightly from the generic i386 target. For now, we don't give them
3024 their own source file, but include them here. As a consequence,
3025 they'll always be included. */
3027 /* System V Release 4 (SVR4). */
3029 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3033 i386_svr4_sigtramp_p (struct frame_info *this_frame)
3035 CORE_ADDR pc = get_frame_pc (this_frame);
3038 /* UnixWare uses _sigacthandler. The origin of the other symbols is
3039 currently unknown. */
3040 find_pc_partial_function (pc, &name, NULL, NULL);
3041 return (name && (strcmp ("_sigreturn", name) == 0
3042 || strcmp ("_sigacthandler", name) == 0
3043 || strcmp ("sigvechandler", name) == 0));
3046 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3047 address of the associated sigcontext (ucontext) structure. */
3050 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
3052 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3053 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3057 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
3058 sp = extract_unsigned_integer (buf, 4, byte_order);
3060 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
3067 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3069 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3070 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3073 /* System V Release 4 (SVR4). */
3076 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3078 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3080 /* System V Release 4 uses ELF. */
3081 i386_elf_init_abi (info, gdbarch);
3083 /* System V Release 4 has shared libraries. */
3084 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
3086 tdep->sigtramp_p = i386_svr4_sigtramp_p;
3087 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
3088 tdep->sc_pc_offset = 36 + 14 * 4;
3089 tdep->sc_sp_offset = 36 + 17 * 4;
3091 tdep->jb_pc_offset = 20;
3097 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3099 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3101 /* DJGPP doesn't have any special frames for signal handlers. */
3102 tdep->sigtramp_p = NULL;
3104 tdep->jb_pc_offset = 36;
3106 /* DJGPP does not support the SSE registers. */
3107 if (! tdesc_has_registers (info.target_desc))
3108 tdep->tdesc = tdesc_i386_mmx;
3110 /* Native compiler is GCC, which uses the SVR4 register numbering
3111 even in COFF and STABS. See the comment in i386_gdbarch_init,
3112 before the calls to set_gdbarch_stab_reg_to_regnum and
3113 set_gdbarch_sdb_reg_to_regnum. */
3114 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3115 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3117 set_gdbarch_has_dos_based_file_system (gdbarch, 1);
3121 /* i386 register groups. In addition to the normal groups, add "mmx"
3124 static struct reggroup *i386_sse_reggroup;
3125 static struct reggroup *i386_mmx_reggroup;
3128 i386_init_reggroups (void)
3130 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
3131 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
3135 i386_add_reggroups (struct gdbarch *gdbarch)
3137 reggroup_add (gdbarch, i386_sse_reggroup);
3138 reggroup_add (gdbarch, i386_mmx_reggroup);
3139 reggroup_add (gdbarch, general_reggroup);
3140 reggroup_add (gdbarch, float_reggroup);
3141 reggroup_add (gdbarch, all_reggroup);
3142 reggroup_add (gdbarch, save_reggroup);
3143 reggroup_add (gdbarch, restore_reggroup);
3144 reggroup_add (gdbarch, vector_reggroup);
3145 reggroup_add (gdbarch, system_reggroup);
3149 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
3150 struct reggroup *group)
3152 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3153 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
3154 ymm_regnum_p, ymmh_regnum_p;
3156 /* Don't include pseudo registers, except for MMX, in any register
3158 if (i386_byte_regnum_p (gdbarch, regnum))
3161 if (i386_word_regnum_p (gdbarch, regnum))
3164 if (i386_dword_regnum_p (gdbarch, regnum))
3167 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
3168 if (group == i386_mmx_reggroup)
3169 return mmx_regnum_p;
3171 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
3172 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
3173 if (group == i386_sse_reggroup)
3174 return xmm_regnum_p || mxcsr_regnum_p;
3176 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
3177 if (group == vector_reggroup)
3178 return (mmx_regnum_p
3182 && ((tdep->xcr0 & I386_XSTATE_AVX_MASK)
3183 == I386_XSTATE_SSE_MASK)));
3185 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
3186 || i386_fpc_regnum_p (gdbarch, regnum));
3187 if (group == float_reggroup)
3190 /* For "info reg all", don't include upper YMM registers nor XMM
3191 registers when AVX is supported. */
3192 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
3193 if (group == all_reggroup
3195 && (tdep->xcr0 & I386_XSTATE_AVX))
3199 if (group == general_reggroup)
3200 return (!fp_regnum_p
3207 return default_register_reggroup_p (gdbarch, regnum, group);
3211 /* Get the ARGIth function argument for the current function. */
3214 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
3217 struct gdbarch *gdbarch = get_frame_arch (frame);
3218 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3219 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
3220 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
3224 i386_skip_permanent_breakpoint (struct regcache *regcache)
3226 CORE_ADDR current_pc = regcache_read_pc (regcache);
3228 /* On i386, breakpoint is exactly 1 byte long, so we just
3229 adjust the PC in the regcache. */
3231 regcache_write_pc (regcache, current_pc);
3235 #define PREFIX_REPZ 0x01
3236 #define PREFIX_REPNZ 0x02
3237 #define PREFIX_LOCK 0x04
3238 #define PREFIX_DATA 0x08
3239 #define PREFIX_ADDR 0x10
3251 /* i386 arith/logic operations */
3264 struct i386_record_s
3266 struct gdbarch *gdbarch;
3267 struct regcache *regcache;
3268 CORE_ADDR orig_addr;
3274 uint8_t mod, reg, rm;
3283 /* Parse "modrm" part in current memory address that irp->addr point to
3284 Return -1 if something wrong. */
3287 i386_record_modrm (struct i386_record_s *irp)
3289 struct gdbarch *gdbarch = irp->gdbarch;
3291 if (target_read_memory (irp->addr, &irp->modrm, 1))
3294 printf_unfiltered (_("Process record: error reading memory at "
3295 "addr %s len = 1.\n"),
3296 paddress (gdbarch, irp->addr));
3300 irp->mod = (irp->modrm >> 6) & 3;
3301 irp->reg = (irp->modrm >> 3) & 7;
3302 irp->rm = irp->modrm & 7;
3307 /* Get the memory address that current instruction write to and set it to
3308 the argument "addr".
3309 Return -1 if something wrong. */
3312 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
3314 struct gdbarch *gdbarch = irp->gdbarch;
3315 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3327 uint8_t base = irp->rm;
3332 if (target_read_memory (irp->addr, &byte, 1))
3335 printf_unfiltered (_("Process record: error reading memory "
3336 "at addr %s len = 1.\n"),
3337 paddress (gdbarch, irp->addr));
3341 scale = (byte >> 6) & 3;
3342 index = ((byte >> 3) & 7) | irp->rex_x;
3350 if ((base & 7) == 5)
3353 if (target_read_memory (irp->addr, buf, 4))
3356 printf_unfiltered (_("Process record: error reading "
3357 "memory at addr %s len = 4.\n"),
3358 paddress (gdbarch, irp->addr));
3362 *addr = extract_signed_integer (buf, 4, byte_order);
3363 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
3364 *addr += irp->addr + irp->rip_offset;
3368 if (target_read_memory (irp->addr, buf, 1))
3371 printf_unfiltered (_("Process record: error reading memory "
3372 "at addr %s len = 1.\n"),
3373 paddress (gdbarch, irp->addr));
3377 *addr = (int8_t) buf[0];
3380 if (target_read_memory (irp->addr, buf, 4))
3383 printf_unfiltered (_("Process record: error reading memory "
3384 "at addr %s len = 4.\n"),
3385 paddress (gdbarch, irp->addr));
3388 *addr = extract_signed_integer (buf, 4, byte_order);
3396 if (base == 4 && irp->popl_esp_hack)
3397 *addr += irp->popl_esp_hack;
3398 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
3401 if (irp->aflag == 2)
3406 *addr = (uint32_t) (offset64 + *addr);
3408 if (havesib && (index != 4 || scale != 0))
3410 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
3412 if (irp->aflag == 2)
3413 *addr += offset64 << scale;
3415 *addr = (uint32_t) (*addr + (offset64 << scale));
3426 if (target_read_memory (irp->addr, buf, 2))
3429 printf_unfiltered (_("Process record: error reading "
3430 "memory at addr %s len = 2.\n"),
3431 paddress (gdbarch, irp->addr));
3435 *addr = extract_signed_integer (buf, 2, byte_order);
3441 if (target_read_memory (irp->addr, buf, 1))
3444 printf_unfiltered (_("Process record: error reading memory "
3445 "at addr %s len = 1.\n"),
3446 paddress (gdbarch, irp->addr));
3450 *addr = (int8_t) buf[0];
3453 if (target_read_memory (irp->addr, buf, 2))
3456 printf_unfiltered (_("Process record: error reading memory "
3457 "at addr %s len = 2.\n"),
3458 paddress (gdbarch, irp->addr));
3462 *addr = extract_signed_integer (buf, 2, byte_order);
3469 regcache_raw_read_unsigned (irp->regcache,
3470 irp->regmap[X86_RECORD_REBX_REGNUM],
3472 *addr = (uint32_t) (*addr + offset64);
3473 regcache_raw_read_unsigned (irp->regcache,
3474 irp->regmap[X86_RECORD_RESI_REGNUM],
3476 *addr = (uint32_t) (*addr + offset64);
3479 regcache_raw_read_unsigned (irp->regcache,
3480 irp->regmap[X86_RECORD_REBX_REGNUM],
3482 *addr = (uint32_t) (*addr + offset64);
3483 regcache_raw_read_unsigned (irp->regcache,
3484 irp->regmap[X86_RECORD_REDI_REGNUM],
3486 *addr = (uint32_t) (*addr + offset64);
3489 regcache_raw_read_unsigned (irp->regcache,
3490 irp->regmap[X86_RECORD_REBP_REGNUM],
3492 *addr = (uint32_t) (*addr + offset64);
3493 regcache_raw_read_unsigned (irp->regcache,
3494 irp->regmap[X86_RECORD_RESI_REGNUM],
3496 *addr = (uint32_t) (*addr + offset64);
3499 regcache_raw_read_unsigned (irp->regcache,
3500 irp->regmap[X86_RECORD_REBP_REGNUM],
3502 *addr = (uint32_t) (*addr + offset64);
3503 regcache_raw_read_unsigned (irp->regcache,
3504 irp->regmap[X86_RECORD_REDI_REGNUM],
3506 *addr = (uint32_t) (*addr + offset64);
3509 regcache_raw_read_unsigned (irp->regcache,
3510 irp->regmap[X86_RECORD_RESI_REGNUM],
3512 *addr = (uint32_t) (*addr + offset64);
3515 regcache_raw_read_unsigned (irp->regcache,
3516 irp->regmap[X86_RECORD_REDI_REGNUM],
3518 *addr = (uint32_t) (*addr + offset64);
3521 regcache_raw_read_unsigned (irp->regcache,
3522 irp->regmap[X86_RECORD_REBP_REGNUM],
3524 *addr = (uint32_t) (*addr + offset64);
3527 regcache_raw_read_unsigned (irp->regcache,
3528 irp->regmap[X86_RECORD_REBX_REGNUM],
3530 *addr = (uint32_t) (*addr + offset64);
3540 /* Record the value of the memory that willbe changed in current instruction
3541 to "record_arch_list".
3542 Return -1 if something wrong. */
3545 i386_record_lea_modrm (struct i386_record_s *irp)
3547 struct gdbarch *gdbarch = irp->gdbarch;
3550 if (irp->override >= 0)
3552 if (record_memory_query)
3556 target_terminal_ours ();
3558 Process record ignores the memory change of instruction at address %s\n\
3559 because it can't get the value of the segment register.\n\
3560 Do you want to stop the program?"),
3561 paddress (gdbarch, irp->orig_addr));
3562 target_terminal_inferior ();
3570 if (i386_record_lea_modrm_addr (irp, &addr))
3573 if (record_arch_list_add_mem (addr, 1 << irp->ot))
3579 /* Record the push operation to "record_arch_list".
3580 Return -1 if something wrong. */
3583 i386_record_push (struct i386_record_s *irp, int size)
3587 if (record_arch_list_add_reg (irp->regcache,
3588 irp->regmap[X86_RECORD_RESP_REGNUM]))
3590 regcache_raw_read_unsigned (irp->regcache,
3591 irp->regmap[X86_RECORD_RESP_REGNUM],
3593 if (record_arch_list_add_mem ((CORE_ADDR) addr - size, size))
3600 /* Defines contents to record. */
3601 #define I386_SAVE_FPU_REGS 0xfffd
3602 #define I386_SAVE_FPU_ENV 0xfffe
3603 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3605 /* Record the value of floating point registers which will be changed
3606 by the current instruction to "record_arch_list". Return -1 if
3607 something is wrong. */
3609 static int i386_record_floats (struct gdbarch *gdbarch,
3610 struct i386_record_s *ir,
3613 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3616 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3617 happen. Currently we store st0-st7 registers, but we need not store all
3618 registers all the time, in future we use ftag register and record only
3619 those who are not marked as an empty. */
3621 if (I386_SAVE_FPU_REGS == iregnum)
3623 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
3625 if (record_arch_list_add_reg (ir->regcache, i))
3629 else if (I386_SAVE_FPU_ENV == iregnum)
3631 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3633 if (record_arch_list_add_reg (ir->regcache, i))
3637 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
3639 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3641 if (record_arch_list_add_reg (ir->regcache, i))
3645 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
3646 (iregnum <= I387_FOP_REGNUM (tdep)))
3648 if (record_arch_list_add_reg (ir->regcache,iregnum))
3653 /* Parameter error. */
3656 if(I386_SAVE_FPU_ENV != iregnum)
3658 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3660 if (record_arch_list_add_reg (ir->regcache, i))
3667 /* Parse the current instruction and record the values of the registers and
3668 memory that will be changed in current instruction to "record_arch_list".
3669 Return -1 if something wrong. */
3671 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3672 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3675 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
3676 CORE_ADDR input_addr)
3678 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3684 gdb_byte buf[MAX_REGISTER_SIZE];
3685 struct i386_record_s ir;
3686 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3691 memset (&ir, 0, sizeof (struct i386_record_s));
3692 ir.regcache = regcache;
3693 ir.addr = input_addr;
3694 ir.orig_addr = input_addr;
3698 ir.popl_esp_hack = 0;
3699 ir.regmap = tdep->record_regmap;
3700 ir.gdbarch = gdbarch;
3702 if (record_debug > 1)
3703 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
3705 paddress (gdbarch, ir.addr));
3710 if (target_read_memory (ir.addr, &opcode8, 1))
3713 printf_unfiltered (_("Process record: error reading memory at "
3714 "addr %s len = 1.\n"),
3715 paddress (gdbarch, ir.addr));
3719 switch (opcode8) /* Instruction prefixes */
3721 case REPE_PREFIX_OPCODE:
3722 prefixes |= PREFIX_REPZ;
3724 case REPNE_PREFIX_OPCODE:
3725 prefixes |= PREFIX_REPNZ;
3727 case LOCK_PREFIX_OPCODE:
3728 prefixes |= PREFIX_LOCK;
3730 case CS_PREFIX_OPCODE:
3731 ir.override = X86_RECORD_CS_REGNUM;
3733 case SS_PREFIX_OPCODE:
3734 ir.override = X86_RECORD_SS_REGNUM;
3736 case DS_PREFIX_OPCODE:
3737 ir.override = X86_RECORD_DS_REGNUM;
3739 case ES_PREFIX_OPCODE:
3740 ir.override = X86_RECORD_ES_REGNUM;
3742 case FS_PREFIX_OPCODE:
3743 ir.override = X86_RECORD_FS_REGNUM;
3745 case GS_PREFIX_OPCODE:
3746 ir.override = X86_RECORD_GS_REGNUM;
3748 case DATA_PREFIX_OPCODE:
3749 prefixes |= PREFIX_DATA;
3751 case ADDR_PREFIX_OPCODE:
3752 prefixes |= PREFIX_ADDR;
3754 case 0x40: /* i386 inc %eax */
3755 case 0x41: /* i386 inc %ecx */
3756 case 0x42: /* i386 inc %edx */
3757 case 0x43: /* i386 inc %ebx */
3758 case 0x44: /* i386 inc %esp */
3759 case 0x45: /* i386 inc %ebp */
3760 case 0x46: /* i386 inc %esi */
3761 case 0x47: /* i386 inc %edi */
3762 case 0x48: /* i386 dec %eax */
3763 case 0x49: /* i386 dec %ecx */
3764 case 0x4a: /* i386 dec %edx */
3765 case 0x4b: /* i386 dec %ebx */
3766 case 0x4c: /* i386 dec %esp */
3767 case 0x4d: /* i386 dec %ebp */
3768 case 0x4e: /* i386 dec %esi */
3769 case 0x4f: /* i386 dec %edi */
3770 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
3774 rex_w = (opcode8 >> 3) & 1;
3775 rex_r = (opcode8 & 0x4) << 1;
3776 ir.rex_x = (opcode8 & 0x2) << 2;
3777 ir.rex_b = (opcode8 & 0x1) << 3;
3779 else /* 32 bit target */
3788 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
3794 if (prefixes & PREFIX_DATA)
3797 if (prefixes & PREFIX_ADDR)
3799 else if (ir.regmap[X86_RECORD_R8_REGNUM])
3802 /* Now check op code. */
3803 opcode = (uint32_t) opcode8;
3808 if (target_read_memory (ir.addr, &opcode8, 1))
3811 printf_unfiltered (_("Process record: error reading memory at "
3812 "addr %s len = 1.\n"),
3813 paddress (gdbarch, ir.addr));
3817 opcode = (uint32_t) opcode8 | 0x0f00;
3821 case 0x00: /* arith & logic */
3869 if (((opcode >> 3) & 7) != OP_CMPL)
3871 if ((opcode & 1) == 0)
3874 ir.ot = ir.dflag + OT_WORD;
3876 switch ((opcode >> 1) & 3)
3878 case 0: /* OP Ev, Gv */
3879 if (i386_record_modrm (&ir))
3883 if (i386_record_lea_modrm (&ir))
3889 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3891 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
3894 case 1: /* OP Gv, Ev */
3895 if (i386_record_modrm (&ir))
3898 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3900 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
3902 case 2: /* OP A, Iv */
3903 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
3907 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3910 case 0x80: /* GRP1 */
3914 if (i386_record_modrm (&ir))
3917 if (ir.reg != OP_CMPL)
3919 if ((opcode & 1) == 0)
3922 ir.ot = ir.dflag + OT_WORD;
3929 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
3930 if (i386_record_lea_modrm (&ir))
3934 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
3936 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3939 case 0x40: /* inc */
3948 case 0x48: /* dec */
3957 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7);
3958 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3961 case 0xf6: /* GRP3 */
3963 if ((opcode & 1) == 0)
3966 ir.ot = ir.dflag + OT_WORD;
3967 if (i386_record_modrm (&ir))
3970 if (ir.mod != 3 && ir.reg == 0)
3971 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
3976 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3982 if (i386_record_lea_modrm (&ir))
3988 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3990 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
3992 if (ir.reg == 3) /* neg */
3993 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3999 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4000 if (ir.ot != OT_BYTE)
4001 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
4002 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4006 opcode = opcode << 8 | ir.modrm;
4012 case 0xfe: /* GRP4 */
4013 case 0xff: /* GRP5 */
4014 if (i386_record_modrm (&ir))
4016 if (ir.reg >= 2 && opcode == 0xfe)
4019 opcode = opcode << 8 | ir.modrm;
4026 if ((opcode & 1) == 0)
4029 ir.ot = ir.dflag + OT_WORD;
4032 if (i386_record_lea_modrm (&ir))
4038 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4040 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4042 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4045 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4047 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4049 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4052 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
4053 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4055 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4059 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4062 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4064 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4069 opcode = opcode << 8 | ir.modrm;
4075 case 0x84: /* test */
4079 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4082 case 0x98: /* CWDE/CBW */
4083 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4086 case 0x99: /* CDQ/CWD */
4087 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4088 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
4091 case 0x0faf: /* imul */
4094 ir.ot = ir.dflag + OT_WORD;
4095 if (i386_record_modrm (&ir))
4098 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4099 else if (opcode == 0x6b)
4102 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4104 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4105 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4108 case 0x0fc0: /* xadd */
4110 if ((opcode & 1) == 0)
4113 ir.ot = ir.dflag + OT_WORD;
4114 if (i386_record_modrm (&ir))
4119 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4121 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4122 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4124 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4128 if (i386_record_lea_modrm (&ir))
4130 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4132 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4134 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4137 case 0x0fb0: /* cmpxchg */
4139 if ((opcode & 1) == 0)
4142 ir.ot = ir.dflag + OT_WORD;
4143 if (i386_record_modrm (&ir))
4148 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4149 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4151 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4155 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4156 if (i386_record_lea_modrm (&ir))
4159 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4162 case 0x0fc7: /* cmpxchg8b */
4163 if (i386_record_modrm (&ir))
4168 opcode = opcode << 8 | ir.modrm;
4171 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4172 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
4173 if (i386_record_lea_modrm (&ir))
4175 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4178 case 0x50: /* push */
4188 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4190 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4194 case 0x06: /* push es */
4195 case 0x0e: /* push cs */
4196 case 0x16: /* push ss */
4197 case 0x1e: /* push ds */
4198 if (ir.regmap[X86_RECORD_R8_REGNUM])
4203 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4207 case 0x0fa0: /* push fs */
4208 case 0x0fa8: /* push gs */
4209 if (ir.regmap[X86_RECORD_R8_REGNUM])
4214 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4218 case 0x60: /* pusha */
4219 if (ir.regmap[X86_RECORD_R8_REGNUM])
4224 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
4228 case 0x58: /* pop */
4236 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4237 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
4240 case 0x61: /* popa */
4241 if (ir.regmap[X86_RECORD_R8_REGNUM])
4246 for (regnum = X86_RECORD_REAX_REGNUM;
4247 regnum <= X86_RECORD_REDI_REGNUM;
4249 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
4252 case 0x8f: /* pop */
4253 if (ir.regmap[X86_RECORD_R8_REGNUM])
4254 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
4256 ir.ot = ir.dflag + OT_WORD;
4257 if (i386_record_modrm (&ir))
4260 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
4263 ir.popl_esp_hack = 1 << ir.ot;
4264 if (i386_record_lea_modrm (&ir))
4267 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4270 case 0xc8: /* enter */
4271 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
4272 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4274 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4278 case 0xc9: /* leave */
4279 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4280 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
4283 case 0x07: /* pop es */
4284 if (ir.regmap[X86_RECORD_R8_REGNUM])
4289 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4290 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
4291 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4294 case 0x17: /* pop ss */
4295 if (ir.regmap[X86_RECORD_R8_REGNUM])
4300 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4301 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
4302 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4305 case 0x1f: /* pop ds */
4306 if (ir.regmap[X86_RECORD_R8_REGNUM])
4311 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4312 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
4313 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4316 case 0x0fa1: /* pop fs */
4317 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4318 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
4319 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4322 case 0x0fa9: /* pop gs */
4323 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4324 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
4325 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4328 case 0x88: /* mov */
4332 if ((opcode & 1) == 0)
4335 ir.ot = ir.dflag + OT_WORD;
4337 if (i386_record_modrm (&ir))
4342 if (opcode == 0xc6 || opcode == 0xc7)
4343 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4344 if (i386_record_lea_modrm (&ir))
4349 if (opcode == 0xc6 || opcode == 0xc7)
4351 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4353 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4357 case 0x8a: /* mov */
4359 if ((opcode & 1) == 0)
4362 ir.ot = ir.dflag + OT_WORD;
4363 if (i386_record_modrm (&ir))
4366 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4368 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4371 case 0x8c: /* mov seg */
4372 if (i386_record_modrm (&ir))
4377 opcode = opcode << 8 | ir.modrm;
4382 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4386 if (i386_record_lea_modrm (&ir))
4391 case 0x8e: /* mov seg */
4392 if (i386_record_modrm (&ir))
4397 regnum = X86_RECORD_ES_REGNUM;
4400 regnum = X86_RECORD_SS_REGNUM;
4403 regnum = X86_RECORD_DS_REGNUM;
4406 regnum = X86_RECORD_FS_REGNUM;
4409 regnum = X86_RECORD_GS_REGNUM;
4413 opcode = opcode << 8 | ir.modrm;
4417 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
4418 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4421 case 0x0fb6: /* movzbS */
4422 case 0x0fb7: /* movzwS */
4423 case 0x0fbe: /* movsbS */
4424 case 0x0fbf: /* movswS */
4425 if (i386_record_modrm (&ir))
4427 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
4430 case 0x8d: /* lea */
4431 if (i386_record_modrm (&ir))
4436 opcode = opcode << 8 | ir.modrm;
4441 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4443 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4446 case 0xa0: /* mov EAX */
4449 case 0xd7: /* xlat */
4450 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4453 case 0xa2: /* mov EAX */
4455 if (ir.override >= 0)
4457 if (record_memory_query)
4461 target_terminal_ours ();
4463 Process record ignores the memory change of instruction at address %s\n\
4464 because it can't get the value of the segment register.\n\
4465 Do you want to stop the program?"),
4466 paddress (gdbarch, ir.orig_addr));
4467 target_terminal_inferior ();
4474 if ((opcode & 1) == 0)
4477 ir.ot = ir.dflag + OT_WORD;
4480 if (target_read_memory (ir.addr, buf, 8))
4483 printf_unfiltered (_("Process record: error reading "
4484 "memory at addr 0x%s len = 8.\n"),
4485 paddress (gdbarch, ir.addr));
4489 addr = extract_unsigned_integer (buf, 8, byte_order);
4493 if (target_read_memory (ir.addr, buf, 4))
4496 printf_unfiltered (_("Process record: error reading "
4497 "memory at addr 0x%s len = 4.\n"),
4498 paddress (gdbarch, ir.addr));
4502 addr = extract_unsigned_integer (buf, 4, byte_order);
4506 if (target_read_memory (ir.addr, buf, 2))
4509 printf_unfiltered (_("Process record: error reading "
4510 "memory at addr 0x%s len = 2.\n"),
4511 paddress (gdbarch, ir.addr));
4515 addr = extract_unsigned_integer (buf, 2, byte_order);
4517 if (record_arch_list_add_mem (addr, 1 << ir.ot))
4522 case 0xb0: /* mov R, Ib */
4530 I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
4531 ? ((opcode & 0x7) | ir.rex_b)
4532 : ((opcode & 0x7) & 0x3));
4535 case 0xb8: /* mov R, Iv */
4543 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
4546 case 0x91: /* xchg R, EAX */
4553 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4554 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7);
4557 case 0x86: /* xchg Ev, Gv */
4559 if ((opcode & 1) == 0)
4562 ir.ot = ir.dflag + OT_WORD;
4563 if (i386_record_modrm (&ir))
4568 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4570 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4574 if (i386_record_lea_modrm (&ir))
4578 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4580 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4583 case 0xc4: /* les Gv */
4584 case 0xc5: /* lds Gv */
4585 if (ir.regmap[X86_RECORD_R8_REGNUM])
4591 case 0x0fb2: /* lss Gv */
4592 case 0x0fb4: /* lfs Gv */
4593 case 0x0fb5: /* lgs Gv */
4594 if (i386_record_modrm (&ir))
4602 opcode = opcode << 8 | ir.modrm;
4607 case 0xc4: /* les Gv */
4608 regnum = X86_RECORD_ES_REGNUM;
4610 case 0xc5: /* lds Gv */
4611 regnum = X86_RECORD_DS_REGNUM;
4613 case 0x0fb2: /* lss Gv */
4614 regnum = X86_RECORD_SS_REGNUM;
4616 case 0x0fb4: /* lfs Gv */
4617 regnum = X86_RECORD_FS_REGNUM;
4619 case 0x0fb5: /* lgs Gv */
4620 regnum = X86_RECORD_GS_REGNUM;
4623 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
4624 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
4625 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4628 case 0xc0: /* shifts */
4634 if ((opcode & 1) == 0)
4637 ir.ot = ir.dflag + OT_WORD;
4638 if (i386_record_modrm (&ir))
4640 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
4642 if (i386_record_lea_modrm (&ir))
4648 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4650 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4652 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4659 if (i386_record_modrm (&ir))
4663 if (record_arch_list_add_reg (ir.regcache, ir.rm))
4668 if (i386_record_lea_modrm (&ir))
4673 case 0xd8: /* Floats. */
4681 if (i386_record_modrm (&ir))
4683 ir.reg |= ((opcode & 7) << 3);
4689 if (i386_record_lea_modrm_addr (&ir, &addr64))
4697 /* For fcom, ficom nothing to do. */
4703 /* For fcomp, ficomp pop FPU stack, store all. */
4704 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4731 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
4732 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
4733 of code, always affects st(0) register. */
4734 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
4758 /* Handling fld, fild. */
4759 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4763 switch (ir.reg >> 4)
4766 if (record_arch_list_add_mem (addr64, 4))
4770 if (record_arch_list_add_mem (addr64, 8))
4776 if (record_arch_list_add_mem (addr64, 2))
4782 switch (ir.reg >> 4)
4785 if (record_arch_list_add_mem (addr64, 4))
4787 if (3 == (ir.reg & 7))
4789 /* For fstp m32fp. */
4790 if (i386_record_floats (gdbarch, &ir,
4791 I386_SAVE_FPU_REGS))
4796 if (record_arch_list_add_mem (addr64, 4))
4798 if ((3 == (ir.reg & 7))
4799 || (5 == (ir.reg & 7))
4800 || (7 == (ir.reg & 7)))
4802 /* For fstp insn. */
4803 if (i386_record_floats (gdbarch, &ir,
4804 I386_SAVE_FPU_REGS))
4809 if (record_arch_list_add_mem (addr64, 8))
4811 if (3 == (ir.reg & 7))
4813 /* For fstp m64fp. */
4814 if (i386_record_floats (gdbarch, &ir,
4815 I386_SAVE_FPU_REGS))
4820 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
4822 /* For fistp, fbld, fild, fbstp. */
4823 if (i386_record_floats (gdbarch, &ir,
4824 I386_SAVE_FPU_REGS))
4829 if (record_arch_list_add_mem (addr64, 2))
4838 if (i386_record_floats (gdbarch, &ir,
4839 I386_SAVE_FPU_ENV_REG_STACK))
4844 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
4849 if (i386_record_floats (gdbarch, &ir,
4850 I386_SAVE_FPU_ENV_REG_STACK))
4856 if (record_arch_list_add_mem (addr64, 28))
4861 if (record_arch_list_add_mem (addr64, 14))
4867 if (record_arch_list_add_mem (addr64, 2))
4869 /* Insn fstp, fbstp. */
4870 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4875 if (record_arch_list_add_mem (addr64, 10))
4881 if (record_arch_list_add_mem (addr64, 28))
4887 if (record_arch_list_add_mem (addr64, 14))
4891 if (record_arch_list_add_mem (addr64, 80))
4894 if (i386_record_floats (gdbarch, &ir,
4895 I386_SAVE_FPU_ENV_REG_STACK))
4899 if (record_arch_list_add_mem (addr64, 8))
4902 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4907 opcode = opcode << 8 | ir.modrm;
4912 /* Opcode is an extension of modR/M byte. */
4918 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
4922 if (0x0c == (ir.modrm >> 4))
4924 if ((ir.modrm & 0x0f) <= 7)
4926 if (i386_record_floats (gdbarch, &ir,
4927 I386_SAVE_FPU_REGS))
4932 if (i386_record_floats (gdbarch, &ir,
4933 I387_ST0_REGNUM (tdep)))
4935 /* If only st(0) is changing, then we have already
4937 if ((ir.modrm & 0x0f) - 0x08)
4939 if (i386_record_floats (gdbarch, &ir,
4940 I387_ST0_REGNUM (tdep) +
4941 ((ir.modrm & 0x0f) - 0x08)))
4959 if (i386_record_floats (gdbarch, &ir,
4960 I387_ST0_REGNUM (tdep)))
4978 if (i386_record_floats (gdbarch, &ir,
4979 I386_SAVE_FPU_REGS))
4983 if (i386_record_floats (gdbarch, &ir,
4984 I387_ST0_REGNUM (tdep)))
4986 if (i386_record_floats (gdbarch, &ir,
4987 I387_ST0_REGNUM (tdep) + 1))
4994 if (0xe9 == ir.modrm)
4996 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4999 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
5001 if (i386_record_floats (gdbarch, &ir,
5002 I387_ST0_REGNUM (tdep)))
5004 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
5006 if (i386_record_floats (gdbarch, &ir,
5007 I387_ST0_REGNUM (tdep) +
5011 else if ((ir.modrm & 0x0f) - 0x08)
5013 if (i386_record_floats (gdbarch, &ir,
5014 I387_ST0_REGNUM (tdep) +
5015 ((ir.modrm & 0x0f) - 0x08)))
5021 if (0xe3 == ir.modrm)
5023 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
5026 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
5028 if (i386_record_floats (gdbarch, &ir,
5029 I387_ST0_REGNUM (tdep)))
5031 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
5033 if (i386_record_floats (gdbarch, &ir,
5034 I387_ST0_REGNUM (tdep) +
5038 else if ((ir.modrm & 0x0f) - 0x08)
5040 if (i386_record_floats (gdbarch, &ir,
5041 I387_ST0_REGNUM (tdep) +
5042 ((ir.modrm & 0x0f) - 0x08)))
5048 if ((0x0c == ir.modrm >> 4)
5049 || (0x0d == ir.modrm >> 4)
5050 || (0x0f == ir.modrm >> 4))
5052 if ((ir.modrm & 0x0f) <= 7)
5054 if (i386_record_floats (gdbarch, &ir,
5055 I387_ST0_REGNUM (tdep) +
5061 if (i386_record_floats (gdbarch, &ir,
5062 I387_ST0_REGNUM (tdep) +
5063 ((ir.modrm & 0x0f) - 0x08)))
5069 if (0x0c == ir.modrm >> 4)
5071 if (i386_record_floats (gdbarch, &ir,
5072 I387_FTAG_REGNUM (tdep)))
5075 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
5077 if ((ir.modrm & 0x0f) <= 7)
5079 if (i386_record_floats (gdbarch, &ir,
5080 I387_ST0_REGNUM (tdep) +
5086 if (i386_record_floats (gdbarch, &ir,
5087 I386_SAVE_FPU_REGS))
5093 if ((0x0c == ir.modrm >> 4)
5094 || (0x0e == ir.modrm >> 4)
5095 || (0x0f == ir.modrm >> 4)
5096 || (0xd9 == ir.modrm))
5098 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5103 if (0xe0 == ir.modrm)
5105 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
5108 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
5110 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5118 case 0xa4: /* movsS */
5120 case 0xaa: /* stosS */
5122 case 0x6c: /* insS */
5124 regcache_raw_read_unsigned (ir.regcache,
5125 ir.regmap[X86_RECORD_RECX_REGNUM],
5131 if ((opcode & 1) == 0)
5134 ir.ot = ir.dflag + OT_WORD;
5135 regcache_raw_read_unsigned (ir.regcache,
5136 ir.regmap[X86_RECORD_REDI_REGNUM],
5139 regcache_raw_read_unsigned (ir.regcache,
5140 ir.regmap[X86_RECORD_ES_REGNUM],
5142 regcache_raw_read_unsigned (ir.regcache,
5143 ir.regmap[X86_RECORD_DS_REGNUM],
5145 if (ir.aflag && (es != ds))
5147 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5148 if (record_memory_query)
5152 target_terminal_ours ();
5154 Process record ignores the memory change of instruction at address %s\n\
5155 because it can't get the value of the segment register.\n\
5156 Do you want to stop the program?"),
5157 paddress (gdbarch, ir.orig_addr));
5158 target_terminal_inferior ();
5165 if (record_arch_list_add_mem (addr, 1 << ir.ot))
5169 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5170 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5171 if (opcode == 0xa4 || opcode == 0xa5)
5172 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5173 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5174 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5178 case 0xa6: /* cmpsS */
5180 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5181 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5182 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5183 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5184 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5187 case 0xac: /* lodsS */
5189 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5190 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5191 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5192 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5193 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5196 case 0xae: /* scasS */
5198 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5199 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5200 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5201 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5204 case 0x6e: /* outsS */
5206 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5207 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5208 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5209 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5212 case 0xe4: /* port I/O */
5216 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5217 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5227 case 0xc2: /* ret im */
5228 case 0xc3: /* ret */
5229 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5230 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5233 case 0xca: /* lret im */
5234 case 0xcb: /* lret */
5235 case 0xcf: /* iret */
5236 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5237 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5238 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5241 case 0xe8: /* call im */
5242 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5244 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5248 case 0x9a: /* lcall im */
5249 if (ir.regmap[X86_RECORD_R8_REGNUM])
5254 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5255 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5259 case 0xe9: /* jmp im */
5260 case 0xea: /* ljmp im */
5261 case 0xeb: /* jmp Jb */
5262 case 0x70: /* jcc Jb */
5278 case 0x0f80: /* jcc Jv */
5296 case 0x0f90: /* setcc Gv */
5312 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5314 if (i386_record_modrm (&ir))
5317 I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
5321 if (i386_record_lea_modrm (&ir))
5326 case 0x0f40: /* cmov Gv, Ev */
5342 if (i386_record_modrm (&ir))
5345 if (ir.dflag == OT_BYTE)
5347 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
5351 case 0x9c: /* pushf */
5352 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5353 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5355 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5359 case 0x9d: /* popf */
5360 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5361 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5364 case 0x9e: /* sahf */
5365 if (ir.regmap[X86_RECORD_R8_REGNUM])
5371 case 0xf5: /* cmc */
5372 case 0xf8: /* clc */
5373 case 0xf9: /* stc */
5374 case 0xfc: /* cld */
5375 case 0xfd: /* std */
5376 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5379 case 0x9f: /* lahf */
5380 if (ir.regmap[X86_RECORD_R8_REGNUM])
5385 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5386 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5389 /* bit operations */
5390 case 0x0fba: /* bt/bts/btr/btc Gv, im */
5391 ir.ot = ir.dflag + OT_WORD;
5392 if (i386_record_modrm (&ir))
5397 opcode = opcode << 8 | ir.modrm;
5403 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5406 if (i386_record_lea_modrm (&ir))
5410 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5413 case 0x0fa3: /* bt Gv, Ev */
5414 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5417 case 0x0fab: /* bts */
5418 case 0x0fb3: /* btr */
5419 case 0x0fbb: /* btc */
5420 ir.ot = ir.dflag + OT_WORD;
5421 if (i386_record_modrm (&ir))
5424 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5428 if (i386_record_lea_modrm_addr (&ir, &addr64))
5430 regcache_raw_read_unsigned (ir.regcache,
5431 ir.regmap[ir.reg | rex_r],
5436 addr64 += ((int16_t) addr >> 4) << 4;
5439 addr64 += ((int32_t) addr >> 5) << 5;
5442 addr64 += ((int64_t) addr >> 6) << 6;
5445 if (record_arch_list_add_mem (addr64, 1 << ir.ot))
5447 if (i386_record_lea_modrm (&ir))
5450 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5453 case 0x0fbc: /* bsf */
5454 case 0x0fbd: /* bsr */
5455 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5456 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5460 case 0x27: /* daa */
5461 case 0x2f: /* das */
5462 case 0x37: /* aaa */
5463 case 0x3f: /* aas */
5464 case 0xd4: /* aam */
5465 case 0xd5: /* aad */
5466 if (ir.regmap[X86_RECORD_R8_REGNUM])
5471 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5472 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5476 case 0x90: /* nop */
5477 if (prefixes & PREFIX_LOCK)
5484 case 0x9b: /* fwait */
5485 if (target_read_memory (ir.addr, &opcode8, 1))
5488 printf_unfiltered (_("Process record: error reading memory at "
5489 "addr 0x%s len = 1.\n"),
5490 paddress (gdbarch, ir.addr));
5493 opcode = (uint32_t) opcode8;
5499 case 0xcc: /* int3 */
5500 printf_unfiltered (_("Process record does not support instruction "
5507 case 0xcd: /* int */
5511 if (target_read_memory (ir.addr, &interrupt, 1))
5514 printf_unfiltered (_("Process record: error reading memory "
5515 "at addr %s len = 1.\n"),
5516 paddress (gdbarch, ir.addr));
5520 if (interrupt != 0x80
5521 || tdep->i386_intx80_record == NULL)
5523 printf_unfiltered (_("Process record does not support "
5524 "instruction int 0x%02x.\n"),
5529 ret = tdep->i386_intx80_record (ir.regcache);
5536 case 0xce: /* into */
5537 printf_unfiltered (_("Process record does not support "
5538 "instruction into.\n"));
5543 case 0xfa: /* cli */
5544 case 0xfb: /* sti */
5547 case 0x62: /* bound */
5548 printf_unfiltered (_("Process record does not support "
5549 "instruction bound.\n"));
5554 case 0x0fc8: /* bswap reg */
5562 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
5565 case 0xd6: /* salc */
5566 if (ir.regmap[X86_RECORD_R8_REGNUM])
5571 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5572 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5575 case 0xe0: /* loopnz */
5576 case 0xe1: /* loopz */
5577 case 0xe2: /* loop */
5578 case 0xe3: /* jecxz */
5579 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5580 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5583 case 0x0f30: /* wrmsr */
5584 printf_unfiltered (_("Process record does not support "
5585 "instruction wrmsr.\n"));
5590 case 0x0f32: /* rdmsr */
5591 printf_unfiltered (_("Process record does not support "
5592 "instruction rdmsr.\n"));
5597 case 0x0f31: /* rdtsc */
5598 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5599 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5602 case 0x0f34: /* sysenter */
5605 if (ir.regmap[X86_RECORD_R8_REGNUM])
5610 if (tdep->i386_sysenter_record == NULL)
5612 printf_unfiltered (_("Process record does not support "
5613 "instruction sysenter.\n"));
5617 ret = tdep->i386_sysenter_record (ir.regcache);
5623 case 0x0f35: /* sysexit */
5624 printf_unfiltered (_("Process record does not support "
5625 "instruction sysexit.\n"));
5630 case 0x0f05: /* syscall */
5633 if (tdep->i386_syscall_record == NULL)
5635 printf_unfiltered (_("Process record does not support "
5636 "instruction syscall.\n"));
5640 ret = tdep->i386_syscall_record (ir.regcache);
5646 case 0x0f07: /* sysret */
5647 printf_unfiltered (_("Process record does not support "
5648 "instruction sysret.\n"));
5653 case 0x0fa2: /* cpuid */
5654 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5655 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5656 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5657 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
5660 case 0xf4: /* hlt */
5661 printf_unfiltered (_("Process record does not support "
5662 "instruction hlt.\n"));
5668 if (i386_record_modrm (&ir))
5675 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5679 if (i386_record_lea_modrm (&ir))
5688 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5692 opcode = opcode << 8 | ir.modrm;
5699 if (i386_record_modrm (&ir))
5710 opcode = opcode << 8 | ir.modrm;
5713 if (ir.override >= 0)
5715 if (record_memory_query)
5719 target_terminal_ours ();
5721 Process record ignores the memory change of instruction at address %s\n\
5722 because it can't get the value of the segment register.\n\
5723 Do you want to stop the program?"),
5724 paddress (gdbarch, ir.orig_addr));
5725 target_terminal_inferior ();
5732 if (i386_record_lea_modrm_addr (&ir, &addr64))
5734 if (record_arch_list_add_mem (addr64, 2))
5737 if (ir.regmap[X86_RECORD_R8_REGNUM])
5739 if (record_arch_list_add_mem (addr64, 8))
5744 if (record_arch_list_add_mem (addr64, 4))
5755 case 0: /* monitor */
5758 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5762 opcode = opcode << 8 | ir.modrm;
5770 if (ir.override >= 0)
5772 if (record_memory_query)
5776 target_terminal_ours ();
5778 Process record ignores the memory change of instruction at address %s\n\
5779 because it can't get the value of the segment register.\n\
5780 Do you want to stop the program?"),
5781 paddress (gdbarch, ir.orig_addr));
5782 target_terminal_inferior ();
5791 if (i386_record_lea_modrm_addr (&ir, &addr64))
5793 if (record_arch_list_add_mem (addr64, 2))
5796 if (ir.regmap[X86_RECORD_R8_REGNUM])
5798 if (record_arch_list_add_mem (addr64, 8))
5803 if (record_arch_list_add_mem (addr64, 4))
5815 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5816 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5820 else if (ir.rm == 1)
5827 opcode = opcode << 8 | ir.modrm;
5834 if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
5840 if (i386_record_lea_modrm (&ir))
5843 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5846 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5848 case 7: /* invlpg */
5851 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
5852 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
5856 opcode = opcode << 8 | ir.modrm;
5861 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5865 opcode = opcode << 8 | ir.modrm;
5871 case 0x0f08: /* invd */
5872 case 0x0f09: /* wbinvd */
5875 case 0x63: /* arpl */
5876 if (i386_record_modrm (&ir))
5878 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
5880 I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
5881 ? (ir.reg | rex_r) : ir.rm);
5885 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
5886 if (i386_record_lea_modrm (&ir))
5889 if (!ir.regmap[X86_RECORD_R8_REGNUM])
5890 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5893 case 0x0f02: /* lar */
5894 case 0x0f03: /* lsl */
5895 if (i386_record_modrm (&ir))
5897 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5898 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5902 if (i386_record_modrm (&ir))
5904 if (ir.mod == 3 && ir.reg == 3)
5907 opcode = opcode << 8 | ir.modrm;
5919 /* nop (multi byte) */
5922 case 0x0f20: /* mov reg, crN */
5923 case 0x0f22: /* mov crN, reg */
5924 if (i386_record_modrm (&ir))
5926 if ((ir.modrm & 0xc0) != 0xc0)
5929 opcode = opcode << 8 | ir.modrm;
5940 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5942 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5946 opcode = opcode << 8 | ir.modrm;
5952 case 0x0f21: /* mov reg, drN */
5953 case 0x0f23: /* mov drN, reg */
5954 if (i386_record_modrm (&ir))
5956 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
5957 || ir.reg == 5 || ir.reg >= 8)
5960 opcode = opcode << 8 | ir.modrm;
5964 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5966 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5969 case 0x0f06: /* clts */
5970 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5973 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
5975 case 0x0f0d: /* 3DNow! prefetch */
5978 case 0x0f0e: /* 3DNow! femms */
5979 case 0x0f77: /* emms */
5980 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
5982 record_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
5985 case 0x0f0f: /* 3DNow! data */
5986 if (i386_record_modrm (&ir))
5988 if (target_read_memory (ir.addr, &opcode8, 1))
5990 printf_unfiltered (_("Process record: error reading memory at "
5991 "addr %s len = 1.\n"),
5992 paddress (gdbarch, ir.addr));
5998 case 0x0c: /* 3DNow! pi2fw */
5999 case 0x0d: /* 3DNow! pi2fd */
6000 case 0x1c: /* 3DNow! pf2iw */
6001 case 0x1d: /* 3DNow! pf2id */
6002 case 0x8a: /* 3DNow! pfnacc */
6003 case 0x8e: /* 3DNow! pfpnacc */
6004 case 0x90: /* 3DNow! pfcmpge */
6005 case 0x94: /* 3DNow! pfmin */
6006 case 0x96: /* 3DNow! pfrcp */
6007 case 0x97: /* 3DNow! pfrsqrt */
6008 case 0x9a: /* 3DNow! pfsub */
6009 case 0x9e: /* 3DNow! pfadd */
6010 case 0xa0: /* 3DNow! pfcmpgt */
6011 case 0xa4: /* 3DNow! pfmax */
6012 case 0xa6: /* 3DNow! pfrcpit1 */
6013 case 0xa7: /* 3DNow! pfrsqit1 */
6014 case 0xaa: /* 3DNow! pfsubr */
6015 case 0xae: /* 3DNow! pfacc */
6016 case 0xb0: /* 3DNow! pfcmpeq */
6017 case 0xb4: /* 3DNow! pfmul */
6018 case 0xb6: /* 3DNow! pfrcpit2 */
6019 case 0xb7: /* 3DNow! pmulhrw */
6020 case 0xbb: /* 3DNow! pswapd */
6021 case 0xbf: /* 3DNow! pavgusb */
6022 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
6023 goto no_support_3dnow_data;
6024 record_arch_list_add_reg (ir.regcache, ir.reg);
6028 no_support_3dnow_data:
6029 opcode = (opcode << 8) | opcode8;
6035 case 0x0faa: /* rsm */
6036 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6037 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6038 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6039 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6040 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
6041 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6042 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
6043 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6044 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6048 if (i386_record_modrm (&ir))
6052 case 0: /* fxsave */
6056 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6057 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
6059 if (record_arch_list_add_mem (tmpu64, 512))
6064 case 1: /* fxrstor */
6068 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6070 for (i = I387_MM0_REGNUM (tdep);
6071 i386_mmx_regnum_p (gdbarch, i); i++)
6072 record_arch_list_add_reg (ir.regcache, i);
6074 for (i = I387_XMM0_REGNUM (tdep);
6075 i386_xmm_regnum_p (gdbarch, i); i++)
6076 record_arch_list_add_reg (ir.regcache, i);
6078 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
6079 record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
6081 for (i = I387_ST0_REGNUM (tdep);
6082 i386_fp_regnum_p (gdbarch, i); i++)
6083 record_arch_list_add_reg (ir.regcache, i);
6085 for (i = I387_FCTRL_REGNUM (tdep);
6086 i386_fpc_regnum_p (gdbarch, i); i++)
6087 record_arch_list_add_reg (ir.regcache, i);
6091 case 2: /* ldmxcsr */
6092 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
6094 record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
6097 case 3: /* stmxcsr */
6099 if (i386_record_lea_modrm (&ir))
6103 case 5: /* lfence */
6104 case 6: /* mfence */
6105 case 7: /* sfence clflush */
6109 opcode = (opcode << 8) | ir.modrm;
6115 case 0x0fc3: /* movnti */
6116 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
6117 if (i386_record_modrm (&ir))
6122 if (i386_record_lea_modrm (&ir))
6126 /* Add prefix to opcode. */
6253 reswitch_prefix_add:
6261 if (target_read_memory (ir.addr, &opcode8, 1))
6263 printf_unfiltered (_("Process record: error reading memory at "
6264 "addr %s len = 1.\n"),
6265 paddress (gdbarch, ir.addr));
6269 opcode = (uint32_t) opcode8 | opcode << 8;
6270 goto reswitch_prefix_add;
6273 case 0x0f10: /* movups */
6274 case 0x660f10: /* movupd */
6275 case 0xf30f10: /* movss */
6276 case 0xf20f10: /* movsd */
6277 case 0x0f12: /* movlps */
6278 case 0x660f12: /* movlpd */
6279 case 0xf30f12: /* movsldup */
6280 case 0xf20f12: /* movddup */
6281 case 0x0f14: /* unpcklps */
6282 case 0x660f14: /* unpcklpd */
6283 case 0x0f15: /* unpckhps */
6284 case 0x660f15: /* unpckhpd */
6285 case 0x0f16: /* movhps */
6286 case 0x660f16: /* movhpd */
6287 case 0xf30f16: /* movshdup */
6288 case 0x0f28: /* movaps */
6289 case 0x660f28: /* movapd */
6290 case 0x0f2a: /* cvtpi2ps */
6291 case 0x660f2a: /* cvtpi2pd */
6292 case 0xf30f2a: /* cvtsi2ss */
6293 case 0xf20f2a: /* cvtsi2sd */
6294 case 0x0f2c: /* cvttps2pi */
6295 case 0x660f2c: /* cvttpd2pi */
6296 case 0x0f2d: /* cvtps2pi */
6297 case 0x660f2d: /* cvtpd2pi */
6298 case 0x660f3800: /* pshufb */
6299 case 0x660f3801: /* phaddw */
6300 case 0x660f3802: /* phaddd */
6301 case 0x660f3803: /* phaddsw */
6302 case 0x660f3804: /* pmaddubsw */
6303 case 0x660f3805: /* phsubw */
6304 case 0x660f3806: /* phsubd */
6305 case 0x660f3807: /* phsubsw */
6306 case 0x660f3808: /* psignb */
6307 case 0x660f3809: /* psignw */
6308 case 0x660f380a: /* psignd */
6309 case 0x660f380b: /* pmulhrsw */
6310 case 0x660f3810: /* pblendvb */
6311 case 0x660f3814: /* blendvps */
6312 case 0x660f3815: /* blendvpd */
6313 case 0x660f381c: /* pabsb */
6314 case 0x660f381d: /* pabsw */
6315 case 0x660f381e: /* pabsd */
6316 case 0x660f3820: /* pmovsxbw */
6317 case 0x660f3821: /* pmovsxbd */
6318 case 0x660f3822: /* pmovsxbq */
6319 case 0x660f3823: /* pmovsxwd */
6320 case 0x660f3824: /* pmovsxwq */
6321 case 0x660f3825: /* pmovsxdq */
6322 case 0x660f3828: /* pmuldq */
6323 case 0x660f3829: /* pcmpeqq */
6324 case 0x660f382a: /* movntdqa */
6325 case 0x660f3a08: /* roundps */
6326 case 0x660f3a09: /* roundpd */
6327 case 0x660f3a0a: /* roundss */
6328 case 0x660f3a0b: /* roundsd */
6329 case 0x660f3a0c: /* blendps */
6330 case 0x660f3a0d: /* blendpd */
6331 case 0x660f3a0e: /* pblendw */
6332 case 0x660f3a0f: /* palignr */
6333 case 0x660f3a20: /* pinsrb */
6334 case 0x660f3a21: /* insertps */
6335 case 0x660f3a22: /* pinsrd pinsrq */
6336 case 0x660f3a40: /* dpps */
6337 case 0x660f3a41: /* dppd */
6338 case 0x660f3a42: /* mpsadbw */
6339 case 0x660f3a60: /* pcmpestrm */
6340 case 0x660f3a61: /* pcmpestri */
6341 case 0x660f3a62: /* pcmpistrm */
6342 case 0x660f3a63: /* pcmpistri */
6343 case 0x0f51: /* sqrtps */
6344 case 0x660f51: /* sqrtpd */
6345 case 0xf20f51: /* sqrtsd */
6346 case 0xf30f51: /* sqrtss */
6347 case 0x0f52: /* rsqrtps */
6348 case 0xf30f52: /* rsqrtss */
6349 case 0x0f53: /* rcpps */
6350 case 0xf30f53: /* rcpss */
6351 case 0x0f54: /* andps */
6352 case 0x660f54: /* andpd */
6353 case 0x0f55: /* andnps */
6354 case 0x660f55: /* andnpd */
6355 case 0x0f56: /* orps */
6356 case 0x660f56: /* orpd */
6357 case 0x0f57: /* xorps */
6358 case 0x660f57: /* xorpd */
6359 case 0x0f58: /* addps */
6360 case 0x660f58: /* addpd */
6361 case 0xf20f58: /* addsd */
6362 case 0xf30f58: /* addss */
6363 case 0x0f59: /* mulps */
6364 case 0x660f59: /* mulpd */
6365 case 0xf20f59: /* mulsd */
6366 case 0xf30f59: /* mulss */
6367 case 0x0f5a: /* cvtps2pd */
6368 case 0x660f5a: /* cvtpd2ps */
6369 case 0xf20f5a: /* cvtsd2ss */
6370 case 0xf30f5a: /* cvtss2sd */
6371 case 0x0f5b: /* cvtdq2ps */
6372 case 0x660f5b: /* cvtps2dq */
6373 case 0xf30f5b: /* cvttps2dq */
6374 case 0x0f5c: /* subps */
6375 case 0x660f5c: /* subpd */
6376 case 0xf20f5c: /* subsd */
6377 case 0xf30f5c: /* subss */
6378 case 0x0f5d: /* minps */
6379 case 0x660f5d: /* minpd */
6380 case 0xf20f5d: /* minsd */
6381 case 0xf30f5d: /* minss */
6382 case 0x0f5e: /* divps */
6383 case 0x660f5e: /* divpd */
6384 case 0xf20f5e: /* divsd */
6385 case 0xf30f5e: /* divss */
6386 case 0x0f5f: /* maxps */
6387 case 0x660f5f: /* maxpd */
6388 case 0xf20f5f: /* maxsd */
6389 case 0xf30f5f: /* maxss */
6390 case 0x660f60: /* punpcklbw */
6391 case 0x660f61: /* punpcklwd */
6392 case 0x660f62: /* punpckldq */
6393 case 0x660f63: /* packsswb */
6394 case 0x660f64: /* pcmpgtb */
6395 case 0x660f65: /* pcmpgtw */
6396 case 0x660f66: /* pcmpgtd */
6397 case 0x660f67: /* packuswb */
6398 case 0x660f68: /* punpckhbw */
6399 case 0x660f69: /* punpckhwd */
6400 case 0x660f6a: /* punpckhdq */
6401 case 0x660f6b: /* packssdw */
6402 case 0x660f6c: /* punpcklqdq */
6403 case 0x660f6d: /* punpckhqdq */
6404 case 0x660f6e: /* movd */
6405 case 0x660f6f: /* movdqa */
6406 case 0xf30f6f: /* movdqu */
6407 case 0x660f70: /* pshufd */
6408 case 0xf20f70: /* pshuflw */
6409 case 0xf30f70: /* pshufhw */
6410 case 0x660f74: /* pcmpeqb */
6411 case 0x660f75: /* pcmpeqw */
6412 case 0x660f76: /* pcmpeqd */
6413 case 0x660f7c: /* haddpd */
6414 case 0xf20f7c: /* haddps */
6415 case 0x660f7d: /* hsubpd */
6416 case 0xf20f7d: /* hsubps */
6417 case 0xf30f7e: /* movq */
6418 case 0x0fc2: /* cmpps */
6419 case 0x660fc2: /* cmppd */
6420 case 0xf20fc2: /* cmpsd */
6421 case 0xf30fc2: /* cmpss */
6422 case 0x660fc4: /* pinsrw */
6423 case 0x0fc6: /* shufps */
6424 case 0x660fc6: /* shufpd */
6425 case 0x660fd0: /* addsubpd */
6426 case 0xf20fd0: /* addsubps */
6427 case 0x660fd1: /* psrlw */
6428 case 0x660fd2: /* psrld */
6429 case 0x660fd3: /* psrlq */
6430 case 0x660fd4: /* paddq */
6431 case 0x660fd5: /* pmullw */
6432 case 0xf30fd6: /* movq2dq */
6433 case 0x660fd8: /* psubusb */
6434 case 0x660fd9: /* psubusw */
6435 case 0x660fda: /* pminub */
6436 case 0x660fdb: /* pand */
6437 case 0x660fdc: /* paddusb */
6438 case 0x660fdd: /* paddusw */
6439 case 0x660fde: /* pmaxub */
6440 case 0x660fdf: /* pandn */
6441 case 0x660fe0: /* pavgb */
6442 case 0x660fe1: /* psraw */
6443 case 0x660fe2: /* psrad */
6444 case 0x660fe3: /* pavgw */
6445 case 0x660fe4: /* pmulhuw */
6446 case 0x660fe5: /* pmulhw */
6447 case 0x660fe6: /* cvttpd2dq */
6448 case 0xf20fe6: /* cvtpd2dq */
6449 case 0xf30fe6: /* cvtdq2pd */
6450 case 0x660fe8: /* psubsb */
6451 case 0x660fe9: /* psubsw */
6452 case 0x660fea: /* pminsw */
6453 case 0x660feb: /* por */
6454 case 0x660fec: /* paddsb */
6455 case 0x660fed: /* paddsw */
6456 case 0x660fee: /* pmaxsw */
6457 case 0x660fef: /* pxor */
6458 case 0xf20ff0: /* lddqu */
6459 case 0x660ff1: /* psllw */
6460 case 0x660ff2: /* pslld */
6461 case 0x660ff3: /* psllq */
6462 case 0x660ff4: /* pmuludq */
6463 case 0x660ff5: /* pmaddwd */
6464 case 0x660ff6: /* psadbw */
6465 case 0x660ff8: /* psubb */
6466 case 0x660ff9: /* psubw */
6467 case 0x660ffa: /* psubd */
6468 case 0x660ffb: /* psubq */
6469 case 0x660ffc: /* paddb */
6470 case 0x660ffd: /* paddw */
6471 case 0x660ffe: /* paddd */
6472 if (i386_record_modrm (&ir))
6475 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
6477 record_arch_list_add_reg (ir.regcache,
6478 I387_XMM0_REGNUM (tdep) + ir.reg);
6479 if ((opcode & 0xfffffffc) == 0x660f3a60)
6480 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6483 case 0x0f11: /* movups */
6484 case 0x660f11: /* movupd */
6485 case 0xf30f11: /* movss */
6486 case 0xf20f11: /* movsd */
6487 case 0x0f13: /* movlps */
6488 case 0x660f13: /* movlpd */
6489 case 0x0f17: /* movhps */
6490 case 0x660f17: /* movhpd */
6491 case 0x0f29: /* movaps */
6492 case 0x660f29: /* movapd */
6493 case 0x660f3a14: /* pextrb */
6494 case 0x660f3a15: /* pextrw */
6495 case 0x660f3a16: /* pextrd pextrq */
6496 case 0x660f3a17: /* extractps */
6497 case 0x660f7f: /* movdqa */
6498 case 0xf30f7f: /* movdqu */
6499 if (i386_record_modrm (&ir))
6503 if (opcode == 0x0f13 || opcode == 0x660f13
6504 || opcode == 0x0f17 || opcode == 0x660f17)
6507 if (!i386_xmm_regnum_p (gdbarch,
6508 I387_XMM0_REGNUM (tdep) + ir.rm))
6510 record_arch_list_add_reg (ir.regcache,
6511 I387_XMM0_REGNUM (tdep) + ir.rm);
6533 if (i386_record_lea_modrm (&ir))
6538 case 0x0f2b: /* movntps */
6539 case 0x660f2b: /* movntpd */
6540 case 0x0fe7: /* movntq */
6541 case 0x660fe7: /* movntdq */
6544 if (opcode == 0x0fe7)
6548 if (i386_record_lea_modrm (&ir))
6552 case 0xf30f2c: /* cvttss2si */
6553 case 0xf20f2c: /* cvttsd2si */
6554 case 0xf30f2d: /* cvtss2si */
6555 case 0xf20f2d: /* cvtsd2si */
6556 case 0xf20f38f0: /* crc32 */
6557 case 0xf20f38f1: /* crc32 */
6558 case 0x0f50: /* movmskps */
6559 case 0x660f50: /* movmskpd */
6560 case 0x0fc5: /* pextrw */
6561 case 0x660fc5: /* pextrw */
6562 case 0x0fd7: /* pmovmskb */
6563 case 0x660fd7: /* pmovmskb */
6564 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6567 case 0x0f3800: /* pshufb */
6568 case 0x0f3801: /* phaddw */
6569 case 0x0f3802: /* phaddd */
6570 case 0x0f3803: /* phaddsw */
6571 case 0x0f3804: /* pmaddubsw */
6572 case 0x0f3805: /* phsubw */
6573 case 0x0f3806: /* phsubd */
6574 case 0x0f3807: /* phsubsw */
6575 case 0x0f3808: /* psignb */
6576 case 0x0f3809: /* psignw */
6577 case 0x0f380a: /* psignd */
6578 case 0x0f380b: /* pmulhrsw */
6579 case 0x0f381c: /* pabsb */
6580 case 0x0f381d: /* pabsw */
6581 case 0x0f381e: /* pabsd */
6582 case 0x0f382b: /* packusdw */
6583 case 0x0f3830: /* pmovzxbw */
6584 case 0x0f3831: /* pmovzxbd */
6585 case 0x0f3832: /* pmovzxbq */
6586 case 0x0f3833: /* pmovzxwd */
6587 case 0x0f3834: /* pmovzxwq */
6588 case 0x0f3835: /* pmovzxdq */
6589 case 0x0f3837: /* pcmpgtq */
6590 case 0x0f3838: /* pminsb */
6591 case 0x0f3839: /* pminsd */
6592 case 0x0f383a: /* pminuw */
6593 case 0x0f383b: /* pminud */
6594 case 0x0f383c: /* pmaxsb */
6595 case 0x0f383d: /* pmaxsd */
6596 case 0x0f383e: /* pmaxuw */
6597 case 0x0f383f: /* pmaxud */
6598 case 0x0f3840: /* pmulld */
6599 case 0x0f3841: /* phminposuw */
6600 case 0x0f3a0f: /* palignr */
6601 case 0x0f60: /* punpcklbw */
6602 case 0x0f61: /* punpcklwd */
6603 case 0x0f62: /* punpckldq */
6604 case 0x0f63: /* packsswb */
6605 case 0x0f64: /* pcmpgtb */
6606 case 0x0f65: /* pcmpgtw */
6607 case 0x0f66: /* pcmpgtd */
6608 case 0x0f67: /* packuswb */
6609 case 0x0f68: /* punpckhbw */
6610 case 0x0f69: /* punpckhwd */
6611 case 0x0f6a: /* punpckhdq */
6612 case 0x0f6b: /* packssdw */
6613 case 0x0f6e: /* movd */
6614 case 0x0f6f: /* movq */
6615 case 0x0f70: /* pshufw */
6616 case 0x0f74: /* pcmpeqb */
6617 case 0x0f75: /* pcmpeqw */
6618 case 0x0f76: /* pcmpeqd */
6619 case 0x0fc4: /* pinsrw */
6620 case 0x0fd1: /* psrlw */
6621 case 0x0fd2: /* psrld */
6622 case 0x0fd3: /* psrlq */
6623 case 0x0fd4: /* paddq */
6624 case 0x0fd5: /* pmullw */
6625 case 0xf20fd6: /* movdq2q */
6626 case 0x0fd8: /* psubusb */
6627 case 0x0fd9: /* psubusw */
6628 case 0x0fda: /* pminub */
6629 case 0x0fdb: /* pand */
6630 case 0x0fdc: /* paddusb */
6631 case 0x0fdd: /* paddusw */
6632 case 0x0fde: /* pmaxub */
6633 case 0x0fdf: /* pandn */
6634 case 0x0fe0: /* pavgb */
6635 case 0x0fe1: /* psraw */
6636 case 0x0fe2: /* psrad */
6637 case 0x0fe3: /* pavgw */
6638 case 0x0fe4: /* pmulhuw */
6639 case 0x0fe5: /* pmulhw */
6640 case 0x0fe8: /* psubsb */
6641 case 0x0fe9: /* psubsw */
6642 case 0x0fea: /* pminsw */
6643 case 0x0feb: /* por */
6644 case 0x0fec: /* paddsb */
6645 case 0x0fed: /* paddsw */
6646 case 0x0fee: /* pmaxsw */
6647 case 0x0fef: /* pxor */
6648 case 0x0ff1: /* psllw */
6649 case 0x0ff2: /* pslld */
6650 case 0x0ff3: /* psllq */
6651 case 0x0ff4: /* pmuludq */
6652 case 0x0ff5: /* pmaddwd */
6653 case 0x0ff6: /* psadbw */
6654 case 0x0ff8: /* psubb */
6655 case 0x0ff9: /* psubw */
6656 case 0x0ffa: /* psubd */
6657 case 0x0ffb: /* psubq */
6658 case 0x0ffc: /* paddb */
6659 case 0x0ffd: /* paddw */
6660 case 0x0ffe: /* paddd */
6661 if (i386_record_modrm (&ir))
6663 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
6665 record_arch_list_add_reg (ir.regcache,
6666 I387_MM0_REGNUM (tdep) + ir.reg);
6669 case 0x0f71: /* psllw */
6670 case 0x0f72: /* pslld */
6671 case 0x0f73: /* psllq */
6672 if (i386_record_modrm (&ir))
6674 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
6676 record_arch_list_add_reg (ir.regcache,
6677 I387_MM0_REGNUM (tdep) + ir.rm);
6680 case 0x660f71: /* psllw */
6681 case 0x660f72: /* pslld */
6682 case 0x660f73: /* psllq */
6683 if (i386_record_modrm (&ir))
6686 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
6688 record_arch_list_add_reg (ir.regcache,
6689 I387_XMM0_REGNUM (tdep) + ir.rm);
6692 case 0x0f7e: /* movd */
6693 case 0x660f7e: /* movd */
6694 if (i386_record_modrm (&ir))
6697 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6704 if (i386_record_lea_modrm (&ir))
6709 case 0x0f7f: /* movq */
6710 if (i386_record_modrm (&ir))
6714 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
6716 record_arch_list_add_reg (ir.regcache,
6717 I387_MM0_REGNUM (tdep) + ir.rm);
6722 if (i386_record_lea_modrm (&ir))
6727 case 0xf30fb8: /* popcnt */
6728 if (i386_record_modrm (&ir))
6730 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
6731 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6734 case 0x660fd6: /* movq */
6735 if (i386_record_modrm (&ir))
6740 if (!i386_xmm_regnum_p (gdbarch,
6741 I387_XMM0_REGNUM (tdep) + ir.rm))
6743 record_arch_list_add_reg (ir.regcache,
6744 I387_XMM0_REGNUM (tdep) + ir.rm);
6749 if (i386_record_lea_modrm (&ir))
6754 case 0x660f3817: /* ptest */
6755 case 0x0f2e: /* ucomiss */
6756 case 0x660f2e: /* ucomisd */
6757 case 0x0f2f: /* comiss */
6758 case 0x660f2f: /* comisd */
6759 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6762 case 0x0ff7: /* maskmovq */
6763 regcache_raw_read_unsigned (ir.regcache,
6764 ir.regmap[X86_RECORD_REDI_REGNUM],
6766 if (record_arch_list_add_mem (addr, 64))
6770 case 0x660ff7: /* maskmovdqu */
6771 regcache_raw_read_unsigned (ir.regcache,
6772 ir.regmap[X86_RECORD_REDI_REGNUM],
6774 if (record_arch_list_add_mem (addr, 128))
6789 /* In the future, maybe still need to deal with need_dasm. */
6790 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
6791 if (record_arch_list_add_end ())
6797 printf_unfiltered (_("Process record does not support instruction 0x%02x "
6798 "at address %s.\n"),
6799 (unsigned int) (opcode),
6800 paddress (gdbarch, ir.orig_addr));
6804 static const int i386_record_regmap[] =
6806 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
6807 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
6808 0, 0, 0, 0, 0, 0, 0, 0,
6809 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
6810 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
6813 /* Check that the given address appears suitable for a fast
6814 tracepoint, which on x86 means that we need an instruction of at
6815 least 5 bytes, so that we can overwrite it with a 4-byte-offset
6816 jump and not have to worry about program jumps to an address in the
6817 middle of the tracepoint jump. Returns 1 if OK, and writes a size
6818 of instruction to replace, and 0 if not, plus an explanatory
6822 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch,
6823 CORE_ADDR addr, int *isize, char **msg)
6826 static struct ui_file *gdb_null = NULL;
6828 /* This is based on the target agent using a 4-byte relative jump.
6829 Alternate future possibilities include 8-byte offset for x86-84,
6830 or 3-byte jumps if the program has trampoline space close by. */
6833 /* Dummy file descriptor for the disassembler. */
6835 gdb_null = ui_file_new ();
6837 /* Check for fit. */
6838 len = gdb_print_insn (gdbarch, addr, gdb_null, NULL);
6841 /* Return a bit of target-specific detail to add to the caller's
6842 generic failure message. */
6844 *msg = xstrprintf (_("; instruction is only %d bytes long, "
6845 "need at least %d bytes for the jump"),
6858 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
6859 struct tdesc_arch_data *tdesc_data)
6861 const struct target_desc *tdesc = tdep->tdesc;
6862 const struct tdesc_feature *feature_core;
6863 const struct tdesc_feature *feature_sse, *feature_avx;
6864 int i, num_regs, valid_p;
6866 if (! tdesc_has_registers (tdesc))
6869 /* Get core registers. */
6870 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
6871 if (feature_core == NULL)
6874 /* Get SSE registers. */
6875 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
6877 /* Try AVX registers. */
6878 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
6882 /* The XCR0 bits. */
6885 /* AVX register description requires SSE register description. */
6889 tdep->xcr0 = I386_XSTATE_AVX_MASK;
6891 /* It may have been set by OSABI initialization function. */
6892 if (tdep->num_ymm_regs == 0)
6894 tdep->ymmh_register_names = i386_ymmh_names;
6895 tdep->num_ymm_regs = 8;
6896 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
6899 for (i = 0; i < tdep->num_ymm_regs; i++)
6900 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
6901 tdep->ymm0h_regnum + i,
6902 tdep->ymmh_register_names[i]);
6904 else if (feature_sse)
6905 tdep->xcr0 = I386_XSTATE_SSE_MASK;
6908 tdep->xcr0 = I386_XSTATE_X87_MASK;
6909 tdep->num_xmm_regs = 0;
6912 num_regs = tdep->num_core_regs;
6913 for (i = 0; i < num_regs; i++)
6914 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
6915 tdep->register_names[i]);
6919 /* Need to include %mxcsr, so add one. */
6920 num_regs += tdep->num_xmm_regs + 1;
6921 for (; i < num_regs; i++)
6922 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
6923 tdep->register_names[i]);
6930 static struct gdbarch *
6931 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
6933 struct gdbarch_tdep *tdep;
6934 struct gdbarch *gdbarch;
6935 struct tdesc_arch_data *tdesc_data;
6936 const struct target_desc *tdesc;
6940 /* If there is already a candidate, use it. */
6941 arches = gdbarch_list_lookup_by_info (arches, &info);
6943 return arches->gdbarch;
6945 /* Allocate space for the new architecture. */
6946 tdep = XCALLOC (1, struct gdbarch_tdep);
6947 gdbarch = gdbarch_alloc (&info, tdep);
6949 /* General-purpose registers. */
6950 tdep->gregset = NULL;
6951 tdep->gregset_reg_offset = NULL;
6952 tdep->gregset_num_regs = I386_NUM_GREGS;
6953 tdep->sizeof_gregset = 0;
6955 /* Floating-point registers. */
6956 tdep->fpregset = NULL;
6957 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
6959 tdep->xstateregset = NULL;
6961 /* The default settings include the FPU registers, the MMX registers
6962 and the SSE registers. This can be overridden for a specific ABI
6963 by adjusting the members `st0_regnum', `mm0_regnum' and
6964 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
6965 will show up in the output of "info all-registers". */
6967 tdep->st0_regnum = I386_ST0_REGNUM;
6969 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
6970 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
6972 tdep->jb_pc_offset = -1;
6973 tdep->struct_return = pcc_struct_return;
6974 tdep->sigtramp_start = 0;
6975 tdep->sigtramp_end = 0;
6976 tdep->sigtramp_p = i386_sigtramp_p;
6977 tdep->sigcontext_addr = NULL;
6978 tdep->sc_reg_offset = NULL;
6979 tdep->sc_pc_offset = -1;
6980 tdep->sc_sp_offset = -1;
6982 tdep->xsave_xcr0_offset = -1;
6984 tdep->record_regmap = i386_record_regmap;
6986 /* The format used for `long double' on almost all i386 targets is
6987 the i387 extended floating-point format. In fact, of all targets
6988 in the GCC 2.95 tree, only OSF/1 does it different, and insists
6989 on having a `long double' that's not `long' at all. */
6990 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
6992 /* Although the i387 extended floating-point has only 80 significant
6993 bits, a `long double' actually takes up 96, probably to enforce
6995 set_gdbarch_long_double_bit (gdbarch, 96);
6997 /* Register numbers of various important registers. */
6998 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
6999 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
7000 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
7001 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
7003 /* NOTE: kettenis/20040418: GCC does have two possible register
7004 numbering schemes on the i386: dbx and SVR4. These schemes
7005 differ in how they number %ebp, %esp, %eflags, and the
7006 floating-point registers, and are implemented by the arrays
7007 dbx_register_map[] and svr4_dbx_register_map in
7008 gcc/config/i386.c. GCC also defines a third numbering scheme in
7009 gcc/config/i386.c, which it designates as the "default" register
7010 map used in 64bit mode. This last register numbering scheme is
7011 implemented in dbx64_register_map, and is used for AMD64; see
7014 Currently, each GCC i386 target always uses the same register
7015 numbering scheme across all its supported debugging formats
7016 i.e. SDB (COFF), stabs and DWARF 2. This is because
7017 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7018 DBX_REGISTER_NUMBER macro which is defined by each target's
7019 respective config header in a manner independent of the requested
7020 output debugging format.
7022 This does not match the arrangement below, which presumes that
7023 the SDB and stabs numbering schemes differ from the DWARF and
7024 DWARF 2 ones. The reason for this arrangement is that it is
7025 likely to get the numbering scheme for the target's
7026 default/native debug format right. For targets where GCC is the
7027 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7028 targets where the native toolchain uses a different numbering
7029 scheme for a particular debug format (stabs-in-ELF on Solaris)
7030 the defaults below will have to be overridden, like
7031 i386_elf_init_abi() does. */
7033 /* Use the dbx register numbering scheme for stabs and COFF. */
7034 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
7035 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
7037 /* Use the SVR4 register numbering scheme for DWARF 2. */
7038 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
7040 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7041 be in use on any of the supported i386 targets. */
7043 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
7045 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
7047 /* Call dummy code. */
7048 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
7050 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
7051 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
7052 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
7054 set_gdbarch_return_value (gdbarch, i386_return_value);
7056 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
7058 /* Stack grows downward. */
7059 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
7061 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc);
7062 set_gdbarch_decr_pc_after_break (gdbarch, 1);
7063 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
7065 set_gdbarch_frame_args_skip (gdbarch, 8);
7067 set_gdbarch_print_insn (gdbarch, i386_print_insn);
7069 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
7071 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
7073 /* Add the i386 register groups. */
7074 i386_add_reggroups (gdbarch);
7075 tdep->register_reggroup_p = i386_register_reggroup_p;
7077 /* Helper for function argument information. */
7078 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
7080 /* Hook the function epilogue frame unwinder. This unwinder is
7081 appended to the list first, so that it supercedes the Dwarf
7082 unwinder in function epilogues (where the Dwarf unwinder
7083 currently fails). */
7084 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
7086 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7087 to the list before the prologue-based unwinders, so that Dwarf
7088 CFI info will be used if it is available. */
7089 dwarf2_append_unwinders (gdbarch);
7091 frame_base_set_default (gdbarch, &i386_frame_base);
7093 /* Pseudo registers may be changed by amd64_init_abi. */
7094 set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read);
7095 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
7097 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
7098 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
7100 /* Override the normal target description method to make the AVX
7101 upper halves anonymous. */
7102 set_gdbarch_register_name (gdbarch, i386_register_name);
7104 /* Even though the default ABI only includes general-purpose registers,
7105 floating-point registers and the SSE registers, we have to leave a
7106 gap for the upper AVX registers. */
7107 set_gdbarch_num_regs (gdbarch, I386_AVX_NUM_REGS);
7109 /* Get the x86 target description from INFO. */
7110 tdesc = info.target_desc;
7111 if (! tdesc_has_registers (tdesc))
7113 tdep->tdesc = tdesc;
7115 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
7116 tdep->register_names = i386_register_names;
7118 /* No upper YMM registers. */
7119 tdep->ymmh_register_names = NULL;
7120 tdep->ymm0h_regnum = -1;
7122 tdep->num_byte_regs = 8;
7123 tdep->num_word_regs = 8;
7124 tdep->num_dword_regs = 0;
7125 tdep->num_mmx_regs = 8;
7126 tdep->num_ymm_regs = 0;
7128 tdesc_data = tdesc_data_alloc ();
7130 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
7132 /* Hook in ABI-specific overrides, if they have been registered. */
7133 info.tdep_info = (void *) tdesc_data;
7134 gdbarch_init_osabi (info, gdbarch);
7136 if (!i386_validate_tdesc_p (tdep, tdesc_data))
7138 tdesc_data_cleanup (tdesc_data);
7140 gdbarch_free (gdbarch);
7144 /* Wire in pseudo registers. Number of pseudo registers may be
7146 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
7147 + tdep->num_word_regs
7148 + tdep->num_dword_regs
7149 + tdep->num_mmx_regs
7150 + tdep->num_ymm_regs));
7152 /* Target description may be changed. */
7153 tdesc = tdep->tdesc;
7155 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
7157 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7158 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
7160 /* Make %al the first pseudo-register. */
7161 tdep->al_regnum = gdbarch_num_regs (gdbarch);
7162 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
7164 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
7165 if (tdep->num_dword_regs)
7167 /* Support dword pseudo-register if it hasn't been disabled. */
7168 tdep->eax_regnum = ymm0_regnum;
7169 ymm0_regnum += tdep->num_dword_regs;
7172 tdep->eax_regnum = -1;
7174 mm0_regnum = ymm0_regnum;
7175 if (tdep->num_ymm_regs)
7177 /* Support YMM pseudo-register if it is available. */
7178 tdep->ymm0_regnum = ymm0_regnum;
7179 mm0_regnum += tdep->num_ymm_regs;
7182 tdep->ymm0_regnum = -1;
7184 if (tdep->num_mmx_regs != 0)
7186 /* Support MMX pseudo-register if MMX hasn't been disabled. */
7187 tdep->mm0_regnum = mm0_regnum;
7190 tdep->mm0_regnum = -1;
7192 /* Hook in the legacy prologue-based unwinders last (fallback). */
7193 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
7194 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
7196 /* If we have a register mapping, enable the generic core file
7197 support, unless it has already been enabled. */
7198 if (tdep->gregset_reg_offset
7199 && !gdbarch_regset_from_core_section_p (gdbarch))
7200 set_gdbarch_regset_from_core_section (gdbarch,
7201 i386_regset_from_core_section);
7203 set_gdbarch_skip_permanent_breakpoint (gdbarch,
7204 i386_skip_permanent_breakpoint);
7206 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
7207 i386_fast_tracepoint_valid_at);
7212 static enum gdb_osabi
7213 i386_coff_osabi_sniffer (bfd *abfd)
7215 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
7216 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
7217 return GDB_OSABI_GO32;
7219 return GDB_OSABI_UNKNOWN;
7223 /* Provide a prototype to silence -Wmissing-prototypes. */
7224 void _initialize_i386_tdep (void);
7227 _initialize_i386_tdep (void)
7229 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
7231 /* Add the variable that controls the disassembly flavor. */
7232 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
7233 &disassembly_flavor, _("\
7234 Set the disassembly flavor."), _("\
7235 Show the disassembly flavor."), _("\
7236 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7238 NULL, /* FIXME: i18n: */
7239 &setlist, &showlist);
7241 /* Add the variable that controls the convention for returning
7243 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
7244 &struct_convention, _("\
7245 Set the convention for returning small structs."), _("\
7246 Show the convention for returning small structs."), _("\
7247 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7250 NULL, /* FIXME: i18n: */
7251 &setlist, &showlist);
7253 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
7254 i386_coff_osabi_sniffer);
7256 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
7257 i386_svr4_init_abi);
7258 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
7259 i386_go32_init_abi);
7261 /* Initialize the i386-specific register groups. */
7262 i386_init_reggroups ();
7264 /* Initialize the standard target descriptions. */
7265 initialize_tdesc_i386 ();
7266 initialize_tdesc_i386_mmx ();
7267 initialize_tdesc_i386_avx ();
7269 /* Tell remote stub that we support XML target description. */
7270 register_remote_support_xml ("i386");