1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
38 #include "reggroups.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "x86-xstate.h"
52 #include "record-full.h"
53 #include "features/i386/i386.c"
54 #include "features/i386/i386-avx.c"
55 #include "features/i386/i386-mpx.c"
56 #include "features/i386/i386-avx-mpx.c"
57 #include "features/i386/i386-avx-avx512.c"
58 #include "features/i386/i386-avx-mpx-avx512-pku.c"
59 #include "features/i386/i386-mmx.c"
64 #include "stap-probe.h"
65 #include "user-regs.h"
66 #include "cli/cli-utils.h"
67 #include "expression.h"
68 #include "parser-defs.h"
74 static const char *i386_register_names[] =
76 "eax", "ecx", "edx", "ebx",
77 "esp", "ebp", "esi", "edi",
78 "eip", "eflags", "cs", "ss",
79 "ds", "es", "fs", "gs",
80 "st0", "st1", "st2", "st3",
81 "st4", "st5", "st6", "st7",
82 "fctrl", "fstat", "ftag", "fiseg",
83 "fioff", "foseg", "fooff", "fop",
84 "xmm0", "xmm1", "xmm2", "xmm3",
85 "xmm4", "xmm5", "xmm6", "xmm7",
89 static const char *i386_zmm_names[] =
91 "zmm0", "zmm1", "zmm2", "zmm3",
92 "zmm4", "zmm5", "zmm6", "zmm7"
95 static const char *i386_zmmh_names[] =
97 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
98 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
101 static const char *i386_k_names[] =
103 "k0", "k1", "k2", "k3",
104 "k4", "k5", "k6", "k7"
107 static const char *i386_ymm_names[] =
109 "ymm0", "ymm1", "ymm2", "ymm3",
110 "ymm4", "ymm5", "ymm6", "ymm7",
113 static const char *i386_ymmh_names[] =
115 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
116 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
119 static const char *i386_mpx_names[] =
121 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
124 static const char* i386_pkeys_names[] =
129 /* Register names for MPX pseudo-registers. */
131 static const char *i386_bnd_names[] =
133 "bnd0", "bnd1", "bnd2", "bnd3"
136 /* Register names for MMX pseudo-registers. */
138 static const char *i386_mmx_names[] =
140 "mm0", "mm1", "mm2", "mm3",
141 "mm4", "mm5", "mm6", "mm7"
144 /* Register names for byte pseudo-registers. */
146 static const char *i386_byte_names[] =
148 "al", "cl", "dl", "bl",
149 "ah", "ch", "dh", "bh"
152 /* Register names for word pseudo-registers. */
154 static const char *i386_word_names[] =
156 "ax", "cx", "dx", "bx",
160 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
161 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
162 we have 16 upper ZMM regs that have to be handled differently. */
164 const int num_lower_zmm_regs = 16;
169 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
171 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
172 int mm0_regnum = tdep->mm0_regnum;
177 regnum -= mm0_regnum;
178 return regnum >= 0 && regnum < tdep->num_mmx_regs;
184 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
186 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
188 regnum -= tdep->al_regnum;
189 return regnum >= 0 && regnum < tdep->num_byte_regs;
195 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
197 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
199 regnum -= tdep->ax_regnum;
200 return regnum >= 0 && regnum < tdep->num_word_regs;
203 /* Dword register? */
206 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
208 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
209 int eax_regnum = tdep->eax_regnum;
214 regnum -= eax_regnum;
215 return regnum >= 0 && regnum < tdep->num_dword_regs;
218 /* AVX512 register? */
221 i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum)
223 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
224 int zmm0h_regnum = tdep->zmm0h_regnum;
226 if (zmm0h_regnum < 0)
229 regnum -= zmm0h_regnum;
230 return regnum >= 0 && regnum < tdep->num_zmm_regs;
234 i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum)
236 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
237 int zmm0_regnum = tdep->zmm0_regnum;
242 regnum -= zmm0_regnum;
243 return regnum >= 0 && regnum < tdep->num_zmm_regs;
247 i386_k_regnum_p (struct gdbarch *gdbarch, int regnum)
249 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
250 int k0_regnum = tdep->k0_regnum;
256 return regnum >= 0 && regnum < I387_NUM_K_REGS;
260 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
262 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
263 int ymm0h_regnum = tdep->ymm0h_regnum;
265 if (ymm0h_regnum < 0)
268 regnum -= ymm0h_regnum;
269 return regnum >= 0 && regnum < tdep->num_ymm_regs;
275 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
277 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
278 int ymm0_regnum = tdep->ymm0_regnum;
283 regnum -= ymm0_regnum;
284 return regnum >= 0 && regnum < tdep->num_ymm_regs;
288 i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
290 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
291 int ymm16h_regnum = tdep->ymm16h_regnum;
293 if (ymm16h_regnum < 0)
296 regnum -= ymm16h_regnum;
297 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
301 i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
303 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
304 int ymm16_regnum = tdep->ymm16_regnum;
306 if (ymm16_regnum < 0)
309 regnum -= ymm16_regnum;
310 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
316 i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum)
318 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
319 int bnd0_regnum = tdep->bnd0_regnum;
324 regnum -= bnd0_regnum;
325 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
331 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
333 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
334 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
336 if (num_xmm_regs == 0)
339 regnum -= I387_XMM0_REGNUM (tdep);
340 return regnum >= 0 && regnum < num_xmm_regs;
343 /* XMM_512 register? */
346 i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
348 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
349 int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep);
351 if (num_xmm_avx512_regs == 0)
354 regnum -= I387_XMM16_REGNUM (tdep);
355 return regnum >= 0 && regnum < num_xmm_avx512_regs;
359 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
361 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
363 if (I387_NUM_XMM_REGS (tdep) == 0)
366 return (regnum == I387_MXCSR_REGNUM (tdep));
372 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
374 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
376 if (I387_ST0_REGNUM (tdep) < 0)
379 return (I387_ST0_REGNUM (tdep) <= regnum
380 && regnum < I387_FCTRL_REGNUM (tdep));
384 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
386 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
388 if (I387_ST0_REGNUM (tdep) < 0)
391 return (I387_FCTRL_REGNUM (tdep) <= regnum
392 && regnum < I387_XMM0_REGNUM (tdep));
395 /* BNDr (raw) register? */
398 i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum)
400 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
402 if (I387_BND0R_REGNUM (tdep) < 0)
405 regnum -= tdep->bnd0r_regnum;
406 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
409 /* BND control register? */
412 i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum)
414 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
416 if (I387_BNDCFGU_REGNUM (tdep) < 0)
419 regnum -= I387_BNDCFGU_REGNUM (tdep);
420 return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS;
426 i386_pkru_regnum_p (struct gdbarch *gdbarch, int regnum)
428 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
429 int pkru_regnum = tdep->pkru_regnum;
434 regnum -= pkru_regnum;
435 return regnum >= 0 && regnum < I387_NUM_PKEYS_REGS;
438 /* Return the name of register REGNUM, or the empty string if it is
439 an anonymous register. */
442 i386_register_name (struct gdbarch *gdbarch, int regnum)
444 /* Hide the upper YMM registers. */
445 if (i386_ymmh_regnum_p (gdbarch, regnum))
448 /* Hide the upper YMM16-31 registers. */
449 if (i386_ymmh_avx512_regnum_p (gdbarch, regnum))
452 /* Hide the upper ZMM registers. */
453 if (i386_zmmh_regnum_p (gdbarch, regnum))
456 return tdesc_register_name (gdbarch, regnum);
459 /* Return the name of register REGNUM. */
462 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
464 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
465 if (i386_bnd_regnum_p (gdbarch, regnum))
466 return i386_bnd_names[regnum - tdep->bnd0_regnum];
467 if (i386_mmx_regnum_p (gdbarch, regnum))
468 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
469 else if (i386_ymm_regnum_p (gdbarch, regnum))
470 return i386_ymm_names[regnum - tdep->ymm0_regnum];
471 else if (i386_zmm_regnum_p (gdbarch, regnum))
472 return i386_zmm_names[regnum - tdep->zmm0_regnum];
473 else if (i386_byte_regnum_p (gdbarch, regnum))
474 return i386_byte_names[regnum - tdep->al_regnum];
475 else if (i386_word_regnum_p (gdbarch, regnum))
476 return i386_word_names[regnum - tdep->ax_regnum];
478 internal_error (__FILE__, __LINE__, _("invalid regnum"));
481 /* Convert a dbx register number REG to the appropriate register
482 number used by GDB. */
485 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
487 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
489 /* This implements what GCC calls the "default" register map
490 (dbx_register_map[]). */
492 if (reg >= 0 && reg <= 7)
494 /* General-purpose registers. The debug info calls %ebp
495 register 4, and %esp register 5. */
502 else if (reg >= 12 && reg <= 19)
504 /* Floating-point registers. */
505 return reg - 12 + I387_ST0_REGNUM (tdep);
507 else if (reg >= 21 && reg <= 28)
510 int ymm0_regnum = tdep->ymm0_regnum;
513 && i386_xmm_regnum_p (gdbarch, reg))
514 return reg - 21 + ymm0_regnum;
516 return reg - 21 + I387_XMM0_REGNUM (tdep);
518 else if (reg >= 29 && reg <= 36)
521 return reg - 29 + I387_MM0_REGNUM (tdep);
524 /* This will hopefully provoke a warning. */
525 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
528 /* Convert SVR4 DWARF register number REG to the appropriate register number
532 i386_svr4_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
534 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
536 /* This implements the GCC register map that tries to be compatible
537 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
539 /* The SVR4 register numbering includes %eip and %eflags, and
540 numbers the floating point registers differently. */
541 if (reg >= 0 && reg <= 9)
543 /* General-purpose registers. */
546 else if (reg >= 11 && reg <= 18)
548 /* Floating-point registers. */
549 return reg - 11 + I387_ST0_REGNUM (tdep);
551 else if (reg >= 21 && reg <= 36)
553 /* The SSE and MMX registers have the same numbers as with dbx. */
554 return i386_dbx_reg_to_regnum (gdbarch, reg);
559 case 37: return I387_FCTRL_REGNUM (tdep);
560 case 38: return I387_FSTAT_REGNUM (tdep);
561 case 39: return I387_MXCSR_REGNUM (tdep);
562 case 40: return I386_ES_REGNUM;
563 case 41: return I386_CS_REGNUM;
564 case 42: return I386_SS_REGNUM;
565 case 43: return I386_DS_REGNUM;
566 case 44: return I386_FS_REGNUM;
567 case 45: return I386_GS_REGNUM;
573 /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return
574 num_regs + num_pseudo_regs for other debug formats. */
577 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
579 int regnum = i386_svr4_dwarf_reg_to_regnum (gdbarch, reg);
582 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
588 /* This is the variable that is set with "set disassembly-flavor", and
589 its legitimate values. */
590 static const char att_flavor[] = "att";
591 static const char intel_flavor[] = "intel";
592 static const char *const valid_flavors[] =
598 static const char *disassembly_flavor = att_flavor;
601 /* Use the program counter to determine the contents and size of a
602 breakpoint instruction. Return a pointer to a string of bytes that
603 encode a breakpoint instruction, store the length of the string in
604 *LEN and optionally adjust *PC to point to the correct memory
605 location for inserting the breakpoint.
607 On the i386 we have a single breakpoint that fits in a single byte
608 and can be inserted anywhere.
610 This function is 64-bit safe. */
612 constexpr gdb_byte i386_break_insn[] = { 0xcc }; /* int 3 */
614 typedef BP_MANIPULATION (i386_break_insn) i386_breakpoint;
617 /* Displaced instruction handling. */
619 /* Skip the legacy instruction prefixes in INSN.
620 Not all prefixes are valid for any particular insn
621 but we needn't care, the insn will fault if it's invalid.
622 The result is a pointer to the first opcode byte,
623 or NULL if we run off the end of the buffer. */
626 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
628 gdb_byte *end = insn + max_len;
634 case DATA_PREFIX_OPCODE:
635 case ADDR_PREFIX_OPCODE:
636 case CS_PREFIX_OPCODE:
637 case DS_PREFIX_OPCODE:
638 case ES_PREFIX_OPCODE:
639 case FS_PREFIX_OPCODE:
640 case GS_PREFIX_OPCODE:
641 case SS_PREFIX_OPCODE:
642 case LOCK_PREFIX_OPCODE:
643 case REPE_PREFIX_OPCODE:
644 case REPNE_PREFIX_OPCODE:
656 i386_absolute_jmp_p (const gdb_byte *insn)
658 /* jmp far (absolute address in operand). */
664 /* jump near, absolute indirect (/4). */
665 if ((insn[1] & 0x38) == 0x20)
668 /* jump far, absolute indirect (/5). */
669 if ((insn[1] & 0x38) == 0x28)
676 /* Return non-zero if INSN is a jump, zero otherwise. */
679 i386_jmp_p (const gdb_byte *insn)
681 /* jump short, relative. */
685 /* jump near, relative. */
689 return i386_absolute_jmp_p (insn);
693 i386_absolute_call_p (const gdb_byte *insn)
695 /* call far, absolute. */
701 /* Call near, absolute indirect (/2). */
702 if ((insn[1] & 0x38) == 0x10)
705 /* Call far, absolute indirect (/3). */
706 if ((insn[1] & 0x38) == 0x18)
714 i386_ret_p (const gdb_byte *insn)
718 case 0xc2: /* ret near, pop N bytes. */
719 case 0xc3: /* ret near */
720 case 0xca: /* ret far, pop N bytes. */
721 case 0xcb: /* ret far */
722 case 0xcf: /* iret */
731 i386_call_p (const gdb_byte *insn)
733 if (i386_absolute_call_p (insn))
736 /* call near, relative. */
743 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
744 length in bytes. Otherwise, return zero. */
747 i386_syscall_p (const gdb_byte *insn, int *lengthp)
749 /* Is it 'int $0x80'? */
750 if ((insn[0] == 0xcd && insn[1] == 0x80)
751 /* Or is it 'sysenter'? */
752 || (insn[0] == 0x0f && insn[1] == 0x34)
753 /* Or is it 'syscall'? */
754 || (insn[0] == 0x0f && insn[1] == 0x05))
763 /* The gdbarch insn_is_call method. */
766 i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
768 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
770 read_code (addr, buf, I386_MAX_INSN_LEN);
771 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
773 return i386_call_p (insn);
776 /* The gdbarch insn_is_ret method. */
779 i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
781 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
783 read_code (addr, buf, I386_MAX_INSN_LEN);
784 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
786 return i386_ret_p (insn);
789 /* The gdbarch insn_is_jump method. */
792 i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
794 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
796 read_code (addr, buf, I386_MAX_INSN_LEN);
797 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
799 return i386_jmp_p (insn);
802 /* Some kernels may run one past a syscall insn, so we have to cope.
803 Otherwise this is just simple_displaced_step_copy_insn. */
805 struct displaced_step_closure *
806 i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
807 CORE_ADDR from, CORE_ADDR to,
808 struct regcache *regs)
810 size_t len = gdbarch_max_insn_length (gdbarch);
811 gdb_byte *buf = (gdb_byte *) xmalloc (len);
813 read_memory (from, buf, len);
815 /* GDB may get control back after the insn after the syscall.
816 Presumably this is a kernel bug.
817 If this is a syscall, make sure there's a nop afterwards. */
822 insn = i386_skip_prefixes (buf, len);
823 if (insn != NULL && i386_syscall_p (insn, &syscall_length))
824 insn[syscall_length] = NOP_OPCODE;
827 write_memory (to, buf, len);
831 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
832 paddress (gdbarch, from), paddress (gdbarch, to));
833 displaced_step_dump_bytes (gdb_stdlog, buf, len);
836 return (struct displaced_step_closure *) buf;
839 /* Fix up the state of registers and memory after having single-stepped
840 a displaced instruction. */
843 i386_displaced_step_fixup (struct gdbarch *gdbarch,
844 struct displaced_step_closure *closure,
845 CORE_ADDR from, CORE_ADDR to,
846 struct regcache *regs)
848 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
850 /* The offset we applied to the instruction's address.
851 This could well be negative (when viewed as a signed 32-bit
852 value), but ULONGEST won't reflect that, so take care when
854 ULONGEST insn_offset = to - from;
856 /* Since we use simple_displaced_step_copy_insn, our closure is a
857 copy of the instruction. */
858 gdb_byte *insn = (gdb_byte *) closure;
859 /* The start of the insn, needed in case we see some prefixes. */
860 gdb_byte *insn_start = insn;
863 fprintf_unfiltered (gdb_stdlog,
864 "displaced: fixup (%s, %s), "
865 "insn = 0x%02x 0x%02x ...\n",
866 paddress (gdbarch, from), paddress (gdbarch, to),
869 /* The list of issues to contend with here is taken from
870 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
871 Yay for Free Software! */
873 /* Relocate the %eip, if necessary. */
875 /* The instruction recognizers we use assume any leading prefixes
876 have been skipped. */
878 /* This is the size of the buffer in closure. */
879 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
880 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
881 /* If there are too many prefixes, just ignore the insn.
882 It will fault when run. */
887 /* Except in the case of absolute or indirect jump or call
888 instructions, or a return instruction, the new eip is relative to
889 the displaced instruction; make it relative. Well, signal
890 handler returns don't need relocation either, but we use the
891 value of %eip to recognize those; see below. */
892 if (! i386_absolute_jmp_p (insn)
893 && ! i386_absolute_call_p (insn)
894 && ! i386_ret_p (insn))
899 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
901 /* A signal trampoline system call changes the %eip, resuming
902 execution of the main program after the signal handler has
903 returned. That makes them like 'return' instructions; we
904 shouldn't relocate %eip.
906 But most system calls don't, and we do need to relocate %eip.
908 Our heuristic for distinguishing these cases: if stepping
909 over the system call instruction left control directly after
910 the instruction, the we relocate --- control almost certainly
911 doesn't belong in the displaced copy. Otherwise, we assume
912 the instruction has put control where it belongs, and leave
913 it unrelocated. Goodness help us if there are PC-relative
915 if (i386_syscall_p (insn, &insn_len)
916 && orig_eip != to + (insn - insn_start) + insn_len
917 /* GDB can get control back after the insn after the syscall.
918 Presumably this is a kernel bug.
919 i386_displaced_step_copy_insn ensures its a nop,
920 we add one to the length for it. */
921 && orig_eip != to + (insn - insn_start) + insn_len + 1)
924 fprintf_unfiltered (gdb_stdlog,
925 "displaced: syscall changed %%eip; "
930 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
932 /* If we just stepped over a breakpoint insn, we don't backup
933 the pc on purpose; this is to match behaviour without
936 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
939 fprintf_unfiltered (gdb_stdlog,
941 "relocated %%eip from %s to %s\n",
942 paddress (gdbarch, orig_eip),
943 paddress (gdbarch, eip));
947 /* If the instruction was PUSHFL, then the TF bit will be set in the
948 pushed value, and should be cleared. We'll leave this for later,
949 since GDB already messes up the TF flag when stepping over a
952 /* If the instruction was a call, the return address now atop the
953 stack is the address following the copied instruction. We need
954 to make it the address following the original instruction. */
955 if (i386_call_p (insn))
959 const ULONGEST retaddr_len = 4;
961 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
962 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
963 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
964 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
967 fprintf_unfiltered (gdb_stdlog,
968 "displaced: relocated return addr at %s to %s\n",
969 paddress (gdbarch, esp),
970 paddress (gdbarch, retaddr));
975 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
977 target_write_memory (*to, buf, len);
982 i386_relocate_instruction (struct gdbarch *gdbarch,
983 CORE_ADDR *to, CORE_ADDR oldloc)
985 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
986 gdb_byte buf[I386_MAX_INSN_LEN];
987 int offset = 0, rel32, newrel;
989 gdb_byte *insn = buf;
991 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
993 insn_length = gdb_buffered_insn_length (gdbarch, insn,
994 I386_MAX_INSN_LEN, oldloc);
996 /* Get past the prefixes. */
997 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
999 /* Adjust calls with 32-bit relative addresses as push/jump, with
1000 the address pushed being the location where the original call in
1001 the user program would return to. */
1002 if (insn[0] == 0xe8)
1004 gdb_byte push_buf[16];
1005 unsigned int ret_addr;
1007 /* Where "ret" in the original code will return to. */
1008 ret_addr = oldloc + insn_length;
1009 push_buf[0] = 0x68; /* pushq $... */
1010 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
1011 /* Push the push. */
1012 append_insns (to, 5, push_buf);
1014 /* Convert the relative call to a relative jump. */
1017 /* Adjust the destination offset. */
1018 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1019 newrel = (oldloc - *to) + rel32;
1020 store_signed_integer (insn + 1, 4, byte_order, newrel);
1022 if (debug_displaced)
1023 fprintf_unfiltered (gdb_stdlog,
1024 "Adjusted insn rel32=%s at %s to"
1025 " rel32=%s at %s\n",
1026 hex_string (rel32), paddress (gdbarch, oldloc),
1027 hex_string (newrel), paddress (gdbarch, *to));
1029 /* Write the adjusted jump into its displaced location. */
1030 append_insns (to, 5, insn);
1034 /* Adjust jumps with 32-bit relative addresses. Calls are already
1036 if (insn[0] == 0xe9)
1038 /* Adjust conditional jumps. */
1039 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1044 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1045 newrel = (oldloc - *to) + rel32;
1046 store_signed_integer (insn + offset, 4, byte_order, newrel);
1047 if (debug_displaced)
1048 fprintf_unfiltered (gdb_stdlog,
1049 "Adjusted insn rel32=%s at %s to"
1050 " rel32=%s at %s\n",
1051 hex_string (rel32), paddress (gdbarch, oldloc),
1052 hex_string (newrel), paddress (gdbarch, *to));
1055 /* Write the adjusted instructions into their displaced
1057 append_insns (to, insn_length, buf);
1061 #ifdef I386_REGNO_TO_SYMMETRY
1062 #error "The Sequent Symmetry is no longer supported."
1065 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1066 and %esp "belong" to the calling function. Therefore these
1067 registers should be saved if they're going to be modified. */
1069 /* The maximum number of saved registers. This should include all
1070 registers mentioned above, and %eip. */
1071 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1073 struct i386_frame_cache
1081 /* Saved registers. */
1082 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
1087 /* Stack space reserved for local variables. */
1091 /* Allocate and initialize a frame cache. */
1093 static struct i386_frame_cache *
1094 i386_alloc_frame_cache (void)
1096 struct i386_frame_cache *cache;
1099 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
1104 cache->sp_offset = -4;
1107 /* Saved registers. We initialize these to -1 since zero is a valid
1108 offset (that's where %ebp is supposed to be stored). */
1109 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1110 cache->saved_regs[i] = -1;
1111 cache->saved_sp = 0;
1112 cache->saved_sp_reg = -1;
1113 cache->pc_in_eax = 0;
1115 /* Frameless until proven otherwise. */
1121 /* If the instruction at PC is a jump, return the address of its
1122 target. Otherwise, return PC. */
1125 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
1127 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1132 if (target_read_code (pc, &op, 1))
1139 op = read_code_unsigned_integer (pc + 1, 1, byte_order);
1145 /* Relative jump: if data16 == 0, disp32, else disp16. */
1148 delta = read_memory_integer (pc + 2, 2, byte_order);
1150 /* Include the size of the jmp instruction (including the
1156 delta = read_memory_integer (pc + 1, 4, byte_order);
1158 /* Include the size of the jmp instruction. */
1163 /* Relative jump, disp8 (ignore data16). */
1164 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
1166 delta += data16 + 2;
1173 /* Check whether PC points at a prologue for a function returning a
1174 structure or union. If so, it updates CACHE and returns the
1175 address of the first instruction after the code sequence that
1176 removes the "hidden" argument from the stack or CURRENT_PC,
1177 whichever is smaller. Otherwise, return PC. */
1180 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
1181 struct i386_frame_cache *cache)
1183 /* Functions that return a structure or union start with:
1186 xchgl %eax, (%esp) 0x87 0x04 0x24
1187 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1189 (the System V compiler puts out the second `xchg' instruction,
1190 and the assembler doesn't try to optimize it, so the 'sib' form
1191 gets generated). This sequence is used to get the address of the
1192 return buffer for a function that returns a structure. */
1193 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
1194 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
1198 if (current_pc <= pc)
1201 if (target_read_code (pc, &op, 1))
1204 if (op != 0x58) /* popl %eax */
1207 if (target_read_code (pc + 1, buf, 4))
1210 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
1213 if (current_pc == pc)
1215 cache->sp_offset += 4;
1219 if (current_pc == pc + 1)
1221 cache->pc_in_eax = 1;
1225 if (buf[1] == proto1[1])
1232 i386_skip_probe (CORE_ADDR pc)
1234 /* A function may start with
1248 if (target_read_code (pc, &op, 1))
1251 if (op == 0x68 || op == 0x6a)
1255 /* Skip past the `pushl' instruction; it has either a one-byte or a
1256 four-byte operand, depending on the opcode. */
1262 /* Read the following 8 bytes, which should be `call _probe' (6
1263 bytes) followed by `addl $4,%esp' (2 bytes). */
1264 read_memory (pc + delta, buf, sizeof (buf));
1265 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
1266 pc += delta + sizeof (buf);
1272 /* GCC 4.1 and later, can put code in the prologue to realign the
1273 stack pointer. Check whether PC points to such code, and update
1274 CACHE accordingly. Return the first instruction after the code
1275 sequence or CURRENT_PC, whichever is smaller. If we don't
1276 recognize the code, return PC. */
1279 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1280 struct i386_frame_cache *cache)
1282 /* There are 2 code sequences to re-align stack before the frame
1285 1. Use a caller-saved saved register:
1291 2. Use a callee-saved saved register:
1298 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1300 0x83 0xe4 0xf0 andl $-16, %esp
1301 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1306 int offset, offset_and;
1307 static int regnums[8] = {
1308 I386_EAX_REGNUM, /* %eax */
1309 I386_ECX_REGNUM, /* %ecx */
1310 I386_EDX_REGNUM, /* %edx */
1311 I386_EBX_REGNUM, /* %ebx */
1312 I386_ESP_REGNUM, /* %esp */
1313 I386_EBP_REGNUM, /* %ebp */
1314 I386_ESI_REGNUM, /* %esi */
1315 I386_EDI_REGNUM /* %edi */
1318 if (target_read_code (pc, buf, sizeof buf))
1321 /* Check caller-saved saved register. The first instruction has
1322 to be "leal 4(%esp), %reg". */
1323 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1325 /* MOD must be binary 10 and R/M must be binary 100. */
1326 if ((buf[1] & 0xc7) != 0x44)
1329 /* REG has register number. */
1330 reg = (buf[1] >> 3) & 7;
1335 /* Check callee-saved saved register. The first instruction
1336 has to be "pushl %reg". */
1337 if ((buf[0] & 0xf8) != 0x50)
1343 /* The next instruction has to be "leal 8(%esp), %reg". */
1344 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1347 /* MOD must be binary 10 and R/M must be binary 100. */
1348 if ((buf[2] & 0xc7) != 0x44)
1351 /* REG has register number. Registers in pushl and leal have to
1353 if (reg != ((buf[2] >> 3) & 7))
1359 /* Rigister can't be %esp nor %ebp. */
1360 if (reg == 4 || reg == 5)
1363 /* The next instruction has to be "andl $-XXX, %esp". */
1364 if (buf[offset + 1] != 0xe4
1365 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1368 offset_and = offset;
1369 offset += buf[offset] == 0x81 ? 6 : 3;
1371 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1372 0xfc. REG must be binary 110 and MOD must be binary 01. */
1373 if (buf[offset] != 0xff
1374 || buf[offset + 2] != 0xfc
1375 || (buf[offset + 1] & 0xf8) != 0x70)
1378 /* R/M has register. Registers in leal and pushl have to be the
1380 if (reg != (buf[offset + 1] & 7))
1383 if (current_pc > pc + offset_and)
1384 cache->saved_sp_reg = regnums[reg];
1386 return std::min (pc + offset + 3, current_pc);
1389 /* Maximum instruction length we need to handle. */
1390 #define I386_MAX_MATCHED_INSN_LEN 6
1392 /* Instruction description. */
1396 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
1397 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
1400 /* Return whether instruction at PC matches PATTERN. */
1403 i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern)
1407 if (target_read_code (pc, &op, 1))
1410 if ((op & pattern.mask[0]) == pattern.insn[0])
1412 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1413 int insn_matched = 1;
1416 gdb_assert (pattern.len > 1);
1417 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN);
1419 if (target_read_code (pc + 1, buf, pattern.len - 1))
1422 for (i = 1; i < pattern.len; i++)
1424 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i])
1427 return insn_matched;
1432 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1433 the first instruction description that matches. Otherwise, return
1436 static struct i386_insn *
1437 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns)
1439 struct i386_insn *pattern;
1441 for (pattern = insn_patterns; pattern->len > 0; pattern++)
1443 if (i386_match_pattern (pc, *pattern))
1450 /* Return whether PC points inside a sequence of instructions that
1451 matches INSN_PATTERNS. */
1454 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns)
1456 CORE_ADDR current_pc;
1458 struct i386_insn *insn;
1460 insn = i386_match_insn (pc, insn_patterns);
1465 ix = insn - insn_patterns;
1466 for (i = ix - 1; i >= 0; i--)
1468 current_pc -= insn_patterns[i].len;
1470 if (!i386_match_pattern (current_pc, insn_patterns[i]))
1474 current_pc = pc + insn->len;
1475 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++)
1477 if (!i386_match_pattern (current_pc, *insn))
1480 current_pc += insn->len;
1486 /* Some special instructions that might be migrated by GCC into the
1487 part of the prologue that sets up the new stack frame. Because the
1488 stack frame hasn't been setup yet, no registers have been saved
1489 yet, and only the scratch registers %eax, %ecx and %edx can be
1492 struct i386_insn i386_frame_setup_skip_insns[] =
1494 /* Check for `movb imm8, r' and `movl imm32, r'.
1496 ??? Should we handle 16-bit operand-sizes here? */
1498 /* `movb imm8, %al' and `movb imm8, %ah' */
1499 /* `movb imm8, %cl' and `movb imm8, %ch' */
1500 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1501 /* `movb imm8, %dl' and `movb imm8, %dh' */
1502 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1503 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1504 { 5, { 0xb8 }, { 0xfe } },
1505 /* `movl imm32, %edx' */
1506 { 5, { 0xba }, { 0xff } },
1508 /* Check for `mov imm32, r32'. Note that there is an alternative
1509 encoding for `mov m32, %eax'.
1511 ??? Should we handle SIB adressing here?
1512 ??? Should we handle 16-bit operand-sizes here? */
1514 /* `movl m32, %eax' */
1515 { 5, { 0xa1 }, { 0xff } },
1516 /* `movl m32, %eax' and `mov; m32, %ecx' */
1517 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1518 /* `movl m32, %edx' */
1519 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1521 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1522 Because of the symmetry, there are actually two ways to encode
1523 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1524 opcode bytes 0x31 and 0x33 for `xorl'. */
1526 /* `subl %eax, %eax' */
1527 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1528 /* `subl %ecx, %ecx' */
1529 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1530 /* `subl %edx, %edx' */
1531 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1532 /* `xorl %eax, %eax' */
1533 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1534 /* `xorl %ecx, %ecx' */
1535 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1536 /* `xorl %edx, %edx' */
1537 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1542 /* Check whether PC points to a no-op instruction. */
1544 i386_skip_noop (CORE_ADDR pc)
1549 if (target_read_code (pc, &op, 1))
1555 /* Ignore `nop' instruction. */
1559 if (target_read_code (pc, &op, 1))
1563 /* Ignore no-op instruction `mov %edi, %edi'.
1564 Microsoft system dlls often start with
1565 a `mov %edi,%edi' instruction.
1566 The 5 bytes before the function start are
1567 filled with `nop' instructions.
1568 This pattern can be used for hot-patching:
1569 The `mov %edi, %edi' instruction can be replaced by a
1570 near jump to the location of the 5 `nop' instructions
1571 which can be replaced by a 32-bit jump to anywhere
1572 in the 32-bit address space. */
1574 else if (op == 0x8b)
1576 if (target_read_code (pc + 1, &op, 1))
1582 if (target_read_code (pc, &op, 1))
1592 /* Check whether PC points at a code that sets up a new stack frame.
1593 If so, it updates CACHE and returns the address of the first
1594 instruction after the sequence that sets up the frame or LIMIT,
1595 whichever is smaller. If we don't recognize the code, return PC. */
1598 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1599 CORE_ADDR pc, CORE_ADDR limit,
1600 struct i386_frame_cache *cache)
1602 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1603 struct i386_insn *insn;
1610 if (target_read_code (pc, &op, 1))
1613 if (op == 0x55) /* pushl %ebp */
1615 /* Take into account that we've executed the `pushl %ebp' that
1616 starts this instruction sequence. */
1617 cache->saved_regs[I386_EBP_REGNUM] = 0;
1618 cache->sp_offset += 4;
1621 /* If that's all, return now. */
1625 /* Check for some special instructions that might be migrated by
1626 GCC into the prologue and skip them. At this point in the
1627 prologue, code should only touch the scratch registers %eax,
1628 %ecx and %edx, so while the number of posibilities is sheer,
1631 Make sure we only skip these instructions if we later see the
1632 `movl %esp, %ebp' that actually sets up the frame. */
1633 while (pc + skip < limit)
1635 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1642 /* If that's all, return now. */
1643 if (limit <= pc + skip)
1646 if (target_read_code (pc + skip, &op, 1))
1649 /* The i386 prologue looks like
1655 and a different prologue can be generated for atom.
1659 lea -0x10(%esp),%esp
1661 We handle both of them here. */
1665 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1667 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1673 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1678 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1679 if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order)
1688 /* OK, we actually have a frame. We just don't know how large
1689 it is yet. Set its size to zero. We'll adjust it if
1690 necessary. We also now commit to skipping the special
1691 instructions mentioned before. */
1694 /* If that's all, return now. */
1698 /* Check for stack adjustment
1704 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1705 reg, so we don't have to worry about a data16 prefix. */
1706 if (target_read_code (pc, &op, 1))
1710 /* `subl' with 8-bit immediate. */
1711 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1712 /* Some instruction starting with 0x83 other than `subl'. */
1715 /* `subl' with signed 8-bit immediate (though it wouldn't
1716 make sense to be negative). */
1717 cache->locals = read_code_integer (pc + 2, 1, byte_order);
1720 else if (op == 0x81)
1722 /* Maybe it is `subl' with a 32-bit immediate. */
1723 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1724 /* Some instruction starting with 0x81 other than `subl'. */
1727 /* It is `subl' with a 32-bit immediate. */
1728 cache->locals = read_code_integer (pc + 2, 4, byte_order);
1731 else if (op == 0x8d)
1733 /* The ModR/M byte is 0x64. */
1734 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64)
1736 /* 'lea' with 8-bit displacement. */
1737 cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order);
1742 /* Some instruction other than `subl' nor 'lea'. */
1746 else if (op == 0xc8) /* enter */
1748 cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order);
1755 /* Check whether PC points at code that saves registers on the stack.
1756 If so, it updates CACHE and returns the address of the first
1757 instruction after the register saves or CURRENT_PC, whichever is
1758 smaller. Otherwise, return PC. */
1761 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1762 struct i386_frame_cache *cache)
1764 CORE_ADDR offset = 0;
1768 if (cache->locals > 0)
1769 offset -= cache->locals;
1770 for (i = 0; i < 8 && pc < current_pc; i++)
1772 if (target_read_code (pc, &op, 1))
1774 if (op < 0x50 || op > 0x57)
1778 cache->saved_regs[op - 0x50] = offset;
1779 cache->sp_offset += 4;
1786 /* Do a full analysis of the prologue at PC and update CACHE
1787 accordingly. Bail out early if CURRENT_PC is reached. Return the
1788 address where the analysis stopped.
1790 We handle these cases:
1792 The startup sequence can be at the start of the function, or the
1793 function can start with a branch to startup code at the end.
1795 %ebp can be set up with either the 'enter' instruction, or "pushl
1796 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1797 once used in the System V compiler).
1799 Local space is allocated just below the saved %ebp by either the
1800 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1801 16-bit unsigned argument for space to allocate, and the 'addl'
1802 instruction could have either a signed byte, or 32-bit immediate.
1804 Next, the registers used by this function are pushed. With the
1805 System V compiler they will always be in the order: %edi, %esi,
1806 %ebx (and sometimes a harmless bug causes it to also save but not
1807 restore %eax); however, the code below is willing to see the pushes
1808 in any order, and will handle up to 8 of them.
1810 If the setup sequence is at the end of the function, then the next
1811 instruction will be a branch back to the start. */
1814 i386_analyze_prologue (struct gdbarch *gdbarch,
1815 CORE_ADDR pc, CORE_ADDR current_pc,
1816 struct i386_frame_cache *cache)
1818 pc = i386_skip_noop (pc);
1819 pc = i386_follow_jump (gdbarch, pc);
1820 pc = i386_analyze_struct_return (pc, current_pc, cache);
1821 pc = i386_skip_probe (pc);
1822 pc = i386_analyze_stack_align (pc, current_pc, cache);
1823 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1824 return i386_analyze_register_saves (pc, current_pc, cache);
1827 /* Return PC of first real instruction. */
1830 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1832 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1834 static gdb_byte pic_pat[6] =
1836 0xe8, 0, 0, 0, 0, /* call 0x0 */
1837 0x5b, /* popl %ebx */
1839 struct i386_frame_cache cache;
1843 CORE_ADDR func_addr;
1845 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
1847 CORE_ADDR post_prologue_pc
1848 = skip_prologue_using_sal (gdbarch, func_addr);
1849 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
1851 /* Clang always emits a line note before the prologue and another
1852 one after. We trust clang to emit usable line notes. */
1853 if (post_prologue_pc
1855 && COMPUNIT_PRODUCER (cust) != NULL
1856 && startswith (COMPUNIT_PRODUCER (cust), "clang ")))
1857 return std::max (start_pc, post_prologue_pc);
1861 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1862 if (cache.locals < 0)
1865 /* Found valid frame setup. */
1867 /* The native cc on SVR4 in -K PIC mode inserts the following code
1868 to get the address of the global offset table (GOT) into register
1873 movl %ebx,x(%ebp) (optional)
1876 This code is with the rest of the prologue (at the end of the
1877 function), so we have to skip it to get to the first real
1878 instruction at the start of the function. */
1880 for (i = 0; i < 6; i++)
1882 if (target_read_code (pc + i, &op, 1))
1885 if (pic_pat[i] != op)
1892 if (target_read_code (pc + delta, &op, 1))
1895 if (op == 0x89) /* movl %ebx, x(%ebp) */
1897 op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order);
1899 if (op == 0x5d) /* One byte offset from %ebp. */
1901 else if (op == 0x9d) /* Four byte offset from %ebp. */
1903 else /* Unexpected instruction. */
1906 if (target_read_code (pc + delta, &op, 1))
1911 if (delta > 0 && op == 0x81
1912 && read_code_unsigned_integer (pc + delta + 1, 1, byte_order)
1919 /* If the function starts with a branch (to startup code at the end)
1920 the last instruction should bring us back to the first
1921 instruction of the real code. */
1922 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1923 pc = i386_follow_jump (gdbarch, pc);
1928 /* Check that the code pointed to by PC corresponds to a call to
1929 __main, skip it if so. Return PC otherwise. */
1932 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1934 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1937 if (target_read_code (pc, &op, 1))
1943 if (target_read_code (pc + 1, buf, sizeof buf) == 0)
1945 /* Make sure address is computed correctly as a 32bit
1946 integer even if CORE_ADDR is 64 bit wide. */
1947 struct bound_minimal_symbol s;
1948 CORE_ADDR call_dest;
1950 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1951 call_dest = call_dest & 0xffffffffU;
1952 s = lookup_minimal_symbol_by_pc (call_dest);
1953 if (s.minsym != NULL
1954 && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL
1955 && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0)
1963 /* This function is 64-bit safe. */
1966 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1970 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1971 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1975 /* Normal frames. */
1978 i386_frame_cache_1 (struct frame_info *this_frame,
1979 struct i386_frame_cache *cache)
1981 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1982 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1986 cache->pc = get_frame_func (this_frame);
1988 /* In principle, for normal frames, %ebp holds the frame pointer,
1989 which holds the base address for the current stack frame.
1990 However, for functions that don't need it, the frame pointer is
1991 optional. For these "frameless" functions the frame pointer is
1992 actually the frame pointer of the calling frame. Signal
1993 trampolines are just a special case of a "frameless" function.
1994 They (usually) share their frame pointer with the frame that was
1995 in progress when the signal occurred. */
1997 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1998 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1999 if (cache->base == 0)
2005 /* For normal frames, %eip is stored at 4(%ebp). */
2006 cache->saved_regs[I386_EIP_REGNUM] = 4;
2009 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
2012 if (cache->locals < 0)
2014 /* We didn't find a valid frame, which means that CACHE->base
2015 currently holds the frame pointer for our calling frame. If
2016 we're at the start of a function, or somewhere half-way its
2017 prologue, the function's frame probably hasn't been fully
2018 setup yet. Try to reconstruct the base address for the stack
2019 frame by looking at the stack pointer. For truly "frameless"
2020 functions this might work too. */
2022 if (cache->saved_sp_reg != -1)
2024 /* Saved stack pointer has been saved. */
2025 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2026 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2028 /* We're halfway aligning the stack. */
2029 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
2030 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
2032 /* This will be added back below. */
2033 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
2035 else if (cache->pc != 0
2036 || target_read_code (get_frame_pc (this_frame), buf, 1))
2038 /* We're in a known function, but did not find a frame
2039 setup. Assume that the function does not use %ebp.
2040 Alternatively, we may have jumped to an invalid
2041 address; in that case there is definitely no new
2043 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2044 cache->base = extract_unsigned_integer (buf, 4, byte_order)
2048 /* We're in an unknown function. We could not find the start
2049 of the function to analyze the prologue; our best option is
2050 to assume a typical frame layout with the caller's %ebp
2052 cache->saved_regs[I386_EBP_REGNUM] = 0;
2055 if (cache->saved_sp_reg != -1)
2057 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2058 register may be unavailable). */
2059 if (cache->saved_sp == 0
2060 && deprecated_frame_register_read (this_frame,
2061 cache->saved_sp_reg, buf))
2062 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2064 /* Now that we have the base address for the stack frame we can
2065 calculate the value of %esp in the calling frame. */
2066 else if (cache->saved_sp == 0)
2067 cache->saved_sp = cache->base + 8;
2069 /* Adjust all the saved registers such that they contain addresses
2070 instead of offsets. */
2071 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
2072 if (cache->saved_regs[i] != -1)
2073 cache->saved_regs[i] += cache->base;
2078 static struct i386_frame_cache *
2079 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
2081 struct i386_frame_cache *cache;
2084 return (struct i386_frame_cache *) *this_cache;
2086 cache = i386_alloc_frame_cache ();
2087 *this_cache = cache;
2091 i386_frame_cache_1 (this_frame, cache);
2093 CATCH (ex, RETURN_MASK_ERROR)
2095 if (ex.error != NOT_AVAILABLE_ERROR)
2096 throw_exception (ex);
2104 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
2105 struct frame_id *this_id)
2107 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2110 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2111 else if (cache->base == 0)
2113 /* This marks the outermost frame. */
2117 /* See the end of i386_push_dummy_call. */
2118 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2122 static enum unwind_stop_reason
2123 i386_frame_unwind_stop_reason (struct frame_info *this_frame,
2126 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2129 return UNWIND_UNAVAILABLE;
2131 /* This marks the outermost frame. */
2132 if (cache->base == 0)
2133 return UNWIND_OUTERMOST;
2135 return UNWIND_NO_REASON;
2138 static struct value *
2139 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2142 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2144 gdb_assert (regnum >= 0);
2146 /* The System V ABI says that:
2148 "The flags register contains the system flags, such as the
2149 direction flag and the carry flag. The direction flag must be
2150 set to the forward (that is, zero) direction before entry and
2151 upon exit from a function. Other user flags have no specified
2152 role in the standard calling sequence and are not preserved."
2154 To guarantee the "upon exit" part of that statement we fake a
2155 saved flags register that has its direction flag cleared.
2157 Note that GCC doesn't seem to rely on the fact that the direction
2158 flag is cleared after a function return; it always explicitly
2159 clears the flag before operations where it matters.
2161 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2162 right thing to do. The way we fake the flags register here makes
2163 it impossible to change it. */
2165 if (regnum == I386_EFLAGS_REGNUM)
2169 val = get_frame_register_unsigned (this_frame, regnum);
2171 return frame_unwind_got_constant (this_frame, regnum, val);
2174 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
2175 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
2177 if (regnum == I386_ESP_REGNUM
2178 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1))
2180 /* If the SP has been saved, but we don't know where, then this
2181 means that SAVED_SP_REG register was found unavailable back
2182 when we built the cache. */
2183 if (cache->saved_sp == 0)
2184 return frame_unwind_got_register (this_frame, regnum,
2185 cache->saved_sp_reg);
2187 return frame_unwind_got_constant (this_frame, regnum,
2191 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2192 return frame_unwind_got_memory (this_frame, regnum,
2193 cache->saved_regs[regnum]);
2195 return frame_unwind_got_register (this_frame, regnum, regnum);
2198 static const struct frame_unwind i386_frame_unwind =
2201 i386_frame_unwind_stop_reason,
2203 i386_frame_prev_register,
2205 default_frame_sniffer
2208 /* Normal frames, but in a function epilogue. */
2210 /* Implement the stack_frame_destroyed_p gdbarch method.
2212 The epilogue is defined here as the 'ret' instruction, which will
2213 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2214 the function's stack frame. */
2217 i386_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2220 struct compunit_symtab *cust;
2222 cust = find_pc_compunit_symtab (pc);
2223 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
2226 if (target_read_memory (pc, &insn, 1))
2227 return 0; /* Can't read memory at pc. */
2229 if (insn != 0xc3) /* 'ret' instruction. */
2236 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
2237 struct frame_info *this_frame,
2238 void **this_prologue_cache)
2240 if (frame_relative_level (this_frame) == 0)
2241 return i386_stack_frame_destroyed_p (get_frame_arch (this_frame),
2242 get_frame_pc (this_frame));
2247 static struct i386_frame_cache *
2248 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2250 struct i386_frame_cache *cache;
2254 return (struct i386_frame_cache *) *this_cache;
2256 cache = i386_alloc_frame_cache ();
2257 *this_cache = cache;
2261 cache->pc = get_frame_func (this_frame);
2263 /* At this point the stack looks as if we just entered the
2264 function, with the return address at the top of the
2266 sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM);
2267 cache->base = sp + cache->sp_offset;
2268 cache->saved_sp = cache->base + 8;
2269 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
2273 CATCH (ex, RETURN_MASK_ERROR)
2275 if (ex.error != NOT_AVAILABLE_ERROR)
2276 throw_exception (ex);
2283 static enum unwind_stop_reason
2284 i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2287 struct i386_frame_cache *cache =
2288 i386_epilogue_frame_cache (this_frame, this_cache);
2291 return UNWIND_UNAVAILABLE;
2293 return UNWIND_NO_REASON;
2297 i386_epilogue_frame_this_id (struct frame_info *this_frame,
2299 struct frame_id *this_id)
2301 struct i386_frame_cache *cache =
2302 i386_epilogue_frame_cache (this_frame, this_cache);
2305 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2307 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2310 static struct value *
2311 i386_epilogue_frame_prev_register (struct frame_info *this_frame,
2312 void **this_cache, int regnum)
2314 /* Make sure we've initialized the cache. */
2315 i386_epilogue_frame_cache (this_frame, this_cache);
2317 return i386_frame_prev_register (this_frame, this_cache, regnum);
2320 static const struct frame_unwind i386_epilogue_frame_unwind =
2323 i386_epilogue_frame_unwind_stop_reason,
2324 i386_epilogue_frame_this_id,
2325 i386_epilogue_frame_prev_register,
2327 i386_epilogue_frame_sniffer
2331 /* Stack-based trampolines. */
2333 /* These trampolines are used on cross x86 targets, when taking the
2334 address of a nested function. When executing these trampolines,
2335 no stack frame is set up, so we are in a similar situation as in
2336 epilogues and i386_epilogue_frame_this_id can be re-used. */
2338 /* Static chain passed in register. */
2340 struct i386_insn i386_tramp_chain_in_reg_insns[] =
2342 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2343 { 5, { 0xb8 }, { 0xfe } },
2346 { 5, { 0xe9 }, { 0xff } },
2351 /* Static chain passed on stack (when regparm=3). */
2353 struct i386_insn i386_tramp_chain_on_stack_insns[] =
2356 { 5, { 0x68 }, { 0xff } },
2359 { 5, { 0xe9 }, { 0xff } },
2364 /* Return whether PC points inside a stack trampoline. */
2367 i386_in_stack_tramp_p (CORE_ADDR pc)
2372 /* A stack trampoline is detected if no name is associated
2373 to the current pc and if it points inside a trampoline
2376 find_pc_partial_function (pc, &name, NULL, NULL);
2380 if (target_read_memory (pc, &insn, 1))
2383 if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns)
2384 && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns))
2391 i386_stack_tramp_frame_sniffer (const struct frame_unwind *self,
2392 struct frame_info *this_frame,
2395 if (frame_relative_level (this_frame) == 0)
2396 return i386_in_stack_tramp_p (get_frame_pc (this_frame));
2401 static const struct frame_unwind i386_stack_tramp_frame_unwind =
2404 i386_epilogue_frame_unwind_stop_reason,
2405 i386_epilogue_frame_this_id,
2406 i386_epilogue_frame_prev_register,
2408 i386_stack_tramp_frame_sniffer
2411 /* Generate a bytecode expression to get the value of the saved PC. */
2414 i386_gen_return_address (struct gdbarch *gdbarch,
2415 struct agent_expr *ax, struct axs_value *value,
2418 /* The following sequence assumes the traditional use of the base
2420 ax_reg (ax, I386_EBP_REGNUM);
2422 ax_simple (ax, aop_add);
2423 value->type = register_type (gdbarch, I386_EIP_REGNUM);
2424 value->kind = axs_lvalue_memory;
2428 /* Signal trampolines. */
2430 static struct i386_frame_cache *
2431 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2433 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2434 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2435 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2436 struct i386_frame_cache *cache;
2441 return (struct i386_frame_cache *) *this_cache;
2443 cache = i386_alloc_frame_cache ();
2447 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2448 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
2450 addr = tdep->sigcontext_addr (this_frame);
2451 if (tdep->sc_reg_offset)
2455 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
2457 for (i = 0; i < tdep->sc_num_regs; i++)
2458 if (tdep->sc_reg_offset[i] != -1)
2459 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2463 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
2464 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
2469 CATCH (ex, RETURN_MASK_ERROR)
2471 if (ex.error != NOT_AVAILABLE_ERROR)
2472 throw_exception (ex);
2476 *this_cache = cache;
2480 static enum unwind_stop_reason
2481 i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2484 struct i386_frame_cache *cache =
2485 i386_sigtramp_frame_cache (this_frame, this_cache);
2488 return UNWIND_UNAVAILABLE;
2490 return UNWIND_NO_REASON;
2494 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
2495 struct frame_id *this_id)
2497 struct i386_frame_cache *cache =
2498 i386_sigtramp_frame_cache (this_frame, this_cache);
2501 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2504 /* See the end of i386_push_dummy_call. */
2505 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
2509 static struct value *
2510 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
2511 void **this_cache, int regnum)
2513 /* Make sure we've initialized the cache. */
2514 i386_sigtramp_frame_cache (this_frame, this_cache);
2516 return i386_frame_prev_register (this_frame, this_cache, regnum);
2520 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
2521 struct frame_info *this_frame,
2522 void **this_prologue_cache)
2524 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2526 /* We shouldn't even bother if we don't have a sigcontext_addr
2528 if (tdep->sigcontext_addr == NULL)
2531 if (tdep->sigtramp_p != NULL)
2533 if (tdep->sigtramp_p (this_frame))
2537 if (tdep->sigtramp_start != 0)
2539 CORE_ADDR pc = get_frame_pc (this_frame);
2541 gdb_assert (tdep->sigtramp_end != 0);
2542 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2549 static const struct frame_unwind i386_sigtramp_frame_unwind =
2552 i386_sigtramp_frame_unwind_stop_reason,
2553 i386_sigtramp_frame_this_id,
2554 i386_sigtramp_frame_prev_register,
2556 i386_sigtramp_frame_sniffer
2561 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
2563 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2568 static const struct frame_base i386_frame_base =
2571 i386_frame_base_address,
2572 i386_frame_base_address,
2573 i386_frame_base_address
2576 static struct frame_id
2577 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2581 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
2583 /* See the end of i386_push_dummy_call. */
2584 return frame_id_build (fp + 8, get_frame_pc (this_frame));
2587 /* _Decimal128 function return values need 16-byte alignment on the
2591 i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2593 return sp & -(CORE_ADDR)16;
2597 /* Figure out where the longjmp will land. Slurp the args out of the
2598 stack. We expect the first arg to be a pointer to the jmp_buf
2599 structure from which we extract the address that we will land at.
2600 This address is copied into PC. This routine returns non-zero on
2604 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2607 CORE_ADDR sp, jb_addr;
2608 struct gdbarch *gdbarch = get_frame_arch (frame);
2609 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2610 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2612 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2613 longjmp will land. */
2614 if (jb_pc_offset == -1)
2617 get_frame_register (frame, I386_ESP_REGNUM, buf);
2618 sp = extract_unsigned_integer (buf, 4, byte_order);
2619 if (target_read_memory (sp + 4, buf, 4))
2622 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
2623 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
2626 *pc = extract_unsigned_integer (buf, 4, byte_order);
2631 /* Check whether TYPE must be 16-byte-aligned when passed as a
2632 function argument. 16-byte vectors, _Decimal128 and structures or
2633 unions containing such types must be 16-byte-aligned; other
2634 arguments are 4-byte-aligned. */
2637 i386_16_byte_align_p (struct type *type)
2639 type = check_typedef (type);
2640 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
2641 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
2642 && TYPE_LENGTH (type) == 16)
2644 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2645 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
2646 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2647 || TYPE_CODE (type) == TYPE_CODE_UNION)
2650 for (i = 0; i < TYPE_NFIELDS (type); i++)
2652 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
2659 /* Implementation for set_gdbarch_push_dummy_code. */
2662 i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
2663 struct value **args, int nargs, struct type *value_type,
2664 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
2665 struct regcache *regcache)
2667 /* Use 0xcc breakpoint - 1 byte. */
2671 /* Keep the stack aligned. */
2676 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2677 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2678 struct value **args, CORE_ADDR sp, int struct_return,
2679 CORE_ADDR struct_addr)
2681 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2687 /* Determine the total space required for arguments and struct
2688 return address in a first pass (allowing for 16-byte-aligned
2689 arguments), then push arguments in a second pass. */
2691 for (write_pass = 0; write_pass < 2; write_pass++)
2693 int args_space_used = 0;
2699 /* Push value address. */
2700 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2701 write_memory (sp, buf, 4);
2702 args_space_used += 4;
2708 for (i = 0; i < nargs; i++)
2710 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2714 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2715 args_space_used = align_up (args_space_used, 16);
2717 write_memory (sp + args_space_used,
2718 value_contents_all (args[i]), len);
2719 /* The System V ABI says that:
2721 "An argument's size is increased, if necessary, to make it a
2722 multiple of [32-bit] words. This may require tail padding,
2723 depending on the size of the argument."
2725 This makes sure the stack stays word-aligned. */
2726 args_space_used += align_up (len, 4);
2730 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2731 args_space = align_up (args_space, 16);
2732 args_space += align_up (len, 4);
2740 /* The original System V ABI only requires word alignment,
2741 but modern incarnations need 16-byte alignment in order
2742 to support SSE. Since wasting a few bytes here isn't
2743 harmful we unconditionally enforce 16-byte alignment. */
2748 /* Store return address. */
2750 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2751 write_memory (sp, buf, 4);
2753 /* Finally, update the stack pointer... */
2754 store_unsigned_integer (buf, 4, byte_order, sp);
2755 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
2757 /* ...and fake a frame pointer. */
2758 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
2760 /* MarkK wrote: This "+ 8" is all over the place:
2761 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2762 i386_dummy_id). It's there, since all frame unwinders for
2763 a given target have to agree (within a certain margin) on the
2764 definition of the stack address of a frame. Otherwise frame id
2765 comparison might not work correctly. Since DWARF2/GCC uses the
2766 stack address *before* the function call as a frame's CFA. On
2767 the i386, when %ebp is used as a frame pointer, the offset
2768 between the contents %ebp and the CFA as defined by GCC. */
2772 /* These registers are used for returning integers (and on some
2773 targets also for returning `struct' and `union' values when their
2774 size and alignment match an integer type). */
2775 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2776 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2778 /* Read, for architecture GDBARCH, a function return value of TYPE
2779 from REGCACHE, and copy that into VALBUF. */
2782 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2783 struct regcache *regcache, gdb_byte *valbuf)
2785 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2786 int len = TYPE_LENGTH (type);
2787 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2789 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2791 if (tdep->st0_regnum < 0)
2793 warning (_("Cannot find floating-point return value."));
2794 memset (valbuf, 0, len);
2798 /* Floating-point return values can be found in %st(0). Convert
2799 its contents to the desired type. This is probably not
2800 exactly how it would happen on the target itself, but it is
2801 the best we can do. */
2802 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2803 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
2807 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2808 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2810 if (len <= low_size)
2812 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2813 memcpy (valbuf, buf, len);
2815 else if (len <= (low_size + high_size))
2817 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2818 memcpy (valbuf, buf, low_size);
2819 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2820 memcpy (valbuf + low_size, buf, len - low_size);
2823 internal_error (__FILE__, __LINE__,
2824 _("Cannot extract return value of %d bytes long."),
2829 /* Write, for architecture GDBARCH, a function return value of TYPE
2830 from VALBUF into REGCACHE. */
2833 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2834 struct regcache *regcache, const gdb_byte *valbuf)
2836 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2837 int len = TYPE_LENGTH (type);
2839 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2842 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2844 if (tdep->st0_regnum < 0)
2846 warning (_("Cannot set floating-point return value."));
2850 /* Returning floating-point values is a bit tricky. Apart from
2851 storing the return value in %st(0), we have to simulate the
2852 state of the FPU at function return point. */
2854 /* Convert the value found in VALBUF to the extended
2855 floating-point format used by the FPU. This is probably
2856 not exactly how it would happen on the target itself, but
2857 it is the best we can do. */
2858 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
2859 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2861 /* Set the top of the floating-point register stack to 7. The
2862 actual value doesn't really matter, but 7 is what a normal
2863 function return would end up with if the program started out
2864 with a freshly initialized FPU. */
2865 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2867 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2869 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2870 the floating-point register stack to 7, the appropriate value
2871 for the tag word is 0x3fff. */
2872 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2876 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2877 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2879 if (len <= low_size)
2880 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2881 else if (len <= (low_size + high_size))
2883 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2884 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
2885 len - low_size, valbuf + low_size);
2888 internal_error (__FILE__, __LINE__,
2889 _("Cannot store return value of %d bytes long."), len);
2894 /* This is the variable that is set with "set struct-convention", and
2895 its legitimate values. */
2896 static const char default_struct_convention[] = "default";
2897 static const char pcc_struct_convention[] = "pcc";
2898 static const char reg_struct_convention[] = "reg";
2899 static const char *const valid_conventions[] =
2901 default_struct_convention,
2902 pcc_struct_convention,
2903 reg_struct_convention,
2906 static const char *struct_convention = default_struct_convention;
2908 /* Return non-zero if TYPE, which is assumed to be a structure,
2909 a union type, or an array type, should be returned in registers
2910 for architecture GDBARCH. */
2913 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2915 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2916 enum type_code code = TYPE_CODE (type);
2917 int len = TYPE_LENGTH (type);
2919 gdb_assert (code == TYPE_CODE_STRUCT
2920 || code == TYPE_CODE_UNION
2921 || code == TYPE_CODE_ARRAY);
2923 if (struct_convention == pcc_struct_convention
2924 || (struct_convention == default_struct_convention
2925 && tdep->struct_return == pcc_struct_return))
2928 /* Structures consisting of a single `float', `double' or 'long
2929 double' member are returned in %st(0). */
2930 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2932 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2933 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2934 return (len == 4 || len == 8 || len == 12);
2937 return (len == 1 || len == 2 || len == 4 || len == 8);
2940 /* Determine, for architecture GDBARCH, how a return value of TYPE
2941 should be returned. If it is supposed to be returned in registers,
2942 and READBUF is non-zero, read the appropriate value from REGCACHE,
2943 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2944 from WRITEBUF into REGCACHE. */
2946 static enum return_value_convention
2947 i386_return_value (struct gdbarch *gdbarch, struct value *function,
2948 struct type *type, struct regcache *regcache,
2949 gdb_byte *readbuf, const gdb_byte *writebuf)
2951 enum type_code code = TYPE_CODE (type);
2953 if (((code == TYPE_CODE_STRUCT
2954 || code == TYPE_CODE_UNION
2955 || code == TYPE_CODE_ARRAY)
2956 && !i386_reg_struct_return_p (gdbarch, type))
2957 /* Complex double and long double uses the struct return covention. */
2958 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16)
2959 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24)
2960 /* 128-bit decimal float uses the struct return convention. */
2961 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2963 /* The System V ABI says that:
2965 "A function that returns a structure or union also sets %eax
2966 to the value of the original address of the caller's area
2967 before it returns. Thus when the caller receives control
2968 again, the address of the returned object resides in register
2969 %eax and can be used to access the object."
2971 So the ABI guarantees that we can always find the return
2972 value just after the function has returned. */
2974 /* Note that the ABI doesn't mention functions returning arrays,
2975 which is something possible in certain languages such as Ada.
2976 In this case, the value is returned as if it was wrapped in
2977 a record, so the convention applied to records also applies
2984 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2985 read_memory (addr, readbuf, TYPE_LENGTH (type));
2988 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2991 /* This special case is for structures consisting of a single
2992 `float', `double' or 'long double' member. These structures are
2993 returned in %st(0). For these structures, we call ourselves
2994 recursively, changing TYPE into the type of the first member of
2995 the structure. Since that should work for all structures that
2996 have only one member, we don't bother to check the member's type
2998 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
3000 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
3001 return i386_return_value (gdbarch, function, type, regcache,
3006 i386_extract_return_value (gdbarch, type, regcache, readbuf);
3008 i386_store_return_value (gdbarch, type, regcache, writebuf);
3010 return RETURN_VALUE_REGISTER_CONVENTION;
3015 i387_ext_type (struct gdbarch *gdbarch)
3017 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3019 if (!tdep->i387_ext_type)
3021 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
3022 gdb_assert (tdep->i387_ext_type != NULL);
3025 return tdep->i387_ext_type;
3028 /* Construct type for pseudo BND registers. We can't use
3029 tdesc_find_type since a complement of one value has to be used
3030 to describe the upper bound. */
3032 static struct type *
3033 i386_bnd_type (struct gdbarch *gdbarch)
3035 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3038 if (!tdep->i386_bnd_type)
3041 const struct builtin_type *bt = builtin_type (gdbarch);
3043 /* The type we're building is described bellow: */
3048 void *ubound; /* One complement of raw ubound field. */
3052 t = arch_composite_type (gdbarch,
3053 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT);
3055 append_composite_type_field (t, "lbound", bt->builtin_data_ptr);
3056 append_composite_type_field (t, "ubound", bt->builtin_data_ptr);
3058 TYPE_NAME (t) = "builtin_type_bound128";
3059 tdep->i386_bnd_type = t;
3062 return tdep->i386_bnd_type;
3065 /* Construct vector type for pseudo ZMM registers. We can't use
3066 tdesc_find_type since ZMM isn't described in target description. */
3068 static struct type *
3069 i386_zmm_type (struct gdbarch *gdbarch)
3071 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3073 if (!tdep->i386_zmm_type)
3075 const struct builtin_type *bt = builtin_type (gdbarch);
3077 /* The type we're building is this: */
3079 union __gdb_builtin_type_vec512i
3081 int128_t uint128[4];
3082 int64_t v4_int64[8];
3083 int32_t v8_int32[16];
3084 int16_t v16_int16[32];
3085 int8_t v32_int8[64];
3086 double v4_double[8];
3093 t = arch_composite_type (gdbarch,
3094 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION);
3095 append_composite_type_field (t, "v16_float",
3096 init_vector_type (bt->builtin_float, 16));
3097 append_composite_type_field (t, "v8_double",
3098 init_vector_type (bt->builtin_double, 8));
3099 append_composite_type_field (t, "v64_int8",
3100 init_vector_type (bt->builtin_int8, 64));
3101 append_composite_type_field (t, "v32_int16",
3102 init_vector_type (bt->builtin_int16, 32));
3103 append_composite_type_field (t, "v16_int32",
3104 init_vector_type (bt->builtin_int32, 16));
3105 append_composite_type_field (t, "v8_int64",
3106 init_vector_type (bt->builtin_int64, 8));
3107 append_composite_type_field (t, "v4_int128",
3108 init_vector_type (bt->builtin_int128, 4));
3110 TYPE_VECTOR (t) = 1;
3111 TYPE_NAME (t) = "builtin_type_vec512i";
3112 tdep->i386_zmm_type = t;
3115 return tdep->i386_zmm_type;
3118 /* Construct vector type for pseudo YMM registers. We can't use
3119 tdesc_find_type since YMM isn't described in target description. */
3121 static struct type *
3122 i386_ymm_type (struct gdbarch *gdbarch)
3124 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3126 if (!tdep->i386_ymm_type)
3128 const struct builtin_type *bt = builtin_type (gdbarch);
3130 /* The type we're building is this: */
3132 union __gdb_builtin_type_vec256i
3134 int128_t uint128[2];
3135 int64_t v2_int64[4];
3136 int32_t v4_int32[8];
3137 int16_t v8_int16[16];
3138 int8_t v16_int8[32];
3139 double v2_double[4];
3146 t = arch_composite_type (gdbarch,
3147 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
3148 append_composite_type_field (t, "v8_float",
3149 init_vector_type (bt->builtin_float, 8));
3150 append_composite_type_field (t, "v4_double",
3151 init_vector_type (bt->builtin_double, 4));
3152 append_composite_type_field (t, "v32_int8",
3153 init_vector_type (bt->builtin_int8, 32));
3154 append_composite_type_field (t, "v16_int16",
3155 init_vector_type (bt->builtin_int16, 16));
3156 append_composite_type_field (t, "v8_int32",
3157 init_vector_type (bt->builtin_int32, 8));
3158 append_composite_type_field (t, "v4_int64",
3159 init_vector_type (bt->builtin_int64, 4));
3160 append_composite_type_field (t, "v2_int128",
3161 init_vector_type (bt->builtin_int128, 2));
3163 TYPE_VECTOR (t) = 1;
3164 TYPE_NAME (t) = "builtin_type_vec256i";
3165 tdep->i386_ymm_type = t;
3168 return tdep->i386_ymm_type;
3171 /* Construct vector type for MMX registers. */
3172 static struct type *
3173 i386_mmx_type (struct gdbarch *gdbarch)
3175 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3177 if (!tdep->i386_mmx_type)
3179 const struct builtin_type *bt = builtin_type (gdbarch);
3181 /* The type we're building is this: */
3183 union __gdb_builtin_type_vec64i
3186 int32_t v2_int32[2];
3187 int16_t v4_int16[4];
3194 t = arch_composite_type (gdbarch,
3195 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
3197 append_composite_type_field (t, "uint64", bt->builtin_int64);
3198 append_composite_type_field (t, "v2_int32",
3199 init_vector_type (bt->builtin_int32, 2));
3200 append_composite_type_field (t, "v4_int16",
3201 init_vector_type (bt->builtin_int16, 4));
3202 append_composite_type_field (t, "v8_int8",
3203 init_vector_type (bt->builtin_int8, 8));
3205 TYPE_VECTOR (t) = 1;
3206 TYPE_NAME (t) = "builtin_type_vec64i";
3207 tdep->i386_mmx_type = t;
3210 return tdep->i386_mmx_type;
3213 /* Return the GDB type object for the "standard" data type of data in
3217 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3219 if (i386_bnd_regnum_p (gdbarch, regnum))
3220 return i386_bnd_type (gdbarch);
3221 if (i386_mmx_regnum_p (gdbarch, regnum))
3222 return i386_mmx_type (gdbarch);
3223 else if (i386_ymm_regnum_p (gdbarch, regnum))
3224 return i386_ymm_type (gdbarch);
3225 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3226 return i386_ymm_type (gdbarch);
3227 else if (i386_zmm_regnum_p (gdbarch, regnum))
3228 return i386_zmm_type (gdbarch);
3231 const struct builtin_type *bt = builtin_type (gdbarch);
3232 if (i386_byte_regnum_p (gdbarch, regnum))
3233 return bt->builtin_int8;
3234 else if (i386_word_regnum_p (gdbarch, regnum))
3235 return bt->builtin_int16;
3236 else if (i386_dword_regnum_p (gdbarch, regnum))
3237 return bt->builtin_int32;
3238 else if (i386_k_regnum_p (gdbarch, regnum))
3239 return bt->builtin_int64;
3242 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3245 /* Map a cooked register onto a raw register or memory. For the i386,
3246 the MMX registers need to be mapped onto floating point registers. */
3249 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
3251 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
3256 mmxreg = regnum - tdep->mm0_regnum;
3257 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
3258 tos = (fstat >> 11) & 0x7;
3259 fpreg = (mmxreg + tos) % 8;
3261 return (I387_ST0_REGNUM (tdep) + fpreg);
3264 /* A helper function for us by i386_pseudo_register_read_value and
3265 amd64_pseudo_register_read_value. It does all the work but reads
3266 the data into an already-allocated value. */
3269 i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
3270 struct regcache *regcache,
3272 struct value *result_value)
3274 gdb_byte raw_buf[MAX_REGISTER_SIZE];
3275 enum register_status status;
3276 gdb_byte *buf = value_contents_raw (result_value);
3278 if (i386_mmx_regnum_p (gdbarch, regnum))
3280 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3282 /* Extract (always little endian). */
3283 status = regcache_raw_read (regcache, fpnum, raw_buf);
3284 if (status != REG_VALID)
3285 mark_value_bytes_unavailable (result_value, 0,
3286 TYPE_LENGTH (value_type (result_value)));
3288 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
3292 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3293 if (i386_bnd_regnum_p (gdbarch, regnum))
3295 regnum -= tdep->bnd0_regnum;
3297 /* Extract (always little endian). Read lower 128bits. */
3298 status = regcache_raw_read (regcache,
3299 I387_BND0R_REGNUM (tdep) + regnum,
3301 if (status != REG_VALID)
3302 mark_value_bytes_unavailable (result_value, 0, 16);
3305 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3306 LONGEST upper, lower;
3307 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3309 lower = extract_unsigned_integer (raw_buf, 8, byte_order);
3310 upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order);
3313 memcpy (buf, &lower, size);
3314 memcpy (buf + size, &upper, size);
3317 else if (i386_k_regnum_p (gdbarch, regnum))
3319 regnum -= tdep->k0_regnum;
3321 /* Extract (always little endian). */
3322 status = regcache_raw_read (regcache,
3323 tdep->k0_regnum + regnum,
3325 if (status != REG_VALID)
3326 mark_value_bytes_unavailable (result_value, 0, 8);
3328 memcpy (buf, raw_buf, 8);
3330 else if (i386_zmm_regnum_p (gdbarch, regnum))
3332 regnum -= tdep->zmm0_regnum;
3334 if (regnum < num_lower_zmm_regs)
3336 /* Extract (always little endian). Read lower 128bits. */
3337 status = regcache_raw_read (regcache,
3338 I387_XMM0_REGNUM (tdep) + regnum,
3340 if (status != REG_VALID)
3341 mark_value_bytes_unavailable (result_value, 0, 16);
3343 memcpy (buf, raw_buf, 16);
3345 /* Extract (always little endian). Read upper 128bits. */
3346 status = regcache_raw_read (regcache,
3347 tdep->ymm0h_regnum + regnum,
3349 if (status != REG_VALID)
3350 mark_value_bytes_unavailable (result_value, 16, 16);
3352 memcpy (buf + 16, raw_buf, 16);
3356 /* Extract (always little endian). Read lower 128bits. */
3357 status = regcache_raw_read (regcache,
3358 I387_XMM16_REGNUM (tdep) + regnum
3359 - num_lower_zmm_regs,
3361 if (status != REG_VALID)
3362 mark_value_bytes_unavailable (result_value, 0, 16);
3364 memcpy (buf, raw_buf, 16);
3366 /* Extract (always little endian). Read upper 128bits. */
3367 status = regcache_raw_read (regcache,
3368 I387_YMM16H_REGNUM (tdep) + regnum
3369 - num_lower_zmm_regs,
3371 if (status != REG_VALID)
3372 mark_value_bytes_unavailable (result_value, 16, 16);
3374 memcpy (buf + 16, raw_buf, 16);
3377 /* Read upper 256bits. */
3378 status = regcache_raw_read (regcache,
3379 tdep->zmm0h_regnum + regnum,
3381 if (status != REG_VALID)
3382 mark_value_bytes_unavailable (result_value, 32, 32);
3384 memcpy (buf + 32, raw_buf, 32);
3386 else if (i386_ymm_regnum_p (gdbarch, regnum))
3388 regnum -= tdep->ymm0_regnum;
3390 /* Extract (always little endian). Read lower 128bits. */
3391 status = regcache_raw_read (regcache,
3392 I387_XMM0_REGNUM (tdep) + regnum,
3394 if (status != REG_VALID)
3395 mark_value_bytes_unavailable (result_value, 0, 16);
3397 memcpy (buf, raw_buf, 16);
3398 /* Read upper 128bits. */
3399 status = regcache_raw_read (regcache,
3400 tdep->ymm0h_regnum + regnum,
3402 if (status != REG_VALID)
3403 mark_value_bytes_unavailable (result_value, 16, 32);
3405 memcpy (buf + 16, raw_buf, 16);
3407 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3409 regnum -= tdep->ymm16_regnum;
3410 /* Extract (always little endian). Read lower 128bits. */
3411 status = regcache_raw_read (regcache,
3412 I387_XMM16_REGNUM (tdep) + regnum,
3414 if (status != REG_VALID)
3415 mark_value_bytes_unavailable (result_value, 0, 16);
3417 memcpy (buf, raw_buf, 16);
3418 /* Read upper 128bits. */
3419 status = regcache_raw_read (regcache,
3420 tdep->ymm16h_regnum + regnum,
3422 if (status != REG_VALID)
3423 mark_value_bytes_unavailable (result_value, 16, 16);
3425 memcpy (buf + 16, raw_buf, 16);
3427 else if (i386_word_regnum_p (gdbarch, regnum))
3429 int gpnum = regnum - tdep->ax_regnum;
3431 /* Extract (always little endian). */
3432 status = regcache_raw_read (regcache, gpnum, raw_buf);
3433 if (status != REG_VALID)
3434 mark_value_bytes_unavailable (result_value, 0,
3435 TYPE_LENGTH (value_type (result_value)));
3437 memcpy (buf, raw_buf, 2);
3439 else if (i386_byte_regnum_p (gdbarch, regnum))
3441 int gpnum = regnum - tdep->al_regnum;
3443 /* Extract (always little endian). We read both lower and
3445 status = regcache_raw_read (regcache, gpnum % 4, raw_buf);
3446 if (status != REG_VALID)
3447 mark_value_bytes_unavailable (result_value, 0,
3448 TYPE_LENGTH (value_type (result_value)));
3449 else if (gpnum >= 4)
3450 memcpy (buf, raw_buf + 1, 1);
3452 memcpy (buf, raw_buf, 1);
3455 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3459 static struct value *
3460 i386_pseudo_register_read_value (struct gdbarch *gdbarch,
3461 struct regcache *regcache,
3464 struct value *result;
3466 result = allocate_value (register_type (gdbarch, regnum));
3467 VALUE_LVAL (result) = lval_register;
3468 VALUE_REGNUM (result) = regnum;
3470 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result);
3476 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3477 int regnum, const gdb_byte *buf)
3479 gdb_byte raw_buf[MAX_REGISTER_SIZE];
3481 if (i386_mmx_regnum_p (gdbarch, regnum))
3483 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3486 regcache_raw_read (regcache, fpnum, raw_buf);
3487 /* ... Modify ... (always little endian). */
3488 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
3490 regcache_raw_write (regcache, fpnum, raw_buf);
3494 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3496 if (i386_bnd_regnum_p (gdbarch, regnum))
3498 ULONGEST upper, lower;
3499 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3500 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3502 /* New values from input value. */
3503 regnum -= tdep->bnd0_regnum;
3504 lower = extract_unsigned_integer (buf, size, byte_order);
3505 upper = extract_unsigned_integer (buf + size, size, byte_order);
3507 /* Fetching register buffer. */
3508 regcache_raw_read (regcache,
3509 I387_BND0R_REGNUM (tdep) + regnum,
3514 /* Set register bits. */
3515 memcpy (raw_buf, &lower, 8);
3516 memcpy (raw_buf + 8, &upper, 8);
3519 regcache_raw_write (regcache,
3520 I387_BND0R_REGNUM (tdep) + regnum,
3523 else if (i386_k_regnum_p (gdbarch, regnum))
3525 regnum -= tdep->k0_regnum;
3527 regcache_raw_write (regcache,
3528 tdep->k0_regnum + regnum,
3531 else if (i386_zmm_regnum_p (gdbarch, regnum))
3533 regnum -= tdep->zmm0_regnum;
3535 if (regnum < num_lower_zmm_regs)
3537 /* Write lower 128bits. */
3538 regcache_raw_write (regcache,
3539 I387_XMM0_REGNUM (tdep) + regnum,
3541 /* Write upper 128bits. */
3542 regcache_raw_write (regcache,
3543 I387_YMM0_REGNUM (tdep) + regnum,
3548 /* Write lower 128bits. */
3549 regcache_raw_write (regcache,
3550 I387_XMM16_REGNUM (tdep) + regnum
3551 - num_lower_zmm_regs,
3553 /* Write upper 128bits. */
3554 regcache_raw_write (regcache,
3555 I387_YMM16H_REGNUM (tdep) + regnum
3556 - num_lower_zmm_regs,
3559 /* Write upper 256bits. */
3560 regcache_raw_write (regcache,
3561 tdep->zmm0h_regnum + regnum,
3564 else if (i386_ymm_regnum_p (gdbarch, regnum))
3566 regnum -= tdep->ymm0_regnum;
3568 /* ... Write lower 128bits. */
3569 regcache_raw_write (regcache,
3570 I387_XMM0_REGNUM (tdep) + regnum,
3572 /* ... Write upper 128bits. */
3573 regcache_raw_write (regcache,
3574 tdep->ymm0h_regnum + regnum,
3577 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3579 regnum -= tdep->ymm16_regnum;
3581 /* ... Write lower 128bits. */
3582 regcache_raw_write (regcache,
3583 I387_XMM16_REGNUM (tdep) + regnum,
3585 /* ... Write upper 128bits. */
3586 regcache_raw_write (regcache,
3587 tdep->ymm16h_regnum + regnum,
3590 else if (i386_word_regnum_p (gdbarch, regnum))
3592 int gpnum = regnum - tdep->ax_regnum;
3595 regcache_raw_read (regcache, gpnum, raw_buf);
3596 /* ... Modify ... (always little endian). */
3597 memcpy (raw_buf, buf, 2);
3599 regcache_raw_write (regcache, gpnum, raw_buf);
3601 else if (i386_byte_regnum_p (gdbarch, regnum))
3603 int gpnum = regnum - tdep->al_regnum;
3605 /* Read ... We read both lower and upper registers. */
3606 regcache_raw_read (regcache, gpnum % 4, raw_buf);
3607 /* ... Modify ... (always little endian). */
3609 memcpy (raw_buf + 1, buf, 1);
3611 memcpy (raw_buf, buf, 1);
3613 regcache_raw_write (regcache, gpnum % 4, raw_buf);
3616 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3620 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
3623 i386_ax_pseudo_register_collect (struct gdbarch *gdbarch,
3624 struct agent_expr *ax, int regnum)
3626 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3628 if (i386_mmx_regnum_p (gdbarch, regnum))
3630 /* MMX to FPU register mapping depends on current TOS. Let's just
3631 not care and collect everything... */
3634 ax_reg_mask (ax, I387_FSTAT_REGNUM (tdep));
3635 for (i = 0; i < 8; i++)
3636 ax_reg_mask (ax, I387_ST0_REGNUM (tdep) + i);
3639 else if (i386_bnd_regnum_p (gdbarch, regnum))
3641 regnum -= tdep->bnd0_regnum;
3642 ax_reg_mask (ax, I387_BND0R_REGNUM (tdep) + regnum);
3645 else if (i386_k_regnum_p (gdbarch, regnum))
3647 regnum -= tdep->k0_regnum;
3648 ax_reg_mask (ax, tdep->k0_regnum + regnum);
3651 else if (i386_zmm_regnum_p (gdbarch, regnum))
3653 regnum -= tdep->zmm0_regnum;
3654 if (regnum < num_lower_zmm_regs)
3656 ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum);
3657 ax_reg_mask (ax, tdep->ymm0h_regnum + regnum);
3661 ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum
3662 - num_lower_zmm_regs);
3663 ax_reg_mask (ax, I387_YMM16H_REGNUM (tdep) + regnum
3664 - num_lower_zmm_regs);
3666 ax_reg_mask (ax, tdep->zmm0h_regnum + regnum);
3669 else if (i386_ymm_regnum_p (gdbarch, regnum))
3671 regnum -= tdep->ymm0_regnum;
3672 ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum);
3673 ax_reg_mask (ax, tdep->ymm0h_regnum + regnum);
3676 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3678 regnum -= tdep->ymm16_regnum;
3679 ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum);
3680 ax_reg_mask (ax, tdep->ymm16h_regnum + regnum);
3683 else if (i386_word_regnum_p (gdbarch, regnum))
3685 int gpnum = regnum - tdep->ax_regnum;
3687 ax_reg_mask (ax, gpnum);
3690 else if (i386_byte_regnum_p (gdbarch, regnum))
3692 int gpnum = regnum - tdep->al_regnum;
3694 ax_reg_mask (ax, gpnum % 4);
3698 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3703 /* Return the register number of the register allocated by GCC after
3704 REGNUM, or -1 if there is no such register. */
3707 i386_next_regnum (int regnum)
3709 /* GCC allocates the registers in the order:
3711 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3713 Since storing a variable in %esp doesn't make any sense we return
3714 -1 for %ebp and for %esp itself. */
3715 static int next_regnum[] =
3717 I386_EDX_REGNUM, /* Slot for %eax. */
3718 I386_EBX_REGNUM, /* Slot for %ecx. */
3719 I386_ECX_REGNUM, /* Slot for %edx. */
3720 I386_ESI_REGNUM, /* Slot for %ebx. */
3721 -1, -1, /* Slots for %esp and %ebp. */
3722 I386_EDI_REGNUM, /* Slot for %esi. */
3723 I386_EBP_REGNUM /* Slot for %edi. */
3726 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
3727 return next_regnum[regnum];
3732 /* Return nonzero if a value of type TYPE stored in register REGNUM
3733 needs any special handling. */
3736 i386_convert_register_p (struct gdbarch *gdbarch,
3737 int regnum, struct type *type)
3739 int len = TYPE_LENGTH (type);
3741 /* Values may be spread across multiple registers. Most debugging
3742 formats aren't expressive enough to specify the locations, so
3743 some heuristics is involved. Right now we only handle types that
3744 have a length that is a multiple of the word size, since GCC
3745 doesn't seem to put any other types into registers. */
3746 if (len > 4 && len % 4 == 0)
3748 int last_regnum = regnum;
3752 last_regnum = i386_next_regnum (last_regnum);
3756 if (last_regnum != -1)
3760 return i387_convert_register_p (gdbarch, regnum, type);
3763 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3764 return its contents in TO. */
3767 i386_register_to_value (struct frame_info *frame, int regnum,
3768 struct type *type, gdb_byte *to,
3769 int *optimizedp, int *unavailablep)
3771 struct gdbarch *gdbarch = get_frame_arch (frame);
3772 int len = TYPE_LENGTH (type);
3774 if (i386_fp_regnum_p (gdbarch, regnum))
3775 return i387_register_to_value (frame, regnum, type, to,
3776 optimizedp, unavailablep);
3778 /* Read a value spread across multiple registers. */
3780 gdb_assert (len > 4 && len % 4 == 0);
3784 gdb_assert (regnum != -1);
3785 gdb_assert (register_size (gdbarch, regnum) == 4);
3787 if (!get_frame_register_bytes (frame, regnum, 0,
3788 register_size (gdbarch, regnum),
3789 to, optimizedp, unavailablep))
3792 regnum = i386_next_regnum (regnum);
3797 *optimizedp = *unavailablep = 0;
3801 /* Write the contents FROM of a value of type TYPE into register
3802 REGNUM in frame FRAME. */
3805 i386_value_to_register (struct frame_info *frame, int regnum,
3806 struct type *type, const gdb_byte *from)
3808 int len = TYPE_LENGTH (type);
3810 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
3812 i387_value_to_register (frame, regnum, type, from);
3816 /* Write a value spread across multiple registers. */
3818 gdb_assert (len > 4 && len % 4 == 0);
3822 gdb_assert (regnum != -1);
3823 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
3825 put_frame_register (frame, regnum, from);
3826 regnum = i386_next_regnum (regnum);
3832 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3833 in the general-purpose register set REGSET to register cache
3834 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3837 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
3838 int regnum, const void *gregs, size_t len)
3840 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3841 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3842 const gdb_byte *regs = (const gdb_byte *) gregs;
3845 gdb_assert (len >= tdep->sizeof_gregset);
3847 for (i = 0; i < tdep->gregset_num_regs; i++)
3849 if ((regnum == i || regnum == -1)
3850 && tdep->gregset_reg_offset[i] != -1)
3851 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
3855 /* Collect register REGNUM from the register cache REGCACHE and store
3856 it in the buffer specified by GREGS and LEN as described by the
3857 general-purpose register set REGSET. If REGNUM is -1, do this for
3858 all registers in REGSET. */
3861 i386_collect_gregset (const struct regset *regset,
3862 const struct regcache *regcache,
3863 int regnum, void *gregs, size_t len)
3865 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3866 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3867 gdb_byte *regs = (gdb_byte *) gregs;
3870 gdb_assert (len >= tdep->sizeof_gregset);
3872 for (i = 0; i < tdep->gregset_num_regs; i++)
3874 if ((regnum == i || regnum == -1)
3875 && tdep->gregset_reg_offset[i] != -1)
3876 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
3880 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3881 in the floating-point register set REGSET to register cache
3882 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3885 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
3886 int regnum, const void *fpregs, size_t len)
3888 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3889 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3891 if (len == I387_SIZEOF_FXSAVE)
3893 i387_supply_fxsave (regcache, regnum, fpregs);
3897 gdb_assert (len >= tdep->sizeof_fpregset);
3898 i387_supply_fsave (regcache, regnum, fpregs);
3901 /* Collect register REGNUM from the register cache REGCACHE and store
3902 it in the buffer specified by FPREGS and LEN as described by the
3903 floating-point register set REGSET. If REGNUM is -1, do this for
3904 all registers in REGSET. */
3907 i386_collect_fpregset (const struct regset *regset,
3908 const struct regcache *regcache,
3909 int regnum, void *fpregs, size_t len)
3911 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3912 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3914 if (len == I387_SIZEOF_FXSAVE)
3916 i387_collect_fxsave (regcache, regnum, fpregs);
3920 gdb_assert (len >= tdep->sizeof_fpregset);
3921 i387_collect_fsave (regcache, regnum, fpregs);
3924 /* Register set definitions. */
3926 const struct regset i386_gregset =
3928 NULL, i386_supply_gregset, i386_collect_gregset
3931 const struct regset i386_fpregset =
3933 NULL, i386_supply_fpregset, i386_collect_fpregset
3936 /* Default iterator over core file register note sections. */
3939 i386_iterate_over_regset_sections (struct gdbarch *gdbarch,
3940 iterate_over_regset_sections_cb *cb,
3942 const struct regcache *regcache)
3944 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3946 cb (".reg", tdep->sizeof_gregset, &i386_gregset, NULL, cb_data);
3947 if (tdep->sizeof_fpregset)
3948 cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
3952 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3955 i386_pe_skip_trampoline_code (struct frame_info *frame,
3956 CORE_ADDR pc, char *name)
3958 struct gdbarch *gdbarch = get_frame_arch (frame);
3959 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3962 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
3964 unsigned long indirect =
3965 read_memory_unsigned_integer (pc + 2, 4, byte_order);
3966 struct minimal_symbol *indsym =
3967 indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0;
3968 const char *symname = indsym ? MSYMBOL_LINKAGE_NAME (indsym) : 0;
3972 if (startswith (symname, "__imp_")
3973 || startswith (symname, "_imp_"))
3975 read_memory_unsigned_integer (indirect, 4, byte_order);
3978 return 0; /* Not a trampoline. */
3982 /* Return whether the THIS_FRAME corresponds to a sigtramp
3986 i386_sigtramp_p (struct frame_info *this_frame)
3988 CORE_ADDR pc = get_frame_pc (this_frame);
3991 find_pc_partial_function (pc, &name, NULL, NULL);
3992 return (name && strcmp ("_sigtramp", name) == 0);
3996 /* We have two flavours of disassembly. The machinery on this page
3997 deals with switching between those. */
4000 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
4002 gdb_assert (disassembly_flavor == att_flavor
4003 || disassembly_flavor == intel_flavor);
4005 /* FIXME: kettenis/20020915: Until disassembler_options is properly
4006 constified, cast to prevent a compiler warning. */
4007 info->disassembler_options = (char *) disassembly_flavor;
4009 return print_insn_i386 (pc, info);
4013 /* There are a few i386 architecture variants that differ only
4014 slightly from the generic i386 target. For now, we don't give them
4015 their own source file, but include them here. As a consequence,
4016 they'll always be included. */
4018 /* System V Release 4 (SVR4). */
4020 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
4024 i386_svr4_sigtramp_p (struct frame_info *this_frame)
4026 CORE_ADDR pc = get_frame_pc (this_frame);
4029 /* The origin of these symbols is currently unknown. */
4030 find_pc_partial_function (pc, &name, NULL, NULL);
4031 return (name && (strcmp ("_sigreturn", name) == 0
4032 || strcmp ("sigvechandler", name) == 0));
4035 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
4036 address of the associated sigcontext (ucontext) structure. */
4039 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
4041 struct gdbarch *gdbarch = get_frame_arch (this_frame);
4042 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4046 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
4047 sp = extract_unsigned_integer (buf, 4, byte_order);
4049 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
4054 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
4058 i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s)
4060 return (*s == '$' /* Literal number. */
4061 || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */
4062 || (*s == '(' && s[1] == '%') /* Register indirection. */
4063 || (*s == '%' && isalpha (s[1]))); /* Register access. */
4066 /* Helper function for i386_stap_parse_special_token.
4068 This function parses operands of the form `-8+3+1(%rbp)', which
4069 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
4071 Return 1 if the operand was parsed successfully, zero
4075 i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch,
4076 struct stap_parse_info *p)
4078 const char *s = p->arg;
4080 if (isdigit (*s) || *s == '-' || *s == '+')
4084 long displacements[3];
4100 if (!isdigit ((unsigned char) *s))
4103 displacements[0] = strtol (s, &endp, 10);
4106 if (*s != '+' && *s != '-')
4108 /* We are not dealing with a triplet. */
4121 if (!isdigit ((unsigned char) *s))
4124 displacements[1] = strtol (s, &endp, 10);
4127 if (*s != '+' && *s != '-')
4129 /* We are not dealing with a triplet. */
4142 if (!isdigit ((unsigned char) *s))
4145 displacements[2] = strtol (s, &endp, 10);
4148 if (*s != '(' || s[1] != '%')
4154 while (isalnum (*s))
4160 len = s - start - 1;
4161 regname = (char *) alloca (len + 1);
4163 strncpy (regname, start, len);
4164 regname[len] = '\0';
4166 if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1)
4167 error (_("Invalid register name `%s' on expression `%s'."),
4168 regname, p->saved_arg);
4170 for (i = 0; i < 3; i++)
4172 write_exp_elt_opcode (&p->pstate, OP_LONG);
4174 (&p->pstate, builtin_type (gdbarch)->builtin_long);
4175 write_exp_elt_longcst (&p->pstate, displacements[i]);
4176 write_exp_elt_opcode (&p->pstate, OP_LONG);
4178 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4181 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4184 write_exp_string (&p->pstate, str);
4185 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4187 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4188 write_exp_elt_type (&p->pstate,
4189 builtin_type (gdbarch)->builtin_data_ptr);
4190 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4192 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4193 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4194 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4196 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4197 write_exp_elt_type (&p->pstate,
4198 lookup_pointer_type (p->arg_type));
4199 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4201 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4211 /* Helper function for i386_stap_parse_special_token.
4213 This function parses operands of the form `register base +
4214 (register index * size) + offset', as represented in
4215 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4217 Return 1 if the operand was parsed successfully, zero
4221 i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch,
4222 struct stap_parse_info *p)
4224 const char *s = p->arg;
4226 if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+')
4228 int offset_minus = 0;
4237 struct stoken base_token, index_token;
4247 if (offset_minus && !isdigit (*s))
4254 offset = strtol (s, &endp, 10);
4258 if (*s != '(' || s[1] != '%')
4264 while (isalnum (*s))
4267 if (*s != ',' || s[1] != '%')
4270 len_base = s - start;
4271 base = (char *) alloca (len_base + 1);
4272 strncpy (base, start, len_base);
4273 base[len_base] = '\0';
4275 if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1)
4276 error (_("Invalid register name `%s' on expression `%s'."),
4277 base, p->saved_arg);
4282 while (isalnum (*s))
4285 len_index = s - start;
4286 index = (char *) alloca (len_index + 1);
4287 strncpy (index, start, len_index);
4288 index[len_index] = '\0';
4290 if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1)
4291 error (_("Invalid register name `%s' on expression `%s'."),
4292 index, p->saved_arg);
4294 if (*s != ',' && *s != ')')
4310 size = strtol (s, &endp, 10);
4321 write_exp_elt_opcode (&p->pstate, OP_LONG);
4322 write_exp_elt_type (&p->pstate,
4323 builtin_type (gdbarch)->builtin_long);
4324 write_exp_elt_longcst (&p->pstate, offset);
4325 write_exp_elt_opcode (&p->pstate, OP_LONG);
4327 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4330 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4331 base_token.ptr = base;
4332 base_token.length = len_base;
4333 write_exp_string (&p->pstate, base_token);
4334 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4337 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4339 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4340 index_token.ptr = index;
4341 index_token.length = len_index;
4342 write_exp_string (&p->pstate, index_token);
4343 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4347 write_exp_elt_opcode (&p->pstate, OP_LONG);
4348 write_exp_elt_type (&p->pstate,
4349 builtin_type (gdbarch)->builtin_long);
4350 write_exp_elt_longcst (&p->pstate, size);
4351 write_exp_elt_opcode (&p->pstate, OP_LONG);
4353 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4354 write_exp_elt_opcode (&p->pstate, BINOP_MUL);
4357 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4359 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4360 write_exp_elt_type (&p->pstate,
4361 lookup_pointer_type (p->arg_type));
4362 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4364 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4374 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4378 i386_stap_parse_special_token (struct gdbarch *gdbarch,
4379 struct stap_parse_info *p)
4381 /* In order to parse special tokens, we use a state-machine that go
4382 through every known token and try to get a match. */
4386 THREE_ARG_DISPLACEMENT,
4391 current_state = TRIPLET;
4393 /* The special tokens to be parsed here are:
4395 - `register base + (register index * size) + offset', as represented
4396 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4398 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4399 `*(-8 + 3 - 1 + (void *) $eax)'. */
4401 while (current_state != DONE)
4403 switch (current_state)
4406 if (i386_stap_parse_special_token_triplet (gdbarch, p))
4410 case THREE_ARG_DISPLACEMENT:
4411 if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p))
4416 /* Advancing to the next state. */
4425 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always
4426 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */
4429 i386_gnu_triplet_regexp (struct gdbarch *gdbarch)
4431 return "(x86_64|i.86)";
4439 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4441 static const char *const stap_integer_prefixes[] = { "$", NULL };
4442 static const char *const stap_register_prefixes[] = { "%", NULL };
4443 static const char *const stap_register_indirection_prefixes[] = { "(",
4445 static const char *const stap_register_indirection_suffixes[] = { ")",
4448 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4449 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4451 /* Registering SystemTap handlers. */
4452 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
4453 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
4454 set_gdbarch_stap_register_indirection_prefixes (gdbarch,
4455 stap_register_indirection_prefixes);
4456 set_gdbarch_stap_register_indirection_suffixes (gdbarch,
4457 stap_register_indirection_suffixes);
4458 set_gdbarch_stap_is_single_operand (gdbarch,
4459 i386_stap_is_single_operand);
4460 set_gdbarch_stap_parse_special_token (gdbarch,
4461 i386_stap_parse_special_token);
4463 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
4466 /* System V Release 4 (SVR4). */
4469 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4471 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4473 /* System V Release 4 uses ELF. */
4474 i386_elf_init_abi (info, gdbarch);
4476 /* System V Release 4 has shared libraries. */
4477 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
4479 tdep->sigtramp_p = i386_svr4_sigtramp_p;
4480 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
4481 tdep->sc_pc_offset = 36 + 14 * 4;
4482 tdep->sc_sp_offset = 36 + 17 * 4;
4484 tdep->jb_pc_offset = 20;
4490 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4492 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4494 /* DJGPP doesn't have any special frames for signal handlers. */
4495 tdep->sigtramp_p = NULL;
4497 tdep->jb_pc_offset = 36;
4499 /* DJGPP does not support the SSE registers. */
4500 if (! tdesc_has_registers (info.target_desc))
4501 tdep->tdesc = tdesc_i386_mmx;
4503 /* Native compiler is GCC, which uses the SVR4 register numbering
4504 even in COFF and STABS. See the comment in i386_gdbarch_init,
4505 before the calls to set_gdbarch_stab_reg_to_regnum and
4506 set_gdbarch_sdb_reg_to_regnum. */
4507 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4508 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4510 set_gdbarch_has_dos_based_file_system (gdbarch, 1);
4512 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
4516 /* i386 register groups. In addition to the normal groups, add "mmx"
4519 static struct reggroup *i386_sse_reggroup;
4520 static struct reggroup *i386_mmx_reggroup;
4523 i386_init_reggroups (void)
4525 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
4526 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
4530 i386_add_reggroups (struct gdbarch *gdbarch)
4532 reggroup_add (gdbarch, i386_sse_reggroup);
4533 reggroup_add (gdbarch, i386_mmx_reggroup);
4534 reggroup_add (gdbarch, general_reggroup);
4535 reggroup_add (gdbarch, float_reggroup);
4536 reggroup_add (gdbarch, all_reggroup);
4537 reggroup_add (gdbarch, save_reggroup);
4538 reggroup_add (gdbarch, restore_reggroup);
4539 reggroup_add (gdbarch, vector_reggroup);
4540 reggroup_add (gdbarch, system_reggroup);
4544 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
4545 struct reggroup *group)
4547 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4548 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
4549 ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p,
4550 bndr_regnum_p, bnd_regnum_p, k_regnum_p, zmm_regnum_p, zmmh_regnum_p,
4551 zmm_avx512_regnum_p, mpx_ctrl_regnum_p, xmm_avx512_regnum_p,
4552 avx512_p, avx_p, sse_p, pkru_regnum_p;
4554 /* Don't include pseudo registers, except for MMX, in any register
4556 if (i386_byte_regnum_p (gdbarch, regnum))
4559 if (i386_word_regnum_p (gdbarch, regnum))
4562 if (i386_dword_regnum_p (gdbarch, regnum))
4565 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
4566 if (group == i386_mmx_reggroup)
4567 return mmx_regnum_p;
4569 pkru_regnum_p = i386_pkru_regnum_p(gdbarch, regnum);
4570 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
4571 xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum);
4572 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
4573 if (group == i386_sse_reggroup)
4574 return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p;
4576 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
4577 ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum);
4578 zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum);
4580 avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK)
4581 == X86_XSTATE_AVX_AVX512_MASK);
4582 avx_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK)
4583 == X86_XSTATE_AVX_MASK) && !avx512_p;
4584 sse_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK)
4585 == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p;
4587 if (group == vector_reggroup)
4588 return (mmx_regnum_p
4589 || (zmm_regnum_p && avx512_p)
4590 || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p)
4591 || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p)
4594 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
4595 || i386_fpc_regnum_p (gdbarch, regnum));
4596 if (group == float_reggroup)
4599 /* For "info reg all", don't include upper YMM registers nor XMM
4600 registers when AVX is supported. */
4601 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
4602 ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum);
4603 zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum);
4604 if (group == all_reggroup
4605 && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p)
4606 || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p)
4608 || ymmh_avx512_regnum_p
4612 bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum);
4613 if (group == all_reggroup
4614 && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4615 return bnd_regnum_p;
4617 bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum);
4618 if (group == all_reggroup
4619 && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4622 mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum);
4623 if (group == all_reggroup
4624 && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4625 return mpx_ctrl_regnum_p;
4627 if (group == general_reggroup)
4628 return (!fp_regnum_p
4632 && !xmm_avx512_regnum_p
4635 && !ymm_avx512_regnum_p
4636 && !ymmh_avx512_regnum_p
4639 && !mpx_ctrl_regnum_p
4644 return default_register_reggroup_p (gdbarch, regnum, group);
4648 /* Get the ARGIth function argument for the current function. */
4651 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
4654 struct gdbarch *gdbarch = get_frame_arch (frame);
4655 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4656 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
4657 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
4660 #define PREFIX_REPZ 0x01
4661 #define PREFIX_REPNZ 0x02
4662 #define PREFIX_LOCK 0x04
4663 #define PREFIX_DATA 0x08
4664 #define PREFIX_ADDR 0x10
4676 /* i386 arith/logic operations */
4689 struct i386_record_s
4691 struct gdbarch *gdbarch;
4692 struct regcache *regcache;
4693 CORE_ADDR orig_addr;
4699 uint8_t mod, reg, rm;
4708 /* Parse the "modrm" part of the memory address irp->addr points at.
4709 Returns -1 if something goes wrong, 0 otherwise. */
4712 i386_record_modrm (struct i386_record_s *irp)
4714 struct gdbarch *gdbarch = irp->gdbarch;
4716 if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1))
4720 irp->mod = (irp->modrm >> 6) & 3;
4721 irp->reg = (irp->modrm >> 3) & 7;
4722 irp->rm = irp->modrm & 7;
4727 /* Extract the memory address that the current instruction writes to,
4728 and return it in *ADDR. Return -1 if something goes wrong. */
4731 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
4733 struct gdbarch *gdbarch = irp->gdbarch;
4734 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4739 if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM])
4746 uint8_t base = irp->rm;
4751 if (record_read_memory (gdbarch, irp->addr, &byte, 1))
4754 scale = (byte >> 6) & 3;
4755 index = ((byte >> 3) & 7) | irp->rex_x;
4763 if ((base & 7) == 5)
4766 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4769 *addr = extract_signed_integer (buf, 4, byte_order);
4770 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
4771 *addr += irp->addr + irp->rip_offset;
4775 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4778 *addr = (int8_t) buf[0];
4781 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4783 *addr = extract_signed_integer (buf, 4, byte_order);
4791 if (base == 4 && irp->popl_esp_hack)
4792 *addr += irp->popl_esp_hack;
4793 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
4796 if (irp->aflag == 2)
4801 *addr = (uint32_t) (offset64 + *addr);
4803 if (havesib && (index != 4 || scale != 0))
4805 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
4807 if (irp->aflag == 2)
4808 *addr += offset64 << scale;
4810 *addr = (uint32_t) (*addr + (offset64 << scale));
4815 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4816 address from 32-bit to 64-bit. */
4817 *addr = (uint32_t) *addr;
4828 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4831 *addr = extract_signed_integer (buf, 2, byte_order);
4837 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4840 *addr = (int8_t) buf[0];
4843 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4846 *addr = extract_signed_integer (buf, 2, byte_order);
4853 regcache_raw_read_unsigned (irp->regcache,
4854 irp->regmap[X86_RECORD_REBX_REGNUM],
4856 *addr = (uint32_t) (*addr + offset64);
4857 regcache_raw_read_unsigned (irp->regcache,
4858 irp->regmap[X86_RECORD_RESI_REGNUM],
4860 *addr = (uint32_t) (*addr + offset64);
4863 regcache_raw_read_unsigned (irp->regcache,
4864 irp->regmap[X86_RECORD_REBX_REGNUM],
4866 *addr = (uint32_t) (*addr + offset64);
4867 regcache_raw_read_unsigned (irp->regcache,
4868 irp->regmap[X86_RECORD_REDI_REGNUM],
4870 *addr = (uint32_t) (*addr + offset64);
4873 regcache_raw_read_unsigned (irp->regcache,
4874 irp->regmap[X86_RECORD_REBP_REGNUM],
4876 *addr = (uint32_t) (*addr + offset64);
4877 regcache_raw_read_unsigned (irp->regcache,
4878 irp->regmap[X86_RECORD_RESI_REGNUM],
4880 *addr = (uint32_t) (*addr + offset64);
4883 regcache_raw_read_unsigned (irp->regcache,
4884 irp->regmap[X86_RECORD_REBP_REGNUM],
4886 *addr = (uint32_t) (*addr + offset64);
4887 regcache_raw_read_unsigned (irp->regcache,
4888 irp->regmap[X86_RECORD_REDI_REGNUM],
4890 *addr = (uint32_t) (*addr + offset64);
4893 regcache_raw_read_unsigned (irp->regcache,
4894 irp->regmap[X86_RECORD_RESI_REGNUM],
4896 *addr = (uint32_t) (*addr + offset64);
4899 regcache_raw_read_unsigned (irp->regcache,
4900 irp->regmap[X86_RECORD_REDI_REGNUM],
4902 *addr = (uint32_t) (*addr + offset64);
4905 regcache_raw_read_unsigned (irp->regcache,
4906 irp->regmap[X86_RECORD_REBP_REGNUM],
4908 *addr = (uint32_t) (*addr + offset64);
4911 regcache_raw_read_unsigned (irp->regcache,
4912 irp->regmap[X86_RECORD_REBX_REGNUM],
4914 *addr = (uint32_t) (*addr + offset64);
4924 /* Record the address and contents of the memory that will be changed
4925 by the current instruction. Return -1 if something goes wrong, 0
4929 i386_record_lea_modrm (struct i386_record_s *irp)
4931 struct gdbarch *gdbarch = irp->gdbarch;
4934 if (irp->override >= 0)
4936 if (record_full_memory_query)
4939 Process record ignores the memory change of instruction at address %s\n\
4940 because it can't get the value of the segment register.\n\
4941 Do you want to stop the program?"),
4942 paddress (gdbarch, irp->orig_addr)))
4949 if (i386_record_lea_modrm_addr (irp, &addr))
4952 if (record_full_arch_list_add_mem (addr, 1 << irp->ot))
4958 /* Record the effects of a push operation. Return -1 if something
4959 goes wrong, 0 otherwise. */
4962 i386_record_push (struct i386_record_s *irp, int size)
4966 if (record_full_arch_list_add_reg (irp->regcache,
4967 irp->regmap[X86_RECORD_RESP_REGNUM]))
4969 regcache_raw_read_unsigned (irp->regcache,
4970 irp->regmap[X86_RECORD_RESP_REGNUM],
4972 if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size))
4979 /* Defines contents to record. */
4980 #define I386_SAVE_FPU_REGS 0xfffd
4981 #define I386_SAVE_FPU_ENV 0xfffe
4982 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4984 /* Record the values of the floating point registers which will be
4985 changed by the current instruction. Returns -1 if something is
4986 wrong, 0 otherwise. */
4988 static int i386_record_floats (struct gdbarch *gdbarch,
4989 struct i386_record_s *ir,
4992 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4995 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4996 happen. Currently we store st0-st7 registers, but we need not store all
4997 registers all the time, in future we use ftag register and record only
4998 those who are not marked as an empty. */
5000 if (I386_SAVE_FPU_REGS == iregnum)
5002 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
5004 if (record_full_arch_list_add_reg (ir->regcache, i))
5008 else if (I386_SAVE_FPU_ENV == iregnum)
5010 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
5012 if (record_full_arch_list_add_reg (ir->regcache, i))
5016 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
5018 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
5020 if (record_full_arch_list_add_reg (ir->regcache, i))
5024 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
5025 (iregnum <= I387_FOP_REGNUM (tdep)))
5027 if (record_full_arch_list_add_reg (ir->regcache,iregnum))
5032 /* Parameter error. */
5035 if(I386_SAVE_FPU_ENV != iregnum)
5037 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
5039 if (record_full_arch_list_add_reg (ir->regcache, i))
5046 /* Parse the current instruction, and record the values of the
5047 registers and memory that will be changed by the current
5048 instruction. Returns -1 if something goes wrong, 0 otherwise. */
5050 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
5051 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
5054 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
5055 CORE_ADDR input_addr)
5057 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5063 gdb_byte buf[MAX_REGISTER_SIZE];
5064 struct i386_record_s ir;
5065 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5069 memset (&ir, 0, sizeof (struct i386_record_s));
5070 ir.regcache = regcache;
5071 ir.addr = input_addr;
5072 ir.orig_addr = input_addr;
5076 ir.popl_esp_hack = 0;
5077 ir.regmap = tdep->record_regmap;
5078 ir.gdbarch = gdbarch;
5080 if (record_debug > 1)
5081 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
5083 paddress (gdbarch, ir.addr));
5088 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5091 switch (opcode8) /* Instruction prefixes */
5093 case REPE_PREFIX_OPCODE:
5094 prefixes |= PREFIX_REPZ;
5096 case REPNE_PREFIX_OPCODE:
5097 prefixes |= PREFIX_REPNZ;
5099 case LOCK_PREFIX_OPCODE:
5100 prefixes |= PREFIX_LOCK;
5102 case CS_PREFIX_OPCODE:
5103 ir.override = X86_RECORD_CS_REGNUM;
5105 case SS_PREFIX_OPCODE:
5106 ir.override = X86_RECORD_SS_REGNUM;
5108 case DS_PREFIX_OPCODE:
5109 ir.override = X86_RECORD_DS_REGNUM;
5111 case ES_PREFIX_OPCODE:
5112 ir.override = X86_RECORD_ES_REGNUM;
5114 case FS_PREFIX_OPCODE:
5115 ir.override = X86_RECORD_FS_REGNUM;
5117 case GS_PREFIX_OPCODE:
5118 ir.override = X86_RECORD_GS_REGNUM;
5120 case DATA_PREFIX_OPCODE:
5121 prefixes |= PREFIX_DATA;
5123 case ADDR_PREFIX_OPCODE:
5124 prefixes |= PREFIX_ADDR;
5126 case 0x40: /* i386 inc %eax */
5127 case 0x41: /* i386 inc %ecx */
5128 case 0x42: /* i386 inc %edx */
5129 case 0x43: /* i386 inc %ebx */
5130 case 0x44: /* i386 inc %esp */
5131 case 0x45: /* i386 inc %ebp */
5132 case 0x46: /* i386 inc %esi */
5133 case 0x47: /* i386 inc %edi */
5134 case 0x48: /* i386 dec %eax */
5135 case 0x49: /* i386 dec %ecx */
5136 case 0x4a: /* i386 dec %edx */
5137 case 0x4b: /* i386 dec %ebx */
5138 case 0x4c: /* i386 dec %esp */
5139 case 0x4d: /* i386 dec %ebp */
5140 case 0x4e: /* i386 dec %esi */
5141 case 0x4f: /* i386 dec %edi */
5142 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
5145 rex_w = (opcode8 >> 3) & 1;
5146 rex_r = (opcode8 & 0x4) << 1;
5147 ir.rex_x = (opcode8 & 0x2) << 2;
5148 ir.rex_b = (opcode8 & 0x1) << 3;
5150 else /* 32 bit target */
5159 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
5165 if (prefixes & PREFIX_DATA)
5168 if (prefixes & PREFIX_ADDR)
5170 else if (ir.regmap[X86_RECORD_R8_REGNUM])
5173 /* Now check op code. */
5174 opcode = (uint32_t) opcode8;
5179 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5182 opcode = (uint32_t) opcode8 | 0x0f00;
5186 case 0x00: /* arith & logic */
5234 if (((opcode >> 3) & 7) != OP_CMPL)
5236 if ((opcode & 1) == 0)
5239 ir.ot = ir.dflag + OT_WORD;
5241 switch ((opcode >> 1) & 3)
5243 case 0: /* OP Ev, Gv */
5244 if (i386_record_modrm (&ir))
5248 if (i386_record_lea_modrm (&ir))
5254 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5256 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5259 case 1: /* OP Gv, Ev */
5260 if (i386_record_modrm (&ir))
5263 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5265 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5267 case 2: /* OP A, Iv */
5268 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5272 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5275 case 0x80: /* GRP1 */
5279 if (i386_record_modrm (&ir))
5282 if (ir.reg != OP_CMPL)
5284 if ((opcode & 1) == 0)
5287 ir.ot = ir.dflag + OT_WORD;
5294 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5295 if (i386_record_lea_modrm (&ir))
5299 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5301 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5304 case 0x40: /* inc */
5313 case 0x48: /* dec */
5322 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7);
5323 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5326 case 0xf6: /* GRP3 */
5328 if ((opcode & 1) == 0)
5331 ir.ot = ir.dflag + OT_WORD;
5332 if (i386_record_modrm (&ir))
5335 if (ir.mod != 3 && ir.reg == 0)
5336 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5341 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5347 if (i386_record_lea_modrm (&ir))
5353 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5355 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5357 if (ir.reg == 3) /* neg */
5358 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5364 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5365 if (ir.ot != OT_BYTE)
5366 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5367 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5371 opcode = opcode << 8 | ir.modrm;
5377 case 0xfe: /* GRP4 */
5378 case 0xff: /* GRP5 */
5379 if (i386_record_modrm (&ir))
5381 if (ir.reg >= 2 && opcode == 0xfe)
5384 opcode = opcode << 8 | ir.modrm;
5391 if ((opcode & 1) == 0)
5394 ir.ot = ir.dflag + OT_WORD;
5397 if (i386_record_lea_modrm (&ir))
5403 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5405 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5407 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5410 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5412 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5414 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5417 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5418 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5420 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5424 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5427 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5429 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5434 opcode = opcode << 8 | ir.modrm;
5440 case 0x84: /* test */
5444 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5447 case 0x98: /* CWDE/CBW */
5448 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5451 case 0x99: /* CDQ/CWD */
5452 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5453 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5456 case 0x0faf: /* imul */
5459 ir.ot = ir.dflag + OT_WORD;
5460 if (i386_record_modrm (&ir))
5463 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5464 else if (opcode == 0x6b)
5467 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5469 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5470 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5473 case 0x0fc0: /* xadd */
5475 if ((opcode & 1) == 0)
5478 ir.ot = ir.dflag + OT_WORD;
5479 if (i386_record_modrm (&ir))
5484 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5486 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5487 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5489 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5493 if (i386_record_lea_modrm (&ir))
5495 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5497 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5499 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5502 case 0x0fb0: /* cmpxchg */
5504 if ((opcode & 1) == 0)
5507 ir.ot = ir.dflag + OT_WORD;
5508 if (i386_record_modrm (&ir))
5513 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5514 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5516 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5520 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5521 if (i386_record_lea_modrm (&ir))
5524 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5527 case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */
5528 if (i386_record_modrm (&ir))
5532 /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as
5533 an extended opcode. rdrand has bits 110 (/6) and rdseed
5534 has bits 111 (/7). */
5535 if (ir.reg == 6 || ir.reg == 7)
5537 /* The storage register is described by the 3 R/M bits, but the
5538 REX.B prefix may be used to give access to registers
5539 R8~R15. In this case ir.rex_b + R/M will give us the register
5540 in the range R8~R15.
5542 REX.W may also be used to access 64-bit registers, but we
5543 already record entire registers and not just partial bits
5545 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b + ir.rm);
5546 /* These instructions also set conditional bits. */
5547 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5552 /* We don't handle this particular instruction yet. */
5554 opcode = opcode << 8 | ir.modrm;
5558 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5559 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5560 if (i386_record_lea_modrm (&ir))
5562 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5565 case 0x50: /* push */
5575 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5577 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5581 case 0x06: /* push es */
5582 case 0x0e: /* push cs */
5583 case 0x16: /* push ss */
5584 case 0x1e: /* push ds */
5585 if (ir.regmap[X86_RECORD_R8_REGNUM])
5590 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5594 case 0x0fa0: /* push fs */
5595 case 0x0fa8: /* push gs */
5596 if (ir.regmap[X86_RECORD_R8_REGNUM])
5601 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5605 case 0x60: /* pusha */
5606 if (ir.regmap[X86_RECORD_R8_REGNUM])
5611 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
5615 case 0x58: /* pop */
5623 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5624 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5627 case 0x61: /* popa */
5628 if (ir.regmap[X86_RECORD_R8_REGNUM])
5633 for (regnum = X86_RECORD_REAX_REGNUM;
5634 regnum <= X86_RECORD_REDI_REGNUM;
5636 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5639 case 0x8f: /* pop */
5640 if (ir.regmap[X86_RECORD_R8_REGNUM])
5641 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
5643 ir.ot = ir.dflag + OT_WORD;
5644 if (i386_record_modrm (&ir))
5647 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5650 ir.popl_esp_hack = 1 << ir.ot;
5651 if (i386_record_lea_modrm (&ir))
5654 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5657 case 0xc8: /* enter */
5658 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5659 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5661 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5665 case 0xc9: /* leave */
5666 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5667 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5670 case 0x07: /* pop es */
5671 if (ir.regmap[X86_RECORD_R8_REGNUM])
5676 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5677 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
5678 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5681 case 0x17: /* pop ss */
5682 if (ir.regmap[X86_RECORD_R8_REGNUM])
5687 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5688 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
5689 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5692 case 0x1f: /* pop ds */
5693 if (ir.regmap[X86_RECORD_R8_REGNUM])
5698 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5699 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
5700 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5703 case 0x0fa1: /* pop fs */
5704 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5705 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
5706 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5709 case 0x0fa9: /* pop gs */
5710 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5711 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
5712 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5715 case 0x88: /* mov */
5719 if ((opcode & 1) == 0)
5722 ir.ot = ir.dflag + OT_WORD;
5724 if (i386_record_modrm (&ir))
5729 if (opcode == 0xc6 || opcode == 0xc7)
5730 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5731 if (i386_record_lea_modrm (&ir))
5736 if (opcode == 0xc6 || opcode == 0xc7)
5738 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5740 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5744 case 0x8a: /* mov */
5746 if ((opcode & 1) == 0)
5749 ir.ot = ir.dflag + OT_WORD;
5750 if (i386_record_modrm (&ir))
5753 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5755 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5758 case 0x8c: /* mov seg */
5759 if (i386_record_modrm (&ir))
5764 opcode = opcode << 8 | ir.modrm;
5769 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5773 if (i386_record_lea_modrm (&ir))
5778 case 0x8e: /* mov seg */
5779 if (i386_record_modrm (&ir))
5784 regnum = X86_RECORD_ES_REGNUM;
5787 regnum = X86_RECORD_SS_REGNUM;
5790 regnum = X86_RECORD_DS_REGNUM;
5793 regnum = X86_RECORD_FS_REGNUM;
5796 regnum = X86_RECORD_GS_REGNUM;
5800 opcode = opcode << 8 | ir.modrm;
5804 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5805 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5808 case 0x0fb6: /* movzbS */
5809 case 0x0fb7: /* movzwS */
5810 case 0x0fbe: /* movsbS */
5811 case 0x0fbf: /* movswS */
5812 if (i386_record_modrm (&ir))
5814 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5817 case 0x8d: /* lea */
5818 if (i386_record_modrm (&ir))
5823 opcode = opcode << 8 | ir.modrm;
5828 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5830 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5833 case 0xa0: /* mov EAX */
5836 case 0xd7: /* xlat */
5837 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5840 case 0xa2: /* mov EAX */
5842 if (ir.override >= 0)
5844 if (record_full_memory_query)
5847 Process record ignores the memory change of instruction at address %s\n\
5848 because it can't get the value of the segment register.\n\
5849 Do you want to stop the program?"),
5850 paddress (gdbarch, ir.orig_addr)))
5856 if ((opcode & 1) == 0)
5859 ir.ot = ir.dflag + OT_WORD;
5862 if (record_read_memory (gdbarch, ir.addr, buf, 8))
5865 addr = extract_unsigned_integer (buf, 8, byte_order);
5869 if (record_read_memory (gdbarch, ir.addr, buf, 4))
5872 addr = extract_unsigned_integer (buf, 4, byte_order);
5876 if (record_read_memory (gdbarch, ir.addr, buf, 2))
5879 addr = extract_unsigned_integer (buf, 2, byte_order);
5881 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
5886 case 0xb0: /* mov R, Ib */
5894 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
5895 ? ((opcode & 0x7) | ir.rex_b)
5896 : ((opcode & 0x7) & 0x3));
5899 case 0xb8: /* mov R, Iv */
5907 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5910 case 0x91: /* xchg R, EAX */
5917 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5918 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7);
5921 case 0x86: /* xchg Ev, Gv */
5923 if ((opcode & 1) == 0)
5926 ir.ot = ir.dflag + OT_WORD;
5927 if (i386_record_modrm (&ir))
5932 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5934 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5938 if (i386_record_lea_modrm (&ir))
5942 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5944 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5947 case 0xc4: /* les Gv */
5948 case 0xc5: /* lds Gv */
5949 if (ir.regmap[X86_RECORD_R8_REGNUM])
5955 case 0x0fb2: /* lss Gv */
5956 case 0x0fb4: /* lfs Gv */
5957 case 0x0fb5: /* lgs Gv */
5958 if (i386_record_modrm (&ir))
5966 opcode = opcode << 8 | ir.modrm;
5971 case 0xc4: /* les Gv */
5972 regnum = X86_RECORD_ES_REGNUM;
5974 case 0xc5: /* lds Gv */
5975 regnum = X86_RECORD_DS_REGNUM;
5977 case 0x0fb2: /* lss Gv */
5978 regnum = X86_RECORD_SS_REGNUM;
5980 case 0x0fb4: /* lfs Gv */
5981 regnum = X86_RECORD_FS_REGNUM;
5983 case 0x0fb5: /* lgs Gv */
5984 regnum = X86_RECORD_GS_REGNUM;
5987 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5988 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5989 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5992 case 0xc0: /* shifts */
5998 if ((opcode & 1) == 0)
6001 ir.ot = ir.dflag + OT_WORD;
6002 if (i386_record_modrm (&ir))
6004 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
6006 if (i386_record_lea_modrm (&ir))
6012 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
6014 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
6016 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6023 if (i386_record_modrm (&ir))
6027 if (record_full_arch_list_add_reg (ir.regcache, ir.rm))
6032 if (i386_record_lea_modrm (&ir))
6037 case 0xd8: /* Floats. */
6045 if (i386_record_modrm (&ir))
6047 ir.reg |= ((opcode & 7) << 3);
6053 if (i386_record_lea_modrm_addr (&ir, &addr64))
6061 /* For fcom, ficom nothing to do. */
6067 /* For fcomp, ficomp pop FPU stack, store all. */
6068 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6095 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
6096 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
6097 of code, always affects st(0) register. */
6098 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6122 /* Handling fld, fild. */
6123 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6127 switch (ir.reg >> 4)
6130 if (record_full_arch_list_add_mem (addr64, 4))
6134 if (record_full_arch_list_add_mem (addr64, 8))
6140 if (record_full_arch_list_add_mem (addr64, 2))
6146 switch (ir.reg >> 4)
6149 if (record_full_arch_list_add_mem (addr64, 4))
6151 if (3 == (ir.reg & 7))
6153 /* For fstp m32fp. */
6154 if (i386_record_floats (gdbarch, &ir,
6155 I386_SAVE_FPU_REGS))
6160 if (record_full_arch_list_add_mem (addr64, 4))
6162 if ((3 == (ir.reg & 7))
6163 || (5 == (ir.reg & 7))
6164 || (7 == (ir.reg & 7)))
6166 /* For fstp insn. */
6167 if (i386_record_floats (gdbarch, &ir,
6168 I386_SAVE_FPU_REGS))
6173 if (record_full_arch_list_add_mem (addr64, 8))
6175 if (3 == (ir.reg & 7))
6177 /* For fstp m64fp. */
6178 if (i386_record_floats (gdbarch, &ir,
6179 I386_SAVE_FPU_REGS))
6184 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
6186 /* For fistp, fbld, fild, fbstp. */
6187 if (i386_record_floats (gdbarch, &ir,
6188 I386_SAVE_FPU_REGS))
6193 if (record_full_arch_list_add_mem (addr64, 2))
6202 if (i386_record_floats (gdbarch, &ir,
6203 I386_SAVE_FPU_ENV_REG_STACK))
6208 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
6213 if (i386_record_floats (gdbarch, &ir,
6214 I386_SAVE_FPU_ENV_REG_STACK))
6220 if (record_full_arch_list_add_mem (addr64, 28))
6225 if (record_full_arch_list_add_mem (addr64, 14))
6231 if (record_full_arch_list_add_mem (addr64, 2))
6233 /* Insn fstp, fbstp. */
6234 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6239 if (record_full_arch_list_add_mem (addr64, 10))
6245 if (record_full_arch_list_add_mem (addr64, 28))
6251 if (record_full_arch_list_add_mem (addr64, 14))
6255 if (record_full_arch_list_add_mem (addr64, 80))
6258 if (i386_record_floats (gdbarch, &ir,
6259 I386_SAVE_FPU_ENV_REG_STACK))
6263 if (record_full_arch_list_add_mem (addr64, 8))
6266 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6271 opcode = opcode << 8 | ir.modrm;
6276 /* Opcode is an extension of modR/M byte. */
6282 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6286 if (0x0c == (ir.modrm >> 4))
6288 if ((ir.modrm & 0x0f) <= 7)
6290 if (i386_record_floats (gdbarch, &ir,
6291 I386_SAVE_FPU_REGS))
6296 if (i386_record_floats (gdbarch, &ir,
6297 I387_ST0_REGNUM (tdep)))
6299 /* If only st(0) is changing, then we have already
6301 if ((ir.modrm & 0x0f) - 0x08)
6303 if (i386_record_floats (gdbarch, &ir,
6304 I387_ST0_REGNUM (tdep) +
6305 ((ir.modrm & 0x0f) - 0x08)))
6323 if (i386_record_floats (gdbarch, &ir,
6324 I387_ST0_REGNUM (tdep)))
6342 if (i386_record_floats (gdbarch, &ir,
6343 I386_SAVE_FPU_REGS))
6347 if (i386_record_floats (gdbarch, &ir,
6348 I387_ST0_REGNUM (tdep)))
6350 if (i386_record_floats (gdbarch, &ir,
6351 I387_ST0_REGNUM (tdep) + 1))
6358 if (0xe9 == ir.modrm)
6360 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6363 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6365 if (i386_record_floats (gdbarch, &ir,
6366 I387_ST0_REGNUM (tdep)))
6368 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6370 if (i386_record_floats (gdbarch, &ir,
6371 I387_ST0_REGNUM (tdep) +
6375 else if ((ir.modrm & 0x0f) - 0x08)
6377 if (i386_record_floats (gdbarch, &ir,
6378 I387_ST0_REGNUM (tdep) +
6379 ((ir.modrm & 0x0f) - 0x08)))
6385 if (0xe3 == ir.modrm)
6387 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
6390 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6392 if (i386_record_floats (gdbarch, &ir,
6393 I387_ST0_REGNUM (tdep)))
6395 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6397 if (i386_record_floats (gdbarch, &ir,
6398 I387_ST0_REGNUM (tdep) +
6402 else if ((ir.modrm & 0x0f) - 0x08)
6404 if (i386_record_floats (gdbarch, &ir,
6405 I387_ST0_REGNUM (tdep) +
6406 ((ir.modrm & 0x0f) - 0x08)))
6412 if ((0x0c == ir.modrm >> 4)
6413 || (0x0d == ir.modrm >> 4)
6414 || (0x0f == ir.modrm >> 4))
6416 if ((ir.modrm & 0x0f) <= 7)
6418 if (i386_record_floats (gdbarch, &ir,
6419 I387_ST0_REGNUM (tdep) +
6425 if (i386_record_floats (gdbarch, &ir,
6426 I387_ST0_REGNUM (tdep) +
6427 ((ir.modrm & 0x0f) - 0x08)))
6433 if (0x0c == ir.modrm >> 4)
6435 if (i386_record_floats (gdbarch, &ir,
6436 I387_FTAG_REGNUM (tdep)))
6439 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6441 if ((ir.modrm & 0x0f) <= 7)
6443 if (i386_record_floats (gdbarch, &ir,
6444 I387_ST0_REGNUM (tdep) +
6450 if (i386_record_floats (gdbarch, &ir,
6451 I386_SAVE_FPU_REGS))
6457 if ((0x0c == ir.modrm >> 4)
6458 || (0x0e == ir.modrm >> 4)
6459 || (0x0f == ir.modrm >> 4)
6460 || (0xd9 == ir.modrm))
6462 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6467 if (0xe0 == ir.modrm)
6469 if (record_full_arch_list_add_reg (ir.regcache,
6473 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6475 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6483 case 0xa4: /* movsS */
6485 case 0xaa: /* stosS */
6487 case 0x6c: /* insS */
6489 regcache_raw_read_unsigned (ir.regcache,
6490 ir.regmap[X86_RECORD_RECX_REGNUM],
6496 if ((opcode & 1) == 0)
6499 ir.ot = ir.dflag + OT_WORD;
6500 regcache_raw_read_unsigned (ir.regcache,
6501 ir.regmap[X86_RECORD_REDI_REGNUM],
6504 regcache_raw_read_unsigned (ir.regcache,
6505 ir.regmap[X86_RECORD_ES_REGNUM],
6507 regcache_raw_read_unsigned (ir.regcache,
6508 ir.regmap[X86_RECORD_DS_REGNUM],
6510 if (ir.aflag && (es != ds))
6512 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6513 if (record_full_memory_query)
6516 Process record ignores the memory change of instruction at address %s\n\
6517 because it can't get the value of the segment register.\n\
6518 Do you want to stop the program?"),
6519 paddress (gdbarch, ir.orig_addr)))
6525 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
6529 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6530 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6531 if (opcode == 0xa4 || opcode == 0xa5)
6532 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6533 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6534 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6538 case 0xa6: /* cmpsS */
6540 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6541 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6542 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6543 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6544 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6547 case 0xac: /* lodsS */
6549 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6550 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6551 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6552 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6553 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6556 case 0xae: /* scasS */
6558 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6559 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6560 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6561 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6564 case 0x6e: /* outsS */
6566 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6567 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6568 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6569 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6572 case 0xe4: /* port I/O */
6576 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6577 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6587 case 0xc2: /* ret im */
6588 case 0xc3: /* ret */
6589 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6590 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6593 case 0xca: /* lret im */
6594 case 0xcb: /* lret */
6595 case 0xcf: /* iret */
6596 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6597 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6598 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6601 case 0xe8: /* call im */
6602 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6604 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6608 case 0x9a: /* lcall im */
6609 if (ir.regmap[X86_RECORD_R8_REGNUM])
6614 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6615 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6619 case 0xe9: /* jmp im */
6620 case 0xea: /* ljmp im */
6621 case 0xeb: /* jmp Jb */
6622 case 0x70: /* jcc Jb */
6638 case 0x0f80: /* jcc Jv */
6656 case 0x0f90: /* setcc Gv */
6672 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6674 if (i386_record_modrm (&ir))
6677 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
6681 if (i386_record_lea_modrm (&ir))
6686 case 0x0f40: /* cmov Gv, Ev */
6702 if (i386_record_modrm (&ir))
6705 if (ir.dflag == OT_BYTE)
6707 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
6711 case 0x9c: /* pushf */
6712 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6713 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6715 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6719 case 0x9d: /* popf */
6720 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6721 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6724 case 0x9e: /* sahf */
6725 if (ir.regmap[X86_RECORD_R8_REGNUM])
6731 case 0xf5: /* cmc */
6732 case 0xf8: /* clc */
6733 case 0xf9: /* stc */
6734 case 0xfc: /* cld */
6735 case 0xfd: /* std */
6736 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6739 case 0x9f: /* lahf */
6740 if (ir.regmap[X86_RECORD_R8_REGNUM])
6745 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6746 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6749 /* bit operations */
6750 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6751 ir.ot = ir.dflag + OT_WORD;
6752 if (i386_record_modrm (&ir))
6757 opcode = opcode << 8 | ir.modrm;
6763 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6766 if (i386_record_lea_modrm (&ir))
6770 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6773 case 0x0fa3: /* bt Gv, Ev */
6774 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6777 case 0x0fab: /* bts */
6778 case 0x0fb3: /* btr */
6779 case 0x0fbb: /* btc */
6780 ir.ot = ir.dflag + OT_WORD;
6781 if (i386_record_modrm (&ir))
6784 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6788 if (i386_record_lea_modrm_addr (&ir, &addr64))
6790 regcache_raw_read_unsigned (ir.regcache,
6791 ir.regmap[ir.reg | rex_r],
6796 addr64 += ((int16_t) addr >> 4) << 4;
6799 addr64 += ((int32_t) addr >> 5) << 5;
6802 addr64 += ((int64_t) addr >> 6) << 6;
6805 if (record_full_arch_list_add_mem (addr64, 1 << ir.ot))
6807 if (i386_record_lea_modrm (&ir))
6810 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6813 case 0x0fbc: /* bsf */
6814 case 0x0fbd: /* bsr */
6815 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6816 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6820 case 0x27: /* daa */
6821 case 0x2f: /* das */
6822 case 0x37: /* aaa */
6823 case 0x3f: /* aas */
6824 case 0xd4: /* aam */
6825 case 0xd5: /* aad */
6826 if (ir.regmap[X86_RECORD_R8_REGNUM])
6831 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6832 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6836 case 0x90: /* nop */
6837 if (prefixes & PREFIX_LOCK)
6844 case 0x9b: /* fwait */
6845 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
6847 opcode = (uint32_t) opcode8;
6853 case 0xcc: /* int3 */
6854 printf_unfiltered (_("Process record does not support instruction "
6861 case 0xcd: /* int */
6865 if (record_read_memory (gdbarch, ir.addr, &interrupt, 1))
6868 if (interrupt != 0x80
6869 || tdep->i386_intx80_record == NULL)
6871 printf_unfiltered (_("Process record does not support "
6872 "instruction int 0x%02x.\n"),
6877 ret = tdep->i386_intx80_record (ir.regcache);
6884 case 0xce: /* into */
6885 printf_unfiltered (_("Process record does not support "
6886 "instruction into.\n"));
6891 case 0xfa: /* cli */
6892 case 0xfb: /* sti */
6895 case 0x62: /* bound */
6896 printf_unfiltered (_("Process record does not support "
6897 "instruction bound.\n"));
6902 case 0x0fc8: /* bswap reg */
6910 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
6913 case 0xd6: /* salc */
6914 if (ir.regmap[X86_RECORD_R8_REGNUM])
6919 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6920 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6923 case 0xe0: /* loopnz */
6924 case 0xe1: /* loopz */
6925 case 0xe2: /* loop */
6926 case 0xe3: /* jecxz */
6927 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6928 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6931 case 0x0f30: /* wrmsr */
6932 printf_unfiltered (_("Process record does not support "
6933 "instruction wrmsr.\n"));
6938 case 0x0f32: /* rdmsr */
6939 printf_unfiltered (_("Process record does not support "
6940 "instruction rdmsr.\n"));
6945 case 0x0f31: /* rdtsc */
6946 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6947 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6950 case 0x0f34: /* sysenter */
6953 if (ir.regmap[X86_RECORD_R8_REGNUM])
6958 if (tdep->i386_sysenter_record == NULL)
6960 printf_unfiltered (_("Process record does not support "
6961 "instruction sysenter.\n"));
6965 ret = tdep->i386_sysenter_record (ir.regcache);
6971 case 0x0f35: /* sysexit */
6972 printf_unfiltered (_("Process record does not support "
6973 "instruction sysexit.\n"));
6978 case 0x0f05: /* syscall */
6981 if (tdep->i386_syscall_record == NULL)
6983 printf_unfiltered (_("Process record does not support "
6984 "instruction syscall.\n"));
6988 ret = tdep->i386_syscall_record (ir.regcache);
6994 case 0x0f07: /* sysret */
6995 printf_unfiltered (_("Process record does not support "
6996 "instruction sysret.\n"));
7001 case 0x0fa2: /* cpuid */
7002 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7003 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
7004 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7005 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
7008 case 0xf4: /* hlt */
7009 printf_unfiltered (_("Process record does not support "
7010 "instruction hlt.\n"));
7016 if (i386_record_modrm (&ir))
7023 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7027 if (i386_record_lea_modrm (&ir))
7036 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7040 opcode = opcode << 8 | ir.modrm;
7047 if (i386_record_modrm (&ir))
7058 opcode = opcode << 8 | ir.modrm;
7061 if (ir.override >= 0)
7063 if (record_full_memory_query)
7066 Process record ignores the memory change of instruction at address %s\n\
7067 because it can't get the value of the segment register.\n\
7068 Do you want to stop the program?"),
7069 paddress (gdbarch, ir.orig_addr)))
7075 if (i386_record_lea_modrm_addr (&ir, &addr64))
7077 if (record_full_arch_list_add_mem (addr64, 2))
7080 if (ir.regmap[X86_RECORD_R8_REGNUM])
7082 if (record_full_arch_list_add_mem (addr64, 8))
7087 if (record_full_arch_list_add_mem (addr64, 4))
7098 case 0: /* monitor */
7101 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7105 opcode = opcode << 8 | ir.modrm;
7113 if (ir.override >= 0)
7115 if (record_full_memory_query)
7118 Process record ignores the memory change of instruction at address %s\n\
7119 because it can't get the value of the segment register.\n\
7120 Do you want to stop the program?"),
7121 paddress (gdbarch, ir.orig_addr)))
7129 if (i386_record_lea_modrm_addr (&ir, &addr64))
7131 if (record_full_arch_list_add_mem (addr64, 2))
7134 if (ir.regmap[X86_RECORD_R8_REGNUM])
7136 if (record_full_arch_list_add_mem (addr64, 8))
7141 if (record_full_arch_list_add_mem (addr64, 4))
7153 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7154 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7158 else if (ir.rm == 1)
7165 opcode = opcode << 8 | ir.modrm;
7172 if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
7178 if (i386_record_lea_modrm (&ir))
7181 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7184 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7186 case 7: /* invlpg */
7189 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
7190 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
7194 opcode = opcode << 8 | ir.modrm;
7199 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7203 opcode = opcode << 8 | ir.modrm;
7209 case 0x0f08: /* invd */
7210 case 0x0f09: /* wbinvd */
7213 case 0x63: /* arpl */
7214 if (i386_record_modrm (&ir))
7216 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
7218 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
7219 ? (ir.reg | rex_r) : ir.rm);
7223 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
7224 if (i386_record_lea_modrm (&ir))
7227 if (!ir.regmap[X86_RECORD_R8_REGNUM])
7228 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7231 case 0x0f02: /* lar */
7232 case 0x0f03: /* lsl */
7233 if (i386_record_modrm (&ir))
7235 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7236 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7240 if (i386_record_modrm (&ir))
7242 if (ir.mod == 3 && ir.reg == 3)
7245 opcode = opcode << 8 | ir.modrm;
7257 /* nop (multi byte) */
7260 case 0x0f20: /* mov reg, crN */
7261 case 0x0f22: /* mov crN, reg */
7262 if (i386_record_modrm (&ir))
7264 if ((ir.modrm & 0xc0) != 0xc0)
7267 opcode = opcode << 8 | ir.modrm;
7278 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7280 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7284 opcode = opcode << 8 | ir.modrm;
7290 case 0x0f21: /* mov reg, drN */
7291 case 0x0f23: /* mov drN, reg */
7292 if (i386_record_modrm (&ir))
7294 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
7295 || ir.reg == 5 || ir.reg >= 8)
7298 opcode = opcode << 8 | ir.modrm;
7302 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7304 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7307 case 0x0f06: /* clts */
7308 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7311 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7313 case 0x0f0d: /* 3DNow! prefetch */
7316 case 0x0f0e: /* 3DNow! femms */
7317 case 0x0f77: /* emms */
7318 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
7320 record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
7323 case 0x0f0f: /* 3DNow! data */
7324 if (i386_record_modrm (&ir))
7326 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7331 case 0x0c: /* 3DNow! pi2fw */
7332 case 0x0d: /* 3DNow! pi2fd */
7333 case 0x1c: /* 3DNow! pf2iw */
7334 case 0x1d: /* 3DNow! pf2id */
7335 case 0x8a: /* 3DNow! pfnacc */
7336 case 0x8e: /* 3DNow! pfpnacc */
7337 case 0x90: /* 3DNow! pfcmpge */
7338 case 0x94: /* 3DNow! pfmin */
7339 case 0x96: /* 3DNow! pfrcp */
7340 case 0x97: /* 3DNow! pfrsqrt */
7341 case 0x9a: /* 3DNow! pfsub */
7342 case 0x9e: /* 3DNow! pfadd */
7343 case 0xa0: /* 3DNow! pfcmpgt */
7344 case 0xa4: /* 3DNow! pfmax */
7345 case 0xa6: /* 3DNow! pfrcpit1 */
7346 case 0xa7: /* 3DNow! pfrsqit1 */
7347 case 0xaa: /* 3DNow! pfsubr */
7348 case 0xae: /* 3DNow! pfacc */
7349 case 0xb0: /* 3DNow! pfcmpeq */
7350 case 0xb4: /* 3DNow! pfmul */
7351 case 0xb6: /* 3DNow! pfrcpit2 */
7352 case 0xb7: /* 3DNow! pmulhrw */
7353 case 0xbb: /* 3DNow! pswapd */
7354 case 0xbf: /* 3DNow! pavgusb */
7355 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7356 goto no_support_3dnow_data;
7357 record_full_arch_list_add_reg (ir.regcache, ir.reg);
7361 no_support_3dnow_data:
7362 opcode = (opcode << 8) | opcode8;
7368 case 0x0faa: /* rsm */
7369 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7370 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7371 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
7372 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7373 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
7374 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
7375 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
7376 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
7377 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
7381 if (i386_record_modrm (&ir))
7385 case 0: /* fxsave */
7389 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7390 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
7392 if (record_full_arch_list_add_mem (tmpu64, 512))
7397 case 1: /* fxrstor */
7401 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7403 for (i = I387_MM0_REGNUM (tdep);
7404 i386_mmx_regnum_p (gdbarch, i); i++)
7405 record_full_arch_list_add_reg (ir.regcache, i);
7407 for (i = I387_XMM0_REGNUM (tdep);
7408 i386_xmm_regnum_p (gdbarch, i); i++)
7409 record_full_arch_list_add_reg (ir.regcache, i);
7411 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7412 record_full_arch_list_add_reg (ir.regcache,
7413 I387_MXCSR_REGNUM(tdep));
7415 for (i = I387_ST0_REGNUM (tdep);
7416 i386_fp_regnum_p (gdbarch, i); i++)
7417 record_full_arch_list_add_reg (ir.regcache, i);
7419 for (i = I387_FCTRL_REGNUM (tdep);
7420 i386_fpc_regnum_p (gdbarch, i); i++)
7421 record_full_arch_list_add_reg (ir.regcache, i);
7425 case 2: /* ldmxcsr */
7426 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7428 record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
7431 case 3: /* stmxcsr */
7433 if (i386_record_lea_modrm (&ir))
7437 case 5: /* lfence */
7438 case 6: /* mfence */
7439 case 7: /* sfence clflush */
7443 opcode = (opcode << 8) | ir.modrm;
7449 case 0x0fc3: /* movnti */
7450 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
7451 if (i386_record_modrm (&ir))
7456 if (i386_record_lea_modrm (&ir))
7460 /* Add prefix to opcode. */
7575 /* Mask out PREFIX_ADDR. */
7576 switch ((prefixes & ~PREFIX_ADDR))
7588 reswitch_prefix_add:
7596 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7599 opcode = (uint32_t) opcode8 | opcode << 8;
7600 goto reswitch_prefix_add;
7603 case 0x0f10: /* movups */
7604 case 0x660f10: /* movupd */
7605 case 0xf30f10: /* movss */
7606 case 0xf20f10: /* movsd */
7607 case 0x0f12: /* movlps */
7608 case 0x660f12: /* movlpd */
7609 case 0xf30f12: /* movsldup */
7610 case 0xf20f12: /* movddup */
7611 case 0x0f14: /* unpcklps */
7612 case 0x660f14: /* unpcklpd */
7613 case 0x0f15: /* unpckhps */
7614 case 0x660f15: /* unpckhpd */
7615 case 0x0f16: /* movhps */
7616 case 0x660f16: /* movhpd */
7617 case 0xf30f16: /* movshdup */
7618 case 0x0f28: /* movaps */
7619 case 0x660f28: /* movapd */
7620 case 0x0f2a: /* cvtpi2ps */
7621 case 0x660f2a: /* cvtpi2pd */
7622 case 0xf30f2a: /* cvtsi2ss */
7623 case 0xf20f2a: /* cvtsi2sd */
7624 case 0x0f2c: /* cvttps2pi */
7625 case 0x660f2c: /* cvttpd2pi */
7626 case 0x0f2d: /* cvtps2pi */
7627 case 0x660f2d: /* cvtpd2pi */
7628 case 0x660f3800: /* pshufb */
7629 case 0x660f3801: /* phaddw */
7630 case 0x660f3802: /* phaddd */
7631 case 0x660f3803: /* phaddsw */
7632 case 0x660f3804: /* pmaddubsw */
7633 case 0x660f3805: /* phsubw */
7634 case 0x660f3806: /* phsubd */
7635 case 0x660f3807: /* phsubsw */
7636 case 0x660f3808: /* psignb */
7637 case 0x660f3809: /* psignw */
7638 case 0x660f380a: /* psignd */
7639 case 0x660f380b: /* pmulhrsw */
7640 case 0x660f3810: /* pblendvb */
7641 case 0x660f3814: /* blendvps */
7642 case 0x660f3815: /* blendvpd */
7643 case 0x660f381c: /* pabsb */
7644 case 0x660f381d: /* pabsw */
7645 case 0x660f381e: /* pabsd */
7646 case 0x660f3820: /* pmovsxbw */
7647 case 0x660f3821: /* pmovsxbd */
7648 case 0x660f3822: /* pmovsxbq */
7649 case 0x660f3823: /* pmovsxwd */
7650 case 0x660f3824: /* pmovsxwq */
7651 case 0x660f3825: /* pmovsxdq */
7652 case 0x660f3828: /* pmuldq */
7653 case 0x660f3829: /* pcmpeqq */
7654 case 0x660f382a: /* movntdqa */
7655 case 0x660f3a08: /* roundps */
7656 case 0x660f3a09: /* roundpd */
7657 case 0x660f3a0a: /* roundss */
7658 case 0x660f3a0b: /* roundsd */
7659 case 0x660f3a0c: /* blendps */
7660 case 0x660f3a0d: /* blendpd */
7661 case 0x660f3a0e: /* pblendw */
7662 case 0x660f3a0f: /* palignr */
7663 case 0x660f3a20: /* pinsrb */
7664 case 0x660f3a21: /* insertps */
7665 case 0x660f3a22: /* pinsrd pinsrq */
7666 case 0x660f3a40: /* dpps */
7667 case 0x660f3a41: /* dppd */
7668 case 0x660f3a42: /* mpsadbw */
7669 case 0x660f3a60: /* pcmpestrm */
7670 case 0x660f3a61: /* pcmpestri */
7671 case 0x660f3a62: /* pcmpistrm */
7672 case 0x660f3a63: /* pcmpistri */
7673 case 0x0f51: /* sqrtps */
7674 case 0x660f51: /* sqrtpd */
7675 case 0xf20f51: /* sqrtsd */
7676 case 0xf30f51: /* sqrtss */
7677 case 0x0f52: /* rsqrtps */
7678 case 0xf30f52: /* rsqrtss */
7679 case 0x0f53: /* rcpps */
7680 case 0xf30f53: /* rcpss */
7681 case 0x0f54: /* andps */
7682 case 0x660f54: /* andpd */
7683 case 0x0f55: /* andnps */
7684 case 0x660f55: /* andnpd */
7685 case 0x0f56: /* orps */
7686 case 0x660f56: /* orpd */
7687 case 0x0f57: /* xorps */
7688 case 0x660f57: /* xorpd */
7689 case 0x0f58: /* addps */
7690 case 0x660f58: /* addpd */
7691 case 0xf20f58: /* addsd */
7692 case 0xf30f58: /* addss */
7693 case 0x0f59: /* mulps */
7694 case 0x660f59: /* mulpd */
7695 case 0xf20f59: /* mulsd */
7696 case 0xf30f59: /* mulss */
7697 case 0x0f5a: /* cvtps2pd */
7698 case 0x660f5a: /* cvtpd2ps */
7699 case 0xf20f5a: /* cvtsd2ss */
7700 case 0xf30f5a: /* cvtss2sd */
7701 case 0x0f5b: /* cvtdq2ps */
7702 case 0x660f5b: /* cvtps2dq */
7703 case 0xf30f5b: /* cvttps2dq */
7704 case 0x0f5c: /* subps */
7705 case 0x660f5c: /* subpd */
7706 case 0xf20f5c: /* subsd */
7707 case 0xf30f5c: /* subss */
7708 case 0x0f5d: /* minps */
7709 case 0x660f5d: /* minpd */
7710 case 0xf20f5d: /* minsd */
7711 case 0xf30f5d: /* minss */
7712 case 0x0f5e: /* divps */
7713 case 0x660f5e: /* divpd */
7714 case 0xf20f5e: /* divsd */
7715 case 0xf30f5e: /* divss */
7716 case 0x0f5f: /* maxps */
7717 case 0x660f5f: /* maxpd */
7718 case 0xf20f5f: /* maxsd */
7719 case 0xf30f5f: /* maxss */
7720 case 0x660f60: /* punpcklbw */
7721 case 0x660f61: /* punpcklwd */
7722 case 0x660f62: /* punpckldq */
7723 case 0x660f63: /* packsswb */
7724 case 0x660f64: /* pcmpgtb */
7725 case 0x660f65: /* pcmpgtw */
7726 case 0x660f66: /* pcmpgtd */
7727 case 0x660f67: /* packuswb */
7728 case 0x660f68: /* punpckhbw */
7729 case 0x660f69: /* punpckhwd */
7730 case 0x660f6a: /* punpckhdq */
7731 case 0x660f6b: /* packssdw */
7732 case 0x660f6c: /* punpcklqdq */
7733 case 0x660f6d: /* punpckhqdq */
7734 case 0x660f6e: /* movd */
7735 case 0x660f6f: /* movdqa */
7736 case 0xf30f6f: /* movdqu */
7737 case 0x660f70: /* pshufd */
7738 case 0xf20f70: /* pshuflw */
7739 case 0xf30f70: /* pshufhw */
7740 case 0x660f74: /* pcmpeqb */
7741 case 0x660f75: /* pcmpeqw */
7742 case 0x660f76: /* pcmpeqd */
7743 case 0x660f7c: /* haddpd */
7744 case 0xf20f7c: /* haddps */
7745 case 0x660f7d: /* hsubpd */
7746 case 0xf20f7d: /* hsubps */
7747 case 0xf30f7e: /* movq */
7748 case 0x0fc2: /* cmpps */
7749 case 0x660fc2: /* cmppd */
7750 case 0xf20fc2: /* cmpsd */
7751 case 0xf30fc2: /* cmpss */
7752 case 0x660fc4: /* pinsrw */
7753 case 0x0fc6: /* shufps */
7754 case 0x660fc6: /* shufpd */
7755 case 0x660fd0: /* addsubpd */
7756 case 0xf20fd0: /* addsubps */
7757 case 0x660fd1: /* psrlw */
7758 case 0x660fd2: /* psrld */
7759 case 0x660fd3: /* psrlq */
7760 case 0x660fd4: /* paddq */
7761 case 0x660fd5: /* pmullw */
7762 case 0xf30fd6: /* movq2dq */
7763 case 0x660fd8: /* psubusb */
7764 case 0x660fd9: /* psubusw */
7765 case 0x660fda: /* pminub */
7766 case 0x660fdb: /* pand */
7767 case 0x660fdc: /* paddusb */
7768 case 0x660fdd: /* paddusw */
7769 case 0x660fde: /* pmaxub */
7770 case 0x660fdf: /* pandn */
7771 case 0x660fe0: /* pavgb */
7772 case 0x660fe1: /* psraw */
7773 case 0x660fe2: /* psrad */
7774 case 0x660fe3: /* pavgw */
7775 case 0x660fe4: /* pmulhuw */
7776 case 0x660fe5: /* pmulhw */
7777 case 0x660fe6: /* cvttpd2dq */
7778 case 0xf20fe6: /* cvtpd2dq */
7779 case 0xf30fe6: /* cvtdq2pd */
7780 case 0x660fe8: /* psubsb */
7781 case 0x660fe9: /* psubsw */
7782 case 0x660fea: /* pminsw */
7783 case 0x660feb: /* por */
7784 case 0x660fec: /* paddsb */
7785 case 0x660fed: /* paddsw */
7786 case 0x660fee: /* pmaxsw */
7787 case 0x660fef: /* pxor */
7788 case 0xf20ff0: /* lddqu */
7789 case 0x660ff1: /* psllw */
7790 case 0x660ff2: /* pslld */
7791 case 0x660ff3: /* psllq */
7792 case 0x660ff4: /* pmuludq */
7793 case 0x660ff5: /* pmaddwd */
7794 case 0x660ff6: /* psadbw */
7795 case 0x660ff8: /* psubb */
7796 case 0x660ff9: /* psubw */
7797 case 0x660ffa: /* psubd */
7798 case 0x660ffb: /* psubq */
7799 case 0x660ffc: /* paddb */
7800 case 0x660ffd: /* paddw */
7801 case 0x660ffe: /* paddd */
7802 if (i386_record_modrm (&ir))
7805 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
7807 record_full_arch_list_add_reg (ir.regcache,
7808 I387_XMM0_REGNUM (tdep) + ir.reg);
7809 if ((opcode & 0xfffffffc) == 0x660f3a60)
7810 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7813 case 0x0f11: /* movups */
7814 case 0x660f11: /* movupd */
7815 case 0xf30f11: /* movss */
7816 case 0xf20f11: /* movsd */
7817 case 0x0f13: /* movlps */
7818 case 0x660f13: /* movlpd */
7819 case 0x0f17: /* movhps */
7820 case 0x660f17: /* movhpd */
7821 case 0x0f29: /* movaps */
7822 case 0x660f29: /* movapd */
7823 case 0x660f3a14: /* pextrb */
7824 case 0x660f3a15: /* pextrw */
7825 case 0x660f3a16: /* pextrd pextrq */
7826 case 0x660f3a17: /* extractps */
7827 case 0x660f7f: /* movdqa */
7828 case 0xf30f7f: /* movdqu */
7829 if (i386_record_modrm (&ir))
7833 if (opcode == 0x0f13 || opcode == 0x660f13
7834 || opcode == 0x0f17 || opcode == 0x660f17)
7837 if (!i386_xmm_regnum_p (gdbarch,
7838 I387_XMM0_REGNUM (tdep) + ir.rm))
7840 record_full_arch_list_add_reg (ir.regcache,
7841 I387_XMM0_REGNUM (tdep) + ir.rm);
7863 if (i386_record_lea_modrm (&ir))
7868 case 0x0f2b: /* movntps */
7869 case 0x660f2b: /* movntpd */
7870 case 0x0fe7: /* movntq */
7871 case 0x660fe7: /* movntdq */
7874 if (opcode == 0x0fe7)
7878 if (i386_record_lea_modrm (&ir))
7882 case 0xf30f2c: /* cvttss2si */
7883 case 0xf20f2c: /* cvttsd2si */
7884 case 0xf30f2d: /* cvtss2si */
7885 case 0xf20f2d: /* cvtsd2si */
7886 case 0xf20f38f0: /* crc32 */
7887 case 0xf20f38f1: /* crc32 */
7888 case 0x0f50: /* movmskps */
7889 case 0x660f50: /* movmskpd */
7890 case 0x0fc5: /* pextrw */
7891 case 0x660fc5: /* pextrw */
7892 case 0x0fd7: /* pmovmskb */
7893 case 0x660fd7: /* pmovmskb */
7894 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7897 case 0x0f3800: /* pshufb */
7898 case 0x0f3801: /* phaddw */
7899 case 0x0f3802: /* phaddd */
7900 case 0x0f3803: /* phaddsw */
7901 case 0x0f3804: /* pmaddubsw */
7902 case 0x0f3805: /* phsubw */
7903 case 0x0f3806: /* phsubd */
7904 case 0x0f3807: /* phsubsw */
7905 case 0x0f3808: /* psignb */
7906 case 0x0f3809: /* psignw */
7907 case 0x0f380a: /* psignd */
7908 case 0x0f380b: /* pmulhrsw */
7909 case 0x0f381c: /* pabsb */
7910 case 0x0f381d: /* pabsw */
7911 case 0x0f381e: /* pabsd */
7912 case 0x0f382b: /* packusdw */
7913 case 0x0f3830: /* pmovzxbw */
7914 case 0x0f3831: /* pmovzxbd */
7915 case 0x0f3832: /* pmovzxbq */
7916 case 0x0f3833: /* pmovzxwd */
7917 case 0x0f3834: /* pmovzxwq */
7918 case 0x0f3835: /* pmovzxdq */
7919 case 0x0f3837: /* pcmpgtq */
7920 case 0x0f3838: /* pminsb */
7921 case 0x0f3839: /* pminsd */
7922 case 0x0f383a: /* pminuw */
7923 case 0x0f383b: /* pminud */
7924 case 0x0f383c: /* pmaxsb */
7925 case 0x0f383d: /* pmaxsd */
7926 case 0x0f383e: /* pmaxuw */
7927 case 0x0f383f: /* pmaxud */
7928 case 0x0f3840: /* pmulld */
7929 case 0x0f3841: /* phminposuw */
7930 case 0x0f3a0f: /* palignr */
7931 case 0x0f60: /* punpcklbw */
7932 case 0x0f61: /* punpcklwd */
7933 case 0x0f62: /* punpckldq */
7934 case 0x0f63: /* packsswb */
7935 case 0x0f64: /* pcmpgtb */
7936 case 0x0f65: /* pcmpgtw */
7937 case 0x0f66: /* pcmpgtd */
7938 case 0x0f67: /* packuswb */
7939 case 0x0f68: /* punpckhbw */
7940 case 0x0f69: /* punpckhwd */
7941 case 0x0f6a: /* punpckhdq */
7942 case 0x0f6b: /* packssdw */
7943 case 0x0f6e: /* movd */
7944 case 0x0f6f: /* movq */
7945 case 0x0f70: /* pshufw */
7946 case 0x0f74: /* pcmpeqb */
7947 case 0x0f75: /* pcmpeqw */
7948 case 0x0f76: /* pcmpeqd */
7949 case 0x0fc4: /* pinsrw */
7950 case 0x0fd1: /* psrlw */
7951 case 0x0fd2: /* psrld */
7952 case 0x0fd3: /* psrlq */
7953 case 0x0fd4: /* paddq */
7954 case 0x0fd5: /* pmullw */
7955 case 0xf20fd6: /* movdq2q */
7956 case 0x0fd8: /* psubusb */
7957 case 0x0fd9: /* psubusw */
7958 case 0x0fda: /* pminub */
7959 case 0x0fdb: /* pand */
7960 case 0x0fdc: /* paddusb */
7961 case 0x0fdd: /* paddusw */
7962 case 0x0fde: /* pmaxub */
7963 case 0x0fdf: /* pandn */
7964 case 0x0fe0: /* pavgb */
7965 case 0x0fe1: /* psraw */
7966 case 0x0fe2: /* psrad */
7967 case 0x0fe3: /* pavgw */
7968 case 0x0fe4: /* pmulhuw */
7969 case 0x0fe5: /* pmulhw */
7970 case 0x0fe8: /* psubsb */
7971 case 0x0fe9: /* psubsw */
7972 case 0x0fea: /* pminsw */
7973 case 0x0feb: /* por */
7974 case 0x0fec: /* paddsb */
7975 case 0x0fed: /* paddsw */
7976 case 0x0fee: /* pmaxsw */
7977 case 0x0fef: /* pxor */
7978 case 0x0ff1: /* psllw */
7979 case 0x0ff2: /* pslld */
7980 case 0x0ff3: /* psllq */
7981 case 0x0ff4: /* pmuludq */
7982 case 0x0ff5: /* pmaddwd */
7983 case 0x0ff6: /* psadbw */
7984 case 0x0ff8: /* psubb */
7985 case 0x0ff9: /* psubw */
7986 case 0x0ffa: /* psubd */
7987 case 0x0ffb: /* psubq */
7988 case 0x0ffc: /* paddb */
7989 case 0x0ffd: /* paddw */
7990 case 0x0ffe: /* paddd */
7991 if (i386_record_modrm (&ir))
7993 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7995 record_full_arch_list_add_reg (ir.regcache,
7996 I387_MM0_REGNUM (tdep) + ir.reg);
7999 case 0x0f71: /* psllw */
8000 case 0x0f72: /* pslld */
8001 case 0x0f73: /* psllq */
8002 if (i386_record_modrm (&ir))
8004 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
8006 record_full_arch_list_add_reg (ir.regcache,
8007 I387_MM0_REGNUM (tdep) + ir.rm);
8010 case 0x660f71: /* psllw */
8011 case 0x660f72: /* pslld */
8012 case 0x660f73: /* psllq */
8013 if (i386_record_modrm (&ir))
8016 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
8018 record_full_arch_list_add_reg (ir.regcache,
8019 I387_XMM0_REGNUM (tdep) + ir.rm);
8022 case 0x0f7e: /* movd */
8023 case 0x660f7e: /* movd */
8024 if (i386_record_modrm (&ir))
8027 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
8034 if (i386_record_lea_modrm (&ir))
8039 case 0x0f7f: /* movq */
8040 if (i386_record_modrm (&ir))
8044 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
8046 record_full_arch_list_add_reg (ir.regcache,
8047 I387_MM0_REGNUM (tdep) + ir.rm);
8052 if (i386_record_lea_modrm (&ir))
8057 case 0xf30fb8: /* popcnt */
8058 if (i386_record_modrm (&ir))
8060 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
8061 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
8064 case 0x660fd6: /* movq */
8065 if (i386_record_modrm (&ir))
8070 if (!i386_xmm_regnum_p (gdbarch,
8071 I387_XMM0_REGNUM (tdep) + ir.rm))
8073 record_full_arch_list_add_reg (ir.regcache,
8074 I387_XMM0_REGNUM (tdep) + ir.rm);
8079 if (i386_record_lea_modrm (&ir))
8084 case 0x660f3817: /* ptest */
8085 case 0x0f2e: /* ucomiss */
8086 case 0x660f2e: /* ucomisd */
8087 case 0x0f2f: /* comiss */
8088 case 0x660f2f: /* comisd */
8089 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
8092 case 0x0ff7: /* maskmovq */
8093 regcache_raw_read_unsigned (ir.regcache,
8094 ir.regmap[X86_RECORD_REDI_REGNUM],
8096 if (record_full_arch_list_add_mem (addr, 64))
8100 case 0x660ff7: /* maskmovdqu */
8101 regcache_raw_read_unsigned (ir.regcache,
8102 ir.regmap[X86_RECORD_REDI_REGNUM],
8104 if (record_full_arch_list_add_mem (addr, 128))
8119 /* In the future, maybe still need to deal with need_dasm. */
8120 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
8121 if (record_full_arch_list_add_end ())
8127 printf_unfiltered (_("Process record does not support instruction 0x%02x "
8128 "at address %s.\n"),
8129 (unsigned int) (opcode),
8130 paddress (gdbarch, ir.orig_addr));
8134 static const int i386_record_regmap[] =
8136 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
8137 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
8138 0, 0, 0, 0, 0, 0, 0, 0,
8139 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
8140 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
8143 /* Check that the given address appears suitable for a fast
8144 tracepoint, which on x86-64 means that we need an instruction of at
8145 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8146 jump and not have to worry about program jumps to an address in the
8147 middle of the tracepoint jump. On x86, it may be possible to use
8148 4-byte jumps with a 2-byte offset to a trampoline located in the
8149 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8150 of instruction to replace, and 0 if not, plus an explanatory
8154 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, CORE_ADDR addr,
8159 /* Ask the target for the minimum instruction length supported. */
8160 jumplen = target_get_min_fast_tracepoint_insn_len ();
8164 /* If the target does not support the get_min_fast_tracepoint_insn_len
8165 operation, assume that fast tracepoints will always be implemented
8166 using 4-byte relative jumps on both x86 and x86-64. */
8169 else if (jumplen == 0)
8171 /* If the target does support get_min_fast_tracepoint_insn_len but
8172 returns zero, then the IPA has not loaded yet. In this case,
8173 we optimistically assume that truncated 2-byte relative jumps
8174 will be available on x86, and compensate later if this assumption
8175 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8176 jumps will always be used. */
8177 jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4;
8180 /* Check for fit. */
8181 len = gdb_insn_length (gdbarch, addr);
8185 /* Return a bit of target-specific detail to add to the caller's
8186 generic failure message. */
8188 *msg = xstrprintf (_("; instruction is only %d bytes long, "
8189 "need at least %d bytes for the jump"),
8201 /* Return a floating-point format for a floating-point variable of
8202 length LEN in bits. If non-NULL, NAME is the name of its type.
8203 If no suitable type is found, return NULL. */
8205 const struct floatformat **
8206 i386_floatformat_for_type (struct gdbarch *gdbarch,
8207 const char *name, int len)
8209 if (len == 128 && name)
8210 if (strcmp (name, "__float128") == 0
8211 || strcmp (name, "_Float128") == 0
8212 || strcmp (name, "complex _Float128") == 0)
8213 return floatformats_ia64_quad;
8215 return default_floatformat_for_type (gdbarch, name, len);
8219 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
8220 struct tdesc_arch_data *tdesc_data)
8222 const struct target_desc *tdesc = tdep->tdesc;
8223 const struct tdesc_feature *feature_core;
8225 const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx,
8226 *feature_avx512, *feature_pkeys;
8227 int i, num_regs, valid_p;
8229 if (! tdesc_has_registers (tdesc))
8232 /* Get core registers. */
8233 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
8234 if (feature_core == NULL)
8237 /* Get SSE registers. */
8238 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
8240 /* Try AVX registers. */
8241 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
8243 /* Try MPX registers. */
8244 feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx");
8246 /* Try AVX512 registers. */
8247 feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512");
8250 feature_pkeys = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys");
8254 /* The XCR0 bits. */
8257 /* AVX512 register description requires AVX register description. */
8261 tdep->xcr0 = X86_XSTATE_AVX_AVX512_MASK;
8263 /* It may have been set by OSABI initialization function. */
8264 if (tdep->k0_regnum < 0)
8266 tdep->k_register_names = i386_k_names;
8267 tdep->k0_regnum = I386_K0_REGNUM;
8270 for (i = 0; i < I387_NUM_K_REGS; i++)
8271 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8272 tdep->k0_regnum + i,
8275 if (tdep->num_zmm_regs == 0)
8277 tdep->zmmh_register_names = i386_zmmh_names;
8278 tdep->num_zmm_regs = 8;
8279 tdep->zmm0h_regnum = I386_ZMM0H_REGNUM;
8282 for (i = 0; i < tdep->num_zmm_regs; i++)
8283 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8284 tdep->zmm0h_regnum + i,
8285 tdep->zmmh_register_names[i]);
8287 for (i = 0; i < tdep->num_xmm_avx512_regs; i++)
8288 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8289 tdep->xmm16_regnum + i,
8290 tdep->xmm_avx512_register_names[i]);
8292 for (i = 0; i < tdep->num_ymm_avx512_regs; i++)
8293 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8294 tdep->ymm16h_regnum + i,
8295 tdep->ymm16h_register_names[i]);
8299 /* AVX register description requires SSE register description. */
8303 if (!feature_avx512)
8304 tdep->xcr0 = X86_XSTATE_AVX_MASK;
8306 /* It may have been set by OSABI initialization function. */
8307 if (tdep->num_ymm_regs == 0)
8309 tdep->ymmh_register_names = i386_ymmh_names;
8310 tdep->num_ymm_regs = 8;
8311 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
8314 for (i = 0; i < tdep->num_ymm_regs; i++)
8315 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
8316 tdep->ymm0h_regnum + i,
8317 tdep->ymmh_register_names[i]);
8319 else if (feature_sse)
8320 tdep->xcr0 = X86_XSTATE_SSE_MASK;
8323 tdep->xcr0 = X86_XSTATE_X87_MASK;
8324 tdep->num_xmm_regs = 0;
8327 num_regs = tdep->num_core_regs;
8328 for (i = 0; i < num_regs; i++)
8329 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
8330 tdep->register_names[i]);
8334 /* Need to include %mxcsr, so add one. */
8335 num_regs += tdep->num_xmm_regs + 1;
8336 for (; i < num_regs; i++)
8337 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
8338 tdep->register_names[i]);
8343 tdep->xcr0 |= X86_XSTATE_MPX_MASK;
8345 if (tdep->bnd0r_regnum < 0)
8347 tdep->mpx_register_names = i386_mpx_names;
8348 tdep->bnd0r_regnum = I386_BND0R_REGNUM;
8349 tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM;
8352 for (i = 0; i < I387_NUM_MPX_REGS; i++)
8353 valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data,
8354 I387_BND0R_REGNUM (tdep) + i,
8355 tdep->mpx_register_names[i]);
8360 tdep->xcr0 |= X86_XSTATE_PKRU;
8361 if (tdep->pkru_regnum < 0)
8363 tdep->pkeys_register_names = i386_pkeys_names;
8364 tdep->pkru_regnum = I386_PKRU_REGNUM;
8365 tdep->num_pkeys_regs = 1;
8368 for (i = 0; i < I387_NUM_PKEYS_REGS; i++)
8369 valid_p &= tdesc_numbered_register (feature_pkeys, tdesc_data,
8370 I387_PKRU_REGNUM (tdep) + i,
8371 tdep->pkeys_register_names[i]);
8378 /* Note: This is called for both i386 and amd64. */
8380 static struct gdbarch *
8381 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8383 struct gdbarch_tdep *tdep;
8384 struct gdbarch *gdbarch;
8385 struct tdesc_arch_data *tdesc_data;
8386 const struct target_desc *tdesc;
8392 /* If there is already a candidate, use it. */
8393 arches = gdbarch_list_lookup_by_info (arches, &info);
8395 return arches->gdbarch;
8397 /* Allocate space for the new architecture. Assume i386 for now. */
8398 tdep = XCNEW (struct gdbarch_tdep);
8399 gdbarch = gdbarch_alloc (&info, tdep);
8401 /* General-purpose registers. */
8402 tdep->gregset_reg_offset = NULL;
8403 tdep->gregset_num_regs = I386_NUM_GREGS;
8404 tdep->sizeof_gregset = 0;
8406 /* Floating-point registers. */
8407 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
8408 tdep->fpregset = &i386_fpregset;
8410 /* The default settings include the FPU registers, the MMX registers
8411 and the SSE registers. This can be overridden for a specific ABI
8412 by adjusting the members `st0_regnum', `mm0_regnum' and
8413 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8414 will show up in the output of "info all-registers". */
8416 tdep->st0_regnum = I386_ST0_REGNUM;
8418 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8419 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
8421 tdep->jb_pc_offset = -1;
8422 tdep->struct_return = pcc_struct_return;
8423 tdep->sigtramp_start = 0;
8424 tdep->sigtramp_end = 0;
8425 tdep->sigtramp_p = i386_sigtramp_p;
8426 tdep->sigcontext_addr = NULL;
8427 tdep->sc_reg_offset = NULL;
8428 tdep->sc_pc_offset = -1;
8429 tdep->sc_sp_offset = -1;
8431 tdep->xsave_xcr0_offset = -1;
8433 tdep->record_regmap = i386_record_regmap;
8435 set_gdbarch_long_long_align_bit (gdbarch, 32);
8437 /* The format used for `long double' on almost all i386 targets is
8438 the i387 extended floating-point format. In fact, of all targets
8439 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8440 on having a `long double' that's not `long' at all. */
8441 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
8443 /* Although the i387 extended floating-point has only 80 significant
8444 bits, a `long double' actually takes up 96, probably to enforce
8446 set_gdbarch_long_double_bit (gdbarch, 96);
8448 /* Support for floating-point data type variants. */
8449 set_gdbarch_floatformat_for_type (gdbarch, i386_floatformat_for_type);
8451 /* Register numbers of various important registers. */
8452 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
8453 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
8454 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
8455 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
8457 /* NOTE: kettenis/20040418: GCC does have two possible register
8458 numbering schemes on the i386: dbx and SVR4. These schemes
8459 differ in how they number %ebp, %esp, %eflags, and the
8460 floating-point registers, and are implemented by the arrays
8461 dbx_register_map[] and svr4_dbx_register_map in
8462 gcc/config/i386.c. GCC also defines a third numbering scheme in
8463 gcc/config/i386.c, which it designates as the "default" register
8464 map used in 64bit mode. This last register numbering scheme is
8465 implemented in dbx64_register_map, and is used for AMD64; see
8468 Currently, each GCC i386 target always uses the same register
8469 numbering scheme across all its supported debugging formats
8470 i.e. SDB (COFF), stabs and DWARF 2. This is because
8471 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8472 DBX_REGISTER_NUMBER macro which is defined by each target's
8473 respective config header in a manner independent of the requested
8474 output debugging format.
8476 This does not match the arrangement below, which presumes that
8477 the SDB and stabs numbering schemes differ from the DWARF and
8478 DWARF 2 ones. The reason for this arrangement is that it is
8479 likely to get the numbering scheme for the target's
8480 default/native debug format right. For targets where GCC is the
8481 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8482 targets where the native toolchain uses a different numbering
8483 scheme for a particular debug format (stabs-in-ELF on Solaris)
8484 the defaults below will have to be overridden, like
8485 i386_elf_init_abi() does. */
8487 /* Use the dbx register numbering scheme for stabs and COFF. */
8488 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8489 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8491 /* Use the SVR4 register numbering scheme for DWARF 2. */
8492 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_dwarf_reg_to_regnum);
8494 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8495 be in use on any of the supported i386 targets. */
8497 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
8499 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
8501 /* Call dummy code. */
8502 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
8503 set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code);
8504 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
8505 set_gdbarch_frame_align (gdbarch, i386_frame_align);
8507 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
8508 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
8509 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
8511 set_gdbarch_return_value (gdbarch, i386_return_value);
8513 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
8515 /* Stack grows downward. */
8516 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8518 set_gdbarch_breakpoint_kind_from_pc (gdbarch, i386_breakpoint::kind_from_pc);
8519 set_gdbarch_sw_breakpoint_from_kind (gdbarch, i386_breakpoint::bp_from_kind);
8521 set_gdbarch_decr_pc_after_break (gdbarch, 1);
8522 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
8524 set_gdbarch_frame_args_skip (gdbarch, 8);
8526 set_gdbarch_print_insn (gdbarch, i386_print_insn);
8528 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
8530 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
8532 /* Add the i386 register groups. */
8533 i386_add_reggroups (gdbarch);
8534 tdep->register_reggroup_p = i386_register_reggroup_p;
8536 /* Helper for function argument information. */
8537 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
8539 /* Hook the function epilogue frame unwinder. This unwinder is
8540 appended to the list first, so that it supercedes the DWARF
8541 unwinder in function epilogues (where the DWARF unwinder
8542 currently fails). */
8543 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
8545 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8546 to the list before the prologue-based unwinders, so that DWARF
8547 CFI info will be used if it is available. */
8548 dwarf2_append_unwinders (gdbarch);
8550 frame_base_set_default (gdbarch, &i386_frame_base);
8552 /* Pseudo registers may be changed by amd64_init_abi. */
8553 set_gdbarch_pseudo_register_read_value (gdbarch,
8554 i386_pseudo_register_read_value);
8555 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
8556 set_gdbarch_ax_pseudo_register_collect (gdbarch,
8557 i386_ax_pseudo_register_collect);
8559 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
8560 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
8562 /* Override the normal target description method to make the AVX
8563 upper halves anonymous. */
8564 set_gdbarch_register_name (gdbarch, i386_register_name);
8566 /* Even though the default ABI only includes general-purpose registers,
8567 floating-point registers and the SSE registers, we have to leave a
8568 gap for the upper AVX, MPX and AVX512 registers. */
8569 set_gdbarch_num_regs (gdbarch, I386_PKEYS_NUM_REGS);
8571 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
8573 /* Get the x86 target description from INFO. */
8574 tdesc = info.target_desc;
8575 if (! tdesc_has_registers (tdesc))
8577 tdep->tdesc = tdesc;
8579 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
8580 tdep->register_names = i386_register_names;
8582 /* No upper YMM registers. */
8583 tdep->ymmh_register_names = NULL;
8584 tdep->ymm0h_regnum = -1;
8586 /* No upper ZMM registers. */
8587 tdep->zmmh_register_names = NULL;
8588 tdep->zmm0h_regnum = -1;
8590 /* No high XMM registers. */
8591 tdep->xmm_avx512_register_names = NULL;
8592 tdep->xmm16_regnum = -1;
8594 /* No upper YMM16-31 registers. */
8595 tdep->ymm16h_register_names = NULL;
8596 tdep->ymm16h_regnum = -1;
8598 tdep->num_byte_regs = 8;
8599 tdep->num_word_regs = 8;
8600 tdep->num_dword_regs = 0;
8601 tdep->num_mmx_regs = 8;
8602 tdep->num_ymm_regs = 0;
8604 /* No MPX registers. */
8605 tdep->bnd0r_regnum = -1;
8606 tdep->bndcfgu_regnum = -1;
8608 /* No AVX512 registers. */
8609 tdep->k0_regnum = -1;
8610 tdep->num_zmm_regs = 0;
8611 tdep->num_ymm_avx512_regs = 0;
8612 tdep->num_xmm_avx512_regs = 0;
8614 /* No PKEYS registers */
8615 tdep->pkru_regnum = -1;
8616 tdep->num_pkeys_regs = 0;
8618 tdesc_data = tdesc_data_alloc ();
8620 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
8622 set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address);
8624 set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call);
8625 set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret);
8626 set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump);
8628 /* Hook in ABI-specific overrides, if they have been registered.
8629 Note: If INFO specifies a 64 bit arch, this is where we turn
8630 a 32-bit i386 into a 64-bit amd64. */
8631 info.tdep_info = tdesc_data;
8632 gdbarch_init_osabi (info, gdbarch);
8634 if (!i386_validate_tdesc_p (tdep, tdesc_data))
8636 tdesc_data_cleanup (tdesc_data);
8638 gdbarch_free (gdbarch);
8642 num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0);
8644 /* Wire in pseudo registers. Number of pseudo registers may be
8646 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
8647 + tdep->num_word_regs
8648 + tdep->num_dword_regs
8649 + tdep->num_mmx_regs
8650 + tdep->num_ymm_regs
8652 + tdep->num_ymm_avx512_regs
8653 + tdep->num_zmm_regs));
8655 /* Target description may be changed. */
8656 tdesc = tdep->tdesc;
8658 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
8660 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8661 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
8663 /* Make %al the first pseudo-register. */
8664 tdep->al_regnum = gdbarch_num_regs (gdbarch);
8665 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
8667 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
8668 if (tdep->num_dword_regs)
8670 /* Support dword pseudo-register if it hasn't been disabled. */
8671 tdep->eax_regnum = ymm0_regnum;
8672 ymm0_regnum += tdep->num_dword_regs;
8675 tdep->eax_regnum = -1;
8677 mm0_regnum = ymm0_regnum;
8678 if (tdep->num_ymm_regs)
8680 /* Support YMM pseudo-register if it is available. */
8681 tdep->ymm0_regnum = ymm0_regnum;
8682 mm0_regnum += tdep->num_ymm_regs;
8685 tdep->ymm0_regnum = -1;
8687 if (tdep->num_ymm_avx512_regs)
8689 /* Support YMM16-31 pseudo registers if available. */
8690 tdep->ymm16_regnum = mm0_regnum;
8691 mm0_regnum += tdep->num_ymm_avx512_regs;
8694 tdep->ymm16_regnum = -1;
8696 if (tdep->num_zmm_regs)
8698 /* Support ZMM pseudo-register if it is available. */
8699 tdep->zmm0_regnum = mm0_regnum;
8700 mm0_regnum += tdep->num_zmm_regs;
8703 tdep->zmm0_regnum = -1;
8705 bnd0_regnum = mm0_regnum;
8706 if (tdep->num_mmx_regs != 0)
8708 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8709 tdep->mm0_regnum = mm0_regnum;
8710 bnd0_regnum += tdep->num_mmx_regs;
8713 tdep->mm0_regnum = -1;
8715 if (tdep->bnd0r_regnum > 0)
8716 tdep->bnd0_regnum = bnd0_regnum;
8718 tdep-> bnd0_regnum = -1;
8720 /* Hook in the legacy prologue-based unwinders last (fallback). */
8721 frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind);
8722 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
8723 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
8725 /* If we have a register mapping, enable the generic core file
8726 support, unless it has already been enabled. */
8727 if (tdep->gregset_reg_offset
8728 && !gdbarch_iterate_over_regset_sections_p (gdbarch))
8729 set_gdbarch_iterate_over_regset_sections
8730 (gdbarch, i386_iterate_over_regset_sections);
8732 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
8733 i386_fast_tracepoint_valid_at);
8738 static enum gdb_osabi
8739 i386_coff_osabi_sniffer (bfd *abfd)
8741 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
8742 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
8743 return GDB_OSABI_GO32;
8745 return GDB_OSABI_UNKNOWN;
8749 /* Return the target description for a specified XSAVE feature mask. */
8751 const struct target_desc *
8752 i386_target_description (uint64_t xcr0)
8754 switch (xcr0 & X86_XSTATE_ALL_MASK)
8756 case X86_XSTATE_AVX_MPX_AVX512_PKU_MASK:
8757 return tdesc_i386_avx_mpx_avx512_pku;
8758 case X86_XSTATE_AVX_AVX512_MASK:
8759 return tdesc_i386_avx_avx512;
8760 case X86_XSTATE_AVX_MPX_MASK:
8761 return tdesc_i386_avx_mpx;
8762 case X86_XSTATE_MPX_MASK:
8763 return tdesc_i386_mpx;
8764 case X86_XSTATE_AVX_MASK:
8765 return tdesc_i386_avx;
8771 #define MPX_BASE_MASK (~(ULONGEST) 0xfff)
8773 /* Find the bound directory base address. */
8775 static unsigned long
8776 i386_mpx_bd_base (void)
8778 struct regcache *rcache;
8779 struct gdbarch_tdep *tdep;
8781 enum register_status regstatus;
8783 rcache = get_current_regcache ();
8784 tdep = gdbarch_tdep (get_regcache_arch (rcache));
8786 regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret);
8788 if (regstatus != REG_VALID)
8789 error (_("BNDCFGU register invalid, read status %d."), regstatus);
8791 return ret & MPX_BASE_MASK;
8795 i386_mpx_enabled (void)
8797 const struct gdbarch_tdep *tdep = gdbarch_tdep (get_current_arch ());
8798 const struct target_desc *tdesc = tdep->tdesc;
8800 return (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL);
8803 #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */
8804 #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */
8805 #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */
8806 #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */
8808 /* Find the bound table entry given the pointer location and the base
8809 address of the table. */
8812 i386_mpx_get_bt_entry (CORE_ADDR ptr, CORE_ADDR bd_base)
8816 CORE_ADDR mpx_bd_mask, bd_ptr_r_shift, bd_ptr_l_shift;
8817 CORE_ADDR bt_mask, bt_select_r_shift, bt_select_l_shift;
8818 CORE_ADDR bd_entry_addr;
8821 struct gdbarch *gdbarch = get_current_arch ();
8822 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8825 if (gdbarch_ptr_bit (gdbarch) == 64)
8827 mpx_bd_mask = (CORE_ADDR) MPX_BD_MASK;
8828 bd_ptr_r_shift = 20;
8830 bt_select_r_shift = 3;
8831 bt_select_l_shift = 5;
8832 bt_mask = (CORE_ADDR) MPX_BT_MASK;
8834 if ( sizeof (CORE_ADDR) == 4)
8835 error (_("bound table examination not supported\
8836 for 64-bit process with 32-bit GDB"));
8840 mpx_bd_mask = MPX_BD_MASK_32;
8841 bd_ptr_r_shift = 12;
8843 bt_select_r_shift = 2;
8844 bt_select_l_shift = 4;
8845 bt_mask = MPX_BT_MASK_32;
8848 offset1 = ((ptr & mpx_bd_mask) >> bd_ptr_r_shift) << bd_ptr_l_shift;
8849 bd_entry_addr = bd_base + offset1;
8850 bd_entry = read_memory_typed_address (bd_entry_addr, data_ptr_type);
8852 if ((bd_entry & 0x1) == 0)
8853 error (_("Invalid bounds directory entry at %s."),
8854 paddress (get_current_arch (), bd_entry_addr));
8856 /* Clearing status bit. */
8858 bt_addr = bd_entry & ~bt_select_r_shift;
8859 offset2 = ((ptr & bt_mask) >> bt_select_r_shift) << bt_select_l_shift;
8861 return bt_addr + offset2;
8864 /* Print routine for the mpx bounds. */
8867 i386_mpx_print_bounds (const CORE_ADDR bt_entry[4])
8869 struct ui_out *uiout = current_uiout;
8871 struct gdbarch *gdbarch = get_current_arch ();
8872 CORE_ADDR onecompl = ~((CORE_ADDR) 0);
8873 int bounds_in_map = ((~bt_entry[1] == 0 && bt_entry[0] == onecompl) ? 1 : 0);
8875 if (bounds_in_map == 1)
8877 uiout->text ("Null bounds on map:");
8878 uiout->text (" pointer value = ");
8879 uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]);
8885 uiout->text ("{lbound = ");
8886 uiout->field_core_addr ("lower-bound", gdbarch, bt_entry[0]);
8887 uiout->text (", ubound = ");
8889 /* The upper bound is stored in 1's complement. */
8890 uiout->field_core_addr ("upper-bound", gdbarch, ~bt_entry[1]);
8891 uiout->text ("}: pointer value = ");
8892 uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]);
8894 if (gdbarch_ptr_bit (gdbarch) == 64)
8895 size = ( (~(int64_t) bt_entry[1]) - (int64_t) bt_entry[0]);
8897 size = ( ~((int32_t) bt_entry[1]) - (int32_t) bt_entry[0]);
8899 /* In case the bounds are 0x0 and 0xffff... the difference will be -1.
8900 -1 represents in this sense full memory access, and there is no need
8903 size = (size > -1 ? size + 1 : size);
8904 uiout->text (", size = ");
8905 uiout->field_fmt ("size", "%s", plongest (size));
8907 uiout->text (", metadata = ");
8908 uiout->field_core_addr ("metadata", gdbarch, bt_entry[3]);
8913 /* Implement the command "show mpx bound". */
8916 i386_mpx_info_bounds (char *args, int from_tty)
8918 CORE_ADDR bd_base = 0;
8920 CORE_ADDR bt_entry_addr = 0;
8921 CORE_ADDR bt_entry[4];
8923 struct gdbarch *gdbarch = get_current_arch ();
8924 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8926 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386
8927 || !i386_mpx_enabled ())
8929 printf_unfiltered (_("Intel Memory Protection Extensions not "
8930 "supported on this target.\n"));
8936 printf_unfiltered (_("Address of pointer variable expected.\n"));
8940 addr = parse_and_eval_address (args);
8942 bd_base = i386_mpx_bd_base ();
8943 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8945 memset (bt_entry, 0, sizeof (bt_entry));
8947 for (i = 0; i < 4; i++)
8948 bt_entry[i] = read_memory_typed_address (bt_entry_addr
8949 + i * TYPE_LENGTH (data_ptr_type),
8952 i386_mpx_print_bounds (bt_entry);
8955 /* Implement the command "set mpx bound". */
8958 i386_mpx_set_bounds (char *args, int from_tty)
8960 CORE_ADDR bd_base = 0;
8961 CORE_ADDR addr, lower, upper;
8962 CORE_ADDR bt_entry_addr = 0;
8963 CORE_ADDR bt_entry[2];
8964 const char *input = args;
8966 struct gdbarch *gdbarch = get_current_arch ();
8967 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8968 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8970 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386
8971 || !i386_mpx_enabled ())
8972 error (_("Intel Memory Protection Extensions not supported\
8976 error (_("Pointer value expected."));
8978 addr = value_as_address (parse_to_comma_and_eval (&input));
8980 if (input[0] == ',')
8982 if (input[0] == '\0')
8983 error (_("wrong number of arguments: missing lower and upper bound."));
8984 lower = value_as_address (parse_to_comma_and_eval (&input));
8986 if (input[0] == ',')
8988 if (input[0] == '\0')
8989 error (_("Wrong number of arguments; Missing upper bound."));
8990 upper = value_as_address (parse_to_comma_and_eval (&input));
8992 bd_base = i386_mpx_bd_base ();
8993 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8994 for (i = 0; i < 2; i++)
8995 bt_entry[i] = read_memory_typed_address (bt_entry_addr
8996 + i * TYPE_LENGTH (data_ptr_type),
8998 bt_entry[0] = (uint64_t) lower;
8999 bt_entry[1] = ~(uint64_t) upper;
9001 for (i = 0; i < 2; i++)
9002 write_memory_unsigned_integer (bt_entry_addr
9003 + i * TYPE_LENGTH (data_ptr_type),
9004 TYPE_LENGTH (data_ptr_type), byte_order,
9008 static struct cmd_list_element *mpx_set_cmdlist, *mpx_show_cmdlist;
9010 /* Helper function for the CLI commands. */
9013 set_mpx_cmd (char *args, int from_tty)
9015 help_list (mpx_set_cmdlist, "set mpx ", all_commands, gdb_stdout);
9018 /* Helper function for the CLI commands. */
9021 show_mpx_cmd (char *args, int from_tty)
9023 cmd_show_list (mpx_show_cmdlist, from_tty, "");
9026 /* Provide a prototype to silence -Wmissing-prototypes. */
9027 void _initialize_i386_tdep (void);
9030 _initialize_i386_tdep (void)
9032 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
9034 /* Add the variable that controls the disassembly flavor. */
9035 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
9036 &disassembly_flavor, _("\
9037 Set the disassembly flavor."), _("\
9038 Show the disassembly flavor."), _("\
9039 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
9041 NULL, /* FIXME: i18n: */
9042 &setlist, &showlist);
9044 /* Add the variable that controls the convention for returning
9046 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
9047 &struct_convention, _("\
9048 Set the convention for returning small structs."), _("\
9049 Show the convention for returning small structs."), _("\
9050 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
9053 NULL, /* FIXME: i18n: */
9054 &setlist, &showlist);
9056 /* Add "mpx" prefix for the set commands. */
9058 add_prefix_cmd ("mpx", class_support, set_mpx_cmd, _("\
9059 Set Intel Memory Protection Extensions specific variables."),
9060 &mpx_set_cmdlist, "set mpx ",
9061 0 /* allow-unknown */, &setlist);
9063 /* Add "mpx" prefix for the show commands. */
9065 add_prefix_cmd ("mpx", class_support, show_mpx_cmd, _("\
9066 Show Intel Memory Protection Extensions specific variables."),
9067 &mpx_show_cmdlist, "show mpx ",
9068 0 /* allow-unknown */, &showlist);
9070 /* Add "bound" command for the show mpx commands list. */
9072 add_cmd ("bound", no_class, i386_mpx_info_bounds,
9073 "Show the memory bounds for a given array/pointer storage\
9074 in the bound table.",
9077 /* Add "bound" command for the set mpx commands list. */
9079 add_cmd ("bound", no_class, i386_mpx_set_bounds,
9080 "Set the memory bounds for a given array/pointer storage\
9081 in the bound table.",
9084 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
9085 i386_coff_osabi_sniffer);
9087 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
9088 i386_svr4_init_abi);
9089 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
9090 i386_go32_init_abi);
9092 /* Initialize the i386-specific register groups. */
9093 i386_init_reggroups ();
9095 /* Initialize the standard target descriptions. */
9096 initialize_tdesc_i386 ();
9097 initialize_tdesc_i386_mmx ();
9098 initialize_tdesc_i386_avx ();
9099 initialize_tdesc_i386_mpx ();
9100 initialize_tdesc_i386_avx_mpx ();
9101 initialize_tdesc_i386_avx_avx512 ();
9102 initialize_tdesc_i386_avx_mpx_avx512_pku ();
9104 /* Tell remote stub that we support XML target description. */
9105 register_remote_support_xml ("i386");