1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
37 #include "reggroups.h"
46 #include "exceptions.h"
47 #include "gdb_assert.h"
48 #include "gdb_string.h"
50 #include "i386-tdep.h"
51 #include "i387-tdep.h"
52 #include "i386-xstate.h"
57 #include "features/i386/i386.c"
58 #include "features/i386/i386-avx.c"
59 #include "features/i386/i386-mmx.c"
66 static const char *i386_register_names[] =
68 "eax", "ecx", "edx", "ebx",
69 "esp", "ebp", "esi", "edi",
70 "eip", "eflags", "cs", "ss",
71 "ds", "es", "fs", "gs",
72 "st0", "st1", "st2", "st3",
73 "st4", "st5", "st6", "st7",
74 "fctrl", "fstat", "ftag", "fiseg",
75 "fioff", "foseg", "fooff", "fop",
76 "xmm0", "xmm1", "xmm2", "xmm3",
77 "xmm4", "xmm5", "xmm6", "xmm7",
81 static const char *i386_ymm_names[] =
83 "ymm0", "ymm1", "ymm2", "ymm3",
84 "ymm4", "ymm5", "ymm6", "ymm7",
87 static const char *i386_ymmh_names[] =
89 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
90 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
93 /* Register names for MMX pseudo-registers. */
95 static const char *i386_mmx_names[] =
97 "mm0", "mm1", "mm2", "mm3",
98 "mm4", "mm5", "mm6", "mm7"
101 /* Register names for byte pseudo-registers. */
103 static const char *i386_byte_names[] =
105 "al", "cl", "dl", "bl",
106 "ah", "ch", "dh", "bh"
109 /* Register names for word pseudo-registers. */
111 static const char *i386_word_names[] =
113 "ax", "cx", "dx", "bx",
120 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
122 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
123 int mm0_regnum = tdep->mm0_regnum;
128 regnum -= mm0_regnum;
129 return regnum >= 0 && regnum < tdep->num_mmx_regs;
135 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
137 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
139 regnum -= tdep->al_regnum;
140 return regnum >= 0 && regnum < tdep->num_byte_regs;
146 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
148 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
150 regnum -= tdep->ax_regnum;
151 return regnum >= 0 && regnum < tdep->num_word_regs;
154 /* Dword register? */
157 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
159 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
160 int eax_regnum = tdep->eax_regnum;
165 regnum -= eax_regnum;
166 return regnum >= 0 && regnum < tdep->num_dword_regs;
170 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
172 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
173 int ymm0h_regnum = tdep->ymm0h_regnum;
175 if (ymm0h_regnum < 0)
178 regnum -= ymm0h_regnum;
179 return regnum >= 0 && regnum < tdep->num_ymm_regs;
185 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
187 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
188 int ymm0_regnum = tdep->ymm0_regnum;
193 regnum -= ymm0_regnum;
194 return regnum >= 0 && regnum < tdep->num_ymm_regs;
200 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
202 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
203 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
205 if (num_xmm_regs == 0)
208 regnum -= I387_XMM0_REGNUM (tdep);
209 return regnum >= 0 && regnum < num_xmm_regs;
213 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
215 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
217 if (I387_NUM_XMM_REGS (tdep) == 0)
220 return (regnum == I387_MXCSR_REGNUM (tdep));
226 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
228 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
230 if (I387_ST0_REGNUM (tdep) < 0)
233 return (I387_ST0_REGNUM (tdep) <= regnum
234 && regnum < I387_FCTRL_REGNUM (tdep));
238 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
240 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
242 if (I387_ST0_REGNUM (tdep) < 0)
245 return (I387_FCTRL_REGNUM (tdep) <= regnum
246 && regnum < I387_XMM0_REGNUM (tdep));
249 /* Return the name of register REGNUM, or the empty string if it is
250 an anonymous register. */
253 i386_register_name (struct gdbarch *gdbarch, int regnum)
255 /* Hide the upper YMM registers. */
256 if (i386_ymmh_regnum_p (gdbarch, regnum))
259 return tdesc_register_name (gdbarch, regnum);
262 /* Return the name of register REGNUM. */
265 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
267 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
268 if (i386_mmx_regnum_p (gdbarch, regnum))
269 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
270 else if (i386_ymm_regnum_p (gdbarch, regnum))
271 return i386_ymm_names[regnum - tdep->ymm0_regnum];
272 else if (i386_byte_regnum_p (gdbarch, regnum))
273 return i386_byte_names[regnum - tdep->al_regnum];
274 else if (i386_word_regnum_p (gdbarch, regnum))
275 return i386_word_names[regnum - tdep->ax_regnum];
277 internal_error (__FILE__, __LINE__, _("invalid regnum"));
280 /* Convert a dbx register number REG to the appropriate register
281 number used by GDB. */
284 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
286 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
288 /* This implements what GCC calls the "default" register map
289 (dbx_register_map[]). */
291 if (reg >= 0 && reg <= 7)
293 /* General-purpose registers. The debug info calls %ebp
294 register 4, and %esp register 5. */
301 else if (reg >= 12 && reg <= 19)
303 /* Floating-point registers. */
304 return reg - 12 + I387_ST0_REGNUM (tdep);
306 else if (reg >= 21 && reg <= 28)
309 int ymm0_regnum = tdep->ymm0_regnum;
312 && i386_xmm_regnum_p (gdbarch, reg))
313 return reg - 21 + ymm0_regnum;
315 return reg - 21 + I387_XMM0_REGNUM (tdep);
317 else if (reg >= 29 && reg <= 36)
320 return reg - 29 + I387_MM0_REGNUM (tdep);
323 /* This will hopefully provoke a warning. */
324 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
327 /* Convert SVR4 register number REG to the appropriate register number
331 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
333 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
335 /* This implements the GCC register map that tries to be compatible
336 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
338 /* The SVR4 register numbering includes %eip and %eflags, and
339 numbers the floating point registers differently. */
340 if (reg >= 0 && reg <= 9)
342 /* General-purpose registers. */
345 else if (reg >= 11 && reg <= 18)
347 /* Floating-point registers. */
348 return reg - 11 + I387_ST0_REGNUM (tdep);
350 else if (reg >= 21 && reg <= 36)
352 /* The SSE and MMX registers have the same numbers as with dbx. */
353 return i386_dbx_reg_to_regnum (gdbarch, reg);
358 case 37: return I387_FCTRL_REGNUM (tdep);
359 case 38: return I387_FSTAT_REGNUM (tdep);
360 case 39: return I387_MXCSR_REGNUM (tdep);
361 case 40: return I386_ES_REGNUM;
362 case 41: return I386_CS_REGNUM;
363 case 42: return I386_SS_REGNUM;
364 case 43: return I386_DS_REGNUM;
365 case 44: return I386_FS_REGNUM;
366 case 45: return I386_GS_REGNUM;
369 /* This will hopefully provoke a warning. */
370 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
375 /* This is the variable that is set with "set disassembly-flavor", and
376 its legitimate values. */
377 static const char att_flavor[] = "att";
378 static const char intel_flavor[] = "intel";
379 static const char *const valid_flavors[] =
385 static const char *disassembly_flavor = att_flavor;
388 /* Use the program counter to determine the contents and size of a
389 breakpoint instruction. Return a pointer to a string of bytes that
390 encode a breakpoint instruction, store the length of the string in
391 *LEN and optionally adjust *PC to point to the correct memory
392 location for inserting the breakpoint.
394 On the i386 we have a single breakpoint that fits in a single byte
395 and can be inserted anywhere.
397 This function is 64-bit safe. */
399 static const gdb_byte *
400 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
402 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */
404 *len = sizeof (break_insn);
408 /* Displaced instruction handling. */
410 /* Skip the legacy instruction prefixes in INSN.
411 Not all prefixes are valid for any particular insn
412 but we needn't care, the insn will fault if it's invalid.
413 The result is a pointer to the first opcode byte,
414 or NULL if we run off the end of the buffer. */
417 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
419 gdb_byte *end = insn + max_len;
425 case DATA_PREFIX_OPCODE:
426 case ADDR_PREFIX_OPCODE:
427 case CS_PREFIX_OPCODE:
428 case DS_PREFIX_OPCODE:
429 case ES_PREFIX_OPCODE:
430 case FS_PREFIX_OPCODE:
431 case GS_PREFIX_OPCODE:
432 case SS_PREFIX_OPCODE:
433 case LOCK_PREFIX_OPCODE:
434 case REPE_PREFIX_OPCODE:
435 case REPNE_PREFIX_OPCODE:
447 i386_absolute_jmp_p (const gdb_byte *insn)
449 /* jmp far (absolute address in operand). */
455 /* jump near, absolute indirect (/4). */
456 if ((insn[1] & 0x38) == 0x20)
459 /* jump far, absolute indirect (/5). */
460 if ((insn[1] & 0x38) == 0x28)
468 i386_absolute_call_p (const gdb_byte *insn)
470 /* call far, absolute. */
476 /* Call near, absolute indirect (/2). */
477 if ((insn[1] & 0x38) == 0x10)
480 /* Call far, absolute indirect (/3). */
481 if ((insn[1] & 0x38) == 0x18)
489 i386_ret_p (const gdb_byte *insn)
493 case 0xc2: /* ret near, pop N bytes. */
494 case 0xc3: /* ret near */
495 case 0xca: /* ret far, pop N bytes. */
496 case 0xcb: /* ret far */
497 case 0xcf: /* iret */
506 i386_call_p (const gdb_byte *insn)
508 if (i386_absolute_call_p (insn))
511 /* call near, relative. */
518 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
519 length in bytes. Otherwise, return zero. */
522 i386_syscall_p (const gdb_byte *insn, int *lengthp)
524 /* Is it 'int $0x80'? */
525 if ((insn[0] == 0xcd && insn[1] == 0x80)
526 /* Or is it 'sysenter'? */
527 || (insn[0] == 0x0f && insn[1] == 0x34)
528 /* Or is it 'syscall'? */
529 || (insn[0] == 0x0f && insn[1] == 0x05))
538 /* Some kernels may run one past a syscall insn, so we have to cope.
539 Otherwise this is just simple_displaced_step_copy_insn. */
541 struct displaced_step_closure *
542 i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
543 CORE_ADDR from, CORE_ADDR to,
544 struct regcache *regs)
546 size_t len = gdbarch_max_insn_length (gdbarch);
547 gdb_byte *buf = xmalloc (len);
549 read_memory (from, buf, len);
551 /* GDB may get control back after the insn after the syscall.
552 Presumably this is a kernel bug.
553 If this is a syscall, make sure there's a nop afterwards. */
558 insn = i386_skip_prefixes (buf, len);
559 if (insn != NULL && i386_syscall_p (insn, &syscall_length))
560 insn[syscall_length] = NOP_OPCODE;
563 write_memory (to, buf, len);
567 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
568 paddress (gdbarch, from), paddress (gdbarch, to));
569 displaced_step_dump_bytes (gdb_stdlog, buf, len);
572 return (struct displaced_step_closure *) buf;
575 /* Fix up the state of registers and memory after having single-stepped
576 a displaced instruction. */
579 i386_displaced_step_fixup (struct gdbarch *gdbarch,
580 struct displaced_step_closure *closure,
581 CORE_ADDR from, CORE_ADDR to,
582 struct regcache *regs)
584 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
586 /* The offset we applied to the instruction's address.
587 This could well be negative (when viewed as a signed 32-bit
588 value), but ULONGEST won't reflect that, so take care when
590 ULONGEST insn_offset = to - from;
592 /* Since we use simple_displaced_step_copy_insn, our closure is a
593 copy of the instruction. */
594 gdb_byte *insn = (gdb_byte *) closure;
595 /* The start of the insn, needed in case we see some prefixes. */
596 gdb_byte *insn_start = insn;
599 fprintf_unfiltered (gdb_stdlog,
600 "displaced: fixup (%s, %s), "
601 "insn = 0x%02x 0x%02x ...\n",
602 paddress (gdbarch, from), paddress (gdbarch, to),
605 /* The list of issues to contend with here is taken from
606 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
607 Yay for Free Software! */
609 /* Relocate the %eip, if necessary. */
611 /* The instruction recognizers we use assume any leading prefixes
612 have been skipped. */
614 /* This is the size of the buffer in closure. */
615 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
616 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
617 /* If there are too many prefixes, just ignore the insn.
618 It will fault when run. */
623 /* Except in the case of absolute or indirect jump or call
624 instructions, or a return instruction, the new eip is relative to
625 the displaced instruction; make it relative. Well, signal
626 handler returns don't need relocation either, but we use the
627 value of %eip to recognize those; see below. */
628 if (! i386_absolute_jmp_p (insn)
629 && ! i386_absolute_call_p (insn)
630 && ! i386_ret_p (insn))
635 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
637 /* A signal trampoline system call changes the %eip, resuming
638 execution of the main program after the signal handler has
639 returned. That makes them like 'return' instructions; we
640 shouldn't relocate %eip.
642 But most system calls don't, and we do need to relocate %eip.
644 Our heuristic for distinguishing these cases: if stepping
645 over the system call instruction left control directly after
646 the instruction, the we relocate --- control almost certainly
647 doesn't belong in the displaced copy. Otherwise, we assume
648 the instruction has put control where it belongs, and leave
649 it unrelocated. Goodness help us if there are PC-relative
651 if (i386_syscall_p (insn, &insn_len)
652 && orig_eip != to + (insn - insn_start) + insn_len
653 /* GDB can get control back after the insn after the syscall.
654 Presumably this is a kernel bug.
655 i386_displaced_step_copy_insn ensures its a nop,
656 we add one to the length for it. */
657 && orig_eip != to + (insn - insn_start) + insn_len + 1)
660 fprintf_unfiltered (gdb_stdlog,
661 "displaced: syscall changed %%eip; "
666 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
668 /* If we just stepped over a breakpoint insn, we don't backup
669 the pc on purpose; this is to match behaviour without
672 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
675 fprintf_unfiltered (gdb_stdlog,
677 "relocated %%eip from %s to %s\n",
678 paddress (gdbarch, orig_eip),
679 paddress (gdbarch, eip));
683 /* If the instruction was PUSHFL, then the TF bit will be set in the
684 pushed value, and should be cleared. We'll leave this for later,
685 since GDB already messes up the TF flag when stepping over a
688 /* If the instruction was a call, the return address now atop the
689 stack is the address following the copied instruction. We need
690 to make it the address following the original instruction. */
691 if (i386_call_p (insn))
695 const ULONGEST retaddr_len = 4;
697 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
698 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
699 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
700 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
703 fprintf_unfiltered (gdb_stdlog,
704 "displaced: relocated return addr at %s to %s\n",
705 paddress (gdbarch, esp),
706 paddress (gdbarch, retaddr));
711 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
713 target_write_memory (*to, buf, len);
718 i386_relocate_instruction (struct gdbarch *gdbarch,
719 CORE_ADDR *to, CORE_ADDR oldloc)
721 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
722 gdb_byte buf[I386_MAX_INSN_LEN];
723 int offset = 0, rel32, newrel;
725 gdb_byte *insn = buf;
727 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
729 insn_length = gdb_buffered_insn_length (gdbarch, insn,
730 I386_MAX_INSN_LEN, oldloc);
732 /* Get past the prefixes. */
733 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
735 /* Adjust calls with 32-bit relative addresses as push/jump, with
736 the address pushed being the location where the original call in
737 the user program would return to. */
740 gdb_byte push_buf[16];
741 unsigned int ret_addr;
743 /* Where "ret" in the original code will return to. */
744 ret_addr = oldloc + insn_length;
745 push_buf[0] = 0x68; /* pushq $... */
746 memcpy (&push_buf[1], &ret_addr, 4);
748 append_insns (to, 5, push_buf);
750 /* Convert the relative call to a relative jump. */
753 /* Adjust the destination offset. */
754 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
755 newrel = (oldloc - *to) + rel32;
756 store_signed_integer (insn + 1, 4, byte_order, newrel);
759 fprintf_unfiltered (gdb_stdlog,
760 "Adjusted insn rel32=%s at %s to"
762 hex_string (rel32), paddress (gdbarch, oldloc),
763 hex_string (newrel), paddress (gdbarch, *to));
765 /* Write the adjusted jump into its displaced location. */
766 append_insns (to, 5, insn);
770 /* Adjust jumps with 32-bit relative addresses. Calls are already
774 /* Adjust conditional jumps. */
775 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
780 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
781 newrel = (oldloc - *to) + rel32;
782 store_signed_integer (insn + offset, 4, byte_order, newrel);
784 fprintf_unfiltered (gdb_stdlog,
785 "Adjusted insn rel32=%s at %s to"
787 hex_string (rel32), paddress (gdbarch, oldloc),
788 hex_string (newrel), paddress (gdbarch, *to));
791 /* Write the adjusted instructions into their displaced
793 append_insns (to, insn_length, buf);
797 #ifdef I386_REGNO_TO_SYMMETRY
798 #error "The Sequent Symmetry is no longer supported."
801 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
802 and %esp "belong" to the calling function. Therefore these
803 registers should be saved if they're going to be modified. */
805 /* The maximum number of saved registers. This should include all
806 registers mentioned above, and %eip. */
807 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
809 struct i386_frame_cache
817 /* Saved registers. */
818 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
823 /* Stack space reserved for local variables. */
827 /* Allocate and initialize a frame cache. */
829 static struct i386_frame_cache *
830 i386_alloc_frame_cache (void)
832 struct i386_frame_cache *cache;
835 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
840 cache->sp_offset = -4;
843 /* Saved registers. We initialize these to -1 since zero is a valid
844 offset (that's where %ebp is supposed to be stored). */
845 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
846 cache->saved_regs[i] = -1;
848 cache->saved_sp_reg = -1;
849 cache->pc_in_eax = 0;
851 /* Frameless until proven otherwise. */
857 /* If the instruction at PC is a jump, return the address of its
858 target. Otherwise, return PC. */
861 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
863 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
868 if (target_read_memory (pc, &op, 1))
874 op = read_memory_unsigned_integer (pc + 1, 1, byte_order);
880 /* Relative jump: if data16 == 0, disp32, else disp16. */
883 delta = read_memory_integer (pc + 2, 2, byte_order);
885 /* Include the size of the jmp instruction (including the
891 delta = read_memory_integer (pc + 1, 4, byte_order);
893 /* Include the size of the jmp instruction. */
898 /* Relative jump, disp8 (ignore data16). */
899 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
908 /* Check whether PC points at a prologue for a function returning a
909 structure or union. If so, it updates CACHE and returns the
910 address of the first instruction after the code sequence that
911 removes the "hidden" argument from the stack or CURRENT_PC,
912 whichever is smaller. Otherwise, return PC. */
915 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
916 struct i386_frame_cache *cache)
918 /* Functions that return a structure or union start with:
921 xchgl %eax, (%esp) 0x87 0x04 0x24
922 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
924 (the System V compiler puts out the second `xchg' instruction,
925 and the assembler doesn't try to optimize it, so the 'sib' form
926 gets generated). This sequence is used to get the address of the
927 return buffer for a function that returns a structure. */
928 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
929 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
933 if (current_pc <= pc)
936 if (target_read_memory (pc, &op, 1))
939 if (op != 0x58) /* popl %eax */
942 if (target_read_memory (pc + 1, buf, 4))
945 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
948 if (current_pc == pc)
950 cache->sp_offset += 4;
954 if (current_pc == pc + 1)
956 cache->pc_in_eax = 1;
960 if (buf[1] == proto1[1])
967 i386_skip_probe (CORE_ADDR pc)
969 /* A function may start with
983 if (target_read_memory (pc, &op, 1))
986 if (op == 0x68 || op == 0x6a)
990 /* Skip past the `pushl' instruction; it has either a one-byte or a
991 four-byte operand, depending on the opcode. */
997 /* Read the following 8 bytes, which should be `call _probe' (6
998 bytes) followed by `addl $4,%esp' (2 bytes). */
999 read_memory (pc + delta, buf, sizeof (buf));
1000 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
1001 pc += delta + sizeof (buf);
1007 /* GCC 4.1 and later, can put code in the prologue to realign the
1008 stack pointer. Check whether PC points to such code, and update
1009 CACHE accordingly. Return the first instruction after the code
1010 sequence or CURRENT_PC, whichever is smaller. If we don't
1011 recognize the code, return PC. */
1014 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1015 struct i386_frame_cache *cache)
1017 /* There are 2 code sequences to re-align stack before the frame
1020 1. Use a caller-saved saved register:
1026 2. Use a callee-saved saved register:
1033 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1035 0x83 0xe4 0xf0 andl $-16, %esp
1036 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1041 int offset, offset_and;
1042 static int regnums[8] = {
1043 I386_EAX_REGNUM, /* %eax */
1044 I386_ECX_REGNUM, /* %ecx */
1045 I386_EDX_REGNUM, /* %edx */
1046 I386_EBX_REGNUM, /* %ebx */
1047 I386_ESP_REGNUM, /* %esp */
1048 I386_EBP_REGNUM, /* %ebp */
1049 I386_ESI_REGNUM, /* %esi */
1050 I386_EDI_REGNUM /* %edi */
1053 if (target_read_memory (pc, buf, sizeof buf))
1056 /* Check caller-saved saved register. The first instruction has
1057 to be "leal 4(%esp), %reg". */
1058 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1060 /* MOD must be binary 10 and R/M must be binary 100. */
1061 if ((buf[1] & 0xc7) != 0x44)
1064 /* REG has register number. */
1065 reg = (buf[1] >> 3) & 7;
1070 /* Check callee-saved saved register. The first instruction
1071 has to be "pushl %reg". */
1072 if ((buf[0] & 0xf8) != 0x50)
1078 /* The next instruction has to be "leal 8(%esp), %reg". */
1079 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1082 /* MOD must be binary 10 and R/M must be binary 100. */
1083 if ((buf[2] & 0xc7) != 0x44)
1086 /* REG has register number. Registers in pushl and leal have to
1088 if (reg != ((buf[2] >> 3) & 7))
1094 /* Rigister can't be %esp nor %ebp. */
1095 if (reg == 4 || reg == 5)
1098 /* The next instruction has to be "andl $-XXX, %esp". */
1099 if (buf[offset + 1] != 0xe4
1100 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1103 offset_and = offset;
1104 offset += buf[offset] == 0x81 ? 6 : 3;
1106 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1107 0xfc. REG must be binary 110 and MOD must be binary 01. */
1108 if (buf[offset] != 0xff
1109 || buf[offset + 2] != 0xfc
1110 || (buf[offset + 1] & 0xf8) != 0x70)
1113 /* R/M has register. Registers in leal and pushl have to be the
1115 if (reg != (buf[offset + 1] & 7))
1118 if (current_pc > pc + offset_and)
1119 cache->saved_sp_reg = regnums[reg];
1121 return min (pc + offset + 3, current_pc);
1124 /* Maximum instruction length we need to handle. */
1125 #define I386_MAX_MATCHED_INSN_LEN 6
1127 /* Instruction description. */
1131 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
1132 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
1135 /* Return whether instruction at PC matches PATTERN. */
1138 i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern)
1142 if (target_read_memory (pc, &op, 1))
1145 if ((op & pattern.mask[0]) == pattern.insn[0])
1147 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1148 int insn_matched = 1;
1151 gdb_assert (pattern.len > 1);
1152 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN);
1154 if (target_read_memory (pc + 1, buf, pattern.len - 1))
1157 for (i = 1; i < pattern.len; i++)
1159 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i])
1162 return insn_matched;
1167 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1168 the first instruction description that matches. Otherwise, return
1171 static struct i386_insn *
1172 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns)
1174 struct i386_insn *pattern;
1176 for (pattern = insn_patterns; pattern->len > 0; pattern++)
1178 if (i386_match_pattern (pc, *pattern))
1185 /* Return whether PC points inside a sequence of instructions that
1186 matches INSN_PATTERNS. */
1189 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns)
1191 CORE_ADDR current_pc;
1194 struct i386_insn *insn;
1196 insn = i386_match_insn (pc, insn_patterns);
1201 ix = insn - insn_patterns;
1202 for (i = ix - 1; i >= 0; i--)
1204 current_pc -= insn_patterns[i].len;
1206 if (!i386_match_pattern (current_pc, insn_patterns[i]))
1210 current_pc = pc + insn->len;
1211 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++)
1213 if (!i386_match_pattern (current_pc, *insn))
1216 current_pc += insn->len;
1222 /* Some special instructions that might be migrated by GCC into the
1223 part of the prologue that sets up the new stack frame. Because the
1224 stack frame hasn't been setup yet, no registers have been saved
1225 yet, and only the scratch registers %eax, %ecx and %edx can be
1228 struct i386_insn i386_frame_setup_skip_insns[] =
1230 /* Check for `movb imm8, r' and `movl imm32, r'.
1232 ??? Should we handle 16-bit operand-sizes here? */
1234 /* `movb imm8, %al' and `movb imm8, %ah' */
1235 /* `movb imm8, %cl' and `movb imm8, %ch' */
1236 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1237 /* `movb imm8, %dl' and `movb imm8, %dh' */
1238 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1239 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1240 { 5, { 0xb8 }, { 0xfe } },
1241 /* `movl imm32, %edx' */
1242 { 5, { 0xba }, { 0xff } },
1244 /* Check for `mov imm32, r32'. Note that there is an alternative
1245 encoding for `mov m32, %eax'.
1247 ??? Should we handle SIB adressing here?
1248 ??? Should we handle 16-bit operand-sizes here? */
1250 /* `movl m32, %eax' */
1251 { 5, { 0xa1 }, { 0xff } },
1252 /* `movl m32, %eax' and `mov; m32, %ecx' */
1253 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1254 /* `movl m32, %edx' */
1255 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1257 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1258 Because of the symmetry, there are actually two ways to encode
1259 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1260 opcode bytes 0x31 and 0x33 for `xorl'. */
1262 /* `subl %eax, %eax' */
1263 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1264 /* `subl %ecx, %ecx' */
1265 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1266 /* `subl %edx, %edx' */
1267 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1268 /* `xorl %eax, %eax' */
1269 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1270 /* `xorl %ecx, %ecx' */
1271 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1272 /* `xorl %edx, %edx' */
1273 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1278 /* Check whether PC points to a no-op instruction. */
1280 i386_skip_noop (CORE_ADDR pc)
1285 if (target_read_memory (pc, &op, 1))
1291 /* Ignore `nop' instruction. */
1295 if (target_read_memory (pc, &op, 1))
1299 /* Ignore no-op instruction `mov %edi, %edi'.
1300 Microsoft system dlls often start with
1301 a `mov %edi,%edi' instruction.
1302 The 5 bytes before the function start are
1303 filled with `nop' instructions.
1304 This pattern can be used for hot-patching:
1305 The `mov %edi, %edi' instruction can be replaced by a
1306 near jump to the location of the 5 `nop' instructions
1307 which can be replaced by a 32-bit jump to anywhere
1308 in the 32-bit address space. */
1310 else if (op == 0x8b)
1312 if (target_read_memory (pc + 1, &op, 1))
1318 if (target_read_memory (pc, &op, 1))
1328 /* Check whether PC points at a code that sets up a new stack frame.
1329 If so, it updates CACHE and returns the address of the first
1330 instruction after the sequence that sets up the frame or LIMIT,
1331 whichever is smaller. If we don't recognize the code, return PC. */
1334 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1335 CORE_ADDR pc, CORE_ADDR limit,
1336 struct i386_frame_cache *cache)
1338 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1339 struct i386_insn *insn;
1346 if (target_read_memory (pc, &op, 1))
1349 if (op == 0x55) /* pushl %ebp */
1351 /* Take into account that we've executed the `pushl %ebp' that
1352 starts this instruction sequence. */
1353 cache->saved_regs[I386_EBP_REGNUM] = 0;
1354 cache->sp_offset += 4;
1357 /* If that's all, return now. */
1361 /* Check for some special instructions that might be migrated by
1362 GCC into the prologue and skip them. At this point in the
1363 prologue, code should only touch the scratch registers %eax,
1364 %ecx and %edx, so while the number of posibilities is sheer,
1367 Make sure we only skip these instructions if we later see the
1368 `movl %esp, %ebp' that actually sets up the frame. */
1369 while (pc + skip < limit)
1371 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1378 /* If that's all, return now. */
1379 if (limit <= pc + skip)
1382 if (target_read_memory (pc + skip, &op, 1))
1385 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1389 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1394 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1402 /* OK, we actually have a frame. We just don't know how large
1403 it is yet. Set its size to zero. We'll adjust it if
1404 necessary. We also now commit to skipping the special
1405 instructions mentioned before. */
1409 /* If that's all, return now. */
1413 /* Check for stack adjustment
1417 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1418 reg, so we don't have to worry about a data16 prefix. */
1419 if (target_read_memory (pc, &op, 1))
1423 /* `subl' with 8-bit immediate. */
1424 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1425 /* Some instruction starting with 0x83 other than `subl'. */
1428 /* `subl' with signed 8-bit immediate (though it wouldn't
1429 make sense to be negative). */
1430 cache->locals = read_memory_integer (pc + 2, 1, byte_order);
1433 else if (op == 0x81)
1435 /* Maybe it is `subl' with a 32-bit immediate. */
1436 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1437 /* Some instruction starting with 0x81 other than `subl'. */
1440 /* It is `subl' with a 32-bit immediate. */
1441 cache->locals = read_memory_integer (pc + 2, 4, byte_order);
1446 /* Some instruction other than `subl'. */
1450 else if (op == 0xc8) /* enter */
1452 cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order);
1459 /* Check whether PC points at code that saves registers on the stack.
1460 If so, it updates CACHE and returns the address of the first
1461 instruction after the register saves or CURRENT_PC, whichever is
1462 smaller. Otherwise, return PC. */
1465 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1466 struct i386_frame_cache *cache)
1468 CORE_ADDR offset = 0;
1472 if (cache->locals > 0)
1473 offset -= cache->locals;
1474 for (i = 0; i < 8 && pc < current_pc; i++)
1476 if (target_read_memory (pc, &op, 1))
1478 if (op < 0x50 || op > 0x57)
1482 cache->saved_regs[op - 0x50] = offset;
1483 cache->sp_offset += 4;
1490 /* Do a full analysis of the prologue at PC and update CACHE
1491 accordingly. Bail out early if CURRENT_PC is reached. Return the
1492 address where the analysis stopped.
1494 We handle these cases:
1496 The startup sequence can be at the start of the function, or the
1497 function can start with a branch to startup code at the end.
1499 %ebp can be set up with either the 'enter' instruction, or "pushl
1500 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1501 once used in the System V compiler).
1503 Local space is allocated just below the saved %ebp by either the
1504 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1505 16-bit unsigned argument for space to allocate, and the 'addl'
1506 instruction could have either a signed byte, or 32-bit immediate.
1508 Next, the registers used by this function are pushed. With the
1509 System V compiler they will always be in the order: %edi, %esi,
1510 %ebx (and sometimes a harmless bug causes it to also save but not
1511 restore %eax); however, the code below is willing to see the pushes
1512 in any order, and will handle up to 8 of them.
1514 If the setup sequence is at the end of the function, then the next
1515 instruction will be a branch back to the start. */
1518 i386_analyze_prologue (struct gdbarch *gdbarch,
1519 CORE_ADDR pc, CORE_ADDR current_pc,
1520 struct i386_frame_cache *cache)
1522 pc = i386_skip_noop (pc);
1523 pc = i386_follow_jump (gdbarch, pc);
1524 pc = i386_analyze_struct_return (pc, current_pc, cache);
1525 pc = i386_skip_probe (pc);
1526 pc = i386_analyze_stack_align (pc, current_pc, cache);
1527 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1528 return i386_analyze_register_saves (pc, current_pc, cache);
1531 /* Return PC of first real instruction. */
1534 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1536 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1538 static gdb_byte pic_pat[6] =
1540 0xe8, 0, 0, 0, 0, /* call 0x0 */
1541 0x5b, /* popl %ebx */
1543 struct i386_frame_cache cache;
1549 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1550 if (cache.locals < 0)
1553 /* Found valid frame setup. */
1555 /* The native cc on SVR4 in -K PIC mode inserts the following code
1556 to get the address of the global offset table (GOT) into register
1561 movl %ebx,x(%ebp) (optional)
1564 This code is with the rest of the prologue (at the end of the
1565 function), so we have to skip it to get to the first real
1566 instruction at the start of the function. */
1568 for (i = 0; i < 6; i++)
1570 if (target_read_memory (pc + i, &op, 1))
1573 if (pic_pat[i] != op)
1580 if (target_read_memory (pc + delta, &op, 1))
1583 if (op == 0x89) /* movl %ebx, x(%ebp) */
1585 op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order);
1587 if (op == 0x5d) /* One byte offset from %ebp. */
1589 else if (op == 0x9d) /* Four byte offset from %ebp. */
1591 else /* Unexpected instruction. */
1594 if (target_read_memory (pc + delta, &op, 1))
1599 if (delta > 0 && op == 0x81
1600 && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order)
1607 /* If the function starts with a branch (to startup code at the end)
1608 the last instruction should bring us back to the first
1609 instruction of the real code. */
1610 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1611 pc = i386_follow_jump (gdbarch, pc);
1616 /* Check that the code pointed to by PC corresponds to a call to
1617 __main, skip it if so. Return PC otherwise. */
1620 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1622 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1625 if (target_read_memory (pc, &op, 1))
1631 if (target_read_memory (pc + 1, buf, sizeof buf) == 0)
1633 /* Make sure address is computed correctly as a 32bit
1634 integer even if CORE_ADDR is 64 bit wide. */
1635 struct minimal_symbol *s;
1636 CORE_ADDR call_dest;
1638 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1639 call_dest = call_dest & 0xffffffffU;
1640 s = lookup_minimal_symbol_by_pc (call_dest);
1642 && SYMBOL_LINKAGE_NAME (s) != NULL
1643 && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0)
1651 /* This function is 64-bit safe. */
1654 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1658 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1659 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1663 /* Normal frames. */
1666 i386_frame_cache_1 (struct frame_info *this_frame,
1667 struct i386_frame_cache *cache)
1669 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1670 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1674 cache->pc = get_frame_func (this_frame);
1676 /* In principle, for normal frames, %ebp holds the frame pointer,
1677 which holds the base address for the current stack frame.
1678 However, for functions that don't need it, the frame pointer is
1679 optional. For these "frameless" functions the frame pointer is
1680 actually the frame pointer of the calling frame. Signal
1681 trampolines are just a special case of a "frameless" function.
1682 They (usually) share their frame pointer with the frame that was
1683 in progress when the signal occurred. */
1685 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1686 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1687 if (cache->base == 0)
1693 /* For normal frames, %eip is stored at 4(%ebp). */
1694 cache->saved_regs[I386_EIP_REGNUM] = 4;
1697 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
1700 if (cache->locals < 0)
1702 /* We didn't find a valid frame, which means that CACHE->base
1703 currently holds the frame pointer for our calling frame. If
1704 we're at the start of a function, or somewhere half-way its
1705 prologue, the function's frame probably hasn't been fully
1706 setup yet. Try to reconstruct the base address for the stack
1707 frame by looking at the stack pointer. For truly "frameless"
1708 functions this might work too. */
1710 if (cache->saved_sp_reg != -1)
1712 /* Saved stack pointer has been saved. */
1713 get_frame_register (this_frame, cache->saved_sp_reg, buf);
1714 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
1716 /* We're halfway aligning the stack. */
1717 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
1718 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
1720 /* This will be added back below. */
1721 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
1723 else if (cache->pc != 0
1724 || target_read_memory (get_frame_pc (this_frame), buf, 1))
1726 /* We're in a known function, but did not find a frame
1727 setup. Assume that the function does not use %ebp.
1728 Alternatively, we may have jumped to an invalid
1729 address; in that case there is definitely no new
1731 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1732 cache->base = extract_unsigned_integer (buf, 4, byte_order)
1736 /* We're in an unknown function. We could not find the start
1737 of the function to analyze the prologue; our best option is
1738 to assume a typical frame layout with the caller's %ebp
1740 cache->saved_regs[I386_EBP_REGNUM] = 0;
1743 if (cache->saved_sp_reg != -1)
1745 /* Saved stack pointer has been saved (but the SAVED_SP_REG
1746 register may be unavailable). */
1747 if (cache->saved_sp == 0
1748 && frame_register_read (this_frame, cache->saved_sp_reg, buf))
1749 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
1751 /* Now that we have the base address for the stack frame we can
1752 calculate the value of %esp in the calling frame. */
1753 else if (cache->saved_sp == 0)
1754 cache->saved_sp = cache->base + 8;
1756 /* Adjust all the saved registers such that they contain addresses
1757 instead of offsets. */
1758 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1759 if (cache->saved_regs[i] != -1)
1760 cache->saved_regs[i] += cache->base;
1765 static struct i386_frame_cache *
1766 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
1768 volatile struct gdb_exception ex;
1769 struct i386_frame_cache *cache;
1774 cache = i386_alloc_frame_cache ();
1775 *this_cache = cache;
1777 TRY_CATCH (ex, RETURN_MASK_ERROR)
1779 i386_frame_cache_1 (this_frame, cache);
1781 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
1782 throw_exception (ex);
1788 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
1789 struct frame_id *this_id)
1791 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1793 /* This marks the outermost frame. */
1794 if (cache->base == 0)
1797 /* See the end of i386_push_dummy_call. */
1798 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
1801 static enum unwind_stop_reason
1802 i386_frame_unwind_stop_reason (struct frame_info *this_frame,
1805 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1808 return UNWIND_UNAVAILABLE;
1810 /* This marks the outermost frame. */
1811 if (cache->base == 0)
1812 return UNWIND_OUTERMOST;
1814 return UNWIND_NO_REASON;
1817 static struct value *
1818 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
1821 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1823 gdb_assert (regnum >= 0);
1825 /* The System V ABI says that:
1827 "The flags register contains the system flags, such as the
1828 direction flag and the carry flag. The direction flag must be
1829 set to the forward (that is, zero) direction before entry and
1830 upon exit from a function. Other user flags have no specified
1831 role in the standard calling sequence and are not preserved."
1833 To guarantee the "upon exit" part of that statement we fake a
1834 saved flags register that has its direction flag cleared.
1836 Note that GCC doesn't seem to rely on the fact that the direction
1837 flag is cleared after a function return; it always explicitly
1838 clears the flag before operations where it matters.
1840 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1841 right thing to do. The way we fake the flags register here makes
1842 it impossible to change it. */
1844 if (regnum == I386_EFLAGS_REGNUM)
1848 val = get_frame_register_unsigned (this_frame, regnum);
1850 return frame_unwind_got_constant (this_frame, regnum, val);
1853 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
1854 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
1856 if (regnum == I386_ESP_REGNUM
1857 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1))
1859 /* If the SP has been saved, but we don't know where, then this
1860 means that SAVED_SP_REG register was found unavailable back
1861 when we built the cache. */
1862 if (cache->saved_sp == 0)
1863 return frame_unwind_got_register (this_frame, regnum,
1864 cache->saved_sp_reg);
1866 return frame_unwind_got_constant (this_frame, regnum,
1870 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
1871 return frame_unwind_got_memory (this_frame, regnum,
1872 cache->saved_regs[regnum]);
1874 return frame_unwind_got_register (this_frame, regnum, regnum);
1877 static const struct frame_unwind i386_frame_unwind =
1880 i386_frame_unwind_stop_reason,
1882 i386_frame_prev_register,
1884 default_frame_sniffer
1887 /* Normal frames, but in a function epilogue. */
1889 /* The epilogue is defined here as the 'ret' instruction, which will
1890 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1891 the function's stack frame. */
1894 i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1897 struct symtab *symtab;
1899 symtab = find_pc_symtab (pc);
1900 if (symtab && symtab->epilogue_unwind_valid)
1903 if (target_read_memory (pc, &insn, 1))
1904 return 0; /* Can't read memory at pc. */
1906 if (insn != 0xc3) /* 'ret' instruction. */
1913 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
1914 struct frame_info *this_frame,
1915 void **this_prologue_cache)
1917 if (frame_relative_level (this_frame) == 0)
1918 return i386_in_function_epilogue_p (get_frame_arch (this_frame),
1919 get_frame_pc (this_frame));
1924 static struct i386_frame_cache *
1925 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
1927 volatile struct gdb_exception ex;
1928 struct i386_frame_cache *cache;
1934 cache = i386_alloc_frame_cache ();
1935 *this_cache = cache;
1937 TRY_CATCH (ex, RETURN_MASK_ERROR)
1939 cache->pc = get_frame_func (this_frame);
1941 /* At this point the stack looks as if we just entered the
1942 function, with the return address at the top of the
1944 sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM);
1945 cache->base = sp + cache->sp_offset;
1946 cache->saved_sp = cache->base + 8;
1947 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
1951 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
1952 throw_exception (ex);
1957 static enum unwind_stop_reason
1958 i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
1961 struct i386_frame_cache *cache =
1962 i386_epilogue_frame_cache (this_frame, this_cache);
1965 return UNWIND_UNAVAILABLE;
1967 return UNWIND_NO_REASON;
1971 i386_epilogue_frame_this_id (struct frame_info *this_frame,
1973 struct frame_id *this_id)
1975 struct i386_frame_cache *cache =
1976 i386_epilogue_frame_cache (this_frame, this_cache);
1981 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
1984 static struct value *
1985 i386_epilogue_frame_prev_register (struct frame_info *this_frame,
1986 void **this_cache, int regnum)
1988 /* Make sure we've initialized the cache. */
1989 i386_epilogue_frame_cache (this_frame, this_cache);
1991 return i386_frame_prev_register (this_frame, this_cache, regnum);
1994 static const struct frame_unwind i386_epilogue_frame_unwind =
1997 i386_epilogue_frame_unwind_stop_reason,
1998 i386_epilogue_frame_this_id,
1999 i386_epilogue_frame_prev_register,
2001 i386_epilogue_frame_sniffer
2005 /* Stack-based trampolines. */
2007 /* These trampolines are used on cross x86 targets, when taking the
2008 address of a nested function. When executing these trampolines,
2009 no stack frame is set up, so we are in a similar situation as in
2010 epilogues and i386_epilogue_frame_this_id can be re-used. */
2012 /* Static chain passed in register. */
2014 struct i386_insn i386_tramp_chain_in_reg_insns[] =
2016 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2017 { 5, { 0xb8 }, { 0xfe } },
2020 { 5, { 0xe9 }, { 0xff } },
2025 /* Static chain passed on stack (when regparm=3). */
2027 struct i386_insn i386_tramp_chain_on_stack_insns[] =
2030 { 5, { 0x68 }, { 0xff } },
2033 { 5, { 0xe9 }, { 0xff } },
2038 /* Return whether PC points inside a stack trampoline. */
2041 i386_in_stack_tramp_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2046 /* A stack trampoline is detected if no name is associated
2047 to the current pc and if it points inside a trampoline
2050 find_pc_partial_function (pc, &name, NULL, NULL);
2054 if (target_read_memory (pc, &insn, 1))
2057 if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns)
2058 && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns))
2065 i386_stack_tramp_frame_sniffer (const struct frame_unwind *self,
2066 struct frame_info *this_frame,
2069 if (frame_relative_level (this_frame) == 0)
2070 return i386_in_stack_tramp_p (get_frame_arch (this_frame),
2071 get_frame_pc (this_frame));
2076 static const struct frame_unwind i386_stack_tramp_frame_unwind =
2079 i386_epilogue_frame_unwind_stop_reason,
2080 i386_epilogue_frame_this_id,
2081 i386_epilogue_frame_prev_register,
2083 i386_stack_tramp_frame_sniffer
2086 /* Generate a bytecode expression to get the value of the saved PC. */
2089 i386_gen_return_address (struct gdbarch *gdbarch,
2090 struct agent_expr *ax, struct axs_value *value,
2093 /* The following sequence assumes the traditional use of the base
2095 ax_reg (ax, I386_EBP_REGNUM);
2097 ax_simple (ax, aop_add);
2098 value->type = register_type (gdbarch, I386_EIP_REGNUM);
2099 value->kind = axs_lvalue_memory;
2103 /* Signal trampolines. */
2105 static struct i386_frame_cache *
2106 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2108 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2109 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2110 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2111 volatile struct gdb_exception ex;
2112 struct i386_frame_cache *cache;
2119 cache = i386_alloc_frame_cache ();
2121 TRY_CATCH (ex, RETURN_MASK_ERROR)
2123 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2124 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
2126 addr = tdep->sigcontext_addr (this_frame);
2127 if (tdep->sc_reg_offset)
2131 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
2133 for (i = 0; i < tdep->sc_num_regs; i++)
2134 if (tdep->sc_reg_offset[i] != -1)
2135 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2139 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
2140 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
2145 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2146 throw_exception (ex);
2148 *this_cache = cache;
2152 static enum unwind_stop_reason
2153 i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2156 struct i386_frame_cache *cache =
2157 i386_sigtramp_frame_cache (this_frame, this_cache);
2160 return UNWIND_UNAVAILABLE;
2162 return UNWIND_NO_REASON;
2166 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
2167 struct frame_id *this_id)
2169 struct i386_frame_cache *cache =
2170 i386_sigtramp_frame_cache (this_frame, this_cache);
2175 /* See the end of i386_push_dummy_call. */
2176 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
2179 static struct value *
2180 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
2181 void **this_cache, int regnum)
2183 /* Make sure we've initialized the cache. */
2184 i386_sigtramp_frame_cache (this_frame, this_cache);
2186 return i386_frame_prev_register (this_frame, this_cache, regnum);
2190 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
2191 struct frame_info *this_frame,
2192 void **this_prologue_cache)
2194 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2196 /* We shouldn't even bother if we don't have a sigcontext_addr
2198 if (tdep->sigcontext_addr == NULL)
2201 if (tdep->sigtramp_p != NULL)
2203 if (tdep->sigtramp_p (this_frame))
2207 if (tdep->sigtramp_start != 0)
2209 CORE_ADDR pc = get_frame_pc (this_frame);
2211 gdb_assert (tdep->sigtramp_end != 0);
2212 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2219 static const struct frame_unwind i386_sigtramp_frame_unwind =
2222 i386_sigtramp_frame_unwind_stop_reason,
2223 i386_sigtramp_frame_this_id,
2224 i386_sigtramp_frame_prev_register,
2226 i386_sigtramp_frame_sniffer
2231 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
2233 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2238 static const struct frame_base i386_frame_base =
2241 i386_frame_base_address,
2242 i386_frame_base_address,
2243 i386_frame_base_address
2246 static struct frame_id
2247 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2251 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
2253 /* See the end of i386_push_dummy_call. */
2254 return frame_id_build (fp + 8, get_frame_pc (this_frame));
2257 /* _Decimal128 function return values need 16-byte alignment on the
2261 i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2263 return sp & -(CORE_ADDR)16;
2267 /* Figure out where the longjmp will land. Slurp the args out of the
2268 stack. We expect the first arg to be a pointer to the jmp_buf
2269 structure from which we extract the address that we will land at.
2270 This address is copied into PC. This routine returns non-zero on
2274 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2277 CORE_ADDR sp, jb_addr;
2278 struct gdbarch *gdbarch = get_frame_arch (frame);
2279 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2280 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2282 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2283 longjmp will land. */
2284 if (jb_pc_offset == -1)
2287 get_frame_register (frame, I386_ESP_REGNUM, buf);
2288 sp = extract_unsigned_integer (buf, 4, byte_order);
2289 if (target_read_memory (sp + 4, buf, 4))
2292 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
2293 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
2296 *pc = extract_unsigned_integer (buf, 4, byte_order);
2301 /* Check whether TYPE must be 16-byte-aligned when passed as a
2302 function argument. 16-byte vectors, _Decimal128 and structures or
2303 unions containing such types must be 16-byte-aligned; other
2304 arguments are 4-byte-aligned. */
2307 i386_16_byte_align_p (struct type *type)
2309 type = check_typedef (type);
2310 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
2311 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
2312 && TYPE_LENGTH (type) == 16)
2314 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2315 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
2316 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2317 || TYPE_CODE (type) == TYPE_CODE_UNION)
2320 for (i = 0; i < TYPE_NFIELDS (type); i++)
2322 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
2330 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2331 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2332 struct value **args, CORE_ADDR sp, int struct_return,
2333 CORE_ADDR struct_addr)
2335 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2341 /* Determine the total space required for arguments and struct
2342 return address in a first pass (allowing for 16-byte-aligned
2343 arguments), then push arguments in a second pass. */
2345 for (write_pass = 0; write_pass < 2; write_pass++)
2347 int args_space_used = 0;
2348 int have_16_byte_aligned_arg = 0;
2354 /* Push value address. */
2355 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2356 write_memory (sp, buf, 4);
2357 args_space_used += 4;
2363 for (i = 0; i < nargs; i++)
2365 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2369 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2370 args_space_used = align_up (args_space_used, 16);
2372 write_memory (sp + args_space_used,
2373 value_contents_all (args[i]), len);
2374 /* The System V ABI says that:
2376 "An argument's size is increased, if necessary, to make it a
2377 multiple of [32-bit] words. This may require tail padding,
2378 depending on the size of the argument."
2380 This makes sure the stack stays word-aligned. */
2381 args_space_used += align_up (len, 4);
2385 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2387 args_space = align_up (args_space, 16);
2388 have_16_byte_aligned_arg = 1;
2390 args_space += align_up (len, 4);
2396 if (have_16_byte_aligned_arg)
2397 args_space = align_up (args_space, 16);
2402 /* Store return address. */
2404 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2405 write_memory (sp, buf, 4);
2407 /* Finally, update the stack pointer... */
2408 store_unsigned_integer (buf, 4, byte_order, sp);
2409 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
2411 /* ...and fake a frame pointer. */
2412 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
2414 /* MarkK wrote: This "+ 8" is all over the place:
2415 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2416 i386_dummy_id). It's there, since all frame unwinders for
2417 a given target have to agree (within a certain margin) on the
2418 definition of the stack address of a frame. Otherwise frame id
2419 comparison might not work correctly. Since DWARF2/GCC uses the
2420 stack address *before* the function call as a frame's CFA. On
2421 the i386, when %ebp is used as a frame pointer, the offset
2422 between the contents %ebp and the CFA as defined by GCC. */
2426 /* These registers are used for returning integers (and on some
2427 targets also for returning `struct' and `union' values when their
2428 size and alignment match an integer type). */
2429 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2430 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2432 /* Read, for architecture GDBARCH, a function return value of TYPE
2433 from REGCACHE, and copy that into VALBUF. */
2436 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2437 struct regcache *regcache, gdb_byte *valbuf)
2439 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2440 int len = TYPE_LENGTH (type);
2441 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2443 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2445 if (tdep->st0_regnum < 0)
2447 warning (_("Cannot find floating-point return value."));
2448 memset (valbuf, 0, len);
2452 /* Floating-point return values can be found in %st(0). Convert
2453 its contents to the desired type. This is probably not
2454 exactly how it would happen on the target itself, but it is
2455 the best we can do. */
2456 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2457 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
2461 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2462 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2464 if (len <= low_size)
2466 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2467 memcpy (valbuf, buf, len);
2469 else if (len <= (low_size + high_size))
2471 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2472 memcpy (valbuf, buf, low_size);
2473 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2474 memcpy (valbuf + low_size, buf, len - low_size);
2477 internal_error (__FILE__, __LINE__,
2478 _("Cannot extract return value of %d bytes long."),
2483 /* Write, for architecture GDBARCH, a function return value of TYPE
2484 from VALBUF into REGCACHE. */
2487 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2488 struct regcache *regcache, const gdb_byte *valbuf)
2490 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2491 int len = TYPE_LENGTH (type);
2493 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2496 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2498 if (tdep->st0_regnum < 0)
2500 warning (_("Cannot set floating-point return value."));
2504 /* Returning floating-point values is a bit tricky. Apart from
2505 storing the return value in %st(0), we have to simulate the
2506 state of the FPU at function return point. */
2508 /* Convert the value found in VALBUF to the extended
2509 floating-point format used by the FPU. This is probably
2510 not exactly how it would happen on the target itself, but
2511 it is the best we can do. */
2512 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
2513 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2515 /* Set the top of the floating-point register stack to 7. The
2516 actual value doesn't really matter, but 7 is what a normal
2517 function return would end up with if the program started out
2518 with a freshly initialized FPU. */
2519 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2521 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2523 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2524 the floating-point register stack to 7, the appropriate value
2525 for the tag word is 0x3fff. */
2526 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2530 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2531 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2533 if (len <= low_size)
2534 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2535 else if (len <= (low_size + high_size))
2537 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2538 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
2539 len - low_size, valbuf + low_size);
2542 internal_error (__FILE__, __LINE__,
2543 _("Cannot store return value of %d bytes long."), len);
2548 /* This is the variable that is set with "set struct-convention", and
2549 its legitimate values. */
2550 static const char default_struct_convention[] = "default";
2551 static const char pcc_struct_convention[] = "pcc";
2552 static const char reg_struct_convention[] = "reg";
2553 static const char *const valid_conventions[] =
2555 default_struct_convention,
2556 pcc_struct_convention,
2557 reg_struct_convention,
2560 static const char *struct_convention = default_struct_convention;
2562 /* Return non-zero if TYPE, which is assumed to be a structure,
2563 a union type, or an array type, should be returned in registers
2564 for architecture GDBARCH. */
2567 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2569 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2570 enum type_code code = TYPE_CODE (type);
2571 int len = TYPE_LENGTH (type);
2573 gdb_assert (code == TYPE_CODE_STRUCT
2574 || code == TYPE_CODE_UNION
2575 || code == TYPE_CODE_ARRAY);
2577 if (struct_convention == pcc_struct_convention
2578 || (struct_convention == default_struct_convention
2579 && tdep->struct_return == pcc_struct_return))
2582 /* Structures consisting of a single `float', `double' or 'long
2583 double' member are returned in %st(0). */
2584 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2586 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2587 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2588 return (len == 4 || len == 8 || len == 12);
2591 return (len == 1 || len == 2 || len == 4 || len == 8);
2594 /* Determine, for architecture GDBARCH, how a return value of TYPE
2595 should be returned. If it is supposed to be returned in registers,
2596 and READBUF is non-zero, read the appropriate value from REGCACHE,
2597 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2598 from WRITEBUF into REGCACHE. */
2600 static enum return_value_convention
2601 i386_return_value (struct gdbarch *gdbarch, struct type *func_type,
2602 struct type *type, struct regcache *regcache,
2603 gdb_byte *readbuf, const gdb_byte *writebuf)
2605 enum type_code code = TYPE_CODE (type);
2607 if (((code == TYPE_CODE_STRUCT
2608 || code == TYPE_CODE_UNION
2609 || code == TYPE_CODE_ARRAY)
2610 && !i386_reg_struct_return_p (gdbarch, type))
2611 /* 128-bit decimal float uses the struct return convention. */
2612 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2614 /* The System V ABI says that:
2616 "A function that returns a structure or union also sets %eax
2617 to the value of the original address of the caller's area
2618 before it returns. Thus when the caller receives control
2619 again, the address of the returned object resides in register
2620 %eax and can be used to access the object."
2622 So the ABI guarantees that we can always find the return
2623 value just after the function has returned. */
2625 /* Note that the ABI doesn't mention functions returning arrays,
2626 which is something possible in certain languages such as Ada.
2627 In this case, the value is returned as if it was wrapped in
2628 a record, so the convention applied to records also applies
2635 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2636 read_memory (addr, readbuf, TYPE_LENGTH (type));
2639 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2642 /* This special case is for structures consisting of a single
2643 `float', `double' or 'long double' member. These structures are
2644 returned in %st(0). For these structures, we call ourselves
2645 recursively, changing TYPE into the type of the first member of
2646 the structure. Since that should work for all structures that
2647 have only one member, we don't bother to check the member's type
2649 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2651 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2652 return i386_return_value (gdbarch, func_type, type, regcache,
2657 i386_extract_return_value (gdbarch, type, regcache, readbuf);
2659 i386_store_return_value (gdbarch, type, regcache, writebuf);
2661 return RETURN_VALUE_REGISTER_CONVENTION;
2666 i387_ext_type (struct gdbarch *gdbarch)
2668 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2670 if (!tdep->i387_ext_type)
2672 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
2673 gdb_assert (tdep->i387_ext_type != NULL);
2676 return tdep->i387_ext_type;
2679 /* Construct vector type for pseudo YMM registers. We can't use
2680 tdesc_find_type since YMM isn't described in target description. */
2682 static struct type *
2683 i386_ymm_type (struct gdbarch *gdbarch)
2685 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2687 if (!tdep->i386_ymm_type)
2689 const struct builtin_type *bt = builtin_type (gdbarch);
2691 /* The type we're building is this: */
2693 union __gdb_builtin_type_vec256i
2695 int128_t uint128[2];
2696 int64_t v2_int64[4];
2697 int32_t v4_int32[8];
2698 int16_t v8_int16[16];
2699 int8_t v16_int8[32];
2700 double v2_double[4];
2707 t = arch_composite_type (gdbarch,
2708 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
2709 append_composite_type_field (t, "v8_float",
2710 init_vector_type (bt->builtin_float, 8));
2711 append_composite_type_field (t, "v4_double",
2712 init_vector_type (bt->builtin_double, 4));
2713 append_composite_type_field (t, "v32_int8",
2714 init_vector_type (bt->builtin_int8, 32));
2715 append_composite_type_field (t, "v16_int16",
2716 init_vector_type (bt->builtin_int16, 16));
2717 append_composite_type_field (t, "v8_int32",
2718 init_vector_type (bt->builtin_int32, 8));
2719 append_composite_type_field (t, "v4_int64",
2720 init_vector_type (bt->builtin_int64, 4));
2721 append_composite_type_field (t, "v2_int128",
2722 init_vector_type (bt->builtin_int128, 2));
2724 TYPE_VECTOR (t) = 1;
2725 TYPE_NAME (t) = "builtin_type_vec256i";
2726 tdep->i386_ymm_type = t;
2729 return tdep->i386_ymm_type;
2732 /* Construct vector type for MMX registers. */
2733 static struct type *
2734 i386_mmx_type (struct gdbarch *gdbarch)
2736 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2738 if (!tdep->i386_mmx_type)
2740 const struct builtin_type *bt = builtin_type (gdbarch);
2742 /* The type we're building is this: */
2744 union __gdb_builtin_type_vec64i
2747 int32_t v2_int32[2];
2748 int16_t v4_int16[4];
2755 t = arch_composite_type (gdbarch,
2756 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
2758 append_composite_type_field (t, "uint64", bt->builtin_int64);
2759 append_composite_type_field (t, "v2_int32",
2760 init_vector_type (bt->builtin_int32, 2));
2761 append_composite_type_field (t, "v4_int16",
2762 init_vector_type (bt->builtin_int16, 4));
2763 append_composite_type_field (t, "v8_int8",
2764 init_vector_type (bt->builtin_int8, 8));
2766 TYPE_VECTOR (t) = 1;
2767 TYPE_NAME (t) = "builtin_type_vec64i";
2768 tdep->i386_mmx_type = t;
2771 return tdep->i386_mmx_type;
2774 /* Return the GDB type object for the "standard" data type of data in
2777 static struct type *
2778 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2780 if (i386_mmx_regnum_p (gdbarch, regnum))
2781 return i386_mmx_type (gdbarch);
2782 else if (i386_ymm_regnum_p (gdbarch, regnum))
2783 return i386_ymm_type (gdbarch);
2786 const struct builtin_type *bt = builtin_type (gdbarch);
2787 if (i386_byte_regnum_p (gdbarch, regnum))
2788 return bt->builtin_int8;
2789 else if (i386_word_regnum_p (gdbarch, regnum))
2790 return bt->builtin_int16;
2791 else if (i386_dword_regnum_p (gdbarch, regnum))
2792 return bt->builtin_int32;
2795 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2798 /* Map a cooked register onto a raw register or memory. For the i386,
2799 the MMX registers need to be mapped onto floating point registers. */
2802 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
2804 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
2809 mmxreg = regnum - tdep->mm0_regnum;
2810 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2811 tos = (fstat >> 11) & 0x7;
2812 fpreg = (mmxreg + tos) % 8;
2814 return (I387_ST0_REGNUM (tdep) + fpreg);
2817 /* A helper function for us by i386_pseudo_register_read_value and
2818 amd64_pseudo_register_read_value. It does all the work but reads
2819 the data into an already-allocated value. */
2822 i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
2823 struct regcache *regcache,
2825 struct value *result_value)
2827 gdb_byte raw_buf[MAX_REGISTER_SIZE];
2828 enum register_status status;
2829 gdb_byte *buf = value_contents_raw (result_value);
2831 if (i386_mmx_regnum_p (gdbarch, regnum))
2833 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2835 /* Extract (always little endian). */
2836 status = regcache_raw_read (regcache, fpnum, raw_buf);
2837 if (status != REG_VALID)
2838 mark_value_bytes_unavailable (result_value, 0,
2839 TYPE_LENGTH (value_type (result_value)));
2841 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
2845 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2847 if (i386_ymm_regnum_p (gdbarch, regnum))
2849 regnum -= tdep->ymm0_regnum;
2851 /* Extract (always little endian). Read lower 128bits. */
2852 status = regcache_raw_read (regcache,
2853 I387_XMM0_REGNUM (tdep) + regnum,
2855 if (status != REG_VALID)
2856 mark_value_bytes_unavailable (result_value, 0, 16);
2858 memcpy (buf, raw_buf, 16);
2859 /* Read upper 128bits. */
2860 status = regcache_raw_read (regcache,
2861 tdep->ymm0h_regnum + regnum,
2863 if (status != REG_VALID)
2864 mark_value_bytes_unavailable (result_value, 16, 32);
2866 memcpy (buf + 16, raw_buf, 16);
2868 else if (i386_word_regnum_p (gdbarch, regnum))
2870 int gpnum = regnum - tdep->ax_regnum;
2872 /* Extract (always little endian). */
2873 status = regcache_raw_read (regcache, gpnum, raw_buf);
2874 if (status != REG_VALID)
2875 mark_value_bytes_unavailable (result_value, 0,
2876 TYPE_LENGTH (value_type (result_value)));
2878 memcpy (buf, raw_buf, 2);
2880 else if (i386_byte_regnum_p (gdbarch, regnum))
2882 /* Check byte pseudo registers last since this function will
2883 be called from amd64_pseudo_register_read, which handles
2884 byte pseudo registers differently. */
2885 int gpnum = regnum - tdep->al_regnum;
2887 /* Extract (always little endian). We read both lower and
2889 status = regcache_raw_read (regcache, gpnum % 4, raw_buf);
2890 if (status != REG_VALID)
2891 mark_value_bytes_unavailable (result_value, 0,
2892 TYPE_LENGTH (value_type (result_value)));
2893 else if (gpnum >= 4)
2894 memcpy (buf, raw_buf + 1, 1);
2896 memcpy (buf, raw_buf, 1);
2899 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2903 static struct value *
2904 i386_pseudo_register_read_value (struct gdbarch *gdbarch,
2905 struct regcache *regcache,
2908 struct value *result;
2910 result = allocate_value (register_type (gdbarch, regnum));
2911 VALUE_LVAL (result) = lval_register;
2912 VALUE_REGNUM (result) = regnum;
2914 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result);
2920 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2921 int regnum, const gdb_byte *buf)
2923 gdb_byte raw_buf[MAX_REGISTER_SIZE];
2925 if (i386_mmx_regnum_p (gdbarch, regnum))
2927 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2930 regcache_raw_read (regcache, fpnum, raw_buf);
2931 /* ... Modify ... (always little endian). */
2932 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
2934 regcache_raw_write (regcache, fpnum, raw_buf);
2938 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2940 if (i386_ymm_regnum_p (gdbarch, regnum))
2942 regnum -= tdep->ymm0_regnum;
2944 /* ... Write lower 128bits. */
2945 regcache_raw_write (regcache,
2946 I387_XMM0_REGNUM (tdep) + regnum,
2948 /* ... Write upper 128bits. */
2949 regcache_raw_write (regcache,
2950 tdep->ymm0h_regnum + regnum,
2953 else if (i386_word_regnum_p (gdbarch, regnum))
2955 int gpnum = regnum - tdep->ax_regnum;
2958 regcache_raw_read (regcache, gpnum, raw_buf);
2959 /* ... Modify ... (always little endian). */
2960 memcpy (raw_buf, buf, 2);
2962 regcache_raw_write (regcache, gpnum, raw_buf);
2964 else if (i386_byte_regnum_p (gdbarch, regnum))
2966 /* Check byte pseudo registers last since this function will
2967 be called from amd64_pseudo_register_read, which handles
2968 byte pseudo registers differently. */
2969 int gpnum = regnum - tdep->al_regnum;
2971 /* Read ... We read both lower and upper registers. */
2972 regcache_raw_read (regcache, gpnum % 4, raw_buf);
2973 /* ... Modify ... (always little endian). */
2975 memcpy (raw_buf + 1, buf, 1);
2977 memcpy (raw_buf, buf, 1);
2979 regcache_raw_write (regcache, gpnum % 4, raw_buf);
2982 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2987 /* Return the register number of the register allocated by GCC after
2988 REGNUM, or -1 if there is no such register. */
2991 i386_next_regnum (int regnum)
2993 /* GCC allocates the registers in the order:
2995 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2997 Since storing a variable in %esp doesn't make any sense we return
2998 -1 for %ebp and for %esp itself. */
2999 static int next_regnum[] =
3001 I386_EDX_REGNUM, /* Slot for %eax. */
3002 I386_EBX_REGNUM, /* Slot for %ecx. */
3003 I386_ECX_REGNUM, /* Slot for %edx. */
3004 I386_ESI_REGNUM, /* Slot for %ebx. */
3005 -1, -1, /* Slots for %esp and %ebp. */
3006 I386_EDI_REGNUM, /* Slot for %esi. */
3007 I386_EBP_REGNUM /* Slot for %edi. */
3010 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
3011 return next_regnum[regnum];
3016 /* Return nonzero if a value of type TYPE stored in register REGNUM
3017 needs any special handling. */
3020 i386_convert_register_p (struct gdbarch *gdbarch,
3021 int regnum, struct type *type)
3023 int len = TYPE_LENGTH (type);
3025 /* Values may be spread across multiple registers. Most debugging
3026 formats aren't expressive enough to specify the locations, so
3027 some heuristics is involved. Right now we only handle types that
3028 have a length that is a multiple of the word size, since GCC
3029 doesn't seem to put any other types into registers. */
3030 if (len > 4 && len % 4 == 0)
3032 int last_regnum = regnum;
3036 last_regnum = i386_next_regnum (last_regnum);
3040 if (last_regnum != -1)
3044 return i387_convert_register_p (gdbarch, regnum, type);
3047 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3048 return its contents in TO. */
3051 i386_register_to_value (struct frame_info *frame, int regnum,
3052 struct type *type, gdb_byte *to,
3053 int *optimizedp, int *unavailablep)
3055 struct gdbarch *gdbarch = get_frame_arch (frame);
3056 int len = TYPE_LENGTH (type);
3058 if (i386_fp_regnum_p (gdbarch, regnum))
3059 return i387_register_to_value (frame, regnum, type, to,
3060 optimizedp, unavailablep);
3062 /* Read a value spread across multiple registers. */
3064 gdb_assert (len > 4 && len % 4 == 0);
3068 gdb_assert (regnum != -1);
3069 gdb_assert (register_size (gdbarch, regnum) == 4);
3071 if (!get_frame_register_bytes (frame, regnum, 0,
3072 register_size (gdbarch, regnum),
3073 to, optimizedp, unavailablep))
3076 regnum = i386_next_regnum (regnum);
3081 *optimizedp = *unavailablep = 0;
3085 /* Write the contents FROM of a value of type TYPE into register
3086 REGNUM in frame FRAME. */
3089 i386_value_to_register (struct frame_info *frame, int regnum,
3090 struct type *type, const gdb_byte *from)
3092 int len = TYPE_LENGTH (type);
3094 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
3096 i387_value_to_register (frame, regnum, type, from);
3100 /* Write a value spread across multiple registers. */
3102 gdb_assert (len > 4 && len % 4 == 0);
3106 gdb_assert (regnum != -1);
3107 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
3109 put_frame_register (frame, regnum, from);
3110 regnum = i386_next_regnum (regnum);
3116 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3117 in the general-purpose register set REGSET to register cache
3118 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3121 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
3122 int regnum, const void *gregs, size_t len)
3124 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3125 const gdb_byte *regs = gregs;
3128 gdb_assert (len == tdep->sizeof_gregset);
3130 for (i = 0; i < tdep->gregset_num_regs; i++)
3132 if ((regnum == i || regnum == -1)
3133 && tdep->gregset_reg_offset[i] != -1)
3134 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
3138 /* Collect register REGNUM from the register cache REGCACHE and store
3139 it in the buffer specified by GREGS and LEN as described by the
3140 general-purpose register set REGSET. If REGNUM is -1, do this for
3141 all registers in REGSET. */
3144 i386_collect_gregset (const struct regset *regset,
3145 const struct regcache *regcache,
3146 int regnum, void *gregs, size_t len)
3148 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3149 gdb_byte *regs = gregs;
3152 gdb_assert (len == tdep->sizeof_gregset);
3154 for (i = 0; i < tdep->gregset_num_regs; i++)
3156 if ((regnum == i || regnum == -1)
3157 && tdep->gregset_reg_offset[i] != -1)
3158 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
3162 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3163 in the floating-point register set REGSET to register cache
3164 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3167 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
3168 int regnum, const void *fpregs, size_t len)
3170 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3172 if (len == I387_SIZEOF_FXSAVE)
3174 i387_supply_fxsave (regcache, regnum, fpregs);
3178 gdb_assert (len == tdep->sizeof_fpregset);
3179 i387_supply_fsave (regcache, regnum, fpregs);
3182 /* Collect register REGNUM from the register cache REGCACHE and store
3183 it in the buffer specified by FPREGS and LEN as described by the
3184 floating-point register set REGSET. If REGNUM is -1, do this for
3185 all registers in REGSET. */
3188 i386_collect_fpregset (const struct regset *regset,
3189 const struct regcache *regcache,
3190 int regnum, void *fpregs, size_t len)
3192 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3194 if (len == I387_SIZEOF_FXSAVE)
3196 i387_collect_fxsave (regcache, regnum, fpregs);
3200 gdb_assert (len == tdep->sizeof_fpregset);
3201 i387_collect_fsave (regcache, regnum, fpregs);
3204 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
3207 i386_supply_xstateregset (const struct regset *regset,
3208 struct regcache *regcache, int regnum,
3209 const void *xstateregs, size_t len)
3211 i387_supply_xsave (regcache, regnum, xstateregs);
3214 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
3217 i386_collect_xstateregset (const struct regset *regset,
3218 const struct regcache *regcache,
3219 int regnum, void *xstateregs, size_t len)
3221 i387_collect_xsave (regcache, regnum, xstateregs, 1);
3224 /* Return the appropriate register set for the core section identified
3225 by SECT_NAME and SECT_SIZE. */
3227 const struct regset *
3228 i386_regset_from_core_section (struct gdbarch *gdbarch,
3229 const char *sect_name, size_t sect_size)
3231 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3233 if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset)
3235 if (tdep->gregset == NULL)
3236 tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset,
3237 i386_collect_gregset);
3238 return tdep->gregset;
3241 if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
3242 || (strcmp (sect_name, ".reg-xfp") == 0
3243 && sect_size == I387_SIZEOF_FXSAVE))
3245 if (tdep->fpregset == NULL)
3246 tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset,
3247 i386_collect_fpregset);
3248 return tdep->fpregset;
3251 if (strcmp (sect_name, ".reg-xstate") == 0)
3253 if (tdep->xstateregset == NULL)
3254 tdep->xstateregset = regset_alloc (gdbarch,
3255 i386_supply_xstateregset,
3256 i386_collect_xstateregset);
3258 return tdep->xstateregset;
3265 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3268 i386_pe_skip_trampoline_code (struct frame_info *frame,
3269 CORE_ADDR pc, char *name)
3271 struct gdbarch *gdbarch = get_frame_arch (frame);
3272 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3275 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
3277 unsigned long indirect =
3278 read_memory_unsigned_integer (pc + 2, 4, byte_order);
3279 struct minimal_symbol *indsym =
3280 indirect ? lookup_minimal_symbol_by_pc (indirect) : 0;
3281 const char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0;
3285 if (strncmp (symname, "__imp_", 6) == 0
3286 || strncmp (symname, "_imp_", 5) == 0)
3288 read_memory_unsigned_integer (indirect, 4, byte_order);
3291 return 0; /* Not a trampoline. */
3295 /* Return whether the THIS_FRAME corresponds to a sigtramp
3299 i386_sigtramp_p (struct frame_info *this_frame)
3301 CORE_ADDR pc = get_frame_pc (this_frame);
3304 find_pc_partial_function (pc, &name, NULL, NULL);
3305 return (name && strcmp ("_sigtramp", name) == 0);
3309 /* We have two flavours of disassembly. The machinery on this page
3310 deals with switching between those. */
3313 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
3315 gdb_assert (disassembly_flavor == att_flavor
3316 || disassembly_flavor == intel_flavor);
3318 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3319 constified, cast to prevent a compiler warning. */
3320 info->disassembler_options = (char *) disassembly_flavor;
3322 return print_insn_i386 (pc, info);
3326 /* There are a few i386 architecture variants that differ only
3327 slightly from the generic i386 target. For now, we don't give them
3328 their own source file, but include them here. As a consequence,
3329 they'll always be included. */
3331 /* System V Release 4 (SVR4). */
3333 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3337 i386_svr4_sigtramp_p (struct frame_info *this_frame)
3339 CORE_ADDR pc = get_frame_pc (this_frame);
3342 /* UnixWare uses _sigacthandler. The origin of the other symbols is
3343 currently unknown. */
3344 find_pc_partial_function (pc, &name, NULL, NULL);
3345 return (name && (strcmp ("_sigreturn", name) == 0
3346 || strcmp ("_sigacthandler", name) == 0
3347 || strcmp ("sigvechandler", name) == 0));
3350 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3351 address of the associated sigcontext (ucontext) structure. */
3354 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
3356 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3357 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3361 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
3362 sp = extract_unsigned_integer (buf, 4, byte_order);
3364 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
3371 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3373 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3374 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3377 /* System V Release 4 (SVR4). */
3380 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3382 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3384 /* System V Release 4 uses ELF. */
3385 i386_elf_init_abi (info, gdbarch);
3387 /* System V Release 4 has shared libraries. */
3388 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
3390 tdep->sigtramp_p = i386_svr4_sigtramp_p;
3391 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
3392 tdep->sc_pc_offset = 36 + 14 * 4;
3393 tdep->sc_sp_offset = 36 + 17 * 4;
3395 tdep->jb_pc_offset = 20;
3401 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3403 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3405 /* DJGPP doesn't have any special frames for signal handlers. */
3406 tdep->sigtramp_p = NULL;
3408 tdep->jb_pc_offset = 36;
3410 /* DJGPP does not support the SSE registers. */
3411 if (! tdesc_has_registers (info.target_desc))
3412 tdep->tdesc = tdesc_i386_mmx;
3414 /* Native compiler is GCC, which uses the SVR4 register numbering
3415 even in COFF and STABS. See the comment in i386_gdbarch_init,
3416 before the calls to set_gdbarch_stab_reg_to_regnum and
3417 set_gdbarch_sdb_reg_to_regnum. */
3418 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3419 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3421 set_gdbarch_has_dos_based_file_system (gdbarch, 1);
3425 /* i386 register groups. In addition to the normal groups, add "mmx"
3428 static struct reggroup *i386_sse_reggroup;
3429 static struct reggroup *i386_mmx_reggroup;
3432 i386_init_reggroups (void)
3434 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
3435 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
3439 i386_add_reggroups (struct gdbarch *gdbarch)
3441 reggroup_add (gdbarch, i386_sse_reggroup);
3442 reggroup_add (gdbarch, i386_mmx_reggroup);
3443 reggroup_add (gdbarch, general_reggroup);
3444 reggroup_add (gdbarch, float_reggroup);
3445 reggroup_add (gdbarch, all_reggroup);
3446 reggroup_add (gdbarch, save_reggroup);
3447 reggroup_add (gdbarch, restore_reggroup);
3448 reggroup_add (gdbarch, vector_reggroup);
3449 reggroup_add (gdbarch, system_reggroup);
3453 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
3454 struct reggroup *group)
3456 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3457 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
3458 ymm_regnum_p, ymmh_regnum_p;
3460 /* Don't include pseudo registers, except for MMX, in any register
3462 if (i386_byte_regnum_p (gdbarch, regnum))
3465 if (i386_word_regnum_p (gdbarch, regnum))
3468 if (i386_dword_regnum_p (gdbarch, regnum))
3471 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
3472 if (group == i386_mmx_reggroup)
3473 return mmx_regnum_p;
3475 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
3476 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
3477 if (group == i386_sse_reggroup)
3478 return xmm_regnum_p || mxcsr_regnum_p;
3480 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
3481 if (group == vector_reggroup)
3482 return (mmx_regnum_p
3486 && ((tdep->xcr0 & I386_XSTATE_AVX_MASK)
3487 == I386_XSTATE_SSE_MASK)));
3489 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
3490 || i386_fpc_regnum_p (gdbarch, regnum));
3491 if (group == float_reggroup)
3494 /* For "info reg all", don't include upper YMM registers nor XMM
3495 registers when AVX is supported. */
3496 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
3497 if (group == all_reggroup
3499 && (tdep->xcr0 & I386_XSTATE_AVX))
3503 if (group == general_reggroup)
3504 return (!fp_regnum_p
3511 return default_register_reggroup_p (gdbarch, regnum, group);
3515 /* Get the ARGIth function argument for the current function. */
3518 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
3521 struct gdbarch *gdbarch = get_frame_arch (frame);
3522 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3523 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
3524 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
3528 i386_skip_permanent_breakpoint (struct regcache *regcache)
3530 CORE_ADDR current_pc = regcache_read_pc (regcache);
3532 /* On i386, breakpoint is exactly 1 byte long, so we just
3533 adjust the PC in the regcache. */
3535 regcache_write_pc (regcache, current_pc);
3539 #define PREFIX_REPZ 0x01
3540 #define PREFIX_REPNZ 0x02
3541 #define PREFIX_LOCK 0x04
3542 #define PREFIX_DATA 0x08
3543 #define PREFIX_ADDR 0x10
3555 /* i386 arith/logic operations */
3568 struct i386_record_s
3570 struct gdbarch *gdbarch;
3571 struct regcache *regcache;
3572 CORE_ADDR orig_addr;
3578 uint8_t mod, reg, rm;
3587 /* Parse "modrm" part in current memory address that irp->addr point to
3588 Return -1 if something wrong. */
3591 i386_record_modrm (struct i386_record_s *irp)
3593 struct gdbarch *gdbarch = irp->gdbarch;
3595 if (target_read_memory (irp->addr, &irp->modrm, 1))
3598 printf_unfiltered (_("Process record: error reading memory at "
3599 "addr %s len = 1.\n"),
3600 paddress (gdbarch, irp->addr));
3604 irp->mod = (irp->modrm >> 6) & 3;
3605 irp->reg = (irp->modrm >> 3) & 7;
3606 irp->rm = irp->modrm & 7;
3611 /* Get the memory address that current instruction write to and set it to
3612 the argument "addr".
3613 Return -1 if something wrong. */
3616 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
3618 struct gdbarch *gdbarch = irp->gdbarch;
3619 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3631 uint8_t base = irp->rm;
3636 if (target_read_memory (irp->addr, &byte, 1))
3639 printf_unfiltered (_("Process record: error reading memory "
3640 "at addr %s len = 1.\n"),
3641 paddress (gdbarch, irp->addr));
3645 scale = (byte >> 6) & 3;
3646 index = ((byte >> 3) & 7) | irp->rex_x;
3654 if ((base & 7) == 5)
3657 if (target_read_memory (irp->addr, buf, 4))
3660 printf_unfiltered (_("Process record: error reading "
3661 "memory at addr %s len = 4.\n"),
3662 paddress (gdbarch, irp->addr));
3666 *addr = extract_signed_integer (buf, 4, byte_order);
3667 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
3668 *addr += irp->addr + irp->rip_offset;
3672 if (target_read_memory (irp->addr, buf, 1))
3675 printf_unfiltered (_("Process record: error reading memory "
3676 "at addr %s len = 1.\n"),
3677 paddress (gdbarch, irp->addr));
3681 *addr = (int8_t) buf[0];
3684 if (target_read_memory (irp->addr, buf, 4))
3687 printf_unfiltered (_("Process record: error reading memory "
3688 "at addr %s len = 4.\n"),
3689 paddress (gdbarch, irp->addr));
3692 *addr = extract_signed_integer (buf, 4, byte_order);
3700 if (base == 4 && irp->popl_esp_hack)
3701 *addr += irp->popl_esp_hack;
3702 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
3705 if (irp->aflag == 2)
3710 *addr = (uint32_t) (offset64 + *addr);
3712 if (havesib && (index != 4 || scale != 0))
3714 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
3716 if (irp->aflag == 2)
3717 *addr += offset64 << scale;
3719 *addr = (uint32_t) (*addr + (offset64 << scale));
3730 if (target_read_memory (irp->addr, buf, 2))
3733 printf_unfiltered (_("Process record: error reading "
3734 "memory at addr %s len = 2.\n"),
3735 paddress (gdbarch, irp->addr));
3739 *addr = extract_signed_integer (buf, 2, byte_order);
3745 if (target_read_memory (irp->addr, buf, 1))
3748 printf_unfiltered (_("Process record: error reading memory "
3749 "at addr %s len = 1.\n"),
3750 paddress (gdbarch, irp->addr));
3754 *addr = (int8_t) buf[0];
3757 if (target_read_memory (irp->addr, buf, 2))
3760 printf_unfiltered (_("Process record: error reading memory "
3761 "at addr %s len = 2.\n"),
3762 paddress (gdbarch, irp->addr));
3766 *addr = extract_signed_integer (buf, 2, byte_order);
3773 regcache_raw_read_unsigned (irp->regcache,
3774 irp->regmap[X86_RECORD_REBX_REGNUM],
3776 *addr = (uint32_t) (*addr + offset64);
3777 regcache_raw_read_unsigned (irp->regcache,
3778 irp->regmap[X86_RECORD_RESI_REGNUM],
3780 *addr = (uint32_t) (*addr + offset64);
3783 regcache_raw_read_unsigned (irp->regcache,
3784 irp->regmap[X86_RECORD_REBX_REGNUM],
3786 *addr = (uint32_t) (*addr + offset64);
3787 regcache_raw_read_unsigned (irp->regcache,
3788 irp->regmap[X86_RECORD_REDI_REGNUM],
3790 *addr = (uint32_t) (*addr + offset64);
3793 regcache_raw_read_unsigned (irp->regcache,
3794 irp->regmap[X86_RECORD_REBP_REGNUM],
3796 *addr = (uint32_t) (*addr + offset64);
3797 regcache_raw_read_unsigned (irp->regcache,
3798 irp->regmap[X86_RECORD_RESI_REGNUM],
3800 *addr = (uint32_t) (*addr + offset64);
3803 regcache_raw_read_unsigned (irp->regcache,
3804 irp->regmap[X86_RECORD_REBP_REGNUM],
3806 *addr = (uint32_t) (*addr + offset64);
3807 regcache_raw_read_unsigned (irp->regcache,
3808 irp->regmap[X86_RECORD_REDI_REGNUM],
3810 *addr = (uint32_t) (*addr + offset64);
3813 regcache_raw_read_unsigned (irp->regcache,
3814 irp->regmap[X86_RECORD_RESI_REGNUM],
3816 *addr = (uint32_t) (*addr + offset64);
3819 regcache_raw_read_unsigned (irp->regcache,
3820 irp->regmap[X86_RECORD_REDI_REGNUM],
3822 *addr = (uint32_t) (*addr + offset64);
3825 regcache_raw_read_unsigned (irp->regcache,
3826 irp->regmap[X86_RECORD_REBP_REGNUM],
3828 *addr = (uint32_t) (*addr + offset64);
3831 regcache_raw_read_unsigned (irp->regcache,
3832 irp->regmap[X86_RECORD_REBX_REGNUM],
3834 *addr = (uint32_t) (*addr + offset64);
3844 /* Record the value of the memory that willbe changed in current instruction
3845 to "record_arch_list".
3846 Return -1 if something wrong. */
3849 i386_record_lea_modrm (struct i386_record_s *irp)
3851 struct gdbarch *gdbarch = irp->gdbarch;
3854 if (irp->override >= 0)
3856 if (record_memory_query)
3860 target_terminal_ours ();
3862 Process record ignores the memory change of instruction at address %s\n\
3863 because it can't get the value of the segment register.\n\
3864 Do you want to stop the program?"),
3865 paddress (gdbarch, irp->orig_addr));
3866 target_terminal_inferior ();
3874 if (i386_record_lea_modrm_addr (irp, &addr))
3877 if (record_arch_list_add_mem (addr, 1 << irp->ot))
3883 /* Record the push operation to "record_arch_list".
3884 Return -1 if something wrong. */
3887 i386_record_push (struct i386_record_s *irp, int size)
3891 if (record_arch_list_add_reg (irp->regcache,
3892 irp->regmap[X86_RECORD_RESP_REGNUM]))
3894 regcache_raw_read_unsigned (irp->regcache,
3895 irp->regmap[X86_RECORD_RESP_REGNUM],
3897 if (record_arch_list_add_mem ((CORE_ADDR) addr - size, size))
3904 /* Defines contents to record. */
3905 #define I386_SAVE_FPU_REGS 0xfffd
3906 #define I386_SAVE_FPU_ENV 0xfffe
3907 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3909 /* Record the value of floating point registers which will be changed
3910 by the current instruction to "record_arch_list". Return -1 if
3911 something is wrong. */
3913 static int i386_record_floats (struct gdbarch *gdbarch,
3914 struct i386_record_s *ir,
3917 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3920 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3921 happen. Currently we store st0-st7 registers, but we need not store all
3922 registers all the time, in future we use ftag register and record only
3923 those who are not marked as an empty. */
3925 if (I386_SAVE_FPU_REGS == iregnum)
3927 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
3929 if (record_arch_list_add_reg (ir->regcache, i))
3933 else if (I386_SAVE_FPU_ENV == iregnum)
3935 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3937 if (record_arch_list_add_reg (ir->regcache, i))
3941 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
3943 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3945 if (record_arch_list_add_reg (ir->regcache, i))
3949 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
3950 (iregnum <= I387_FOP_REGNUM (tdep)))
3952 if (record_arch_list_add_reg (ir->regcache,iregnum))
3957 /* Parameter error. */
3960 if(I386_SAVE_FPU_ENV != iregnum)
3962 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3964 if (record_arch_list_add_reg (ir->regcache, i))
3971 /* Parse the current instruction and record the values of the registers and
3972 memory that will be changed in current instruction to "record_arch_list".
3973 Return -1 if something wrong. */
3975 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3976 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3979 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
3980 CORE_ADDR input_addr)
3982 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3988 gdb_byte buf[MAX_REGISTER_SIZE];
3989 struct i386_record_s ir;
3990 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3995 memset (&ir, 0, sizeof (struct i386_record_s));
3996 ir.regcache = regcache;
3997 ir.addr = input_addr;
3998 ir.orig_addr = input_addr;
4002 ir.popl_esp_hack = 0;
4003 ir.regmap = tdep->record_regmap;
4004 ir.gdbarch = gdbarch;
4006 if (record_debug > 1)
4007 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
4009 paddress (gdbarch, ir.addr));
4014 if (target_read_memory (ir.addr, &opcode8, 1))
4017 printf_unfiltered (_("Process record: error reading memory at "
4018 "addr %s len = 1.\n"),
4019 paddress (gdbarch, ir.addr));
4023 switch (opcode8) /* Instruction prefixes */
4025 case REPE_PREFIX_OPCODE:
4026 prefixes |= PREFIX_REPZ;
4028 case REPNE_PREFIX_OPCODE:
4029 prefixes |= PREFIX_REPNZ;
4031 case LOCK_PREFIX_OPCODE:
4032 prefixes |= PREFIX_LOCK;
4034 case CS_PREFIX_OPCODE:
4035 ir.override = X86_RECORD_CS_REGNUM;
4037 case SS_PREFIX_OPCODE:
4038 ir.override = X86_RECORD_SS_REGNUM;
4040 case DS_PREFIX_OPCODE:
4041 ir.override = X86_RECORD_DS_REGNUM;
4043 case ES_PREFIX_OPCODE:
4044 ir.override = X86_RECORD_ES_REGNUM;
4046 case FS_PREFIX_OPCODE:
4047 ir.override = X86_RECORD_FS_REGNUM;
4049 case GS_PREFIX_OPCODE:
4050 ir.override = X86_RECORD_GS_REGNUM;
4052 case DATA_PREFIX_OPCODE:
4053 prefixes |= PREFIX_DATA;
4055 case ADDR_PREFIX_OPCODE:
4056 prefixes |= PREFIX_ADDR;
4058 case 0x40: /* i386 inc %eax */
4059 case 0x41: /* i386 inc %ecx */
4060 case 0x42: /* i386 inc %edx */
4061 case 0x43: /* i386 inc %ebx */
4062 case 0x44: /* i386 inc %esp */
4063 case 0x45: /* i386 inc %ebp */
4064 case 0x46: /* i386 inc %esi */
4065 case 0x47: /* i386 inc %edi */
4066 case 0x48: /* i386 dec %eax */
4067 case 0x49: /* i386 dec %ecx */
4068 case 0x4a: /* i386 dec %edx */
4069 case 0x4b: /* i386 dec %ebx */
4070 case 0x4c: /* i386 dec %esp */
4071 case 0x4d: /* i386 dec %ebp */
4072 case 0x4e: /* i386 dec %esi */
4073 case 0x4f: /* i386 dec %edi */
4074 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
4078 rex_w = (opcode8 >> 3) & 1;
4079 rex_r = (opcode8 & 0x4) << 1;
4080 ir.rex_x = (opcode8 & 0x2) << 2;
4081 ir.rex_b = (opcode8 & 0x1) << 3;
4083 else /* 32 bit target */
4092 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
4098 if (prefixes & PREFIX_DATA)
4101 if (prefixes & PREFIX_ADDR)
4103 else if (ir.regmap[X86_RECORD_R8_REGNUM])
4106 /* Now check op code. */
4107 opcode = (uint32_t) opcode8;
4112 if (target_read_memory (ir.addr, &opcode8, 1))
4115 printf_unfiltered (_("Process record: error reading memory at "
4116 "addr %s len = 1.\n"),
4117 paddress (gdbarch, ir.addr));
4121 opcode = (uint32_t) opcode8 | 0x0f00;
4125 case 0x00: /* arith & logic */
4173 if (((opcode >> 3) & 7) != OP_CMPL)
4175 if ((opcode & 1) == 0)
4178 ir.ot = ir.dflag + OT_WORD;
4180 switch ((opcode >> 1) & 3)
4182 case 0: /* OP Ev, Gv */
4183 if (i386_record_modrm (&ir))
4187 if (i386_record_lea_modrm (&ir))
4193 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4195 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4198 case 1: /* OP Gv, Ev */
4199 if (i386_record_modrm (&ir))
4202 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4204 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4206 case 2: /* OP A, Iv */
4207 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4211 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4214 case 0x80: /* GRP1 */
4218 if (i386_record_modrm (&ir))
4221 if (ir.reg != OP_CMPL)
4223 if ((opcode & 1) == 0)
4226 ir.ot = ir.dflag + OT_WORD;
4233 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4234 if (i386_record_lea_modrm (&ir))
4238 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
4240 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4243 case 0x40: /* inc */
4252 case 0x48: /* dec */
4261 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7);
4262 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4265 case 0xf6: /* GRP3 */
4267 if ((opcode & 1) == 0)
4270 ir.ot = ir.dflag + OT_WORD;
4271 if (i386_record_modrm (&ir))
4274 if (ir.mod != 3 && ir.reg == 0)
4275 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4280 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4286 if (i386_record_lea_modrm (&ir))
4292 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4294 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4296 if (ir.reg == 3) /* neg */
4297 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4303 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4304 if (ir.ot != OT_BYTE)
4305 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
4306 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4310 opcode = opcode << 8 | ir.modrm;
4316 case 0xfe: /* GRP4 */
4317 case 0xff: /* GRP5 */
4318 if (i386_record_modrm (&ir))
4320 if (ir.reg >= 2 && opcode == 0xfe)
4323 opcode = opcode << 8 | ir.modrm;
4330 if ((opcode & 1) == 0)
4333 ir.ot = ir.dflag + OT_WORD;
4336 if (i386_record_lea_modrm (&ir))
4342 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4344 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4346 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4349 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4351 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4353 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4356 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
4357 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4359 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4363 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4366 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4368 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4373 opcode = opcode << 8 | ir.modrm;
4379 case 0x84: /* test */
4383 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4386 case 0x98: /* CWDE/CBW */
4387 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4390 case 0x99: /* CDQ/CWD */
4391 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4392 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
4395 case 0x0faf: /* imul */
4398 ir.ot = ir.dflag + OT_WORD;
4399 if (i386_record_modrm (&ir))
4402 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4403 else if (opcode == 0x6b)
4406 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4408 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4409 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4412 case 0x0fc0: /* xadd */
4414 if ((opcode & 1) == 0)
4417 ir.ot = ir.dflag + OT_WORD;
4418 if (i386_record_modrm (&ir))
4423 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4425 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4426 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4428 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4432 if (i386_record_lea_modrm (&ir))
4434 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4436 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4438 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4441 case 0x0fb0: /* cmpxchg */
4443 if ((opcode & 1) == 0)
4446 ir.ot = ir.dflag + OT_WORD;
4447 if (i386_record_modrm (&ir))
4452 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4453 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4455 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4459 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4460 if (i386_record_lea_modrm (&ir))
4463 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4466 case 0x0fc7: /* cmpxchg8b */
4467 if (i386_record_modrm (&ir))
4472 opcode = opcode << 8 | ir.modrm;
4475 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4476 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
4477 if (i386_record_lea_modrm (&ir))
4479 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4482 case 0x50: /* push */
4492 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4494 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4498 case 0x06: /* push es */
4499 case 0x0e: /* push cs */
4500 case 0x16: /* push ss */
4501 case 0x1e: /* push ds */
4502 if (ir.regmap[X86_RECORD_R8_REGNUM])
4507 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4511 case 0x0fa0: /* push fs */
4512 case 0x0fa8: /* push gs */
4513 if (ir.regmap[X86_RECORD_R8_REGNUM])
4518 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4522 case 0x60: /* pusha */
4523 if (ir.regmap[X86_RECORD_R8_REGNUM])
4528 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
4532 case 0x58: /* pop */
4540 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4541 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
4544 case 0x61: /* popa */
4545 if (ir.regmap[X86_RECORD_R8_REGNUM])
4550 for (regnum = X86_RECORD_REAX_REGNUM;
4551 regnum <= X86_RECORD_REDI_REGNUM;
4553 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
4556 case 0x8f: /* pop */
4557 if (ir.regmap[X86_RECORD_R8_REGNUM])
4558 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
4560 ir.ot = ir.dflag + OT_WORD;
4561 if (i386_record_modrm (&ir))
4564 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
4567 ir.popl_esp_hack = 1 << ir.ot;
4568 if (i386_record_lea_modrm (&ir))
4571 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4574 case 0xc8: /* enter */
4575 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
4576 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4578 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4582 case 0xc9: /* leave */
4583 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4584 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
4587 case 0x07: /* pop es */
4588 if (ir.regmap[X86_RECORD_R8_REGNUM])
4593 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4594 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
4595 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4598 case 0x17: /* pop ss */
4599 if (ir.regmap[X86_RECORD_R8_REGNUM])
4604 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4605 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
4606 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4609 case 0x1f: /* pop ds */
4610 if (ir.regmap[X86_RECORD_R8_REGNUM])
4615 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4616 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
4617 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4620 case 0x0fa1: /* pop fs */
4621 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4622 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
4623 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4626 case 0x0fa9: /* pop gs */
4627 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4628 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
4629 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4632 case 0x88: /* mov */
4636 if ((opcode & 1) == 0)
4639 ir.ot = ir.dflag + OT_WORD;
4641 if (i386_record_modrm (&ir))
4646 if (opcode == 0xc6 || opcode == 0xc7)
4647 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4648 if (i386_record_lea_modrm (&ir))
4653 if (opcode == 0xc6 || opcode == 0xc7)
4655 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4657 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4661 case 0x8a: /* mov */
4663 if ((opcode & 1) == 0)
4666 ir.ot = ir.dflag + OT_WORD;
4667 if (i386_record_modrm (&ir))
4670 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4672 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4675 case 0x8c: /* mov seg */
4676 if (i386_record_modrm (&ir))
4681 opcode = opcode << 8 | ir.modrm;
4686 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4690 if (i386_record_lea_modrm (&ir))
4695 case 0x8e: /* mov seg */
4696 if (i386_record_modrm (&ir))
4701 regnum = X86_RECORD_ES_REGNUM;
4704 regnum = X86_RECORD_SS_REGNUM;
4707 regnum = X86_RECORD_DS_REGNUM;
4710 regnum = X86_RECORD_FS_REGNUM;
4713 regnum = X86_RECORD_GS_REGNUM;
4717 opcode = opcode << 8 | ir.modrm;
4721 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
4722 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4725 case 0x0fb6: /* movzbS */
4726 case 0x0fb7: /* movzwS */
4727 case 0x0fbe: /* movsbS */
4728 case 0x0fbf: /* movswS */
4729 if (i386_record_modrm (&ir))
4731 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
4734 case 0x8d: /* lea */
4735 if (i386_record_modrm (&ir))
4740 opcode = opcode << 8 | ir.modrm;
4745 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4747 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4750 case 0xa0: /* mov EAX */
4753 case 0xd7: /* xlat */
4754 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4757 case 0xa2: /* mov EAX */
4759 if (ir.override >= 0)
4761 if (record_memory_query)
4765 target_terminal_ours ();
4767 Process record ignores the memory change of instruction at address %s\n\
4768 because it can't get the value of the segment register.\n\
4769 Do you want to stop the program?"),
4770 paddress (gdbarch, ir.orig_addr));
4771 target_terminal_inferior ();
4778 if ((opcode & 1) == 0)
4781 ir.ot = ir.dflag + OT_WORD;
4784 if (target_read_memory (ir.addr, buf, 8))
4787 printf_unfiltered (_("Process record: error reading "
4788 "memory at addr 0x%s len = 8.\n"),
4789 paddress (gdbarch, ir.addr));
4793 addr = extract_unsigned_integer (buf, 8, byte_order);
4797 if (target_read_memory (ir.addr, buf, 4))
4800 printf_unfiltered (_("Process record: error reading "
4801 "memory at addr 0x%s len = 4.\n"),
4802 paddress (gdbarch, ir.addr));
4806 addr = extract_unsigned_integer (buf, 4, byte_order);
4810 if (target_read_memory (ir.addr, buf, 2))
4813 printf_unfiltered (_("Process record: error reading "
4814 "memory at addr 0x%s len = 2.\n"),
4815 paddress (gdbarch, ir.addr));
4819 addr = extract_unsigned_integer (buf, 2, byte_order);
4821 if (record_arch_list_add_mem (addr, 1 << ir.ot))
4826 case 0xb0: /* mov R, Ib */
4834 I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
4835 ? ((opcode & 0x7) | ir.rex_b)
4836 : ((opcode & 0x7) & 0x3));
4839 case 0xb8: /* mov R, Iv */
4847 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
4850 case 0x91: /* xchg R, EAX */
4857 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4858 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7);
4861 case 0x86: /* xchg Ev, Gv */
4863 if ((opcode & 1) == 0)
4866 ir.ot = ir.dflag + OT_WORD;
4867 if (i386_record_modrm (&ir))
4872 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4874 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4878 if (i386_record_lea_modrm (&ir))
4882 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4884 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4887 case 0xc4: /* les Gv */
4888 case 0xc5: /* lds Gv */
4889 if (ir.regmap[X86_RECORD_R8_REGNUM])
4895 case 0x0fb2: /* lss Gv */
4896 case 0x0fb4: /* lfs Gv */
4897 case 0x0fb5: /* lgs Gv */
4898 if (i386_record_modrm (&ir))
4906 opcode = opcode << 8 | ir.modrm;
4911 case 0xc4: /* les Gv */
4912 regnum = X86_RECORD_ES_REGNUM;
4914 case 0xc5: /* lds Gv */
4915 regnum = X86_RECORD_DS_REGNUM;
4917 case 0x0fb2: /* lss Gv */
4918 regnum = X86_RECORD_SS_REGNUM;
4920 case 0x0fb4: /* lfs Gv */
4921 regnum = X86_RECORD_FS_REGNUM;
4923 case 0x0fb5: /* lgs Gv */
4924 regnum = X86_RECORD_GS_REGNUM;
4927 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
4928 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
4929 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4932 case 0xc0: /* shifts */
4938 if ((opcode & 1) == 0)
4941 ir.ot = ir.dflag + OT_WORD;
4942 if (i386_record_modrm (&ir))
4944 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
4946 if (i386_record_lea_modrm (&ir))
4952 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4954 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4956 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4963 if (i386_record_modrm (&ir))
4967 if (record_arch_list_add_reg (ir.regcache, ir.rm))
4972 if (i386_record_lea_modrm (&ir))
4977 case 0xd8: /* Floats. */
4985 if (i386_record_modrm (&ir))
4987 ir.reg |= ((opcode & 7) << 3);
4993 if (i386_record_lea_modrm_addr (&ir, &addr64))
5001 /* For fcom, ficom nothing to do. */
5007 /* For fcomp, ficomp pop FPU stack, store all. */
5008 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5035 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5036 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5037 of code, always affects st(0) register. */
5038 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
5062 /* Handling fld, fild. */
5063 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5067 switch (ir.reg >> 4)
5070 if (record_arch_list_add_mem (addr64, 4))
5074 if (record_arch_list_add_mem (addr64, 8))
5080 if (record_arch_list_add_mem (addr64, 2))
5086 switch (ir.reg >> 4)
5089 if (record_arch_list_add_mem (addr64, 4))
5091 if (3 == (ir.reg & 7))
5093 /* For fstp m32fp. */
5094 if (i386_record_floats (gdbarch, &ir,
5095 I386_SAVE_FPU_REGS))
5100 if (record_arch_list_add_mem (addr64, 4))
5102 if ((3 == (ir.reg & 7))
5103 || (5 == (ir.reg & 7))
5104 || (7 == (ir.reg & 7)))
5106 /* For fstp insn. */
5107 if (i386_record_floats (gdbarch, &ir,
5108 I386_SAVE_FPU_REGS))
5113 if (record_arch_list_add_mem (addr64, 8))
5115 if (3 == (ir.reg & 7))
5117 /* For fstp m64fp. */
5118 if (i386_record_floats (gdbarch, &ir,
5119 I386_SAVE_FPU_REGS))
5124 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
5126 /* For fistp, fbld, fild, fbstp. */
5127 if (i386_record_floats (gdbarch, &ir,
5128 I386_SAVE_FPU_REGS))
5133 if (record_arch_list_add_mem (addr64, 2))
5142 if (i386_record_floats (gdbarch, &ir,
5143 I386_SAVE_FPU_ENV_REG_STACK))
5148 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
5153 if (i386_record_floats (gdbarch, &ir,
5154 I386_SAVE_FPU_ENV_REG_STACK))
5160 if (record_arch_list_add_mem (addr64, 28))
5165 if (record_arch_list_add_mem (addr64, 14))
5171 if (record_arch_list_add_mem (addr64, 2))
5173 /* Insn fstp, fbstp. */
5174 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5179 if (record_arch_list_add_mem (addr64, 10))
5185 if (record_arch_list_add_mem (addr64, 28))
5191 if (record_arch_list_add_mem (addr64, 14))
5195 if (record_arch_list_add_mem (addr64, 80))
5198 if (i386_record_floats (gdbarch, &ir,
5199 I386_SAVE_FPU_ENV_REG_STACK))
5203 if (record_arch_list_add_mem (addr64, 8))
5206 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5211 opcode = opcode << 8 | ir.modrm;
5216 /* Opcode is an extension of modR/M byte. */
5222 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
5226 if (0x0c == (ir.modrm >> 4))
5228 if ((ir.modrm & 0x0f) <= 7)
5230 if (i386_record_floats (gdbarch, &ir,
5231 I386_SAVE_FPU_REGS))
5236 if (i386_record_floats (gdbarch, &ir,
5237 I387_ST0_REGNUM (tdep)))
5239 /* If only st(0) is changing, then we have already
5241 if ((ir.modrm & 0x0f) - 0x08)
5243 if (i386_record_floats (gdbarch, &ir,
5244 I387_ST0_REGNUM (tdep) +
5245 ((ir.modrm & 0x0f) - 0x08)))
5263 if (i386_record_floats (gdbarch, &ir,
5264 I387_ST0_REGNUM (tdep)))
5282 if (i386_record_floats (gdbarch, &ir,
5283 I386_SAVE_FPU_REGS))
5287 if (i386_record_floats (gdbarch, &ir,
5288 I387_ST0_REGNUM (tdep)))
5290 if (i386_record_floats (gdbarch, &ir,
5291 I387_ST0_REGNUM (tdep) + 1))
5298 if (0xe9 == ir.modrm)
5300 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5303 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
5305 if (i386_record_floats (gdbarch, &ir,
5306 I387_ST0_REGNUM (tdep)))
5308 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
5310 if (i386_record_floats (gdbarch, &ir,
5311 I387_ST0_REGNUM (tdep) +
5315 else if ((ir.modrm & 0x0f) - 0x08)
5317 if (i386_record_floats (gdbarch, &ir,
5318 I387_ST0_REGNUM (tdep) +
5319 ((ir.modrm & 0x0f) - 0x08)))
5325 if (0xe3 == ir.modrm)
5327 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
5330 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
5332 if (i386_record_floats (gdbarch, &ir,
5333 I387_ST0_REGNUM (tdep)))
5335 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
5337 if (i386_record_floats (gdbarch, &ir,
5338 I387_ST0_REGNUM (tdep) +
5342 else if ((ir.modrm & 0x0f) - 0x08)
5344 if (i386_record_floats (gdbarch, &ir,
5345 I387_ST0_REGNUM (tdep) +
5346 ((ir.modrm & 0x0f) - 0x08)))
5352 if ((0x0c == ir.modrm >> 4)
5353 || (0x0d == ir.modrm >> 4)
5354 || (0x0f == ir.modrm >> 4))
5356 if ((ir.modrm & 0x0f) <= 7)
5358 if (i386_record_floats (gdbarch, &ir,
5359 I387_ST0_REGNUM (tdep) +
5365 if (i386_record_floats (gdbarch, &ir,
5366 I387_ST0_REGNUM (tdep) +
5367 ((ir.modrm & 0x0f) - 0x08)))
5373 if (0x0c == ir.modrm >> 4)
5375 if (i386_record_floats (gdbarch, &ir,
5376 I387_FTAG_REGNUM (tdep)))
5379 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
5381 if ((ir.modrm & 0x0f) <= 7)
5383 if (i386_record_floats (gdbarch, &ir,
5384 I387_ST0_REGNUM (tdep) +
5390 if (i386_record_floats (gdbarch, &ir,
5391 I386_SAVE_FPU_REGS))
5397 if ((0x0c == ir.modrm >> 4)
5398 || (0x0e == ir.modrm >> 4)
5399 || (0x0f == ir.modrm >> 4)
5400 || (0xd9 == ir.modrm))
5402 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5407 if (0xe0 == ir.modrm)
5409 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
5412 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
5414 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5422 case 0xa4: /* movsS */
5424 case 0xaa: /* stosS */
5426 case 0x6c: /* insS */
5428 regcache_raw_read_unsigned (ir.regcache,
5429 ir.regmap[X86_RECORD_RECX_REGNUM],
5435 if ((opcode & 1) == 0)
5438 ir.ot = ir.dflag + OT_WORD;
5439 regcache_raw_read_unsigned (ir.regcache,
5440 ir.regmap[X86_RECORD_REDI_REGNUM],
5443 regcache_raw_read_unsigned (ir.regcache,
5444 ir.regmap[X86_RECORD_ES_REGNUM],
5446 regcache_raw_read_unsigned (ir.regcache,
5447 ir.regmap[X86_RECORD_DS_REGNUM],
5449 if (ir.aflag && (es != ds))
5451 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5452 if (record_memory_query)
5456 target_terminal_ours ();
5458 Process record ignores the memory change of instruction at address %s\n\
5459 because it can't get the value of the segment register.\n\
5460 Do you want to stop the program?"),
5461 paddress (gdbarch, ir.orig_addr));
5462 target_terminal_inferior ();
5469 if (record_arch_list_add_mem (addr, 1 << ir.ot))
5473 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5474 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5475 if (opcode == 0xa4 || opcode == 0xa5)
5476 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5477 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5478 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5482 case 0xa6: /* cmpsS */
5484 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5485 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5486 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5487 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5488 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5491 case 0xac: /* lodsS */
5493 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5494 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5495 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5496 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5497 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5500 case 0xae: /* scasS */
5502 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5503 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5504 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5505 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5508 case 0x6e: /* outsS */
5510 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5511 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5512 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5513 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5516 case 0xe4: /* port I/O */
5520 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5521 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5531 case 0xc2: /* ret im */
5532 case 0xc3: /* ret */
5533 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5534 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5537 case 0xca: /* lret im */
5538 case 0xcb: /* lret */
5539 case 0xcf: /* iret */
5540 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5541 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5542 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5545 case 0xe8: /* call im */
5546 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5548 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5552 case 0x9a: /* lcall im */
5553 if (ir.regmap[X86_RECORD_R8_REGNUM])
5558 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5559 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5563 case 0xe9: /* jmp im */
5564 case 0xea: /* ljmp im */
5565 case 0xeb: /* jmp Jb */
5566 case 0x70: /* jcc Jb */
5582 case 0x0f80: /* jcc Jv */
5600 case 0x0f90: /* setcc Gv */
5616 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5618 if (i386_record_modrm (&ir))
5621 I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
5625 if (i386_record_lea_modrm (&ir))
5630 case 0x0f40: /* cmov Gv, Ev */
5646 if (i386_record_modrm (&ir))
5649 if (ir.dflag == OT_BYTE)
5651 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
5655 case 0x9c: /* pushf */
5656 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5657 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5659 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5663 case 0x9d: /* popf */
5664 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5665 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5668 case 0x9e: /* sahf */
5669 if (ir.regmap[X86_RECORD_R8_REGNUM])
5675 case 0xf5: /* cmc */
5676 case 0xf8: /* clc */
5677 case 0xf9: /* stc */
5678 case 0xfc: /* cld */
5679 case 0xfd: /* std */
5680 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5683 case 0x9f: /* lahf */
5684 if (ir.regmap[X86_RECORD_R8_REGNUM])
5689 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5690 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5693 /* bit operations */
5694 case 0x0fba: /* bt/bts/btr/btc Gv, im */
5695 ir.ot = ir.dflag + OT_WORD;
5696 if (i386_record_modrm (&ir))
5701 opcode = opcode << 8 | ir.modrm;
5707 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5710 if (i386_record_lea_modrm (&ir))
5714 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5717 case 0x0fa3: /* bt Gv, Ev */
5718 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5721 case 0x0fab: /* bts */
5722 case 0x0fb3: /* btr */
5723 case 0x0fbb: /* btc */
5724 ir.ot = ir.dflag + OT_WORD;
5725 if (i386_record_modrm (&ir))
5728 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5732 if (i386_record_lea_modrm_addr (&ir, &addr64))
5734 regcache_raw_read_unsigned (ir.regcache,
5735 ir.regmap[ir.reg | rex_r],
5740 addr64 += ((int16_t) addr >> 4) << 4;
5743 addr64 += ((int32_t) addr >> 5) << 5;
5746 addr64 += ((int64_t) addr >> 6) << 6;
5749 if (record_arch_list_add_mem (addr64, 1 << ir.ot))
5751 if (i386_record_lea_modrm (&ir))
5754 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5757 case 0x0fbc: /* bsf */
5758 case 0x0fbd: /* bsr */
5759 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5760 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5764 case 0x27: /* daa */
5765 case 0x2f: /* das */
5766 case 0x37: /* aaa */
5767 case 0x3f: /* aas */
5768 case 0xd4: /* aam */
5769 case 0xd5: /* aad */
5770 if (ir.regmap[X86_RECORD_R8_REGNUM])
5775 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5776 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5780 case 0x90: /* nop */
5781 if (prefixes & PREFIX_LOCK)
5788 case 0x9b: /* fwait */
5789 if (target_read_memory (ir.addr, &opcode8, 1))
5792 printf_unfiltered (_("Process record: error reading memory at "
5793 "addr 0x%s len = 1.\n"),
5794 paddress (gdbarch, ir.addr));
5797 opcode = (uint32_t) opcode8;
5803 case 0xcc: /* int3 */
5804 printf_unfiltered (_("Process record does not support instruction "
5811 case 0xcd: /* int */
5815 if (target_read_memory (ir.addr, &interrupt, 1))
5818 printf_unfiltered (_("Process record: error reading memory "
5819 "at addr %s len = 1.\n"),
5820 paddress (gdbarch, ir.addr));
5824 if (interrupt != 0x80
5825 || tdep->i386_intx80_record == NULL)
5827 printf_unfiltered (_("Process record does not support "
5828 "instruction int 0x%02x.\n"),
5833 ret = tdep->i386_intx80_record (ir.regcache);
5840 case 0xce: /* into */
5841 printf_unfiltered (_("Process record does not support "
5842 "instruction into.\n"));
5847 case 0xfa: /* cli */
5848 case 0xfb: /* sti */
5851 case 0x62: /* bound */
5852 printf_unfiltered (_("Process record does not support "
5853 "instruction bound.\n"));
5858 case 0x0fc8: /* bswap reg */
5866 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
5869 case 0xd6: /* salc */
5870 if (ir.regmap[X86_RECORD_R8_REGNUM])
5875 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5876 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5879 case 0xe0: /* loopnz */
5880 case 0xe1: /* loopz */
5881 case 0xe2: /* loop */
5882 case 0xe3: /* jecxz */
5883 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5884 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5887 case 0x0f30: /* wrmsr */
5888 printf_unfiltered (_("Process record does not support "
5889 "instruction wrmsr.\n"));
5894 case 0x0f32: /* rdmsr */
5895 printf_unfiltered (_("Process record does not support "
5896 "instruction rdmsr.\n"));
5901 case 0x0f31: /* rdtsc */
5902 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5903 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5906 case 0x0f34: /* sysenter */
5909 if (ir.regmap[X86_RECORD_R8_REGNUM])
5914 if (tdep->i386_sysenter_record == NULL)
5916 printf_unfiltered (_("Process record does not support "
5917 "instruction sysenter.\n"));
5921 ret = tdep->i386_sysenter_record (ir.regcache);
5927 case 0x0f35: /* sysexit */
5928 printf_unfiltered (_("Process record does not support "
5929 "instruction sysexit.\n"));
5934 case 0x0f05: /* syscall */
5937 if (tdep->i386_syscall_record == NULL)
5939 printf_unfiltered (_("Process record does not support "
5940 "instruction syscall.\n"));
5944 ret = tdep->i386_syscall_record (ir.regcache);
5950 case 0x0f07: /* sysret */
5951 printf_unfiltered (_("Process record does not support "
5952 "instruction sysret.\n"));
5957 case 0x0fa2: /* cpuid */
5958 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5959 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5960 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5961 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
5964 case 0xf4: /* hlt */
5965 printf_unfiltered (_("Process record does not support "
5966 "instruction hlt.\n"));
5972 if (i386_record_modrm (&ir))
5979 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5983 if (i386_record_lea_modrm (&ir))
5992 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5996 opcode = opcode << 8 | ir.modrm;
6003 if (i386_record_modrm (&ir))
6014 opcode = opcode << 8 | ir.modrm;
6017 if (ir.override >= 0)
6019 if (record_memory_query)
6023 target_terminal_ours ();
6025 Process record ignores the memory change of instruction at address %s\n\
6026 because it can't get the value of the segment register.\n\
6027 Do you want to stop the program?"),
6028 paddress (gdbarch, ir.orig_addr));
6029 target_terminal_inferior ();
6036 if (i386_record_lea_modrm_addr (&ir, &addr64))
6038 if (record_arch_list_add_mem (addr64, 2))
6041 if (ir.regmap[X86_RECORD_R8_REGNUM])
6043 if (record_arch_list_add_mem (addr64, 8))
6048 if (record_arch_list_add_mem (addr64, 4))
6059 case 0: /* monitor */
6062 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6066 opcode = opcode << 8 | ir.modrm;
6074 if (ir.override >= 0)
6076 if (record_memory_query)
6080 target_terminal_ours ();
6082 Process record ignores the memory change of instruction at address %s\n\
6083 because it can't get the value of the segment register.\n\
6084 Do you want to stop the program?"),
6085 paddress (gdbarch, ir.orig_addr));
6086 target_terminal_inferior ();
6095 if (i386_record_lea_modrm_addr (&ir, &addr64))
6097 if (record_arch_list_add_mem (addr64, 2))
6100 if (ir.regmap[X86_RECORD_R8_REGNUM])
6102 if (record_arch_list_add_mem (addr64, 8))
6107 if (record_arch_list_add_mem (addr64, 4))
6119 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6120 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6124 else if (ir.rm == 1)
6131 opcode = opcode << 8 | ir.modrm;
6138 if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
6144 if (i386_record_lea_modrm (&ir))
6147 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6150 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6152 case 7: /* invlpg */
6155 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
6156 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
6160 opcode = opcode << 8 | ir.modrm;
6165 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6169 opcode = opcode << 8 | ir.modrm;
6175 case 0x0f08: /* invd */
6176 case 0x0f09: /* wbinvd */
6179 case 0x63: /* arpl */
6180 if (i386_record_modrm (&ir))
6182 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
6184 I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
6185 ? (ir.reg | rex_r) : ir.rm);
6189 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
6190 if (i386_record_lea_modrm (&ir))
6193 if (!ir.regmap[X86_RECORD_R8_REGNUM])
6194 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6197 case 0x0f02: /* lar */
6198 case 0x0f03: /* lsl */
6199 if (i386_record_modrm (&ir))
6201 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6202 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6206 if (i386_record_modrm (&ir))
6208 if (ir.mod == 3 && ir.reg == 3)
6211 opcode = opcode << 8 | ir.modrm;
6223 /* nop (multi byte) */
6226 case 0x0f20: /* mov reg, crN */
6227 case 0x0f22: /* mov crN, reg */
6228 if (i386_record_modrm (&ir))
6230 if ((ir.modrm & 0xc0) != 0xc0)
6233 opcode = opcode << 8 | ir.modrm;
6244 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6246 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6250 opcode = opcode << 8 | ir.modrm;
6256 case 0x0f21: /* mov reg, drN */
6257 case 0x0f23: /* mov drN, reg */
6258 if (i386_record_modrm (&ir))
6260 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
6261 || ir.reg == 5 || ir.reg >= 8)
6264 opcode = opcode << 8 | ir.modrm;
6268 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6270 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6273 case 0x0f06: /* clts */
6274 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6277 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
6279 case 0x0f0d: /* 3DNow! prefetch */
6282 case 0x0f0e: /* 3DNow! femms */
6283 case 0x0f77: /* emms */
6284 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
6286 record_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
6289 case 0x0f0f: /* 3DNow! data */
6290 if (i386_record_modrm (&ir))
6292 if (target_read_memory (ir.addr, &opcode8, 1))
6294 printf_unfiltered (_("Process record: error reading memory at "
6295 "addr %s len = 1.\n"),
6296 paddress (gdbarch, ir.addr));
6302 case 0x0c: /* 3DNow! pi2fw */
6303 case 0x0d: /* 3DNow! pi2fd */
6304 case 0x1c: /* 3DNow! pf2iw */
6305 case 0x1d: /* 3DNow! pf2id */
6306 case 0x8a: /* 3DNow! pfnacc */
6307 case 0x8e: /* 3DNow! pfpnacc */
6308 case 0x90: /* 3DNow! pfcmpge */
6309 case 0x94: /* 3DNow! pfmin */
6310 case 0x96: /* 3DNow! pfrcp */
6311 case 0x97: /* 3DNow! pfrsqrt */
6312 case 0x9a: /* 3DNow! pfsub */
6313 case 0x9e: /* 3DNow! pfadd */
6314 case 0xa0: /* 3DNow! pfcmpgt */
6315 case 0xa4: /* 3DNow! pfmax */
6316 case 0xa6: /* 3DNow! pfrcpit1 */
6317 case 0xa7: /* 3DNow! pfrsqit1 */
6318 case 0xaa: /* 3DNow! pfsubr */
6319 case 0xae: /* 3DNow! pfacc */
6320 case 0xb0: /* 3DNow! pfcmpeq */
6321 case 0xb4: /* 3DNow! pfmul */
6322 case 0xb6: /* 3DNow! pfrcpit2 */
6323 case 0xb7: /* 3DNow! pmulhrw */
6324 case 0xbb: /* 3DNow! pswapd */
6325 case 0xbf: /* 3DNow! pavgusb */
6326 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
6327 goto no_support_3dnow_data;
6328 record_arch_list_add_reg (ir.regcache, ir.reg);
6332 no_support_3dnow_data:
6333 opcode = (opcode << 8) | opcode8;
6339 case 0x0faa: /* rsm */
6340 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6341 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6342 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6343 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6344 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
6345 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6346 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
6347 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6348 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6352 if (i386_record_modrm (&ir))
6356 case 0: /* fxsave */
6360 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6361 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
6363 if (record_arch_list_add_mem (tmpu64, 512))
6368 case 1: /* fxrstor */
6372 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6374 for (i = I387_MM0_REGNUM (tdep);
6375 i386_mmx_regnum_p (gdbarch, i); i++)
6376 record_arch_list_add_reg (ir.regcache, i);
6378 for (i = I387_XMM0_REGNUM (tdep);
6379 i386_xmm_regnum_p (gdbarch, i); i++)
6380 record_arch_list_add_reg (ir.regcache, i);
6382 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
6383 record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
6385 for (i = I387_ST0_REGNUM (tdep);
6386 i386_fp_regnum_p (gdbarch, i); i++)
6387 record_arch_list_add_reg (ir.regcache, i);
6389 for (i = I387_FCTRL_REGNUM (tdep);
6390 i386_fpc_regnum_p (gdbarch, i); i++)
6391 record_arch_list_add_reg (ir.regcache, i);
6395 case 2: /* ldmxcsr */
6396 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
6398 record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
6401 case 3: /* stmxcsr */
6403 if (i386_record_lea_modrm (&ir))
6407 case 5: /* lfence */
6408 case 6: /* mfence */
6409 case 7: /* sfence clflush */
6413 opcode = (opcode << 8) | ir.modrm;
6419 case 0x0fc3: /* movnti */
6420 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
6421 if (i386_record_modrm (&ir))
6426 if (i386_record_lea_modrm (&ir))
6430 /* Add prefix to opcode. */
6557 reswitch_prefix_add:
6565 if (target_read_memory (ir.addr, &opcode8, 1))
6567 printf_unfiltered (_("Process record: error reading memory at "
6568 "addr %s len = 1.\n"),
6569 paddress (gdbarch, ir.addr));
6573 opcode = (uint32_t) opcode8 | opcode << 8;
6574 goto reswitch_prefix_add;
6577 case 0x0f10: /* movups */
6578 case 0x660f10: /* movupd */
6579 case 0xf30f10: /* movss */
6580 case 0xf20f10: /* movsd */
6581 case 0x0f12: /* movlps */
6582 case 0x660f12: /* movlpd */
6583 case 0xf30f12: /* movsldup */
6584 case 0xf20f12: /* movddup */
6585 case 0x0f14: /* unpcklps */
6586 case 0x660f14: /* unpcklpd */
6587 case 0x0f15: /* unpckhps */
6588 case 0x660f15: /* unpckhpd */
6589 case 0x0f16: /* movhps */
6590 case 0x660f16: /* movhpd */
6591 case 0xf30f16: /* movshdup */
6592 case 0x0f28: /* movaps */
6593 case 0x660f28: /* movapd */
6594 case 0x0f2a: /* cvtpi2ps */
6595 case 0x660f2a: /* cvtpi2pd */
6596 case 0xf30f2a: /* cvtsi2ss */
6597 case 0xf20f2a: /* cvtsi2sd */
6598 case 0x0f2c: /* cvttps2pi */
6599 case 0x660f2c: /* cvttpd2pi */
6600 case 0x0f2d: /* cvtps2pi */
6601 case 0x660f2d: /* cvtpd2pi */
6602 case 0x660f3800: /* pshufb */
6603 case 0x660f3801: /* phaddw */
6604 case 0x660f3802: /* phaddd */
6605 case 0x660f3803: /* phaddsw */
6606 case 0x660f3804: /* pmaddubsw */
6607 case 0x660f3805: /* phsubw */
6608 case 0x660f3806: /* phsubd */
6609 case 0x660f3807: /* phsubsw */
6610 case 0x660f3808: /* psignb */
6611 case 0x660f3809: /* psignw */
6612 case 0x660f380a: /* psignd */
6613 case 0x660f380b: /* pmulhrsw */
6614 case 0x660f3810: /* pblendvb */
6615 case 0x660f3814: /* blendvps */
6616 case 0x660f3815: /* blendvpd */
6617 case 0x660f381c: /* pabsb */
6618 case 0x660f381d: /* pabsw */
6619 case 0x660f381e: /* pabsd */
6620 case 0x660f3820: /* pmovsxbw */
6621 case 0x660f3821: /* pmovsxbd */
6622 case 0x660f3822: /* pmovsxbq */
6623 case 0x660f3823: /* pmovsxwd */
6624 case 0x660f3824: /* pmovsxwq */
6625 case 0x660f3825: /* pmovsxdq */
6626 case 0x660f3828: /* pmuldq */
6627 case 0x660f3829: /* pcmpeqq */
6628 case 0x660f382a: /* movntdqa */
6629 case 0x660f3a08: /* roundps */
6630 case 0x660f3a09: /* roundpd */
6631 case 0x660f3a0a: /* roundss */
6632 case 0x660f3a0b: /* roundsd */
6633 case 0x660f3a0c: /* blendps */
6634 case 0x660f3a0d: /* blendpd */
6635 case 0x660f3a0e: /* pblendw */
6636 case 0x660f3a0f: /* palignr */
6637 case 0x660f3a20: /* pinsrb */
6638 case 0x660f3a21: /* insertps */
6639 case 0x660f3a22: /* pinsrd pinsrq */
6640 case 0x660f3a40: /* dpps */
6641 case 0x660f3a41: /* dppd */
6642 case 0x660f3a42: /* mpsadbw */
6643 case 0x660f3a60: /* pcmpestrm */
6644 case 0x660f3a61: /* pcmpestri */
6645 case 0x660f3a62: /* pcmpistrm */
6646 case 0x660f3a63: /* pcmpistri */
6647 case 0x0f51: /* sqrtps */
6648 case 0x660f51: /* sqrtpd */
6649 case 0xf20f51: /* sqrtsd */
6650 case 0xf30f51: /* sqrtss */
6651 case 0x0f52: /* rsqrtps */
6652 case 0xf30f52: /* rsqrtss */
6653 case 0x0f53: /* rcpps */
6654 case 0xf30f53: /* rcpss */
6655 case 0x0f54: /* andps */
6656 case 0x660f54: /* andpd */
6657 case 0x0f55: /* andnps */
6658 case 0x660f55: /* andnpd */
6659 case 0x0f56: /* orps */
6660 case 0x660f56: /* orpd */
6661 case 0x0f57: /* xorps */
6662 case 0x660f57: /* xorpd */
6663 case 0x0f58: /* addps */
6664 case 0x660f58: /* addpd */
6665 case 0xf20f58: /* addsd */
6666 case 0xf30f58: /* addss */
6667 case 0x0f59: /* mulps */
6668 case 0x660f59: /* mulpd */
6669 case 0xf20f59: /* mulsd */
6670 case 0xf30f59: /* mulss */
6671 case 0x0f5a: /* cvtps2pd */
6672 case 0x660f5a: /* cvtpd2ps */
6673 case 0xf20f5a: /* cvtsd2ss */
6674 case 0xf30f5a: /* cvtss2sd */
6675 case 0x0f5b: /* cvtdq2ps */
6676 case 0x660f5b: /* cvtps2dq */
6677 case 0xf30f5b: /* cvttps2dq */
6678 case 0x0f5c: /* subps */
6679 case 0x660f5c: /* subpd */
6680 case 0xf20f5c: /* subsd */
6681 case 0xf30f5c: /* subss */
6682 case 0x0f5d: /* minps */
6683 case 0x660f5d: /* minpd */
6684 case 0xf20f5d: /* minsd */
6685 case 0xf30f5d: /* minss */
6686 case 0x0f5e: /* divps */
6687 case 0x660f5e: /* divpd */
6688 case 0xf20f5e: /* divsd */
6689 case 0xf30f5e: /* divss */
6690 case 0x0f5f: /* maxps */
6691 case 0x660f5f: /* maxpd */
6692 case 0xf20f5f: /* maxsd */
6693 case 0xf30f5f: /* maxss */
6694 case 0x660f60: /* punpcklbw */
6695 case 0x660f61: /* punpcklwd */
6696 case 0x660f62: /* punpckldq */
6697 case 0x660f63: /* packsswb */
6698 case 0x660f64: /* pcmpgtb */
6699 case 0x660f65: /* pcmpgtw */
6700 case 0x660f66: /* pcmpgtd */
6701 case 0x660f67: /* packuswb */
6702 case 0x660f68: /* punpckhbw */
6703 case 0x660f69: /* punpckhwd */
6704 case 0x660f6a: /* punpckhdq */
6705 case 0x660f6b: /* packssdw */
6706 case 0x660f6c: /* punpcklqdq */
6707 case 0x660f6d: /* punpckhqdq */
6708 case 0x660f6e: /* movd */
6709 case 0x660f6f: /* movdqa */
6710 case 0xf30f6f: /* movdqu */
6711 case 0x660f70: /* pshufd */
6712 case 0xf20f70: /* pshuflw */
6713 case 0xf30f70: /* pshufhw */
6714 case 0x660f74: /* pcmpeqb */
6715 case 0x660f75: /* pcmpeqw */
6716 case 0x660f76: /* pcmpeqd */
6717 case 0x660f7c: /* haddpd */
6718 case 0xf20f7c: /* haddps */
6719 case 0x660f7d: /* hsubpd */
6720 case 0xf20f7d: /* hsubps */
6721 case 0xf30f7e: /* movq */
6722 case 0x0fc2: /* cmpps */
6723 case 0x660fc2: /* cmppd */
6724 case 0xf20fc2: /* cmpsd */
6725 case 0xf30fc2: /* cmpss */
6726 case 0x660fc4: /* pinsrw */
6727 case 0x0fc6: /* shufps */
6728 case 0x660fc6: /* shufpd */
6729 case 0x660fd0: /* addsubpd */
6730 case 0xf20fd0: /* addsubps */
6731 case 0x660fd1: /* psrlw */
6732 case 0x660fd2: /* psrld */
6733 case 0x660fd3: /* psrlq */
6734 case 0x660fd4: /* paddq */
6735 case 0x660fd5: /* pmullw */
6736 case 0xf30fd6: /* movq2dq */
6737 case 0x660fd8: /* psubusb */
6738 case 0x660fd9: /* psubusw */
6739 case 0x660fda: /* pminub */
6740 case 0x660fdb: /* pand */
6741 case 0x660fdc: /* paddusb */
6742 case 0x660fdd: /* paddusw */
6743 case 0x660fde: /* pmaxub */
6744 case 0x660fdf: /* pandn */
6745 case 0x660fe0: /* pavgb */
6746 case 0x660fe1: /* psraw */
6747 case 0x660fe2: /* psrad */
6748 case 0x660fe3: /* pavgw */
6749 case 0x660fe4: /* pmulhuw */
6750 case 0x660fe5: /* pmulhw */
6751 case 0x660fe6: /* cvttpd2dq */
6752 case 0xf20fe6: /* cvtpd2dq */
6753 case 0xf30fe6: /* cvtdq2pd */
6754 case 0x660fe8: /* psubsb */
6755 case 0x660fe9: /* psubsw */
6756 case 0x660fea: /* pminsw */
6757 case 0x660feb: /* por */
6758 case 0x660fec: /* paddsb */
6759 case 0x660fed: /* paddsw */
6760 case 0x660fee: /* pmaxsw */
6761 case 0x660fef: /* pxor */
6762 case 0xf20ff0: /* lddqu */
6763 case 0x660ff1: /* psllw */
6764 case 0x660ff2: /* pslld */
6765 case 0x660ff3: /* psllq */
6766 case 0x660ff4: /* pmuludq */
6767 case 0x660ff5: /* pmaddwd */
6768 case 0x660ff6: /* psadbw */
6769 case 0x660ff8: /* psubb */
6770 case 0x660ff9: /* psubw */
6771 case 0x660ffa: /* psubd */
6772 case 0x660ffb: /* psubq */
6773 case 0x660ffc: /* paddb */
6774 case 0x660ffd: /* paddw */
6775 case 0x660ffe: /* paddd */
6776 if (i386_record_modrm (&ir))
6779 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
6781 record_arch_list_add_reg (ir.regcache,
6782 I387_XMM0_REGNUM (tdep) + ir.reg);
6783 if ((opcode & 0xfffffffc) == 0x660f3a60)
6784 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6787 case 0x0f11: /* movups */
6788 case 0x660f11: /* movupd */
6789 case 0xf30f11: /* movss */
6790 case 0xf20f11: /* movsd */
6791 case 0x0f13: /* movlps */
6792 case 0x660f13: /* movlpd */
6793 case 0x0f17: /* movhps */
6794 case 0x660f17: /* movhpd */
6795 case 0x0f29: /* movaps */
6796 case 0x660f29: /* movapd */
6797 case 0x660f3a14: /* pextrb */
6798 case 0x660f3a15: /* pextrw */
6799 case 0x660f3a16: /* pextrd pextrq */
6800 case 0x660f3a17: /* extractps */
6801 case 0x660f7f: /* movdqa */
6802 case 0xf30f7f: /* movdqu */
6803 if (i386_record_modrm (&ir))
6807 if (opcode == 0x0f13 || opcode == 0x660f13
6808 || opcode == 0x0f17 || opcode == 0x660f17)
6811 if (!i386_xmm_regnum_p (gdbarch,
6812 I387_XMM0_REGNUM (tdep) + ir.rm))
6814 record_arch_list_add_reg (ir.regcache,
6815 I387_XMM0_REGNUM (tdep) + ir.rm);
6837 if (i386_record_lea_modrm (&ir))
6842 case 0x0f2b: /* movntps */
6843 case 0x660f2b: /* movntpd */
6844 case 0x0fe7: /* movntq */
6845 case 0x660fe7: /* movntdq */
6848 if (opcode == 0x0fe7)
6852 if (i386_record_lea_modrm (&ir))
6856 case 0xf30f2c: /* cvttss2si */
6857 case 0xf20f2c: /* cvttsd2si */
6858 case 0xf30f2d: /* cvtss2si */
6859 case 0xf20f2d: /* cvtsd2si */
6860 case 0xf20f38f0: /* crc32 */
6861 case 0xf20f38f1: /* crc32 */
6862 case 0x0f50: /* movmskps */
6863 case 0x660f50: /* movmskpd */
6864 case 0x0fc5: /* pextrw */
6865 case 0x660fc5: /* pextrw */
6866 case 0x0fd7: /* pmovmskb */
6867 case 0x660fd7: /* pmovmskb */
6868 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6871 case 0x0f3800: /* pshufb */
6872 case 0x0f3801: /* phaddw */
6873 case 0x0f3802: /* phaddd */
6874 case 0x0f3803: /* phaddsw */
6875 case 0x0f3804: /* pmaddubsw */
6876 case 0x0f3805: /* phsubw */
6877 case 0x0f3806: /* phsubd */
6878 case 0x0f3807: /* phsubsw */
6879 case 0x0f3808: /* psignb */
6880 case 0x0f3809: /* psignw */
6881 case 0x0f380a: /* psignd */
6882 case 0x0f380b: /* pmulhrsw */
6883 case 0x0f381c: /* pabsb */
6884 case 0x0f381d: /* pabsw */
6885 case 0x0f381e: /* pabsd */
6886 case 0x0f382b: /* packusdw */
6887 case 0x0f3830: /* pmovzxbw */
6888 case 0x0f3831: /* pmovzxbd */
6889 case 0x0f3832: /* pmovzxbq */
6890 case 0x0f3833: /* pmovzxwd */
6891 case 0x0f3834: /* pmovzxwq */
6892 case 0x0f3835: /* pmovzxdq */
6893 case 0x0f3837: /* pcmpgtq */
6894 case 0x0f3838: /* pminsb */
6895 case 0x0f3839: /* pminsd */
6896 case 0x0f383a: /* pminuw */
6897 case 0x0f383b: /* pminud */
6898 case 0x0f383c: /* pmaxsb */
6899 case 0x0f383d: /* pmaxsd */
6900 case 0x0f383e: /* pmaxuw */
6901 case 0x0f383f: /* pmaxud */
6902 case 0x0f3840: /* pmulld */
6903 case 0x0f3841: /* phminposuw */
6904 case 0x0f3a0f: /* palignr */
6905 case 0x0f60: /* punpcklbw */
6906 case 0x0f61: /* punpcklwd */
6907 case 0x0f62: /* punpckldq */
6908 case 0x0f63: /* packsswb */
6909 case 0x0f64: /* pcmpgtb */
6910 case 0x0f65: /* pcmpgtw */
6911 case 0x0f66: /* pcmpgtd */
6912 case 0x0f67: /* packuswb */
6913 case 0x0f68: /* punpckhbw */
6914 case 0x0f69: /* punpckhwd */
6915 case 0x0f6a: /* punpckhdq */
6916 case 0x0f6b: /* packssdw */
6917 case 0x0f6e: /* movd */
6918 case 0x0f6f: /* movq */
6919 case 0x0f70: /* pshufw */
6920 case 0x0f74: /* pcmpeqb */
6921 case 0x0f75: /* pcmpeqw */
6922 case 0x0f76: /* pcmpeqd */
6923 case 0x0fc4: /* pinsrw */
6924 case 0x0fd1: /* psrlw */
6925 case 0x0fd2: /* psrld */
6926 case 0x0fd3: /* psrlq */
6927 case 0x0fd4: /* paddq */
6928 case 0x0fd5: /* pmullw */
6929 case 0xf20fd6: /* movdq2q */
6930 case 0x0fd8: /* psubusb */
6931 case 0x0fd9: /* psubusw */
6932 case 0x0fda: /* pminub */
6933 case 0x0fdb: /* pand */
6934 case 0x0fdc: /* paddusb */
6935 case 0x0fdd: /* paddusw */
6936 case 0x0fde: /* pmaxub */
6937 case 0x0fdf: /* pandn */
6938 case 0x0fe0: /* pavgb */
6939 case 0x0fe1: /* psraw */
6940 case 0x0fe2: /* psrad */
6941 case 0x0fe3: /* pavgw */
6942 case 0x0fe4: /* pmulhuw */
6943 case 0x0fe5: /* pmulhw */
6944 case 0x0fe8: /* psubsb */
6945 case 0x0fe9: /* psubsw */
6946 case 0x0fea: /* pminsw */
6947 case 0x0feb: /* por */
6948 case 0x0fec: /* paddsb */
6949 case 0x0fed: /* paddsw */
6950 case 0x0fee: /* pmaxsw */
6951 case 0x0fef: /* pxor */
6952 case 0x0ff1: /* psllw */
6953 case 0x0ff2: /* pslld */
6954 case 0x0ff3: /* psllq */
6955 case 0x0ff4: /* pmuludq */
6956 case 0x0ff5: /* pmaddwd */
6957 case 0x0ff6: /* psadbw */
6958 case 0x0ff8: /* psubb */
6959 case 0x0ff9: /* psubw */
6960 case 0x0ffa: /* psubd */
6961 case 0x0ffb: /* psubq */
6962 case 0x0ffc: /* paddb */
6963 case 0x0ffd: /* paddw */
6964 case 0x0ffe: /* paddd */
6965 if (i386_record_modrm (&ir))
6967 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
6969 record_arch_list_add_reg (ir.regcache,
6970 I387_MM0_REGNUM (tdep) + ir.reg);
6973 case 0x0f71: /* psllw */
6974 case 0x0f72: /* pslld */
6975 case 0x0f73: /* psllq */
6976 if (i386_record_modrm (&ir))
6978 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
6980 record_arch_list_add_reg (ir.regcache,
6981 I387_MM0_REGNUM (tdep) + ir.rm);
6984 case 0x660f71: /* psllw */
6985 case 0x660f72: /* pslld */
6986 case 0x660f73: /* psllq */
6987 if (i386_record_modrm (&ir))
6990 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
6992 record_arch_list_add_reg (ir.regcache,
6993 I387_XMM0_REGNUM (tdep) + ir.rm);
6996 case 0x0f7e: /* movd */
6997 case 0x660f7e: /* movd */
6998 if (i386_record_modrm (&ir))
7001 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7008 if (i386_record_lea_modrm (&ir))
7013 case 0x0f7f: /* movq */
7014 if (i386_record_modrm (&ir))
7018 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7020 record_arch_list_add_reg (ir.regcache,
7021 I387_MM0_REGNUM (tdep) + ir.rm);
7026 if (i386_record_lea_modrm (&ir))
7031 case 0xf30fb8: /* popcnt */
7032 if (i386_record_modrm (&ir))
7034 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
7035 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7038 case 0x660fd6: /* movq */
7039 if (i386_record_modrm (&ir))
7044 if (!i386_xmm_regnum_p (gdbarch,
7045 I387_XMM0_REGNUM (tdep) + ir.rm))
7047 record_arch_list_add_reg (ir.regcache,
7048 I387_XMM0_REGNUM (tdep) + ir.rm);
7053 if (i386_record_lea_modrm (&ir))
7058 case 0x660f3817: /* ptest */
7059 case 0x0f2e: /* ucomiss */
7060 case 0x660f2e: /* ucomisd */
7061 case 0x0f2f: /* comiss */
7062 case 0x660f2f: /* comisd */
7063 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7066 case 0x0ff7: /* maskmovq */
7067 regcache_raw_read_unsigned (ir.regcache,
7068 ir.regmap[X86_RECORD_REDI_REGNUM],
7070 if (record_arch_list_add_mem (addr, 64))
7074 case 0x660ff7: /* maskmovdqu */
7075 regcache_raw_read_unsigned (ir.regcache,
7076 ir.regmap[X86_RECORD_REDI_REGNUM],
7078 if (record_arch_list_add_mem (addr, 128))
7093 /* In the future, maybe still need to deal with need_dasm. */
7094 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
7095 if (record_arch_list_add_end ())
7101 printf_unfiltered (_("Process record does not support instruction 0x%02x "
7102 "at address %s.\n"),
7103 (unsigned int) (opcode),
7104 paddress (gdbarch, ir.orig_addr));
7108 static const int i386_record_regmap[] =
7110 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
7111 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
7112 0, 0, 0, 0, 0, 0, 0, 0,
7113 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
7114 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
7117 /* Check that the given address appears suitable for a fast
7118 tracepoint, which on x86-64 means that we need an instruction of at
7119 least 5 bytes, so that we can overwrite it with a 4-byte-offset
7120 jump and not have to worry about program jumps to an address in the
7121 middle of the tracepoint jump. On x86, it may be possible to use
7122 4-byte jumps with a 2-byte offset to a trampoline located in the
7123 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
7124 of instruction to replace, and 0 if not, plus an explanatory
7128 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch,
7129 CORE_ADDR addr, int *isize, char **msg)
7132 static struct ui_file *gdb_null = NULL;
7134 /* Ask the target for the minimum instruction length supported. */
7135 jumplen = target_get_min_fast_tracepoint_insn_len ();
7139 /* If the target does not support the get_min_fast_tracepoint_insn_len
7140 operation, assume that fast tracepoints will always be implemented
7141 using 4-byte relative jumps on both x86 and x86-64. */
7144 else if (jumplen == 0)
7146 /* If the target does support get_min_fast_tracepoint_insn_len but
7147 returns zero, then the IPA has not loaded yet. In this case,
7148 we optimistically assume that truncated 2-byte relative jumps
7149 will be available on x86, and compensate later if this assumption
7150 turns out to be incorrect. On x86-64 architectures, 4-byte relative
7151 jumps will always be used. */
7152 jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4;
7155 /* Dummy file descriptor for the disassembler. */
7157 gdb_null = ui_file_new ();
7159 /* Check for fit. */
7160 len = gdb_print_insn (gdbarch, addr, gdb_null, NULL);
7166 /* Return a bit of target-specific detail to add to the caller's
7167 generic failure message. */
7169 *msg = xstrprintf (_("; instruction is only %d bytes long, "
7170 "need at least %d bytes for the jump"),
7183 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
7184 struct tdesc_arch_data *tdesc_data)
7186 const struct target_desc *tdesc = tdep->tdesc;
7187 const struct tdesc_feature *feature_core;
7188 const struct tdesc_feature *feature_sse, *feature_avx;
7189 int i, num_regs, valid_p;
7191 if (! tdesc_has_registers (tdesc))
7194 /* Get core registers. */
7195 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
7196 if (feature_core == NULL)
7199 /* Get SSE registers. */
7200 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
7202 /* Try AVX registers. */
7203 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
7207 /* The XCR0 bits. */
7210 /* AVX register description requires SSE register description. */
7214 tdep->xcr0 = I386_XSTATE_AVX_MASK;
7216 /* It may have been set by OSABI initialization function. */
7217 if (tdep->num_ymm_regs == 0)
7219 tdep->ymmh_register_names = i386_ymmh_names;
7220 tdep->num_ymm_regs = 8;
7221 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
7224 for (i = 0; i < tdep->num_ymm_regs; i++)
7225 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
7226 tdep->ymm0h_regnum + i,
7227 tdep->ymmh_register_names[i]);
7229 else if (feature_sse)
7230 tdep->xcr0 = I386_XSTATE_SSE_MASK;
7233 tdep->xcr0 = I386_XSTATE_X87_MASK;
7234 tdep->num_xmm_regs = 0;
7237 num_regs = tdep->num_core_regs;
7238 for (i = 0; i < num_regs; i++)
7239 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
7240 tdep->register_names[i]);
7244 /* Need to include %mxcsr, so add one. */
7245 num_regs += tdep->num_xmm_regs + 1;
7246 for (; i < num_regs; i++)
7247 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
7248 tdep->register_names[i]);
7255 static struct gdbarch *
7256 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
7258 struct gdbarch_tdep *tdep;
7259 struct gdbarch *gdbarch;
7260 struct tdesc_arch_data *tdesc_data;
7261 const struct target_desc *tdesc;
7265 /* If there is already a candidate, use it. */
7266 arches = gdbarch_list_lookup_by_info (arches, &info);
7268 return arches->gdbarch;
7270 /* Allocate space for the new architecture. */
7271 tdep = XCALLOC (1, struct gdbarch_tdep);
7272 gdbarch = gdbarch_alloc (&info, tdep);
7274 /* General-purpose registers. */
7275 tdep->gregset = NULL;
7276 tdep->gregset_reg_offset = NULL;
7277 tdep->gregset_num_regs = I386_NUM_GREGS;
7278 tdep->sizeof_gregset = 0;
7280 /* Floating-point registers. */
7281 tdep->fpregset = NULL;
7282 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
7284 tdep->xstateregset = NULL;
7286 /* The default settings include the FPU registers, the MMX registers
7287 and the SSE registers. This can be overridden for a specific ABI
7288 by adjusting the members `st0_regnum', `mm0_regnum' and
7289 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
7290 will show up in the output of "info all-registers". */
7292 tdep->st0_regnum = I386_ST0_REGNUM;
7294 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
7295 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
7297 tdep->jb_pc_offset = -1;
7298 tdep->struct_return = pcc_struct_return;
7299 tdep->sigtramp_start = 0;
7300 tdep->sigtramp_end = 0;
7301 tdep->sigtramp_p = i386_sigtramp_p;
7302 tdep->sigcontext_addr = NULL;
7303 tdep->sc_reg_offset = NULL;
7304 tdep->sc_pc_offset = -1;
7305 tdep->sc_sp_offset = -1;
7307 tdep->xsave_xcr0_offset = -1;
7309 tdep->record_regmap = i386_record_regmap;
7311 set_gdbarch_long_long_align_bit (gdbarch, 32);
7313 /* The format used for `long double' on almost all i386 targets is
7314 the i387 extended floating-point format. In fact, of all targets
7315 in the GCC 2.95 tree, only OSF/1 does it different, and insists
7316 on having a `long double' that's not `long' at all. */
7317 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
7319 /* Although the i387 extended floating-point has only 80 significant
7320 bits, a `long double' actually takes up 96, probably to enforce
7322 set_gdbarch_long_double_bit (gdbarch, 96);
7324 /* Register numbers of various important registers. */
7325 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
7326 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
7327 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
7328 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
7330 /* NOTE: kettenis/20040418: GCC does have two possible register
7331 numbering schemes on the i386: dbx and SVR4. These schemes
7332 differ in how they number %ebp, %esp, %eflags, and the
7333 floating-point registers, and are implemented by the arrays
7334 dbx_register_map[] and svr4_dbx_register_map in
7335 gcc/config/i386.c. GCC also defines a third numbering scheme in
7336 gcc/config/i386.c, which it designates as the "default" register
7337 map used in 64bit mode. This last register numbering scheme is
7338 implemented in dbx64_register_map, and is used for AMD64; see
7341 Currently, each GCC i386 target always uses the same register
7342 numbering scheme across all its supported debugging formats
7343 i.e. SDB (COFF), stabs and DWARF 2. This is because
7344 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7345 DBX_REGISTER_NUMBER macro which is defined by each target's
7346 respective config header in a manner independent of the requested
7347 output debugging format.
7349 This does not match the arrangement below, which presumes that
7350 the SDB and stabs numbering schemes differ from the DWARF and
7351 DWARF 2 ones. The reason for this arrangement is that it is
7352 likely to get the numbering scheme for the target's
7353 default/native debug format right. For targets where GCC is the
7354 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7355 targets where the native toolchain uses a different numbering
7356 scheme for a particular debug format (stabs-in-ELF on Solaris)
7357 the defaults below will have to be overridden, like
7358 i386_elf_init_abi() does. */
7360 /* Use the dbx register numbering scheme for stabs and COFF. */
7361 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
7362 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
7364 /* Use the SVR4 register numbering scheme for DWARF 2. */
7365 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
7367 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7368 be in use on any of the supported i386 targets. */
7370 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
7372 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
7374 /* Call dummy code. */
7375 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
7376 set_gdbarch_frame_align (gdbarch, i386_frame_align);
7378 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
7379 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
7380 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
7382 set_gdbarch_return_value (gdbarch, i386_return_value);
7384 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
7386 /* Stack grows downward. */
7387 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
7389 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc);
7390 set_gdbarch_decr_pc_after_break (gdbarch, 1);
7391 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
7393 set_gdbarch_frame_args_skip (gdbarch, 8);
7395 set_gdbarch_print_insn (gdbarch, i386_print_insn);
7397 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
7399 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
7401 /* Add the i386 register groups. */
7402 i386_add_reggroups (gdbarch);
7403 tdep->register_reggroup_p = i386_register_reggroup_p;
7405 /* Helper for function argument information. */
7406 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
7408 /* Hook the function epilogue frame unwinder. This unwinder is
7409 appended to the list first, so that it supercedes the DWARF
7410 unwinder in function epilogues (where the DWARF unwinder
7411 currently fails). */
7412 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
7414 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7415 to the list before the prologue-based unwinders, so that DWARF
7416 CFI info will be used if it is available. */
7417 dwarf2_append_unwinders (gdbarch);
7419 frame_base_set_default (gdbarch, &i386_frame_base);
7421 /* Pseudo registers may be changed by amd64_init_abi. */
7422 set_gdbarch_pseudo_register_read_value (gdbarch,
7423 i386_pseudo_register_read_value);
7424 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
7426 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
7427 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
7429 /* Override the normal target description method to make the AVX
7430 upper halves anonymous. */
7431 set_gdbarch_register_name (gdbarch, i386_register_name);
7433 /* Even though the default ABI only includes general-purpose registers,
7434 floating-point registers and the SSE registers, we have to leave a
7435 gap for the upper AVX registers. */
7436 set_gdbarch_num_regs (gdbarch, I386_AVX_NUM_REGS);
7438 /* Get the x86 target description from INFO. */
7439 tdesc = info.target_desc;
7440 if (! tdesc_has_registers (tdesc))
7442 tdep->tdesc = tdesc;
7444 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
7445 tdep->register_names = i386_register_names;
7447 /* No upper YMM registers. */
7448 tdep->ymmh_register_names = NULL;
7449 tdep->ymm0h_regnum = -1;
7451 tdep->num_byte_regs = 8;
7452 tdep->num_word_regs = 8;
7453 tdep->num_dword_regs = 0;
7454 tdep->num_mmx_regs = 8;
7455 tdep->num_ymm_regs = 0;
7457 tdesc_data = tdesc_data_alloc ();
7459 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
7461 set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address);
7463 /* Hook in ABI-specific overrides, if they have been registered. */
7464 info.tdep_info = (void *) tdesc_data;
7465 gdbarch_init_osabi (info, gdbarch);
7467 if (!i386_validate_tdesc_p (tdep, tdesc_data))
7469 tdesc_data_cleanup (tdesc_data);
7471 gdbarch_free (gdbarch);
7475 /* Wire in pseudo registers. Number of pseudo registers may be
7477 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
7478 + tdep->num_word_regs
7479 + tdep->num_dword_regs
7480 + tdep->num_mmx_regs
7481 + tdep->num_ymm_regs));
7483 /* Target description may be changed. */
7484 tdesc = tdep->tdesc;
7486 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
7488 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7489 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
7491 /* Make %al the first pseudo-register. */
7492 tdep->al_regnum = gdbarch_num_regs (gdbarch);
7493 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
7495 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
7496 if (tdep->num_dword_regs)
7498 /* Support dword pseudo-register if it hasn't been disabled. */
7499 tdep->eax_regnum = ymm0_regnum;
7500 ymm0_regnum += tdep->num_dword_regs;
7503 tdep->eax_regnum = -1;
7505 mm0_regnum = ymm0_regnum;
7506 if (tdep->num_ymm_regs)
7508 /* Support YMM pseudo-register if it is available. */
7509 tdep->ymm0_regnum = ymm0_regnum;
7510 mm0_regnum += tdep->num_ymm_regs;
7513 tdep->ymm0_regnum = -1;
7515 if (tdep->num_mmx_regs != 0)
7517 /* Support MMX pseudo-register if MMX hasn't been disabled. */
7518 tdep->mm0_regnum = mm0_regnum;
7521 tdep->mm0_regnum = -1;
7523 /* Hook in the legacy prologue-based unwinders last (fallback). */
7524 frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind);
7525 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
7526 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
7528 /* If we have a register mapping, enable the generic core file
7529 support, unless it has already been enabled. */
7530 if (tdep->gregset_reg_offset
7531 && !gdbarch_regset_from_core_section_p (gdbarch))
7532 set_gdbarch_regset_from_core_section (gdbarch,
7533 i386_regset_from_core_section);
7535 set_gdbarch_skip_permanent_breakpoint (gdbarch,
7536 i386_skip_permanent_breakpoint);
7538 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
7539 i386_fast_tracepoint_valid_at);
7544 static enum gdb_osabi
7545 i386_coff_osabi_sniffer (bfd *abfd)
7547 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
7548 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
7549 return GDB_OSABI_GO32;
7551 return GDB_OSABI_UNKNOWN;
7555 /* Provide a prototype to silence -Wmissing-prototypes. */
7556 void _initialize_i386_tdep (void);
7559 _initialize_i386_tdep (void)
7561 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
7563 /* Add the variable that controls the disassembly flavor. */
7564 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
7565 &disassembly_flavor, _("\
7566 Set the disassembly flavor."), _("\
7567 Show the disassembly flavor."), _("\
7568 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7570 NULL, /* FIXME: i18n: */
7571 &setlist, &showlist);
7573 /* Add the variable that controls the convention for returning
7575 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
7576 &struct_convention, _("\
7577 Set the convention for returning small structs."), _("\
7578 Show the convention for returning small structs."), _("\
7579 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7582 NULL, /* FIXME: i18n: */
7583 &setlist, &showlist);
7585 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
7586 i386_coff_osabi_sniffer);
7588 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
7589 i386_svr4_init_abi);
7590 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
7591 i386_go32_init_abi);
7593 /* Initialize the i386-specific register groups. */
7594 i386_init_reggroups ();
7596 /* Initialize the standard target descriptions. */
7597 initialize_tdesc_i386 ();
7598 initialize_tdesc_i386_mmx ();
7599 initialize_tdesc_i386_avx ();
7601 /* Tell remote stub that we support XML target description. */
7602 register_remote_support_xml ("i386");