1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
47 #include "gdb_assert.h"
48 #include "gdb_string.h"
50 #include "i386-tdep.h"
51 #include "i387-tdep.h"
58 static char *i386_register_names[] =
60 "eax", "ecx", "edx", "ebx",
61 "esp", "ebp", "esi", "edi",
62 "eip", "eflags", "cs", "ss",
63 "ds", "es", "fs", "gs",
64 "st0", "st1", "st2", "st3",
65 "st4", "st5", "st6", "st7",
66 "fctrl", "fstat", "ftag", "fiseg",
67 "fioff", "foseg", "fooff", "fop",
68 "xmm0", "xmm1", "xmm2", "xmm3",
69 "xmm4", "xmm5", "xmm6", "xmm7",
73 static const int i386_num_register_names = ARRAY_SIZE (i386_register_names);
75 /* Register names for MMX pseudo-registers. */
77 static char *i386_mmx_names[] =
79 "mm0", "mm1", "mm2", "mm3",
80 "mm4", "mm5", "mm6", "mm7"
83 static const int i386_num_mmx_regs = ARRAY_SIZE (i386_mmx_names);
86 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
88 int mm0_regnum = gdbarch_tdep (gdbarch)->mm0_regnum;
93 return (regnum >= mm0_regnum && regnum < mm0_regnum + i386_num_mmx_regs);
99 i386_sse_regnum_p (struct gdbarch *gdbarch, int regnum)
101 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
103 if (I387_NUM_XMM_REGS (tdep) == 0)
106 return (I387_XMM0_REGNUM (tdep) <= regnum
107 && regnum < I387_MXCSR_REGNUM (tdep));
111 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
113 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
115 if (I387_NUM_XMM_REGS (tdep) == 0)
118 return (regnum == I387_MXCSR_REGNUM (tdep));
124 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
126 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
128 if (I387_ST0_REGNUM (tdep) < 0)
131 return (I387_ST0_REGNUM (tdep) <= regnum
132 && regnum < I387_FCTRL_REGNUM (tdep));
136 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
138 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
140 if (I387_ST0_REGNUM (tdep) < 0)
143 return (I387_FCTRL_REGNUM (tdep) <= regnum
144 && regnum < I387_XMM0_REGNUM (tdep));
147 /* Return the name of register REGNUM. */
150 i386_register_name (struct gdbarch *gdbarch, int regnum)
152 if (i386_mmx_regnum_p (gdbarch, regnum))
153 return i386_mmx_names[regnum - I387_MM0_REGNUM (gdbarch_tdep (gdbarch))];
155 if (regnum >= 0 && regnum < i386_num_register_names)
156 return i386_register_names[regnum];
161 /* Convert a dbx register number REG to the appropriate register
162 number used by GDB. */
165 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
167 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
169 /* This implements what GCC calls the "default" register map
170 (dbx_register_map[]). */
172 if (reg >= 0 && reg <= 7)
174 /* General-purpose registers. The debug info calls %ebp
175 register 4, and %esp register 5. */
182 else if (reg >= 12 && reg <= 19)
184 /* Floating-point registers. */
185 return reg - 12 + I387_ST0_REGNUM (tdep);
187 else if (reg >= 21 && reg <= 28)
190 return reg - 21 + I387_XMM0_REGNUM (tdep);
192 else if (reg >= 29 && reg <= 36)
195 return reg - 29 + I387_MM0_REGNUM (tdep);
198 /* This will hopefully provoke a warning. */
199 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
202 /* Convert SVR4 register number REG to the appropriate register number
206 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
208 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
210 /* This implements the GCC register map that tries to be compatible
211 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
213 /* The SVR4 register numbering includes %eip and %eflags, and
214 numbers the floating point registers differently. */
215 if (reg >= 0 && reg <= 9)
217 /* General-purpose registers. */
220 else if (reg >= 11 && reg <= 18)
222 /* Floating-point registers. */
223 return reg - 11 + I387_ST0_REGNUM (tdep);
225 else if (reg >= 21 && reg <= 36)
227 /* The SSE and MMX registers have the same numbers as with dbx. */
228 return i386_dbx_reg_to_regnum (gdbarch, reg);
233 case 37: return I387_FCTRL_REGNUM (tdep);
234 case 38: return I387_FSTAT_REGNUM (tdep);
235 case 39: return I387_MXCSR_REGNUM (tdep);
236 case 40: return I386_ES_REGNUM;
237 case 41: return I386_CS_REGNUM;
238 case 42: return I386_SS_REGNUM;
239 case 43: return I386_DS_REGNUM;
240 case 44: return I386_FS_REGNUM;
241 case 45: return I386_GS_REGNUM;
244 /* This will hopefully provoke a warning. */
245 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
250 /* This is the variable that is set with "set disassembly-flavor", and
251 its legitimate values. */
252 static const char att_flavor[] = "att";
253 static const char intel_flavor[] = "intel";
254 static const char *valid_flavors[] =
260 static const char *disassembly_flavor = att_flavor;
263 /* Use the program counter to determine the contents and size of a
264 breakpoint instruction. Return a pointer to a string of bytes that
265 encode a breakpoint instruction, store the length of the string in
266 *LEN and optionally adjust *PC to point to the correct memory
267 location for inserting the breakpoint.
269 On the i386 we have a single breakpoint that fits in a single byte
270 and can be inserted anywhere.
272 This function is 64-bit safe. */
274 static const gdb_byte *
275 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
277 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */
279 *len = sizeof (break_insn);
283 /* Displaced instruction handling. */
285 /* Skip the legacy instruction prefixes in INSN.
286 Not all prefixes are valid for any particular insn
287 but we needn't care, the insn will fault if it's invalid.
288 The result is a pointer to the first opcode byte,
289 or NULL if we run off the end of the buffer. */
292 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
294 gdb_byte *end = insn + max_len;
300 case DATA_PREFIX_OPCODE:
301 case ADDR_PREFIX_OPCODE:
302 case CS_PREFIX_OPCODE:
303 case DS_PREFIX_OPCODE:
304 case ES_PREFIX_OPCODE:
305 case FS_PREFIX_OPCODE:
306 case GS_PREFIX_OPCODE:
307 case SS_PREFIX_OPCODE:
308 case LOCK_PREFIX_OPCODE:
309 case REPE_PREFIX_OPCODE:
310 case REPNE_PREFIX_OPCODE:
322 i386_absolute_jmp_p (const gdb_byte *insn)
324 /* jmp far (absolute address in operand) */
330 /* jump near, absolute indirect (/4) */
331 if ((insn[1] & 0x38) == 0x20)
334 /* jump far, absolute indirect (/5) */
335 if ((insn[1] & 0x38) == 0x28)
343 i386_absolute_call_p (const gdb_byte *insn)
345 /* call far, absolute */
351 /* Call near, absolute indirect (/2) */
352 if ((insn[1] & 0x38) == 0x10)
355 /* Call far, absolute indirect (/3) */
356 if ((insn[1] & 0x38) == 0x18)
364 i386_ret_p (const gdb_byte *insn)
368 case 0xc2: /* ret near, pop N bytes */
369 case 0xc3: /* ret near */
370 case 0xca: /* ret far, pop N bytes */
371 case 0xcb: /* ret far */
372 case 0xcf: /* iret */
381 i386_call_p (const gdb_byte *insn)
383 if (i386_absolute_call_p (insn))
386 /* call near, relative */
393 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
394 length in bytes. Otherwise, return zero. */
397 i386_syscall_p (const gdb_byte *insn, ULONGEST *lengthp)
408 /* Fix up the state of registers and memory after having single-stepped
409 a displaced instruction. */
412 i386_displaced_step_fixup (struct gdbarch *gdbarch,
413 struct displaced_step_closure *closure,
414 CORE_ADDR from, CORE_ADDR to,
415 struct regcache *regs)
417 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
419 /* The offset we applied to the instruction's address.
420 This could well be negative (when viewed as a signed 32-bit
421 value), but ULONGEST won't reflect that, so take care when
423 ULONGEST insn_offset = to - from;
425 /* Since we use simple_displaced_step_copy_insn, our closure is a
426 copy of the instruction. */
427 gdb_byte *insn = (gdb_byte *) closure;
428 /* The start of the insn, needed in case we see some prefixes. */
429 gdb_byte *insn_start = insn;
432 fprintf_unfiltered (gdb_stdlog,
433 "displaced: fixup (%s, %s), "
434 "insn = 0x%02x 0x%02x ...\n",
435 paddress (gdbarch, from), paddress (gdbarch, to),
438 /* The list of issues to contend with here is taken from
439 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
440 Yay for Free Software! */
442 /* Relocate the %eip, if necessary. */
444 /* The instruction recognizers we use assume any leading prefixes
445 have been skipped. */
447 /* This is the size of the buffer in closure. */
448 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
449 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
450 /* If there are too many prefixes, just ignore the insn.
451 It will fault when run. */
456 /* Except in the case of absolute or indirect jump or call
457 instructions, or a return instruction, the new eip is relative to
458 the displaced instruction; make it relative. Well, signal
459 handler returns don't need relocation either, but we use the
460 value of %eip to recognize those; see below. */
461 if (! i386_absolute_jmp_p (insn)
462 && ! i386_absolute_call_p (insn)
463 && ! i386_ret_p (insn))
468 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
470 /* A signal trampoline system call changes the %eip, resuming
471 execution of the main program after the signal handler has
472 returned. That makes them like 'return' instructions; we
473 shouldn't relocate %eip.
475 But most system calls don't, and we do need to relocate %eip.
477 Our heuristic for distinguishing these cases: if stepping
478 over the system call instruction left control directly after
479 the instruction, the we relocate --- control almost certainly
480 doesn't belong in the displaced copy. Otherwise, we assume
481 the instruction has put control where it belongs, and leave
482 it unrelocated. Goodness help us if there are PC-relative
484 if (i386_syscall_p (insn, &insn_len)
485 && orig_eip != to + (insn - insn_start) + insn_len)
488 fprintf_unfiltered (gdb_stdlog,
489 "displaced: syscall changed %%eip; "
494 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
496 /* If we just stepped over a breakpoint insn, we don't backup
497 the pc on purpose; this is to match behaviour without
500 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
503 fprintf_unfiltered (gdb_stdlog,
505 "relocated %%eip from %s to %s\n",
506 paddress (gdbarch, orig_eip),
507 paddress (gdbarch, eip));
511 /* If the instruction was PUSHFL, then the TF bit will be set in the
512 pushed value, and should be cleared. We'll leave this for later,
513 since GDB already messes up the TF flag when stepping over a
516 /* If the instruction was a call, the return address now atop the
517 stack is the address following the copied instruction. We need
518 to make it the address following the original instruction. */
519 if (i386_call_p (insn))
523 const ULONGEST retaddr_len = 4;
525 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
526 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
527 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
528 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
531 fprintf_unfiltered (gdb_stdlog,
532 "displaced: relocated return addr at %s to %s\n",
533 paddress (gdbarch, esp),
534 paddress (gdbarch, retaddr));
538 #ifdef I386_REGNO_TO_SYMMETRY
539 #error "The Sequent Symmetry is no longer supported."
542 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
543 and %esp "belong" to the calling function. Therefore these
544 registers should be saved if they're going to be modified. */
546 /* The maximum number of saved registers. This should include all
547 registers mentioned above, and %eip. */
548 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
550 struct i386_frame_cache
557 /* Saved registers. */
558 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
563 /* Stack space reserved for local variables. */
567 /* Allocate and initialize a frame cache. */
569 static struct i386_frame_cache *
570 i386_alloc_frame_cache (void)
572 struct i386_frame_cache *cache;
575 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
579 cache->sp_offset = -4;
582 /* Saved registers. We initialize these to -1 since zero is a valid
583 offset (that's where %ebp is supposed to be stored). */
584 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
585 cache->saved_regs[i] = -1;
587 cache->saved_sp_reg = -1;
588 cache->pc_in_eax = 0;
590 /* Frameless until proven otherwise. */
596 /* If the instruction at PC is a jump, return the address of its
597 target. Otherwise, return PC. */
600 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
602 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
607 target_read_memory (pc, &op, 1);
611 op = read_memory_unsigned_integer (pc + 1, 1, byte_order);
617 /* Relative jump: if data16 == 0, disp32, else disp16. */
620 delta = read_memory_integer (pc + 2, 2, byte_order);
622 /* Include the size of the jmp instruction (including the
628 delta = read_memory_integer (pc + 1, 4, byte_order);
630 /* Include the size of the jmp instruction. */
635 /* Relative jump, disp8 (ignore data16). */
636 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
645 /* Check whether PC points at a prologue for a function returning a
646 structure or union. If so, it updates CACHE and returns the
647 address of the first instruction after the code sequence that
648 removes the "hidden" argument from the stack or CURRENT_PC,
649 whichever is smaller. Otherwise, return PC. */
652 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
653 struct i386_frame_cache *cache)
655 /* Functions that return a structure or union start with:
658 xchgl %eax, (%esp) 0x87 0x04 0x24
659 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
661 (the System V compiler puts out the second `xchg' instruction,
662 and the assembler doesn't try to optimize it, so the 'sib' form
663 gets generated). This sequence is used to get the address of the
664 return buffer for a function that returns a structure. */
665 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
666 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
670 if (current_pc <= pc)
673 target_read_memory (pc, &op, 1);
675 if (op != 0x58) /* popl %eax */
678 target_read_memory (pc + 1, buf, 4);
679 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
682 if (current_pc == pc)
684 cache->sp_offset += 4;
688 if (current_pc == pc + 1)
690 cache->pc_in_eax = 1;
694 if (buf[1] == proto1[1])
701 i386_skip_probe (CORE_ADDR pc)
703 /* A function may start with
717 target_read_memory (pc, &op, 1);
719 if (op == 0x68 || op == 0x6a)
723 /* Skip past the `pushl' instruction; it has either a one-byte or a
724 four-byte operand, depending on the opcode. */
730 /* Read the following 8 bytes, which should be `call _probe' (6
731 bytes) followed by `addl $4,%esp' (2 bytes). */
732 read_memory (pc + delta, buf, sizeof (buf));
733 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
734 pc += delta + sizeof (buf);
740 /* GCC 4.1 and later, can put code in the prologue to realign the
741 stack pointer. Check whether PC points to such code, and update
742 CACHE accordingly. Return the first instruction after the code
743 sequence or CURRENT_PC, whichever is smaller. If we don't
744 recognize the code, return PC. */
747 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
748 struct i386_frame_cache *cache)
750 /* There are 2 code sequences to re-align stack before the frame
753 1. Use a caller-saved saved register:
759 2. Use a callee-saved saved register:
766 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
768 0x83 0xe4 0xf0 andl $-16, %esp
769 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
774 int offset, offset_and;
775 static int regnums[8] = {
776 I386_EAX_REGNUM, /* %eax */
777 I386_ECX_REGNUM, /* %ecx */
778 I386_EDX_REGNUM, /* %edx */
779 I386_EBX_REGNUM, /* %ebx */
780 I386_ESP_REGNUM, /* %esp */
781 I386_EBP_REGNUM, /* %ebp */
782 I386_ESI_REGNUM, /* %esi */
783 I386_EDI_REGNUM /* %edi */
786 if (target_read_memory (pc, buf, sizeof buf))
789 /* Check caller-saved saved register. The first instruction has
790 to be "leal 4(%esp), %reg". */
791 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
793 /* MOD must be binary 10 and R/M must be binary 100. */
794 if ((buf[1] & 0xc7) != 0x44)
797 /* REG has register number. */
798 reg = (buf[1] >> 3) & 7;
803 /* Check callee-saved saved register. The first instruction
804 has to be "pushl %reg". */
805 if ((buf[0] & 0xf8) != 0x50)
811 /* The next instruction has to be "leal 8(%esp), %reg". */
812 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
815 /* MOD must be binary 10 and R/M must be binary 100. */
816 if ((buf[2] & 0xc7) != 0x44)
819 /* REG has register number. Registers in pushl and leal have to
821 if (reg != ((buf[2] >> 3) & 7))
827 /* Rigister can't be %esp nor %ebp. */
828 if (reg == 4 || reg == 5)
831 /* The next instruction has to be "andl $-XXX, %esp". */
832 if (buf[offset + 1] != 0xe4
833 || (buf[offset] != 0x81 && buf[offset] != 0x83))
837 offset += buf[offset] == 0x81 ? 6 : 3;
839 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
840 0xfc. REG must be binary 110 and MOD must be binary 01. */
841 if (buf[offset] != 0xff
842 || buf[offset + 2] != 0xfc
843 || (buf[offset + 1] & 0xf8) != 0x70)
846 /* R/M has register. Registers in leal and pushl have to be the
848 if (reg != (buf[offset + 1] & 7))
851 if (current_pc > pc + offset_and)
852 cache->saved_sp_reg = regnums[reg];
854 return min (pc + offset + 3, current_pc);
857 /* Maximum instruction length we need to handle. */
858 #define I386_MAX_MATCHED_INSN_LEN 6
860 /* Instruction description. */
864 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
865 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
868 /* Search for the instruction at PC in the list SKIP_INSNS. Return
869 the first instruction description that matches. Otherwise, return
872 static struct i386_insn *
873 i386_match_insn (CORE_ADDR pc, struct i386_insn *skip_insns)
875 struct i386_insn *insn;
878 target_read_memory (pc, &op, 1);
880 for (insn = skip_insns; insn->len > 0; insn++)
882 if ((op & insn->mask[0]) == insn->insn[0])
884 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
885 int insn_matched = 1;
888 gdb_assert (insn->len > 1);
889 gdb_assert (insn->len <= I386_MAX_MATCHED_INSN_LEN);
891 target_read_memory (pc + 1, buf, insn->len - 1);
892 for (i = 1; i < insn->len; i++)
894 if ((buf[i - 1] & insn->mask[i]) != insn->insn[i])
906 /* Some special instructions that might be migrated by GCC into the
907 part of the prologue that sets up the new stack frame. Because the
908 stack frame hasn't been setup yet, no registers have been saved
909 yet, and only the scratch registers %eax, %ecx and %edx can be
912 struct i386_insn i386_frame_setup_skip_insns[] =
914 /* Check for `movb imm8, r' and `movl imm32, r'.
916 ??? Should we handle 16-bit operand-sizes here? */
918 /* `movb imm8, %al' and `movb imm8, %ah' */
919 /* `movb imm8, %cl' and `movb imm8, %ch' */
920 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
921 /* `movb imm8, %dl' and `movb imm8, %dh' */
922 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
923 /* `movl imm32, %eax' and `movl imm32, %ecx' */
924 { 5, { 0xb8 }, { 0xfe } },
925 /* `movl imm32, %edx' */
926 { 5, { 0xba }, { 0xff } },
928 /* Check for `mov imm32, r32'. Note that there is an alternative
929 encoding for `mov m32, %eax'.
931 ??? Should we handle SIB adressing here?
932 ??? Should we handle 16-bit operand-sizes here? */
934 /* `movl m32, %eax' */
935 { 5, { 0xa1 }, { 0xff } },
936 /* `movl m32, %eax' and `mov; m32, %ecx' */
937 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
938 /* `movl m32, %edx' */
939 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
941 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
942 Because of the symmetry, there are actually two ways to encode
943 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
944 opcode bytes 0x31 and 0x33 for `xorl'. */
946 /* `subl %eax, %eax' */
947 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
948 /* `subl %ecx, %ecx' */
949 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
950 /* `subl %edx, %edx' */
951 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
952 /* `xorl %eax, %eax' */
953 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
954 /* `xorl %ecx, %ecx' */
955 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
956 /* `xorl %edx, %edx' */
957 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
962 /* Check whether PC points to a no-op instruction. */
964 i386_skip_noop (CORE_ADDR pc)
969 target_read_memory (pc, &op, 1);
974 /* Ignore `nop' instruction. */
978 target_read_memory (pc, &op, 1);
981 /* Ignore no-op instruction `mov %edi, %edi'.
982 Microsoft system dlls often start with
983 a `mov %edi,%edi' instruction.
984 The 5 bytes before the function start are
985 filled with `nop' instructions.
986 This pattern can be used for hot-patching:
987 The `mov %edi, %edi' instruction can be replaced by a
988 near jump to the location of the 5 `nop' instructions
989 which can be replaced by a 32-bit jump to anywhere
990 in the 32-bit address space. */
994 target_read_memory (pc + 1, &op, 1);
998 target_read_memory (pc, &op, 1);
1006 /* Check whether PC points at a code that sets up a new stack frame.
1007 If so, it updates CACHE and returns the address of the first
1008 instruction after the sequence that sets up the frame or LIMIT,
1009 whichever is smaller. If we don't recognize the code, return PC. */
1012 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1013 CORE_ADDR pc, CORE_ADDR limit,
1014 struct i386_frame_cache *cache)
1016 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1017 struct i386_insn *insn;
1024 target_read_memory (pc, &op, 1);
1026 if (op == 0x55) /* pushl %ebp */
1028 /* Take into account that we've executed the `pushl %ebp' that
1029 starts this instruction sequence. */
1030 cache->saved_regs[I386_EBP_REGNUM] = 0;
1031 cache->sp_offset += 4;
1034 /* If that's all, return now. */
1038 /* Check for some special instructions that might be migrated by
1039 GCC into the prologue and skip them. At this point in the
1040 prologue, code should only touch the scratch registers %eax,
1041 %ecx and %edx, so while the number of posibilities is sheer,
1044 Make sure we only skip these instructions if we later see the
1045 `movl %esp, %ebp' that actually sets up the frame. */
1046 while (pc + skip < limit)
1048 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1055 /* If that's all, return now. */
1056 if (limit <= pc + skip)
1059 target_read_memory (pc + skip, &op, 1);
1061 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1065 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1070 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1078 /* OK, we actually have a frame. We just don't know how large
1079 it is yet. Set its size to zero. We'll adjust it if
1080 necessary. We also now commit to skipping the special
1081 instructions mentioned before. */
1085 /* If that's all, return now. */
1089 /* Check for stack adjustment
1093 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1094 reg, so we don't have to worry about a data16 prefix. */
1095 target_read_memory (pc, &op, 1);
1098 /* `subl' with 8-bit immediate. */
1099 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1100 /* Some instruction starting with 0x83 other than `subl'. */
1103 /* `subl' with signed 8-bit immediate (though it wouldn't
1104 make sense to be negative). */
1105 cache->locals = read_memory_integer (pc + 2, 1, byte_order);
1108 else if (op == 0x81)
1110 /* Maybe it is `subl' with a 32-bit immediate. */
1111 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1112 /* Some instruction starting with 0x81 other than `subl'. */
1115 /* It is `subl' with a 32-bit immediate. */
1116 cache->locals = read_memory_integer (pc + 2, 4, byte_order);
1121 /* Some instruction other than `subl'. */
1125 else if (op == 0xc8) /* enter */
1127 cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order);
1134 /* Check whether PC points at code that saves registers on the stack.
1135 If so, it updates CACHE and returns the address of the first
1136 instruction after the register saves or CURRENT_PC, whichever is
1137 smaller. Otherwise, return PC. */
1140 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1141 struct i386_frame_cache *cache)
1143 CORE_ADDR offset = 0;
1147 if (cache->locals > 0)
1148 offset -= cache->locals;
1149 for (i = 0; i < 8 && pc < current_pc; i++)
1151 target_read_memory (pc, &op, 1);
1152 if (op < 0x50 || op > 0x57)
1156 cache->saved_regs[op - 0x50] = offset;
1157 cache->sp_offset += 4;
1164 /* Do a full analysis of the prologue at PC and update CACHE
1165 accordingly. Bail out early if CURRENT_PC is reached. Return the
1166 address where the analysis stopped.
1168 We handle these cases:
1170 The startup sequence can be at the start of the function, or the
1171 function can start with a branch to startup code at the end.
1173 %ebp can be set up with either the 'enter' instruction, or "pushl
1174 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1175 once used in the System V compiler).
1177 Local space is allocated just below the saved %ebp by either the
1178 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1179 16-bit unsigned argument for space to allocate, and the 'addl'
1180 instruction could have either a signed byte, or 32-bit immediate.
1182 Next, the registers used by this function are pushed. With the
1183 System V compiler they will always be in the order: %edi, %esi,
1184 %ebx (and sometimes a harmless bug causes it to also save but not
1185 restore %eax); however, the code below is willing to see the pushes
1186 in any order, and will handle up to 8 of them.
1188 If the setup sequence is at the end of the function, then the next
1189 instruction will be a branch back to the start. */
1192 i386_analyze_prologue (struct gdbarch *gdbarch,
1193 CORE_ADDR pc, CORE_ADDR current_pc,
1194 struct i386_frame_cache *cache)
1196 pc = i386_skip_noop (pc);
1197 pc = i386_follow_jump (gdbarch, pc);
1198 pc = i386_analyze_struct_return (pc, current_pc, cache);
1199 pc = i386_skip_probe (pc);
1200 pc = i386_analyze_stack_align (pc, current_pc, cache);
1201 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1202 return i386_analyze_register_saves (pc, current_pc, cache);
1205 /* Return PC of first real instruction. */
1208 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1210 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1212 static gdb_byte pic_pat[6] =
1214 0xe8, 0, 0, 0, 0, /* call 0x0 */
1215 0x5b, /* popl %ebx */
1217 struct i386_frame_cache cache;
1223 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1224 if (cache.locals < 0)
1227 /* Found valid frame setup. */
1229 /* The native cc on SVR4 in -K PIC mode inserts the following code
1230 to get the address of the global offset table (GOT) into register
1235 movl %ebx,x(%ebp) (optional)
1238 This code is with the rest of the prologue (at the end of the
1239 function), so we have to skip it to get to the first real
1240 instruction at the start of the function. */
1242 for (i = 0; i < 6; i++)
1244 target_read_memory (pc + i, &op, 1);
1245 if (pic_pat[i] != op)
1252 target_read_memory (pc + delta, &op, 1);
1254 if (op == 0x89) /* movl %ebx, x(%ebp) */
1256 op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order);
1258 if (op == 0x5d) /* One byte offset from %ebp. */
1260 else if (op == 0x9d) /* Four byte offset from %ebp. */
1262 else /* Unexpected instruction. */
1265 target_read_memory (pc + delta, &op, 1);
1269 if (delta > 0 && op == 0x81
1270 && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order)
1277 /* If the function starts with a branch (to startup code at the end)
1278 the last instruction should bring us back to the first
1279 instruction of the real code. */
1280 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1281 pc = i386_follow_jump (gdbarch, pc);
1286 /* Check that the code pointed to by PC corresponds to a call to
1287 __main, skip it if so. Return PC otherwise. */
1290 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1292 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1295 target_read_memory (pc, &op, 1);
1300 if (target_read_memory (pc + 1, buf, sizeof buf) == 0)
1302 /* Make sure address is computed correctly as a 32bit
1303 integer even if CORE_ADDR is 64 bit wide. */
1304 struct minimal_symbol *s;
1305 CORE_ADDR call_dest;
1307 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1308 call_dest = call_dest & 0xffffffffU;
1309 s = lookup_minimal_symbol_by_pc (call_dest);
1311 && SYMBOL_LINKAGE_NAME (s) != NULL
1312 && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0)
1320 /* This function is 64-bit safe. */
1323 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1327 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1328 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1332 /* Normal frames. */
1334 static struct i386_frame_cache *
1335 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
1337 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1338 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1339 struct i386_frame_cache *cache;
1346 cache = i386_alloc_frame_cache ();
1347 *this_cache = cache;
1349 /* In principle, for normal frames, %ebp holds the frame pointer,
1350 which holds the base address for the current stack frame.
1351 However, for functions that don't need it, the frame pointer is
1352 optional. For these "frameless" functions the frame pointer is
1353 actually the frame pointer of the calling frame. Signal
1354 trampolines are just a special case of a "frameless" function.
1355 They (usually) share their frame pointer with the frame that was
1356 in progress when the signal occurred. */
1358 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1359 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1360 if (cache->base == 0)
1363 /* For normal frames, %eip is stored at 4(%ebp). */
1364 cache->saved_regs[I386_EIP_REGNUM] = 4;
1366 cache->pc = get_frame_func (this_frame);
1368 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
1371 if (cache->saved_sp_reg != -1)
1373 /* Saved stack pointer has been saved. */
1374 get_frame_register (this_frame, cache->saved_sp_reg, buf);
1375 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
1378 if (cache->locals < 0)
1380 /* We didn't find a valid frame, which means that CACHE->base
1381 currently holds the frame pointer for our calling frame. If
1382 we're at the start of a function, or somewhere half-way its
1383 prologue, the function's frame probably hasn't been fully
1384 setup yet. Try to reconstruct the base address for the stack
1385 frame by looking at the stack pointer. For truly "frameless"
1386 functions this might work too. */
1388 if (cache->saved_sp_reg != -1)
1390 /* We're halfway aligning the stack. */
1391 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
1392 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
1394 /* This will be added back below. */
1395 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
1399 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1400 cache->base = extract_unsigned_integer (buf, 4, byte_order)
1405 /* Now that we have the base address for the stack frame we can
1406 calculate the value of %esp in the calling frame. */
1407 if (cache->saved_sp == 0)
1408 cache->saved_sp = cache->base + 8;
1410 /* Adjust all the saved registers such that they contain addresses
1411 instead of offsets. */
1412 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1413 if (cache->saved_regs[i] != -1)
1414 cache->saved_regs[i] += cache->base;
1420 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
1421 struct frame_id *this_id)
1423 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1425 /* This marks the outermost frame. */
1426 if (cache->base == 0)
1429 /* See the end of i386_push_dummy_call. */
1430 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
1433 static struct value *
1434 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
1437 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1439 gdb_assert (regnum >= 0);
1441 /* The System V ABI says that:
1443 "The flags register contains the system flags, such as the
1444 direction flag and the carry flag. The direction flag must be
1445 set to the forward (that is, zero) direction before entry and
1446 upon exit from a function. Other user flags have no specified
1447 role in the standard calling sequence and are not preserved."
1449 To guarantee the "upon exit" part of that statement we fake a
1450 saved flags register that has its direction flag cleared.
1452 Note that GCC doesn't seem to rely on the fact that the direction
1453 flag is cleared after a function return; it always explicitly
1454 clears the flag before operations where it matters.
1456 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1457 right thing to do. The way we fake the flags register here makes
1458 it impossible to change it. */
1460 if (regnum == I386_EFLAGS_REGNUM)
1464 val = get_frame_register_unsigned (this_frame, regnum);
1466 return frame_unwind_got_constant (this_frame, regnum, val);
1469 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
1470 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
1472 if (regnum == I386_ESP_REGNUM && cache->saved_sp)
1473 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
1475 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
1476 return frame_unwind_got_memory (this_frame, regnum,
1477 cache->saved_regs[regnum]);
1479 return frame_unwind_got_register (this_frame, regnum, regnum);
1482 static const struct frame_unwind i386_frame_unwind =
1486 i386_frame_prev_register,
1488 default_frame_sniffer
1492 /* Signal trampolines. */
1494 static struct i386_frame_cache *
1495 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
1497 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1498 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1499 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1500 struct i386_frame_cache *cache;
1507 cache = i386_alloc_frame_cache ();
1509 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1510 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
1512 addr = tdep->sigcontext_addr (this_frame);
1513 if (tdep->sc_reg_offset)
1517 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
1519 for (i = 0; i < tdep->sc_num_regs; i++)
1520 if (tdep->sc_reg_offset[i] != -1)
1521 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
1525 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
1526 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
1529 *this_cache = cache;
1534 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
1535 struct frame_id *this_id)
1537 struct i386_frame_cache *cache =
1538 i386_sigtramp_frame_cache (this_frame, this_cache);
1540 /* See the end of i386_push_dummy_call. */
1541 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
1544 static struct value *
1545 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
1546 void **this_cache, int regnum)
1548 /* Make sure we've initialized the cache. */
1549 i386_sigtramp_frame_cache (this_frame, this_cache);
1551 return i386_frame_prev_register (this_frame, this_cache, regnum);
1555 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
1556 struct frame_info *this_frame,
1557 void **this_prologue_cache)
1559 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
1561 /* We shouldn't even bother if we don't have a sigcontext_addr
1563 if (tdep->sigcontext_addr == NULL)
1566 if (tdep->sigtramp_p != NULL)
1568 if (tdep->sigtramp_p (this_frame))
1572 if (tdep->sigtramp_start != 0)
1574 CORE_ADDR pc = get_frame_pc (this_frame);
1576 gdb_assert (tdep->sigtramp_end != 0);
1577 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
1584 static const struct frame_unwind i386_sigtramp_frame_unwind =
1587 i386_sigtramp_frame_this_id,
1588 i386_sigtramp_frame_prev_register,
1590 i386_sigtramp_frame_sniffer
1595 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
1597 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1602 static const struct frame_base i386_frame_base =
1605 i386_frame_base_address,
1606 i386_frame_base_address,
1607 i386_frame_base_address
1610 static struct frame_id
1611 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1615 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
1617 /* See the end of i386_push_dummy_call. */
1618 return frame_id_build (fp + 8, get_frame_pc (this_frame));
1622 /* Figure out where the longjmp will land. Slurp the args out of the
1623 stack. We expect the first arg to be a pointer to the jmp_buf
1624 structure from which we extract the address that we will land at.
1625 This address is copied into PC. This routine returns non-zero on
1629 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1632 CORE_ADDR sp, jb_addr;
1633 struct gdbarch *gdbarch = get_frame_arch (frame);
1634 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1635 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
1637 /* If JB_PC_OFFSET is -1, we have no way to find out where the
1638 longjmp will land. */
1639 if (jb_pc_offset == -1)
1642 get_frame_register (frame, I386_ESP_REGNUM, buf);
1643 sp = extract_unsigned_integer (buf, 4, byte_order);
1644 if (target_read_memory (sp + 4, buf, 4))
1647 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
1648 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
1651 *pc = extract_unsigned_integer (buf, 4, byte_order);
1656 /* Check whether TYPE must be 16-byte-aligned when passed as a
1657 function argument. 16-byte vectors, _Decimal128 and structures or
1658 unions containing such types must be 16-byte-aligned; other
1659 arguments are 4-byte-aligned. */
1662 i386_16_byte_align_p (struct type *type)
1664 type = check_typedef (type);
1665 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
1666 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
1667 && TYPE_LENGTH (type) == 16)
1669 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
1670 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
1671 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1672 || TYPE_CODE (type) == TYPE_CODE_UNION)
1675 for (i = 0; i < TYPE_NFIELDS (type); i++)
1677 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
1685 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1686 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
1687 struct value **args, CORE_ADDR sp, int struct_return,
1688 CORE_ADDR struct_addr)
1690 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1696 /* Determine the total space required for arguments and struct
1697 return address in a first pass (allowing for 16-byte-aligned
1698 arguments), then push arguments in a second pass. */
1700 for (write_pass = 0; write_pass < 2; write_pass++)
1702 int args_space_used = 0;
1703 int have_16_byte_aligned_arg = 0;
1709 /* Push value address. */
1710 store_unsigned_integer (buf, 4, byte_order, struct_addr);
1711 write_memory (sp, buf, 4);
1712 args_space_used += 4;
1718 for (i = 0; i < nargs; i++)
1720 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
1724 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
1725 args_space_used = align_up (args_space_used, 16);
1727 write_memory (sp + args_space_used,
1728 value_contents_all (args[i]), len);
1729 /* The System V ABI says that:
1731 "An argument's size is increased, if necessary, to make it a
1732 multiple of [32-bit] words. This may require tail padding,
1733 depending on the size of the argument."
1735 This makes sure the stack stays word-aligned. */
1736 args_space_used += align_up (len, 4);
1740 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
1742 args_space = align_up (args_space, 16);
1743 have_16_byte_aligned_arg = 1;
1745 args_space += align_up (len, 4);
1751 if (have_16_byte_aligned_arg)
1752 args_space = align_up (args_space, 16);
1757 /* Store return address. */
1759 store_unsigned_integer (buf, 4, byte_order, bp_addr);
1760 write_memory (sp, buf, 4);
1762 /* Finally, update the stack pointer... */
1763 store_unsigned_integer (buf, 4, byte_order, sp);
1764 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
1766 /* ...and fake a frame pointer. */
1767 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
1769 /* MarkK wrote: This "+ 8" is all over the place:
1770 (i386_frame_this_id, i386_sigtramp_frame_this_id,
1771 i386_dummy_id). It's there, since all frame unwinders for
1772 a given target have to agree (within a certain margin) on the
1773 definition of the stack address of a frame. Otherwise frame id
1774 comparison might not work correctly. Since DWARF2/GCC uses the
1775 stack address *before* the function call as a frame's CFA. On
1776 the i386, when %ebp is used as a frame pointer, the offset
1777 between the contents %ebp and the CFA as defined by GCC. */
1781 /* These registers are used for returning integers (and on some
1782 targets also for returning `struct' and `union' values when their
1783 size and alignment match an integer type). */
1784 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
1785 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
1787 /* Read, for architecture GDBARCH, a function return value of TYPE
1788 from REGCACHE, and copy that into VALBUF. */
1791 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
1792 struct regcache *regcache, gdb_byte *valbuf)
1794 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1795 int len = TYPE_LENGTH (type);
1796 gdb_byte buf[I386_MAX_REGISTER_SIZE];
1798 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1800 if (tdep->st0_regnum < 0)
1802 warning (_("Cannot find floating-point return value."));
1803 memset (valbuf, 0, len);
1807 /* Floating-point return values can be found in %st(0). Convert
1808 its contents to the desired type. This is probably not
1809 exactly how it would happen on the target itself, but it is
1810 the best we can do. */
1811 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
1812 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
1816 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
1817 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
1819 if (len <= low_size)
1821 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
1822 memcpy (valbuf, buf, len);
1824 else if (len <= (low_size + high_size))
1826 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
1827 memcpy (valbuf, buf, low_size);
1828 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
1829 memcpy (valbuf + low_size, buf, len - low_size);
1832 internal_error (__FILE__, __LINE__,
1833 _("Cannot extract return value of %d bytes long."), len);
1837 /* Write, for architecture GDBARCH, a function return value of TYPE
1838 from VALBUF into REGCACHE. */
1841 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
1842 struct regcache *regcache, const gdb_byte *valbuf)
1844 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1845 int len = TYPE_LENGTH (type);
1847 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1850 gdb_byte buf[I386_MAX_REGISTER_SIZE];
1852 if (tdep->st0_regnum < 0)
1854 warning (_("Cannot set floating-point return value."));
1858 /* Returning floating-point values is a bit tricky. Apart from
1859 storing the return value in %st(0), we have to simulate the
1860 state of the FPU at function return point. */
1862 /* Convert the value found in VALBUF to the extended
1863 floating-point format used by the FPU. This is probably
1864 not exactly how it would happen on the target itself, but
1865 it is the best we can do. */
1866 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
1867 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
1869 /* Set the top of the floating-point register stack to 7. The
1870 actual value doesn't really matter, but 7 is what a normal
1871 function return would end up with if the program started out
1872 with a freshly initialized FPU. */
1873 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
1875 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
1877 /* Mark %st(1) through %st(7) as empty. Since we set the top of
1878 the floating-point register stack to 7, the appropriate value
1879 for the tag word is 0x3fff. */
1880 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
1884 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
1885 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
1887 if (len <= low_size)
1888 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
1889 else if (len <= (low_size + high_size))
1891 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
1892 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
1893 len - low_size, valbuf + low_size);
1896 internal_error (__FILE__, __LINE__,
1897 _("Cannot store return value of %d bytes long."), len);
1902 /* This is the variable that is set with "set struct-convention", and
1903 its legitimate values. */
1904 static const char default_struct_convention[] = "default";
1905 static const char pcc_struct_convention[] = "pcc";
1906 static const char reg_struct_convention[] = "reg";
1907 static const char *valid_conventions[] =
1909 default_struct_convention,
1910 pcc_struct_convention,
1911 reg_struct_convention,
1914 static const char *struct_convention = default_struct_convention;
1916 /* Return non-zero if TYPE, which is assumed to be a structure,
1917 a union type, or an array type, should be returned in registers
1918 for architecture GDBARCH. */
1921 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
1923 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1924 enum type_code code = TYPE_CODE (type);
1925 int len = TYPE_LENGTH (type);
1927 gdb_assert (code == TYPE_CODE_STRUCT
1928 || code == TYPE_CODE_UNION
1929 || code == TYPE_CODE_ARRAY);
1931 if (struct_convention == pcc_struct_convention
1932 || (struct_convention == default_struct_convention
1933 && tdep->struct_return == pcc_struct_return))
1936 /* Structures consisting of a single `float', `double' or 'long
1937 double' member are returned in %st(0). */
1938 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
1940 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
1941 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1942 return (len == 4 || len == 8 || len == 12);
1945 return (len == 1 || len == 2 || len == 4 || len == 8);
1948 /* Determine, for architecture GDBARCH, how a return value of TYPE
1949 should be returned. If it is supposed to be returned in registers,
1950 and READBUF is non-zero, read the appropriate value from REGCACHE,
1951 and copy it into READBUF. If WRITEBUF is non-zero, write the value
1952 from WRITEBUF into REGCACHE. */
1954 static enum return_value_convention
1955 i386_return_value (struct gdbarch *gdbarch, struct type *func_type,
1956 struct type *type, struct regcache *regcache,
1957 gdb_byte *readbuf, const gdb_byte *writebuf)
1959 enum type_code code = TYPE_CODE (type);
1961 if (((code == TYPE_CODE_STRUCT
1962 || code == TYPE_CODE_UNION
1963 || code == TYPE_CODE_ARRAY)
1964 && !i386_reg_struct_return_p (gdbarch, type))
1965 /* 128-bit decimal float uses the struct return convention. */
1966 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
1968 /* The System V ABI says that:
1970 "A function that returns a structure or union also sets %eax
1971 to the value of the original address of the caller's area
1972 before it returns. Thus when the caller receives control
1973 again, the address of the returned object resides in register
1974 %eax and can be used to access the object."
1976 So the ABI guarantees that we can always find the return
1977 value just after the function has returned. */
1979 /* Note that the ABI doesn't mention functions returning arrays,
1980 which is something possible in certain languages such as Ada.
1981 In this case, the value is returned as if it was wrapped in
1982 a record, so the convention applied to records also applies
1989 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
1990 read_memory (addr, readbuf, TYPE_LENGTH (type));
1993 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
1996 /* This special case is for structures consisting of a single
1997 `float', `double' or 'long double' member. These structures are
1998 returned in %st(0). For these structures, we call ourselves
1999 recursively, changing TYPE into the type of the first member of
2000 the structure. Since that should work for all structures that
2001 have only one member, we don't bother to check the member's type
2003 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2005 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2006 return i386_return_value (gdbarch, func_type, type, regcache,
2011 i386_extract_return_value (gdbarch, type, regcache, readbuf);
2013 i386_store_return_value (gdbarch, type, regcache, writebuf);
2015 return RETURN_VALUE_REGISTER_CONVENTION;
2019 /* Construct types for ISA-specific registers. */
2021 i386_eflags_type (struct gdbarch *gdbarch)
2023 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2025 if (!tdep->i386_eflags_type)
2029 type = arch_flags_type (gdbarch, "builtin_type_i386_eflags", 4);
2030 append_flags_type_flag (type, 0, "CF");
2031 append_flags_type_flag (type, 1, NULL);
2032 append_flags_type_flag (type, 2, "PF");
2033 append_flags_type_flag (type, 4, "AF");
2034 append_flags_type_flag (type, 6, "ZF");
2035 append_flags_type_flag (type, 7, "SF");
2036 append_flags_type_flag (type, 8, "TF");
2037 append_flags_type_flag (type, 9, "IF");
2038 append_flags_type_flag (type, 10, "DF");
2039 append_flags_type_flag (type, 11, "OF");
2040 append_flags_type_flag (type, 14, "NT");
2041 append_flags_type_flag (type, 16, "RF");
2042 append_flags_type_flag (type, 17, "VM");
2043 append_flags_type_flag (type, 18, "AC");
2044 append_flags_type_flag (type, 19, "VIF");
2045 append_flags_type_flag (type, 20, "VIP");
2046 append_flags_type_flag (type, 21, "ID");
2048 tdep->i386_eflags_type = type;
2051 return tdep->i386_eflags_type;
2055 i386_mxcsr_type (struct gdbarch *gdbarch)
2057 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2059 if (!tdep->i386_mxcsr_type)
2063 type = arch_flags_type (gdbarch, "builtin_type_i386_mxcsr", 4);
2064 append_flags_type_flag (type, 0, "IE");
2065 append_flags_type_flag (type, 1, "DE");
2066 append_flags_type_flag (type, 2, "ZE");
2067 append_flags_type_flag (type, 3, "OE");
2068 append_flags_type_flag (type, 4, "UE");
2069 append_flags_type_flag (type, 5, "PE");
2070 append_flags_type_flag (type, 6, "DAZ");
2071 append_flags_type_flag (type, 7, "IM");
2072 append_flags_type_flag (type, 8, "DM");
2073 append_flags_type_flag (type, 9, "ZM");
2074 append_flags_type_flag (type, 10, "OM");
2075 append_flags_type_flag (type, 11, "UM");
2076 append_flags_type_flag (type, 12, "PM");
2077 append_flags_type_flag (type, 15, "FZ");
2079 tdep->i386_mxcsr_type = type;
2082 return tdep->i386_mxcsr_type;
2086 i387_ext_type (struct gdbarch *gdbarch)
2088 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2090 if (!tdep->i387_ext_type)
2092 = arch_float_type (gdbarch, -1, "builtin_type_i387_ext",
2093 floatformats_i387_ext);
2095 return tdep->i387_ext_type;
2098 /* Construct vector type for MMX registers. */
2100 i386_mmx_type (struct gdbarch *gdbarch)
2102 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2104 if (!tdep->i386_mmx_type)
2106 const struct builtin_type *bt = builtin_type (gdbarch);
2108 /* The type we're building is this: */
2110 union __gdb_builtin_type_vec64i
2113 int32_t v2_int32[2];
2114 int16_t v4_int16[4];
2121 t = arch_composite_type (gdbarch,
2122 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
2124 append_composite_type_field (t, "uint64", bt->builtin_int64);
2125 append_composite_type_field (t, "v2_int32",
2126 init_vector_type (bt->builtin_int32, 2));
2127 append_composite_type_field (t, "v4_int16",
2128 init_vector_type (bt->builtin_int16, 4));
2129 append_composite_type_field (t, "v8_int8",
2130 init_vector_type (bt->builtin_int8, 8));
2132 TYPE_VECTOR (t) = 1;
2133 TYPE_NAME (t) = "builtin_type_vec64i";
2134 tdep->i386_mmx_type = t;
2137 return tdep->i386_mmx_type;
2141 i386_sse_type (struct gdbarch *gdbarch)
2143 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2145 if (!tdep->i386_sse_type)
2147 const struct builtin_type *bt = builtin_type (gdbarch);
2149 /* The type we're building is this: */
2151 union __gdb_builtin_type_vec128i
2154 int64_t v2_int64[2];
2155 int32_t v4_int32[4];
2156 int16_t v8_int16[8];
2157 int8_t v16_int8[16];
2158 double v2_double[2];
2165 t = arch_composite_type (gdbarch,
2166 "__gdb_builtin_type_vec128i", TYPE_CODE_UNION);
2167 append_composite_type_field (t, "v4_float",
2168 init_vector_type (bt->builtin_float, 4));
2169 append_composite_type_field (t, "v2_double",
2170 init_vector_type (bt->builtin_double, 2));
2171 append_composite_type_field (t, "v16_int8",
2172 init_vector_type (bt->builtin_int8, 16));
2173 append_composite_type_field (t, "v8_int16",
2174 init_vector_type (bt->builtin_int16, 8));
2175 append_composite_type_field (t, "v4_int32",
2176 init_vector_type (bt->builtin_int32, 4));
2177 append_composite_type_field (t, "v2_int64",
2178 init_vector_type (bt->builtin_int64, 2));
2179 append_composite_type_field (t, "uint128", bt->builtin_int128);
2181 TYPE_VECTOR (t) = 1;
2182 TYPE_NAME (t) = "builtin_type_vec128i";
2183 tdep->i386_sse_type = t;
2186 return tdep->i386_sse_type;
2189 /* Return the GDB type object for the "standard" data type of data in
2190 register REGNUM. Perhaps %esi and %edi should go here, but
2191 potentially they could be used for things other than address. */
2193 static struct type *
2194 i386_register_type (struct gdbarch *gdbarch, int regnum)
2196 if (regnum == I386_EIP_REGNUM)
2197 return builtin_type (gdbarch)->builtin_func_ptr;
2199 if (regnum == I386_EFLAGS_REGNUM)
2200 return i386_eflags_type (gdbarch);
2202 if (regnum == I386_EBP_REGNUM || regnum == I386_ESP_REGNUM)
2203 return builtin_type (gdbarch)->builtin_data_ptr;
2205 if (i386_fp_regnum_p (gdbarch, regnum))
2206 return i387_ext_type (gdbarch);
2208 if (i386_mmx_regnum_p (gdbarch, regnum))
2209 return i386_mmx_type (gdbarch);
2211 if (i386_sse_regnum_p (gdbarch, regnum))
2212 return i386_sse_type (gdbarch);
2214 if (regnum == I387_MXCSR_REGNUM (gdbarch_tdep (gdbarch)))
2215 return i386_mxcsr_type (gdbarch);
2217 return builtin_type (gdbarch)->builtin_int;
2220 /* Map a cooked register onto a raw register or memory. For the i386,
2221 the MMX registers need to be mapped onto floating point registers. */
2224 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
2226 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
2231 mmxreg = regnum - tdep->mm0_regnum;
2232 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2233 tos = (fstat >> 11) & 0x7;
2234 fpreg = (mmxreg + tos) % 8;
2236 return (I387_ST0_REGNUM (tdep) + fpreg);
2240 i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2241 int regnum, gdb_byte *buf)
2243 if (i386_mmx_regnum_p (gdbarch, regnum))
2245 gdb_byte mmx_buf[MAX_REGISTER_SIZE];
2246 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2248 /* Extract (always little endian). */
2249 regcache_raw_read (regcache, fpnum, mmx_buf);
2250 memcpy (buf, mmx_buf, register_size (gdbarch, regnum));
2253 regcache_raw_read (regcache, regnum, buf);
2257 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2258 int regnum, const gdb_byte *buf)
2260 if (i386_mmx_regnum_p (gdbarch, regnum))
2262 gdb_byte mmx_buf[MAX_REGISTER_SIZE];
2263 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2266 regcache_raw_read (regcache, fpnum, mmx_buf);
2267 /* ... Modify ... (always little endian). */
2268 memcpy (mmx_buf, buf, register_size (gdbarch, regnum));
2270 regcache_raw_write (regcache, fpnum, mmx_buf);
2273 regcache_raw_write (regcache, regnum, buf);
2277 /* Return the register number of the register allocated by GCC after
2278 REGNUM, or -1 if there is no such register. */
2281 i386_next_regnum (int regnum)
2283 /* GCC allocates the registers in the order:
2285 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2287 Since storing a variable in %esp doesn't make any sense we return
2288 -1 for %ebp and for %esp itself. */
2289 static int next_regnum[] =
2291 I386_EDX_REGNUM, /* Slot for %eax. */
2292 I386_EBX_REGNUM, /* Slot for %ecx. */
2293 I386_ECX_REGNUM, /* Slot for %edx. */
2294 I386_ESI_REGNUM, /* Slot for %ebx. */
2295 -1, -1, /* Slots for %esp and %ebp. */
2296 I386_EDI_REGNUM, /* Slot for %esi. */
2297 I386_EBP_REGNUM /* Slot for %edi. */
2300 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
2301 return next_regnum[regnum];
2306 /* Return nonzero if a value of type TYPE stored in register REGNUM
2307 needs any special handling. */
2310 i386_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type)
2312 int len = TYPE_LENGTH (type);
2314 /* Values may be spread across multiple registers. Most debugging
2315 formats aren't expressive enough to specify the locations, so
2316 some heuristics is involved. Right now we only handle types that
2317 have a length that is a multiple of the word size, since GCC
2318 doesn't seem to put any other types into registers. */
2319 if (len > 4 && len % 4 == 0)
2321 int last_regnum = regnum;
2325 last_regnum = i386_next_regnum (last_regnum);
2329 if (last_regnum != -1)
2333 return i387_convert_register_p (gdbarch, regnum, type);
2336 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2337 return its contents in TO. */
2340 i386_register_to_value (struct frame_info *frame, int regnum,
2341 struct type *type, gdb_byte *to)
2343 struct gdbarch *gdbarch = get_frame_arch (frame);
2344 int len = TYPE_LENGTH (type);
2346 /* FIXME: kettenis/20030609: What should we do if REGNUM isn't
2347 available in FRAME (i.e. if it wasn't saved)? */
2349 if (i386_fp_regnum_p (gdbarch, regnum))
2351 i387_register_to_value (frame, regnum, type, to);
2355 /* Read a value spread across multiple registers. */
2357 gdb_assert (len > 4 && len % 4 == 0);
2361 gdb_assert (regnum != -1);
2362 gdb_assert (register_size (gdbarch, regnum) == 4);
2364 get_frame_register (frame, regnum, to);
2365 regnum = i386_next_regnum (regnum);
2371 /* Write the contents FROM of a value of type TYPE into register
2372 REGNUM in frame FRAME. */
2375 i386_value_to_register (struct frame_info *frame, int regnum,
2376 struct type *type, const gdb_byte *from)
2378 int len = TYPE_LENGTH (type);
2380 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
2382 i387_value_to_register (frame, regnum, type, from);
2386 /* Write a value spread across multiple registers. */
2388 gdb_assert (len > 4 && len % 4 == 0);
2392 gdb_assert (regnum != -1);
2393 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
2395 put_frame_register (frame, regnum, from);
2396 regnum = i386_next_regnum (regnum);
2402 /* Supply register REGNUM from the buffer specified by GREGS and LEN
2403 in the general-purpose register set REGSET to register cache
2404 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2407 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
2408 int regnum, const void *gregs, size_t len)
2410 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2411 const gdb_byte *regs = gregs;
2414 gdb_assert (len == tdep->sizeof_gregset);
2416 for (i = 0; i < tdep->gregset_num_regs; i++)
2418 if ((regnum == i || regnum == -1)
2419 && tdep->gregset_reg_offset[i] != -1)
2420 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
2424 /* Collect register REGNUM from the register cache REGCACHE and store
2425 it in the buffer specified by GREGS and LEN as described by the
2426 general-purpose register set REGSET. If REGNUM is -1, do this for
2427 all registers in REGSET. */
2430 i386_collect_gregset (const struct regset *regset,
2431 const struct regcache *regcache,
2432 int regnum, void *gregs, size_t len)
2434 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2435 gdb_byte *regs = gregs;
2438 gdb_assert (len == tdep->sizeof_gregset);
2440 for (i = 0; i < tdep->gregset_num_regs; i++)
2442 if ((regnum == i || regnum == -1)
2443 && tdep->gregset_reg_offset[i] != -1)
2444 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
2448 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2449 in the floating-point register set REGSET to register cache
2450 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2453 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
2454 int regnum, const void *fpregs, size_t len)
2456 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2458 if (len == I387_SIZEOF_FXSAVE)
2460 i387_supply_fxsave (regcache, regnum, fpregs);
2464 gdb_assert (len == tdep->sizeof_fpregset);
2465 i387_supply_fsave (regcache, regnum, fpregs);
2468 /* Collect register REGNUM from the register cache REGCACHE and store
2469 it in the buffer specified by FPREGS and LEN as described by the
2470 floating-point register set REGSET. If REGNUM is -1, do this for
2471 all registers in REGSET. */
2474 i386_collect_fpregset (const struct regset *regset,
2475 const struct regcache *regcache,
2476 int regnum, void *fpregs, size_t len)
2478 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2480 if (len == I387_SIZEOF_FXSAVE)
2482 i387_collect_fxsave (regcache, regnum, fpregs);
2486 gdb_assert (len == tdep->sizeof_fpregset);
2487 i387_collect_fsave (regcache, regnum, fpregs);
2490 /* Return the appropriate register set for the core section identified
2491 by SECT_NAME and SECT_SIZE. */
2493 const struct regset *
2494 i386_regset_from_core_section (struct gdbarch *gdbarch,
2495 const char *sect_name, size_t sect_size)
2497 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2499 if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset)
2501 if (tdep->gregset == NULL)
2502 tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset,
2503 i386_collect_gregset);
2504 return tdep->gregset;
2507 if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
2508 || (strcmp (sect_name, ".reg-xfp") == 0
2509 && sect_size == I387_SIZEOF_FXSAVE))
2511 if (tdep->fpregset == NULL)
2512 tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset,
2513 i386_collect_fpregset);
2514 return tdep->fpregset;
2521 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
2524 i386_pe_skip_trampoline_code (struct frame_info *frame,
2525 CORE_ADDR pc, char *name)
2527 struct gdbarch *gdbarch = get_frame_arch (frame);
2528 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2531 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
2533 unsigned long indirect =
2534 read_memory_unsigned_integer (pc + 2, 4, byte_order);
2535 struct minimal_symbol *indsym =
2536 indirect ? lookup_minimal_symbol_by_pc (indirect) : 0;
2537 char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0;
2541 if (strncmp (symname, "__imp_", 6) == 0
2542 || strncmp (symname, "_imp_", 5) == 0)
2544 read_memory_unsigned_integer (indirect, 4, byte_order);
2547 return 0; /* Not a trampoline. */
2551 /* Return whether the THIS_FRAME corresponds to a sigtramp
2555 i386_sigtramp_p (struct frame_info *this_frame)
2557 CORE_ADDR pc = get_frame_pc (this_frame);
2560 find_pc_partial_function (pc, &name, NULL, NULL);
2561 return (name && strcmp ("_sigtramp", name) == 0);
2565 /* We have two flavours of disassembly. The machinery on this page
2566 deals with switching between those. */
2569 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
2571 gdb_assert (disassembly_flavor == att_flavor
2572 || disassembly_flavor == intel_flavor);
2574 /* FIXME: kettenis/20020915: Until disassembler_options is properly
2575 constified, cast to prevent a compiler warning. */
2576 info->disassembler_options = (char *) disassembly_flavor;
2578 return print_insn_i386 (pc, info);
2582 /* There are a few i386 architecture variants that differ only
2583 slightly from the generic i386 target. For now, we don't give them
2584 their own source file, but include them here. As a consequence,
2585 they'll always be included. */
2587 /* System V Release 4 (SVR4). */
2589 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
2593 i386_svr4_sigtramp_p (struct frame_info *this_frame)
2595 CORE_ADDR pc = get_frame_pc (this_frame);
2598 /* UnixWare uses _sigacthandler. The origin of the other symbols is
2599 currently unknown. */
2600 find_pc_partial_function (pc, &name, NULL, NULL);
2601 return (name && (strcmp ("_sigreturn", name) == 0
2602 || strcmp ("_sigacthandler", name) == 0
2603 || strcmp ("sigvechandler", name) == 0));
2606 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
2607 address of the associated sigcontext (ucontext) structure. */
2610 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
2612 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2613 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2617 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2618 sp = extract_unsigned_integer (buf, 4, byte_order);
2620 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
2627 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2629 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
2630 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
2633 /* System V Release 4 (SVR4). */
2636 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2638 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2640 /* System V Release 4 uses ELF. */
2641 i386_elf_init_abi (info, gdbarch);
2643 /* System V Release 4 has shared libraries. */
2644 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
2646 tdep->sigtramp_p = i386_svr4_sigtramp_p;
2647 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
2648 tdep->sc_pc_offset = 36 + 14 * 4;
2649 tdep->sc_sp_offset = 36 + 17 * 4;
2651 tdep->jb_pc_offset = 20;
2657 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2659 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2661 /* DJGPP doesn't have any special frames for signal handlers. */
2662 tdep->sigtramp_p = NULL;
2664 tdep->jb_pc_offset = 36;
2666 /* DJGPP does not support the SSE registers. */
2667 tdep->num_xmm_regs = 0;
2668 set_gdbarch_num_regs (gdbarch, I386_NUM_GREGS + I386_NUM_FREGS);
2670 /* Native compiler is GCC, which uses the SVR4 register numbering
2671 even in COFF and STABS. See the comment in i386_gdbarch_init,
2672 before the calls to set_gdbarch_stab_reg_to_regnum and
2673 set_gdbarch_sdb_reg_to_regnum. */
2674 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
2675 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
2679 /* i386 register groups. In addition to the normal groups, add "mmx"
2682 static struct reggroup *i386_sse_reggroup;
2683 static struct reggroup *i386_mmx_reggroup;
2686 i386_init_reggroups (void)
2688 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
2689 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
2693 i386_add_reggroups (struct gdbarch *gdbarch)
2695 reggroup_add (gdbarch, i386_sse_reggroup);
2696 reggroup_add (gdbarch, i386_mmx_reggroup);
2697 reggroup_add (gdbarch, general_reggroup);
2698 reggroup_add (gdbarch, float_reggroup);
2699 reggroup_add (gdbarch, all_reggroup);
2700 reggroup_add (gdbarch, save_reggroup);
2701 reggroup_add (gdbarch, restore_reggroup);
2702 reggroup_add (gdbarch, vector_reggroup);
2703 reggroup_add (gdbarch, system_reggroup);
2707 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2708 struct reggroup *group)
2710 int sse_regnum_p = (i386_sse_regnum_p (gdbarch, regnum)
2711 || i386_mxcsr_regnum_p (gdbarch, regnum));
2712 int fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
2713 || i386_fpc_regnum_p (gdbarch, regnum));
2714 int mmx_regnum_p = (i386_mmx_regnum_p (gdbarch, regnum));
2716 if (group == i386_mmx_reggroup)
2717 return mmx_regnum_p;
2718 if (group == i386_sse_reggroup)
2719 return sse_regnum_p;
2720 if (group == vector_reggroup)
2721 return (mmx_regnum_p || sse_regnum_p);
2722 if (group == float_reggroup)
2724 if (group == general_reggroup)
2725 return (!fp_regnum_p && !mmx_regnum_p && !sse_regnum_p);
2727 return default_register_reggroup_p (gdbarch, regnum, group);
2731 /* Get the ARGIth function argument for the current function. */
2734 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
2737 struct gdbarch *gdbarch = get_frame_arch (frame);
2738 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2739 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
2740 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
2744 i386_skip_permanent_breakpoint (struct regcache *regcache)
2746 CORE_ADDR current_pc = regcache_read_pc (regcache);
2748 /* On i386, breakpoint is exactly 1 byte long, so we just
2749 adjust the PC in the regcache. */
2751 regcache_write_pc (regcache, current_pc);
2755 #define PREFIX_REPZ 0x01
2756 #define PREFIX_REPNZ 0x02
2757 #define PREFIX_LOCK 0x04
2758 #define PREFIX_DATA 0x08
2759 #define PREFIX_ADDR 0x10
2769 /* i386 arith/logic operations */
2782 struct i386_record_s
2784 struct regcache *regcache;
2790 uint8_t mod, reg, rm;
2794 /* Parse "modrm" part in current memory address that irp->addr point to
2795 Return -1 if something wrong. */
2798 i386_record_modrm (struct i386_record_s *irp)
2800 struct gdbarch *gdbarch = get_regcache_arch (irp->regcache);
2802 if (target_read_memory (irp->addr, &irp->modrm, 1))
2805 printf_unfiltered (_("Process record: error reading memory at "
2806 "addr %s len = 1.\n"),
2807 paddress (gdbarch, irp->addr));
2811 irp->mod = (irp->modrm >> 6) & 3;
2812 irp->reg = (irp->modrm >> 3) & 7;
2813 irp->rm = irp->modrm & 7;
2818 /* Get the memory address that current instruction write to and set it to
2819 the argument "addr".
2820 Return -1 if something wrong. */
2823 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint32_t * addr)
2825 struct gdbarch *gdbarch = get_regcache_arch (irp->regcache);
2837 uint8_t base = irp->rm;
2842 if (target_read_memory (irp->addr, &tmpu8, 1))
2845 printf_unfiltered (_("Process record: error reading memory "
2846 "at addr %s len = 1.\n"),
2847 paddress (gdbarch, irp->addr));
2851 scale = (tmpu8 >> 6) & 3;
2852 index = ((tmpu8 >> 3) & 7);
2859 if ((base & 7) == 5)
2862 if (target_read_memory (irp->addr, (gdb_byte *) addr, 4))
2865 printf_unfiltered (_("Process record: error reading "
2866 "memory at addr %s len = 4.\n"),
2867 paddress (gdbarch, irp->addr));
2878 if (target_read_memory (irp->addr, &tmpu8, 1))
2881 printf_unfiltered (_("Process record: error reading memory "
2882 "at addr %s len = 1.\n"),
2883 paddress (gdbarch, irp->addr));
2887 *addr = (int8_t) tmpu8;
2890 if (target_read_memory (irp->addr, (gdb_byte *) addr, 4))
2893 printf_unfiltered (_("Process record: error reading memory "
2894 "at addr %s len = 4.\n"),
2895 paddress (gdbarch, irp->addr));
2904 regcache_raw_read (irp->regcache, base, (gdb_byte *) & tmpu32);
2908 /* XXX: index == 4 is always invalid */
2909 if (havesib && (index != 4 || scale != 0))
2911 regcache_raw_read (irp->regcache, index, (gdb_byte *) & tmpu32);
2912 *addr += tmpu32 << scale;
2923 if (target_read_memory
2924 (irp->addr, (gdb_byte *) & tmpu16, 2))
2927 printf_unfiltered (_("Process record: error reading "
2928 "memory at addr %s len = 2.\n"),
2929 paddress (gdbarch, irp->addr));
2933 *addr = (int16_t) tmpu16;
2943 if (target_read_memory (irp->addr, &tmpu8, 1))
2946 printf_unfiltered (_("Process record: error reading memory "
2947 "at addr %s len = 1.\n"),
2948 paddress (gdbarch, irp->addr));
2952 *addr = (int8_t) tmpu8;
2955 if (target_read_memory (irp->addr, (gdb_byte *) & tmpu16, 2))
2958 printf_unfiltered (_("Process record: error reading memory "
2959 "at addr %s len = 2.\n"),
2960 paddress (gdbarch, irp->addr));
2964 *addr = (int16_t) tmpu16;
2971 regcache_raw_read (irp->regcache, I386_EBX_REGNUM,
2972 (gdb_byte *) & tmpu32);
2974 regcache_raw_read (irp->regcache, I386_ESI_REGNUM,
2975 (gdb_byte *) & tmpu32);
2979 regcache_raw_read (irp->regcache, I386_EBX_REGNUM,
2980 (gdb_byte *) & tmpu32);
2982 regcache_raw_read (irp->regcache, I386_EDI_REGNUM,
2983 (gdb_byte *) & tmpu32);
2987 regcache_raw_read (irp->regcache, I386_EBP_REGNUM,
2988 (gdb_byte *) & tmpu32);
2990 regcache_raw_read (irp->regcache, I386_ESI_REGNUM,
2991 (gdb_byte *) & tmpu32);
2995 regcache_raw_read (irp->regcache, I386_EBP_REGNUM,
2996 (gdb_byte *) & tmpu32);
2998 regcache_raw_read (irp->regcache, I386_EDI_REGNUM,
2999 (gdb_byte *) & tmpu32);
3003 regcache_raw_read (irp->regcache, I386_ESI_REGNUM,
3004 (gdb_byte *) & tmpu32);
3008 regcache_raw_read (irp->regcache, I386_EDI_REGNUM,
3009 (gdb_byte *) & tmpu32);
3013 regcache_raw_read (irp->regcache, I386_EBP_REGNUM,
3014 (gdb_byte *) & tmpu32);
3018 regcache_raw_read (irp->regcache, I386_EBX_REGNUM,
3019 (gdb_byte *) & tmpu32);
3030 /* Record the value of the memory that willbe changed in current instruction
3031 to "record_arch_list".
3032 Return -1 if something wrong. */
3035 i386_record_lea_modrm (struct i386_record_s *irp)
3037 struct gdbarch *gdbarch = get_regcache_arch (irp->regcache);
3043 printf_unfiltered (_("Process record ignores the memory change "
3044 "of instruction at address %s because it "
3045 "can't get the value of the segment register.\n"),
3046 paddress (gdbarch, irp->addr));
3050 if (i386_record_lea_modrm_addr (irp, &addr))
3053 if (record_arch_list_add_mem (addr, 1 << irp->ot))
3059 /* Parse the current instruction and record the values of the registers and
3060 memory that will be changed in current instruction to "record_arch_list".
3061 Return -1 if something wrong. */
3064 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
3072 struct i386_record_s ir;
3074 memset (&ir, 0, sizeof (struct i386_record_s));
3075 ir.regcache = regcache;
3080 if (record_debug > 1)
3081 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
3083 paddress (gdbarch, ir.addr));
3088 if (target_read_memory (ir.addr, &tmpu8, 1))
3091 printf_unfiltered (_("Process record: error reading memory at "
3092 "addr %s len = 1.\n"),
3093 paddress (gdbarch, ir.addr));
3100 prefixes |= PREFIX_REPZ;
3103 prefixes |= PREFIX_REPNZ;
3106 prefixes |= PREFIX_LOCK;
3109 ir.override = I386_CS_REGNUM;
3112 ir.override = I386_SS_REGNUM;
3115 ir.override = I386_DS_REGNUM;
3118 ir.override = I386_ES_REGNUM;
3121 ir.override = I386_FS_REGNUM;
3124 ir.override = I386_GS_REGNUM;
3127 prefixes |= PREFIX_DATA;
3130 prefixes |= PREFIX_ADDR;
3138 if (prefixes & PREFIX_DATA)
3140 if (prefixes & PREFIX_ADDR)
3143 /* now check op code */
3144 opcode = (uint32_t) tmpu8;
3149 if (target_read_memory (ir.addr, &tmpu8, 1))
3152 printf_unfiltered (_("Process record: error reading memory at "
3153 "addr %s len = 1.\n"),
3154 paddress (gdbarch, ir.addr));
3158 opcode = (uint16_t) tmpu8 | 0x0f00;
3211 if (((opcode >> 3) & 7) != OP_CMPL)
3213 if ((opcode & 1) == 0)
3216 ir.ot = ir.dflag + OT_WORD;
3218 switch ((opcode >> 1) & 3)
3222 if (i386_record_modrm (&ir))
3226 if (i386_record_lea_modrm (&ir))
3231 if (ir.ot == OT_BYTE)
3233 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3239 if (i386_record_modrm (&ir))
3241 if (ir.ot == OT_BYTE)
3243 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3248 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3253 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3262 if (i386_record_modrm (&ir))
3265 if (ir.reg != OP_CMPL)
3267 if ((opcode & 1) == 0)
3270 ir.ot = ir.dflag + OT_WORD;
3274 if (i386_record_lea_modrm (&ir))
3279 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3283 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3305 if (record_arch_list_add_reg (ir.regcache, opcode & 7))
3307 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3314 if ((opcode & 1) == 0)
3317 ir.ot = ir.dflag + OT_WORD;
3318 if (i386_record_modrm (&ir))
3325 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3332 if (i386_record_lea_modrm (&ir))
3337 if (ir.ot == OT_BYTE)
3339 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3347 if (i386_record_lea_modrm (&ir))
3352 if (ir.ot == OT_BYTE)
3354 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3357 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3368 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3370 if (ir.ot != OT_BYTE)
3372 if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM))
3375 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3380 opcode = opcode << 8 | ir.modrm;
3390 if ((opcode & 1) == 0)
3393 ir.ot = ir.dflag + OT_WORD;
3394 if (i386_record_modrm (&ir))
3396 if (ir.reg >= 2 && opcode == 0xfe)
3399 opcode = opcode << 8 | ir.modrm;
3411 if (i386_record_lea_modrm (&ir))
3416 if (ir.ot == OT_BYTE)
3418 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3421 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3428 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3430 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
3431 (gdb_byte *) & tmpu32);
3432 if (record_arch_list_add_mem
3433 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1))))
3438 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3440 if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM))
3442 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
3443 (gdb_byte *) & tmpu32);
3444 if (record_arch_list_add_mem
3445 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 2)), (1 << (ir.dflag + 2))))
3455 opcode = opcode << 8 | ir.modrm;
3466 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3472 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3478 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3480 if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM))
3488 ir.ot = ir.dflag + OT_WORD;
3489 if (i386_record_modrm (&ir))
3491 if (ir.ot == OT_BYTE)
3493 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3495 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3502 if ((opcode & 1) == 0)
3505 ir.ot = ir.dflag + OT_WORD;
3506 if (i386_record_modrm (&ir))
3510 if (ir.ot == OT_BYTE)
3512 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3514 if (ir.ot == OT_BYTE)
3516 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3521 if (i386_record_lea_modrm (&ir))
3523 if (ir.ot == OT_BYTE)
3525 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3528 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3535 if ((opcode & 1) == 0)
3538 ir.ot = ir.dflag + OT_WORD;
3539 if (i386_record_modrm (&ir))
3543 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3545 if (ir.ot == OT_BYTE)
3547 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3552 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3554 if (i386_record_lea_modrm (&ir))
3557 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3563 if (i386_record_modrm (&ir))
3568 opcode = opcode << 8 | ir.modrm;
3571 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3573 if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM))
3575 if (i386_record_lea_modrm (&ir))
3577 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3604 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3606 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
3607 (gdb_byte *) & tmpu32);
3608 if (record_arch_list_add_mem
3609 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1))))
3622 ir.ot = ir.dflag + OT_WORD;
3623 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3625 if (ir.ot == OT_BYTE)
3627 if (record_arch_list_add_reg (ir.regcache, opcode & 0x7))
3633 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3635 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
3636 (gdb_byte *) & tmpu32);
3637 if (record_arch_list_add_mem
3638 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 4)), (1 << (ir.dflag + 4))))
3644 for (tmpu8 = I386_EAX_REGNUM; tmpu8 <= I386_EDI_REGNUM; tmpu8++)
3646 if (record_arch_list_add_reg (ir.regcache, tmpu8))
3653 ir.ot = ir.dflag + OT_WORD;
3654 if (i386_record_modrm (&ir))
3658 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3663 if (i386_record_lea_modrm (&ir))
3666 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3672 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3674 if (record_arch_list_add_reg (ir.regcache, I386_EBP_REGNUM))
3676 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
3677 (gdb_byte *) & tmpu32);
3678 if (record_arch_list_add_mem
3679 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1))))
3685 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3687 if (record_arch_list_add_reg (ir.regcache, I386_EBP_REGNUM))
3693 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3695 if (record_arch_list_add_reg (ir.regcache, I386_ES_REGNUM))
3701 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3703 if (record_arch_list_add_reg (ir.regcache, I386_SS_REGNUM))
3709 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3711 if (record_arch_list_add_reg (ir.regcache, I386_DS_REGNUM))
3717 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3719 if (record_arch_list_add_reg (ir.regcache, I386_FS_REGNUM))
3725 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3727 if (record_arch_list_add_reg (ir.regcache, I386_GS_REGNUM))
3736 if ((opcode & 1) == 0)
3739 ir.ot = ir.dflag + OT_WORD;
3741 if (i386_record_modrm (&ir))
3746 if (i386_record_lea_modrm (&ir))
3751 if (ir.ot == OT_BYTE)
3753 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3756 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3762 if ((opcode & 1) == 0)
3765 ir.ot = ir.dflag + OT_WORD;
3767 if (i386_record_modrm (&ir))
3770 if (ir.ot == OT_BYTE)
3772 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3775 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3781 if (i386_record_modrm (&ir))
3787 tmpu8 = I386_ES_REGNUM;
3790 tmpu8 = I386_SS_REGNUM;
3793 tmpu8 = I386_DS_REGNUM;
3796 tmpu8 = I386_FS_REGNUM;
3799 tmpu8 = I386_GS_REGNUM;
3803 opcode = opcode << 8 | ir.modrm;
3807 if (record_arch_list_add_reg (ir.regcache, tmpu8))
3810 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3816 if (i386_record_modrm (&ir))
3821 opcode = opcode << 8 | ir.modrm;
3827 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3833 if (i386_record_lea_modrm (&ir))
3837 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3849 if (i386_record_modrm (&ir))
3851 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3857 if (i386_record_modrm (&ir))
3862 opcode = opcode << 8 | ir.modrm;
3867 if (ir.ot == OT_BYTE)
3869 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3878 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3891 printf_unfiltered (_("Process record ignores the memory change "
3892 "of instruction at address %s because "
3893 "it can't get the value of the segment "
3895 paddress (gdbarch, ir.addr));
3899 if ((opcode & 1) == 0)
3902 ir.ot = ir.dflag + OT_WORD;
3905 if (target_read_memory
3906 (ir.addr, (gdb_byte *) & addr, 4))
3909 printf_unfiltered (_("Process record: error reading "
3910 "memory at addr %s len = 4.\n"),
3911 paddress (gdbarch, ir.addr));
3918 if (target_read_memory
3919 (ir.addr, (gdb_byte *) & tmpu16, 4))
3922 printf_unfiltered (_("Process record: error reading "
3923 "memory at addr %s len = 4.\n"),
3924 paddress (gdbarch, ir.addr));
3930 if (record_arch_list_add_mem (addr, 1 << ir.ot))
3945 if (record_arch_list_add_reg (ir.regcache, (opcode & 0x7) & 0x3))
3958 if (record_arch_list_add_reg (ir.regcache, opcode & 0x7))
3970 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3972 if (record_arch_list_add_reg (ir.regcache, opcode & 0x7))
3979 if ((opcode & 1) == 0)
3982 ir.ot = ir.dflag + OT_WORD;
3984 if (i386_record_modrm (&ir))
3989 if (ir.ot == OT_BYTE)
3991 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3996 if (i386_record_lea_modrm (&ir))
4000 if (ir.ot == OT_BYTE)
4002 if (record_arch_list_add_reg (ir.regcache, ir.reg))
4016 if (i386_record_modrm (&ir))
4024 opcode = opcode << 8 | ir.modrm;
4032 tmpu8 = I386_ES_REGNUM;
4036 tmpu8 = I386_DS_REGNUM;
4040 tmpu8 = I386_SS_REGNUM;
4044 tmpu8 = I386_FS_REGNUM;
4048 tmpu8 = I386_GS_REGNUM;
4051 if (record_arch_list_add_reg (ir.regcache, tmpu8))
4054 if (record_arch_list_add_reg (ir.regcache, ir.reg))
4065 if ((opcode & 1) == 0)
4068 ir.ot = ir.dflag + OT_WORD;
4070 if (i386_record_modrm (&ir))
4073 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
4075 if (i386_record_lea_modrm (&ir))
4080 if (ir.ot == OT_BYTE)
4082 if (record_arch_list_add_reg (ir.regcache, ir.rm))
4086 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4094 if (i386_record_modrm (&ir))
4098 if (record_arch_list_add_reg (ir.regcache, ir.rm))
4103 if (i386_record_lea_modrm (&ir))
4109 /* It just record the memory change of instrcution. */
4118 if (i386_record_modrm (&ir))
4120 ir.reg |= ((opcode & 7) << 3);
4126 if (i386_record_lea_modrm_addr (&ir, &addr))
4183 switch (ir.reg >> 4)
4186 if (record_arch_list_add_mem (addr, 4))
4190 if (record_arch_list_add_mem (addr, 8))
4195 if (record_arch_list_add_mem (addr, 2))
4201 switch (ir.reg >> 4)
4205 if (record_arch_list_add_mem (addr, 4))
4209 if (record_arch_list_add_mem (addr, 8))
4214 if (record_arch_list_add_mem (addr, 2))
4231 if (record_arch_list_add_mem (addr, 28))
4236 if (record_arch_list_add_mem (addr, 14))
4242 if (record_arch_list_add_mem (addr, 2))
4247 if (record_arch_list_add_mem (addr, 10))
4253 if (record_arch_list_add_mem (addr, 28))
4259 if (record_arch_list_add_mem (addr, 14))
4263 if (record_arch_list_add_mem (addr, 80))
4267 if (record_arch_list_add_mem (addr, 8))
4272 opcode = opcode << 8 | ir.modrm;
4292 if ((opcode & 1) == 0)
4295 ir.ot = ir.dflag + OT_WORD;
4296 if (opcode == 0xa4 || opcode == 0xa5)
4298 if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM))
4301 if (record_arch_list_add_reg (ir.regcache, I386_EDI_REGNUM))
4304 regcache_raw_read (ir.regcache, I386_EDI_REGNUM,
4305 (gdb_byte *) & addr);
4309 /* addr += ((uint32_t)read_register (I386_ES_REGNUM)) << 4; */
4311 printf_unfiltered (_("Process record ignores the memory change "
4312 "of instruction at address %s because "
4313 "it can't get the value of the segment "
4315 paddress (gdbarch, ir.addr));
4318 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
4322 regcache_raw_read (ir.regcache, I386_ECX_REGNUM,
4323 (gdb_byte *) & count);
4327 regcache_raw_read (ir.regcache, I386_EFLAGS_REGNUM,
4328 (gdb_byte *) & tmpu32);
4329 if ((tmpu32 >> 10) & 0x1)
4330 addr -= (count - 1) * (1 << ir.ot);
4334 if (record_arch_list_add_mem (addr, count * (1 << ir.ot)))
4338 if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
4345 if (record_arch_list_add_mem (addr, 1 << ir.ot))
4355 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
4357 if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM))
4359 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
4361 if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
4369 if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM))
4371 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
4373 if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
4381 if (record_arch_list_add_reg (ir.regcache, I386_EDI_REGNUM))
4383 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
4385 if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
4388 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4395 if (record_arch_list_add_reg (ir.regcache, I386_EDI_REGNUM))
4397 if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM))
4399 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
4401 if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
4404 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4413 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
4432 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
4434 if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM))
4440 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
4442 if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM))
4444 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4450 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
4452 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
4453 (gdb_byte *) & tmpu32);
4454 if (record_arch_list_add_mem
4455 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1))))
4461 if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM))
4463 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
4465 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
4466 (gdb_byte *) & tmpu32);
4467 if (record_arch_list_add_mem
4468 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 2)), (1 << (ir.dflag + 2))))
4532 if (i386_record_modrm (&ir))
4536 if (record_arch_list_add_reg (ir.regcache, ir.rm & 0x3))
4541 if (i386_record_lea_modrm (&ir))
4563 if (i386_record_modrm (&ir))
4565 if (ir.dflag == OT_BYTE)
4567 if (record_arch_list_add_reg (ir.regcache, ir.reg & 0x3))
4574 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
4576 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
4577 (gdb_byte *) & tmpu32);
4578 if (record_arch_list_add_mem
4579 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1))))
4585 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
4587 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4603 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4609 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
4613 /* bit operations */
4614 /* bt/bts/btr/btc Gv, im */
4622 ir.ot = ir.dflag + OT_WORD;
4623 if (i386_record_modrm (&ir))
4628 opcode = opcode << 8 | ir.modrm;
4636 if (i386_record_lea_modrm (&ir))
4641 if (record_arch_list_add_reg (ir.regcache, ir.rm))
4645 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4651 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4659 if (record_arch_list_add_reg (ir.regcache, ir.reg))
4661 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4678 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
4680 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4687 if (prefixes & PREFIX_LOCK)
4697 printf_unfiltered (_("Process record doesn't support instruction "
4706 printf_unfiltered (_("Process record doesn't support instruction "
4717 if (target_read_memory (ir.addr, &tmpu8, 1))
4720 printf_unfiltered (_("Process record: error reading memory "
4721 "at addr %s len = 1.\n"),
4722 paddress (gdbarch, ir.addr));
4727 || gdbarch_tdep (gdbarch)->i386_intx80_record == NULL)
4729 printf_unfiltered (_("Process record doesn't support "
4730 "instruction int 0x%02x.\n"),
4735 ret = gdbarch_tdep (gdbarch)->i386_intx80_record (ir.regcache);
4744 printf_unfiltered (_("Process record doesn't support "
4745 "instruction into.\n"));
4758 printf_unfiltered (_("Process record doesn't support "
4759 "instruction bound.\n"));
4773 if (record_arch_list_add_reg (ir.regcache, opcode & 7))
4779 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
4781 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4793 if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
4799 printf_unfiltered (_("Process record doesn't support "
4800 "instruction wrmsr.\n"));
4807 printf_unfiltered (_("Process record doesn't support "
4808 "instruction rdmsr.\n"));
4815 printf_unfiltered (_("Process record doesn't support "
4816 "instruction rdtsc.\n"));
4825 if (gdbarch_tdep (gdbarch)->i386_sysenter_record == NULL)
4827 printf_unfiltered (_("Process record doesn't support "
4828 "instruction sysenter.\n"));
4832 ret = gdbarch_tdep (gdbarch)->i386_sysenter_record (ir.regcache);
4840 printf_unfiltered (_("Process record doesn't support "
4841 "instruction sysexit.\n"));
4848 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
4850 if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
4852 if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM))
4854 if (record_arch_list_add_reg (ir.regcache, I386_EBX_REGNUM))
4860 printf_unfiltered (_("Process record doesn't support "
4861 "instruction hlt.\n"));
4867 if (i386_record_modrm (&ir))
4877 if (record_arch_list_add_reg (ir.regcache, ir.rm))
4883 if (i386_record_lea_modrm (&ir))
4896 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4901 opcode = opcode << 8 | ir.modrm;
4908 if (i386_record_modrm (&ir))
4920 opcode = opcode << 8 | ir.modrm;
4927 printf_unfiltered (_("Process record ignores the memory "
4928 "change of instruction at "
4929 "address %s because it can't get "
4930 "the value of the segment "
4932 paddress (gdbarch, ir.addr));
4936 if (i386_record_lea_modrm_addr (&ir, &addr))
4938 if (record_arch_list_add_mem (addr, 2))
4941 if (record_arch_list_add_mem (addr, 4))
4956 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4961 opcode = opcode << 8 | ir.modrm;
4972 printf_unfiltered (_("Process record ignores the memory "
4973 "change of instruction at "
4974 "address %s because it can't get "
4975 "the value of the segment "
4977 paddress (gdbarch, ir.addr));
4983 if (i386_record_lea_modrm_addr (&ir, &addr))
4985 if (record_arch_list_add_mem (addr, 2))
4988 if (record_arch_list_add_mem (addr, 4))
5003 opcode = opcode << 8 | ir.modrm;
5011 if (record_arch_list_add_reg (ir.regcache, ir.rm))
5017 if (i386_record_lea_modrm (&ir))
5035 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
5036 if (i386_record_modrm (&ir))
5040 if (i386_record_lea_modrm (&ir))
5045 if (record_arch_list_add_reg (ir.regcache, ir.rm))
5048 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
5056 if (i386_record_modrm (&ir))
5058 if (record_arch_list_add_reg (ir.regcache, ir.reg))
5060 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
5067 /* nop (multi byte) */
5081 if (i386_record_modrm (&ir))
5083 if ((ir.modrm & 0xc0) != 0xc0)
5086 opcode = opcode << 8 | ir.modrm;
5101 if (record_arch_list_add_reg (ir.regcache, ir.rm))
5107 opcode = opcode << 8 | ir.modrm;
5117 if (i386_record_modrm (&ir))
5119 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
5120 || ir.reg == 5 || ir.reg >= 8)
5123 opcode = opcode << 8 | ir.modrm;
5131 if (record_arch_list_add_reg (ir.regcache, ir.rm))
5140 /* MMX/SSE/SSE2/PNI support */
5152 /* In the future, Maybe still need to deal with need_dasm */
5153 if (record_arch_list_add_reg (ir.regcache, I386_EIP_REGNUM))
5155 if (record_arch_list_add_end ())
5161 printf_unfiltered (_("Process record doesn't support instruction 0x%02x "
5162 "at address %s.\n"),
5163 (unsigned int) (opcode), paddress (gdbarch, ir.addr));
5168 static struct gdbarch *
5169 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
5171 struct gdbarch_tdep *tdep;
5172 struct gdbarch *gdbarch;
5174 /* If there is already a candidate, use it. */
5175 arches = gdbarch_list_lookup_by_info (arches, &info);
5177 return arches->gdbarch;
5179 /* Allocate space for the new architecture. */
5180 tdep = XCALLOC (1, struct gdbarch_tdep);
5181 gdbarch = gdbarch_alloc (&info, tdep);
5183 /* General-purpose registers. */
5184 tdep->gregset = NULL;
5185 tdep->gregset_reg_offset = NULL;
5186 tdep->gregset_num_regs = I386_NUM_GREGS;
5187 tdep->sizeof_gregset = 0;
5189 /* Floating-point registers. */
5190 tdep->fpregset = NULL;
5191 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
5193 /* The default settings include the FPU registers, the MMX registers
5194 and the SSE registers. This can be overridden for a specific ABI
5195 by adjusting the members `st0_regnum', `mm0_regnum' and
5196 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
5197 will show up in the output of "info all-registers". Ideally we
5198 should try to autodetect whether they are available, such that we
5199 can prevent "info all-registers" from displaying registers that
5202 NOTE: kevinb/2003-07-13: ... if it's a choice between printing
5203 [the SSE registers] always (even when they don't exist) or never
5204 showing them to the user (even when they do exist), I prefer the
5205 former over the latter. */
5207 tdep->st0_regnum = I386_ST0_REGNUM;
5209 /* The MMX registers are implemented as pseudo-registers. Put off
5210 calculating the register number for %mm0 until we know the number
5211 of raw registers. */
5212 tdep->mm0_regnum = 0;
5214 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
5215 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
5217 tdep->jb_pc_offset = -1;
5218 tdep->struct_return = pcc_struct_return;
5219 tdep->sigtramp_start = 0;
5220 tdep->sigtramp_end = 0;
5221 tdep->sigtramp_p = i386_sigtramp_p;
5222 tdep->sigcontext_addr = NULL;
5223 tdep->sc_reg_offset = NULL;
5224 tdep->sc_pc_offset = -1;
5225 tdep->sc_sp_offset = -1;
5227 /* The format used for `long double' on almost all i386 targets is
5228 the i387 extended floating-point format. In fact, of all targets
5229 in the GCC 2.95 tree, only OSF/1 does it different, and insists
5230 on having a `long double' that's not `long' at all. */
5231 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
5233 /* Although the i387 extended floating-point has only 80 significant
5234 bits, a `long double' actually takes up 96, probably to enforce
5236 set_gdbarch_long_double_bit (gdbarch, 96);
5238 /* The default ABI includes general-purpose registers,
5239 floating-point registers, and the SSE registers. */
5240 set_gdbarch_num_regs (gdbarch, I386_SSE_NUM_REGS);
5241 set_gdbarch_register_name (gdbarch, i386_register_name);
5242 set_gdbarch_register_type (gdbarch, i386_register_type);
5244 /* Register numbers of various important registers. */
5245 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
5246 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
5247 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
5248 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
5250 /* NOTE: kettenis/20040418: GCC does have two possible register
5251 numbering schemes on the i386: dbx and SVR4. These schemes
5252 differ in how they number %ebp, %esp, %eflags, and the
5253 floating-point registers, and are implemented by the arrays
5254 dbx_register_map[] and svr4_dbx_register_map in
5255 gcc/config/i386.c. GCC also defines a third numbering scheme in
5256 gcc/config/i386.c, which it designates as the "default" register
5257 map used in 64bit mode. This last register numbering scheme is
5258 implemented in dbx64_register_map, and is used for AMD64; see
5261 Currently, each GCC i386 target always uses the same register
5262 numbering scheme across all its supported debugging formats
5263 i.e. SDB (COFF), stabs and DWARF 2. This is because
5264 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
5265 DBX_REGISTER_NUMBER macro which is defined by each target's
5266 respective config header in a manner independent of the requested
5267 output debugging format.
5269 This does not match the arrangement below, which presumes that
5270 the SDB and stabs numbering schemes differ from the DWARF and
5271 DWARF 2 ones. The reason for this arrangement is that it is
5272 likely to get the numbering scheme for the target's
5273 default/native debug format right. For targets where GCC is the
5274 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
5275 targets where the native toolchain uses a different numbering
5276 scheme for a particular debug format (stabs-in-ELF on Solaris)
5277 the defaults below will have to be overridden, like
5278 i386_elf_init_abi() does. */
5280 /* Use the dbx register numbering scheme for stabs and COFF. */
5281 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
5282 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
5284 /* Use the SVR4 register numbering scheme for DWARF 2. */
5285 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
5287 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
5288 be in use on any of the supported i386 targets. */
5290 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
5292 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
5294 /* Call dummy code. */
5295 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
5297 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
5298 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
5299 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
5301 set_gdbarch_return_value (gdbarch, i386_return_value);
5303 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
5305 /* Stack grows downward. */
5306 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
5308 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc);
5309 set_gdbarch_decr_pc_after_break (gdbarch, 1);
5310 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
5312 set_gdbarch_frame_args_skip (gdbarch, 8);
5314 /* Wire in the MMX registers. */
5315 set_gdbarch_num_pseudo_regs (gdbarch, i386_num_mmx_regs);
5316 set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read);
5317 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
5319 set_gdbarch_print_insn (gdbarch, i386_print_insn);
5321 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
5323 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
5325 /* Add the i386 register groups. */
5326 i386_add_reggroups (gdbarch);
5327 set_gdbarch_register_reggroup_p (gdbarch, i386_register_reggroup_p);
5329 /* Helper for function argument information. */
5330 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
5332 /* Hook in the DWARF CFI frame unwinder. */
5333 dwarf2_append_unwinders (gdbarch);
5335 frame_base_set_default (gdbarch, &i386_frame_base);
5337 /* Hook in ABI-specific overrides, if they have been registered. */
5338 gdbarch_init_osabi (info, gdbarch);
5340 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
5341 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
5343 /* If we have a register mapping, enable the generic core file
5344 support, unless it has already been enabled. */
5345 if (tdep->gregset_reg_offset
5346 && !gdbarch_regset_from_core_section_p (gdbarch))
5347 set_gdbarch_regset_from_core_section (gdbarch,
5348 i386_regset_from_core_section);
5350 /* Unless support for MMX has been disabled, make %mm0 the first
5352 if (tdep->mm0_regnum == 0)
5353 tdep->mm0_regnum = gdbarch_num_regs (gdbarch);
5355 set_gdbarch_skip_permanent_breakpoint (gdbarch,
5356 i386_skip_permanent_breakpoint);
5361 static enum gdb_osabi
5362 i386_coff_osabi_sniffer (bfd *abfd)
5364 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
5365 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
5366 return GDB_OSABI_GO32;
5368 return GDB_OSABI_UNKNOWN;
5372 /* Provide a prototype to silence -Wmissing-prototypes. */
5373 void _initialize_i386_tdep (void);
5376 _initialize_i386_tdep (void)
5378 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
5380 /* Add the variable that controls the disassembly flavor. */
5381 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
5382 &disassembly_flavor, _("\
5383 Set the disassembly flavor."), _("\
5384 Show the disassembly flavor."), _("\
5385 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
5387 NULL, /* FIXME: i18n: */
5388 &setlist, &showlist);
5390 /* Add the variable that controls the convention for returning
5392 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
5393 &struct_convention, _("\
5394 Set the convention for returning small structs."), _("\
5395 Show the convention for returning small structs."), _("\
5396 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
5399 NULL, /* FIXME: i18n: */
5400 &setlist, &showlist);
5402 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
5403 i386_coff_osabi_sniffer);
5405 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
5406 i386_svr4_init_abi);
5407 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
5408 i386_go32_init_abi);
5410 /* Initialize the i386-specific register groups. */
5411 i386_init_reggroups ();