1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010, 2011 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
48 #include "exceptions.h"
49 #include "gdb_assert.h"
50 #include "gdb_string.h"
52 #include "i386-tdep.h"
53 #include "i387-tdep.h"
54 #include "i386-xstate.h"
59 #include "features/i386/i386.c"
60 #include "features/i386/i386-avx.c"
61 #include "features/i386/i386-mmx.c"
65 static const char *i386_register_names[] =
67 "eax", "ecx", "edx", "ebx",
68 "esp", "ebp", "esi", "edi",
69 "eip", "eflags", "cs", "ss",
70 "ds", "es", "fs", "gs",
71 "st0", "st1", "st2", "st3",
72 "st4", "st5", "st6", "st7",
73 "fctrl", "fstat", "ftag", "fiseg",
74 "fioff", "foseg", "fooff", "fop",
75 "xmm0", "xmm1", "xmm2", "xmm3",
76 "xmm4", "xmm5", "xmm6", "xmm7",
80 static const char *i386_ymm_names[] =
82 "ymm0", "ymm1", "ymm2", "ymm3",
83 "ymm4", "ymm5", "ymm6", "ymm7",
86 static const char *i386_ymmh_names[] =
88 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
89 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
92 /* Register names for MMX pseudo-registers. */
94 static const char *i386_mmx_names[] =
96 "mm0", "mm1", "mm2", "mm3",
97 "mm4", "mm5", "mm6", "mm7"
100 /* Register names for byte pseudo-registers. */
102 static const char *i386_byte_names[] =
104 "al", "cl", "dl", "bl",
105 "ah", "ch", "dh", "bh"
108 /* Register names for word pseudo-registers. */
110 static const char *i386_word_names[] =
112 "ax", "cx", "dx", "bx",
119 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
121 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
122 int mm0_regnum = tdep->mm0_regnum;
127 regnum -= mm0_regnum;
128 return regnum >= 0 && regnum < tdep->num_mmx_regs;
134 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
136 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
138 regnum -= tdep->al_regnum;
139 return regnum >= 0 && regnum < tdep->num_byte_regs;
145 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
147 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
149 regnum -= tdep->ax_regnum;
150 return regnum >= 0 && regnum < tdep->num_word_regs;
153 /* Dword register? */
156 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
158 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
159 int eax_regnum = tdep->eax_regnum;
164 regnum -= eax_regnum;
165 return regnum >= 0 && regnum < tdep->num_dword_regs;
169 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
171 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
172 int ymm0h_regnum = tdep->ymm0h_regnum;
174 if (ymm0h_regnum < 0)
177 regnum -= ymm0h_regnum;
178 return regnum >= 0 && regnum < tdep->num_ymm_regs;
184 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
186 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
187 int ymm0_regnum = tdep->ymm0_regnum;
192 regnum -= ymm0_regnum;
193 return regnum >= 0 && regnum < tdep->num_ymm_regs;
199 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
201 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
202 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
204 if (num_xmm_regs == 0)
207 regnum -= I387_XMM0_REGNUM (tdep);
208 return regnum >= 0 && regnum < num_xmm_regs;
212 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
214 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
216 if (I387_NUM_XMM_REGS (tdep) == 0)
219 return (regnum == I387_MXCSR_REGNUM (tdep));
225 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
227 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
229 if (I387_ST0_REGNUM (tdep) < 0)
232 return (I387_ST0_REGNUM (tdep) <= regnum
233 && regnum < I387_FCTRL_REGNUM (tdep));
237 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
239 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
241 if (I387_ST0_REGNUM (tdep) < 0)
244 return (I387_FCTRL_REGNUM (tdep) <= regnum
245 && regnum < I387_XMM0_REGNUM (tdep));
248 /* Return the name of register REGNUM, or the empty string if it is
249 an anonymous register. */
252 i386_register_name (struct gdbarch *gdbarch, int regnum)
254 /* Hide the upper YMM registers. */
255 if (i386_ymmh_regnum_p (gdbarch, regnum))
258 return tdesc_register_name (gdbarch, regnum);
261 /* Return the name of register REGNUM. */
264 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
266 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
267 if (i386_mmx_regnum_p (gdbarch, regnum))
268 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
269 else if (i386_ymm_regnum_p (gdbarch, regnum))
270 return i386_ymm_names[regnum - tdep->ymm0_regnum];
271 else if (i386_byte_regnum_p (gdbarch, regnum))
272 return i386_byte_names[regnum - tdep->al_regnum];
273 else if (i386_word_regnum_p (gdbarch, regnum))
274 return i386_word_names[regnum - tdep->ax_regnum];
276 internal_error (__FILE__, __LINE__, _("invalid regnum"));
279 /* Convert a dbx register number REG to the appropriate register
280 number used by GDB. */
283 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
285 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
287 /* This implements what GCC calls the "default" register map
288 (dbx_register_map[]). */
290 if (reg >= 0 && reg <= 7)
292 /* General-purpose registers. The debug info calls %ebp
293 register 4, and %esp register 5. */
300 else if (reg >= 12 && reg <= 19)
302 /* Floating-point registers. */
303 return reg - 12 + I387_ST0_REGNUM (tdep);
305 else if (reg >= 21 && reg <= 28)
308 int ymm0_regnum = tdep->ymm0_regnum;
311 && i386_xmm_regnum_p (gdbarch, reg))
312 return reg - 21 + ymm0_regnum;
314 return reg - 21 + I387_XMM0_REGNUM (tdep);
316 else if (reg >= 29 && reg <= 36)
319 return reg - 29 + I387_MM0_REGNUM (tdep);
322 /* This will hopefully provoke a warning. */
323 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
326 /* Convert SVR4 register number REG to the appropriate register number
330 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
332 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
334 /* This implements the GCC register map that tries to be compatible
335 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
337 /* The SVR4 register numbering includes %eip and %eflags, and
338 numbers the floating point registers differently. */
339 if (reg >= 0 && reg <= 9)
341 /* General-purpose registers. */
344 else if (reg >= 11 && reg <= 18)
346 /* Floating-point registers. */
347 return reg - 11 + I387_ST0_REGNUM (tdep);
349 else if (reg >= 21 && reg <= 36)
351 /* The SSE and MMX registers have the same numbers as with dbx. */
352 return i386_dbx_reg_to_regnum (gdbarch, reg);
357 case 37: return I387_FCTRL_REGNUM (tdep);
358 case 38: return I387_FSTAT_REGNUM (tdep);
359 case 39: return I387_MXCSR_REGNUM (tdep);
360 case 40: return I386_ES_REGNUM;
361 case 41: return I386_CS_REGNUM;
362 case 42: return I386_SS_REGNUM;
363 case 43: return I386_DS_REGNUM;
364 case 44: return I386_FS_REGNUM;
365 case 45: return I386_GS_REGNUM;
368 /* This will hopefully provoke a warning. */
369 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
374 /* This is the variable that is set with "set disassembly-flavor", and
375 its legitimate values. */
376 static const char att_flavor[] = "att";
377 static const char intel_flavor[] = "intel";
378 static const char *valid_flavors[] =
384 static const char *disassembly_flavor = att_flavor;
387 /* Use the program counter to determine the contents and size of a
388 breakpoint instruction. Return a pointer to a string of bytes that
389 encode a breakpoint instruction, store the length of the string in
390 *LEN and optionally adjust *PC to point to the correct memory
391 location for inserting the breakpoint.
393 On the i386 we have a single breakpoint that fits in a single byte
394 and can be inserted anywhere.
396 This function is 64-bit safe. */
398 static const gdb_byte *
399 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
401 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */
403 *len = sizeof (break_insn);
407 /* Displaced instruction handling. */
409 /* Skip the legacy instruction prefixes in INSN.
410 Not all prefixes are valid for any particular insn
411 but we needn't care, the insn will fault if it's invalid.
412 The result is a pointer to the first opcode byte,
413 or NULL if we run off the end of the buffer. */
416 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
418 gdb_byte *end = insn + max_len;
424 case DATA_PREFIX_OPCODE:
425 case ADDR_PREFIX_OPCODE:
426 case CS_PREFIX_OPCODE:
427 case DS_PREFIX_OPCODE:
428 case ES_PREFIX_OPCODE:
429 case FS_PREFIX_OPCODE:
430 case GS_PREFIX_OPCODE:
431 case SS_PREFIX_OPCODE:
432 case LOCK_PREFIX_OPCODE:
433 case REPE_PREFIX_OPCODE:
434 case REPNE_PREFIX_OPCODE:
446 i386_absolute_jmp_p (const gdb_byte *insn)
448 /* jmp far (absolute address in operand). */
454 /* jump near, absolute indirect (/4). */
455 if ((insn[1] & 0x38) == 0x20)
458 /* jump far, absolute indirect (/5). */
459 if ((insn[1] & 0x38) == 0x28)
467 i386_absolute_call_p (const gdb_byte *insn)
469 /* call far, absolute. */
475 /* Call near, absolute indirect (/2). */
476 if ((insn[1] & 0x38) == 0x10)
479 /* Call far, absolute indirect (/3). */
480 if ((insn[1] & 0x38) == 0x18)
488 i386_ret_p (const gdb_byte *insn)
492 case 0xc2: /* ret near, pop N bytes. */
493 case 0xc3: /* ret near */
494 case 0xca: /* ret far, pop N bytes. */
495 case 0xcb: /* ret far */
496 case 0xcf: /* iret */
505 i386_call_p (const gdb_byte *insn)
507 if (i386_absolute_call_p (insn))
510 /* call near, relative. */
517 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
518 length in bytes. Otherwise, return zero. */
521 i386_syscall_p (const gdb_byte *insn, int *lengthp)
532 /* Some kernels may run one past a syscall insn, so we have to cope.
533 Otherwise this is just simple_displaced_step_copy_insn. */
535 struct displaced_step_closure *
536 i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
537 CORE_ADDR from, CORE_ADDR to,
538 struct regcache *regs)
540 size_t len = gdbarch_max_insn_length (gdbarch);
541 gdb_byte *buf = xmalloc (len);
543 read_memory (from, buf, len);
545 /* GDB may get control back after the insn after the syscall.
546 Presumably this is a kernel bug.
547 If this is a syscall, make sure there's a nop afterwards. */
552 insn = i386_skip_prefixes (buf, len);
553 if (insn != NULL && i386_syscall_p (insn, &syscall_length))
554 insn[syscall_length] = NOP_OPCODE;
557 write_memory (to, buf, len);
561 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
562 paddress (gdbarch, from), paddress (gdbarch, to));
563 displaced_step_dump_bytes (gdb_stdlog, buf, len);
566 return (struct displaced_step_closure *) buf;
569 /* Fix up the state of registers and memory after having single-stepped
570 a displaced instruction. */
573 i386_displaced_step_fixup (struct gdbarch *gdbarch,
574 struct displaced_step_closure *closure,
575 CORE_ADDR from, CORE_ADDR to,
576 struct regcache *regs)
578 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
580 /* The offset we applied to the instruction's address.
581 This could well be negative (when viewed as a signed 32-bit
582 value), but ULONGEST won't reflect that, so take care when
584 ULONGEST insn_offset = to - from;
586 /* Since we use simple_displaced_step_copy_insn, our closure is a
587 copy of the instruction. */
588 gdb_byte *insn = (gdb_byte *) closure;
589 /* The start of the insn, needed in case we see some prefixes. */
590 gdb_byte *insn_start = insn;
593 fprintf_unfiltered (gdb_stdlog,
594 "displaced: fixup (%s, %s), "
595 "insn = 0x%02x 0x%02x ...\n",
596 paddress (gdbarch, from), paddress (gdbarch, to),
599 /* The list of issues to contend with here is taken from
600 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
601 Yay for Free Software! */
603 /* Relocate the %eip, if necessary. */
605 /* The instruction recognizers we use assume any leading prefixes
606 have been skipped. */
608 /* This is the size of the buffer in closure. */
609 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
610 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
611 /* If there are too many prefixes, just ignore the insn.
612 It will fault when run. */
617 /* Except in the case of absolute or indirect jump or call
618 instructions, or a return instruction, the new eip is relative to
619 the displaced instruction; make it relative. Well, signal
620 handler returns don't need relocation either, but we use the
621 value of %eip to recognize those; see below. */
622 if (! i386_absolute_jmp_p (insn)
623 && ! i386_absolute_call_p (insn)
624 && ! i386_ret_p (insn))
629 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
631 /* A signal trampoline system call changes the %eip, resuming
632 execution of the main program after the signal handler has
633 returned. That makes them like 'return' instructions; we
634 shouldn't relocate %eip.
636 But most system calls don't, and we do need to relocate %eip.
638 Our heuristic for distinguishing these cases: if stepping
639 over the system call instruction left control directly after
640 the instruction, the we relocate --- control almost certainly
641 doesn't belong in the displaced copy. Otherwise, we assume
642 the instruction has put control where it belongs, and leave
643 it unrelocated. Goodness help us if there are PC-relative
645 if (i386_syscall_p (insn, &insn_len)
646 && orig_eip != to + (insn - insn_start) + insn_len
647 /* GDB can get control back after the insn after the syscall.
648 Presumably this is a kernel bug.
649 i386_displaced_step_copy_insn ensures its a nop,
650 we add one to the length for it. */
651 && orig_eip != to + (insn - insn_start) + insn_len + 1)
654 fprintf_unfiltered (gdb_stdlog,
655 "displaced: syscall changed %%eip; "
660 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
662 /* If we just stepped over a breakpoint insn, we don't backup
663 the pc on purpose; this is to match behaviour without
666 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
669 fprintf_unfiltered (gdb_stdlog,
671 "relocated %%eip from %s to %s\n",
672 paddress (gdbarch, orig_eip),
673 paddress (gdbarch, eip));
677 /* If the instruction was PUSHFL, then the TF bit will be set in the
678 pushed value, and should be cleared. We'll leave this for later,
679 since GDB already messes up the TF flag when stepping over a
682 /* If the instruction was a call, the return address now atop the
683 stack is the address following the copied instruction. We need
684 to make it the address following the original instruction. */
685 if (i386_call_p (insn))
689 const ULONGEST retaddr_len = 4;
691 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
692 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
693 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
694 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
697 fprintf_unfiltered (gdb_stdlog,
698 "displaced: relocated return addr at %s to %s\n",
699 paddress (gdbarch, esp),
700 paddress (gdbarch, retaddr));
705 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
707 target_write_memory (*to, buf, len);
712 i386_relocate_instruction (struct gdbarch *gdbarch,
713 CORE_ADDR *to, CORE_ADDR oldloc)
715 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
716 gdb_byte buf[I386_MAX_INSN_LEN];
717 int offset = 0, rel32, newrel;
719 gdb_byte *insn = buf;
721 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
723 insn_length = gdb_buffered_insn_length (gdbarch, insn,
724 I386_MAX_INSN_LEN, oldloc);
726 /* Get past the prefixes. */
727 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
729 /* Adjust calls with 32-bit relative addresses as push/jump, with
730 the address pushed being the location where the original call in
731 the user program would return to. */
734 gdb_byte push_buf[16];
735 unsigned int ret_addr;
737 /* Where "ret" in the original code will return to. */
738 ret_addr = oldloc + insn_length;
739 push_buf[0] = 0x68; /* pushq $... */
740 memcpy (&push_buf[1], &ret_addr, 4);
742 append_insns (to, 5, push_buf);
744 /* Convert the relative call to a relative jump. */
747 /* Adjust the destination offset. */
748 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
749 newrel = (oldloc - *to) + rel32;
750 store_signed_integer (insn + 1, 4, byte_order, newrel);
753 fprintf_unfiltered (gdb_stdlog,
754 "Adjusted insn rel32=%s at %s to"
756 hex_string (rel32), paddress (gdbarch, oldloc),
757 hex_string (newrel), paddress (gdbarch, *to));
759 /* Write the adjusted jump into its displaced location. */
760 append_insns (to, 5, insn);
764 /* Adjust jumps with 32-bit relative addresses. Calls are already
768 /* Adjust conditional jumps. */
769 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
774 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
775 newrel = (oldloc - *to) + rel32;
776 store_signed_integer (insn + offset, 4, byte_order, newrel);
778 fprintf_unfiltered (gdb_stdlog,
779 "Adjusted insn rel32=%s at %s to"
781 hex_string (rel32), paddress (gdbarch, oldloc),
782 hex_string (newrel), paddress (gdbarch, *to));
785 /* Write the adjusted instructions into their displaced
787 append_insns (to, insn_length, buf);
791 #ifdef I386_REGNO_TO_SYMMETRY
792 #error "The Sequent Symmetry is no longer supported."
795 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
796 and %esp "belong" to the calling function. Therefore these
797 registers should be saved if they're going to be modified. */
799 /* The maximum number of saved registers. This should include all
800 registers mentioned above, and %eip. */
801 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
803 struct i386_frame_cache
811 /* Saved registers. */
812 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
817 /* Stack space reserved for local variables. */
821 /* Allocate and initialize a frame cache. */
823 static struct i386_frame_cache *
824 i386_alloc_frame_cache (void)
826 struct i386_frame_cache *cache;
829 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
834 cache->sp_offset = -4;
837 /* Saved registers. We initialize these to -1 since zero is a valid
838 offset (that's where %ebp is supposed to be stored). */
839 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
840 cache->saved_regs[i] = -1;
842 cache->saved_sp_reg = -1;
843 cache->pc_in_eax = 0;
845 /* Frameless until proven otherwise. */
851 /* If the instruction at PC is a jump, return the address of its
852 target. Otherwise, return PC. */
855 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
857 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
862 if (target_read_memory (pc, &op, 1))
868 op = read_memory_unsigned_integer (pc + 1, 1, byte_order);
874 /* Relative jump: if data16 == 0, disp32, else disp16. */
877 delta = read_memory_integer (pc + 2, 2, byte_order);
879 /* Include the size of the jmp instruction (including the
885 delta = read_memory_integer (pc + 1, 4, byte_order);
887 /* Include the size of the jmp instruction. */
892 /* Relative jump, disp8 (ignore data16). */
893 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
902 /* Check whether PC points at a prologue for a function returning a
903 structure or union. If so, it updates CACHE and returns the
904 address of the first instruction after the code sequence that
905 removes the "hidden" argument from the stack or CURRENT_PC,
906 whichever is smaller. Otherwise, return PC. */
909 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
910 struct i386_frame_cache *cache)
912 /* Functions that return a structure or union start with:
915 xchgl %eax, (%esp) 0x87 0x04 0x24
916 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
918 (the System V compiler puts out the second `xchg' instruction,
919 and the assembler doesn't try to optimize it, so the 'sib' form
920 gets generated). This sequence is used to get the address of the
921 return buffer for a function that returns a structure. */
922 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
923 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
927 if (current_pc <= pc)
930 if (target_read_memory (pc, &op, 1))
933 if (op != 0x58) /* popl %eax */
936 if (target_read_memory (pc + 1, buf, 4))
939 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
942 if (current_pc == pc)
944 cache->sp_offset += 4;
948 if (current_pc == pc + 1)
950 cache->pc_in_eax = 1;
954 if (buf[1] == proto1[1])
961 i386_skip_probe (CORE_ADDR pc)
963 /* A function may start with
977 if (target_read_memory (pc, &op, 1))
980 if (op == 0x68 || op == 0x6a)
984 /* Skip past the `pushl' instruction; it has either a one-byte or a
985 four-byte operand, depending on the opcode. */
991 /* Read the following 8 bytes, which should be `call _probe' (6
992 bytes) followed by `addl $4,%esp' (2 bytes). */
993 read_memory (pc + delta, buf, sizeof (buf));
994 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
995 pc += delta + sizeof (buf);
1001 /* GCC 4.1 and later, can put code in the prologue to realign the
1002 stack pointer. Check whether PC points to such code, and update
1003 CACHE accordingly. Return the first instruction after the code
1004 sequence or CURRENT_PC, whichever is smaller. If we don't
1005 recognize the code, return PC. */
1008 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1009 struct i386_frame_cache *cache)
1011 /* There are 2 code sequences to re-align stack before the frame
1014 1. Use a caller-saved saved register:
1020 2. Use a callee-saved saved register:
1027 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1029 0x83 0xe4 0xf0 andl $-16, %esp
1030 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1035 int offset, offset_and;
1036 static int regnums[8] = {
1037 I386_EAX_REGNUM, /* %eax */
1038 I386_ECX_REGNUM, /* %ecx */
1039 I386_EDX_REGNUM, /* %edx */
1040 I386_EBX_REGNUM, /* %ebx */
1041 I386_ESP_REGNUM, /* %esp */
1042 I386_EBP_REGNUM, /* %ebp */
1043 I386_ESI_REGNUM, /* %esi */
1044 I386_EDI_REGNUM /* %edi */
1047 if (target_read_memory (pc, buf, sizeof buf))
1050 /* Check caller-saved saved register. The first instruction has
1051 to be "leal 4(%esp), %reg". */
1052 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1054 /* MOD must be binary 10 and R/M must be binary 100. */
1055 if ((buf[1] & 0xc7) != 0x44)
1058 /* REG has register number. */
1059 reg = (buf[1] >> 3) & 7;
1064 /* Check callee-saved saved register. The first instruction
1065 has to be "pushl %reg". */
1066 if ((buf[0] & 0xf8) != 0x50)
1072 /* The next instruction has to be "leal 8(%esp), %reg". */
1073 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1076 /* MOD must be binary 10 and R/M must be binary 100. */
1077 if ((buf[2] & 0xc7) != 0x44)
1080 /* REG has register number. Registers in pushl and leal have to
1082 if (reg != ((buf[2] >> 3) & 7))
1088 /* Rigister can't be %esp nor %ebp. */
1089 if (reg == 4 || reg == 5)
1092 /* The next instruction has to be "andl $-XXX, %esp". */
1093 if (buf[offset + 1] != 0xe4
1094 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1097 offset_and = offset;
1098 offset += buf[offset] == 0x81 ? 6 : 3;
1100 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1101 0xfc. REG must be binary 110 and MOD must be binary 01. */
1102 if (buf[offset] != 0xff
1103 || buf[offset + 2] != 0xfc
1104 || (buf[offset + 1] & 0xf8) != 0x70)
1107 /* R/M has register. Registers in leal and pushl have to be the
1109 if (reg != (buf[offset + 1] & 7))
1112 if (current_pc > pc + offset_and)
1113 cache->saved_sp_reg = regnums[reg];
1115 return min (pc + offset + 3, current_pc);
1118 /* Maximum instruction length we need to handle. */
1119 #define I386_MAX_MATCHED_INSN_LEN 6
1121 /* Instruction description. */
1125 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
1126 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
1129 /* Return whether instruction at PC matches PATTERN. */
1132 i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern)
1136 if (target_read_memory (pc, &op, 1))
1139 if ((op & pattern.mask[0]) == pattern.insn[0])
1141 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1142 int insn_matched = 1;
1145 gdb_assert (pattern.len > 1);
1146 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN);
1148 if (target_read_memory (pc + 1, buf, pattern.len - 1))
1151 for (i = 1; i < pattern.len; i++)
1153 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i])
1156 return insn_matched;
1161 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1162 the first instruction description that matches. Otherwise, return
1165 static struct i386_insn *
1166 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns)
1168 struct i386_insn *pattern;
1170 for (pattern = insn_patterns; pattern->len > 0; pattern++)
1172 if (i386_match_pattern (pc, *pattern))
1179 /* Return whether PC points inside a sequence of instructions that
1180 matches INSN_PATTERNS. */
1183 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns)
1185 CORE_ADDR current_pc;
1188 struct i386_insn *insn;
1190 insn = i386_match_insn (pc, insn_patterns);
1195 ix = insn - insn_patterns;
1196 for (i = ix - 1; i >= 0; i--)
1198 current_pc -= insn_patterns[i].len;
1200 if (!i386_match_pattern (current_pc, insn_patterns[i]))
1204 current_pc = pc + insn->len;
1205 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++)
1207 if (!i386_match_pattern (current_pc, *insn))
1210 current_pc += insn->len;
1216 /* Some special instructions that might be migrated by GCC into the
1217 part of the prologue that sets up the new stack frame. Because the
1218 stack frame hasn't been setup yet, no registers have been saved
1219 yet, and only the scratch registers %eax, %ecx and %edx can be
1222 struct i386_insn i386_frame_setup_skip_insns[] =
1224 /* Check for `movb imm8, r' and `movl imm32, r'.
1226 ??? Should we handle 16-bit operand-sizes here? */
1228 /* `movb imm8, %al' and `movb imm8, %ah' */
1229 /* `movb imm8, %cl' and `movb imm8, %ch' */
1230 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1231 /* `movb imm8, %dl' and `movb imm8, %dh' */
1232 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1233 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1234 { 5, { 0xb8 }, { 0xfe } },
1235 /* `movl imm32, %edx' */
1236 { 5, { 0xba }, { 0xff } },
1238 /* Check for `mov imm32, r32'. Note that there is an alternative
1239 encoding for `mov m32, %eax'.
1241 ??? Should we handle SIB adressing here?
1242 ??? Should we handle 16-bit operand-sizes here? */
1244 /* `movl m32, %eax' */
1245 { 5, { 0xa1 }, { 0xff } },
1246 /* `movl m32, %eax' and `mov; m32, %ecx' */
1247 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1248 /* `movl m32, %edx' */
1249 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1251 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1252 Because of the symmetry, there are actually two ways to encode
1253 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1254 opcode bytes 0x31 and 0x33 for `xorl'. */
1256 /* `subl %eax, %eax' */
1257 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1258 /* `subl %ecx, %ecx' */
1259 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1260 /* `subl %edx, %edx' */
1261 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1262 /* `xorl %eax, %eax' */
1263 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1264 /* `xorl %ecx, %ecx' */
1265 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1266 /* `xorl %edx, %edx' */
1267 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1272 /* Check whether PC points to a no-op instruction. */
1274 i386_skip_noop (CORE_ADDR pc)
1279 if (target_read_memory (pc, &op, 1))
1285 /* Ignore `nop' instruction. */
1289 if (target_read_memory (pc, &op, 1))
1293 /* Ignore no-op instruction `mov %edi, %edi'.
1294 Microsoft system dlls often start with
1295 a `mov %edi,%edi' instruction.
1296 The 5 bytes before the function start are
1297 filled with `nop' instructions.
1298 This pattern can be used for hot-patching:
1299 The `mov %edi, %edi' instruction can be replaced by a
1300 near jump to the location of the 5 `nop' instructions
1301 which can be replaced by a 32-bit jump to anywhere
1302 in the 32-bit address space. */
1304 else if (op == 0x8b)
1306 if (target_read_memory (pc + 1, &op, 1))
1312 if (target_read_memory (pc, &op, 1))
1322 /* Check whether PC points at a code that sets up a new stack frame.
1323 If so, it updates CACHE and returns the address of the first
1324 instruction after the sequence that sets up the frame or LIMIT,
1325 whichever is smaller. If we don't recognize the code, return PC. */
1328 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1329 CORE_ADDR pc, CORE_ADDR limit,
1330 struct i386_frame_cache *cache)
1332 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1333 struct i386_insn *insn;
1340 if (target_read_memory (pc, &op, 1))
1343 if (op == 0x55) /* pushl %ebp */
1345 /* Take into account that we've executed the `pushl %ebp' that
1346 starts this instruction sequence. */
1347 cache->saved_regs[I386_EBP_REGNUM] = 0;
1348 cache->sp_offset += 4;
1351 /* If that's all, return now. */
1355 /* Check for some special instructions that might be migrated by
1356 GCC into the prologue and skip them. At this point in the
1357 prologue, code should only touch the scratch registers %eax,
1358 %ecx and %edx, so while the number of posibilities is sheer,
1361 Make sure we only skip these instructions if we later see the
1362 `movl %esp, %ebp' that actually sets up the frame. */
1363 while (pc + skip < limit)
1365 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1372 /* If that's all, return now. */
1373 if (limit <= pc + skip)
1376 if (target_read_memory (pc + skip, &op, 1))
1379 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1383 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1388 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1396 /* OK, we actually have a frame. We just don't know how large
1397 it is yet. Set its size to zero. We'll adjust it if
1398 necessary. We also now commit to skipping the special
1399 instructions mentioned before. */
1403 /* If that's all, return now. */
1407 /* Check for stack adjustment
1411 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1412 reg, so we don't have to worry about a data16 prefix. */
1413 if (target_read_memory (pc, &op, 1))
1417 /* `subl' with 8-bit immediate. */
1418 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1419 /* Some instruction starting with 0x83 other than `subl'. */
1422 /* `subl' with signed 8-bit immediate (though it wouldn't
1423 make sense to be negative). */
1424 cache->locals = read_memory_integer (pc + 2, 1, byte_order);
1427 else if (op == 0x81)
1429 /* Maybe it is `subl' with a 32-bit immediate. */
1430 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1431 /* Some instruction starting with 0x81 other than `subl'. */
1434 /* It is `subl' with a 32-bit immediate. */
1435 cache->locals = read_memory_integer (pc + 2, 4, byte_order);
1440 /* Some instruction other than `subl'. */
1444 else if (op == 0xc8) /* enter */
1446 cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order);
1453 /* Check whether PC points at code that saves registers on the stack.
1454 If so, it updates CACHE and returns the address of the first
1455 instruction after the register saves or CURRENT_PC, whichever is
1456 smaller. Otherwise, return PC. */
1459 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1460 struct i386_frame_cache *cache)
1462 CORE_ADDR offset = 0;
1466 if (cache->locals > 0)
1467 offset -= cache->locals;
1468 for (i = 0; i < 8 && pc < current_pc; i++)
1470 if (target_read_memory (pc, &op, 1))
1472 if (op < 0x50 || op > 0x57)
1476 cache->saved_regs[op - 0x50] = offset;
1477 cache->sp_offset += 4;
1484 /* Do a full analysis of the prologue at PC and update CACHE
1485 accordingly. Bail out early if CURRENT_PC is reached. Return the
1486 address where the analysis stopped.
1488 We handle these cases:
1490 The startup sequence can be at the start of the function, or the
1491 function can start with a branch to startup code at the end.
1493 %ebp can be set up with either the 'enter' instruction, or "pushl
1494 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1495 once used in the System V compiler).
1497 Local space is allocated just below the saved %ebp by either the
1498 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1499 16-bit unsigned argument for space to allocate, and the 'addl'
1500 instruction could have either a signed byte, or 32-bit immediate.
1502 Next, the registers used by this function are pushed. With the
1503 System V compiler they will always be in the order: %edi, %esi,
1504 %ebx (and sometimes a harmless bug causes it to also save but not
1505 restore %eax); however, the code below is willing to see the pushes
1506 in any order, and will handle up to 8 of them.
1508 If the setup sequence is at the end of the function, then the next
1509 instruction will be a branch back to the start. */
1512 i386_analyze_prologue (struct gdbarch *gdbarch,
1513 CORE_ADDR pc, CORE_ADDR current_pc,
1514 struct i386_frame_cache *cache)
1516 pc = i386_skip_noop (pc);
1517 pc = i386_follow_jump (gdbarch, pc);
1518 pc = i386_analyze_struct_return (pc, current_pc, cache);
1519 pc = i386_skip_probe (pc);
1520 pc = i386_analyze_stack_align (pc, current_pc, cache);
1521 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1522 return i386_analyze_register_saves (pc, current_pc, cache);
1525 /* Return PC of first real instruction. */
1528 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1530 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1532 static gdb_byte pic_pat[6] =
1534 0xe8, 0, 0, 0, 0, /* call 0x0 */
1535 0x5b, /* popl %ebx */
1537 struct i386_frame_cache cache;
1543 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1544 if (cache.locals < 0)
1547 /* Found valid frame setup. */
1549 /* The native cc on SVR4 in -K PIC mode inserts the following code
1550 to get the address of the global offset table (GOT) into register
1555 movl %ebx,x(%ebp) (optional)
1558 This code is with the rest of the prologue (at the end of the
1559 function), so we have to skip it to get to the first real
1560 instruction at the start of the function. */
1562 for (i = 0; i < 6; i++)
1564 if (target_read_memory (pc + i, &op, 1))
1567 if (pic_pat[i] != op)
1574 if (target_read_memory (pc + delta, &op, 1))
1577 if (op == 0x89) /* movl %ebx, x(%ebp) */
1579 op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order);
1581 if (op == 0x5d) /* One byte offset from %ebp. */
1583 else if (op == 0x9d) /* Four byte offset from %ebp. */
1585 else /* Unexpected instruction. */
1588 if (target_read_memory (pc + delta, &op, 1))
1593 if (delta > 0 && op == 0x81
1594 && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order)
1601 /* If the function starts with a branch (to startup code at the end)
1602 the last instruction should bring us back to the first
1603 instruction of the real code. */
1604 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1605 pc = i386_follow_jump (gdbarch, pc);
1610 /* Check that the code pointed to by PC corresponds to a call to
1611 __main, skip it if so. Return PC otherwise. */
1614 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1616 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1619 if (target_read_memory (pc, &op, 1))
1625 if (target_read_memory (pc + 1, buf, sizeof buf) == 0)
1627 /* Make sure address is computed correctly as a 32bit
1628 integer even if CORE_ADDR is 64 bit wide. */
1629 struct minimal_symbol *s;
1630 CORE_ADDR call_dest;
1632 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1633 call_dest = call_dest & 0xffffffffU;
1634 s = lookup_minimal_symbol_by_pc (call_dest);
1636 && SYMBOL_LINKAGE_NAME (s) != NULL
1637 && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0)
1645 /* This function is 64-bit safe. */
1648 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1652 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1653 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1657 /* Normal frames. */
1660 i386_frame_cache_1 (struct frame_info *this_frame,
1661 struct i386_frame_cache *cache)
1663 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1664 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1668 cache->pc = get_frame_func (this_frame);
1670 /* In principle, for normal frames, %ebp holds the frame pointer,
1671 which holds the base address for the current stack frame.
1672 However, for functions that don't need it, the frame pointer is
1673 optional. For these "frameless" functions the frame pointer is
1674 actually the frame pointer of the calling frame. Signal
1675 trampolines are just a special case of a "frameless" function.
1676 They (usually) share their frame pointer with the frame that was
1677 in progress when the signal occurred. */
1679 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1680 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1681 if (cache->base == 0)
1684 /* For normal frames, %eip is stored at 4(%ebp). */
1685 cache->saved_regs[I386_EIP_REGNUM] = 4;
1688 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
1691 if (cache->locals < 0)
1693 /* We didn't find a valid frame, which means that CACHE->base
1694 currently holds the frame pointer for our calling frame. If
1695 we're at the start of a function, or somewhere half-way its
1696 prologue, the function's frame probably hasn't been fully
1697 setup yet. Try to reconstruct the base address for the stack
1698 frame by looking at the stack pointer. For truly "frameless"
1699 functions this might work too. */
1701 if (cache->saved_sp_reg != -1)
1703 /* Saved stack pointer has been saved. */
1704 get_frame_register (this_frame, cache->saved_sp_reg, buf);
1705 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
1707 /* We're halfway aligning the stack. */
1708 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
1709 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
1711 /* This will be added back below. */
1712 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
1714 else if (cache->pc != 0
1715 || target_read_memory (get_frame_pc (this_frame), buf, 1))
1717 /* We're in a known function, but did not find a frame
1718 setup. Assume that the function does not use %ebp.
1719 Alternatively, we may have jumped to an invalid
1720 address; in that case there is definitely no new
1722 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1723 cache->base = extract_unsigned_integer (buf, 4, byte_order)
1727 /* We're in an unknown function. We could not find the start
1728 of the function to analyze the prologue; our best option is
1729 to assume a typical frame layout with the caller's %ebp
1731 cache->saved_regs[I386_EBP_REGNUM] = 0;
1734 if (cache->saved_sp_reg != -1)
1736 /* Saved stack pointer has been saved (but the SAVED_SP_REG
1737 register may be unavailable). */
1738 if (cache->saved_sp == 0
1739 && frame_register_read (this_frame, cache->saved_sp_reg, buf))
1740 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
1742 /* Now that we have the base address for the stack frame we can
1743 calculate the value of %esp in the calling frame. */
1744 else if (cache->saved_sp == 0)
1745 cache->saved_sp = cache->base + 8;
1747 /* Adjust all the saved registers such that they contain addresses
1748 instead of offsets. */
1749 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1750 if (cache->saved_regs[i] != -1)
1751 cache->saved_regs[i] += cache->base;
1756 static struct i386_frame_cache *
1757 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
1759 volatile struct gdb_exception ex;
1760 struct i386_frame_cache *cache;
1765 cache = i386_alloc_frame_cache ();
1766 *this_cache = cache;
1768 TRY_CATCH (ex, RETURN_MASK_ERROR)
1770 i386_frame_cache_1 (this_frame, cache);
1772 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
1773 throw_exception (ex);
1779 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
1780 struct frame_id *this_id)
1782 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1784 /* This marks the outermost frame. */
1785 if (cache->base == 0)
1788 /* See the end of i386_push_dummy_call. */
1789 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
1792 static enum unwind_stop_reason
1793 i386_frame_unwind_stop_reason (struct frame_info *this_frame,
1796 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1799 return UNWIND_UNAVAILABLE;
1801 /* This marks the outermost frame. */
1802 if (cache->base == 0)
1803 return UNWIND_OUTERMOST;
1805 return UNWIND_NO_REASON;
1808 static struct value *
1809 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
1812 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1814 gdb_assert (regnum >= 0);
1816 /* The System V ABI says that:
1818 "The flags register contains the system flags, such as the
1819 direction flag and the carry flag. The direction flag must be
1820 set to the forward (that is, zero) direction before entry and
1821 upon exit from a function. Other user flags have no specified
1822 role in the standard calling sequence and are not preserved."
1824 To guarantee the "upon exit" part of that statement we fake a
1825 saved flags register that has its direction flag cleared.
1827 Note that GCC doesn't seem to rely on the fact that the direction
1828 flag is cleared after a function return; it always explicitly
1829 clears the flag before operations where it matters.
1831 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1832 right thing to do. The way we fake the flags register here makes
1833 it impossible to change it. */
1835 if (regnum == I386_EFLAGS_REGNUM)
1839 val = get_frame_register_unsigned (this_frame, regnum);
1841 return frame_unwind_got_constant (this_frame, regnum, val);
1844 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
1845 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
1847 if (regnum == I386_ESP_REGNUM
1848 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1))
1850 /* If the SP has been saved, but we don't know where, then this
1851 means that SAVED_SP_REG register was found unavailable back
1852 when we built the cache. */
1853 if (cache->saved_sp == 0)
1854 return frame_unwind_got_register (this_frame, regnum,
1855 cache->saved_sp_reg);
1857 return frame_unwind_got_constant (this_frame, regnum,
1861 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
1862 return frame_unwind_got_memory (this_frame, regnum,
1863 cache->saved_regs[regnum]);
1865 return frame_unwind_got_register (this_frame, regnum, regnum);
1868 static const struct frame_unwind i386_frame_unwind =
1871 i386_frame_unwind_stop_reason,
1873 i386_frame_prev_register,
1875 default_frame_sniffer
1878 /* Normal frames, but in a function epilogue. */
1880 /* The epilogue is defined here as the 'ret' instruction, which will
1881 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1882 the function's stack frame. */
1885 i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1889 if (target_read_memory (pc, &insn, 1))
1890 return 0; /* Can't read memory at pc. */
1892 if (insn != 0xc3) /* 'ret' instruction. */
1899 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
1900 struct frame_info *this_frame,
1901 void **this_prologue_cache)
1903 if (frame_relative_level (this_frame) == 0)
1904 return i386_in_function_epilogue_p (get_frame_arch (this_frame),
1905 get_frame_pc (this_frame));
1910 static struct i386_frame_cache *
1911 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
1913 volatile struct gdb_exception ex;
1914 struct i386_frame_cache *cache;
1920 cache = i386_alloc_frame_cache ();
1921 *this_cache = cache;
1923 TRY_CATCH (ex, RETURN_MASK_ERROR)
1925 cache->pc = get_frame_func (this_frame);
1927 /* At this point the stack looks as if we just entered the
1928 function, with the return address at the top of the
1930 sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM);
1931 cache->base = sp + cache->sp_offset;
1932 cache->saved_sp = cache->base + 8;
1933 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
1937 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
1938 throw_exception (ex);
1943 static enum unwind_stop_reason
1944 i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
1947 struct i386_frame_cache *cache =
1948 i386_epilogue_frame_cache (this_frame, this_cache);
1951 return UNWIND_UNAVAILABLE;
1953 return UNWIND_NO_REASON;
1957 i386_epilogue_frame_this_id (struct frame_info *this_frame,
1959 struct frame_id *this_id)
1961 struct i386_frame_cache *cache =
1962 i386_epilogue_frame_cache (this_frame, this_cache);
1967 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
1970 static struct value *
1971 i386_epilogue_frame_prev_register (struct frame_info *this_frame,
1972 void **this_cache, int regnum)
1974 /* Make sure we've initialized the cache. */
1975 i386_epilogue_frame_cache (this_frame, this_cache);
1977 return i386_frame_prev_register (this_frame, this_cache, regnum);
1980 static const struct frame_unwind i386_epilogue_frame_unwind =
1983 i386_epilogue_frame_unwind_stop_reason,
1984 i386_epilogue_frame_this_id,
1985 i386_epilogue_frame_prev_register,
1987 i386_epilogue_frame_sniffer
1991 /* Stack-based trampolines. */
1993 /* These trampolines are used on cross x86 targets, when taking the
1994 address of a nested function. When executing these trampolines,
1995 no stack frame is set up, so we are in a similar situation as in
1996 epilogues and i386_epilogue_frame_this_id can be re-used. */
1998 /* Static chain passed in register. */
2000 struct i386_insn i386_tramp_chain_in_reg_insns[] =
2002 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2003 { 5, { 0xb8 }, { 0xfe } },
2006 { 5, { 0xe9 }, { 0xff } },
2011 /* Static chain passed on stack (when regparm=3). */
2013 struct i386_insn i386_tramp_chain_on_stack_insns[] =
2016 { 5, { 0x68 }, { 0xff } },
2019 { 5, { 0xe9 }, { 0xff } },
2024 /* Return whether PC points inside a stack trampoline. */
2027 i386_in_stack_tramp_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2032 /* A stack trampoline is detected if no name is associated
2033 to the current pc and if it points inside a trampoline
2036 find_pc_partial_function (pc, &name, NULL, NULL);
2040 if (target_read_memory (pc, &insn, 1))
2043 if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns)
2044 && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns))
2051 i386_stack_tramp_frame_sniffer (const struct frame_unwind *self,
2052 struct frame_info *this_frame,
2055 if (frame_relative_level (this_frame) == 0)
2056 return i386_in_stack_tramp_p (get_frame_arch (this_frame),
2057 get_frame_pc (this_frame));
2062 static const struct frame_unwind i386_stack_tramp_frame_unwind =
2065 i386_epilogue_frame_unwind_stop_reason,
2066 i386_epilogue_frame_this_id,
2067 i386_epilogue_frame_prev_register,
2069 i386_stack_tramp_frame_sniffer
2073 /* Signal trampolines. */
2075 static struct i386_frame_cache *
2076 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2078 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2079 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2080 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2081 volatile struct gdb_exception ex;
2082 struct i386_frame_cache *cache;
2089 cache = i386_alloc_frame_cache ();
2091 TRY_CATCH (ex, RETURN_MASK_ERROR)
2093 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2094 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
2096 addr = tdep->sigcontext_addr (this_frame);
2097 if (tdep->sc_reg_offset)
2101 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
2103 for (i = 0; i < tdep->sc_num_regs; i++)
2104 if (tdep->sc_reg_offset[i] != -1)
2105 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2109 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
2110 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
2115 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2116 throw_exception (ex);
2118 *this_cache = cache;
2122 static enum unwind_stop_reason
2123 i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2126 struct i386_frame_cache *cache =
2127 i386_sigtramp_frame_cache (this_frame, this_cache);
2130 return UNWIND_UNAVAILABLE;
2132 return UNWIND_NO_REASON;
2136 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
2137 struct frame_id *this_id)
2139 struct i386_frame_cache *cache =
2140 i386_sigtramp_frame_cache (this_frame, this_cache);
2145 /* See the end of i386_push_dummy_call. */
2146 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
2149 static struct value *
2150 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
2151 void **this_cache, int regnum)
2153 /* Make sure we've initialized the cache. */
2154 i386_sigtramp_frame_cache (this_frame, this_cache);
2156 return i386_frame_prev_register (this_frame, this_cache, regnum);
2160 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
2161 struct frame_info *this_frame,
2162 void **this_prologue_cache)
2164 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2166 /* We shouldn't even bother if we don't have a sigcontext_addr
2168 if (tdep->sigcontext_addr == NULL)
2171 if (tdep->sigtramp_p != NULL)
2173 if (tdep->sigtramp_p (this_frame))
2177 if (tdep->sigtramp_start != 0)
2179 CORE_ADDR pc = get_frame_pc (this_frame);
2181 gdb_assert (tdep->sigtramp_end != 0);
2182 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2189 static const struct frame_unwind i386_sigtramp_frame_unwind =
2192 i386_sigtramp_frame_unwind_stop_reason,
2193 i386_sigtramp_frame_this_id,
2194 i386_sigtramp_frame_prev_register,
2196 i386_sigtramp_frame_sniffer
2201 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
2203 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2208 static const struct frame_base i386_frame_base =
2211 i386_frame_base_address,
2212 i386_frame_base_address,
2213 i386_frame_base_address
2216 static struct frame_id
2217 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2221 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
2223 /* See the end of i386_push_dummy_call. */
2224 return frame_id_build (fp + 8, get_frame_pc (this_frame));
2228 /* Figure out where the longjmp will land. Slurp the args out of the
2229 stack. We expect the first arg to be a pointer to the jmp_buf
2230 structure from which we extract the address that we will land at.
2231 This address is copied into PC. This routine returns non-zero on
2235 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2238 CORE_ADDR sp, jb_addr;
2239 struct gdbarch *gdbarch = get_frame_arch (frame);
2240 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2241 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2243 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2244 longjmp will land. */
2245 if (jb_pc_offset == -1)
2248 get_frame_register (frame, I386_ESP_REGNUM, buf);
2249 sp = extract_unsigned_integer (buf, 4, byte_order);
2250 if (target_read_memory (sp + 4, buf, 4))
2253 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
2254 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
2257 *pc = extract_unsigned_integer (buf, 4, byte_order);
2262 /* Check whether TYPE must be 16-byte-aligned when passed as a
2263 function argument. 16-byte vectors, _Decimal128 and structures or
2264 unions containing such types must be 16-byte-aligned; other
2265 arguments are 4-byte-aligned. */
2268 i386_16_byte_align_p (struct type *type)
2270 type = check_typedef (type);
2271 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
2272 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
2273 && TYPE_LENGTH (type) == 16)
2275 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2276 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
2277 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2278 || TYPE_CODE (type) == TYPE_CODE_UNION)
2281 for (i = 0; i < TYPE_NFIELDS (type); i++)
2283 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
2291 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2292 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2293 struct value **args, CORE_ADDR sp, int struct_return,
2294 CORE_ADDR struct_addr)
2296 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2302 /* Determine the total space required for arguments and struct
2303 return address in a first pass (allowing for 16-byte-aligned
2304 arguments), then push arguments in a second pass. */
2306 for (write_pass = 0; write_pass < 2; write_pass++)
2308 int args_space_used = 0;
2309 int have_16_byte_aligned_arg = 0;
2315 /* Push value address. */
2316 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2317 write_memory (sp, buf, 4);
2318 args_space_used += 4;
2324 for (i = 0; i < nargs; i++)
2326 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2330 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2331 args_space_used = align_up (args_space_used, 16);
2333 write_memory (sp + args_space_used,
2334 value_contents_all (args[i]), len);
2335 /* The System V ABI says that:
2337 "An argument's size is increased, if necessary, to make it a
2338 multiple of [32-bit] words. This may require tail padding,
2339 depending on the size of the argument."
2341 This makes sure the stack stays word-aligned. */
2342 args_space_used += align_up (len, 4);
2346 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2348 args_space = align_up (args_space, 16);
2349 have_16_byte_aligned_arg = 1;
2351 args_space += align_up (len, 4);
2357 if (have_16_byte_aligned_arg)
2358 args_space = align_up (args_space, 16);
2363 /* Store return address. */
2365 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2366 write_memory (sp, buf, 4);
2368 /* Finally, update the stack pointer... */
2369 store_unsigned_integer (buf, 4, byte_order, sp);
2370 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
2372 /* ...and fake a frame pointer. */
2373 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
2375 /* MarkK wrote: This "+ 8" is all over the place:
2376 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2377 i386_dummy_id). It's there, since all frame unwinders for
2378 a given target have to agree (within a certain margin) on the
2379 definition of the stack address of a frame. Otherwise frame id
2380 comparison might not work correctly. Since DWARF2/GCC uses the
2381 stack address *before* the function call as a frame's CFA. On
2382 the i386, when %ebp is used as a frame pointer, the offset
2383 between the contents %ebp and the CFA as defined by GCC. */
2387 /* These registers are used for returning integers (and on some
2388 targets also for returning `struct' and `union' values when their
2389 size and alignment match an integer type). */
2390 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2391 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2393 /* Read, for architecture GDBARCH, a function return value of TYPE
2394 from REGCACHE, and copy that into VALBUF. */
2397 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2398 struct regcache *regcache, gdb_byte *valbuf)
2400 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2401 int len = TYPE_LENGTH (type);
2402 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2404 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2406 if (tdep->st0_regnum < 0)
2408 warning (_("Cannot find floating-point return value."));
2409 memset (valbuf, 0, len);
2413 /* Floating-point return values can be found in %st(0). Convert
2414 its contents to the desired type. This is probably not
2415 exactly how it would happen on the target itself, but it is
2416 the best we can do. */
2417 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2418 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
2422 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2423 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2425 if (len <= low_size)
2427 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2428 memcpy (valbuf, buf, len);
2430 else if (len <= (low_size + high_size))
2432 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2433 memcpy (valbuf, buf, low_size);
2434 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2435 memcpy (valbuf + low_size, buf, len - low_size);
2438 internal_error (__FILE__, __LINE__,
2439 _("Cannot extract return value of %d bytes long."),
2444 /* Write, for architecture GDBARCH, a function return value of TYPE
2445 from VALBUF into REGCACHE. */
2448 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2449 struct regcache *regcache, const gdb_byte *valbuf)
2451 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2452 int len = TYPE_LENGTH (type);
2454 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2457 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2459 if (tdep->st0_regnum < 0)
2461 warning (_("Cannot set floating-point return value."));
2465 /* Returning floating-point values is a bit tricky. Apart from
2466 storing the return value in %st(0), we have to simulate the
2467 state of the FPU at function return point. */
2469 /* Convert the value found in VALBUF to the extended
2470 floating-point format used by the FPU. This is probably
2471 not exactly how it would happen on the target itself, but
2472 it is the best we can do. */
2473 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
2474 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2476 /* Set the top of the floating-point register stack to 7. The
2477 actual value doesn't really matter, but 7 is what a normal
2478 function return would end up with if the program started out
2479 with a freshly initialized FPU. */
2480 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2482 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2484 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2485 the floating-point register stack to 7, the appropriate value
2486 for the tag word is 0x3fff. */
2487 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2491 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2492 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2494 if (len <= low_size)
2495 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2496 else if (len <= (low_size + high_size))
2498 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2499 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
2500 len - low_size, valbuf + low_size);
2503 internal_error (__FILE__, __LINE__,
2504 _("Cannot store return value of %d bytes long."), len);
2509 /* This is the variable that is set with "set struct-convention", and
2510 its legitimate values. */
2511 static const char default_struct_convention[] = "default";
2512 static const char pcc_struct_convention[] = "pcc";
2513 static const char reg_struct_convention[] = "reg";
2514 static const char *valid_conventions[] =
2516 default_struct_convention,
2517 pcc_struct_convention,
2518 reg_struct_convention,
2521 static const char *struct_convention = default_struct_convention;
2523 /* Return non-zero if TYPE, which is assumed to be a structure,
2524 a union type, or an array type, should be returned in registers
2525 for architecture GDBARCH. */
2528 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2530 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2531 enum type_code code = TYPE_CODE (type);
2532 int len = TYPE_LENGTH (type);
2534 gdb_assert (code == TYPE_CODE_STRUCT
2535 || code == TYPE_CODE_UNION
2536 || code == TYPE_CODE_ARRAY);
2538 if (struct_convention == pcc_struct_convention
2539 || (struct_convention == default_struct_convention
2540 && tdep->struct_return == pcc_struct_return))
2543 /* Structures consisting of a single `float', `double' or 'long
2544 double' member are returned in %st(0). */
2545 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2547 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2548 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2549 return (len == 4 || len == 8 || len == 12);
2552 return (len == 1 || len == 2 || len == 4 || len == 8);
2555 /* Determine, for architecture GDBARCH, how a return value of TYPE
2556 should be returned. If it is supposed to be returned in registers,
2557 and READBUF is non-zero, read the appropriate value from REGCACHE,
2558 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2559 from WRITEBUF into REGCACHE. */
2561 static enum return_value_convention
2562 i386_return_value (struct gdbarch *gdbarch, struct type *func_type,
2563 struct type *type, struct regcache *regcache,
2564 gdb_byte *readbuf, const gdb_byte *writebuf)
2566 enum type_code code = TYPE_CODE (type);
2568 if (((code == TYPE_CODE_STRUCT
2569 || code == TYPE_CODE_UNION
2570 || code == TYPE_CODE_ARRAY)
2571 && !i386_reg_struct_return_p (gdbarch, type))
2572 /* 128-bit decimal float uses the struct return convention. */
2573 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2575 /* The System V ABI says that:
2577 "A function that returns a structure or union also sets %eax
2578 to the value of the original address of the caller's area
2579 before it returns. Thus when the caller receives control
2580 again, the address of the returned object resides in register
2581 %eax and can be used to access the object."
2583 So the ABI guarantees that we can always find the return
2584 value just after the function has returned. */
2586 /* Note that the ABI doesn't mention functions returning arrays,
2587 which is something possible in certain languages such as Ada.
2588 In this case, the value is returned as if it was wrapped in
2589 a record, so the convention applied to records also applies
2596 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2597 read_memory (addr, readbuf, TYPE_LENGTH (type));
2600 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2603 /* This special case is for structures consisting of a single
2604 `float', `double' or 'long double' member. These structures are
2605 returned in %st(0). For these structures, we call ourselves
2606 recursively, changing TYPE into the type of the first member of
2607 the structure. Since that should work for all structures that
2608 have only one member, we don't bother to check the member's type
2610 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2612 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2613 return i386_return_value (gdbarch, func_type, type, regcache,
2618 i386_extract_return_value (gdbarch, type, regcache, readbuf);
2620 i386_store_return_value (gdbarch, type, regcache, writebuf);
2622 return RETURN_VALUE_REGISTER_CONVENTION;
2627 i387_ext_type (struct gdbarch *gdbarch)
2629 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2631 if (!tdep->i387_ext_type)
2633 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
2634 gdb_assert (tdep->i387_ext_type != NULL);
2637 return tdep->i387_ext_type;
2640 /* Construct vector type for pseudo YMM registers. We can't use
2641 tdesc_find_type since YMM isn't described in target description. */
2643 static struct type *
2644 i386_ymm_type (struct gdbarch *gdbarch)
2646 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2648 if (!tdep->i386_ymm_type)
2650 const struct builtin_type *bt = builtin_type (gdbarch);
2652 /* The type we're building is this: */
2654 union __gdb_builtin_type_vec256i
2656 int128_t uint128[2];
2657 int64_t v2_int64[4];
2658 int32_t v4_int32[8];
2659 int16_t v8_int16[16];
2660 int8_t v16_int8[32];
2661 double v2_double[4];
2668 t = arch_composite_type (gdbarch,
2669 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
2670 append_composite_type_field (t, "v8_float",
2671 init_vector_type (bt->builtin_float, 8));
2672 append_composite_type_field (t, "v4_double",
2673 init_vector_type (bt->builtin_double, 4));
2674 append_composite_type_field (t, "v32_int8",
2675 init_vector_type (bt->builtin_int8, 32));
2676 append_composite_type_field (t, "v16_int16",
2677 init_vector_type (bt->builtin_int16, 16));
2678 append_composite_type_field (t, "v8_int32",
2679 init_vector_type (bt->builtin_int32, 8));
2680 append_composite_type_field (t, "v4_int64",
2681 init_vector_type (bt->builtin_int64, 4));
2682 append_composite_type_field (t, "v2_int128",
2683 init_vector_type (bt->builtin_int128, 2));
2685 TYPE_VECTOR (t) = 1;
2686 TYPE_NAME (t) = "builtin_type_vec256i";
2687 tdep->i386_ymm_type = t;
2690 return tdep->i386_ymm_type;
2693 /* Construct vector type for MMX registers. */
2694 static struct type *
2695 i386_mmx_type (struct gdbarch *gdbarch)
2697 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2699 if (!tdep->i386_mmx_type)
2701 const struct builtin_type *bt = builtin_type (gdbarch);
2703 /* The type we're building is this: */
2705 union __gdb_builtin_type_vec64i
2708 int32_t v2_int32[2];
2709 int16_t v4_int16[4];
2716 t = arch_composite_type (gdbarch,
2717 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
2719 append_composite_type_field (t, "uint64", bt->builtin_int64);
2720 append_composite_type_field (t, "v2_int32",
2721 init_vector_type (bt->builtin_int32, 2));
2722 append_composite_type_field (t, "v4_int16",
2723 init_vector_type (bt->builtin_int16, 4));
2724 append_composite_type_field (t, "v8_int8",
2725 init_vector_type (bt->builtin_int8, 8));
2727 TYPE_VECTOR (t) = 1;
2728 TYPE_NAME (t) = "builtin_type_vec64i";
2729 tdep->i386_mmx_type = t;
2732 return tdep->i386_mmx_type;
2735 /* Return the GDB type object for the "standard" data type of data in
2738 static struct type *
2739 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2741 if (i386_mmx_regnum_p (gdbarch, regnum))
2742 return i386_mmx_type (gdbarch);
2743 else if (i386_ymm_regnum_p (gdbarch, regnum))
2744 return i386_ymm_type (gdbarch);
2747 const struct builtin_type *bt = builtin_type (gdbarch);
2748 if (i386_byte_regnum_p (gdbarch, regnum))
2749 return bt->builtin_int8;
2750 else if (i386_word_regnum_p (gdbarch, regnum))
2751 return bt->builtin_int16;
2752 else if (i386_dword_regnum_p (gdbarch, regnum))
2753 return bt->builtin_int32;
2756 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2759 /* Map a cooked register onto a raw register or memory. For the i386,
2760 the MMX registers need to be mapped onto floating point registers. */
2763 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
2765 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
2770 mmxreg = regnum - tdep->mm0_regnum;
2771 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2772 tos = (fstat >> 11) & 0x7;
2773 fpreg = (mmxreg + tos) % 8;
2775 return (I387_ST0_REGNUM (tdep) + fpreg);
2778 enum register_status
2779 i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2780 int regnum, gdb_byte *buf)
2782 gdb_byte raw_buf[MAX_REGISTER_SIZE];
2783 enum register_status status;
2785 if (i386_mmx_regnum_p (gdbarch, regnum))
2787 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2789 /* Extract (always little endian). */
2790 status = regcache_raw_read (regcache, fpnum, raw_buf);
2791 if (status != REG_VALID)
2793 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
2797 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2799 if (i386_ymm_regnum_p (gdbarch, regnum))
2801 regnum -= tdep->ymm0_regnum;
2803 /* Extract (always little endian). Read lower 128bits. */
2804 status = regcache_raw_read (regcache,
2805 I387_XMM0_REGNUM (tdep) + regnum,
2807 if (status != REG_VALID)
2809 memcpy (buf, raw_buf, 16);
2810 /* Read upper 128bits. */
2811 status = regcache_raw_read (regcache,
2812 tdep->ymm0h_regnum + regnum,
2814 if (status != REG_VALID)
2816 memcpy (buf + 16, raw_buf, 16);
2818 else if (i386_word_regnum_p (gdbarch, regnum))
2820 int gpnum = regnum - tdep->ax_regnum;
2822 /* Extract (always little endian). */
2823 status = regcache_raw_read (regcache, gpnum, raw_buf);
2824 if (status != REG_VALID)
2826 memcpy (buf, raw_buf, 2);
2828 else if (i386_byte_regnum_p (gdbarch, regnum))
2830 /* Check byte pseudo registers last since this function will
2831 be called from amd64_pseudo_register_read, which handles
2832 byte pseudo registers differently. */
2833 int gpnum = regnum - tdep->al_regnum;
2835 /* Extract (always little endian). We read both lower and
2837 status = regcache_raw_read (regcache, gpnum % 4, raw_buf);
2838 if (status != REG_VALID)
2841 memcpy (buf, raw_buf + 1, 1);
2843 memcpy (buf, raw_buf, 1);
2846 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2853 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2854 int regnum, const gdb_byte *buf)
2856 gdb_byte raw_buf[MAX_REGISTER_SIZE];
2858 if (i386_mmx_regnum_p (gdbarch, regnum))
2860 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2863 regcache_raw_read (regcache, fpnum, raw_buf);
2864 /* ... Modify ... (always little endian). */
2865 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
2867 regcache_raw_write (regcache, fpnum, raw_buf);
2871 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2873 if (i386_ymm_regnum_p (gdbarch, regnum))
2875 regnum -= tdep->ymm0_regnum;
2877 /* ... Write lower 128bits. */
2878 regcache_raw_write (regcache,
2879 I387_XMM0_REGNUM (tdep) + regnum,
2881 /* ... Write upper 128bits. */
2882 regcache_raw_write (regcache,
2883 tdep->ymm0h_regnum + regnum,
2886 else if (i386_word_regnum_p (gdbarch, regnum))
2888 int gpnum = regnum - tdep->ax_regnum;
2891 regcache_raw_read (regcache, gpnum, raw_buf);
2892 /* ... Modify ... (always little endian). */
2893 memcpy (raw_buf, buf, 2);
2895 regcache_raw_write (regcache, gpnum, raw_buf);
2897 else if (i386_byte_regnum_p (gdbarch, regnum))
2899 /* Check byte pseudo registers last since this function will
2900 be called from amd64_pseudo_register_read, which handles
2901 byte pseudo registers differently. */
2902 int gpnum = regnum - tdep->al_regnum;
2904 /* Read ... We read both lower and upper registers. */
2905 regcache_raw_read (regcache, gpnum % 4, raw_buf);
2906 /* ... Modify ... (always little endian). */
2908 memcpy (raw_buf + 1, buf, 1);
2910 memcpy (raw_buf, buf, 1);
2912 regcache_raw_write (regcache, gpnum % 4, raw_buf);
2915 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2920 /* Return the register number of the register allocated by GCC after
2921 REGNUM, or -1 if there is no such register. */
2924 i386_next_regnum (int regnum)
2926 /* GCC allocates the registers in the order:
2928 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2930 Since storing a variable in %esp doesn't make any sense we return
2931 -1 for %ebp and for %esp itself. */
2932 static int next_regnum[] =
2934 I386_EDX_REGNUM, /* Slot for %eax. */
2935 I386_EBX_REGNUM, /* Slot for %ecx. */
2936 I386_ECX_REGNUM, /* Slot for %edx. */
2937 I386_ESI_REGNUM, /* Slot for %ebx. */
2938 -1, -1, /* Slots for %esp and %ebp. */
2939 I386_EDI_REGNUM, /* Slot for %esi. */
2940 I386_EBP_REGNUM /* Slot for %edi. */
2943 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
2944 return next_regnum[regnum];
2949 /* Return nonzero if a value of type TYPE stored in register REGNUM
2950 needs any special handling. */
2953 i386_convert_register_p (struct gdbarch *gdbarch,
2954 int regnum, struct type *type)
2956 int len = TYPE_LENGTH (type);
2958 /* Values may be spread across multiple registers. Most debugging
2959 formats aren't expressive enough to specify the locations, so
2960 some heuristics is involved. Right now we only handle types that
2961 have a length that is a multiple of the word size, since GCC
2962 doesn't seem to put any other types into registers. */
2963 if (len > 4 && len % 4 == 0)
2965 int last_regnum = regnum;
2969 last_regnum = i386_next_regnum (last_regnum);
2973 if (last_regnum != -1)
2977 return i387_convert_register_p (gdbarch, regnum, type);
2980 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2981 return its contents in TO. */
2984 i386_register_to_value (struct frame_info *frame, int regnum,
2985 struct type *type, gdb_byte *to,
2986 int *optimizedp, int *unavailablep)
2988 struct gdbarch *gdbarch = get_frame_arch (frame);
2989 int len = TYPE_LENGTH (type);
2991 if (i386_fp_regnum_p (gdbarch, regnum))
2992 return i387_register_to_value (frame, regnum, type, to,
2993 optimizedp, unavailablep);
2995 /* Read a value spread across multiple registers. */
2997 gdb_assert (len > 4 && len % 4 == 0);
3001 gdb_assert (regnum != -1);
3002 gdb_assert (register_size (gdbarch, regnum) == 4);
3004 if (!get_frame_register_bytes (frame, regnum, 0,
3005 register_size (gdbarch, regnum),
3006 to, optimizedp, unavailablep))
3009 regnum = i386_next_regnum (regnum);
3014 *optimizedp = *unavailablep = 0;
3018 /* Write the contents FROM of a value of type TYPE into register
3019 REGNUM in frame FRAME. */
3022 i386_value_to_register (struct frame_info *frame, int regnum,
3023 struct type *type, const gdb_byte *from)
3025 int len = TYPE_LENGTH (type);
3027 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
3029 i387_value_to_register (frame, regnum, type, from);
3033 /* Write a value spread across multiple registers. */
3035 gdb_assert (len > 4 && len % 4 == 0);
3039 gdb_assert (regnum != -1);
3040 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
3042 put_frame_register (frame, regnum, from);
3043 regnum = i386_next_regnum (regnum);
3049 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3050 in the general-purpose register set REGSET to register cache
3051 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3054 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
3055 int regnum, const void *gregs, size_t len)
3057 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3058 const gdb_byte *regs = gregs;
3061 gdb_assert (len == tdep->sizeof_gregset);
3063 for (i = 0; i < tdep->gregset_num_regs; i++)
3065 if ((regnum == i || regnum == -1)
3066 && tdep->gregset_reg_offset[i] != -1)
3067 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
3071 /* Collect register REGNUM from the register cache REGCACHE and store
3072 it in the buffer specified by GREGS and LEN as described by the
3073 general-purpose register set REGSET. If REGNUM is -1, do this for
3074 all registers in REGSET. */
3077 i386_collect_gregset (const struct regset *regset,
3078 const struct regcache *regcache,
3079 int regnum, void *gregs, size_t len)
3081 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3082 gdb_byte *regs = gregs;
3085 gdb_assert (len == tdep->sizeof_gregset);
3087 for (i = 0; i < tdep->gregset_num_regs; i++)
3089 if ((regnum == i || regnum == -1)
3090 && tdep->gregset_reg_offset[i] != -1)
3091 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
3095 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3096 in the floating-point register set REGSET to register cache
3097 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3100 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
3101 int regnum, const void *fpregs, size_t len)
3103 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3105 if (len == I387_SIZEOF_FXSAVE)
3107 i387_supply_fxsave (regcache, regnum, fpregs);
3111 gdb_assert (len == tdep->sizeof_fpregset);
3112 i387_supply_fsave (regcache, regnum, fpregs);
3115 /* Collect register REGNUM from the register cache REGCACHE and store
3116 it in the buffer specified by FPREGS and LEN as described by the
3117 floating-point register set REGSET. If REGNUM is -1, do this for
3118 all registers in REGSET. */
3121 i386_collect_fpregset (const struct regset *regset,
3122 const struct regcache *regcache,
3123 int regnum, void *fpregs, size_t len)
3125 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3127 if (len == I387_SIZEOF_FXSAVE)
3129 i387_collect_fxsave (regcache, regnum, fpregs);
3133 gdb_assert (len == tdep->sizeof_fpregset);
3134 i387_collect_fsave (regcache, regnum, fpregs);
3137 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
3140 i386_supply_xstateregset (const struct regset *regset,
3141 struct regcache *regcache, int regnum,
3142 const void *xstateregs, size_t len)
3144 i387_supply_xsave (regcache, regnum, xstateregs);
3147 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
3150 i386_collect_xstateregset (const struct regset *regset,
3151 const struct regcache *regcache,
3152 int regnum, void *xstateregs, size_t len)
3154 i387_collect_xsave (regcache, regnum, xstateregs, 1);
3157 /* Return the appropriate register set for the core section identified
3158 by SECT_NAME and SECT_SIZE. */
3160 const struct regset *
3161 i386_regset_from_core_section (struct gdbarch *gdbarch,
3162 const char *sect_name, size_t sect_size)
3164 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3166 if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset)
3168 if (tdep->gregset == NULL)
3169 tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset,
3170 i386_collect_gregset);
3171 return tdep->gregset;
3174 if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
3175 || (strcmp (sect_name, ".reg-xfp") == 0
3176 && sect_size == I387_SIZEOF_FXSAVE))
3178 if (tdep->fpregset == NULL)
3179 tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset,
3180 i386_collect_fpregset);
3181 return tdep->fpregset;
3184 if (strcmp (sect_name, ".reg-xstate") == 0)
3186 if (tdep->xstateregset == NULL)
3187 tdep->xstateregset = regset_alloc (gdbarch,
3188 i386_supply_xstateregset,
3189 i386_collect_xstateregset);
3191 return tdep->xstateregset;
3198 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3201 i386_pe_skip_trampoline_code (struct frame_info *frame,
3202 CORE_ADDR pc, char *name)
3204 struct gdbarch *gdbarch = get_frame_arch (frame);
3205 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3208 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
3210 unsigned long indirect =
3211 read_memory_unsigned_integer (pc + 2, 4, byte_order);
3212 struct minimal_symbol *indsym =
3213 indirect ? lookup_minimal_symbol_by_pc (indirect) : 0;
3214 char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0;
3218 if (strncmp (symname, "__imp_", 6) == 0
3219 || strncmp (symname, "_imp_", 5) == 0)
3221 read_memory_unsigned_integer (indirect, 4, byte_order);
3224 return 0; /* Not a trampoline. */
3228 /* Return whether the THIS_FRAME corresponds to a sigtramp
3232 i386_sigtramp_p (struct frame_info *this_frame)
3234 CORE_ADDR pc = get_frame_pc (this_frame);
3237 find_pc_partial_function (pc, &name, NULL, NULL);
3238 return (name && strcmp ("_sigtramp", name) == 0);
3242 /* We have two flavours of disassembly. The machinery on this page
3243 deals with switching between those. */
3246 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
3248 gdb_assert (disassembly_flavor == att_flavor
3249 || disassembly_flavor == intel_flavor);
3251 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3252 constified, cast to prevent a compiler warning. */
3253 info->disassembler_options = (char *) disassembly_flavor;
3255 return print_insn_i386 (pc, info);
3259 /* There are a few i386 architecture variants that differ only
3260 slightly from the generic i386 target. For now, we don't give them
3261 their own source file, but include them here. As a consequence,
3262 they'll always be included. */
3264 /* System V Release 4 (SVR4). */
3266 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3270 i386_svr4_sigtramp_p (struct frame_info *this_frame)
3272 CORE_ADDR pc = get_frame_pc (this_frame);
3275 /* UnixWare uses _sigacthandler. The origin of the other symbols is
3276 currently unknown. */
3277 find_pc_partial_function (pc, &name, NULL, NULL);
3278 return (name && (strcmp ("_sigreturn", name) == 0
3279 || strcmp ("_sigacthandler", name) == 0
3280 || strcmp ("sigvechandler", name) == 0));
3283 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3284 address of the associated sigcontext (ucontext) structure. */
3287 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
3289 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3290 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3294 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
3295 sp = extract_unsigned_integer (buf, 4, byte_order);
3297 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
3304 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3306 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3307 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3310 /* System V Release 4 (SVR4). */
3313 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3315 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3317 /* System V Release 4 uses ELF. */
3318 i386_elf_init_abi (info, gdbarch);
3320 /* System V Release 4 has shared libraries. */
3321 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
3323 tdep->sigtramp_p = i386_svr4_sigtramp_p;
3324 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
3325 tdep->sc_pc_offset = 36 + 14 * 4;
3326 tdep->sc_sp_offset = 36 + 17 * 4;
3328 tdep->jb_pc_offset = 20;
3334 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3336 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3338 /* DJGPP doesn't have any special frames for signal handlers. */
3339 tdep->sigtramp_p = NULL;
3341 tdep->jb_pc_offset = 36;
3343 /* DJGPP does not support the SSE registers. */
3344 if (! tdesc_has_registers (info.target_desc))
3345 tdep->tdesc = tdesc_i386_mmx;
3347 /* Native compiler is GCC, which uses the SVR4 register numbering
3348 even in COFF and STABS. See the comment in i386_gdbarch_init,
3349 before the calls to set_gdbarch_stab_reg_to_regnum and
3350 set_gdbarch_sdb_reg_to_regnum. */
3351 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3352 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3354 set_gdbarch_has_dos_based_file_system (gdbarch, 1);
3358 /* i386 register groups. In addition to the normal groups, add "mmx"
3361 static struct reggroup *i386_sse_reggroup;
3362 static struct reggroup *i386_mmx_reggroup;
3365 i386_init_reggroups (void)
3367 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
3368 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
3372 i386_add_reggroups (struct gdbarch *gdbarch)
3374 reggroup_add (gdbarch, i386_sse_reggroup);
3375 reggroup_add (gdbarch, i386_mmx_reggroup);
3376 reggroup_add (gdbarch, general_reggroup);
3377 reggroup_add (gdbarch, float_reggroup);
3378 reggroup_add (gdbarch, all_reggroup);
3379 reggroup_add (gdbarch, save_reggroup);
3380 reggroup_add (gdbarch, restore_reggroup);
3381 reggroup_add (gdbarch, vector_reggroup);
3382 reggroup_add (gdbarch, system_reggroup);
3386 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
3387 struct reggroup *group)
3389 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3390 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
3391 ymm_regnum_p, ymmh_regnum_p;
3393 /* Don't include pseudo registers, except for MMX, in any register
3395 if (i386_byte_regnum_p (gdbarch, regnum))
3398 if (i386_word_regnum_p (gdbarch, regnum))
3401 if (i386_dword_regnum_p (gdbarch, regnum))
3404 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
3405 if (group == i386_mmx_reggroup)
3406 return mmx_regnum_p;
3408 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
3409 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
3410 if (group == i386_sse_reggroup)
3411 return xmm_regnum_p || mxcsr_regnum_p;
3413 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
3414 if (group == vector_reggroup)
3415 return (mmx_regnum_p
3419 && ((tdep->xcr0 & I386_XSTATE_AVX_MASK)
3420 == I386_XSTATE_SSE_MASK)));
3422 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
3423 || i386_fpc_regnum_p (gdbarch, regnum));
3424 if (group == float_reggroup)
3427 /* For "info reg all", don't include upper YMM registers nor XMM
3428 registers when AVX is supported. */
3429 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
3430 if (group == all_reggroup
3432 && (tdep->xcr0 & I386_XSTATE_AVX))
3436 if (group == general_reggroup)
3437 return (!fp_regnum_p
3444 return default_register_reggroup_p (gdbarch, regnum, group);
3448 /* Get the ARGIth function argument for the current function. */
3451 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
3454 struct gdbarch *gdbarch = get_frame_arch (frame);
3455 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3456 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
3457 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
3461 i386_skip_permanent_breakpoint (struct regcache *regcache)
3463 CORE_ADDR current_pc = regcache_read_pc (regcache);
3465 /* On i386, breakpoint is exactly 1 byte long, so we just
3466 adjust the PC in the regcache. */
3468 regcache_write_pc (regcache, current_pc);
3472 #define PREFIX_REPZ 0x01
3473 #define PREFIX_REPNZ 0x02
3474 #define PREFIX_LOCK 0x04
3475 #define PREFIX_DATA 0x08
3476 #define PREFIX_ADDR 0x10
3488 /* i386 arith/logic operations */
3501 struct i386_record_s
3503 struct gdbarch *gdbarch;
3504 struct regcache *regcache;
3505 CORE_ADDR orig_addr;
3511 uint8_t mod, reg, rm;
3520 /* Parse "modrm" part in current memory address that irp->addr point to
3521 Return -1 if something wrong. */
3524 i386_record_modrm (struct i386_record_s *irp)
3526 struct gdbarch *gdbarch = irp->gdbarch;
3528 if (target_read_memory (irp->addr, &irp->modrm, 1))
3531 printf_unfiltered (_("Process record: error reading memory at "
3532 "addr %s len = 1.\n"),
3533 paddress (gdbarch, irp->addr));
3537 irp->mod = (irp->modrm >> 6) & 3;
3538 irp->reg = (irp->modrm >> 3) & 7;
3539 irp->rm = irp->modrm & 7;
3544 /* Get the memory address that current instruction write to and set it to
3545 the argument "addr".
3546 Return -1 if something wrong. */
3549 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
3551 struct gdbarch *gdbarch = irp->gdbarch;
3552 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3564 uint8_t base = irp->rm;
3569 if (target_read_memory (irp->addr, &byte, 1))
3572 printf_unfiltered (_("Process record: error reading memory "
3573 "at addr %s len = 1.\n"),
3574 paddress (gdbarch, irp->addr));
3578 scale = (byte >> 6) & 3;
3579 index = ((byte >> 3) & 7) | irp->rex_x;
3587 if ((base & 7) == 5)
3590 if (target_read_memory (irp->addr, buf, 4))
3593 printf_unfiltered (_("Process record: error reading "
3594 "memory at addr %s len = 4.\n"),
3595 paddress (gdbarch, irp->addr));
3599 *addr = extract_signed_integer (buf, 4, byte_order);
3600 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
3601 *addr += irp->addr + irp->rip_offset;
3605 if (target_read_memory (irp->addr, buf, 1))
3608 printf_unfiltered (_("Process record: error reading memory "
3609 "at addr %s len = 1.\n"),
3610 paddress (gdbarch, irp->addr));
3614 *addr = (int8_t) buf[0];
3617 if (target_read_memory (irp->addr, buf, 4))
3620 printf_unfiltered (_("Process record: error reading memory "
3621 "at addr %s len = 4.\n"),
3622 paddress (gdbarch, irp->addr));
3625 *addr = extract_signed_integer (buf, 4, byte_order);
3633 if (base == 4 && irp->popl_esp_hack)
3634 *addr += irp->popl_esp_hack;
3635 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
3638 if (irp->aflag == 2)
3643 *addr = (uint32_t) (offset64 + *addr);
3645 if (havesib && (index != 4 || scale != 0))
3647 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
3649 if (irp->aflag == 2)
3650 *addr += offset64 << scale;
3652 *addr = (uint32_t) (*addr + (offset64 << scale));
3663 if (target_read_memory (irp->addr, buf, 2))
3666 printf_unfiltered (_("Process record: error reading "
3667 "memory at addr %s len = 2.\n"),
3668 paddress (gdbarch, irp->addr));
3672 *addr = extract_signed_integer (buf, 2, byte_order);
3678 if (target_read_memory (irp->addr, buf, 1))
3681 printf_unfiltered (_("Process record: error reading memory "
3682 "at addr %s len = 1.\n"),
3683 paddress (gdbarch, irp->addr));
3687 *addr = (int8_t) buf[0];
3690 if (target_read_memory (irp->addr, buf, 2))
3693 printf_unfiltered (_("Process record: error reading memory "
3694 "at addr %s len = 2.\n"),
3695 paddress (gdbarch, irp->addr));
3699 *addr = extract_signed_integer (buf, 2, byte_order);
3706 regcache_raw_read_unsigned (irp->regcache,
3707 irp->regmap[X86_RECORD_REBX_REGNUM],
3709 *addr = (uint32_t) (*addr + offset64);
3710 regcache_raw_read_unsigned (irp->regcache,
3711 irp->regmap[X86_RECORD_RESI_REGNUM],
3713 *addr = (uint32_t) (*addr + offset64);
3716 regcache_raw_read_unsigned (irp->regcache,
3717 irp->regmap[X86_RECORD_REBX_REGNUM],
3719 *addr = (uint32_t) (*addr + offset64);
3720 regcache_raw_read_unsigned (irp->regcache,
3721 irp->regmap[X86_RECORD_REDI_REGNUM],
3723 *addr = (uint32_t) (*addr + offset64);
3726 regcache_raw_read_unsigned (irp->regcache,
3727 irp->regmap[X86_RECORD_REBP_REGNUM],
3729 *addr = (uint32_t) (*addr + offset64);
3730 regcache_raw_read_unsigned (irp->regcache,
3731 irp->regmap[X86_RECORD_RESI_REGNUM],
3733 *addr = (uint32_t) (*addr + offset64);
3736 regcache_raw_read_unsigned (irp->regcache,
3737 irp->regmap[X86_RECORD_REBP_REGNUM],
3739 *addr = (uint32_t) (*addr + offset64);
3740 regcache_raw_read_unsigned (irp->regcache,
3741 irp->regmap[X86_RECORD_REDI_REGNUM],
3743 *addr = (uint32_t) (*addr + offset64);
3746 regcache_raw_read_unsigned (irp->regcache,
3747 irp->regmap[X86_RECORD_RESI_REGNUM],
3749 *addr = (uint32_t) (*addr + offset64);
3752 regcache_raw_read_unsigned (irp->regcache,
3753 irp->regmap[X86_RECORD_REDI_REGNUM],
3755 *addr = (uint32_t) (*addr + offset64);
3758 regcache_raw_read_unsigned (irp->regcache,
3759 irp->regmap[X86_RECORD_REBP_REGNUM],
3761 *addr = (uint32_t) (*addr + offset64);
3764 regcache_raw_read_unsigned (irp->regcache,
3765 irp->regmap[X86_RECORD_REBX_REGNUM],
3767 *addr = (uint32_t) (*addr + offset64);
3777 /* Record the value of the memory that willbe changed in current instruction
3778 to "record_arch_list".
3779 Return -1 if something wrong. */
3782 i386_record_lea_modrm (struct i386_record_s *irp)
3784 struct gdbarch *gdbarch = irp->gdbarch;
3787 if (irp->override >= 0)
3789 if (record_memory_query)
3793 target_terminal_ours ();
3795 Process record ignores the memory change of instruction at address %s\n\
3796 because it can't get the value of the segment register.\n\
3797 Do you want to stop the program?"),
3798 paddress (gdbarch, irp->orig_addr));
3799 target_terminal_inferior ();
3807 if (i386_record_lea_modrm_addr (irp, &addr))
3810 if (record_arch_list_add_mem (addr, 1 << irp->ot))
3816 /* Record the push operation to "record_arch_list".
3817 Return -1 if something wrong. */
3820 i386_record_push (struct i386_record_s *irp, int size)
3824 if (record_arch_list_add_reg (irp->regcache,
3825 irp->regmap[X86_RECORD_RESP_REGNUM]))
3827 regcache_raw_read_unsigned (irp->regcache,
3828 irp->regmap[X86_RECORD_RESP_REGNUM],
3830 if (record_arch_list_add_mem ((CORE_ADDR) addr - size, size))
3837 /* Defines contents to record. */
3838 #define I386_SAVE_FPU_REGS 0xfffd
3839 #define I386_SAVE_FPU_ENV 0xfffe
3840 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3842 /* Record the value of floating point registers which will be changed
3843 by the current instruction to "record_arch_list". Return -1 if
3844 something is wrong. */
3846 static int i386_record_floats (struct gdbarch *gdbarch,
3847 struct i386_record_s *ir,
3850 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3853 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3854 happen. Currently we store st0-st7 registers, but we need not store all
3855 registers all the time, in future we use ftag register and record only
3856 those who are not marked as an empty. */
3858 if (I386_SAVE_FPU_REGS == iregnum)
3860 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
3862 if (record_arch_list_add_reg (ir->regcache, i))
3866 else if (I386_SAVE_FPU_ENV == iregnum)
3868 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3870 if (record_arch_list_add_reg (ir->regcache, i))
3874 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
3876 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3878 if (record_arch_list_add_reg (ir->regcache, i))
3882 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
3883 (iregnum <= I387_FOP_REGNUM (tdep)))
3885 if (record_arch_list_add_reg (ir->regcache,iregnum))
3890 /* Parameter error. */
3893 if(I386_SAVE_FPU_ENV != iregnum)
3895 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3897 if (record_arch_list_add_reg (ir->regcache, i))
3904 /* Parse the current instruction and record the values of the registers and
3905 memory that will be changed in current instruction to "record_arch_list".
3906 Return -1 if something wrong. */
3908 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3909 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3912 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
3913 CORE_ADDR input_addr)
3915 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3921 gdb_byte buf[MAX_REGISTER_SIZE];
3922 struct i386_record_s ir;
3923 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3928 memset (&ir, 0, sizeof (struct i386_record_s));
3929 ir.regcache = regcache;
3930 ir.addr = input_addr;
3931 ir.orig_addr = input_addr;
3935 ir.popl_esp_hack = 0;
3936 ir.regmap = tdep->record_regmap;
3937 ir.gdbarch = gdbarch;
3939 if (record_debug > 1)
3940 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
3942 paddress (gdbarch, ir.addr));
3947 if (target_read_memory (ir.addr, &opcode8, 1))
3950 printf_unfiltered (_("Process record: error reading memory at "
3951 "addr %s len = 1.\n"),
3952 paddress (gdbarch, ir.addr));
3956 switch (opcode8) /* Instruction prefixes */
3958 case REPE_PREFIX_OPCODE:
3959 prefixes |= PREFIX_REPZ;
3961 case REPNE_PREFIX_OPCODE:
3962 prefixes |= PREFIX_REPNZ;
3964 case LOCK_PREFIX_OPCODE:
3965 prefixes |= PREFIX_LOCK;
3967 case CS_PREFIX_OPCODE:
3968 ir.override = X86_RECORD_CS_REGNUM;
3970 case SS_PREFIX_OPCODE:
3971 ir.override = X86_RECORD_SS_REGNUM;
3973 case DS_PREFIX_OPCODE:
3974 ir.override = X86_RECORD_DS_REGNUM;
3976 case ES_PREFIX_OPCODE:
3977 ir.override = X86_RECORD_ES_REGNUM;
3979 case FS_PREFIX_OPCODE:
3980 ir.override = X86_RECORD_FS_REGNUM;
3982 case GS_PREFIX_OPCODE:
3983 ir.override = X86_RECORD_GS_REGNUM;
3985 case DATA_PREFIX_OPCODE:
3986 prefixes |= PREFIX_DATA;
3988 case ADDR_PREFIX_OPCODE:
3989 prefixes |= PREFIX_ADDR;
3991 case 0x40: /* i386 inc %eax */
3992 case 0x41: /* i386 inc %ecx */
3993 case 0x42: /* i386 inc %edx */
3994 case 0x43: /* i386 inc %ebx */
3995 case 0x44: /* i386 inc %esp */
3996 case 0x45: /* i386 inc %ebp */
3997 case 0x46: /* i386 inc %esi */
3998 case 0x47: /* i386 inc %edi */
3999 case 0x48: /* i386 dec %eax */
4000 case 0x49: /* i386 dec %ecx */
4001 case 0x4a: /* i386 dec %edx */
4002 case 0x4b: /* i386 dec %ebx */
4003 case 0x4c: /* i386 dec %esp */
4004 case 0x4d: /* i386 dec %ebp */
4005 case 0x4e: /* i386 dec %esi */
4006 case 0x4f: /* i386 dec %edi */
4007 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
4011 rex_w = (opcode8 >> 3) & 1;
4012 rex_r = (opcode8 & 0x4) << 1;
4013 ir.rex_x = (opcode8 & 0x2) << 2;
4014 ir.rex_b = (opcode8 & 0x1) << 3;
4016 else /* 32 bit target */
4025 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
4031 if (prefixes & PREFIX_DATA)
4034 if (prefixes & PREFIX_ADDR)
4036 else if (ir.regmap[X86_RECORD_R8_REGNUM])
4039 /* Now check op code. */
4040 opcode = (uint32_t) opcode8;
4045 if (target_read_memory (ir.addr, &opcode8, 1))
4048 printf_unfiltered (_("Process record: error reading memory at "
4049 "addr %s len = 1.\n"),
4050 paddress (gdbarch, ir.addr));
4054 opcode = (uint32_t) opcode8 | 0x0f00;
4058 case 0x00: /* arith & logic */
4106 if (((opcode >> 3) & 7) != OP_CMPL)
4108 if ((opcode & 1) == 0)
4111 ir.ot = ir.dflag + OT_WORD;
4113 switch ((opcode >> 1) & 3)
4115 case 0: /* OP Ev, Gv */
4116 if (i386_record_modrm (&ir))
4120 if (i386_record_lea_modrm (&ir))
4126 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4128 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4131 case 1: /* OP Gv, Ev */
4132 if (i386_record_modrm (&ir))
4135 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4137 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4139 case 2: /* OP A, Iv */
4140 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4144 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4147 case 0x80: /* GRP1 */
4151 if (i386_record_modrm (&ir))
4154 if (ir.reg != OP_CMPL)
4156 if ((opcode & 1) == 0)
4159 ir.ot = ir.dflag + OT_WORD;
4166 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4167 if (i386_record_lea_modrm (&ir))
4171 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
4173 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4176 case 0x40: /* inc */
4185 case 0x48: /* dec */
4194 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7);
4195 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4198 case 0xf6: /* GRP3 */
4200 if ((opcode & 1) == 0)
4203 ir.ot = ir.dflag + OT_WORD;
4204 if (i386_record_modrm (&ir))
4207 if (ir.mod != 3 && ir.reg == 0)
4208 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4213 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4219 if (i386_record_lea_modrm (&ir))
4225 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4227 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4229 if (ir.reg == 3) /* neg */
4230 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4236 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4237 if (ir.ot != OT_BYTE)
4238 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
4239 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4243 opcode = opcode << 8 | ir.modrm;
4249 case 0xfe: /* GRP4 */
4250 case 0xff: /* GRP5 */
4251 if (i386_record_modrm (&ir))
4253 if (ir.reg >= 2 && opcode == 0xfe)
4256 opcode = opcode << 8 | ir.modrm;
4263 if ((opcode & 1) == 0)
4266 ir.ot = ir.dflag + OT_WORD;
4269 if (i386_record_lea_modrm (&ir))
4275 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4277 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4279 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4282 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4284 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4286 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4289 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
4290 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4292 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4296 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4299 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4301 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4306 opcode = opcode << 8 | ir.modrm;
4312 case 0x84: /* test */
4316 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4319 case 0x98: /* CWDE/CBW */
4320 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4323 case 0x99: /* CDQ/CWD */
4324 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4325 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
4328 case 0x0faf: /* imul */
4331 ir.ot = ir.dflag + OT_WORD;
4332 if (i386_record_modrm (&ir))
4335 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4336 else if (opcode == 0x6b)
4339 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4341 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4342 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4345 case 0x0fc0: /* xadd */
4347 if ((opcode & 1) == 0)
4350 ir.ot = ir.dflag + OT_WORD;
4351 if (i386_record_modrm (&ir))
4356 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4358 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4359 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4361 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4365 if (i386_record_lea_modrm (&ir))
4367 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4369 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4371 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4374 case 0x0fb0: /* cmpxchg */
4376 if ((opcode & 1) == 0)
4379 ir.ot = ir.dflag + OT_WORD;
4380 if (i386_record_modrm (&ir))
4385 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4386 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4388 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4392 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4393 if (i386_record_lea_modrm (&ir))
4396 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4399 case 0x0fc7: /* cmpxchg8b */
4400 if (i386_record_modrm (&ir))
4405 opcode = opcode << 8 | ir.modrm;
4408 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4409 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
4410 if (i386_record_lea_modrm (&ir))
4412 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4415 case 0x50: /* push */
4425 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4427 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4431 case 0x06: /* push es */
4432 case 0x0e: /* push cs */
4433 case 0x16: /* push ss */
4434 case 0x1e: /* push ds */
4435 if (ir.regmap[X86_RECORD_R8_REGNUM])
4440 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4444 case 0x0fa0: /* push fs */
4445 case 0x0fa8: /* push gs */
4446 if (ir.regmap[X86_RECORD_R8_REGNUM])
4451 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4455 case 0x60: /* pusha */
4456 if (ir.regmap[X86_RECORD_R8_REGNUM])
4461 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
4465 case 0x58: /* pop */
4473 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4474 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
4477 case 0x61: /* popa */
4478 if (ir.regmap[X86_RECORD_R8_REGNUM])
4483 for (regnum = X86_RECORD_REAX_REGNUM;
4484 regnum <= X86_RECORD_REDI_REGNUM;
4486 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
4489 case 0x8f: /* pop */
4490 if (ir.regmap[X86_RECORD_R8_REGNUM])
4491 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
4493 ir.ot = ir.dflag + OT_WORD;
4494 if (i386_record_modrm (&ir))
4497 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
4500 ir.popl_esp_hack = 1 << ir.ot;
4501 if (i386_record_lea_modrm (&ir))
4504 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4507 case 0xc8: /* enter */
4508 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
4509 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4511 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4515 case 0xc9: /* leave */
4516 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4517 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
4520 case 0x07: /* pop es */
4521 if (ir.regmap[X86_RECORD_R8_REGNUM])
4526 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4527 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
4528 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4531 case 0x17: /* pop ss */
4532 if (ir.regmap[X86_RECORD_R8_REGNUM])
4537 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4538 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
4539 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4542 case 0x1f: /* pop ds */
4543 if (ir.regmap[X86_RECORD_R8_REGNUM])
4548 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4549 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
4550 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4553 case 0x0fa1: /* pop fs */
4554 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4555 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
4556 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4559 case 0x0fa9: /* pop gs */
4560 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4561 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
4562 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4565 case 0x88: /* mov */
4569 if ((opcode & 1) == 0)
4572 ir.ot = ir.dflag + OT_WORD;
4574 if (i386_record_modrm (&ir))
4579 if (opcode == 0xc6 || opcode == 0xc7)
4580 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4581 if (i386_record_lea_modrm (&ir))
4586 if (opcode == 0xc6 || opcode == 0xc7)
4588 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4590 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4594 case 0x8a: /* mov */
4596 if ((opcode & 1) == 0)
4599 ir.ot = ir.dflag + OT_WORD;
4600 if (i386_record_modrm (&ir))
4603 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4605 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4608 case 0x8c: /* mov seg */
4609 if (i386_record_modrm (&ir))
4614 opcode = opcode << 8 | ir.modrm;
4619 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4623 if (i386_record_lea_modrm (&ir))
4628 case 0x8e: /* mov seg */
4629 if (i386_record_modrm (&ir))
4634 regnum = X86_RECORD_ES_REGNUM;
4637 regnum = X86_RECORD_SS_REGNUM;
4640 regnum = X86_RECORD_DS_REGNUM;
4643 regnum = X86_RECORD_FS_REGNUM;
4646 regnum = X86_RECORD_GS_REGNUM;
4650 opcode = opcode << 8 | ir.modrm;
4654 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
4655 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4658 case 0x0fb6: /* movzbS */
4659 case 0x0fb7: /* movzwS */
4660 case 0x0fbe: /* movsbS */
4661 case 0x0fbf: /* movswS */
4662 if (i386_record_modrm (&ir))
4664 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
4667 case 0x8d: /* lea */
4668 if (i386_record_modrm (&ir))
4673 opcode = opcode << 8 | ir.modrm;
4678 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4680 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4683 case 0xa0: /* mov EAX */
4686 case 0xd7: /* xlat */
4687 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4690 case 0xa2: /* mov EAX */
4692 if (ir.override >= 0)
4694 if (record_memory_query)
4698 target_terminal_ours ();
4700 Process record ignores the memory change of instruction at address %s\n\
4701 because it can't get the value of the segment register.\n\
4702 Do you want to stop the program?"),
4703 paddress (gdbarch, ir.orig_addr));
4704 target_terminal_inferior ();
4711 if ((opcode & 1) == 0)
4714 ir.ot = ir.dflag + OT_WORD;
4717 if (target_read_memory (ir.addr, buf, 8))
4720 printf_unfiltered (_("Process record: error reading "
4721 "memory at addr 0x%s len = 8.\n"),
4722 paddress (gdbarch, ir.addr));
4726 addr = extract_unsigned_integer (buf, 8, byte_order);
4730 if (target_read_memory (ir.addr, buf, 4))
4733 printf_unfiltered (_("Process record: error reading "
4734 "memory at addr 0x%s len = 4.\n"),
4735 paddress (gdbarch, ir.addr));
4739 addr = extract_unsigned_integer (buf, 4, byte_order);
4743 if (target_read_memory (ir.addr, buf, 2))
4746 printf_unfiltered (_("Process record: error reading "
4747 "memory at addr 0x%s len = 2.\n"),
4748 paddress (gdbarch, ir.addr));
4752 addr = extract_unsigned_integer (buf, 2, byte_order);
4754 if (record_arch_list_add_mem (addr, 1 << ir.ot))
4759 case 0xb0: /* mov R, Ib */
4767 I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
4768 ? ((opcode & 0x7) | ir.rex_b)
4769 : ((opcode & 0x7) & 0x3));
4772 case 0xb8: /* mov R, Iv */
4780 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
4783 case 0x91: /* xchg R, EAX */
4790 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4791 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7);
4794 case 0x86: /* xchg Ev, Gv */
4796 if ((opcode & 1) == 0)
4799 ir.ot = ir.dflag + OT_WORD;
4800 if (i386_record_modrm (&ir))
4805 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4807 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4811 if (i386_record_lea_modrm (&ir))
4815 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4817 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4820 case 0xc4: /* les Gv */
4821 case 0xc5: /* lds Gv */
4822 if (ir.regmap[X86_RECORD_R8_REGNUM])
4828 case 0x0fb2: /* lss Gv */
4829 case 0x0fb4: /* lfs Gv */
4830 case 0x0fb5: /* lgs Gv */
4831 if (i386_record_modrm (&ir))
4839 opcode = opcode << 8 | ir.modrm;
4844 case 0xc4: /* les Gv */
4845 regnum = X86_RECORD_ES_REGNUM;
4847 case 0xc5: /* lds Gv */
4848 regnum = X86_RECORD_DS_REGNUM;
4850 case 0x0fb2: /* lss Gv */
4851 regnum = X86_RECORD_SS_REGNUM;
4853 case 0x0fb4: /* lfs Gv */
4854 regnum = X86_RECORD_FS_REGNUM;
4856 case 0x0fb5: /* lgs Gv */
4857 regnum = X86_RECORD_GS_REGNUM;
4860 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
4861 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
4862 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4865 case 0xc0: /* shifts */
4871 if ((opcode & 1) == 0)
4874 ir.ot = ir.dflag + OT_WORD;
4875 if (i386_record_modrm (&ir))
4877 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
4879 if (i386_record_lea_modrm (&ir))
4885 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4887 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4889 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4896 if (i386_record_modrm (&ir))
4900 if (record_arch_list_add_reg (ir.regcache, ir.rm))
4905 if (i386_record_lea_modrm (&ir))
4910 case 0xd8: /* Floats. */
4918 if (i386_record_modrm (&ir))
4920 ir.reg |= ((opcode & 7) << 3);
4926 if (i386_record_lea_modrm_addr (&ir, &addr64))
4934 /* For fcom, ficom nothing to do. */
4940 /* For fcomp, ficomp pop FPU stack, store all. */
4941 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4968 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
4969 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
4970 of code, always affects st(0) register. */
4971 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
4995 /* Handling fld, fild. */
4996 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5000 switch (ir.reg >> 4)
5003 if (record_arch_list_add_mem (addr64, 4))
5007 if (record_arch_list_add_mem (addr64, 8))
5013 if (record_arch_list_add_mem (addr64, 2))
5019 switch (ir.reg >> 4)
5022 if (record_arch_list_add_mem (addr64, 4))
5024 if (3 == (ir.reg & 7))
5026 /* For fstp m32fp. */
5027 if (i386_record_floats (gdbarch, &ir,
5028 I386_SAVE_FPU_REGS))
5033 if (record_arch_list_add_mem (addr64, 4))
5035 if ((3 == (ir.reg & 7))
5036 || (5 == (ir.reg & 7))
5037 || (7 == (ir.reg & 7)))
5039 /* For fstp insn. */
5040 if (i386_record_floats (gdbarch, &ir,
5041 I386_SAVE_FPU_REGS))
5046 if (record_arch_list_add_mem (addr64, 8))
5048 if (3 == (ir.reg & 7))
5050 /* For fstp m64fp. */
5051 if (i386_record_floats (gdbarch, &ir,
5052 I386_SAVE_FPU_REGS))
5057 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
5059 /* For fistp, fbld, fild, fbstp. */
5060 if (i386_record_floats (gdbarch, &ir,
5061 I386_SAVE_FPU_REGS))
5066 if (record_arch_list_add_mem (addr64, 2))
5075 if (i386_record_floats (gdbarch, &ir,
5076 I386_SAVE_FPU_ENV_REG_STACK))
5081 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
5086 if (i386_record_floats (gdbarch, &ir,
5087 I386_SAVE_FPU_ENV_REG_STACK))
5093 if (record_arch_list_add_mem (addr64, 28))
5098 if (record_arch_list_add_mem (addr64, 14))
5104 if (record_arch_list_add_mem (addr64, 2))
5106 /* Insn fstp, fbstp. */
5107 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5112 if (record_arch_list_add_mem (addr64, 10))
5118 if (record_arch_list_add_mem (addr64, 28))
5124 if (record_arch_list_add_mem (addr64, 14))
5128 if (record_arch_list_add_mem (addr64, 80))
5131 if (i386_record_floats (gdbarch, &ir,
5132 I386_SAVE_FPU_ENV_REG_STACK))
5136 if (record_arch_list_add_mem (addr64, 8))
5139 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5144 opcode = opcode << 8 | ir.modrm;
5149 /* Opcode is an extension of modR/M byte. */
5155 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
5159 if (0x0c == (ir.modrm >> 4))
5161 if ((ir.modrm & 0x0f) <= 7)
5163 if (i386_record_floats (gdbarch, &ir,
5164 I386_SAVE_FPU_REGS))
5169 if (i386_record_floats (gdbarch, &ir,
5170 I387_ST0_REGNUM (tdep)))
5172 /* If only st(0) is changing, then we have already
5174 if ((ir.modrm & 0x0f) - 0x08)
5176 if (i386_record_floats (gdbarch, &ir,
5177 I387_ST0_REGNUM (tdep) +
5178 ((ir.modrm & 0x0f) - 0x08)))
5196 if (i386_record_floats (gdbarch, &ir,
5197 I387_ST0_REGNUM (tdep)))
5215 if (i386_record_floats (gdbarch, &ir,
5216 I386_SAVE_FPU_REGS))
5220 if (i386_record_floats (gdbarch, &ir,
5221 I387_ST0_REGNUM (tdep)))
5223 if (i386_record_floats (gdbarch, &ir,
5224 I387_ST0_REGNUM (tdep) + 1))
5231 if (0xe9 == ir.modrm)
5233 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5236 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
5238 if (i386_record_floats (gdbarch, &ir,
5239 I387_ST0_REGNUM (tdep)))
5241 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
5243 if (i386_record_floats (gdbarch, &ir,
5244 I387_ST0_REGNUM (tdep) +
5248 else if ((ir.modrm & 0x0f) - 0x08)
5250 if (i386_record_floats (gdbarch, &ir,
5251 I387_ST0_REGNUM (tdep) +
5252 ((ir.modrm & 0x0f) - 0x08)))
5258 if (0xe3 == ir.modrm)
5260 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
5263 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
5265 if (i386_record_floats (gdbarch, &ir,
5266 I387_ST0_REGNUM (tdep)))
5268 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
5270 if (i386_record_floats (gdbarch, &ir,
5271 I387_ST0_REGNUM (tdep) +
5275 else if ((ir.modrm & 0x0f) - 0x08)
5277 if (i386_record_floats (gdbarch, &ir,
5278 I387_ST0_REGNUM (tdep) +
5279 ((ir.modrm & 0x0f) - 0x08)))
5285 if ((0x0c == ir.modrm >> 4)
5286 || (0x0d == ir.modrm >> 4)
5287 || (0x0f == ir.modrm >> 4))
5289 if ((ir.modrm & 0x0f) <= 7)
5291 if (i386_record_floats (gdbarch, &ir,
5292 I387_ST0_REGNUM (tdep) +
5298 if (i386_record_floats (gdbarch, &ir,
5299 I387_ST0_REGNUM (tdep) +
5300 ((ir.modrm & 0x0f) - 0x08)))
5306 if (0x0c == ir.modrm >> 4)
5308 if (i386_record_floats (gdbarch, &ir,
5309 I387_FTAG_REGNUM (tdep)))
5312 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
5314 if ((ir.modrm & 0x0f) <= 7)
5316 if (i386_record_floats (gdbarch, &ir,
5317 I387_ST0_REGNUM (tdep) +
5323 if (i386_record_floats (gdbarch, &ir,
5324 I386_SAVE_FPU_REGS))
5330 if ((0x0c == ir.modrm >> 4)
5331 || (0x0e == ir.modrm >> 4)
5332 || (0x0f == ir.modrm >> 4)
5333 || (0xd9 == ir.modrm))
5335 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5340 if (0xe0 == ir.modrm)
5342 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
5345 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
5347 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5355 case 0xa4: /* movsS */
5357 case 0xaa: /* stosS */
5359 case 0x6c: /* insS */
5361 regcache_raw_read_unsigned (ir.regcache,
5362 ir.regmap[X86_RECORD_RECX_REGNUM],
5368 if ((opcode & 1) == 0)
5371 ir.ot = ir.dflag + OT_WORD;
5372 regcache_raw_read_unsigned (ir.regcache,
5373 ir.regmap[X86_RECORD_REDI_REGNUM],
5376 regcache_raw_read_unsigned (ir.regcache,
5377 ir.regmap[X86_RECORD_ES_REGNUM],
5379 regcache_raw_read_unsigned (ir.regcache,
5380 ir.regmap[X86_RECORD_DS_REGNUM],
5382 if (ir.aflag && (es != ds))
5384 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5385 if (record_memory_query)
5389 target_terminal_ours ();
5391 Process record ignores the memory change of instruction at address %s\n\
5392 because it can't get the value of the segment register.\n\
5393 Do you want to stop the program?"),
5394 paddress (gdbarch, ir.orig_addr));
5395 target_terminal_inferior ();
5402 if (record_arch_list_add_mem (addr, 1 << ir.ot))
5406 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5407 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5408 if (opcode == 0xa4 || opcode == 0xa5)
5409 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5410 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5411 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5415 case 0xa6: /* cmpsS */
5417 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5418 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5419 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5420 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5421 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5424 case 0xac: /* lodsS */
5426 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5427 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5428 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5429 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5430 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5433 case 0xae: /* scasS */
5435 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5436 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5437 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5438 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5441 case 0x6e: /* outsS */
5443 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5444 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5445 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5446 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5449 case 0xe4: /* port I/O */
5453 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5454 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5464 case 0xc2: /* ret im */
5465 case 0xc3: /* ret */
5466 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5467 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5470 case 0xca: /* lret im */
5471 case 0xcb: /* lret */
5472 case 0xcf: /* iret */
5473 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5474 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5475 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5478 case 0xe8: /* call im */
5479 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5481 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5485 case 0x9a: /* lcall im */
5486 if (ir.regmap[X86_RECORD_R8_REGNUM])
5491 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5492 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5496 case 0xe9: /* jmp im */
5497 case 0xea: /* ljmp im */
5498 case 0xeb: /* jmp Jb */
5499 case 0x70: /* jcc Jb */
5515 case 0x0f80: /* jcc Jv */
5533 case 0x0f90: /* setcc Gv */
5549 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5551 if (i386_record_modrm (&ir))
5554 I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
5558 if (i386_record_lea_modrm (&ir))
5563 case 0x0f40: /* cmov Gv, Ev */
5579 if (i386_record_modrm (&ir))
5582 if (ir.dflag == OT_BYTE)
5584 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
5588 case 0x9c: /* pushf */
5589 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5590 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5592 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5596 case 0x9d: /* popf */
5597 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5598 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5601 case 0x9e: /* sahf */
5602 if (ir.regmap[X86_RECORD_R8_REGNUM])
5608 case 0xf5: /* cmc */
5609 case 0xf8: /* clc */
5610 case 0xf9: /* stc */
5611 case 0xfc: /* cld */
5612 case 0xfd: /* std */
5613 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5616 case 0x9f: /* lahf */
5617 if (ir.regmap[X86_RECORD_R8_REGNUM])
5622 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5623 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5626 /* bit operations */
5627 case 0x0fba: /* bt/bts/btr/btc Gv, im */
5628 ir.ot = ir.dflag + OT_WORD;
5629 if (i386_record_modrm (&ir))
5634 opcode = opcode << 8 | ir.modrm;
5640 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5643 if (i386_record_lea_modrm (&ir))
5647 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5650 case 0x0fa3: /* bt Gv, Ev */
5651 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5654 case 0x0fab: /* bts */
5655 case 0x0fb3: /* btr */
5656 case 0x0fbb: /* btc */
5657 ir.ot = ir.dflag + OT_WORD;
5658 if (i386_record_modrm (&ir))
5661 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5665 if (i386_record_lea_modrm_addr (&ir, &addr64))
5667 regcache_raw_read_unsigned (ir.regcache,
5668 ir.regmap[ir.reg | rex_r],
5673 addr64 += ((int16_t) addr >> 4) << 4;
5676 addr64 += ((int32_t) addr >> 5) << 5;
5679 addr64 += ((int64_t) addr >> 6) << 6;
5682 if (record_arch_list_add_mem (addr64, 1 << ir.ot))
5684 if (i386_record_lea_modrm (&ir))
5687 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5690 case 0x0fbc: /* bsf */
5691 case 0x0fbd: /* bsr */
5692 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5693 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5697 case 0x27: /* daa */
5698 case 0x2f: /* das */
5699 case 0x37: /* aaa */
5700 case 0x3f: /* aas */
5701 case 0xd4: /* aam */
5702 case 0xd5: /* aad */
5703 if (ir.regmap[X86_RECORD_R8_REGNUM])
5708 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5709 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5713 case 0x90: /* nop */
5714 if (prefixes & PREFIX_LOCK)
5721 case 0x9b: /* fwait */
5722 if (target_read_memory (ir.addr, &opcode8, 1))
5725 printf_unfiltered (_("Process record: error reading memory at "
5726 "addr 0x%s len = 1.\n"),
5727 paddress (gdbarch, ir.addr));
5730 opcode = (uint32_t) opcode8;
5736 case 0xcc: /* int3 */
5737 printf_unfiltered (_("Process record does not support instruction "
5744 case 0xcd: /* int */
5748 if (target_read_memory (ir.addr, &interrupt, 1))
5751 printf_unfiltered (_("Process record: error reading memory "
5752 "at addr %s len = 1.\n"),
5753 paddress (gdbarch, ir.addr));
5757 if (interrupt != 0x80
5758 || tdep->i386_intx80_record == NULL)
5760 printf_unfiltered (_("Process record does not support "
5761 "instruction int 0x%02x.\n"),
5766 ret = tdep->i386_intx80_record (ir.regcache);
5773 case 0xce: /* into */
5774 printf_unfiltered (_("Process record does not support "
5775 "instruction into.\n"));
5780 case 0xfa: /* cli */
5781 case 0xfb: /* sti */
5784 case 0x62: /* bound */
5785 printf_unfiltered (_("Process record does not support "
5786 "instruction bound.\n"));
5791 case 0x0fc8: /* bswap reg */
5799 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
5802 case 0xd6: /* salc */
5803 if (ir.regmap[X86_RECORD_R8_REGNUM])
5808 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5809 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5812 case 0xe0: /* loopnz */
5813 case 0xe1: /* loopz */
5814 case 0xe2: /* loop */
5815 case 0xe3: /* jecxz */
5816 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5817 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5820 case 0x0f30: /* wrmsr */
5821 printf_unfiltered (_("Process record does not support "
5822 "instruction wrmsr.\n"));
5827 case 0x0f32: /* rdmsr */
5828 printf_unfiltered (_("Process record does not support "
5829 "instruction rdmsr.\n"));
5834 case 0x0f31: /* rdtsc */
5835 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5836 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5839 case 0x0f34: /* sysenter */
5842 if (ir.regmap[X86_RECORD_R8_REGNUM])
5847 if (tdep->i386_sysenter_record == NULL)
5849 printf_unfiltered (_("Process record does not support "
5850 "instruction sysenter.\n"));
5854 ret = tdep->i386_sysenter_record (ir.regcache);
5860 case 0x0f35: /* sysexit */
5861 printf_unfiltered (_("Process record does not support "
5862 "instruction sysexit.\n"));
5867 case 0x0f05: /* syscall */
5870 if (tdep->i386_syscall_record == NULL)
5872 printf_unfiltered (_("Process record does not support "
5873 "instruction syscall.\n"));
5877 ret = tdep->i386_syscall_record (ir.regcache);
5883 case 0x0f07: /* sysret */
5884 printf_unfiltered (_("Process record does not support "
5885 "instruction sysret.\n"));
5890 case 0x0fa2: /* cpuid */
5891 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5892 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5893 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5894 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
5897 case 0xf4: /* hlt */
5898 printf_unfiltered (_("Process record does not support "
5899 "instruction hlt.\n"));
5905 if (i386_record_modrm (&ir))
5912 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5916 if (i386_record_lea_modrm (&ir))
5925 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5929 opcode = opcode << 8 | ir.modrm;
5936 if (i386_record_modrm (&ir))
5947 opcode = opcode << 8 | ir.modrm;
5950 if (ir.override >= 0)
5952 if (record_memory_query)
5956 target_terminal_ours ();
5958 Process record ignores the memory change of instruction at address %s\n\
5959 because it can't get the value of the segment register.\n\
5960 Do you want to stop the program?"),
5961 paddress (gdbarch, ir.orig_addr));
5962 target_terminal_inferior ();
5969 if (i386_record_lea_modrm_addr (&ir, &addr64))
5971 if (record_arch_list_add_mem (addr64, 2))
5974 if (ir.regmap[X86_RECORD_R8_REGNUM])
5976 if (record_arch_list_add_mem (addr64, 8))
5981 if (record_arch_list_add_mem (addr64, 4))
5992 case 0: /* monitor */
5995 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5999 opcode = opcode << 8 | ir.modrm;
6007 if (ir.override >= 0)
6009 if (record_memory_query)
6013 target_terminal_ours ();
6015 Process record ignores the memory change of instruction at address %s\n\
6016 because it can't get the value of the segment register.\n\
6017 Do you want to stop the program?"),
6018 paddress (gdbarch, ir.orig_addr));
6019 target_terminal_inferior ();
6028 if (i386_record_lea_modrm_addr (&ir, &addr64))
6030 if (record_arch_list_add_mem (addr64, 2))
6033 if (ir.regmap[X86_RECORD_R8_REGNUM])
6035 if (record_arch_list_add_mem (addr64, 8))
6040 if (record_arch_list_add_mem (addr64, 4))
6052 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6053 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6057 else if (ir.rm == 1)
6064 opcode = opcode << 8 | ir.modrm;
6071 if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
6077 if (i386_record_lea_modrm (&ir))
6080 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6083 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6085 case 7: /* invlpg */
6088 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
6089 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
6093 opcode = opcode << 8 | ir.modrm;
6098 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6102 opcode = opcode << 8 | ir.modrm;
6108 case 0x0f08: /* invd */
6109 case 0x0f09: /* wbinvd */
6112 case 0x63: /* arpl */
6113 if (i386_record_modrm (&ir))
6115 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
6117 I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
6118 ? (ir.reg | rex_r) : ir.rm);
6122 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
6123 if (i386_record_lea_modrm (&ir))
6126 if (!ir.regmap[X86_RECORD_R8_REGNUM])
6127 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6130 case 0x0f02: /* lar */
6131 case 0x0f03: /* lsl */
6132 if (i386_record_modrm (&ir))
6134 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6135 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6139 if (i386_record_modrm (&ir))
6141 if (ir.mod == 3 && ir.reg == 3)
6144 opcode = opcode << 8 | ir.modrm;
6156 /* nop (multi byte) */
6159 case 0x0f20: /* mov reg, crN */
6160 case 0x0f22: /* mov crN, reg */
6161 if (i386_record_modrm (&ir))
6163 if ((ir.modrm & 0xc0) != 0xc0)
6166 opcode = opcode << 8 | ir.modrm;
6177 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6179 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6183 opcode = opcode << 8 | ir.modrm;
6189 case 0x0f21: /* mov reg, drN */
6190 case 0x0f23: /* mov drN, reg */
6191 if (i386_record_modrm (&ir))
6193 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
6194 || ir.reg == 5 || ir.reg >= 8)
6197 opcode = opcode << 8 | ir.modrm;
6201 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6203 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6206 case 0x0f06: /* clts */
6207 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6210 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
6212 case 0x0f0d: /* 3DNow! prefetch */
6215 case 0x0f0e: /* 3DNow! femms */
6216 case 0x0f77: /* emms */
6217 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
6219 record_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
6222 case 0x0f0f: /* 3DNow! data */
6223 if (i386_record_modrm (&ir))
6225 if (target_read_memory (ir.addr, &opcode8, 1))
6227 printf_unfiltered (_("Process record: error reading memory at "
6228 "addr %s len = 1.\n"),
6229 paddress (gdbarch, ir.addr));
6235 case 0x0c: /* 3DNow! pi2fw */
6236 case 0x0d: /* 3DNow! pi2fd */
6237 case 0x1c: /* 3DNow! pf2iw */
6238 case 0x1d: /* 3DNow! pf2id */
6239 case 0x8a: /* 3DNow! pfnacc */
6240 case 0x8e: /* 3DNow! pfpnacc */
6241 case 0x90: /* 3DNow! pfcmpge */
6242 case 0x94: /* 3DNow! pfmin */
6243 case 0x96: /* 3DNow! pfrcp */
6244 case 0x97: /* 3DNow! pfrsqrt */
6245 case 0x9a: /* 3DNow! pfsub */
6246 case 0x9e: /* 3DNow! pfadd */
6247 case 0xa0: /* 3DNow! pfcmpgt */
6248 case 0xa4: /* 3DNow! pfmax */
6249 case 0xa6: /* 3DNow! pfrcpit1 */
6250 case 0xa7: /* 3DNow! pfrsqit1 */
6251 case 0xaa: /* 3DNow! pfsubr */
6252 case 0xae: /* 3DNow! pfacc */
6253 case 0xb0: /* 3DNow! pfcmpeq */
6254 case 0xb4: /* 3DNow! pfmul */
6255 case 0xb6: /* 3DNow! pfrcpit2 */
6256 case 0xb7: /* 3DNow! pmulhrw */
6257 case 0xbb: /* 3DNow! pswapd */
6258 case 0xbf: /* 3DNow! pavgusb */
6259 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
6260 goto no_support_3dnow_data;
6261 record_arch_list_add_reg (ir.regcache, ir.reg);
6265 no_support_3dnow_data:
6266 opcode = (opcode << 8) | opcode8;
6272 case 0x0faa: /* rsm */
6273 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6274 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6275 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6276 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6277 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
6278 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6279 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
6280 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6281 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6285 if (i386_record_modrm (&ir))
6289 case 0: /* fxsave */
6293 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6294 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
6296 if (record_arch_list_add_mem (tmpu64, 512))
6301 case 1: /* fxrstor */
6305 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6307 for (i = I387_MM0_REGNUM (tdep);
6308 i386_mmx_regnum_p (gdbarch, i); i++)
6309 record_arch_list_add_reg (ir.regcache, i);
6311 for (i = I387_XMM0_REGNUM (tdep);
6312 i386_xmm_regnum_p (gdbarch, i); i++)
6313 record_arch_list_add_reg (ir.regcache, i);
6315 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
6316 record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
6318 for (i = I387_ST0_REGNUM (tdep);
6319 i386_fp_regnum_p (gdbarch, i); i++)
6320 record_arch_list_add_reg (ir.regcache, i);
6322 for (i = I387_FCTRL_REGNUM (tdep);
6323 i386_fpc_regnum_p (gdbarch, i); i++)
6324 record_arch_list_add_reg (ir.regcache, i);
6328 case 2: /* ldmxcsr */
6329 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
6331 record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
6334 case 3: /* stmxcsr */
6336 if (i386_record_lea_modrm (&ir))
6340 case 5: /* lfence */
6341 case 6: /* mfence */
6342 case 7: /* sfence clflush */
6346 opcode = (opcode << 8) | ir.modrm;
6352 case 0x0fc3: /* movnti */
6353 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
6354 if (i386_record_modrm (&ir))
6359 if (i386_record_lea_modrm (&ir))
6363 /* Add prefix to opcode. */
6490 reswitch_prefix_add:
6498 if (target_read_memory (ir.addr, &opcode8, 1))
6500 printf_unfiltered (_("Process record: error reading memory at "
6501 "addr %s len = 1.\n"),
6502 paddress (gdbarch, ir.addr));
6506 opcode = (uint32_t) opcode8 | opcode << 8;
6507 goto reswitch_prefix_add;
6510 case 0x0f10: /* movups */
6511 case 0x660f10: /* movupd */
6512 case 0xf30f10: /* movss */
6513 case 0xf20f10: /* movsd */
6514 case 0x0f12: /* movlps */
6515 case 0x660f12: /* movlpd */
6516 case 0xf30f12: /* movsldup */
6517 case 0xf20f12: /* movddup */
6518 case 0x0f14: /* unpcklps */
6519 case 0x660f14: /* unpcklpd */
6520 case 0x0f15: /* unpckhps */
6521 case 0x660f15: /* unpckhpd */
6522 case 0x0f16: /* movhps */
6523 case 0x660f16: /* movhpd */
6524 case 0xf30f16: /* movshdup */
6525 case 0x0f28: /* movaps */
6526 case 0x660f28: /* movapd */
6527 case 0x0f2a: /* cvtpi2ps */
6528 case 0x660f2a: /* cvtpi2pd */
6529 case 0xf30f2a: /* cvtsi2ss */
6530 case 0xf20f2a: /* cvtsi2sd */
6531 case 0x0f2c: /* cvttps2pi */
6532 case 0x660f2c: /* cvttpd2pi */
6533 case 0x0f2d: /* cvtps2pi */
6534 case 0x660f2d: /* cvtpd2pi */
6535 case 0x660f3800: /* pshufb */
6536 case 0x660f3801: /* phaddw */
6537 case 0x660f3802: /* phaddd */
6538 case 0x660f3803: /* phaddsw */
6539 case 0x660f3804: /* pmaddubsw */
6540 case 0x660f3805: /* phsubw */
6541 case 0x660f3806: /* phsubd */
6542 case 0x660f3807: /* phsubsw */
6543 case 0x660f3808: /* psignb */
6544 case 0x660f3809: /* psignw */
6545 case 0x660f380a: /* psignd */
6546 case 0x660f380b: /* pmulhrsw */
6547 case 0x660f3810: /* pblendvb */
6548 case 0x660f3814: /* blendvps */
6549 case 0x660f3815: /* blendvpd */
6550 case 0x660f381c: /* pabsb */
6551 case 0x660f381d: /* pabsw */
6552 case 0x660f381e: /* pabsd */
6553 case 0x660f3820: /* pmovsxbw */
6554 case 0x660f3821: /* pmovsxbd */
6555 case 0x660f3822: /* pmovsxbq */
6556 case 0x660f3823: /* pmovsxwd */
6557 case 0x660f3824: /* pmovsxwq */
6558 case 0x660f3825: /* pmovsxdq */
6559 case 0x660f3828: /* pmuldq */
6560 case 0x660f3829: /* pcmpeqq */
6561 case 0x660f382a: /* movntdqa */
6562 case 0x660f3a08: /* roundps */
6563 case 0x660f3a09: /* roundpd */
6564 case 0x660f3a0a: /* roundss */
6565 case 0x660f3a0b: /* roundsd */
6566 case 0x660f3a0c: /* blendps */
6567 case 0x660f3a0d: /* blendpd */
6568 case 0x660f3a0e: /* pblendw */
6569 case 0x660f3a0f: /* palignr */
6570 case 0x660f3a20: /* pinsrb */
6571 case 0x660f3a21: /* insertps */
6572 case 0x660f3a22: /* pinsrd pinsrq */
6573 case 0x660f3a40: /* dpps */
6574 case 0x660f3a41: /* dppd */
6575 case 0x660f3a42: /* mpsadbw */
6576 case 0x660f3a60: /* pcmpestrm */
6577 case 0x660f3a61: /* pcmpestri */
6578 case 0x660f3a62: /* pcmpistrm */
6579 case 0x660f3a63: /* pcmpistri */
6580 case 0x0f51: /* sqrtps */
6581 case 0x660f51: /* sqrtpd */
6582 case 0xf20f51: /* sqrtsd */
6583 case 0xf30f51: /* sqrtss */
6584 case 0x0f52: /* rsqrtps */
6585 case 0xf30f52: /* rsqrtss */
6586 case 0x0f53: /* rcpps */
6587 case 0xf30f53: /* rcpss */
6588 case 0x0f54: /* andps */
6589 case 0x660f54: /* andpd */
6590 case 0x0f55: /* andnps */
6591 case 0x660f55: /* andnpd */
6592 case 0x0f56: /* orps */
6593 case 0x660f56: /* orpd */
6594 case 0x0f57: /* xorps */
6595 case 0x660f57: /* xorpd */
6596 case 0x0f58: /* addps */
6597 case 0x660f58: /* addpd */
6598 case 0xf20f58: /* addsd */
6599 case 0xf30f58: /* addss */
6600 case 0x0f59: /* mulps */
6601 case 0x660f59: /* mulpd */
6602 case 0xf20f59: /* mulsd */
6603 case 0xf30f59: /* mulss */
6604 case 0x0f5a: /* cvtps2pd */
6605 case 0x660f5a: /* cvtpd2ps */
6606 case 0xf20f5a: /* cvtsd2ss */
6607 case 0xf30f5a: /* cvtss2sd */
6608 case 0x0f5b: /* cvtdq2ps */
6609 case 0x660f5b: /* cvtps2dq */
6610 case 0xf30f5b: /* cvttps2dq */
6611 case 0x0f5c: /* subps */
6612 case 0x660f5c: /* subpd */
6613 case 0xf20f5c: /* subsd */
6614 case 0xf30f5c: /* subss */
6615 case 0x0f5d: /* minps */
6616 case 0x660f5d: /* minpd */
6617 case 0xf20f5d: /* minsd */
6618 case 0xf30f5d: /* minss */
6619 case 0x0f5e: /* divps */
6620 case 0x660f5e: /* divpd */
6621 case 0xf20f5e: /* divsd */
6622 case 0xf30f5e: /* divss */
6623 case 0x0f5f: /* maxps */
6624 case 0x660f5f: /* maxpd */
6625 case 0xf20f5f: /* maxsd */
6626 case 0xf30f5f: /* maxss */
6627 case 0x660f60: /* punpcklbw */
6628 case 0x660f61: /* punpcklwd */
6629 case 0x660f62: /* punpckldq */
6630 case 0x660f63: /* packsswb */
6631 case 0x660f64: /* pcmpgtb */
6632 case 0x660f65: /* pcmpgtw */
6633 case 0x660f66: /* pcmpgtd */
6634 case 0x660f67: /* packuswb */
6635 case 0x660f68: /* punpckhbw */
6636 case 0x660f69: /* punpckhwd */
6637 case 0x660f6a: /* punpckhdq */
6638 case 0x660f6b: /* packssdw */
6639 case 0x660f6c: /* punpcklqdq */
6640 case 0x660f6d: /* punpckhqdq */
6641 case 0x660f6e: /* movd */
6642 case 0x660f6f: /* movdqa */
6643 case 0xf30f6f: /* movdqu */
6644 case 0x660f70: /* pshufd */
6645 case 0xf20f70: /* pshuflw */
6646 case 0xf30f70: /* pshufhw */
6647 case 0x660f74: /* pcmpeqb */
6648 case 0x660f75: /* pcmpeqw */
6649 case 0x660f76: /* pcmpeqd */
6650 case 0x660f7c: /* haddpd */
6651 case 0xf20f7c: /* haddps */
6652 case 0x660f7d: /* hsubpd */
6653 case 0xf20f7d: /* hsubps */
6654 case 0xf30f7e: /* movq */
6655 case 0x0fc2: /* cmpps */
6656 case 0x660fc2: /* cmppd */
6657 case 0xf20fc2: /* cmpsd */
6658 case 0xf30fc2: /* cmpss */
6659 case 0x660fc4: /* pinsrw */
6660 case 0x0fc6: /* shufps */
6661 case 0x660fc6: /* shufpd */
6662 case 0x660fd0: /* addsubpd */
6663 case 0xf20fd0: /* addsubps */
6664 case 0x660fd1: /* psrlw */
6665 case 0x660fd2: /* psrld */
6666 case 0x660fd3: /* psrlq */
6667 case 0x660fd4: /* paddq */
6668 case 0x660fd5: /* pmullw */
6669 case 0xf30fd6: /* movq2dq */
6670 case 0x660fd8: /* psubusb */
6671 case 0x660fd9: /* psubusw */
6672 case 0x660fda: /* pminub */
6673 case 0x660fdb: /* pand */
6674 case 0x660fdc: /* paddusb */
6675 case 0x660fdd: /* paddusw */
6676 case 0x660fde: /* pmaxub */
6677 case 0x660fdf: /* pandn */
6678 case 0x660fe0: /* pavgb */
6679 case 0x660fe1: /* psraw */
6680 case 0x660fe2: /* psrad */
6681 case 0x660fe3: /* pavgw */
6682 case 0x660fe4: /* pmulhuw */
6683 case 0x660fe5: /* pmulhw */
6684 case 0x660fe6: /* cvttpd2dq */
6685 case 0xf20fe6: /* cvtpd2dq */
6686 case 0xf30fe6: /* cvtdq2pd */
6687 case 0x660fe8: /* psubsb */
6688 case 0x660fe9: /* psubsw */
6689 case 0x660fea: /* pminsw */
6690 case 0x660feb: /* por */
6691 case 0x660fec: /* paddsb */
6692 case 0x660fed: /* paddsw */
6693 case 0x660fee: /* pmaxsw */
6694 case 0x660fef: /* pxor */
6695 case 0xf20ff0: /* lddqu */
6696 case 0x660ff1: /* psllw */
6697 case 0x660ff2: /* pslld */
6698 case 0x660ff3: /* psllq */
6699 case 0x660ff4: /* pmuludq */
6700 case 0x660ff5: /* pmaddwd */
6701 case 0x660ff6: /* psadbw */
6702 case 0x660ff8: /* psubb */
6703 case 0x660ff9: /* psubw */
6704 case 0x660ffa: /* psubd */
6705 case 0x660ffb: /* psubq */
6706 case 0x660ffc: /* paddb */
6707 case 0x660ffd: /* paddw */
6708 case 0x660ffe: /* paddd */
6709 if (i386_record_modrm (&ir))
6712 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
6714 record_arch_list_add_reg (ir.regcache,
6715 I387_XMM0_REGNUM (tdep) + ir.reg);
6716 if ((opcode & 0xfffffffc) == 0x660f3a60)
6717 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6720 case 0x0f11: /* movups */
6721 case 0x660f11: /* movupd */
6722 case 0xf30f11: /* movss */
6723 case 0xf20f11: /* movsd */
6724 case 0x0f13: /* movlps */
6725 case 0x660f13: /* movlpd */
6726 case 0x0f17: /* movhps */
6727 case 0x660f17: /* movhpd */
6728 case 0x0f29: /* movaps */
6729 case 0x660f29: /* movapd */
6730 case 0x660f3a14: /* pextrb */
6731 case 0x660f3a15: /* pextrw */
6732 case 0x660f3a16: /* pextrd pextrq */
6733 case 0x660f3a17: /* extractps */
6734 case 0x660f7f: /* movdqa */
6735 case 0xf30f7f: /* movdqu */
6736 if (i386_record_modrm (&ir))
6740 if (opcode == 0x0f13 || opcode == 0x660f13
6741 || opcode == 0x0f17 || opcode == 0x660f17)
6744 if (!i386_xmm_regnum_p (gdbarch,
6745 I387_XMM0_REGNUM (tdep) + ir.rm))
6747 record_arch_list_add_reg (ir.regcache,
6748 I387_XMM0_REGNUM (tdep) + ir.rm);
6770 if (i386_record_lea_modrm (&ir))
6775 case 0x0f2b: /* movntps */
6776 case 0x660f2b: /* movntpd */
6777 case 0x0fe7: /* movntq */
6778 case 0x660fe7: /* movntdq */
6781 if (opcode == 0x0fe7)
6785 if (i386_record_lea_modrm (&ir))
6789 case 0xf30f2c: /* cvttss2si */
6790 case 0xf20f2c: /* cvttsd2si */
6791 case 0xf30f2d: /* cvtss2si */
6792 case 0xf20f2d: /* cvtsd2si */
6793 case 0xf20f38f0: /* crc32 */
6794 case 0xf20f38f1: /* crc32 */
6795 case 0x0f50: /* movmskps */
6796 case 0x660f50: /* movmskpd */
6797 case 0x0fc5: /* pextrw */
6798 case 0x660fc5: /* pextrw */
6799 case 0x0fd7: /* pmovmskb */
6800 case 0x660fd7: /* pmovmskb */
6801 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6804 case 0x0f3800: /* pshufb */
6805 case 0x0f3801: /* phaddw */
6806 case 0x0f3802: /* phaddd */
6807 case 0x0f3803: /* phaddsw */
6808 case 0x0f3804: /* pmaddubsw */
6809 case 0x0f3805: /* phsubw */
6810 case 0x0f3806: /* phsubd */
6811 case 0x0f3807: /* phsubsw */
6812 case 0x0f3808: /* psignb */
6813 case 0x0f3809: /* psignw */
6814 case 0x0f380a: /* psignd */
6815 case 0x0f380b: /* pmulhrsw */
6816 case 0x0f381c: /* pabsb */
6817 case 0x0f381d: /* pabsw */
6818 case 0x0f381e: /* pabsd */
6819 case 0x0f382b: /* packusdw */
6820 case 0x0f3830: /* pmovzxbw */
6821 case 0x0f3831: /* pmovzxbd */
6822 case 0x0f3832: /* pmovzxbq */
6823 case 0x0f3833: /* pmovzxwd */
6824 case 0x0f3834: /* pmovzxwq */
6825 case 0x0f3835: /* pmovzxdq */
6826 case 0x0f3837: /* pcmpgtq */
6827 case 0x0f3838: /* pminsb */
6828 case 0x0f3839: /* pminsd */
6829 case 0x0f383a: /* pminuw */
6830 case 0x0f383b: /* pminud */
6831 case 0x0f383c: /* pmaxsb */
6832 case 0x0f383d: /* pmaxsd */
6833 case 0x0f383e: /* pmaxuw */
6834 case 0x0f383f: /* pmaxud */
6835 case 0x0f3840: /* pmulld */
6836 case 0x0f3841: /* phminposuw */
6837 case 0x0f3a0f: /* palignr */
6838 case 0x0f60: /* punpcklbw */
6839 case 0x0f61: /* punpcklwd */
6840 case 0x0f62: /* punpckldq */
6841 case 0x0f63: /* packsswb */
6842 case 0x0f64: /* pcmpgtb */
6843 case 0x0f65: /* pcmpgtw */
6844 case 0x0f66: /* pcmpgtd */
6845 case 0x0f67: /* packuswb */
6846 case 0x0f68: /* punpckhbw */
6847 case 0x0f69: /* punpckhwd */
6848 case 0x0f6a: /* punpckhdq */
6849 case 0x0f6b: /* packssdw */
6850 case 0x0f6e: /* movd */
6851 case 0x0f6f: /* movq */
6852 case 0x0f70: /* pshufw */
6853 case 0x0f74: /* pcmpeqb */
6854 case 0x0f75: /* pcmpeqw */
6855 case 0x0f76: /* pcmpeqd */
6856 case 0x0fc4: /* pinsrw */
6857 case 0x0fd1: /* psrlw */
6858 case 0x0fd2: /* psrld */
6859 case 0x0fd3: /* psrlq */
6860 case 0x0fd4: /* paddq */
6861 case 0x0fd5: /* pmullw */
6862 case 0xf20fd6: /* movdq2q */
6863 case 0x0fd8: /* psubusb */
6864 case 0x0fd9: /* psubusw */
6865 case 0x0fda: /* pminub */
6866 case 0x0fdb: /* pand */
6867 case 0x0fdc: /* paddusb */
6868 case 0x0fdd: /* paddusw */
6869 case 0x0fde: /* pmaxub */
6870 case 0x0fdf: /* pandn */
6871 case 0x0fe0: /* pavgb */
6872 case 0x0fe1: /* psraw */
6873 case 0x0fe2: /* psrad */
6874 case 0x0fe3: /* pavgw */
6875 case 0x0fe4: /* pmulhuw */
6876 case 0x0fe5: /* pmulhw */
6877 case 0x0fe8: /* psubsb */
6878 case 0x0fe9: /* psubsw */
6879 case 0x0fea: /* pminsw */
6880 case 0x0feb: /* por */
6881 case 0x0fec: /* paddsb */
6882 case 0x0fed: /* paddsw */
6883 case 0x0fee: /* pmaxsw */
6884 case 0x0fef: /* pxor */
6885 case 0x0ff1: /* psllw */
6886 case 0x0ff2: /* pslld */
6887 case 0x0ff3: /* psllq */
6888 case 0x0ff4: /* pmuludq */
6889 case 0x0ff5: /* pmaddwd */
6890 case 0x0ff6: /* psadbw */
6891 case 0x0ff8: /* psubb */
6892 case 0x0ff9: /* psubw */
6893 case 0x0ffa: /* psubd */
6894 case 0x0ffb: /* psubq */
6895 case 0x0ffc: /* paddb */
6896 case 0x0ffd: /* paddw */
6897 case 0x0ffe: /* paddd */
6898 if (i386_record_modrm (&ir))
6900 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
6902 record_arch_list_add_reg (ir.regcache,
6903 I387_MM0_REGNUM (tdep) + ir.reg);
6906 case 0x0f71: /* psllw */
6907 case 0x0f72: /* pslld */
6908 case 0x0f73: /* psllq */
6909 if (i386_record_modrm (&ir))
6911 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
6913 record_arch_list_add_reg (ir.regcache,
6914 I387_MM0_REGNUM (tdep) + ir.rm);
6917 case 0x660f71: /* psllw */
6918 case 0x660f72: /* pslld */
6919 case 0x660f73: /* psllq */
6920 if (i386_record_modrm (&ir))
6923 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
6925 record_arch_list_add_reg (ir.regcache,
6926 I387_XMM0_REGNUM (tdep) + ir.rm);
6929 case 0x0f7e: /* movd */
6930 case 0x660f7e: /* movd */
6931 if (i386_record_modrm (&ir))
6934 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6941 if (i386_record_lea_modrm (&ir))
6946 case 0x0f7f: /* movq */
6947 if (i386_record_modrm (&ir))
6951 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
6953 record_arch_list_add_reg (ir.regcache,
6954 I387_MM0_REGNUM (tdep) + ir.rm);
6959 if (i386_record_lea_modrm (&ir))
6964 case 0xf30fb8: /* popcnt */
6965 if (i386_record_modrm (&ir))
6967 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
6968 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6971 case 0x660fd6: /* movq */
6972 if (i386_record_modrm (&ir))
6977 if (!i386_xmm_regnum_p (gdbarch,
6978 I387_XMM0_REGNUM (tdep) + ir.rm))
6980 record_arch_list_add_reg (ir.regcache,
6981 I387_XMM0_REGNUM (tdep) + ir.rm);
6986 if (i386_record_lea_modrm (&ir))
6991 case 0x660f3817: /* ptest */
6992 case 0x0f2e: /* ucomiss */
6993 case 0x660f2e: /* ucomisd */
6994 case 0x0f2f: /* comiss */
6995 case 0x660f2f: /* comisd */
6996 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6999 case 0x0ff7: /* maskmovq */
7000 regcache_raw_read_unsigned (ir.regcache,
7001 ir.regmap[X86_RECORD_REDI_REGNUM],
7003 if (record_arch_list_add_mem (addr, 64))
7007 case 0x660ff7: /* maskmovdqu */
7008 regcache_raw_read_unsigned (ir.regcache,
7009 ir.regmap[X86_RECORD_REDI_REGNUM],
7011 if (record_arch_list_add_mem (addr, 128))
7026 /* In the future, maybe still need to deal with need_dasm. */
7027 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
7028 if (record_arch_list_add_end ())
7034 printf_unfiltered (_("Process record does not support instruction 0x%02x "
7035 "at address %s.\n"),
7036 (unsigned int) (opcode),
7037 paddress (gdbarch, ir.orig_addr));
7041 static const int i386_record_regmap[] =
7043 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
7044 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
7045 0, 0, 0, 0, 0, 0, 0, 0,
7046 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
7047 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
7050 /* Check that the given address appears suitable for a fast
7051 tracepoint, which on x86 means that we need an instruction of at
7052 least 5 bytes, so that we can overwrite it with a 4-byte-offset
7053 jump and not have to worry about program jumps to an address in the
7054 middle of the tracepoint jump. Returns 1 if OK, and writes a size
7055 of instruction to replace, and 0 if not, plus an explanatory
7059 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch,
7060 CORE_ADDR addr, int *isize, char **msg)
7063 static struct ui_file *gdb_null = NULL;
7065 /* This is based on the target agent using a 4-byte relative jump.
7066 Alternate future possibilities include 8-byte offset for x86-84,
7067 or 3-byte jumps if the program has trampoline space close by. */
7070 /* Dummy file descriptor for the disassembler. */
7072 gdb_null = ui_file_new ();
7074 /* Check for fit. */
7075 len = gdb_print_insn (gdbarch, addr, gdb_null, NULL);
7078 /* Return a bit of target-specific detail to add to the caller's
7079 generic failure message. */
7081 *msg = xstrprintf (_("; instruction is only %d bytes long, "
7082 "need at least %d bytes for the jump"),
7095 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
7096 struct tdesc_arch_data *tdesc_data)
7098 const struct target_desc *tdesc = tdep->tdesc;
7099 const struct tdesc_feature *feature_core;
7100 const struct tdesc_feature *feature_sse, *feature_avx;
7101 int i, num_regs, valid_p;
7103 if (! tdesc_has_registers (tdesc))
7106 /* Get core registers. */
7107 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
7108 if (feature_core == NULL)
7111 /* Get SSE registers. */
7112 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
7114 /* Try AVX registers. */
7115 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
7119 /* The XCR0 bits. */
7122 /* AVX register description requires SSE register description. */
7126 tdep->xcr0 = I386_XSTATE_AVX_MASK;
7128 /* It may have been set by OSABI initialization function. */
7129 if (tdep->num_ymm_regs == 0)
7131 tdep->ymmh_register_names = i386_ymmh_names;
7132 tdep->num_ymm_regs = 8;
7133 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
7136 for (i = 0; i < tdep->num_ymm_regs; i++)
7137 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
7138 tdep->ymm0h_regnum + i,
7139 tdep->ymmh_register_names[i]);
7141 else if (feature_sse)
7142 tdep->xcr0 = I386_XSTATE_SSE_MASK;
7145 tdep->xcr0 = I386_XSTATE_X87_MASK;
7146 tdep->num_xmm_regs = 0;
7149 num_regs = tdep->num_core_regs;
7150 for (i = 0; i < num_regs; i++)
7151 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
7152 tdep->register_names[i]);
7156 /* Need to include %mxcsr, so add one. */
7157 num_regs += tdep->num_xmm_regs + 1;
7158 for (; i < num_regs; i++)
7159 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
7160 tdep->register_names[i]);
7167 static struct gdbarch *
7168 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
7170 struct gdbarch_tdep *tdep;
7171 struct gdbarch *gdbarch;
7172 struct tdesc_arch_data *tdesc_data;
7173 const struct target_desc *tdesc;
7177 /* If there is already a candidate, use it. */
7178 arches = gdbarch_list_lookup_by_info (arches, &info);
7180 return arches->gdbarch;
7182 /* Allocate space for the new architecture. */
7183 tdep = XCALLOC (1, struct gdbarch_tdep);
7184 gdbarch = gdbarch_alloc (&info, tdep);
7186 /* General-purpose registers. */
7187 tdep->gregset = NULL;
7188 tdep->gregset_reg_offset = NULL;
7189 tdep->gregset_num_regs = I386_NUM_GREGS;
7190 tdep->sizeof_gregset = 0;
7192 /* Floating-point registers. */
7193 tdep->fpregset = NULL;
7194 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
7196 tdep->xstateregset = NULL;
7198 /* The default settings include the FPU registers, the MMX registers
7199 and the SSE registers. This can be overridden for a specific ABI
7200 by adjusting the members `st0_regnum', `mm0_regnum' and
7201 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
7202 will show up in the output of "info all-registers". */
7204 tdep->st0_regnum = I386_ST0_REGNUM;
7206 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
7207 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
7209 tdep->jb_pc_offset = -1;
7210 tdep->struct_return = pcc_struct_return;
7211 tdep->sigtramp_start = 0;
7212 tdep->sigtramp_end = 0;
7213 tdep->sigtramp_p = i386_sigtramp_p;
7214 tdep->sigcontext_addr = NULL;
7215 tdep->sc_reg_offset = NULL;
7216 tdep->sc_pc_offset = -1;
7217 tdep->sc_sp_offset = -1;
7219 tdep->xsave_xcr0_offset = -1;
7221 tdep->record_regmap = i386_record_regmap;
7223 /* The format used for `long double' on almost all i386 targets is
7224 the i387 extended floating-point format. In fact, of all targets
7225 in the GCC 2.95 tree, only OSF/1 does it different, and insists
7226 on having a `long double' that's not `long' at all. */
7227 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
7229 /* Although the i387 extended floating-point has only 80 significant
7230 bits, a `long double' actually takes up 96, probably to enforce
7232 set_gdbarch_long_double_bit (gdbarch, 96);
7234 /* Register numbers of various important registers. */
7235 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
7236 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
7237 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
7238 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
7240 /* NOTE: kettenis/20040418: GCC does have two possible register
7241 numbering schemes on the i386: dbx and SVR4. These schemes
7242 differ in how they number %ebp, %esp, %eflags, and the
7243 floating-point registers, and are implemented by the arrays
7244 dbx_register_map[] and svr4_dbx_register_map in
7245 gcc/config/i386.c. GCC also defines a third numbering scheme in
7246 gcc/config/i386.c, which it designates as the "default" register
7247 map used in 64bit mode. This last register numbering scheme is
7248 implemented in dbx64_register_map, and is used for AMD64; see
7251 Currently, each GCC i386 target always uses the same register
7252 numbering scheme across all its supported debugging formats
7253 i.e. SDB (COFF), stabs and DWARF 2. This is because
7254 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7255 DBX_REGISTER_NUMBER macro which is defined by each target's
7256 respective config header in a manner independent of the requested
7257 output debugging format.
7259 This does not match the arrangement below, which presumes that
7260 the SDB and stabs numbering schemes differ from the DWARF and
7261 DWARF 2 ones. The reason for this arrangement is that it is
7262 likely to get the numbering scheme for the target's
7263 default/native debug format right. For targets where GCC is the
7264 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7265 targets where the native toolchain uses a different numbering
7266 scheme for a particular debug format (stabs-in-ELF on Solaris)
7267 the defaults below will have to be overridden, like
7268 i386_elf_init_abi() does. */
7270 /* Use the dbx register numbering scheme for stabs and COFF. */
7271 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
7272 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
7274 /* Use the SVR4 register numbering scheme for DWARF 2. */
7275 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
7277 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7278 be in use on any of the supported i386 targets. */
7280 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
7282 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
7284 /* Call dummy code. */
7285 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
7287 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
7288 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
7289 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
7291 set_gdbarch_return_value (gdbarch, i386_return_value);
7293 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
7295 /* Stack grows downward. */
7296 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
7298 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc);
7299 set_gdbarch_decr_pc_after_break (gdbarch, 1);
7300 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
7302 set_gdbarch_frame_args_skip (gdbarch, 8);
7304 set_gdbarch_print_insn (gdbarch, i386_print_insn);
7306 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
7308 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
7310 /* Add the i386 register groups. */
7311 i386_add_reggroups (gdbarch);
7312 tdep->register_reggroup_p = i386_register_reggroup_p;
7314 /* Helper for function argument information. */
7315 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
7317 /* Hook the function epilogue frame unwinder. This unwinder is
7318 appended to the list first, so that it supercedes the DWARF
7319 unwinder in function epilogues (where the DWARF unwinder
7320 currently fails). */
7321 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
7323 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7324 to the list before the prologue-based unwinders, so that DWARF
7325 CFI info will be used if it is available. */
7326 dwarf2_append_unwinders (gdbarch);
7328 frame_base_set_default (gdbarch, &i386_frame_base);
7330 /* Pseudo registers may be changed by amd64_init_abi. */
7331 set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read);
7332 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
7334 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
7335 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
7337 /* Override the normal target description method to make the AVX
7338 upper halves anonymous. */
7339 set_gdbarch_register_name (gdbarch, i386_register_name);
7341 /* Even though the default ABI only includes general-purpose registers,
7342 floating-point registers and the SSE registers, we have to leave a
7343 gap for the upper AVX registers. */
7344 set_gdbarch_num_regs (gdbarch, I386_AVX_NUM_REGS);
7346 /* Get the x86 target description from INFO. */
7347 tdesc = info.target_desc;
7348 if (! tdesc_has_registers (tdesc))
7350 tdep->tdesc = tdesc;
7352 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
7353 tdep->register_names = i386_register_names;
7355 /* No upper YMM registers. */
7356 tdep->ymmh_register_names = NULL;
7357 tdep->ymm0h_regnum = -1;
7359 tdep->num_byte_regs = 8;
7360 tdep->num_word_regs = 8;
7361 tdep->num_dword_regs = 0;
7362 tdep->num_mmx_regs = 8;
7363 tdep->num_ymm_regs = 0;
7365 tdesc_data = tdesc_data_alloc ();
7367 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
7369 /* Hook in ABI-specific overrides, if they have been registered. */
7370 info.tdep_info = (void *) tdesc_data;
7371 gdbarch_init_osabi (info, gdbarch);
7373 if (!i386_validate_tdesc_p (tdep, tdesc_data))
7375 tdesc_data_cleanup (tdesc_data);
7377 gdbarch_free (gdbarch);
7381 /* Wire in pseudo registers. Number of pseudo registers may be
7383 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
7384 + tdep->num_word_regs
7385 + tdep->num_dword_regs
7386 + tdep->num_mmx_regs
7387 + tdep->num_ymm_regs));
7389 /* Target description may be changed. */
7390 tdesc = tdep->tdesc;
7392 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
7394 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7395 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
7397 /* Make %al the first pseudo-register. */
7398 tdep->al_regnum = gdbarch_num_regs (gdbarch);
7399 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
7401 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
7402 if (tdep->num_dword_regs)
7404 /* Support dword pseudo-register if it hasn't been disabled. */
7405 tdep->eax_regnum = ymm0_regnum;
7406 ymm0_regnum += tdep->num_dword_regs;
7409 tdep->eax_regnum = -1;
7411 mm0_regnum = ymm0_regnum;
7412 if (tdep->num_ymm_regs)
7414 /* Support YMM pseudo-register if it is available. */
7415 tdep->ymm0_regnum = ymm0_regnum;
7416 mm0_regnum += tdep->num_ymm_regs;
7419 tdep->ymm0_regnum = -1;
7421 if (tdep->num_mmx_regs != 0)
7423 /* Support MMX pseudo-register if MMX hasn't been disabled. */
7424 tdep->mm0_regnum = mm0_regnum;
7427 tdep->mm0_regnum = -1;
7429 /* Hook in the legacy prologue-based unwinders last (fallback). */
7430 frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind);
7431 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
7432 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
7434 /* If we have a register mapping, enable the generic core file
7435 support, unless it has already been enabled. */
7436 if (tdep->gregset_reg_offset
7437 && !gdbarch_regset_from_core_section_p (gdbarch))
7438 set_gdbarch_regset_from_core_section (gdbarch,
7439 i386_regset_from_core_section);
7441 set_gdbarch_skip_permanent_breakpoint (gdbarch,
7442 i386_skip_permanent_breakpoint);
7444 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
7445 i386_fast_tracepoint_valid_at);
7450 static enum gdb_osabi
7451 i386_coff_osabi_sniffer (bfd *abfd)
7453 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
7454 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
7455 return GDB_OSABI_GO32;
7457 return GDB_OSABI_UNKNOWN;
7461 /* Provide a prototype to silence -Wmissing-prototypes. */
7462 void _initialize_i386_tdep (void);
7465 _initialize_i386_tdep (void)
7467 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
7469 /* Add the variable that controls the disassembly flavor. */
7470 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
7471 &disassembly_flavor, _("\
7472 Set the disassembly flavor."), _("\
7473 Show the disassembly flavor."), _("\
7474 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7476 NULL, /* FIXME: i18n: */
7477 &setlist, &showlist);
7479 /* Add the variable that controls the convention for returning
7481 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
7482 &struct_convention, _("\
7483 Set the convention for returning small structs."), _("\
7484 Show the convention for returning small structs."), _("\
7485 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7488 NULL, /* FIXME: i18n: */
7489 &setlist, &showlist);
7491 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
7492 i386_coff_osabi_sniffer);
7494 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
7495 i386_svr4_init_abi);
7496 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
7497 i386_go32_init_abi);
7499 /* Initialize the i386-specific register groups. */
7500 i386_init_reggroups ();
7502 /* Initialize the standard target descriptions. */
7503 initialize_tdesc_i386 ();
7504 initialize_tdesc_i386_mmx ();
7505 initialize_tdesc_i386_avx ();
7507 /* Tell remote stub that we support XML target description. */
7508 register_remote_support_xml ("i386");