1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010, 2011 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
48 #include "exceptions.h"
49 #include "gdb_assert.h"
50 #include "gdb_string.h"
52 #include "i386-tdep.h"
53 #include "i387-tdep.h"
54 #include "i386-xstate.h"
59 #include "features/i386/i386.c"
60 #include "features/i386/i386-avx.c"
61 #include "features/i386/i386-mmx.c"
65 static const char *i386_register_names[] =
67 "eax", "ecx", "edx", "ebx",
68 "esp", "ebp", "esi", "edi",
69 "eip", "eflags", "cs", "ss",
70 "ds", "es", "fs", "gs",
71 "st0", "st1", "st2", "st3",
72 "st4", "st5", "st6", "st7",
73 "fctrl", "fstat", "ftag", "fiseg",
74 "fioff", "foseg", "fooff", "fop",
75 "xmm0", "xmm1", "xmm2", "xmm3",
76 "xmm4", "xmm5", "xmm6", "xmm7",
80 static const char *i386_ymm_names[] =
82 "ymm0", "ymm1", "ymm2", "ymm3",
83 "ymm4", "ymm5", "ymm6", "ymm7",
86 static const char *i386_ymmh_names[] =
88 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
89 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
92 /* Register names for MMX pseudo-registers. */
94 static const char *i386_mmx_names[] =
96 "mm0", "mm1", "mm2", "mm3",
97 "mm4", "mm5", "mm6", "mm7"
100 /* Register names for byte pseudo-registers. */
102 static const char *i386_byte_names[] =
104 "al", "cl", "dl", "bl",
105 "ah", "ch", "dh", "bh"
108 /* Register names for word pseudo-registers. */
110 static const char *i386_word_names[] =
112 "ax", "cx", "dx", "bx",
119 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
121 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
122 int mm0_regnum = tdep->mm0_regnum;
127 regnum -= mm0_regnum;
128 return regnum >= 0 && regnum < tdep->num_mmx_regs;
134 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
136 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
138 regnum -= tdep->al_regnum;
139 return regnum >= 0 && regnum < tdep->num_byte_regs;
145 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
147 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
149 regnum -= tdep->ax_regnum;
150 return regnum >= 0 && regnum < tdep->num_word_regs;
153 /* Dword register? */
156 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
158 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
159 int eax_regnum = tdep->eax_regnum;
164 regnum -= eax_regnum;
165 return regnum >= 0 && regnum < tdep->num_dword_regs;
169 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
171 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
172 int ymm0h_regnum = tdep->ymm0h_regnum;
174 if (ymm0h_regnum < 0)
177 regnum -= ymm0h_regnum;
178 return regnum >= 0 && regnum < tdep->num_ymm_regs;
184 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
186 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
187 int ymm0_regnum = tdep->ymm0_regnum;
192 regnum -= ymm0_regnum;
193 return regnum >= 0 && regnum < tdep->num_ymm_regs;
199 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
201 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
202 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
204 if (num_xmm_regs == 0)
207 regnum -= I387_XMM0_REGNUM (tdep);
208 return regnum >= 0 && regnum < num_xmm_regs;
212 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
214 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
216 if (I387_NUM_XMM_REGS (tdep) == 0)
219 return (regnum == I387_MXCSR_REGNUM (tdep));
225 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
227 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
229 if (I387_ST0_REGNUM (tdep) < 0)
232 return (I387_ST0_REGNUM (tdep) <= regnum
233 && regnum < I387_FCTRL_REGNUM (tdep));
237 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
239 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
241 if (I387_ST0_REGNUM (tdep) < 0)
244 return (I387_FCTRL_REGNUM (tdep) <= regnum
245 && regnum < I387_XMM0_REGNUM (tdep));
248 /* Return the name of register REGNUM, or the empty string if it is
249 an anonymous register. */
252 i386_register_name (struct gdbarch *gdbarch, int regnum)
254 /* Hide the upper YMM registers. */
255 if (i386_ymmh_regnum_p (gdbarch, regnum))
258 return tdesc_register_name (gdbarch, regnum);
261 /* Return the name of register REGNUM. */
264 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
266 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
267 if (i386_mmx_regnum_p (gdbarch, regnum))
268 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
269 else if (i386_ymm_regnum_p (gdbarch, regnum))
270 return i386_ymm_names[regnum - tdep->ymm0_regnum];
271 else if (i386_byte_regnum_p (gdbarch, regnum))
272 return i386_byte_names[regnum - tdep->al_regnum];
273 else if (i386_word_regnum_p (gdbarch, regnum))
274 return i386_word_names[regnum - tdep->ax_regnum];
276 internal_error (__FILE__, __LINE__, _("invalid regnum"));
279 /* Convert a dbx register number REG to the appropriate register
280 number used by GDB. */
283 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
285 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
287 /* This implements what GCC calls the "default" register map
288 (dbx_register_map[]). */
290 if (reg >= 0 && reg <= 7)
292 /* General-purpose registers. The debug info calls %ebp
293 register 4, and %esp register 5. */
300 else if (reg >= 12 && reg <= 19)
302 /* Floating-point registers. */
303 return reg - 12 + I387_ST0_REGNUM (tdep);
305 else if (reg >= 21 && reg <= 28)
308 int ymm0_regnum = tdep->ymm0_regnum;
311 && i386_xmm_regnum_p (gdbarch, reg))
312 return reg - 21 + ymm0_regnum;
314 return reg - 21 + I387_XMM0_REGNUM (tdep);
316 else if (reg >= 29 && reg <= 36)
319 return reg - 29 + I387_MM0_REGNUM (tdep);
322 /* This will hopefully provoke a warning. */
323 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
326 /* Convert SVR4 register number REG to the appropriate register number
330 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
332 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
334 /* This implements the GCC register map that tries to be compatible
335 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
337 /* The SVR4 register numbering includes %eip and %eflags, and
338 numbers the floating point registers differently. */
339 if (reg >= 0 && reg <= 9)
341 /* General-purpose registers. */
344 else if (reg >= 11 && reg <= 18)
346 /* Floating-point registers. */
347 return reg - 11 + I387_ST0_REGNUM (tdep);
349 else if (reg >= 21 && reg <= 36)
351 /* The SSE and MMX registers have the same numbers as with dbx. */
352 return i386_dbx_reg_to_regnum (gdbarch, reg);
357 case 37: return I387_FCTRL_REGNUM (tdep);
358 case 38: return I387_FSTAT_REGNUM (tdep);
359 case 39: return I387_MXCSR_REGNUM (tdep);
360 case 40: return I386_ES_REGNUM;
361 case 41: return I386_CS_REGNUM;
362 case 42: return I386_SS_REGNUM;
363 case 43: return I386_DS_REGNUM;
364 case 44: return I386_FS_REGNUM;
365 case 45: return I386_GS_REGNUM;
368 /* This will hopefully provoke a warning. */
369 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
374 /* This is the variable that is set with "set disassembly-flavor", and
375 its legitimate values. */
376 static const char att_flavor[] = "att";
377 static const char intel_flavor[] = "intel";
378 static const char *valid_flavors[] =
384 static const char *disassembly_flavor = att_flavor;
387 /* Use the program counter to determine the contents and size of a
388 breakpoint instruction. Return a pointer to a string of bytes that
389 encode a breakpoint instruction, store the length of the string in
390 *LEN and optionally adjust *PC to point to the correct memory
391 location for inserting the breakpoint.
393 On the i386 we have a single breakpoint that fits in a single byte
394 and can be inserted anywhere.
396 This function is 64-bit safe. */
398 static const gdb_byte *
399 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
401 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */
403 *len = sizeof (break_insn);
407 /* Displaced instruction handling. */
409 /* Skip the legacy instruction prefixes in INSN.
410 Not all prefixes are valid for any particular insn
411 but we needn't care, the insn will fault if it's invalid.
412 The result is a pointer to the first opcode byte,
413 or NULL if we run off the end of the buffer. */
416 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
418 gdb_byte *end = insn + max_len;
424 case DATA_PREFIX_OPCODE:
425 case ADDR_PREFIX_OPCODE:
426 case CS_PREFIX_OPCODE:
427 case DS_PREFIX_OPCODE:
428 case ES_PREFIX_OPCODE:
429 case FS_PREFIX_OPCODE:
430 case GS_PREFIX_OPCODE:
431 case SS_PREFIX_OPCODE:
432 case LOCK_PREFIX_OPCODE:
433 case REPE_PREFIX_OPCODE:
434 case REPNE_PREFIX_OPCODE:
446 i386_absolute_jmp_p (const gdb_byte *insn)
448 /* jmp far (absolute address in operand). */
454 /* jump near, absolute indirect (/4). */
455 if ((insn[1] & 0x38) == 0x20)
458 /* jump far, absolute indirect (/5). */
459 if ((insn[1] & 0x38) == 0x28)
467 i386_absolute_call_p (const gdb_byte *insn)
469 /* call far, absolute. */
475 /* Call near, absolute indirect (/2). */
476 if ((insn[1] & 0x38) == 0x10)
479 /* Call far, absolute indirect (/3). */
480 if ((insn[1] & 0x38) == 0x18)
488 i386_ret_p (const gdb_byte *insn)
492 case 0xc2: /* ret near, pop N bytes. */
493 case 0xc3: /* ret near */
494 case 0xca: /* ret far, pop N bytes. */
495 case 0xcb: /* ret far */
496 case 0xcf: /* iret */
505 i386_call_p (const gdb_byte *insn)
507 if (i386_absolute_call_p (insn))
510 /* call near, relative. */
517 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
518 length in bytes. Otherwise, return zero. */
521 i386_syscall_p (const gdb_byte *insn, int *lengthp)
532 /* Some kernels may run one past a syscall insn, so we have to cope.
533 Otherwise this is just simple_displaced_step_copy_insn. */
535 struct displaced_step_closure *
536 i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
537 CORE_ADDR from, CORE_ADDR to,
538 struct regcache *regs)
540 size_t len = gdbarch_max_insn_length (gdbarch);
541 gdb_byte *buf = xmalloc (len);
543 read_memory (from, buf, len);
545 /* GDB may get control back after the insn after the syscall.
546 Presumably this is a kernel bug.
547 If this is a syscall, make sure there's a nop afterwards. */
552 insn = i386_skip_prefixes (buf, len);
553 if (insn != NULL && i386_syscall_p (insn, &syscall_length))
554 insn[syscall_length] = NOP_OPCODE;
557 write_memory (to, buf, len);
561 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
562 paddress (gdbarch, from), paddress (gdbarch, to));
563 displaced_step_dump_bytes (gdb_stdlog, buf, len);
566 return (struct displaced_step_closure *) buf;
569 /* Fix up the state of registers and memory after having single-stepped
570 a displaced instruction. */
573 i386_displaced_step_fixup (struct gdbarch *gdbarch,
574 struct displaced_step_closure *closure,
575 CORE_ADDR from, CORE_ADDR to,
576 struct regcache *regs)
578 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
580 /* The offset we applied to the instruction's address.
581 This could well be negative (when viewed as a signed 32-bit
582 value), but ULONGEST won't reflect that, so take care when
584 ULONGEST insn_offset = to - from;
586 /* Since we use simple_displaced_step_copy_insn, our closure is a
587 copy of the instruction. */
588 gdb_byte *insn = (gdb_byte *) closure;
589 /* The start of the insn, needed in case we see some prefixes. */
590 gdb_byte *insn_start = insn;
593 fprintf_unfiltered (gdb_stdlog,
594 "displaced: fixup (%s, %s), "
595 "insn = 0x%02x 0x%02x ...\n",
596 paddress (gdbarch, from), paddress (gdbarch, to),
599 /* The list of issues to contend with here is taken from
600 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
601 Yay for Free Software! */
603 /* Relocate the %eip, if necessary. */
605 /* The instruction recognizers we use assume any leading prefixes
606 have been skipped. */
608 /* This is the size of the buffer in closure. */
609 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
610 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
611 /* If there are too many prefixes, just ignore the insn.
612 It will fault when run. */
617 /* Except in the case of absolute or indirect jump or call
618 instructions, or a return instruction, the new eip is relative to
619 the displaced instruction; make it relative. Well, signal
620 handler returns don't need relocation either, but we use the
621 value of %eip to recognize those; see below. */
622 if (! i386_absolute_jmp_p (insn)
623 && ! i386_absolute_call_p (insn)
624 && ! i386_ret_p (insn))
629 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
631 /* A signal trampoline system call changes the %eip, resuming
632 execution of the main program after the signal handler has
633 returned. That makes them like 'return' instructions; we
634 shouldn't relocate %eip.
636 But most system calls don't, and we do need to relocate %eip.
638 Our heuristic for distinguishing these cases: if stepping
639 over the system call instruction left control directly after
640 the instruction, the we relocate --- control almost certainly
641 doesn't belong in the displaced copy. Otherwise, we assume
642 the instruction has put control where it belongs, and leave
643 it unrelocated. Goodness help us if there are PC-relative
645 if (i386_syscall_p (insn, &insn_len)
646 && orig_eip != to + (insn - insn_start) + insn_len
647 /* GDB can get control back after the insn after the syscall.
648 Presumably this is a kernel bug.
649 i386_displaced_step_copy_insn ensures its a nop,
650 we add one to the length for it. */
651 && orig_eip != to + (insn - insn_start) + insn_len + 1)
654 fprintf_unfiltered (gdb_stdlog,
655 "displaced: syscall changed %%eip; "
660 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
662 /* If we just stepped over a breakpoint insn, we don't backup
663 the pc on purpose; this is to match behaviour without
666 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
669 fprintf_unfiltered (gdb_stdlog,
671 "relocated %%eip from %s to %s\n",
672 paddress (gdbarch, orig_eip),
673 paddress (gdbarch, eip));
677 /* If the instruction was PUSHFL, then the TF bit will be set in the
678 pushed value, and should be cleared. We'll leave this for later,
679 since GDB already messes up the TF flag when stepping over a
682 /* If the instruction was a call, the return address now atop the
683 stack is the address following the copied instruction. We need
684 to make it the address following the original instruction. */
685 if (i386_call_p (insn))
689 const ULONGEST retaddr_len = 4;
691 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
692 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
693 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
694 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
697 fprintf_unfiltered (gdb_stdlog,
698 "displaced: relocated return addr at %s to %s\n",
699 paddress (gdbarch, esp),
700 paddress (gdbarch, retaddr));
705 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
707 target_write_memory (*to, buf, len);
712 i386_relocate_instruction (struct gdbarch *gdbarch,
713 CORE_ADDR *to, CORE_ADDR oldloc)
715 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
716 gdb_byte buf[I386_MAX_INSN_LEN];
717 int offset = 0, rel32, newrel;
719 gdb_byte *insn = buf;
721 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
723 insn_length = gdb_buffered_insn_length (gdbarch, insn,
724 I386_MAX_INSN_LEN, oldloc);
726 /* Get past the prefixes. */
727 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
729 /* Adjust calls with 32-bit relative addresses as push/jump, with
730 the address pushed being the location where the original call in
731 the user program would return to. */
734 gdb_byte push_buf[16];
735 unsigned int ret_addr;
737 /* Where "ret" in the original code will return to. */
738 ret_addr = oldloc + insn_length;
739 push_buf[0] = 0x68; /* pushq $... */
740 memcpy (&push_buf[1], &ret_addr, 4);
742 append_insns (to, 5, push_buf);
744 /* Convert the relative call to a relative jump. */
747 /* Adjust the destination offset. */
748 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
749 newrel = (oldloc - *to) + rel32;
750 store_signed_integer (insn + 1, 4, byte_order, newrel);
753 fprintf_unfiltered (gdb_stdlog,
754 "Adjusted insn rel32=%s at %s to"
756 hex_string (rel32), paddress (gdbarch, oldloc),
757 hex_string (newrel), paddress (gdbarch, *to));
759 /* Write the adjusted jump into its displaced location. */
760 append_insns (to, 5, insn);
764 /* Adjust jumps with 32-bit relative addresses. Calls are already
768 /* Adjust conditional jumps. */
769 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
774 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
775 newrel = (oldloc - *to) + rel32;
776 store_signed_integer (insn + offset, 4, byte_order, newrel);
778 fprintf_unfiltered (gdb_stdlog,
779 "Adjusted insn rel32=%s at %s to"
781 hex_string (rel32), paddress (gdbarch, oldloc),
782 hex_string (newrel), paddress (gdbarch, *to));
785 /* Write the adjusted instructions into their displaced
787 append_insns (to, insn_length, buf);
791 #ifdef I386_REGNO_TO_SYMMETRY
792 #error "The Sequent Symmetry is no longer supported."
795 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
796 and %esp "belong" to the calling function. Therefore these
797 registers should be saved if they're going to be modified. */
799 /* The maximum number of saved registers. This should include all
800 registers mentioned above, and %eip. */
801 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
803 struct i386_frame_cache
811 /* Saved registers. */
812 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
817 /* Stack space reserved for local variables. */
821 /* Allocate and initialize a frame cache. */
823 static struct i386_frame_cache *
824 i386_alloc_frame_cache (void)
826 struct i386_frame_cache *cache;
829 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
834 cache->sp_offset = -4;
837 /* Saved registers. We initialize these to -1 since zero is a valid
838 offset (that's where %ebp is supposed to be stored). */
839 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
840 cache->saved_regs[i] = -1;
842 cache->saved_sp_reg = -1;
843 cache->pc_in_eax = 0;
845 /* Frameless until proven otherwise. */
851 /* If the instruction at PC is a jump, return the address of its
852 target. Otherwise, return PC. */
855 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
857 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
862 if (target_read_memory (pc, &op, 1))
868 op = read_memory_unsigned_integer (pc + 1, 1, byte_order);
874 /* Relative jump: if data16 == 0, disp32, else disp16. */
877 delta = read_memory_integer (pc + 2, 2, byte_order);
879 /* Include the size of the jmp instruction (including the
885 delta = read_memory_integer (pc + 1, 4, byte_order);
887 /* Include the size of the jmp instruction. */
892 /* Relative jump, disp8 (ignore data16). */
893 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
902 /* Check whether PC points at a prologue for a function returning a
903 structure or union. If so, it updates CACHE and returns the
904 address of the first instruction after the code sequence that
905 removes the "hidden" argument from the stack or CURRENT_PC,
906 whichever is smaller. Otherwise, return PC. */
909 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
910 struct i386_frame_cache *cache)
912 /* Functions that return a structure or union start with:
915 xchgl %eax, (%esp) 0x87 0x04 0x24
916 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
918 (the System V compiler puts out the second `xchg' instruction,
919 and the assembler doesn't try to optimize it, so the 'sib' form
920 gets generated). This sequence is used to get the address of the
921 return buffer for a function that returns a structure. */
922 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
923 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
927 if (current_pc <= pc)
930 if (target_read_memory (pc, &op, 1))
933 if (op != 0x58) /* popl %eax */
936 if (target_read_memory (pc + 1, buf, 4))
939 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
942 if (current_pc == pc)
944 cache->sp_offset += 4;
948 if (current_pc == pc + 1)
950 cache->pc_in_eax = 1;
954 if (buf[1] == proto1[1])
961 i386_skip_probe (CORE_ADDR pc)
963 /* A function may start with
977 if (target_read_memory (pc, &op, 1))
980 if (op == 0x68 || op == 0x6a)
984 /* Skip past the `pushl' instruction; it has either a one-byte or a
985 four-byte operand, depending on the opcode. */
991 /* Read the following 8 bytes, which should be `call _probe' (6
992 bytes) followed by `addl $4,%esp' (2 bytes). */
993 read_memory (pc + delta, buf, sizeof (buf));
994 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
995 pc += delta + sizeof (buf);
1001 /* GCC 4.1 and later, can put code in the prologue to realign the
1002 stack pointer. Check whether PC points to such code, and update
1003 CACHE accordingly. Return the first instruction after the code
1004 sequence or CURRENT_PC, whichever is smaller. If we don't
1005 recognize the code, return PC. */
1008 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1009 struct i386_frame_cache *cache)
1011 /* There are 2 code sequences to re-align stack before the frame
1014 1. Use a caller-saved saved register:
1020 2. Use a callee-saved saved register:
1027 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1029 0x83 0xe4 0xf0 andl $-16, %esp
1030 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1035 int offset, offset_and;
1036 static int regnums[8] = {
1037 I386_EAX_REGNUM, /* %eax */
1038 I386_ECX_REGNUM, /* %ecx */
1039 I386_EDX_REGNUM, /* %edx */
1040 I386_EBX_REGNUM, /* %ebx */
1041 I386_ESP_REGNUM, /* %esp */
1042 I386_EBP_REGNUM, /* %ebp */
1043 I386_ESI_REGNUM, /* %esi */
1044 I386_EDI_REGNUM /* %edi */
1047 if (target_read_memory (pc, buf, sizeof buf))
1050 /* Check caller-saved saved register. The first instruction has
1051 to be "leal 4(%esp), %reg". */
1052 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1054 /* MOD must be binary 10 and R/M must be binary 100. */
1055 if ((buf[1] & 0xc7) != 0x44)
1058 /* REG has register number. */
1059 reg = (buf[1] >> 3) & 7;
1064 /* Check callee-saved saved register. The first instruction
1065 has to be "pushl %reg". */
1066 if ((buf[0] & 0xf8) != 0x50)
1072 /* The next instruction has to be "leal 8(%esp), %reg". */
1073 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1076 /* MOD must be binary 10 and R/M must be binary 100. */
1077 if ((buf[2] & 0xc7) != 0x44)
1080 /* REG has register number. Registers in pushl and leal have to
1082 if (reg != ((buf[2] >> 3) & 7))
1088 /* Rigister can't be %esp nor %ebp. */
1089 if (reg == 4 || reg == 5)
1092 /* The next instruction has to be "andl $-XXX, %esp". */
1093 if (buf[offset + 1] != 0xe4
1094 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1097 offset_and = offset;
1098 offset += buf[offset] == 0x81 ? 6 : 3;
1100 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1101 0xfc. REG must be binary 110 and MOD must be binary 01. */
1102 if (buf[offset] != 0xff
1103 || buf[offset + 2] != 0xfc
1104 || (buf[offset + 1] & 0xf8) != 0x70)
1107 /* R/M has register. Registers in leal and pushl have to be the
1109 if (reg != (buf[offset + 1] & 7))
1112 if (current_pc > pc + offset_and)
1113 cache->saved_sp_reg = regnums[reg];
1115 return min (pc + offset + 3, current_pc);
1118 /* Maximum instruction length we need to handle. */
1119 #define I386_MAX_MATCHED_INSN_LEN 6
1121 /* Instruction description. */
1125 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
1126 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
1129 /* Return whether instruction at PC matches PATTERN. */
1132 i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern)
1136 if (target_read_memory (pc, &op, 1))
1139 if ((op & pattern.mask[0]) == pattern.insn[0])
1141 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1142 int insn_matched = 1;
1145 gdb_assert (pattern.len > 1);
1146 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN);
1148 if (target_read_memory (pc + 1, buf, pattern.len - 1))
1151 for (i = 1; i < pattern.len; i++)
1153 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i])
1156 return insn_matched;
1161 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1162 the first instruction description that matches. Otherwise, return
1165 static struct i386_insn *
1166 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns)
1168 struct i386_insn *pattern;
1170 for (pattern = insn_patterns; pattern->len > 0; pattern++)
1172 if (i386_match_pattern (pc, *pattern))
1179 /* Return whether PC points inside a sequence of instructions that
1180 matches INSN_PATTERNS. */
1183 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns)
1185 CORE_ADDR current_pc;
1188 struct i386_insn *insn;
1190 insn = i386_match_insn (pc, insn_patterns);
1195 ix = insn - insn_patterns;
1196 for (i = ix - 1; i >= 0; i--)
1198 current_pc -= insn_patterns[i].len;
1200 if (!i386_match_pattern (current_pc, insn_patterns[i]))
1204 current_pc = pc + insn->len;
1205 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++)
1207 if (!i386_match_pattern (current_pc, *insn))
1210 current_pc += insn->len;
1216 /* Some special instructions that might be migrated by GCC into the
1217 part of the prologue that sets up the new stack frame. Because the
1218 stack frame hasn't been setup yet, no registers have been saved
1219 yet, and only the scratch registers %eax, %ecx and %edx can be
1222 struct i386_insn i386_frame_setup_skip_insns[] =
1224 /* Check for `movb imm8, r' and `movl imm32, r'.
1226 ??? Should we handle 16-bit operand-sizes here? */
1228 /* `movb imm8, %al' and `movb imm8, %ah' */
1229 /* `movb imm8, %cl' and `movb imm8, %ch' */
1230 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1231 /* `movb imm8, %dl' and `movb imm8, %dh' */
1232 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1233 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1234 { 5, { 0xb8 }, { 0xfe } },
1235 /* `movl imm32, %edx' */
1236 { 5, { 0xba }, { 0xff } },
1238 /* Check for `mov imm32, r32'. Note that there is an alternative
1239 encoding for `mov m32, %eax'.
1241 ??? Should we handle SIB adressing here?
1242 ??? Should we handle 16-bit operand-sizes here? */
1244 /* `movl m32, %eax' */
1245 { 5, { 0xa1 }, { 0xff } },
1246 /* `movl m32, %eax' and `mov; m32, %ecx' */
1247 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1248 /* `movl m32, %edx' */
1249 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1251 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1252 Because of the symmetry, there are actually two ways to encode
1253 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1254 opcode bytes 0x31 and 0x33 for `xorl'. */
1256 /* `subl %eax, %eax' */
1257 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1258 /* `subl %ecx, %ecx' */
1259 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1260 /* `subl %edx, %edx' */
1261 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1262 /* `xorl %eax, %eax' */
1263 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1264 /* `xorl %ecx, %ecx' */
1265 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1266 /* `xorl %edx, %edx' */
1267 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1272 /* Check whether PC points to a no-op instruction. */
1274 i386_skip_noop (CORE_ADDR pc)
1279 if (target_read_memory (pc, &op, 1))
1285 /* Ignore `nop' instruction. */
1289 if (target_read_memory (pc, &op, 1))
1293 /* Ignore no-op instruction `mov %edi, %edi'.
1294 Microsoft system dlls often start with
1295 a `mov %edi,%edi' instruction.
1296 The 5 bytes before the function start are
1297 filled with `nop' instructions.
1298 This pattern can be used for hot-patching:
1299 The `mov %edi, %edi' instruction can be replaced by a
1300 near jump to the location of the 5 `nop' instructions
1301 which can be replaced by a 32-bit jump to anywhere
1302 in the 32-bit address space. */
1304 else if (op == 0x8b)
1306 if (target_read_memory (pc + 1, &op, 1))
1312 if (target_read_memory (pc, &op, 1))
1322 /* Check whether PC points at a code that sets up a new stack frame.
1323 If so, it updates CACHE and returns the address of the first
1324 instruction after the sequence that sets up the frame or LIMIT,
1325 whichever is smaller. If we don't recognize the code, return PC. */
1328 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1329 CORE_ADDR pc, CORE_ADDR limit,
1330 struct i386_frame_cache *cache)
1332 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1333 struct i386_insn *insn;
1340 if (target_read_memory (pc, &op, 1))
1343 if (op == 0x55) /* pushl %ebp */
1345 /* Take into account that we've executed the `pushl %ebp' that
1346 starts this instruction sequence. */
1347 cache->saved_regs[I386_EBP_REGNUM] = 0;
1348 cache->sp_offset += 4;
1351 /* If that's all, return now. */
1355 /* Check for some special instructions that might be migrated by
1356 GCC into the prologue and skip them. At this point in the
1357 prologue, code should only touch the scratch registers %eax,
1358 %ecx and %edx, so while the number of posibilities is sheer,
1361 Make sure we only skip these instructions if we later see the
1362 `movl %esp, %ebp' that actually sets up the frame. */
1363 while (pc + skip < limit)
1365 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1372 /* If that's all, return now. */
1373 if (limit <= pc + skip)
1376 if (target_read_memory (pc + skip, &op, 1))
1379 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1383 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1388 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1396 /* OK, we actually have a frame. We just don't know how large
1397 it is yet. Set its size to zero. We'll adjust it if
1398 necessary. We also now commit to skipping the special
1399 instructions mentioned before. */
1403 /* If that's all, return now. */
1407 /* Check for stack adjustment
1411 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1412 reg, so we don't have to worry about a data16 prefix. */
1413 if (target_read_memory (pc, &op, 1))
1417 /* `subl' with 8-bit immediate. */
1418 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1419 /* Some instruction starting with 0x83 other than `subl'. */
1422 /* `subl' with signed 8-bit immediate (though it wouldn't
1423 make sense to be negative). */
1424 cache->locals = read_memory_integer (pc + 2, 1, byte_order);
1427 else if (op == 0x81)
1429 /* Maybe it is `subl' with a 32-bit immediate. */
1430 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1431 /* Some instruction starting with 0x81 other than `subl'. */
1434 /* It is `subl' with a 32-bit immediate. */
1435 cache->locals = read_memory_integer (pc + 2, 4, byte_order);
1440 /* Some instruction other than `subl'. */
1444 else if (op == 0xc8) /* enter */
1446 cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order);
1453 /* Check whether PC points at code that saves registers on the stack.
1454 If so, it updates CACHE and returns the address of the first
1455 instruction after the register saves or CURRENT_PC, whichever is
1456 smaller. Otherwise, return PC. */
1459 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1460 struct i386_frame_cache *cache)
1462 CORE_ADDR offset = 0;
1466 if (cache->locals > 0)
1467 offset -= cache->locals;
1468 for (i = 0; i < 8 && pc < current_pc; i++)
1470 if (target_read_memory (pc, &op, 1))
1472 if (op < 0x50 || op > 0x57)
1476 cache->saved_regs[op - 0x50] = offset;
1477 cache->sp_offset += 4;
1484 /* Do a full analysis of the prologue at PC and update CACHE
1485 accordingly. Bail out early if CURRENT_PC is reached. Return the
1486 address where the analysis stopped.
1488 We handle these cases:
1490 The startup sequence can be at the start of the function, or the
1491 function can start with a branch to startup code at the end.
1493 %ebp can be set up with either the 'enter' instruction, or "pushl
1494 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1495 once used in the System V compiler).
1497 Local space is allocated just below the saved %ebp by either the
1498 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1499 16-bit unsigned argument for space to allocate, and the 'addl'
1500 instruction could have either a signed byte, or 32-bit immediate.
1502 Next, the registers used by this function are pushed. With the
1503 System V compiler they will always be in the order: %edi, %esi,
1504 %ebx (and sometimes a harmless bug causes it to also save but not
1505 restore %eax); however, the code below is willing to see the pushes
1506 in any order, and will handle up to 8 of them.
1508 If the setup sequence is at the end of the function, then the next
1509 instruction will be a branch back to the start. */
1512 i386_analyze_prologue (struct gdbarch *gdbarch,
1513 CORE_ADDR pc, CORE_ADDR current_pc,
1514 struct i386_frame_cache *cache)
1516 pc = i386_skip_noop (pc);
1517 pc = i386_follow_jump (gdbarch, pc);
1518 pc = i386_analyze_struct_return (pc, current_pc, cache);
1519 pc = i386_skip_probe (pc);
1520 pc = i386_analyze_stack_align (pc, current_pc, cache);
1521 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1522 return i386_analyze_register_saves (pc, current_pc, cache);
1525 /* Return PC of first real instruction. */
1528 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1530 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1532 static gdb_byte pic_pat[6] =
1534 0xe8, 0, 0, 0, 0, /* call 0x0 */
1535 0x5b, /* popl %ebx */
1537 struct i386_frame_cache cache;
1543 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1544 if (cache.locals < 0)
1547 /* Found valid frame setup. */
1549 /* The native cc on SVR4 in -K PIC mode inserts the following code
1550 to get the address of the global offset table (GOT) into register
1555 movl %ebx,x(%ebp) (optional)
1558 This code is with the rest of the prologue (at the end of the
1559 function), so we have to skip it to get to the first real
1560 instruction at the start of the function. */
1562 for (i = 0; i < 6; i++)
1564 if (target_read_memory (pc + i, &op, 1))
1567 if (pic_pat[i] != op)
1574 if (target_read_memory (pc + delta, &op, 1))
1577 if (op == 0x89) /* movl %ebx, x(%ebp) */
1579 op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order);
1581 if (op == 0x5d) /* One byte offset from %ebp. */
1583 else if (op == 0x9d) /* Four byte offset from %ebp. */
1585 else /* Unexpected instruction. */
1588 if (target_read_memory (pc + delta, &op, 1))
1593 if (delta > 0 && op == 0x81
1594 && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order)
1601 /* If the function starts with a branch (to startup code at the end)
1602 the last instruction should bring us back to the first
1603 instruction of the real code. */
1604 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1605 pc = i386_follow_jump (gdbarch, pc);
1610 /* Check that the code pointed to by PC corresponds to a call to
1611 __main, skip it if so. Return PC otherwise. */
1614 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1616 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1619 if (target_read_memory (pc, &op, 1))
1625 if (target_read_memory (pc + 1, buf, sizeof buf) == 0)
1627 /* Make sure address is computed correctly as a 32bit
1628 integer even if CORE_ADDR is 64 bit wide. */
1629 struct minimal_symbol *s;
1630 CORE_ADDR call_dest;
1632 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1633 call_dest = call_dest & 0xffffffffU;
1634 s = lookup_minimal_symbol_by_pc (call_dest);
1636 && SYMBOL_LINKAGE_NAME (s) != NULL
1637 && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0)
1645 /* This function is 64-bit safe. */
1648 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1652 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1653 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1657 /* Normal frames. */
1660 i386_frame_cache_1 (struct frame_info *this_frame,
1661 struct i386_frame_cache *cache)
1663 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1664 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1668 cache->pc = get_frame_func (this_frame);
1670 /* In principle, for normal frames, %ebp holds the frame pointer,
1671 which holds the base address for the current stack frame.
1672 However, for functions that don't need it, the frame pointer is
1673 optional. For these "frameless" functions the frame pointer is
1674 actually the frame pointer of the calling frame. Signal
1675 trampolines are just a special case of a "frameless" function.
1676 They (usually) share their frame pointer with the frame that was
1677 in progress when the signal occurred. */
1679 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1680 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1681 if (cache->base == 0)
1684 /* For normal frames, %eip is stored at 4(%ebp). */
1685 cache->saved_regs[I386_EIP_REGNUM] = 4;
1688 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
1691 if (cache->locals < 0)
1693 /* We didn't find a valid frame, which means that CACHE->base
1694 currently holds the frame pointer for our calling frame. If
1695 we're at the start of a function, or somewhere half-way its
1696 prologue, the function's frame probably hasn't been fully
1697 setup yet. Try to reconstruct the base address for the stack
1698 frame by looking at the stack pointer. For truly "frameless"
1699 functions this might work too. */
1701 if (cache->saved_sp_reg != -1)
1703 /* Saved stack pointer has been saved. */
1704 get_frame_register (this_frame, cache->saved_sp_reg, buf);
1705 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
1707 /* We're halfway aligning the stack. */
1708 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
1709 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
1711 /* This will be added back below. */
1712 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
1714 else if (cache->pc != 0
1715 || target_read_memory (get_frame_pc (this_frame), buf, 1))
1717 /* We're in a known function, but did not find a frame
1718 setup. Assume that the function does not use %ebp.
1719 Alternatively, we may have jumped to an invalid
1720 address; in that case there is definitely no new
1722 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1723 cache->base = extract_unsigned_integer (buf, 4, byte_order)
1727 /* We're in an unknown function. We could not find the start
1728 of the function to analyze the prologue; our best option is
1729 to assume a typical frame layout with the caller's %ebp
1731 cache->saved_regs[I386_EBP_REGNUM] = 0;
1734 if (cache->saved_sp_reg != -1)
1736 /* Saved stack pointer has been saved (but the SAVED_SP_REG
1737 register may be unavailable). */
1738 if (cache->saved_sp == 0
1739 && frame_register_read (this_frame, cache->saved_sp_reg, buf))
1740 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
1742 /* Now that we have the base address for the stack frame we can
1743 calculate the value of %esp in the calling frame. */
1744 else if (cache->saved_sp == 0)
1745 cache->saved_sp = cache->base + 8;
1747 /* Adjust all the saved registers such that they contain addresses
1748 instead of offsets. */
1749 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1750 if (cache->saved_regs[i] != -1)
1751 cache->saved_regs[i] += cache->base;
1756 static struct i386_frame_cache *
1757 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
1759 volatile struct gdb_exception ex;
1760 struct i386_frame_cache *cache;
1765 cache = i386_alloc_frame_cache ();
1766 *this_cache = cache;
1768 TRY_CATCH (ex, RETURN_MASK_ERROR)
1770 i386_frame_cache_1 (this_frame, cache);
1772 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
1773 throw_exception (ex);
1779 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
1780 struct frame_id *this_id)
1782 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1784 /* This marks the outermost frame. */
1785 if (cache->base == 0)
1788 /* See the end of i386_push_dummy_call. */
1789 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
1792 static enum unwind_stop_reason
1793 i386_frame_unwind_stop_reason (struct frame_info *this_frame,
1796 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1799 return UNWIND_UNAVAILABLE;
1801 /* This marks the outermost frame. */
1802 if (cache->base == 0)
1803 return UNWIND_OUTERMOST;
1805 return UNWIND_NO_REASON;
1808 static struct value *
1809 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
1812 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1814 gdb_assert (regnum >= 0);
1816 /* The System V ABI says that:
1818 "The flags register contains the system flags, such as the
1819 direction flag and the carry flag. The direction flag must be
1820 set to the forward (that is, zero) direction before entry and
1821 upon exit from a function. Other user flags have no specified
1822 role in the standard calling sequence and are not preserved."
1824 To guarantee the "upon exit" part of that statement we fake a
1825 saved flags register that has its direction flag cleared.
1827 Note that GCC doesn't seem to rely on the fact that the direction
1828 flag is cleared after a function return; it always explicitly
1829 clears the flag before operations where it matters.
1831 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1832 right thing to do. The way we fake the flags register here makes
1833 it impossible to change it. */
1835 if (regnum == I386_EFLAGS_REGNUM)
1839 val = get_frame_register_unsigned (this_frame, regnum);
1841 return frame_unwind_got_constant (this_frame, regnum, val);
1844 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
1845 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
1847 if (regnum == I386_ESP_REGNUM
1848 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1))
1850 /* If the SP has been saved, but we don't know where, then this
1851 means that SAVED_SP_REG register was found unavailable back
1852 when we built the cache. */
1853 if (cache->saved_sp == 0)
1854 return frame_unwind_got_register (this_frame, regnum,
1855 cache->saved_sp_reg);
1857 return frame_unwind_got_constant (this_frame, regnum,
1861 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
1862 return frame_unwind_got_memory (this_frame, regnum,
1863 cache->saved_regs[regnum]);
1865 return frame_unwind_got_register (this_frame, regnum, regnum);
1868 static const struct frame_unwind i386_frame_unwind =
1871 i386_frame_unwind_stop_reason,
1873 i386_frame_prev_register,
1875 default_frame_sniffer
1878 /* Normal frames, but in a function epilogue. */
1880 /* The epilogue is defined here as the 'ret' instruction, which will
1881 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1882 the function's stack frame. */
1885 i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1888 struct symtab *symtab;
1890 symtab = find_pc_symtab (pc);
1891 if (symtab && symtab->epilogue_unwind_valid)
1894 if (target_read_memory (pc, &insn, 1))
1895 return 0; /* Can't read memory at pc. */
1897 if (insn != 0xc3) /* 'ret' instruction. */
1904 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
1905 struct frame_info *this_frame,
1906 void **this_prologue_cache)
1908 if (frame_relative_level (this_frame) == 0)
1909 return i386_in_function_epilogue_p (get_frame_arch (this_frame),
1910 get_frame_pc (this_frame));
1915 static struct i386_frame_cache *
1916 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
1918 volatile struct gdb_exception ex;
1919 struct i386_frame_cache *cache;
1925 cache = i386_alloc_frame_cache ();
1926 *this_cache = cache;
1928 TRY_CATCH (ex, RETURN_MASK_ERROR)
1930 cache->pc = get_frame_func (this_frame);
1932 /* At this point the stack looks as if we just entered the
1933 function, with the return address at the top of the
1935 sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM);
1936 cache->base = sp + cache->sp_offset;
1937 cache->saved_sp = cache->base + 8;
1938 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
1942 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
1943 throw_exception (ex);
1948 static enum unwind_stop_reason
1949 i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
1952 struct i386_frame_cache *cache =
1953 i386_epilogue_frame_cache (this_frame, this_cache);
1956 return UNWIND_UNAVAILABLE;
1958 return UNWIND_NO_REASON;
1962 i386_epilogue_frame_this_id (struct frame_info *this_frame,
1964 struct frame_id *this_id)
1966 struct i386_frame_cache *cache =
1967 i386_epilogue_frame_cache (this_frame, this_cache);
1972 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
1975 static struct value *
1976 i386_epilogue_frame_prev_register (struct frame_info *this_frame,
1977 void **this_cache, int regnum)
1979 /* Make sure we've initialized the cache. */
1980 i386_epilogue_frame_cache (this_frame, this_cache);
1982 return i386_frame_prev_register (this_frame, this_cache, regnum);
1985 static const struct frame_unwind i386_epilogue_frame_unwind =
1988 i386_epilogue_frame_unwind_stop_reason,
1989 i386_epilogue_frame_this_id,
1990 i386_epilogue_frame_prev_register,
1992 i386_epilogue_frame_sniffer
1996 /* Stack-based trampolines. */
1998 /* These trampolines are used on cross x86 targets, when taking the
1999 address of a nested function. When executing these trampolines,
2000 no stack frame is set up, so we are in a similar situation as in
2001 epilogues and i386_epilogue_frame_this_id can be re-used. */
2003 /* Static chain passed in register. */
2005 struct i386_insn i386_tramp_chain_in_reg_insns[] =
2007 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2008 { 5, { 0xb8 }, { 0xfe } },
2011 { 5, { 0xe9 }, { 0xff } },
2016 /* Static chain passed on stack (when regparm=3). */
2018 struct i386_insn i386_tramp_chain_on_stack_insns[] =
2021 { 5, { 0x68 }, { 0xff } },
2024 { 5, { 0xe9 }, { 0xff } },
2029 /* Return whether PC points inside a stack trampoline. */
2032 i386_in_stack_tramp_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2037 /* A stack trampoline is detected if no name is associated
2038 to the current pc and if it points inside a trampoline
2041 find_pc_partial_function (pc, &name, NULL, NULL);
2045 if (target_read_memory (pc, &insn, 1))
2048 if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns)
2049 && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns))
2056 i386_stack_tramp_frame_sniffer (const struct frame_unwind *self,
2057 struct frame_info *this_frame,
2060 if (frame_relative_level (this_frame) == 0)
2061 return i386_in_stack_tramp_p (get_frame_arch (this_frame),
2062 get_frame_pc (this_frame));
2067 static const struct frame_unwind i386_stack_tramp_frame_unwind =
2070 i386_epilogue_frame_unwind_stop_reason,
2071 i386_epilogue_frame_this_id,
2072 i386_epilogue_frame_prev_register,
2074 i386_stack_tramp_frame_sniffer
2078 /* Signal trampolines. */
2080 static struct i386_frame_cache *
2081 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2083 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2084 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2085 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2086 volatile struct gdb_exception ex;
2087 struct i386_frame_cache *cache;
2094 cache = i386_alloc_frame_cache ();
2096 TRY_CATCH (ex, RETURN_MASK_ERROR)
2098 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2099 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
2101 addr = tdep->sigcontext_addr (this_frame);
2102 if (tdep->sc_reg_offset)
2106 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
2108 for (i = 0; i < tdep->sc_num_regs; i++)
2109 if (tdep->sc_reg_offset[i] != -1)
2110 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2114 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
2115 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
2120 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
2121 throw_exception (ex);
2123 *this_cache = cache;
2127 static enum unwind_stop_reason
2128 i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2131 struct i386_frame_cache *cache =
2132 i386_sigtramp_frame_cache (this_frame, this_cache);
2135 return UNWIND_UNAVAILABLE;
2137 return UNWIND_NO_REASON;
2141 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
2142 struct frame_id *this_id)
2144 struct i386_frame_cache *cache =
2145 i386_sigtramp_frame_cache (this_frame, this_cache);
2150 /* See the end of i386_push_dummy_call. */
2151 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
2154 static struct value *
2155 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
2156 void **this_cache, int regnum)
2158 /* Make sure we've initialized the cache. */
2159 i386_sigtramp_frame_cache (this_frame, this_cache);
2161 return i386_frame_prev_register (this_frame, this_cache, regnum);
2165 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
2166 struct frame_info *this_frame,
2167 void **this_prologue_cache)
2169 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2171 /* We shouldn't even bother if we don't have a sigcontext_addr
2173 if (tdep->sigcontext_addr == NULL)
2176 if (tdep->sigtramp_p != NULL)
2178 if (tdep->sigtramp_p (this_frame))
2182 if (tdep->sigtramp_start != 0)
2184 CORE_ADDR pc = get_frame_pc (this_frame);
2186 gdb_assert (tdep->sigtramp_end != 0);
2187 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2194 static const struct frame_unwind i386_sigtramp_frame_unwind =
2197 i386_sigtramp_frame_unwind_stop_reason,
2198 i386_sigtramp_frame_this_id,
2199 i386_sigtramp_frame_prev_register,
2201 i386_sigtramp_frame_sniffer
2206 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
2208 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2213 static const struct frame_base i386_frame_base =
2216 i386_frame_base_address,
2217 i386_frame_base_address,
2218 i386_frame_base_address
2221 static struct frame_id
2222 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2226 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
2228 /* See the end of i386_push_dummy_call. */
2229 return frame_id_build (fp + 8, get_frame_pc (this_frame));
2232 /* _Decimal128 function return values need 16-byte alignment on the
2236 i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2238 return sp & -(CORE_ADDR)16;
2242 /* Figure out where the longjmp will land. Slurp the args out of the
2243 stack. We expect the first arg to be a pointer to the jmp_buf
2244 structure from which we extract the address that we will land at.
2245 This address is copied into PC. This routine returns non-zero on
2249 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2252 CORE_ADDR sp, jb_addr;
2253 struct gdbarch *gdbarch = get_frame_arch (frame);
2254 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2255 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2257 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2258 longjmp will land. */
2259 if (jb_pc_offset == -1)
2262 get_frame_register (frame, I386_ESP_REGNUM, buf);
2263 sp = extract_unsigned_integer (buf, 4, byte_order);
2264 if (target_read_memory (sp + 4, buf, 4))
2267 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
2268 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
2271 *pc = extract_unsigned_integer (buf, 4, byte_order);
2276 /* Check whether TYPE must be 16-byte-aligned when passed as a
2277 function argument. 16-byte vectors, _Decimal128 and structures or
2278 unions containing such types must be 16-byte-aligned; other
2279 arguments are 4-byte-aligned. */
2282 i386_16_byte_align_p (struct type *type)
2284 type = check_typedef (type);
2285 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
2286 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
2287 && TYPE_LENGTH (type) == 16)
2289 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2290 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
2291 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2292 || TYPE_CODE (type) == TYPE_CODE_UNION)
2295 for (i = 0; i < TYPE_NFIELDS (type); i++)
2297 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
2305 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2306 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2307 struct value **args, CORE_ADDR sp, int struct_return,
2308 CORE_ADDR struct_addr)
2310 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2316 /* Determine the total space required for arguments and struct
2317 return address in a first pass (allowing for 16-byte-aligned
2318 arguments), then push arguments in a second pass. */
2320 for (write_pass = 0; write_pass < 2; write_pass++)
2322 int args_space_used = 0;
2323 int have_16_byte_aligned_arg = 0;
2329 /* Push value address. */
2330 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2331 write_memory (sp, buf, 4);
2332 args_space_used += 4;
2338 for (i = 0; i < nargs; i++)
2340 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2344 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2345 args_space_used = align_up (args_space_used, 16);
2347 write_memory (sp + args_space_used,
2348 value_contents_all (args[i]), len);
2349 /* The System V ABI says that:
2351 "An argument's size is increased, if necessary, to make it a
2352 multiple of [32-bit] words. This may require tail padding,
2353 depending on the size of the argument."
2355 This makes sure the stack stays word-aligned. */
2356 args_space_used += align_up (len, 4);
2360 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2362 args_space = align_up (args_space, 16);
2363 have_16_byte_aligned_arg = 1;
2365 args_space += align_up (len, 4);
2371 if (have_16_byte_aligned_arg)
2372 args_space = align_up (args_space, 16);
2377 /* Store return address. */
2379 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2380 write_memory (sp, buf, 4);
2382 /* Finally, update the stack pointer... */
2383 store_unsigned_integer (buf, 4, byte_order, sp);
2384 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
2386 /* ...and fake a frame pointer. */
2387 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
2389 /* MarkK wrote: This "+ 8" is all over the place:
2390 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2391 i386_dummy_id). It's there, since all frame unwinders for
2392 a given target have to agree (within a certain margin) on the
2393 definition of the stack address of a frame. Otherwise frame id
2394 comparison might not work correctly. Since DWARF2/GCC uses the
2395 stack address *before* the function call as a frame's CFA. On
2396 the i386, when %ebp is used as a frame pointer, the offset
2397 between the contents %ebp and the CFA as defined by GCC. */
2401 /* These registers are used for returning integers (and on some
2402 targets also for returning `struct' and `union' values when their
2403 size and alignment match an integer type). */
2404 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2405 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2407 /* Read, for architecture GDBARCH, a function return value of TYPE
2408 from REGCACHE, and copy that into VALBUF. */
2411 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2412 struct regcache *regcache, gdb_byte *valbuf)
2414 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2415 int len = TYPE_LENGTH (type);
2416 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2418 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2420 if (tdep->st0_regnum < 0)
2422 warning (_("Cannot find floating-point return value."));
2423 memset (valbuf, 0, len);
2427 /* Floating-point return values can be found in %st(0). Convert
2428 its contents to the desired type. This is probably not
2429 exactly how it would happen on the target itself, but it is
2430 the best we can do. */
2431 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2432 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
2436 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2437 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2439 if (len <= low_size)
2441 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2442 memcpy (valbuf, buf, len);
2444 else if (len <= (low_size + high_size))
2446 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2447 memcpy (valbuf, buf, low_size);
2448 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2449 memcpy (valbuf + low_size, buf, len - low_size);
2452 internal_error (__FILE__, __LINE__,
2453 _("Cannot extract return value of %d bytes long."),
2458 /* Write, for architecture GDBARCH, a function return value of TYPE
2459 from VALBUF into REGCACHE. */
2462 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2463 struct regcache *regcache, const gdb_byte *valbuf)
2465 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2466 int len = TYPE_LENGTH (type);
2468 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2471 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2473 if (tdep->st0_regnum < 0)
2475 warning (_("Cannot set floating-point return value."));
2479 /* Returning floating-point values is a bit tricky. Apart from
2480 storing the return value in %st(0), we have to simulate the
2481 state of the FPU at function return point. */
2483 /* Convert the value found in VALBUF to the extended
2484 floating-point format used by the FPU. This is probably
2485 not exactly how it would happen on the target itself, but
2486 it is the best we can do. */
2487 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
2488 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2490 /* Set the top of the floating-point register stack to 7. The
2491 actual value doesn't really matter, but 7 is what a normal
2492 function return would end up with if the program started out
2493 with a freshly initialized FPU. */
2494 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2496 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2498 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2499 the floating-point register stack to 7, the appropriate value
2500 for the tag word is 0x3fff. */
2501 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2505 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2506 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2508 if (len <= low_size)
2509 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2510 else if (len <= (low_size + high_size))
2512 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2513 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
2514 len - low_size, valbuf + low_size);
2517 internal_error (__FILE__, __LINE__,
2518 _("Cannot store return value of %d bytes long."), len);
2523 /* This is the variable that is set with "set struct-convention", and
2524 its legitimate values. */
2525 static const char default_struct_convention[] = "default";
2526 static const char pcc_struct_convention[] = "pcc";
2527 static const char reg_struct_convention[] = "reg";
2528 static const char *valid_conventions[] =
2530 default_struct_convention,
2531 pcc_struct_convention,
2532 reg_struct_convention,
2535 static const char *struct_convention = default_struct_convention;
2537 /* Return non-zero if TYPE, which is assumed to be a structure,
2538 a union type, or an array type, should be returned in registers
2539 for architecture GDBARCH. */
2542 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2544 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2545 enum type_code code = TYPE_CODE (type);
2546 int len = TYPE_LENGTH (type);
2548 gdb_assert (code == TYPE_CODE_STRUCT
2549 || code == TYPE_CODE_UNION
2550 || code == TYPE_CODE_ARRAY);
2552 if (struct_convention == pcc_struct_convention
2553 || (struct_convention == default_struct_convention
2554 && tdep->struct_return == pcc_struct_return))
2557 /* Structures consisting of a single `float', `double' or 'long
2558 double' member are returned in %st(0). */
2559 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2561 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2562 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2563 return (len == 4 || len == 8 || len == 12);
2566 return (len == 1 || len == 2 || len == 4 || len == 8);
2569 /* Determine, for architecture GDBARCH, how a return value of TYPE
2570 should be returned. If it is supposed to be returned in registers,
2571 and READBUF is non-zero, read the appropriate value from REGCACHE,
2572 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2573 from WRITEBUF into REGCACHE. */
2575 static enum return_value_convention
2576 i386_return_value (struct gdbarch *gdbarch, struct type *func_type,
2577 struct type *type, struct regcache *regcache,
2578 gdb_byte *readbuf, const gdb_byte *writebuf)
2580 enum type_code code = TYPE_CODE (type);
2582 if (((code == TYPE_CODE_STRUCT
2583 || code == TYPE_CODE_UNION
2584 || code == TYPE_CODE_ARRAY)
2585 && !i386_reg_struct_return_p (gdbarch, type))
2586 /* 128-bit decimal float uses the struct return convention. */
2587 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2589 /* The System V ABI says that:
2591 "A function that returns a structure or union also sets %eax
2592 to the value of the original address of the caller's area
2593 before it returns. Thus when the caller receives control
2594 again, the address of the returned object resides in register
2595 %eax and can be used to access the object."
2597 So the ABI guarantees that we can always find the return
2598 value just after the function has returned. */
2600 /* Note that the ABI doesn't mention functions returning arrays,
2601 which is something possible in certain languages such as Ada.
2602 In this case, the value is returned as if it was wrapped in
2603 a record, so the convention applied to records also applies
2610 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2611 read_memory (addr, readbuf, TYPE_LENGTH (type));
2614 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2617 /* This special case is for structures consisting of a single
2618 `float', `double' or 'long double' member. These structures are
2619 returned in %st(0). For these structures, we call ourselves
2620 recursively, changing TYPE into the type of the first member of
2621 the structure. Since that should work for all structures that
2622 have only one member, we don't bother to check the member's type
2624 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2626 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2627 return i386_return_value (gdbarch, func_type, type, regcache,
2632 i386_extract_return_value (gdbarch, type, regcache, readbuf);
2634 i386_store_return_value (gdbarch, type, regcache, writebuf);
2636 return RETURN_VALUE_REGISTER_CONVENTION;
2641 i387_ext_type (struct gdbarch *gdbarch)
2643 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2645 if (!tdep->i387_ext_type)
2647 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
2648 gdb_assert (tdep->i387_ext_type != NULL);
2651 return tdep->i387_ext_type;
2654 /* Construct vector type for pseudo YMM registers. We can't use
2655 tdesc_find_type since YMM isn't described in target description. */
2657 static struct type *
2658 i386_ymm_type (struct gdbarch *gdbarch)
2660 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2662 if (!tdep->i386_ymm_type)
2664 const struct builtin_type *bt = builtin_type (gdbarch);
2666 /* The type we're building is this: */
2668 union __gdb_builtin_type_vec256i
2670 int128_t uint128[2];
2671 int64_t v2_int64[4];
2672 int32_t v4_int32[8];
2673 int16_t v8_int16[16];
2674 int8_t v16_int8[32];
2675 double v2_double[4];
2682 t = arch_composite_type (gdbarch,
2683 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
2684 append_composite_type_field (t, "v8_float",
2685 init_vector_type (bt->builtin_float, 8));
2686 append_composite_type_field (t, "v4_double",
2687 init_vector_type (bt->builtin_double, 4));
2688 append_composite_type_field (t, "v32_int8",
2689 init_vector_type (bt->builtin_int8, 32));
2690 append_composite_type_field (t, "v16_int16",
2691 init_vector_type (bt->builtin_int16, 16));
2692 append_composite_type_field (t, "v8_int32",
2693 init_vector_type (bt->builtin_int32, 8));
2694 append_composite_type_field (t, "v4_int64",
2695 init_vector_type (bt->builtin_int64, 4));
2696 append_composite_type_field (t, "v2_int128",
2697 init_vector_type (bt->builtin_int128, 2));
2699 TYPE_VECTOR (t) = 1;
2700 TYPE_NAME (t) = "builtin_type_vec256i";
2701 tdep->i386_ymm_type = t;
2704 return tdep->i386_ymm_type;
2707 /* Construct vector type for MMX registers. */
2708 static struct type *
2709 i386_mmx_type (struct gdbarch *gdbarch)
2711 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2713 if (!tdep->i386_mmx_type)
2715 const struct builtin_type *bt = builtin_type (gdbarch);
2717 /* The type we're building is this: */
2719 union __gdb_builtin_type_vec64i
2722 int32_t v2_int32[2];
2723 int16_t v4_int16[4];
2730 t = arch_composite_type (gdbarch,
2731 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
2733 append_composite_type_field (t, "uint64", bt->builtin_int64);
2734 append_composite_type_field (t, "v2_int32",
2735 init_vector_type (bt->builtin_int32, 2));
2736 append_composite_type_field (t, "v4_int16",
2737 init_vector_type (bt->builtin_int16, 4));
2738 append_composite_type_field (t, "v8_int8",
2739 init_vector_type (bt->builtin_int8, 8));
2741 TYPE_VECTOR (t) = 1;
2742 TYPE_NAME (t) = "builtin_type_vec64i";
2743 tdep->i386_mmx_type = t;
2746 return tdep->i386_mmx_type;
2749 /* Return the GDB type object for the "standard" data type of data in
2752 static struct type *
2753 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2755 if (i386_mmx_regnum_p (gdbarch, regnum))
2756 return i386_mmx_type (gdbarch);
2757 else if (i386_ymm_regnum_p (gdbarch, regnum))
2758 return i386_ymm_type (gdbarch);
2761 const struct builtin_type *bt = builtin_type (gdbarch);
2762 if (i386_byte_regnum_p (gdbarch, regnum))
2763 return bt->builtin_int8;
2764 else if (i386_word_regnum_p (gdbarch, regnum))
2765 return bt->builtin_int16;
2766 else if (i386_dword_regnum_p (gdbarch, regnum))
2767 return bt->builtin_int32;
2770 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2773 /* Map a cooked register onto a raw register or memory. For the i386,
2774 the MMX registers need to be mapped onto floating point registers. */
2777 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
2779 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
2784 mmxreg = regnum - tdep->mm0_regnum;
2785 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2786 tos = (fstat >> 11) & 0x7;
2787 fpreg = (mmxreg + tos) % 8;
2789 return (I387_ST0_REGNUM (tdep) + fpreg);
2792 /* A helper function for us by i386_pseudo_register_read_value and
2793 amd64_pseudo_register_read_value. It does all the work but reads
2794 the data into an already-allocated value. */
2797 i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
2798 struct regcache *regcache,
2800 struct value *result_value)
2802 gdb_byte raw_buf[MAX_REGISTER_SIZE];
2803 enum register_status status;
2804 gdb_byte *buf = value_contents_raw (result_value);
2806 if (i386_mmx_regnum_p (gdbarch, regnum))
2808 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2810 /* Extract (always little endian). */
2811 status = regcache_raw_read (regcache, fpnum, raw_buf);
2812 if (status != REG_VALID)
2813 mark_value_bytes_unavailable (result_value, 0,
2814 TYPE_LENGTH (value_type (result_value)));
2816 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
2820 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2822 if (i386_ymm_regnum_p (gdbarch, regnum))
2824 regnum -= tdep->ymm0_regnum;
2826 /* Extract (always little endian). Read lower 128bits. */
2827 status = regcache_raw_read (regcache,
2828 I387_XMM0_REGNUM (tdep) + regnum,
2830 if (status != REG_VALID)
2831 mark_value_bytes_unavailable (result_value, 0, 16);
2833 memcpy (buf, raw_buf, 16);
2834 /* Read upper 128bits. */
2835 status = regcache_raw_read (regcache,
2836 tdep->ymm0h_regnum + regnum,
2838 if (status != REG_VALID)
2839 mark_value_bytes_unavailable (result_value, 16, 32);
2841 memcpy (buf + 16, raw_buf, 16);
2843 else if (i386_word_regnum_p (gdbarch, regnum))
2845 int gpnum = regnum - tdep->ax_regnum;
2847 /* Extract (always little endian). */
2848 status = regcache_raw_read (regcache, gpnum, raw_buf);
2849 if (status != REG_VALID)
2850 mark_value_bytes_unavailable (result_value, 0,
2851 TYPE_LENGTH (value_type (result_value)));
2853 memcpy (buf, raw_buf, 2);
2855 else if (i386_byte_regnum_p (gdbarch, regnum))
2857 /* Check byte pseudo registers last since this function will
2858 be called from amd64_pseudo_register_read, which handles
2859 byte pseudo registers differently. */
2860 int gpnum = regnum - tdep->al_regnum;
2862 /* Extract (always little endian). We read both lower and
2864 status = regcache_raw_read (regcache, gpnum % 4, raw_buf);
2865 if (status != REG_VALID)
2866 mark_value_bytes_unavailable (result_value, 0,
2867 TYPE_LENGTH (value_type (result_value)));
2868 else if (gpnum >= 4)
2869 memcpy (buf, raw_buf + 1, 1);
2871 memcpy (buf, raw_buf, 1);
2874 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2878 static struct value *
2879 i386_pseudo_register_read_value (struct gdbarch *gdbarch,
2880 struct regcache *regcache,
2883 struct value *result;
2885 result = allocate_value (register_type (gdbarch, regnum));
2886 VALUE_LVAL (result) = lval_register;
2887 VALUE_REGNUM (result) = regnum;
2889 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result);
2895 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2896 int regnum, const gdb_byte *buf)
2898 gdb_byte raw_buf[MAX_REGISTER_SIZE];
2900 if (i386_mmx_regnum_p (gdbarch, regnum))
2902 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2905 regcache_raw_read (regcache, fpnum, raw_buf);
2906 /* ... Modify ... (always little endian). */
2907 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
2909 regcache_raw_write (regcache, fpnum, raw_buf);
2913 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2915 if (i386_ymm_regnum_p (gdbarch, regnum))
2917 regnum -= tdep->ymm0_regnum;
2919 /* ... Write lower 128bits. */
2920 regcache_raw_write (regcache,
2921 I387_XMM0_REGNUM (tdep) + regnum,
2923 /* ... Write upper 128bits. */
2924 regcache_raw_write (regcache,
2925 tdep->ymm0h_regnum + regnum,
2928 else if (i386_word_regnum_p (gdbarch, regnum))
2930 int gpnum = regnum - tdep->ax_regnum;
2933 regcache_raw_read (regcache, gpnum, raw_buf);
2934 /* ... Modify ... (always little endian). */
2935 memcpy (raw_buf, buf, 2);
2937 regcache_raw_write (regcache, gpnum, raw_buf);
2939 else if (i386_byte_regnum_p (gdbarch, regnum))
2941 /* Check byte pseudo registers last since this function will
2942 be called from amd64_pseudo_register_read, which handles
2943 byte pseudo registers differently. */
2944 int gpnum = regnum - tdep->al_regnum;
2946 /* Read ... We read both lower and upper registers. */
2947 regcache_raw_read (regcache, gpnum % 4, raw_buf);
2948 /* ... Modify ... (always little endian). */
2950 memcpy (raw_buf + 1, buf, 1);
2952 memcpy (raw_buf, buf, 1);
2954 regcache_raw_write (regcache, gpnum % 4, raw_buf);
2957 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2962 /* Return the register number of the register allocated by GCC after
2963 REGNUM, or -1 if there is no such register. */
2966 i386_next_regnum (int regnum)
2968 /* GCC allocates the registers in the order:
2970 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2972 Since storing a variable in %esp doesn't make any sense we return
2973 -1 for %ebp and for %esp itself. */
2974 static int next_regnum[] =
2976 I386_EDX_REGNUM, /* Slot for %eax. */
2977 I386_EBX_REGNUM, /* Slot for %ecx. */
2978 I386_ECX_REGNUM, /* Slot for %edx. */
2979 I386_ESI_REGNUM, /* Slot for %ebx. */
2980 -1, -1, /* Slots for %esp and %ebp. */
2981 I386_EDI_REGNUM, /* Slot for %esi. */
2982 I386_EBP_REGNUM /* Slot for %edi. */
2985 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
2986 return next_regnum[regnum];
2991 /* Return nonzero if a value of type TYPE stored in register REGNUM
2992 needs any special handling. */
2995 i386_convert_register_p (struct gdbarch *gdbarch,
2996 int regnum, struct type *type)
2998 int len = TYPE_LENGTH (type);
3000 /* Values may be spread across multiple registers. Most debugging
3001 formats aren't expressive enough to specify the locations, so
3002 some heuristics is involved. Right now we only handle types that
3003 have a length that is a multiple of the word size, since GCC
3004 doesn't seem to put any other types into registers. */
3005 if (len > 4 && len % 4 == 0)
3007 int last_regnum = regnum;
3011 last_regnum = i386_next_regnum (last_regnum);
3015 if (last_regnum != -1)
3019 return i387_convert_register_p (gdbarch, regnum, type);
3022 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3023 return its contents in TO. */
3026 i386_register_to_value (struct frame_info *frame, int regnum,
3027 struct type *type, gdb_byte *to,
3028 int *optimizedp, int *unavailablep)
3030 struct gdbarch *gdbarch = get_frame_arch (frame);
3031 int len = TYPE_LENGTH (type);
3033 if (i386_fp_regnum_p (gdbarch, regnum))
3034 return i387_register_to_value (frame, regnum, type, to,
3035 optimizedp, unavailablep);
3037 /* Read a value spread across multiple registers. */
3039 gdb_assert (len > 4 && len % 4 == 0);
3043 gdb_assert (regnum != -1);
3044 gdb_assert (register_size (gdbarch, regnum) == 4);
3046 if (!get_frame_register_bytes (frame, regnum, 0,
3047 register_size (gdbarch, regnum),
3048 to, optimizedp, unavailablep))
3051 regnum = i386_next_regnum (regnum);
3056 *optimizedp = *unavailablep = 0;
3060 /* Write the contents FROM of a value of type TYPE into register
3061 REGNUM in frame FRAME. */
3064 i386_value_to_register (struct frame_info *frame, int regnum,
3065 struct type *type, const gdb_byte *from)
3067 int len = TYPE_LENGTH (type);
3069 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
3071 i387_value_to_register (frame, regnum, type, from);
3075 /* Write a value spread across multiple registers. */
3077 gdb_assert (len > 4 && len % 4 == 0);
3081 gdb_assert (regnum != -1);
3082 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
3084 put_frame_register (frame, regnum, from);
3085 regnum = i386_next_regnum (regnum);
3091 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3092 in the general-purpose register set REGSET to register cache
3093 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3096 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
3097 int regnum, const void *gregs, size_t len)
3099 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3100 const gdb_byte *regs = gregs;
3103 gdb_assert (len == tdep->sizeof_gregset);
3105 for (i = 0; i < tdep->gregset_num_regs; i++)
3107 if ((regnum == i || regnum == -1)
3108 && tdep->gregset_reg_offset[i] != -1)
3109 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
3113 /* Collect register REGNUM from the register cache REGCACHE and store
3114 it in the buffer specified by GREGS and LEN as described by the
3115 general-purpose register set REGSET. If REGNUM is -1, do this for
3116 all registers in REGSET. */
3119 i386_collect_gregset (const struct regset *regset,
3120 const struct regcache *regcache,
3121 int regnum, void *gregs, size_t len)
3123 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3124 gdb_byte *regs = gregs;
3127 gdb_assert (len == tdep->sizeof_gregset);
3129 for (i = 0; i < tdep->gregset_num_regs; i++)
3131 if ((regnum == i || regnum == -1)
3132 && tdep->gregset_reg_offset[i] != -1)
3133 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
3137 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3138 in the floating-point register set REGSET to register cache
3139 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3142 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
3143 int regnum, const void *fpregs, size_t len)
3145 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3147 if (len == I387_SIZEOF_FXSAVE)
3149 i387_supply_fxsave (regcache, regnum, fpregs);
3153 gdb_assert (len == tdep->sizeof_fpregset);
3154 i387_supply_fsave (regcache, regnum, fpregs);
3157 /* Collect register REGNUM from the register cache REGCACHE and store
3158 it in the buffer specified by FPREGS and LEN as described by the
3159 floating-point register set REGSET. If REGNUM is -1, do this for
3160 all registers in REGSET. */
3163 i386_collect_fpregset (const struct regset *regset,
3164 const struct regcache *regcache,
3165 int regnum, void *fpregs, size_t len)
3167 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
3169 if (len == I387_SIZEOF_FXSAVE)
3171 i387_collect_fxsave (regcache, regnum, fpregs);
3175 gdb_assert (len == tdep->sizeof_fpregset);
3176 i387_collect_fsave (regcache, regnum, fpregs);
3179 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
3182 i386_supply_xstateregset (const struct regset *regset,
3183 struct regcache *regcache, int regnum,
3184 const void *xstateregs, size_t len)
3186 i387_supply_xsave (regcache, regnum, xstateregs);
3189 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
3192 i386_collect_xstateregset (const struct regset *regset,
3193 const struct regcache *regcache,
3194 int regnum, void *xstateregs, size_t len)
3196 i387_collect_xsave (regcache, regnum, xstateregs, 1);
3199 /* Return the appropriate register set for the core section identified
3200 by SECT_NAME and SECT_SIZE. */
3202 const struct regset *
3203 i386_regset_from_core_section (struct gdbarch *gdbarch,
3204 const char *sect_name, size_t sect_size)
3206 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3208 if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset)
3210 if (tdep->gregset == NULL)
3211 tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset,
3212 i386_collect_gregset);
3213 return tdep->gregset;
3216 if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
3217 || (strcmp (sect_name, ".reg-xfp") == 0
3218 && sect_size == I387_SIZEOF_FXSAVE))
3220 if (tdep->fpregset == NULL)
3221 tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset,
3222 i386_collect_fpregset);
3223 return tdep->fpregset;
3226 if (strcmp (sect_name, ".reg-xstate") == 0)
3228 if (tdep->xstateregset == NULL)
3229 tdep->xstateregset = regset_alloc (gdbarch,
3230 i386_supply_xstateregset,
3231 i386_collect_xstateregset);
3233 return tdep->xstateregset;
3240 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3243 i386_pe_skip_trampoline_code (struct frame_info *frame,
3244 CORE_ADDR pc, char *name)
3246 struct gdbarch *gdbarch = get_frame_arch (frame);
3247 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3250 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
3252 unsigned long indirect =
3253 read_memory_unsigned_integer (pc + 2, 4, byte_order);
3254 struct minimal_symbol *indsym =
3255 indirect ? lookup_minimal_symbol_by_pc (indirect) : 0;
3256 char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0;
3260 if (strncmp (symname, "__imp_", 6) == 0
3261 || strncmp (symname, "_imp_", 5) == 0)
3263 read_memory_unsigned_integer (indirect, 4, byte_order);
3266 return 0; /* Not a trampoline. */
3270 /* Return whether the THIS_FRAME corresponds to a sigtramp
3274 i386_sigtramp_p (struct frame_info *this_frame)
3276 CORE_ADDR pc = get_frame_pc (this_frame);
3279 find_pc_partial_function (pc, &name, NULL, NULL);
3280 return (name && strcmp ("_sigtramp", name) == 0);
3284 /* We have two flavours of disassembly. The machinery on this page
3285 deals with switching between those. */
3288 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
3290 gdb_assert (disassembly_flavor == att_flavor
3291 || disassembly_flavor == intel_flavor);
3293 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3294 constified, cast to prevent a compiler warning. */
3295 info->disassembler_options = (char *) disassembly_flavor;
3297 return print_insn_i386 (pc, info);
3301 /* There are a few i386 architecture variants that differ only
3302 slightly from the generic i386 target. For now, we don't give them
3303 their own source file, but include them here. As a consequence,
3304 they'll always be included. */
3306 /* System V Release 4 (SVR4). */
3308 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3312 i386_svr4_sigtramp_p (struct frame_info *this_frame)
3314 CORE_ADDR pc = get_frame_pc (this_frame);
3317 /* UnixWare uses _sigacthandler. The origin of the other symbols is
3318 currently unknown. */
3319 find_pc_partial_function (pc, &name, NULL, NULL);
3320 return (name && (strcmp ("_sigreturn", name) == 0
3321 || strcmp ("_sigacthandler", name) == 0
3322 || strcmp ("sigvechandler", name) == 0));
3325 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3326 address of the associated sigcontext (ucontext) structure. */
3329 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
3331 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3332 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3336 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
3337 sp = extract_unsigned_integer (buf, 4, byte_order);
3339 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
3346 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3348 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3349 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3352 /* System V Release 4 (SVR4). */
3355 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3357 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3359 /* System V Release 4 uses ELF. */
3360 i386_elf_init_abi (info, gdbarch);
3362 /* System V Release 4 has shared libraries. */
3363 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
3365 tdep->sigtramp_p = i386_svr4_sigtramp_p;
3366 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
3367 tdep->sc_pc_offset = 36 + 14 * 4;
3368 tdep->sc_sp_offset = 36 + 17 * 4;
3370 tdep->jb_pc_offset = 20;
3376 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3378 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3380 /* DJGPP doesn't have any special frames for signal handlers. */
3381 tdep->sigtramp_p = NULL;
3383 tdep->jb_pc_offset = 36;
3385 /* DJGPP does not support the SSE registers. */
3386 if (! tdesc_has_registers (info.target_desc))
3387 tdep->tdesc = tdesc_i386_mmx;
3389 /* Native compiler is GCC, which uses the SVR4 register numbering
3390 even in COFF and STABS. See the comment in i386_gdbarch_init,
3391 before the calls to set_gdbarch_stab_reg_to_regnum and
3392 set_gdbarch_sdb_reg_to_regnum. */
3393 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3394 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3396 set_gdbarch_has_dos_based_file_system (gdbarch, 1);
3400 /* i386 register groups. In addition to the normal groups, add "mmx"
3403 static struct reggroup *i386_sse_reggroup;
3404 static struct reggroup *i386_mmx_reggroup;
3407 i386_init_reggroups (void)
3409 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
3410 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
3414 i386_add_reggroups (struct gdbarch *gdbarch)
3416 reggroup_add (gdbarch, i386_sse_reggroup);
3417 reggroup_add (gdbarch, i386_mmx_reggroup);
3418 reggroup_add (gdbarch, general_reggroup);
3419 reggroup_add (gdbarch, float_reggroup);
3420 reggroup_add (gdbarch, all_reggroup);
3421 reggroup_add (gdbarch, save_reggroup);
3422 reggroup_add (gdbarch, restore_reggroup);
3423 reggroup_add (gdbarch, vector_reggroup);
3424 reggroup_add (gdbarch, system_reggroup);
3428 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
3429 struct reggroup *group)
3431 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3432 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
3433 ymm_regnum_p, ymmh_regnum_p;
3435 /* Don't include pseudo registers, except for MMX, in any register
3437 if (i386_byte_regnum_p (gdbarch, regnum))
3440 if (i386_word_regnum_p (gdbarch, regnum))
3443 if (i386_dword_regnum_p (gdbarch, regnum))
3446 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
3447 if (group == i386_mmx_reggroup)
3448 return mmx_regnum_p;
3450 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
3451 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
3452 if (group == i386_sse_reggroup)
3453 return xmm_regnum_p || mxcsr_regnum_p;
3455 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
3456 if (group == vector_reggroup)
3457 return (mmx_regnum_p
3461 && ((tdep->xcr0 & I386_XSTATE_AVX_MASK)
3462 == I386_XSTATE_SSE_MASK)));
3464 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
3465 || i386_fpc_regnum_p (gdbarch, regnum));
3466 if (group == float_reggroup)
3469 /* For "info reg all", don't include upper YMM registers nor XMM
3470 registers when AVX is supported. */
3471 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
3472 if (group == all_reggroup
3474 && (tdep->xcr0 & I386_XSTATE_AVX))
3478 if (group == general_reggroup)
3479 return (!fp_regnum_p
3486 return default_register_reggroup_p (gdbarch, regnum, group);
3490 /* Get the ARGIth function argument for the current function. */
3493 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
3496 struct gdbarch *gdbarch = get_frame_arch (frame);
3497 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3498 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
3499 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
3503 i386_skip_permanent_breakpoint (struct regcache *regcache)
3505 CORE_ADDR current_pc = regcache_read_pc (regcache);
3507 /* On i386, breakpoint is exactly 1 byte long, so we just
3508 adjust the PC in the regcache. */
3510 regcache_write_pc (regcache, current_pc);
3514 #define PREFIX_REPZ 0x01
3515 #define PREFIX_REPNZ 0x02
3516 #define PREFIX_LOCK 0x04
3517 #define PREFIX_DATA 0x08
3518 #define PREFIX_ADDR 0x10
3530 /* i386 arith/logic operations */
3543 struct i386_record_s
3545 struct gdbarch *gdbarch;
3546 struct regcache *regcache;
3547 CORE_ADDR orig_addr;
3553 uint8_t mod, reg, rm;
3562 /* Parse "modrm" part in current memory address that irp->addr point to
3563 Return -1 if something wrong. */
3566 i386_record_modrm (struct i386_record_s *irp)
3568 struct gdbarch *gdbarch = irp->gdbarch;
3570 if (target_read_memory (irp->addr, &irp->modrm, 1))
3573 printf_unfiltered (_("Process record: error reading memory at "
3574 "addr %s len = 1.\n"),
3575 paddress (gdbarch, irp->addr));
3579 irp->mod = (irp->modrm >> 6) & 3;
3580 irp->reg = (irp->modrm >> 3) & 7;
3581 irp->rm = irp->modrm & 7;
3586 /* Get the memory address that current instruction write to and set it to
3587 the argument "addr".
3588 Return -1 if something wrong. */
3591 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
3593 struct gdbarch *gdbarch = irp->gdbarch;
3594 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3606 uint8_t base = irp->rm;
3611 if (target_read_memory (irp->addr, &byte, 1))
3614 printf_unfiltered (_("Process record: error reading memory "
3615 "at addr %s len = 1.\n"),
3616 paddress (gdbarch, irp->addr));
3620 scale = (byte >> 6) & 3;
3621 index = ((byte >> 3) & 7) | irp->rex_x;
3629 if ((base & 7) == 5)
3632 if (target_read_memory (irp->addr, buf, 4))
3635 printf_unfiltered (_("Process record: error reading "
3636 "memory at addr %s len = 4.\n"),
3637 paddress (gdbarch, irp->addr));
3641 *addr = extract_signed_integer (buf, 4, byte_order);
3642 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
3643 *addr += irp->addr + irp->rip_offset;
3647 if (target_read_memory (irp->addr, buf, 1))
3650 printf_unfiltered (_("Process record: error reading memory "
3651 "at addr %s len = 1.\n"),
3652 paddress (gdbarch, irp->addr));
3656 *addr = (int8_t) buf[0];
3659 if (target_read_memory (irp->addr, buf, 4))
3662 printf_unfiltered (_("Process record: error reading memory "
3663 "at addr %s len = 4.\n"),
3664 paddress (gdbarch, irp->addr));
3667 *addr = extract_signed_integer (buf, 4, byte_order);
3675 if (base == 4 && irp->popl_esp_hack)
3676 *addr += irp->popl_esp_hack;
3677 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
3680 if (irp->aflag == 2)
3685 *addr = (uint32_t) (offset64 + *addr);
3687 if (havesib && (index != 4 || scale != 0))
3689 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
3691 if (irp->aflag == 2)
3692 *addr += offset64 << scale;
3694 *addr = (uint32_t) (*addr + (offset64 << scale));
3705 if (target_read_memory (irp->addr, buf, 2))
3708 printf_unfiltered (_("Process record: error reading "
3709 "memory at addr %s len = 2.\n"),
3710 paddress (gdbarch, irp->addr));
3714 *addr = extract_signed_integer (buf, 2, byte_order);
3720 if (target_read_memory (irp->addr, buf, 1))
3723 printf_unfiltered (_("Process record: error reading memory "
3724 "at addr %s len = 1.\n"),
3725 paddress (gdbarch, irp->addr));
3729 *addr = (int8_t) buf[0];
3732 if (target_read_memory (irp->addr, buf, 2))
3735 printf_unfiltered (_("Process record: error reading memory "
3736 "at addr %s len = 2.\n"),
3737 paddress (gdbarch, irp->addr));
3741 *addr = extract_signed_integer (buf, 2, byte_order);
3748 regcache_raw_read_unsigned (irp->regcache,
3749 irp->regmap[X86_RECORD_REBX_REGNUM],
3751 *addr = (uint32_t) (*addr + offset64);
3752 regcache_raw_read_unsigned (irp->regcache,
3753 irp->regmap[X86_RECORD_RESI_REGNUM],
3755 *addr = (uint32_t) (*addr + offset64);
3758 regcache_raw_read_unsigned (irp->regcache,
3759 irp->regmap[X86_RECORD_REBX_REGNUM],
3761 *addr = (uint32_t) (*addr + offset64);
3762 regcache_raw_read_unsigned (irp->regcache,
3763 irp->regmap[X86_RECORD_REDI_REGNUM],
3765 *addr = (uint32_t) (*addr + offset64);
3768 regcache_raw_read_unsigned (irp->regcache,
3769 irp->regmap[X86_RECORD_REBP_REGNUM],
3771 *addr = (uint32_t) (*addr + offset64);
3772 regcache_raw_read_unsigned (irp->regcache,
3773 irp->regmap[X86_RECORD_RESI_REGNUM],
3775 *addr = (uint32_t) (*addr + offset64);
3778 regcache_raw_read_unsigned (irp->regcache,
3779 irp->regmap[X86_RECORD_REBP_REGNUM],
3781 *addr = (uint32_t) (*addr + offset64);
3782 regcache_raw_read_unsigned (irp->regcache,
3783 irp->regmap[X86_RECORD_REDI_REGNUM],
3785 *addr = (uint32_t) (*addr + offset64);
3788 regcache_raw_read_unsigned (irp->regcache,
3789 irp->regmap[X86_RECORD_RESI_REGNUM],
3791 *addr = (uint32_t) (*addr + offset64);
3794 regcache_raw_read_unsigned (irp->regcache,
3795 irp->regmap[X86_RECORD_REDI_REGNUM],
3797 *addr = (uint32_t) (*addr + offset64);
3800 regcache_raw_read_unsigned (irp->regcache,
3801 irp->regmap[X86_RECORD_REBP_REGNUM],
3803 *addr = (uint32_t) (*addr + offset64);
3806 regcache_raw_read_unsigned (irp->regcache,
3807 irp->regmap[X86_RECORD_REBX_REGNUM],
3809 *addr = (uint32_t) (*addr + offset64);
3819 /* Record the value of the memory that willbe changed in current instruction
3820 to "record_arch_list".
3821 Return -1 if something wrong. */
3824 i386_record_lea_modrm (struct i386_record_s *irp)
3826 struct gdbarch *gdbarch = irp->gdbarch;
3829 if (irp->override >= 0)
3831 if (record_memory_query)
3835 target_terminal_ours ();
3837 Process record ignores the memory change of instruction at address %s\n\
3838 because it can't get the value of the segment register.\n\
3839 Do you want to stop the program?"),
3840 paddress (gdbarch, irp->orig_addr));
3841 target_terminal_inferior ();
3849 if (i386_record_lea_modrm_addr (irp, &addr))
3852 if (record_arch_list_add_mem (addr, 1 << irp->ot))
3858 /* Record the push operation to "record_arch_list".
3859 Return -1 if something wrong. */
3862 i386_record_push (struct i386_record_s *irp, int size)
3866 if (record_arch_list_add_reg (irp->regcache,
3867 irp->regmap[X86_RECORD_RESP_REGNUM]))
3869 regcache_raw_read_unsigned (irp->regcache,
3870 irp->regmap[X86_RECORD_RESP_REGNUM],
3872 if (record_arch_list_add_mem ((CORE_ADDR) addr - size, size))
3879 /* Defines contents to record. */
3880 #define I386_SAVE_FPU_REGS 0xfffd
3881 #define I386_SAVE_FPU_ENV 0xfffe
3882 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3884 /* Record the value of floating point registers which will be changed
3885 by the current instruction to "record_arch_list". Return -1 if
3886 something is wrong. */
3888 static int i386_record_floats (struct gdbarch *gdbarch,
3889 struct i386_record_s *ir,
3892 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3895 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3896 happen. Currently we store st0-st7 registers, but we need not store all
3897 registers all the time, in future we use ftag register and record only
3898 those who are not marked as an empty. */
3900 if (I386_SAVE_FPU_REGS == iregnum)
3902 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
3904 if (record_arch_list_add_reg (ir->regcache, i))
3908 else if (I386_SAVE_FPU_ENV == iregnum)
3910 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3912 if (record_arch_list_add_reg (ir->regcache, i))
3916 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
3918 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3920 if (record_arch_list_add_reg (ir->regcache, i))
3924 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
3925 (iregnum <= I387_FOP_REGNUM (tdep)))
3927 if (record_arch_list_add_reg (ir->regcache,iregnum))
3932 /* Parameter error. */
3935 if(I386_SAVE_FPU_ENV != iregnum)
3937 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3939 if (record_arch_list_add_reg (ir->regcache, i))
3946 /* Parse the current instruction and record the values of the registers and
3947 memory that will be changed in current instruction to "record_arch_list".
3948 Return -1 if something wrong. */
3950 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3951 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3954 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
3955 CORE_ADDR input_addr)
3957 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3963 gdb_byte buf[MAX_REGISTER_SIZE];
3964 struct i386_record_s ir;
3965 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3970 memset (&ir, 0, sizeof (struct i386_record_s));
3971 ir.regcache = regcache;
3972 ir.addr = input_addr;
3973 ir.orig_addr = input_addr;
3977 ir.popl_esp_hack = 0;
3978 ir.regmap = tdep->record_regmap;
3979 ir.gdbarch = gdbarch;
3981 if (record_debug > 1)
3982 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
3984 paddress (gdbarch, ir.addr));
3989 if (target_read_memory (ir.addr, &opcode8, 1))
3992 printf_unfiltered (_("Process record: error reading memory at "
3993 "addr %s len = 1.\n"),
3994 paddress (gdbarch, ir.addr));
3998 switch (opcode8) /* Instruction prefixes */
4000 case REPE_PREFIX_OPCODE:
4001 prefixes |= PREFIX_REPZ;
4003 case REPNE_PREFIX_OPCODE:
4004 prefixes |= PREFIX_REPNZ;
4006 case LOCK_PREFIX_OPCODE:
4007 prefixes |= PREFIX_LOCK;
4009 case CS_PREFIX_OPCODE:
4010 ir.override = X86_RECORD_CS_REGNUM;
4012 case SS_PREFIX_OPCODE:
4013 ir.override = X86_RECORD_SS_REGNUM;
4015 case DS_PREFIX_OPCODE:
4016 ir.override = X86_RECORD_DS_REGNUM;
4018 case ES_PREFIX_OPCODE:
4019 ir.override = X86_RECORD_ES_REGNUM;
4021 case FS_PREFIX_OPCODE:
4022 ir.override = X86_RECORD_FS_REGNUM;
4024 case GS_PREFIX_OPCODE:
4025 ir.override = X86_RECORD_GS_REGNUM;
4027 case DATA_PREFIX_OPCODE:
4028 prefixes |= PREFIX_DATA;
4030 case ADDR_PREFIX_OPCODE:
4031 prefixes |= PREFIX_ADDR;
4033 case 0x40: /* i386 inc %eax */
4034 case 0x41: /* i386 inc %ecx */
4035 case 0x42: /* i386 inc %edx */
4036 case 0x43: /* i386 inc %ebx */
4037 case 0x44: /* i386 inc %esp */
4038 case 0x45: /* i386 inc %ebp */
4039 case 0x46: /* i386 inc %esi */
4040 case 0x47: /* i386 inc %edi */
4041 case 0x48: /* i386 dec %eax */
4042 case 0x49: /* i386 dec %ecx */
4043 case 0x4a: /* i386 dec %edx */
4044 case 0x4b: /* i386 dec %ebx */
4045 case 0x4c: /* i386 dec %esp */
4046 case 0x4d: /* i386 dec %ebp */
4047 case 0x4e: /* i386 dec %esi */
4048 case 0x4f: /* i386 dec %edi */
4049 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
4053 rex_w = (opcode8 >> 3) & 1;
4054 rex_r = (opcode8 & 0x4) << 1;
4055 ir.rex_x = (opcode8 & 0x2) << 2;
4056 ir.rex_b = (opcode8 & 0x1) << 3;
4058 else /* 32 bit target */
4067 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
4073 if (prefixes & PREFIX_DATA)
4076 if (prefixes & PREFIX_ADDR)
4078 else if (ir.regmap[X86_RECORD_R8_REGNUM])
4081 /* Now check op code. */
4082 opcode = (uint32_t) opcode8;
4087 if (target_read_memory (ir.addr, &opcode8, 1))
4090 printf_unfiltered (_("Process record: error reading memory at "
4091 "addr %s len = 1.\n"),
4092 paddress (gdbarch, ir.addr));
4096 opcode = (uint32_t) opcode8 | 0x0f00;
4100 case 0x00: /* arith & logic */
4148 if (((opcode >> 3) & 7) != OP_CMPL)
4150 if ((opcode & 1) == 0)
4153 ir.ot = ir.dflag + OT_WORD;
4155 switch ((opcode >> 1) & 3)
4157 case 0: /* OP Ev, Gv */
4158 if (i386_record_modrm (&ir))
4162 if (i386_record_lea_modrm (&ir))
4168 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4170 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4173 case 1: /* OP Gv, Ev */
4174 if (i386_record_modrm (&ir))
4177 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4179 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4181 case 2: /* OP A, Iv */
4182 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4186 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4189 case 0x80: /* GRP1 */
4193 if (i386_record_modrm (&ir))
4196 if (ir.reg != OP_CMPL)
4198 if ((opcode & 1) == 0)
4201 ir.ot = ir.dflag + OT_WORD;
4208 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4209 if (i386_record_lea_modrm (&ir))
4213 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
4215 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4218 case 0x40: /* inc */
4227 case 0x48: /* dec */
4236 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7);
4237 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4240 case 0xf6: /* GRP3 */
4242 if ((opcode & 1) == 0)
4245 ir.ot = ir.dflag + OT_WORD;
4246 if (i386_record_modrm (&ir))
4249 if (ir.mod != 3 && ir.reg == 0)
4250 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4255 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4261 if (i386_record_lea_modrm (&ir))
4267 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4269 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4271 if (ir.reg == 3) /* neg */
4272 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4278 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4279 if (ir.ot != OT_BYTE)
4280 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
4281 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4285 opcode = opcode << 8 | ir.modrm;
4291 case 0xfe: /* GRP4 */
4292 case 0xff: /* GRP5 */
4293 if (i386_record_modrm (&ir))
4295 if (ir.reg >= 2 && opcode == 0xfe)
4298 opcode = opcode << 8 | ir.modrm;
4305 if ((opcode & 1) == 0)
4308 ir.ot = ir.dflag + OT_WORD;
4311 if (i386_record_lea_modrm (&ir))
4317 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4319 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4321 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4324 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4326 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4328 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4331 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
4332 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4334 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4338 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4341 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4343 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4348 opcode = opcode << 8 | ir.modrm;
4354 case 0x84: /* test */
4358 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4361 case 0x98: /* CWDE/CBW */
4362 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4365 case 0x99: /* CDQ/CWD */
4366 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4367 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
4370 case 0x0faf: /* imul */
4373 ir.ot = ir.dflag + OT_WORD;
4374 if (i386_record_modrm (&ir))
4377 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4378 else if (opcode == 0x6b)
4381 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4383 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4384 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4387 case 0x0fc0: /* xadd */
4389 if ((opcode & 1) == 0)
4392 ir.ot = ir.dflag + OT_WORD;
4393 if (i386_record_modrm (&ir))
4398 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4400 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4401 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4403 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4407 if (i386_record_lea_modrm (&ir))
4409 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4411 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4413 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4416 case 0x0fb0: /* cmpxchg */
4418 if ((opcode & 1) == 0)
4421 ir.ot = ir.dflag + OT_WORD;
4422 if (i386_record_modrm (&ir))
4427 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4428 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4430 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4434 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4435 if (i386_record_lea_modrm (&ir))
4438 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4441 case 0x0fc7: /* cmpxchg8b */
4442 if (i386_record_modrm (&ir))
4447 opcode = opcode << 8 | ir.modrm;
4450 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4451 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
4452 if (i386_record_lea_modrm (&ir))
4454 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4457 case 0x50: /* push */
4467 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4469 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4473 case 0x06: /* push es */
4474 case 0x0e: /* push cs */
4475 case 0x16: /* push ss */
4476 case 0x1e: /* push ds */
4477 if (ir.regmap[X86_RECORD_R8_REGNUM])
4482 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4486 case 0x0fa0: /* push fs */
4487 case 0x0fa8: /* push gs */
4488 if (ir.regmap[X86_RECORD_R8_REGNUM])
4493 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4497 case 0x60: /* pusha */
4498 if (ir.regmap[X86_RECORD_R8_REGNUM])
4503 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
4507 case 0x58: /* pop */
4515 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4516 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
4519 case 0x61: /* popa */
4520 if (ir.regmap[X86_RECORD_R8_REGNUM])
4525 for (regnum = X86_RECORD_REAX_REGNUM;
4526 regnum <= X86_RECORD_REDI_REGNUM;
4528 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
4531 case 0x8f: /* pop */
4532 if (ir.regmap[X86_RECORD_R8_REGNUM])
4533 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
4535 ir.ot = ir.dflag + OT_WORD;
4536 if (i386_record_modrm (&ir))
4539 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
4542 ir.popl_esp_hack = 1 << ir.ot;
4543 if (i386_record_lea_modrm (&ir))
4546 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4549 case 0xc8: /* enter */
4550 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
4551 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4553 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4557 case 0xc9: /* leave */
4558 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4559 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
4562 case 0x07: /* pop es */
4563 if (ir.regmap[X86_RECORD_R8_REGNUM])
4568 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4569 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
4570 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4573 case 0x17: /* pop ss */
4574 if (ir.regmap[X86_RECORD_R8_REGNUM])
4579 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4580 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
4581 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4584 case 0x1f: /* pop ds */
4585 if (ir.regmap[X86_RECORD_R8_REGNUM])
4590 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4591 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
4592 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4595 case 0x0fa1: /* pop fs */
4596 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4597 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
4598 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4601 case 0x0fa9: /* pop gs */
4602 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4603 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
4604 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4607 case 0x88: /* mov */
4611 if ((opcode & 1) == 0)
4614 ir.ot = ir.dflag + OT_WORD;
4616 if (i386_record_modrm (&ir))
4621 if (opcode == 0xc6 || opcode == 0xc7)
4622 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4623 if (i386_record_lea_modrm (&ir))
4628 if (opcode == 0xc6 || opcode == 0xc7)
4630 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4632 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4636 case 0x8a: /* mov */
4638 if ((opcode & 1) == 0)
4641 ir.ot = ir.dflag + OT_WORD;
4642 if (i386_record_modrm (&ir))
4645 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4647 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4650 case 0x8c: /* mov seg */
4651 if (i386_record_modrm (&ir))
4656 opcode = opcode << 8 | ir.modrm;
4661 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4665 if (i386_record_lea_modrm (&ir))
4670 case 0x8e: /* mov seg */
4671 if (i386_record_modrm (&ir))
4676 regnum = X86_RECORD_ES_REGNUM;
4679 regnum = X86_RECORD_SS_REGNUM;
4682 regnum = X86_RECORD_DS_REGNUM;
4685 regnum = X86_RECORD_FS_REGNUM;
4688 regnum = X86_RECORD_GS_REGNUM;
4692 opcode = opcode << 8 | ir.modrm;
4696 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
4697 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4700 case 0x0fb6: /* movzbS */
4701 case 0x0fb7: /* movzwS */
4702 case 0x0fbe: /* movsbS */
4703 case 0x0fbf: /* movswS */
4704 if (i386_record_modrm (&ir))
4706 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
4709 case 0x8d: /* lea */
4710 if (i386_record_modrm (&ir))
4715 opcode = opcode << 8 | ir.modrm;
4720 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4722 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4725 case 0xa0: /* mov EAX */
4728 case 0xd7: /* xlat */
4729 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4732 case 0xa2: /* mov EAX */
4734 if (ir.override >= 0)
4736 if (record_memory_query)
4740 target_terminal_ours ();
4742 Process record ignores the memory change of instruction at address %s\n\
4743 because it can't get the value of the segment register.\n\
4744 Do you want to stop the program?"),
4745 paddress (gdbarch, ir.orig_addr));
4746 target_terminal_inferior ();
4753 if ((opcode & 1) == 0)
4756 ir.ot = ir.dflag + OT_WORD;
4759 if (target_read_memory (ir.addr, buf, 8))
4762 printf_unfiltered (_("Process record: error reading "
4763 "memory at addr 0x%s len = 8.\n"),
4764 paddress (gdbarch, ir.addr));
4768 addr = extract_unsigned_integer (buf, 8, byte_order);
4772 if (target_read_memory (ir.addr, buf, 4))
4775 printf_unfiltered (_("Process record: error reading "
4776 "memory at addr 0x%s len = 4.\n"),
4777 paddress (gdbarch, ir.addr));
4781 addr = extract_unsigned_integer (buf, 4, byte_order);
4785 if (target_read_memory (ir.addr, buf, 2))
4788 printf_unfiltered (_("Process record: error reading "
4789 "memory at addr 0x%s len = 2.\n"),
4790 paddress (gdbarch, ir.addr));
4794 addr = extract_unsigned_integer (buf, 2, byte_order);
4796 if (record_arch_list_add_mem (addr, 1 << ir.ot))
4801 case 0xb0: /* mov R, Ib */
4809 I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
4810 ? ((opcode & 0x7) | ir.rex_b)
4811 : ((opcode & 0x7) & 0x3));
4814 case 0xb8: /* mov R, Iv */
4822 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
4825 case 0x91: /* xchg R, EAX */
4832 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4833 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7);
4836 case 0x86: /* xchg Ev, Gv */
4838 if ((opcode & 1) == 0)
4841 ir.ot = ir.dflag + OT_WORD;
4842 if (i386_record_modrm (&ir))
4847 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4849 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4853 if (i386_record_lea_modrm (&ir))
4857 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4859 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4862 case 0xc4: /* les Gv */
4863 case 0xc5: /* lds Gv */
4864 if (ir.regmap[X86_RECORD_R8_REGNUM])
4870 case 0x0fb2: /* lss Gv */
4871 case 0x0fb4: /* lfs Gv */
4872 case 0x0fb5: /* lgs Gv */
4873 if (i386_record_modrm (&ir))
4881 opcode = opcode << 8 | ir.modrm;
4886 case 0xc4: /* les Gv */
4887 regnum = X86_RECORD_ES_REGNUM;
4889 case 0xc5: /* lds Gv */
4890 regnum = X86_RECORD_DS_REGNUM;
4892 case 0x0fb2: /* lss Gv */
4893 regnum = X86_RECORD_SS_REGNUM;
4895 case 0x0fb4: /* lfs Gv */
4896 regnum = X86_RECORD_FS_REGNUM;
4898 case 0x0fb5: /* lgs Gv */
4899 regnum = X86_RECORD_GS_REGNUM;
4902 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
4903 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
4904 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4907 case 0xc0: /* shifts */
4913 if ((opcode & 1) == 0)
4916 ir.ot = ir.dflag + OT_WORD;
4917 if (i386_record_modrm (&ir))
4919 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
4921 if (i386_record_lea_modrm (&ir))
4927 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4929 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4931 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4938 if (i386_record_modrm (&ir))
4942 if (record_arch_list_add_reg (ir.regcache, ir.rm))
4947 if (i386_record_lea_modrm (&ir))
4952 case 0xd8: /* Floats. */
4960 if (i386_record_modrm (&ir))
4962 ir.reg |= ((opcode & 7) << 3);
4968 if (i386_record_lea_modrm_addr (&ir, &addr64))
4976 /* For fcom, ficom nothing to do. */
4982 /* For fcomp, ficomp pop FPU stack, store all. */
4983 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5010 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5011 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5012 of code, always affects st(0) register. */
5013 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
5037 /* Handling fld, fild. */
5038 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5042 switch (ir.reg >> 4)
5045 if (record_arch_list_add_mem (addr64, 4))
5049 if (record_arch_list_add_mem (addr64, 8))
5055 if (record_arch_list_add_mem (addr64, 2))
5061 switch (ir.reg >> 4)
5064 if (record_arch_list_add_mem (addr64, 4))
5066 if (3 == (ir.reg & 7))
5068 /* For fstp m32fp. */
5069 if (i386_record_floats (gdbarch, &ir,
5070 I386_SAVE_FPU_REGS))
5075 if (record_arch_list_add_mem (addr64, 4))
5077 if ((3 == (ir.reg & 7))
5078 || (5 == (ir.reg & 7))
5079 || (7 == (ir.reg & 7)))
5081 /* For fstp insn. */
5082 if (i386_record_floats (gdbarch, &ir,
5083 I386_SAVE_FPU_REGS))
5088 if (record_arch_list_add_mem (addr64, 8))
5090 if (3 == (ir.reg & 7))
5092 /* For fstp m64fp. */
5093 if (i386_record_floats (gdbarch, &ir,
5094 I386_SAVE_FPU_REGS))
5099 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
5101 /* For fistp, fbld, fild, fbstp. */
5102 if (i386_record_floats (gdbarch, &ir,
5103 I386_SAVE_FPU_REGS))
5108 if (record_arch_list_add_mem (addr64, 2))
5117 if (i386_record_floats (gdbarch, &ir,
5118 I386_SAVE_FPU_ENV_REG_STACK))
5123 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
5128 if (i386_record_floats (gdbarch, &ir,
5129 I386_SAVE_FPU_ENV_REG_STACK))
5135 if (record_arch_list_add_mem (addr64, 28))
5140 if (record_arch_list_add_mem (addr64, 14))
5146 if (record_arch_list_add_mem (addr64, 2))
5148 /* Insn fstp, fbstp. */
5149 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5154 if (record_arch_list_add_mem (addr64, 10))
5160 if (record_arch_list_add_mem (addr64, 28))
5166 if (record_arch_list_add_mem (addr64, 14))
5170 if (record_arch_list_add_mem (addr64, 80))
5173 if (i386_record_floats (gdbarch, &ir,
5174 I386_SAVE_FPU_ENV_REG_STACK))
5178 if (record_arch_list_add_mem (addr64, 8))
5181 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5186 opcode = opcode << 8 | ir.modrm;
5191 /* Opcode is an extension of modR/M byte. */
5197 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
5201 if (0x0c == (ir.modrm >> 4))
5203 if ((ir.modrm & 0x0f) <= 7)
5205 if (i386_record_floats (gdbarch, &ir,
5206 I386_SAVE_FPU_REGS))
5211 if (i386_record_floats (gdbarch, &ir,
5212 I387_ST0_REGNUM (tdep)))
5214 /* If only st(0) is changing, then we have already
5216 if ((ir.modrm & 0x0f) - 0x08)
5218 if (i386_record_floats (gdbarch, &ir,
5219 I387_ST0_REGNUM (tdep) +
5220 ((ir.modrm & 0x0f) - 0x08)))
5238 if (i386_record_floats (gdbarch, &ir,
5239 I387_ST0_REGNUM (tdep)))
5257 if (i386_record_floats (gdbarch, &ir,
5258 I386_SAVE_FPU_REGS))
5262 if (i386_record_floats (gdbarch, &ir,
5263 I387_ST0_REGNUM (tdep)))
5265 if (i386_record_floats (gdbarch, &ir,
5266 I387_ST0_REGNUM (tdep) + 1))
5273 if (0xe9 == ir.modrm)
5275 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5278 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
5280 if (i386_record_floats (gdbarch, &ir,
5281 I387_ST0_REGNUM (tdep)))
5283 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
5285 if (i386_record_floats (gdbarch, &ir,
5286 I387_ST0_REGNUM (tdep) +
5290 else if ((ir.modrm & 0x0f) - 0x08)
5292 if (i386_record_floats (gdbarch, &ir,
5293 I387_ST0_REGNUM (tdep) +
5294 ((ir.modrm & 0x0f) - 0x08)))
5300 if (0xe3 == ir.modrm)
5302 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
5305 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
5307 if (i386_record_floats (gdbarch, &ir,
5308 I387_ST0_REGNUM (tdep)))
5310 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
5312 if (i386_record_floats (gdbarch, &ir,
5313 I387_ST0_REGNUM (tdep) +
5317 else if ((ir.modrm & 0x0f) - 0x08)
5319 if (i386_record_floats (gdbarch, &ir,
5320 I387_ST0_REGNUM (tdep) +
5321 ((ir.modrm & 0x0f) - 0x08)))
5327 if ((0x0c == ir.modrm >> 4)
5328 || (0x0d == ir.modrm >> 4)
5329 || (0x0f == ir.modrm >> 4))
5331 if ((ir.modrm & 0x0f) <= 7)
5333 if (i386_record_floats (gdbarch, &ir,
5334 I387_ST0_REGNUM (tdep) +
5340 if (i386_record_floats (gdbarch, &ir,
5341 I387_ST0_REGNUM (tdep) +
5342 ((ir.modrm & 0x0f) - 0x08)))
5348 if (0x0c == ir.modrm >> 4)
5350 if (i386_record_floats (gdbarch, &ir,
5351 I387_FTAG_REGNUM (tdep)))
5354 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
5356 if ((ir.modrm & 0x0f) <= 7)
5358 if (i386_record_floats (gdbarch, &ir,
5359 I387_ST0_REGNUM (tdep) +
5365 if (i386_record_floats (gdbarch, &ir,
5366 I386_SAVE_FPU_REGS))
5372 if ((0x0c == ir.modrm >> 4)
5373 || (0x0e == ir.modrm >> 4)
5374 || (0x0f == ir.modrm >> 4)
5375 || (0xd9 == ir.modrm))
5377 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5382 if (0xe0 == ir.modrm)
5384 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
5387 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
5389 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5397 case 0xa4: /* movsS */
5399 case 0xaa: /* stosS */
5401 case 0x6c: /* insS */
5403 regcache_raw_read_unsigned (ir.regcache,
5404 ir.regmap[X86_RECORD_RECX_REGNUM],
5410 if ((opcode & 1) == 0)
5413 ir.ot = ir.dflag + OT_WORD;
5414 regcache_raw_read_unsigned (ir.regcache,
5415 ir.regmap[X86_RECORD_REDI_REGNUM],
5418 regcache_raw_read_unsigned (ir.regcache,
5419 ir.regmap[X86_RECORD_ES_REGNUM],
5421 regcache_raw_read_unsigned (ir.regcache,
5422 ir.regmap[X86_RECORD_DS_REGNUM],
5424 if (ir.aflag && (es != ds))
5426 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5427 if (record_memory_query)
5431 target_terminal_ours ();
5433 Process record ignores the memory change of instruction at address %s\n\
5434 because it can't get the value of the segment register.\n\
5435 Do you want to stop the program?"),
5436 paddress (gdbarch, ir.orig_addr));
5437 target_terminal_inferior ();
5444 if (record_arch_list_add_mem (addr, 1 << ir.ot))
5448 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5449 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5450 if (opcode == 0xa4 || opcode == 0xa5)
5451 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5452 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5453 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5457 case 0xa6: /* cmpsS */
5459 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5460 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5461 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5462 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5463 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5466 case 0xac: /* lodsS */
5468 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5469 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5470 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5471 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5472 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5475 case 0xae: /* scasS */
5477 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5478 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5479 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5480 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5483 case 0x6e: /* outsS */
5485 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5486 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5487 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5488 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5491 case 0xe4: /* port I/O */
5495 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5496 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5506 case 0xc2: /* ret im */
5507 case 0xc3: /* ret */
5508 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5509 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5512 case 0xca: /* lret im */
5513 case 0xcb: /* lret */
5514 case 0xcf: /* iret */
5515 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5516 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5517 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5520 case 0xe8: /* call im */
5521 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5523 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5527 case 0x9a: /* lcall im */
5528 if (ir.regmap[X86_RECORD_R8_REGNUM])
5533 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5534 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5538 case 0xe9: /* jmp im */
5539 case 0xea: /* ljmp im */
5540 case 0xeb: /* jmp Jb */
5541 case 0x70: /* jcc Jb */
5557 case 0x0f80: /* jcc Jv */
5575 case 0x0f90: /* setcc Gv */
5591 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5593 if (i386_record_modrm (&ir))
5596 I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
5600 if (i386_record_lea_modrm (&ir))
5605 case 0x0f40: /* cmov Gv, Ev */
5621 if (i386_record_modrm (&ir))
5624 if (ir.dflag == OT_BYTE)
5626 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
5630 case 0x9c: /* pushf */
5631 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5632 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5634 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5638 case 0x9d: /* popf */
5639 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5640 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5643 case 0x9e: /* sahf */
5644 if (ir.regmap[X86_RECORD_R8_REGNUM])
5650 case 0xf5: /* cmc */
5651 case 0xf8: /* clc */
5652 case 0xf9: /* stc */
5653 case 0xfc: /* cld */
5654 case 0xfd: /* std */
5655 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5658 case 0x9f: /* lahf */
5659 if (ir.regmap[X86_RECORD_R8_REGNUM])
5664 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5665 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5668 /* bit operations */
5669 case 0x0fba: /* bt/bts/btr/btc Gv, im */
5670 ir.ot = ir.dflag + OT_WORD;
5671 if (i386_record_modrm (&ir))
5676 opcode = opcode << 8 | ir.modrm;
5682 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5685 if (i386_record_lea_modrm (&ir))
5689 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5692 case 0x0fa3: /* bt Gv, Ev */
5693 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5696 case 0x0fab: /* bts */
5697 case 0x0fb3: /* btr */
5698 case 0x0fbb: /* btc */
5699 ir.ot = ir.dflag + OT_WORD;
5700 if (i386_record_modrm (&ir))
5703 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5707 if (i386_record_lea_modrm_addr (&ir, &addr64))
5709 regcache_raw_read_unsigned (ir.regcache,
5710 ir.regmap[ir.reg | rex_r],
5715 addr64 += ((int16_t) addr >> 4) << 4;
5718 addr64 += ((int32_t) addr >> 5) << 5;
5721 addr64 += ((int64_t) addr >> 6) << 6;
5724 if (record_arch_list_add_mem (addr64, 1 << ir.ot))
5726 if (i386_record_lea_modrm (&ir))
5729 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5732 case 0x0fbc: /* bsf */
5733 case 0x0fbd: /* bsr */
5734 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5735 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5739 case 0x27: /* daa */
5740 case 0x2f: /* das */
5741 case 0x37: /* aaa */
5742 case 0x3f: /* aas */
5743 case 0xd4: /* aam */
5744 case 0xd5: /* aad */
5745 if (ir.regmap[X86_RECORD_R8_REGNUM])
5750 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5751 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5755 case 0x90: /* nop */
5756 if (prefixes & PREFIX_LOCK)
5763 case 0x9b: /* fwait */
5764 if (target_read_memory (ir.addr, &opcode8, 1))
5767 printf_unfiltered (_("Process record: error reading memory at "
5768 "addr 0x%s len = 1.\n"),
5769 paddress (gdbarch, ir.addr));
5772 opcode = (uint32_t) opcode8;
5778 case 0xcc: /* int3 */
5779 printf_unfiltered (_("Process record does not support instruction "
5786 case 0xcd: /* int */
5790 if (target_read_memory (ir.addr, &interrupt, 1))
5793 printf_unfiltered (_("Process record: error reading memory "
5794 "at addr %s len = 1.\n"),
5795 paddress (gdbarch, ir.addr));
5799 if (interrupt != 0x80
5800 || tdep->i386_intx80_record == NULL)
5802 printf_unfiltered (_("Process record does not support "
5803 "instruction int 0x%02x.\n"),
5808 ret = tdep->i386_intx80_record (ir.regcache);
5815 case 0xce: /* into */
5816 printf_unfiltered (_("Process record does not support "
5817 "instruction into.\n"));
5822 case 0xfa: /* cli */
5823 case 0xfb: /* sti */
5826 case 0x62: /* bound */
5827 printf_unfiltered (_("Process record does not support "
5828 "instruction bound.\n"));
5833 case 0x0fc8: /* bswap reg */
5841 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
5844 case 0xd6: /* salc */
5845 if (ir.regmap[X86_RECORD_R8_REGNUM])
5850 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5851 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5854 case 0xe0: /* loopnz */
5855 case 0xe1: /* loopz */
5856 case 0xe2: /* loop */
5857 case 0xe3: /* jecxz */
5858 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5859 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5862 case 0x0f30: /* wrmsr */
5863 printf_unfiltered (_("Process record does not support "
5864 "instruction wrmsr.\n"));
5869 case 0x0f32: /* rdmsr */
5870 printf_unfiltered (_("Process record does not support "
5871 "instruction rdmsr.\n"));
5876 case 0x0f31: /* rdtsc */
5877 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5878 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5881 case 0x0f34: /* sysenter */
5884 if (ir.regmap[X86_RECORD_R8_REGNUM])
5889 if (tdep->i386_sysenter_record == NULL)
5891 printf_unfiltered (_("Process record does not support "
5892 "instruction sysenter.\n"));
5896 ret = tdep->i386_sysenter_record (ir.regcache);
5902 case 0x0f35: /* sysexit */
5903 printf_unfiltered (_("Process record does not support "
5904 "instruction sysexit.\n"));
5909 case 0x0f05: /* syscall */
5912 if (tdep->i386_syscall_record == NULL)
5914 printf_unfiltered (_("Process record does not support "
5915 "instruction syscall.\n"));
5919 ret = tdep->i386_syscall_record (ir.regcache);
5925 case 0x0f07: /* sysret */
5926 printf_unfiltered (_("Process record does not support "
5927 "instruction sysret.\n"));
5932 case 0x0fa2: /* cpuid */
5933 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5934 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5935 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5936 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
5939 case 0xf4: /* hlt */
5940 printf_unfiltered (_("Process record does not support "
5941 "instruction hlt.\n"));
5947 if (i386_record_modrm (&ir))
5954 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5958 if (i386_record_lea_modrm (&ir))
5967 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5971 opcode = opcode << 8 | ir.modrm;
5978 if (i386_record_modrm (&ir))
5989 opcode = opcode << 8 | ir.modrm;
5992 if (ir.override >= 0)
5994 if (record_memory_query)
5998 target_terminal_ours ();
6000 Process record ignores the memory change of instruction at address %s\n\
6001 because it can't get the value of the segment register.\n\
6002 Do you want to stop the program?"),
6003 paddress (gdbarch, ir.orig_addr));
6004 target_terminal_inferior ();
6011 if (i386_record_lea_modrm_addr (&ir, &addr64))
6013 if (record_arch_list_add_mem (addr64, 2))
6016 if (ir.regmap[X86_RECORD_R8_REGNUM])
6018 if (record_arch_list_add_mem (addr64, 8))
6023 if (record_arch_list_add_mem (addr64, 4))
6034 case 0: /* monitor */
6037 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6041 opcode = opcode << 8 | ir.modrm;
6049 if (ir.override >= 0)
6051 if (record_memory_query)
6055 target_terminal_ours ();
6057 Process record ignores the memory change of instruction at address %s\n\
6058 because it can't get the value of the segment register.\n\
6059 Do you want to stop the program?"),
6060 paddress (gdbarch, ir.orig_addr));
6061 target_terminal_inferior ();
6070 if (i386_record_lea_modrm_addr (&ir, &addr64))
6072 if (record_arch_list_add_mem (addr64, 2))
6075 if (ir.regmap[X86_RECORD_R8_REGNUM])
6077 if (record_arch_list_add_mem (addr64, 8))
6082 if (record_arch_list_add_mem (addr64, 4))
6094 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6095 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6099 else if (ir.rm == 1)
6106 opcode = opcode << 8 | ir.modrm;
6113 if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
6119 if (i386_record_lea_modrm (&ir))
6122 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6125 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6127 case 7: /* invlpg */
6130 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
6131 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
6135 opcode = opcode << 8 | ir.modrm;
6140 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6144 opcode = opcode << 8 | ir.modrm;
6150 case 0x0f08: /* invd */
6151 case 0x0f09: /* wbinvd */
6154 case 0x63: /* arpl */
6155 if (i386_record_modrm (&ir))
6157 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
6159 I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
6160 ? (ir.reg | rex_r) : ir.rm);
6164 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
6165 if (i386_record_lea_modrm (&ir))
6168 if (!ir.regmap[X86_RECORD_R8_REGNUM])
6169 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6172 case 0x0f02: /* lar */
6173 case 0x0f03: /* lsl */
6174 if (i386_record_modrm (&ir))
6176 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6177 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6181 if (i386_record_modrm (&ir))
6183 if (ir.mod == 3 && ir.reg == 3)
6186 opcode = opcode << 8 | ir.modrm;
6198 /* nop (multi byte) */
6201 case 0x0f20: /* mov reg, crN */
6202 case 0x0f22: /* mov crN, reg */
6203 if (i386_record_modrm (&ir))
6205 if ((ir.modrm & 0xc0) != 0xc0)
6208 opcode = opcode << 8 | ir.modrm;
6219 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6221 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6225 opcode = opcode << 8 | ir.modrm;
6231 case 0x0f21: /* mov reg, drN */
6232 case 0x0f23: /* mov drN, reg */
6233 if (i386_record_modrm (&ir))
6235 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
6236 || ir.reg == 5 || ir.reg >= 8)
6239 opcode = opcode << 8 | ir.modrm;
6243 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6245 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6248 case 0x0f06: /* clts */
6249 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6252 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
6254 case 0x0f0d: /* 3DNow! prefetch */
6257 case 0x0f0e: /* 3DNow! femms */
6258 case 0x0f77: /* emms */
6259 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
6261 record_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
6264 case 0x0f0f: /* 3DNow! data */
6265 if (i386_record_modrm (&ir))
6267 if (target_read_memory (ir.addr, &opcode8, 1))
6269 printf_unfiltered (_("Process record: error reading memory at "
6270 "addr %s len = 1.\n"),
6271 paddress (gdbarch, ir.addr));
6277 case 0x0c: /* 3DNow! pi2fw */
6278 case 0x0d: /* 3DNow! pi2fd */
6279 case 0x1c: /* 3DNow! pf2iw */
6280 case 0x1d: /* 3DNow! pf2id */
6281 case 0x8a: /* 3DNow! pfnacc */
6282 case 0x8e: /* 3DNow! pfpnacc */
6283 case 0x90: /* 3DNow! pfcmpge */
6284 case 0x94: /* 3DNow! pfmin */
6285 case 0x96: /* 3DNow! pfrcp */
6286 case 0x97: /* 3DNow! pfrsqrt */
6287 case 0x9a: /* 3DNow! pfsub */
6288 case 0x9e: /* 3DNow! pfadd */
6289 case 0xa0: /* 3DNow! pfcmpgt */
6290 case 0xa4: /* 3DNow! pfmax */
6291 case 0xa6: /* 3DNow! pfrcpit1 */
6292 case 0xa7: /* 3DNow! pfrsqit1 */
6293 case 0xaa: /* 3DNow! pfsubr */
6294 case 0xae: /* 3DNow! pfacc */
6295 case 0xb0: /* 3DNow! pfcmpeq */
6296 case 0xb4: /* 3DNow! pfmul */
6297 case 0xb6: /* 3DNow! pfrcpit2 */
6298 case 0xb7: /* 3DNow! pmulhrw */
6299 case 0xbb: /* 3DNow! pswapd */
6300 case 0xbf: /* 3DNow! pavgusb */
6301 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
6302 goto no_support_3dnow_data;
6303 record_arch_list_add_reg (ir.regcache, ir.reg);
6307 no_support_3dnow_data:
6308 opcode = (opcode << 8) | opcode8;
6314 case 0x0faa: /* rsm */
6315 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6316 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6317 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6318 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6319 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
6320 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6321 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
6322 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6323 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6327 if (i386_record_modrm (&ir))
6331 case 0: /* fxsave */
6335 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6336 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
6338 if (record_arch_list_add_mem (tmpu64, 512))
6343 case 1: /* fxrstor */
6347 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6349 for (i = I387_MM0_REGNUM (tdep);
6350 i386_mmx_regnum_p (gdbarch, i); i++)
6351 record_arch_list_add_reg (ir.regcache, i);
6353 for (i = I387_XMM0_REGNUM (tdep);
6354 i386_xmm_regnum_p (gdbarch, i); i++)
6355 record_arch_list_add_reg (ir.regcache, i);
6357 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
6358 record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
6360 for (i = I387_ST0_REGNUM (tdep);
6361 i386_fp_regnum_p (gdbarch, i); i++)
6362 record_arch_list_add_reg (ir.regcache, i);
6364 for (i = I387_FCTRL_REGNUM (tdep);
6365 i386_fpc_regnum_p (gdbarch, i); i++)
6366 record_arch_list_add_reg (ir.regcache, i);
6370 case 2: /* ldmxcsr */
6371 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
6373 record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
6376 case 3: /* stmxcsr */
6378 if (i386_record_lea_modrm (&ir))
6382 case 5: /* lfence */
6383 case 6: /* mfence */
6384 case 7: /* sfence clflush */
6388 opcode = (opcode << 8) | ir.modrm;
6394 case 0x0fc3: /* movnti */
6395 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
6396 if (i386_record_modrm (&ir))
6401 if (i386_record_lea_modrm (&ir))
6405 /* Add prefix to opcode. */
6532 reswitch_prefix_add:
6540 if (target_read_memory (ir.addr, &opcode8, 1))
6542 printf_unfiltered (_("Process record: error reading memory at "
6543 "addr %s len = 1.\n"),
6544 paddress (gdbarch, ir.addr));
6548 opcode = (uint32_t) opcode8 | opcode << 8;
6549 goto reswitch_prefix_add;
6552 case 0x0f10: /* movups */
6553 case 0x660f10: /* movupd */
6554 case 0xf30f10: /* movss */
6555 case 0xf20f10: /* movsd */
6556 case 0x0f12: /* movlps */
6557 case 0x660f12: /* movlpd */
6558 case 0xf30f12: /* movsldup */
6559 case 0xf20f12: /* movddup */
6560 case 0x0f14: /* unpcklps */
6561 case 0x660f14: /* unpcklpd */
6562 case 0x0f15: /* unpckhps */
6563 case 0x660f15: /* unpckhpd */
6564 case 0x0f16: /* movhps */
6565 case 0x660f16: /* movhpd */
6566 case 0xf30f16: /* movshdup */
6567 case 0x0f28: /* movaps */
6568 case 0x660f28: /* movapd */
6569 case 0x0f2a: /* cvtpi2ps */
6570 case 0x660f2a: /* cvtpi2pd */
6571 case 0xf30f2a: /* cvtsi2ss */
6572 case 0xf20f2a: /* cvtsi2sd */
6573 case 0x0f2c: /* cvttps2pi */
6574 case 0x660f2c: /* cvttpd2pi */
6575 case 0x0f2d: /* cvtps2pi */
6576 case 0x660f2d: /* cvtpd2pi */
6577 case 0x660f3800: /* pshufb */
6578 case 0x660f3801: /* phaddw */
6579 case 0x660f3802: /* phaddd */
6580 case 0x660f3803: /* phaddsw */
6581 case 0x660f3804: /* pmaddubsw */
6582 case 0x660f3805: /* phsubw */
6583 case 0x660f3806: /* phsubd */
6584 case 0x660f3807: /* phsubsw */
6585 case 0x660f3808: /* psignb */
6586 case 0x660f3809: /* psignw */
6587 case 0x660f380a: /* psignd */
6588 case 0x660f380b: /* pmulhrsw */
6589 case 0x660f3810: /* pblendvb */
6590 case 0x660f3814: /* blendvps */
6591 case 0x660f3815: /* blendvpd */
6592 case 0x660f381c: /* pabsb */
6593 case 0x660f381d: /* pabsw */
6594 case 0x660f381e: /* pabsd */
6595 case 0x660f3820: /* pmovsxbw */
6596 case 0x660f3821: /* pmovsxbd */
6597 case 0x660f3822: /* pmovsxbq */
6598 case 0x660f3823: /* pmovsxwd */
6599 case 0x660f3824: /* pmovsxwq */
6600 case 0x660f3825: /* pmovsxdq */
6601 case 0x660f3828: /* pmuldq */
6602 case 0x660f3829: /* pcmpeqq */
6603 case 0x660f382a: /* movntdqa */
6604 case 0x660f3a08: /* roundps */
6605 case 0x660f3a09: /* roundpd */
6606 case 0x660f3a0a: /* roundss */
6607 case 0x660f3a0b: /* roundsd */
6608 case 0x660f3a0c: /* blendps */
6609 case 0x660f3a0d: /* blendpd */
6610 case 0x660f3a0e: /* pblendw */
6611 case 0x660f3a0f: /* palignr */
6612 case 0x660f3a20: /* pinsrb */
6613 case 0x660f3a21: /* insertps */
6614 case 0x660f3a22: /* pinsrd pinsrq */
6615 case 0x660f3a40: /* dpps */
6616 case 0x660f3a41: /* dppd */
6617 case 0x660f3a42: /* mpsadbw */
6618 case 0x660f3a60: /* pcmpestrm */
6619 case 0x660f3a61: /* pcmpestri */
6620 case 0x660f3a62: /* pcmpistrm */
6621 case 0x660f3a63: /* pcmpistri */
6622 case 0x0f51: /* sqrtps */
6623 case 0x660f51: /* sqrtpd */
6624 case 0xf20f51: /* sqrtsd */
6625 case 0xf30f51: /* sqrtss */
6626 case 0x0f52: /* rsqrtps */
6627 case 0xf30f52: /* rsqrtss */
6628 case 0x0f53: /* rcpps */
6629 case 0xf30f53: /* rcpss */
6630 case 0x0f54: /* andps */
6631 case 0x660f54: /* andpd */
6632 case 0x0f55: /* andnps */
6633 case 0x660f55: /* andnpd */
6634 case 0x0f56: /* orps */
6635 case 0x660f56: /* orpd */
6636 case 0x0f57: /* xorps */
6637 case 0x660f57: /* xorpd */
6638 case 0x0f58: /* addps */
6639 case 0x660f58: /* addpd */
6640 case 0xf20f58: /* addsd */
6641 case 0xf30f58: /* addss */
6642 case 0x0f59: /* mulps */
6643 case 0x660f59: /* mulpd */
6644 case 0xf20f59: /* mulsd */
6645 case 0xf30f59: /* mulss */
6646 case 0x0f5a: /* cvtps2pd */
6647 case 0x660f5a: /* cvtpd2ps */
6648 case 0xf20f5a: /* cvtsd2ss */
6649 case 0xf30f5a: /* cvtss2sd */
6650 case 0x0f5b: /* cvtdq2ps */
6651 case 0x660f5b: /* cvtps2dq */
6652 case 0xf30f5b: /* cvttps2dq */
6653 case 0x0f5c: /* subps */
6654 case 0x660f5c: /* subpd */
6655 case 0xf20f5c: /* subsd */
6656 case 0xf30f5c: /* subss */
6657 case 0x0f5d: /* minps */
6658 case 0x660f5d: /* minpd */
6659 case 0xf20f5d: /* minsd */
6660 case 0xf30f5d: /* minss */
6661 case 0x0f5e: /* divps */
6662 case 0x660f5e: /* divpd */
6663 case 0xf20f5e: /* divsd */
6664 case 0xf30f5e: /* divss */
6665 case 0x0f5f: /* maxps */
6666 case 0x660f5f: /* maxpd */
6667 case 0xf20f5f: /* maxsd */
6668 case 0xf30f5f: /* maxss */
6669 case 0x660f60: /* punpcklbw */
6670 case 0x660f61: /* punpcklwd */
6671 case 0x660f62: /* punpckldq */
6672 case 0x660f63: /* packsswb */
6673 case 0x660f64: /* pcmpgtb */
6674 case 0x660f65: /* pcmpgtw */
6675 case 0x660f66: /* pcmpgtd */
6676 case 0x660f67: /* packuswb */
6677 case 0x660f68: /* punpckhbw */
6678 case 0x660f69: /* punpckhwd */
6679 case 0x660f6a: /* punpckhdq */
6680 case 0x660f6b: /* packssdw */
6681 case 0x660f6c: /* punpcklqdq */
6682 case 0x660f6d: /* punpckhqdq */
6683 case 0x660f6e: /* movd */
6684 case 0x660f6f: /* movdqa */
6685 case 0xf30f6f: /* movdqu */
6686 case 0x660f70: /* pshufd */
6687 case 0xf20f70: /* pshuflw */
6688 case 0xf30f70: /* pshufhw */
6689 case 0x660f74: /* pcmpeqb */
6690 case 0x660f75: /* pcmpeqw */
6691 case 0x660f76: /* pcmpeqd */
6692 case 0x660f7c: /* haddpd */
6693 case 0xf20f7c: /* haddps */
6694 case 0x660f7d: /* hsubpd */
6695 case 0xf20f7d: /* hsubps */
6696 case 0xf30f7e: /* movq */
6697 case 0x0fc2: /* cmpps */
6698 case 0x660fc2: /* cmppd */
6699 case 0xf20fc2: /* cmpsd */
6700 case 0xf30fc2: /* cmpss */
6701 case 0x660fc4: /* pinsrw */
6702 case 0x0fc6: /* shufps */
6703 case 0x660fc6: /* shufpd */
6704 case 0x660fd0: /* addsubpd */
6705 case 0xf20fd0: /* addsubps */
6706 case 0x660fd1: /* psrlw */
6707 case 0x660fd2: /* psrld */
6708 case 0x660fd3: /* psrlq */
6709 case 0x660fd4: /* paddq */
6710 case 0x660fd5: /* pmullw */
6711 case 0xf30fd6: /* movq2dq */
6712 case 0x660fd8: /* psubusb */
6713 case 0x660fd9: /* psubusw */
6714 case 0x660fda: /* pminub */
6715 case 0x660fdb: /* pand */
6716 case 0x660fdc: /* paddusb */
6717 case 0x660fdd: /* paddusw */
6718 case 0x660fde: /* pmaxub */
6719 case 0x660fdf: /* pandn */
6720 case 0x660fe0: /* pavgb */
6721 case 0x660fe1: /* psraw */
6722 case 0x660fe2: /* psrad */
6723 case 0x660fe3: /* pavgw */
6724 case 0x660fe4: /* pmulhuw */
6725 case 0x660fe5: /* pmulhw */
6726 case 0x660fe6: /* cvttpd2dq */
6727 case 0xf20fe6: /* cvtpd2dq */
6728 case 0xf30fe6: /* cvtdq2pd */
6729 case 0x660fe8: /* psubsb */
6730 case 0x660fe9: /* psubsw */
6731 case 0x660fea: /* pminsw */
6732 case 0x660feb: /* por */
6733 case 0x660fec: /* paddsb */
6734 case 0x660fed: /* paddsw */
6735 case 0x660fee: /* pmaxsw */
6736 case 0x660fef: /* pxor */
6737 case 0xf20ff0: /* lddqu */
6738 case 0x660ff1: /* psllw */
6739 case 0x660ff2: /* pslld */
6740 case 0x660ff3: /* psllq */
6741 case 0x660ff4: /* pmuludq */
6742 case 0x660ff5: /* pmaddwd */
6743 case 0x660ff6: /* psadbw */
6744 case 0x660ff8: /* psubb */
6745 case 0x660ff9: /* psubw */
6746 case 0x660ffa: /* psubd */
6747 case 0x660ffb: /* psubq */
6748 case 0x660ffc: /* paddb */
6749 case 0x660ffd: /* paddw */
6750 case 0x660ffe: /* paddd */
6751 if (i386_record_modrm (&ir))
6754 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
6756 record_arch_list_add_reg (ir.regcache,
6757 I387_XMM0_REGNUM (tdep) + ir.reg);
6758 if ((opcode & 0xfffffffc) == 0x660f3a60)
6759 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6762 case 0x0f11: /* movups */
6763 case 0x660f11: /* movupd */
6764 case 0xf30f11: /* movss */
6765 case 0xf20f11: /* movsd */
6766 case 0x0f13: /* movlps */
6767 case 0x660f13: /* movlpd */
6768 case 0x0f17: /* movhps */
6769 case 0x660f17: /* movhpd */
6770 case 0x0f29: /* movaps */
6771 case 0x660f29: /* movapd */
6772 case 0x660f3a14: /* pextrb */
6773 case 0x660f3a15: /* pextrw */
6774 case 0x660f3a16: /* pextrd pextrq */
6775 case 0x660f3a17: /* extractps */
6776 case 0x660f7f: /* movdqa */
6777 case 0xf30f7f: /* movdqu */
6778 if (i386_record_modrm (&ir))
6782 if (opcode == 0x0f13 || opcode == 0x660f13
6783 || opcode == 0x0f17 || opcode == 0x660f17)
6786 if (!i386_xmm_regnum_p (gdbarch,
6787 I387_XMM0_REGNUM (tdep) + ir.rm))
6789 record_arch_list_add_reg (ir.regcache,
6790 I387_XMM0_REGNUM (tdep) + ir.rm);
6812 if (i386_record_lea_modrm (&ir))
6817 case 0x0f2b: /* movntps */
6818 case 0x660f2b: /* movntpd */
6819 case 0x0fe7: /* movntq */
6820 case 0x660fe7: /* movntdq */
6823 if (opcode == 0x0fe7)
6827 if (i386_record_lea_modrm (&ir))
6831 case 0xf30f2c: /* cvttss2si */
6832 case 0xf20f2c: /* cvttsd2si */
6833 case 0xf30f2d: /* cvtss2si */
6834 case 0xf20f2d: /* cvtsd2si */
6835 case 0xf20f38f0: /* crc32 */
6836 case 0xf20f38f1: /* crc32 */
6837 case 0x0f50: /* movmskps */
6838 case 0x660f50: /* movmskpd */
6839 case 0x0fc5: /* pextrw */
6840 case 0x660fc5: /* pextrw */
6841 case 0x0fd7: /* pmovmskb */
6842 case 0x660fd7: /* pmovmskb */
6843 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6846 case 0x0f3800: /* pshufb */
6847 case 0x0f3801: /* phaddw */
6848 case 0x0f3802: /* phaddd */
6849 case 0x0f3803: /* phaddsw */
6850 case 0x0f3804: /* pmaddubsw */
6851 case 0x0f3805: /* phsubw */
6852 case 0x0f3806: /* phsubd */
6853 case 0x0f3807: /* phsubsw */
6854 case 0x0f3808: /* psignb */
6855 case 0x0f3809: /* psignw */
6856 case 0x0f380a: /* psignd */
6857 case 0x0f380b: /* pmulhrsw */
6858 case 0x0f381c: /* pabsb */
6859 case 0x0f381d: /* pabsw */
6860 case 0x0f381e: /* pabsd */
6861 case 0x0f382b: /* packusdw */
6862 case 0x0f3830: /* pmovzxbw */
6863 case 0x0f3831: /* pmovzxbd */
6864 case 0x0f3832: /* pmovzxbq */
6865 case 0x0f3833: /* pmovzxwd */
6866 case 0x0f3834: /* pmovzxwq */
6867 case 0x0f3835: /* pmovzxdq */
6868 case 0x0f3837: /* pcmpgtq */
6869 case 0x0f3838: /* pminsb */
6870 case 0x0f3839: /* pminsd */
6871 case 0x0f383a: /* pminuw */
6872 case 0x0f383b: /* pminud */
6873 case 0x0f383c: /* pmaxsb */
6874 case 0x0f383d: /* pmaxsd */
6875 case 0x0f383e: /* pmaxuw */
6876 case 0x0f383f: /* pmaxud */
6877 case 0x0f3840: /* pmulld */
6878 case 0x0f3841: /* phminposuw */
6879 case 0x0f3a0f: /* palignr */
6880 case 0x0f60: /* punpcklbw */
6881 case 0x0f61: /* punpcklwd */
6882 case 0x0f62: /* punpckldq */
6883 case 0x0f63: /* packsswb */
6884 case 0x0f64: /* pcmpgtb */
6885 case 0x0f65: /* pcmpgtw */
6886 case 0x0f66: /* pcmpgtd */
6887 case 0x0f67: /* packuswb */
6888 case 0x0f68: /* punpckhbw */
6889 case 0x0f69: /* punpckhwd */
6890 case 0x0f6a: /* punpckhdq */
6891 case 0x0f6b: /* packssdw */
6892 case 0x0f6e: /* movd */
6893 case 0x0f6f: /* movq */
6894 case 0x0f70: /* pshufw */
6895 case 0x0f74: /* pcmpeqb */
6896 case 0x0f75: /* pcmpeqw */
6897 case 0x0f76: /* pcmpeqd */
6898 case 0x0fc4: /* pinsrw */
6899 case 0x0fd1: /* psrlw */
6900 case 0x0fd2: /* psrld */
6901 case 0x0fd3: /* psrlq */
6902 case 0x0fd4: /* paddq */
6903 case 0x0fd5: /* pmullw */
6904 case 0xf20fd6: /* movdq2q */
6905 case 0x0fd8: /* psubusb */
6906 case 0x0fd9: /* psubusw */
6907 case 0x0fda: /* pminub */
6908 case 0x0fdb: /* pand */
6909 case 0x0fdc: /* paddusb */
6910 case 0x0fdd: /* paddusw */
6911 case 0x0fde: /* pmaxub */
6912 case 0x0fdf: /* pandn */
6913 case 0x0fe0: /* pavgb */
6914 case 0x0fe1: /* psraw */
6915 case 0x0fe2: /* psrad */
6916 case 0x0fe3: /* pavgw */
6917 case 0x0fe4: /* pmulhuw */
6918 case 0x0fe5: /* pmulhw */
6919 case 0x0fe8: /* psubsb */
6920 case 0x0fe9: /* psubsw */
6921 case 0x0fea: /* pminsw */
6922 case 0x0feb: /* por */
6923 case 0x0fec: /* paddsb */
6924 case 0x0fed: /* paddsw */
6925 case 0x0fee: /* pmaxsw */
6926 case 0x0fef: /* pxor */
6927 case 0x0ff1: /* psllw */
6928 case 0x0ff2: /* pslld */
6929 case 0x0ff3: /* psllq */
6930 case 0x0ff4: /* pmuludq */
6931 case 0x0ff5: /* pmaddwd */
6932 case 0x0ff6: /* psadbw */
6933 case 0x0ff8: /* psubb */
6934 case 0x0ff9: /* psubw */
6935 case 0x0ffa: /* psubd */
6936 case 0x0ffb: /* psubq */
6937 case 0x0ffc: /* paddb */
6938 case 0x0ffd: /* paddw */
6939 case 0x0ffe: /* paddd */
6940 if (i386_record_modrm (&ir))
6942 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
6944 record_arch_list_add_reg (ir.regcache,
6945 I387_MM0_REGNUM (tdep) + ir.reg);
6948 case 0x0f71: /* psllw */
6949 case 0x0f72: /* pslld */
6950 case 0x0f73: /* psllq */
6951 if (i386_record_modrm (&ir))
6953 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
6955 record_arch_list_add_reg (ir.regcache,
6956 I387_MM0_REGNUM (tdep) + ir.rm);
6959 case 0x660f71: /* psllw */
6960 case 0x660f72: /* pslld */
6961 case 0x660f73: /* psllq */
6962 if (i386_record_modrm (&ir))
6965 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
6967 record_arch_list_add_reg (ir.regcache,
6968 I387_XMM0_REGNUM (tdep) + ir.rm);
6971 case 0x0f7e: /* movd */
6972 case 0x660f7e: /* movd */
6973 if (i386_record_modrm (&ir))
6976 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6983 if (i386_record_lea_modrm (&ir))
6988 case 0x0f7f: /* movq */
6989 if (i386_record_modrm (&ir))
6993 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
6995 record_arch_list_add_reg (ir.regcache,
6996 I387_MM0_REGNUM (tdep) + ir.rm);
7001 if (i386_record_lea_modrm (&ir))
7006 case 0xf30fb8: /* popcnt */
7007 if (i386_record_modrm (&ir))
7009 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
7010 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7013 case 0x660fd6: /* movq */
7014 if (i386_record_modrm (&ir))
7019 if (!i386_xmm_regnum_p (gdbarch,
7020 I387_XMM0_REGNUM (tdep) + ir.rm))
7022 record_arch_list_add_reg (ir.regcache,
7023 I387_XMM0_REGNUM (tdep) + ir.rm);
7028 if (i386_record_lea_modrm (&ir))
7033 case 0x660f3817: /* ptest */
7034 case 0x0f2e: /* ucomiss */
7035 case 0x660f2e: /* ucomisd */
7036 case 0x0f2f: /* comiss */
7037 case 0x660f2f: /* comisd */
7038 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7041 case 0x0ff7: /* maskmovq */
7042 regcache_raw_read_unsigned (ir.regcache,
7043 ir.regmap[X86_RECORD_REDI_REGNUM],
7045 if (record_arch_list_add_mem (addr, 64))
7049 case 0x660ff7: /* maskmovdqu */
7050 regcache_raw_read_unsigned (ir.regcache,
7051 ir.regmap[X86_RECORD_REDI_REGNUM],
7053 if (record_arch_list_add_mem (addr, 128))
7068 /* In the future, maybe still need to deal with need_dasm. */
7069 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
7070 if (record_arch_list_add_end ())
7076 printf_unfiltered (_("Process record does not support instruction 0x%02x "
7077 "at address %s.\n"),
7078 (unsigned int) (opcode),
7079 paddress (gdbarch, ir.orig_addr));
7083 static const int i386_record_regmap[] =
7085 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
7086 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
7087 0, 0, 0, 0, 0, 0, 0, 0,
7088 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
7089 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
7092 /* Check that the given address appears suitable for a fast
7093 tracepoint, which on x86 means that we need an instruction of at
7094 least 5 bytes, so that we can overwrite it with a 4-byte-offset
7095 jump and not have to worry about program jumps to an address in the
7096 middle of the tracepoint jump. Returns 1 if OK, and writes a size
7097 of instruction to replace, and 0 if not, plus an explanatory
7101 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch,
7102 CORE_ADDR addr, int *isize, char **msg)
7105 static struct ui_file *gdb_null = NULL;
7107 /* This is based on the target agent using a 4-byte relative jump.
7108 Alternate future possibilities include 8-byte offset for x86-84,
7109 or 3-byte jumps if the program has trampoline space close by. */
7112 /* Dummy file descriptor for the disassembler. */
7114 gdb_null = ui_file_new ();
7116 /* Check for fit. */
7117 len = gdb_print_insn (gdbarch, addr, gdb_null, NULL);
7120 /* Return a bit of target-specific detail to add to the caller's
7121 generic failure message. */
7123 *msg = xstrprintf (_("; instruction is only %d bytes long, "
7124 "need at least %d bytes for the jump"),
7137 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
7138 struct tdesc_arch_data *tdesc_data)
7140 const struct target_desc *tdesc = tdep->tdesc;
7141 const struct tdesc_feature *feature_core;
7142 const struct tdesc_feature *feature_sse, *feature_avx;
7143 int i, num_regs, valid_p;
7145 if (! tdesc_has_registers (tdesc))
7148 /* Get core registers. */
7149 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
7150 if (feature_core == NULL)
7153 /* Get SSE registers. */
7154 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
7156 /* Try AVX registers. */
7157 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
7161 /* The XCR0 bits. */
7164 /* AVX register description requires SSE register description. */
7168 tdep->xcr0 = I386_XSTATE_AVX_MASK;
7170 /* It may have been set by OSABI initialization function. */
7171 if (tdep->num_ymm_regs == 0)
7173 tdep->ymmh_register_names = i386_ymmh_names;
7174 tdep->num_ymm_regs = 8;
7175 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
7178 for (i = 0; i < tdep->num_ymm_regs; i++)
7179 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
7180 tdep->ymm0h_regnum + i,
7181 tdep->ymmh_register_names[i]);
7183 else if (feature_sse)
7184 tdep->xcr0 = I386_XSTATE_SSE_MASK;
7187 tdep->xcr0 = I386_XSTATE_X87_MASK;
7188 tdep->num_xmm_regs = 0;
7191 num_regs = tdep->num_core_regs;
7192 for (i = 0; i < num_regs; i++)
7193 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
7194 tdep->register_names[i]);
7198 /* Need to include %mxcsr, so add one. */
7199 num_regs += tdep->num_xmm_regs + 1;
7200 for (; i < num_regs; i++)
7201 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
7202 tdep->register_names[i]);
7209 static struct gdbarch *
7210 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
7212 struct gdbarch_tdep *tdep;
7213 struct gdbarch *gdbarch;
7214 struct tdesc_arch_data *tdesc_data;
7215 const struct target_desc *tdesc;
7219 /* If there is already a candidate, use it. */
7220 arches = gdbarch_list_lookup_by_info (arches, &info);
7222 return arches->gdbarch;
7224 /* Allocate space for the new architecture. */
7225 tdep = XCALLOC (1, struct gdbarch_tdep);
7226 gdbarch = gdbarch_alloc (&info, tdep);
7228 /* General-purpose registers. */
7229 tdep->gregset = NULL;
7230 tdep->gregset_reg_offset = NULL;
7231 tdep->gregset_num_regs = I386_NUM_GREGS;
7232 tdep->sizeof_gregset = 0;
7234 /* Floating-point registers. */
7235 tdep->fpregset = NULL;
7236 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
7238 tdep->xstateregset = NULL;
7240 /* The default settings include the FPU registers, the MMX registers
7241 and the SSE registers. This can be overridden for a specific ABI
7242 by adjusting the members `st0_regnum', `mm0_regnum' and
7243 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
7244 will show up in the output of "info all-registers". */
7246 tdep->st0_regnum = I386_ST0_REGNUM;
7248 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
7249 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
7251 tdep->jb_pc_offset = -1;
7252 tdep->struct_return = pcc_struct_return;
7253 tdep->sigtramp_start = 0;
7254 tdep->sigtramp_end = 0;
7255 tdep->sigtramp_p = i386_sigtramp_p;
7256 tdep->sigcontext_addr = NULL;
7257 tdep->sc_reg_offset = NULL;
7258 tdep->sc_pc_offset = -1;
7259 tdep->sc_sp_offset = -1;
7261 tdep->xsave_xcr0_offset = -1;
7263 tdep->record_regmap = i386_record_regmap;
7265 /* The format used for `long double' on almost all i386 targets is
7266 the i387 extended floating-point format. In fact, of all targets
7267 in the GCC 2.95 tree, only OSF/1 does it different, and insists
7268 on having a `long double' that's not `long' at all. */
7269 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
7271 /* Although the i387 extended floating-point has only 80 significant
7272 bits, a `long double' actually takes up 96, probably to enforce
7274 set_gdbarch_long_double_bit (gdbarch, 96);
7276 /* Register numbers of various important registers. */
7277 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
7278 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
7279 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
7280 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
7282 /* NOTE: kettenis/20040418: GCC does have two possible register
7283 numbering schemes on the i386: dbx and SVR4. These schemes
7284 differ in how they number %ebp, %esp, %eflags, and the
7285 floating-point registers, and are implemented by the arrays
7286 dbx_register_map[] and svr4_dbx_register_map in
7287 gcc/config/i386.c. GCC also defines a third numbering scheme in
7288 gcc/config/i386.c, which it designates as the "default" register
7289 map used in 64bit mode. This last register numbering scheme is
7290 implemented in dbx64_register_map, and is used for AMD64; see
7293 Currently, each GCC i386 target always uses the same register
7294 numbering scheme across all its supported debugging formats
7295 i.e. SDB (COFF), stabs and DWARF 2. This is because
7296 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7297 DBX_REGISTER_NUMBER macro which is defined by each target's
7298 respective config header in a manner independent of the requested
7299 output debugging format.
7301 This does not match the arrangement below, which presumes that
7302 the SDB and stabs numbering schemes differ from the DWARF and
7303 DWARF 2 ones. The reason for this arrangement is that it is
7304 likely to get the numbering scheme for the target's
7305 default/native debug format right. For targets where GCC is the
7306 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7307 targets where the native toolchain uses a different numbering
7308 scheme for a particular debug format (stabs-in-ELF on Solaris)
7309 the defaults below will have to be overridden, like
7310 i386_elf_init_abi() does. */
7312 /* Use the dbx register numbering scheme for stabs and COFF. */
7313 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
7314 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
7316 /* Use the SVR4 register numbering scheme for DWARF 2. */
7317 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
7319 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7320 be in use on any of the supported i386 targets. */
7322 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
7324 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
7326 /* Call dummy code. */
7327 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
7328 set_gdbarch_frame_align (gdbarch, i386_frame_align);
7330 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
7331 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
7332 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
7334 set_gdbarch_return_value (gdbarch, i386_return_value);
7336 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
7338 /* Stack grows downward. */
7339 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
7341 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc);
7342 set_gdbarch_decr_pc_after_break (gdbarch, 1);
7343 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
7345 set_gdbarch_frame_args_skip (gdbarch, 8);
7347 set_gdbarch_print_insn (gdbarch, i386_print_insn);
7349 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
7351 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
7353 /* Add the i386 register groups. */
7354 i386_add_reggroups (gdbarch);
7355 tdep->register_reggroup_p = i386_register_reggroup_p;
7357 /* Helper for function argument information. */
7358 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
7360 /* Hook the function epilogue frame unwinder. This unwinder is
7361 appended to the list first, so that it supercedes the DWARF
7362 unwinder in function epilogues (where the DWARF unwinder
7363 currently fails). */
7364 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
7366 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7367 to the list before the prologue-based unwinders, so that DWARF
7368 CFI info will be used if it is available. */
7369 dwarf2_append_unwinders (gdbarch);
7371 frame_base_set_default (gdbarch, &i386_frame_base);
7373 /* Pseudo registers may be changed by amd64_init_abi. */
7374 set_gdbarch_pseudo_register_read_value (gdbarch,
7375 i386_pseudo_register_read_value);
7376 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
7378 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
7379 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
7381 /* Override the normal target description method to make the AVX
7382 upper halves anonymous. */
7383 set_gdbarch_register_name (gdbarch, i386_register_name);
7385 /* Even though the default ABI only includes general-purpose registers,
7386 floating-point registers and the SSE registers, we have to leave a
7387 gap for the upper AVX registers. */
7388 set_gdbarch_num_regs (gdbarch, I386_AVX_NUM_REGS);
7390 /* Get the x86 target description from INFO. */
7391 tdesc = info.target_desc;
7392 if (! tdesc_has_registers (tdesc))
7394 tdep->tdesc = tdesc;
7396 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
7397 tdep->register_names = i386_register_names;
7399 /* No upper YMM registers. */
7400 tdep->ymmh_register_names = NULL;
7401 tdep->ymm0h_regnum = -1;
7403 tdep->num_byte_regs = 8;
7404 tdep->num_word_regs = 8;
7405 tdep->num_dword_regs = 0;
7406 tdep->num_mmx_regs = 8;
7407 tdep->num_ymm_regs = 0;
7409 tdesc_data = tdesc_data_alloc ();
7411 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
7413 /* Hook in ABI-specific overrides, if they have been registered. */
7414 info.tdep_info = (void *) tdesc_data;
7415 gdbarch_init_osabi (info, gdbarch);
7417 if (!i386_validate_tdesc_p (tdep, tdesc_data))
7419 tdesc_data_cleanup (tdesc_data);
7421 gdbarch_free (gdbarch);
7425 /* Wire in pseudo registers. Number of pseudo registers may be
7427 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
7428 + tdep->num_word_regs
7429 + tdep->num_dword_regs
7430 + tdep->num_mmx_regs
7431 + tdep->num_ymm_regs));
7433 /* Target description may be changed. */
7434 tdesc = tdep->tdesc;
7436 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
7438 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7439 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
7441 /* Make %al the first pseudo-register. */
7442 tdep->al_regnum = gdbarch_num_regs (gdbarch);
7443 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
7445 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
7446 if (tdep->num_dword_regs)
7448 /* Support dword pseudo-register if it hasn't been disabled. */
7449 tdep->eax_regnum = ymm0_regnum;
7450 ymm0_regnum += tdep->num_dword_regs;
7453 tdep->eax_regnum = -1;
7455 mm0_regnum = ymm0_regnum;
7456 if (tdep->num_ymm_regs)
7458 /* Support YMM pseudo-register if it is available. */
7459 tdep->ymm0_regnum = ymm0_regnum;
7460 mm0_regnum += tdep->num_ymm_regs;
7463 tdep->ymm0_regnum = -1;
7465 if (tdep->num_mmx_regs != 0)
7467 /* Support MMX pseudo-register if MMX hasn't been disabled. */
7468 tdep->mm0_regnum = mm0_regnum;
7471 tdep->mm0_regnum = -1;
7473 /* Hook in the legacy prologue-based unwinders last (fallback). */
7474 frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind);
7475 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
7476 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
7478 /* If we have a register mapping, enable the generic core file
7479 support, unless it has already been enabled. */
7480 if (tdep->gregset_reg_offset
7481 && !gdbarch_regset_from_core_section_p (gdbarch))
7482 set_gdbarch_regset_from_core_section (gdbarch,
7483 i386_regset_from_core_section);
7485 set_gdbarch_skip_permanent_breakpoint (gdbarch,
7486 i386_skip_permanent_breakpoint);
7488 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
7489 i386_fast_tracepoint_valid_at);
7494 static enum gdb_osabi
7495 i386_coff_osabi_sniffer (bfd *abfd)
7497 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
7498 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
7499 return GDB_OSABI_GO32;
7501 return GDB_OSABI_UNKNOWN;
7505 /* Provide a prototype to silence -Wmissing-prototypes. */
7506 void _initialize_i386_tdep (void);
7509 _initialize_i386_tdep (void)
7511 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
7513 /* Add the variable that controls the disassembly flavor. */
7514 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
7515 &disassembly_flavor, _("\
7516 Set the disassembly flavor."), _("\
7517 Show the disassembly flavor."), _("\
7518 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7520 NULL, /* FIXME: i18n: */
7521 &setlist, &showlist);
7523 /* Add the variable that controls the convention for returning
7525 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
7526 &struct_convention, _("\
7527 Set the convention for returning small structs."), _("\
7528 Show the convention for returning small structs."), _("\
7529 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7532 NULL, /* FIXME: i18n: */
7533 &setlist, &showlist);
7535 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
7536 i386_coff_osabi_sniffer);
7538 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
7539 i386_svr4_init_abi);
7540 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
7541 i386_go32_init_abi);
7543 /* Initialize the i386-specific register groups. */
7544 i386_init_reggroups ();
7546 /* Initialize the standard target descriptions. */
7547 initialize_tdesc_i386 ();
7548 initialize_tdesc_i386_mmx ();
7549 initialize_tdesc_i386_avx ();
7551 /* Tell remote stub that we support XML target description. */
7552 register_remote_support_xml ("i386");