1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
49 #include "gdb_assert.h"
50 #include "gdb_string.h"
52 #include "i386-tdep.h"
53 #include "i387-tdep.h"
54 #include "i386-xstate.h"
59 #include "features/i386/i386.c"
60 #include "features/i386/i386-avx.c"
61 #include "features/i386/i386-mmx.c"
65 static const char *i386_register_names[] =
67 "eax", "ecx", "edx", "ebx",
68 "esp", "ebp", "esi", "edi",
69 "eip", "eflags", "cs", "ss",
70 "ds", "es", "fs", "gs",
71 "st0", "st1", "st2", "st3",
72 "st4", "st5", "st6", "st7",
73 "fctrl", "fstat", "ftag", "fiseg",
74 "fioff", "foseg", "fooff", "fop",
75 "xmm0", "xmm1", "xmm2", "xmm3",
76 "xmm4", "xmm5", "xmm6", "xmm7",
80 static const char *i386_ymm_names[] =
82 "ymm0", "ymm1", "ymm2", "ymm3",
83 "ymm4", "ymm5", "ymm6", "ymm7",
86 static const char *i386_ymmh_names[] =
88 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
89 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
92 /* Register names for MMX pseudo-registers. */
94 static const char *i386_mmx_names[] =
96 "mm0", "mm1", "mm2", "mm3",
97 "mm4", "mm5", "mm6", "mm7"
100 /* Register names for byte pseudo-registers. */
102 static const char *i386_byte_names[] =
104 "al", "cl", "dl", "bl",
105 "ah", "ch", "dh", "bh"
108 /* Register names for word pseudo-registers. */
110 static const char *i386_word_names[] =
112 "ax", "cx", "dx", "bx",
119 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
121 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
122 int mm0_regnum = tdep->mm0_regnum;
127 regnum -= mm0_regnum;
128 return regnum >= 0 && regnum < tdep->num_mmx_regs;
134 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
136 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
138 regnum -= tdep->al_regnum;
139 return regnum >= 0 && regnum < tdep->num_byte_regs;
145 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
147 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
149 regnum -= tdep->ax_regnum;
150 return regnum >= 0 && regnum < tdep->num_word_regs;
153 /* Dword register? */
156 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
158 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
159 int eax_regnum = tdep->eax_regnum;
164 regnum -= eax_regnum;
165 return regnum >= 0 && regnum < tdep->num_dword_regs;
169 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
171 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
172 int ymm0h_regnum = tdep->ymm0h_regnum;
174 if (ymm0h_regnum < 0)
177 regnum -= ymm0h_regnum;
178 return regnum >= 0 && regnum < tdep->num_ymm_regs;
184 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
186 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
187 int ymm0_regnum = tdep->ymm0_regnum;
192 regnum -= ymm0_regnum;
193 return regnum >= 0 && regnum < tdep->num_ymm_regs;
199 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
201 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
202 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
204 if (num_xmm_regs == 0)
207 regnum -= I387_XMM0_REGNUM (tdep);
208 return regnum >= 0 && regnum < num_xmm_regs;
212 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
214 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
216 if (I387_NUM_XMM_REGS (tdep) == 0)
219 return (regnum == I387_MXCSR_REGNUM (tdep));
225 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
227 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
229 if (I387_ST0_REGNUM (tdep) < 0)
232 return (I387_ST0_REGNUM (tdep) <= regnum
233 && regnum < I387_FCTRL_REGNUM (tdep));
237 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
239 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
241 if (I387_ST0_REGNUM (tdep) < 0)
244 return (I387_FCTRL_REGNUM (tdep) <= regnum
245 && regnum < I387_XMM0_REGNUM (tdep));
248 /* Return the name of register REGNUM, or the empty string if it is
249 an anonymous register. */
252 i386_register_name (struct gdbarch *gdbarch, int regnum)
254 /* Hide the upper YMM registers. */
255 if (i386_ymmh_regnum_p (gdbarch, regnum))
258 return tdesc_register_name (gdbarch, regnum);
261 /* Return the name of register REGNUM. */
264 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
266 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
267 if (i386_mmx_regnum_p (gdbarch, regnum))
268 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
269 else if (i386_ymm_regnum_p (gdbarch, regnum))
270 return i386_ymm_names[regnum - tdep->ymm0_regnum];
271 else if (i386_byte_regnum_p (gdbarch, regnum))
272 return i386_byte_names[regnum - tdep->al_regnum];
273 else if (i386_word_regnum_p (gdbarch, regnum))
274 return i386_word_names[regnum - tdep->ax_regnum];
276 internal_error (__FILE__, __LINE__, _("invalid regnum"));
279 /* Convert a dbx register number REG to the appropriate register
280 number used by GDB. */
283 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
285 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
287 /* This implements what GCC calls the "default" register map
288 (dbx_register_map[]). */
290 if (reg >= 0 && reg <= 7)
292 /* General-purpose registers. The debug info calls %ebp
293 register 4, and %esp register 5. */
300 else if (reg >= 12 && reg <= 19)
302 /* Floating-point registers. */
303 return reg - 12 + I387_ST0_REGNUM (tdep);
305 else if (reg >= 21 && reg <= 28)
308 int ymm0_regnum = tdep->ymm0_regnum;
311 && i386_xmm_regnum_p (gdbarch, reg))
312 return reg - 21 + ymm0_regnum;
314 return reg - 21 + I387_XMM0_REGNUM (tdep);
316 else if (reg >= 29 && reg <= 36)
319 return reg - 29 + I387_MM0_REGNUM (tdep);
322 /* This will hopefully provoke a warning. */
323 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
326 /* Convert SVR4 register number REG to the appropriate register number
330 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
332 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
334 /* This implements the GCC register map that tries to be compatible
335 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
337 /* The SVR4 register numbering includes %eip and %eflags, and
338 numbers the floating point registers differently. */
339 if (reg >= 0 && reg <= 9)
341 /* General-purpose registers. */
344 else if (reg >= 11 && reg <= 18)
346 /* Floating-point registers. */
347 return reg - 11 + I387_ST0_REGNUM (tdep);
349 else if (reg >= 21 && reg <= 36)
351 /* The SSE and MMX registers have the same numbers as with dbx. */
352 return i386_dbx_reg_to_regnum (gdbarch, reg);
357 case 37: return I387_FCTRL_REGNUM (tdep);
358 case 38: return I387_FSTAT_REGNUM (tdep);
359 case 39: return I387_MXCSR_REGNUM (tdep);
360 case 40: return I386_ES_REGNUM;
361 case 41: return I386_CS_REGNUM;
362 case 42: return I386_SS_REGNUM;
363 case 43: return I386_DS_REGNUM;
364 case 44: return I386_FS_REGNUM;
365 case 45: return I386_GS_REGNUM;
368 /* This will hopefully provoke a warning. */
369 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
374 /* This is the variable that is set with "set disassembly-flavor", and
375 its legitimate values. */
376 static const char att_flavor[] = "att";
377 static const char intel_flavor[] = "intel";
378 static const char *valid_flavors[] =
384 static const char *disassembly_flavor = att_flavor;
387 /* Use the program counter to determine the contents and size of a
388 breakpoint instruction. Return a pointer to a string of bytes that
389 encode a breakpoint instruction, store the length of the string in
390 *LEN and optionally adjust *PC to point to the correct memory
391 location for inserting the breakpoint.
393 On the i386 we have a single breakpoint that fits in a single byte
394 and can be inserted anywhere.
396 This function is 64-bit safe. */
398 static const gdb_byte *
399 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
401 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */
403 *len = sizeof (break_insn);
407 /* Displaced instruction handling. */
409 /* Skip the legacy instruction prefixes in INSN.
410 Not all prefixes are valid for any particular insn
411 but we needn't care, the insn will fault if it's invalid.
412 The result is a pointer to the first opcode byte,
413 or NULL if we run off the end of the buffer. */
416 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
418 gdb_byte *end = insn + max_len;
424 case DATA_PREFIX_OPCODE:
425 case ADDR_PREFIX_OPCODE:
426 case CS_PREFIX_OPCODE:
427 case DS_PREFIX_OPCODE:
428 case ES_PREFIX_OPCODE:
429 case FS_PREFIX_OPCODE:
430 case GS_PREFIX_OPCODE:
431 case SS_PREFIX_OPCODE:
432 case LOCK_PREFIX_OPCODE:
433 case REPE_PREFIX_OPCODE:
434 case REPNE_PREFIX_OPCODE:
446 i386_absolute_jmp_p (const gdb_byte *insn)
448 /* jmp far (absolute address in operand) */
454 /* jump near, absolute indirect (/4) */
455 if ((insn[1] & 0x38) == 0x20)
458 /* jump far, absolute indirect (/5) */
459 if ((insn[1] & 0x38) == 0x28)
467 i386_absolute_call_p (const gdb_byte *insn)
469 /* call far, absolute */
475 /* Call near, absolute indirect (/2) */
476 if ((insn[1] & 0x38) == 0x10)
479 /* Call far, absolute indirect (/3) */
480 if ((insn[1] & 0x38) == 0x18)
488 i386_ret_p (const gdb_byte *insn)
492 case 0xc2: /* ret near, pop N bytes */
493 case 0xc3: /* ret near */
494 case 0xca: /* ret far, pop N bytes */
495 case 0xcb: /* ret far */
496 case 0xcf: /* iret */
505 i386_call_p (const gdb_byte *insn)
507 if (i386_absolute_call_p (insn))
510 /* call near, relative */
517 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
518 length in bytes. Otherwise, return zero. */
521 i386_syscall_p (const gdb_byte *insn, ULONGEST *lengthp)
532 /* Fix up the state of registers and memory after having single-stepped
533 a displaced instruction. */
536 i386_displaced_step_fixup (struct gdbarch *gdbarch,
537 struct displaced_step_closure *closure,
538 CORE_ADDR from, CORE_ADDR to,
539 struct regcache *regs)
541 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
543 /* The offset we applied to the instruction's address.
544 This could well be negative (when viewed as a signed 32-bit
545 value), but ULONGEST won't reflect that, so take care when
547 ULONGEST insn_offset = to - from;
549 /* Since we use simple_displaced_step_copy_insn, our closure is a
550 copy of the instruction. */
551 gdb_byte *insn = (gdb_byte *) closure;
552 /* The start of the insn, needed in case we see some prefixes. */
553 gdb_byte *insn_start = insn;
556 fprintf_unfiltered (gdb_stdlog,
557 "displaced: fixup (%s, %s), "
558 "insn = 0x%02x 0x%02x ...\n",
559 paddress (gdbarch, from), paddress (gdbarch, to),
562 /* The list of issues to contend with here is taken from
563 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
564 Yay for Free Software! */
566 /* Relocate the %eip, if necessary. */
568 /* The instruction recognizers we use assume any leading prefixes
569 have been skipped. */
571 /* This is the size of the buffer in closure. */
572 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
573 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
574 /* If there are too many prefixes, just ignore the insn.
575 It will fault when run. */
580 /* Except in the case of absolute or indirect jump or call
581 instructions, or a return instruction, the new eip is relative to
582 the displaced instruction; make it relative. Well, signal
583 handler returns don't need relocation either, but we use the
584 value of %eip to recognize those; see below. */
585 if (! i386_absolute_jmp_p (insn)
586 && ! i386_absolute_call_p (insn)
587 && ! i386_ret_p (insn))
592 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
594 /* A signal trampoline system call changes the %eip, resuming
595 execution of the main program after the signal handler has
596 returned. That makes them like 'return' instructions; we
597 shouldn't relocate %eip.
599 But most system calls don't, and we do need to relocate %eip.
601 Our heuristic for distinguishing these cases: if stepping
602 over the system call instruction left control directly after
603 the instruction, the we relocate --- control almost certainly
604 doesn't belong in the displaced copy. Otherwise, we assume
605 the instruction has put control where it belongs, and leave
606 it unrelocated. Goodness help us if there are PC-relative
608 if (i386_syscall_p (insn, &insn_len)
609 && orig_eip != to + (insn - insn_start) + insn_len)
612 fprintf_unfiltered (gdb_stdlog,
613 "displaced: syscall changed %%eip; "
618 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
620 /* If we just stepped over a breakpoint insn, we don't backup
621 the pc on purpose; this is to match behaviour without
624 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
627 fprintf_unfiltered (gdb_stdlog,
629 "relocated %%eip from %s to %s\n",
630 paddress (gdbarch, orig_eip),
631 paddress (gdbarch, eip));
635 /* If the instruction was PUSHFL, then the TF bit will be set in the
636 pushed value, and should be cleared. We'll leave this for later,
637 since GDB already messes up the TF flag when stepping over a
640 /* If the instruction was a call, the return address now atop the
641 stack is the address following the copied instruction. We need
642 to make it the address following the original instruction. */
643 if (i386_call_p (insn))
647 const ULONGEST retaddr_len = 4;
649 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
650 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
651 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
652 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
655 fprintf_unfiltered (gdb_stdlog,
656 "displaced: relocated return addr at %s to %s\n",
657 paddress (gdbarch, esp),
658 paddress (gdbarch, retaddr));
663 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
665 target_write_memory (*to, buf, len);
670 i386_relocate_instruction (struct gdbarch *gdbarch,
671 CORE_ADDR *to, CORE_ADDR oldloc)
673 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
674 gdb_byte buf[I386_MAX_INSN_LEN];
675 int offset = 0, rel32, newrel;
677 gdb_byte *insn = buf;
679 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
681 insn_length = gdb_buffered_insn_length (gdbarch, insn,
682 I386_MAX_INSN_LEN, oldloc);
684 /* Get past the prefixes. */
685 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
687 /* Adjust calls with 32-bit relative addresses as push/jump, with
688 the address pushed being the location where the original call in
689 the user program would return to. */
692 gdb_byte push_buf[16];
693 unsigned int ret_addr;
695 /* Where "ret" in the original code will return to. */
696 ret_addr = oldloc + insn_length;
697 push_buf[0] = 0x68; /* pushq $... */
698 memcpy (&push_buf[1], &ret_addr, 4);
700 append_insns (to, 5, push_buf);
702 /* Convert the relative call to a relative jump. */
705 /* Adjust the destination offset. */
706 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
707 newrel = (oldloc - *to) + rel32;
708 store_signed_integer (insn + 1, 4, newrel, byte_order);
710 /* Write the adjusted jump into its displaced location. */
711 append_insns (to, 5, insn);
715 /* Adjust jumps with 32-bit relative addresses. Calls are already
719 /* Adjust conditional jumps. */
720 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
725 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
726 newrel = (oldloc - *to) + rel32;
727 store_signed_integer (insn + offset, 4, newrel, byte_order);
729 fprintf_unfiltered (gdb_stdlog,
730 "Adjusted insn rel32=0x%s at 0x%s to"
731 " rel32=0x%s at 0x%s\n",
732 hex_string (rel32), paddress (gdbarch, oldloc),
733 hex_string (newrel), paddress (gdbarch, *to));
736 /* Write the adjusted instructions into their displaced
738 append_insns (to, insn_length, buf);
742 #ifdef I386_REGNO_TO_SYMMETRY
743 #error "The Sequent Symmetry is no longer supported."
746 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
747 and %esp "belong" to the calling function. Therefore these
748 registers should be saved if they're going to be modified. */
750 /* The maximum number of saved registers. This should include all
751 registers mentioned above, and %eip. */
752 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
754 struct i386_frame_cache
761 /* Saved registers. */
762 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
767 /* Stack space reserved for local variables. */
771 /* Allocate and initialize a frame cache. */
773 static struct i386_frame_cache *
774 i386_alloc_frame_cache (void)
776 struct i386_frame_cache *cache;
779 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
783 cache->sp_offset = -4;
786 /* Saved registers. We initialize these to -1 since zero is a valid
787 offset (that's where %ebp is supposed to be stored). */
788 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
789 cache->saved_regs[i] = -1;
791 cache->saved_sp_reg = -1;
792 cache->pc_in_eax = 0;
794 /* Frameless until proven otherwise. */
800 /* If the instruction at PC is a jump, return the address of its
801 target. Otherwise, return PC. */
804 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
806 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
811 target_read_memory (pc, &op, 1);
815 op = read_memory_unsigned_integer (pc + 1, 1, byte_order);
821 /* Relative jump: if data16 == 0, disp32, else disp16. */
824 delta = read_memory_integer (pc + 2, 2, byte_order);
826 /* Include the size of the jmp instruction (including the
832 delta = read_memory_integer (pc + 1, 4, byte_order);
834 /* Include the size of the jmp instruction. */
839 /* Relative jump, disp8 (ignore data16). */
840 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
849 /* Check whether PC points at a prologue for a function returning a
850 structure or union. If so, it updates CACHE and returns the
851 address of the first instruction after the code sequence that
852 removes the "hidden" argument from the stack or CURRENT_PC,
853 whichever is smaller. Otherwise, return PC. */
856 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
857 struct i386_frame_cache *cache)
859 /* Functions that return a structure or union start with:
862 xchgl %eax, (%esp) 0x87 0x04 0x24
863 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
865 (the System V compiler puts out the second `xchg' instruction,
866 and the assembler doesn't try to optimize it, so the 'sib' form
867 gets generated). This sequence is used to get the address of the
868 return buffer for a function that returns a structure. */
869 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
870 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
874 if (current_pc <= pc)
877 target_read_memory (pc, &op, 1);
879 if (op != 0x58) /* popl %eax */
882 target_read_memory (pc + 1, buf, 4);
883 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
886 if (current_pc == pc)
888 cache->sp_offset += 4;
892 if (current_pc == pc + 1)
894 cache->pc_in_eax = 1;
898 if (buf[1] == proto1[1])
905 i386_skip_probe (CORE_ADDR pc)
907 /* A function may start with
921 target_read_memory (pc, &op, 1);
923 if (op == 0x68 || op == 0x6a)
927 /* Skip past the `pushl' instruction; it has either a one-byte or a
928 four-byte operand, depending on the opcode. */
934 /* Read the following 8 bytes, which should be `call _probe' (6
935 bytes) followed by `addl $4,%esp' (2 bytes). */
936 read_memory (pc + delta, buf, sizeof (buf));
937 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
938 pc += delta + sizeof (buf);
944 /* GCC 4.1 and later, can put code in the prologue to realign the
945 stack pointer. Check whether PC points to such code, and update
946 CACHE accordingly. Return the first instruction after the code
947 sequence or CURRENT_PC, whichever is smaller. If we don't
948 recognize the code, return PC. */
951 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
952 struct i386_frame_cache *cache)
954 /* There are 2 code sequences to re-align stack before the frame
957 1. Use a caller-saved saved register:
963 2. Use a callee-saved saved register:
970 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
972 0x83 0xe4 0xf0 andl $-16, %esp
973 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
978 int offset, offset_and;
979 static int regnums[8] = {
980 I386_EAX_REGNUM, /* %eax */
981 I386_ECX_REGNUM, /* %ecx */
982 I386_EDX_REGNUM, /* %edx */
983 I386_EBX_REGNUM, /* %ebx */
984 I386_ESP_REGNUM, /* %esp */
985 I386_EBP_REGNUM, /* %ebp */
986 I386_ESI_REGNUM, /* %esi */
987 I386_EDI_REGNUM /* %edi */
990 if (target_read_memory (pc, buf, sizeof buf))
993 /* Check caller-saved saved register. The first instruction has
994 to be "leal 4(%esp), %reg". */
995 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
997 /* MOD must be binary 10 and R/M must be binary 100. */
998 if ((buf[1] & 0xc7) != 0x44)
1001 /* REG has register number. */
1002 reg = (buf[1] >> 3) & 7;
1007 /* Check callee-saved saved register. The first instruction
1008 has to be "pushl %reg". */
1009 if ((buf[0] & 0xf8) != 0x50)
1015 /* The next instruction has to be "leal 8(%esp), %reg". */
1016 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1019 /* MOD must be binary 10 and R/M must be binary 100. */
1020 if ((buf[2] & 0xc7) != 0x44)
1023 /* REG has register number. Registers in pushl and leal have to
1025 if (reg != ((buf[2] >> 3) & 7))
1031 /* Rigister can't be %esp nor %ebp. */
1032 if (reg == 4 || reg == 5)
1035 /* The next instruction has to be "andl $-XXX, %esp". */
1036 if (buf[offset + 1] != 0xe4
1037 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1040 offset_and = offset;
1041 offset += buf[offset] == 0x81 ? 6 : 3;
1043 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1044 0xfc. REG must be binary 110 and MOD must be binary 01. */
1045 if (buf[offset] != 0xff
1046 || buf[offset + 2] != 0xfc
1047 || (buf[offset + 1] & 0xf8) != 0x70)
1050 /* R/M has register. Registers in leal and pushl have to be the
1052 if (reg != (buf[offset + 1] & 7))
1055 if (current_pc > pc + offset_and)
1056 cache->saved_sp_reg = regnums[reg];
1058 return min (pc + offset + 3, current_pc);
1061 /* Maximum instruction length we need to handle. */
1062 #define I386_MAX_MATCHED_INSN_LEN 6
1064 /* Instruction description. */
1068 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
1069 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
1072 /* Search for the instruction at PC in the list SKIP_INSNS. Return
1073 the first instruction description that matches. Otherwise, return
1076 static struct i386_insn *
1077 i386_match_insn (CORE_ADDR pc, struct i386_insn *skip_insns)
1079 struct i386_insn *insn;
1082 target_read_memory (pc, &op, 1);
1084 for (insn = skip_insns; insn->len > 0; insn++)
1086 if ((op & insn->mask[0]) == insn->insn[0])
1088 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1089 int insn_matched = 1;
1092 gdb_assert (insn->len > 1);
1093 gdb_assert (insn->len <= I386_MAX_MATCHED_INSN_LEN);
1095 target_read_memory (pc + 1, buf, insn->len - 1);
1096 for (i = 1; i < insn->len; i++)
1098 if ((buf[i - 1] & insn->mask[i]) != insn->insn[i])
1110 /* Some special instructions that might be migrated by GCC into the
1111 part of the prologue that sets up the new stack frame. Because the
1112 stack frame hasn't been setup yet, no registers have been saved
1113 yet, and only the scratch registers %eax, %ecx and %edx can be
1116 struct i386_insn i386_frame_setup_skip_insns[] =
1118 /* Check for `movb imm8, r' and `movl imm32, r'.
1120 ??? Should we handle 16-bit operand-sizes here? */
1122 /* `movb imm8, %al' and `movb imm8, %ah' */
1123 /* `movb imm8, %cl' and `movb imm8, %ch' */
1124 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1125 /* `movb imm8, %dl' and `movb imm8, %dh' */
1126 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1127 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1128 { 5, { 0xb8 }, { 0xfe } },
1129 /* `movl imm32, %edx' */
1130 { 5, { 0xba }, { 0xff } },
1132 /* Check for `mov imm32, r32'. Note that there is an alternative
1133 encoding for `mov m32, %eax'.
1135 ??? Should we handle SIB adressing here?
1136 ??? Should we handle 16-bit operand-sizes here? */
1138 /* `movl m32, %eax' */
1139 { 5, { 0xa1 }, { 0xff } },
1140 /* `movl m32, %eax' and `mov; m32, %ecx' */
1141 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1142 /* `movl m32, %edx' */
1143 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1145 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1146 Because of the symmetry, there are actually two ways to encode
1147 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1148 opcode bytes 0x31 and 0x33 for `xorl'. */
1150 /* `subl %eax, %eax' */
1151 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1152 /* `subl %ecx, %ecx' */
1153 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1154 /* `subl %edx, %edx' */
1155 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1156 /* `xorl %eax, %eax' */
1157 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1158 /* `xorl %ecx, %ecx' */
1159 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1160 /* `xorl %edx, %edx' */
1161 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1166 /* Check whether PC points to a no-op instruction. */
1168 i386_skip_noop (CORE_ADDR pc)
1173 target_read_memory (pc, &op, 1);
1178 /* Ignore `nop' instruction. */
1182 target_read_memory (pc, &op, 1);
1185 /* Ignore no-op instruction `mov %edi, %edi'.
1186 Microsoft system dlls often start with
1187 a `mov %edi,%edi' instruction.
1188 The 5 bytes before the function start are
1189 filled with `nop' instructions.
1190 This pattern can be used for hot-patching:
1191 The `mov %edi, %edi' instruction can be replaced by a
1192 near jump to the location of the 5 `nop' instructions
1193 which can be replaced by a 32-bit jump to anywhere
1194 in the 32-bit address space. */
1196 else if (op == 0x8b)
1198 target_read_memory (pc + 1, &op, 1);
1202 target_read_memory (pc, &op, 1);
1210 /* Check whether PC points at a code that sets up a new stack frame.
1211 If so, it updates CACHE and returns the address of the first
1212 instruction after the sequence that sets up the frame or LIMIT,
1213 whichever is smaller. If we don't recognize the code, return PC. */
1216 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1217 CORE_ADDR pc, CORE_ADDR limit,
1218 struct i386_frame_cache *cache)
1220 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1221 struct i386_insn *insn;
1228 target_read_memory (pc, &op, 1);
1230 if (op == 0x55) /* pushl %ebp */
1232 /* Take into account that we've executed the `pushl %ebp' that
1233 starts this instruction sequence. */
1234 cache->saved_regs[I386_EBP_REGNUM] = 0;
1235 cache->sp_offset += 4;
1238 /* If that's all, return now. */
1242 /* Check for some special instructions that might be migrated by
1243 GCC into the prologue and skip them. At this point in the
1244 prologue, code should only touch the scratch registers %eax,
1245 %ecx and %edx, so while the number of posibilities is sheer,
1248 Make sure we only skip these instructions if we later see the
1249 `movl %esp, %ebp' that actually sets up the frame. */
1250 while (pc + skip < limit)
1252 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1259 /* If that's all, return now. */
1260 if (limit <= pc + skip)
1263 target_read_memory (pc + skip, &op, 1);
1265 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1269 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1274 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1282 /* OK, we actually have a frame. We just don't know how large
1283 it is yet. Set its size to zero. We'll adjust it if
1284 necessary. We also now commit to skipping the special
1285 instructions mentioned before. */
1289 /* If that's all, return now. */
1293 /* Check for stack adjustment
1297 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1298 reg, so we don't have to worry about a data16 prefix. */
1299 target_read_memory (pc, &op, 1);
1302 /* `subl' with 8-bit immediate. */
1303 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1304 /* Some instruction starting with 0x83 other than `subl'. */
1307 /* `subl' with signed 8-bit immediate (though it wouldn't
1308 make sense to be negative). */
1309 cache->locals = read_memory_integer (pc + 2, 1, byte_order);
1312 else if (op == 0x81)
1314 /* Maybe it is `subl' with a 32-bit immediate. */
1315 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1316 /* Some instruction starting with 0x81 other than `subl'. */
1319 /* It is `subl' with a 32-bit immediate. */
1320 cache->locals = read_memory_integer (pc + 2, 4, byte_order);
1325 /* Some instruction other than `subl'. */
1329 else if (op == 0xc8) /* enter */
1331 cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order);
1338 /* Check whether PC points at code that saves registers on the stack.
1339 If so, it updates CACHE and returns the address of the first
1340 instruction after the register saves or CURRENT_PC, whichever is
1341 smaller. Otherwise, return PC. */
1344 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1345 struct i386_frame_cache *cache)
1347 CORE_ADDR offset = 0;
1351 if (cache->locals > 0)
1352 offset -= cache->locals;
1353 for (i = 0; i < 8 && pc < current_pc; i++)
1355 target_read_memory (pc, &op, 1);
1356 if (op < 0x50 || op > 0x57)
1360 cache->saved_regs[op - 0x50] = offset;
1361 cache->sp_offset += 4;
1368 /* Do a full analysis of the prologue at PC and update CACHE
1369 accordingly. Bail out early if CURRENT_PC is reached. Return the
1370 address where the analysis stopped.
1372 We handle these cases:
1374 The startup sequence can be at the start of the function, or the
1375 function can start with a branch to startup code at the end.
1377 %ebp can be set up with either the 'enter' instruction, or "pushl
1378 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1379 once used in the System V compiler).
1381 Local space is allocated just below the saved %ebp by either the
1382 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1383 16-bit unsigned argument for space to allocate, and the 'addl'
1384 instruction could have either a signed byte, or 32-bit immediate.
1386 Next, the registers used by this function are pushed. With the
1387 System V compiler they will always be in the order: %edi, %esi,
1388 %ebx (and sometimes a harmless bug causes it to also save but not
1389 restore %eax); however, the code below is willing to see the pushes
1390 in any order, and will handle up to 8 of them.
1392 If the setup sequence is at the end of the function, then the next
1393 instruction will be a branch back to the start. */
1396 i386_analyze_prologue (struct gdbarch *gdbarch,
1397 CORE_ADDR pc, CORE_ADDR current_pc,
1398 struct i386_frame_cache *cache)
1400 pc = i386_skip_noop (pc);
1401 pc = i386_follow_jump (gdbarch, pc);
1402 pc = i386_analyze_struct_return (pc, current_pc, cache);
1403 pc = i386_skip_probe (pc);
1404 pc = i386_analyze_stack_align (pc, current_pc, cache);
1405 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1406 return i386_analyze_register_saves (pc, current_pc, cache);
1409 /* Return PC of first real instruction. */
1412 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1414 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1416 static gdb_byte pic_pat[6] =
1418 0xe8, 0, 0, 0, 0, /* call 0x0 */
1419 0x5b, /* popl %ebx */
1421 struct i386_frame_cache cache;
1427 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1428 if (cache.locals < 0)
1431 /* Found valid frame setup. */
1433 /* The native cc on SVR4 in -K PIC mode inserts the following code
1434 to get the address of the global offset table (GOT) into register
1439 movl %ebx,x(%ebp) (optional)
1442 This code is with the rest of the prologue (at the end of the
1443 function), so we have to skip it to get to the first real
1444 instruction at the start of the function. */
1446 for (i = 0; i < 6; i++)
1448 target_read_memory (pc + i, &op, 1);
1449 if (pic_pat[i] != op)
1456 target_read_memory (pc + delta, &op, 1);
1458 if (op == 0x89) /* movl %ebx, x(%ebp) */
1460 op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order);
1462 if (op == 0x5d) /* One byte offset from %ebp. */
1464 else if (op == 0x9d) /* Four byte offset from %ebp. */
1466 else /* Unexpected instruction. */
1469 target_read_memory (pc + delta, &op, 1);
1473 if (delta > 0 && op == 0x81
1474 && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order)
1481 /* If the function starts with a branch (to startup code at the end)
1482 the last instruction should bring us back to the first
1483 instruction of the real code. */
1484 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1485 pc = i386_follow_jump (gdbarch, pc);
1490 /* Check that the code pointed to by PC corresponds to a call to
1491 __main, skip it if so. Return PC otherwise. */
1494 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1496 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1499 target_read_memory (pc, &op, 1);
1504 if (target_read_memory (pc + 1, buf, sizeof buf) == 0)
1506 /* Make sure address is computed correctly as a 32bit
1507 integer even if CORE_ADDR is 64 bit wide. */
1508 struct minimal_symbol *s;
1509 CORE_ADDR call_dest;
1511 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1512 call_dest = call_dest & 0xffffffffU;
1513 s = lookup_minimal_symbol_by_pc (call_dest);
1515 && SYMBOL_LINKAGE_NAME (s) != NULL
1516 && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0)
1524 /* This function is 64-bit safe. */
1527 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1531 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1532 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1536 /* Normal frames. */
1538 static struct i386_frame_cache *
1539 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
1541 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1542 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1543 struct i386_frame_cache *cache;
1550 cache = i386_alloc_frame_cache ();
1551 *this_cache = cache;
1553 /* In principle, for normal frames, %ebp holds the frame pointer,
1554 which holds the base address for the current stack frame.
1555 However, for functions that don't need it, the frame pointer is
1556 optional. For these "frameless" functions the frame pointer is
1557 actually the frame pointer of the calling frame. Signal
1558 trampolines are just a special case of a "frameless" function.
1559 They (usually) share their frame pointer with the frame that was
1560 in progress when the signal occurred. */
1562 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1563 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1564 if (cache->base == 0)
1567 /* For normal frames, %eip is stored at 4(%ebp). */
1568 cache->saved_regs[I386_EIP_REGNUM] = 4;
1570 cache->pc = get_frame_func (this_frame);
1572 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
1575 if (cache->saved_sp_reg != -1)
1577 /* Saved stack pointer has been saved. */
1578 get_frame_register (this_frame, cache->saved_sp_reg, buf);
1579 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
1582 if (cache->locals < 0)
1584 /* We didn't find a valid frame, which means that CACHE->base
1585 currently holds the frame pointer for our calling frame. If
1586 we're at the start of a function, or somewhere half-way its
1587 prologue, the function's frame probably hasn't been fully
1588 setup yet. Try to reconstruct the base address for the stack
1589 frame by looking at the stack pointer. For truly "frameless"
1590 functions this might work too. */
1592 if (cache->saved_sp_reg != -1)
1594 /* We're halfway aligning the stack. */
1595 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
1596 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
1598 /* This will be added back below. */
1599 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
1601 else if (cache->pc != 0
1602 || target_read_memory (get_frame_pc (this_frame), buf, 1))
1604 /* We're in a known function, but did not find a frame
1605 setup. Assume that the function does not use %ebp.
1606 Alternatively, we may have jumped to an invalid
1607 address; in that case there is definitely no new
1609 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1610 cache->base = extract_unsigned_integer (buf, 4, byte_order)
1614 /* We're in an unknown function. We could not find the start
1615 of the function to analyze the prologue; our best option is
1616 to assume a typical frame layout with the caller's %ebp
1618 cache->saved_regs[I386_EBP_REGNUM] = 0;
1621 /* Now that we have the base address for the stack frame we can
1622 calculate the value of %esp in the calling frame. */
1623 if (cache->saved_sp == 0)
1624 cache->saved_sp = cache->base + 8;
1626 /* Adjust all the saved registers such that they contain addresses
1627 instead of offsets. */
1628 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1629 if (cache->saved_regs[i] != -1)
1630 cache->saved_regs[i] += cache->base;
1636 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
1637 struct frame_id *this_id)
1639 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1641 /* This marks the outermost frame. */
1642 if (cache->base == 0)
1645 /* See the end of i386_push_dummy_call. */
1646 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
1649 static struct value *
1650 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
1653 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1655 gdb_assert (regnum >= 0);
1657 /* The System V ABI says that:
1659 "The flags register contains the system flags, such as the
1660 direction flag and the carry flag. The direction flag must be
1661 set to the forward (that is, zero) direction before entry and
1662 upon exit from a function. Other user flags have no specified
1663 role in the standard calling sequence and are not preserved."
1665 To guarantee the "upon exit" part of that statement we fake a
1666 saved flags register that has its direction flag cleared.
1668 Note that GCC doesn't seem to rely on the fact that the direction
1669 flag is cleared after a function return; it always explicitly
1670 clears the flag before operations where it matters.
1672 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1673 right thing to do. The way we fake the flags register here makes
1674 it impossible to change it. */
1676 if (regnum == I386_EFLAGS_REGNUM)
1680 val = get_frame_register_unsigned (this_frame, regnum);
1682 return frame_unwind_got_constant (this_frame, regnum, val);
1685 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
1686 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
1688 if (regnum == I386_ESP_REGNUM && cache->saved_sp)
1689 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
1691 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
1692 return frame_unwind_got_memory (this_frame, regnum,
1693 cache->saved_regs[regnum]);
1695 return frame_unwind_got_register (this_frame, regnum, regnum);
1698 static const struct frame_unwind i386_frame_unwind =
1702 i386_frame_prev_register,
1704 default_frame_sniffer
1707 /* Normal frames, but in a function epilogue. */
1709 /* The epilogue is defined here as the 'ret' instruction, which will
1710 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1711 the function's stack frame. */
1714 i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1718 if (target_read_memory (pc, &insn, 1))
1719 return 0; /* Can't read memory at pc. */
1721 if (insn != 0xc3) /* 'ret' instruction. */
1728 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
1729 struct frame_info *this_frame,
1730 void **this_prologue_cache)
1732 if (frame_relative_level (this_frame) == 0)
1733 return i386_in_function_epilogue_p (get_frame_arch (this_frame),
1734 get_frame_pc (this_frame));
1739 static struct i386_frame_cache *
1740 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
1742 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1743 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1744 struct i386_frame_cache *cache;
1750 cache = i386_alloc_frame_cache ();
1751 *this_cache = cache;
1753 /* Cache base will be %esp plus cache->sp_offset (-4). */
1754 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1755 cache->base = extract_unsigned_integer (buf, 4,
1756 byte_order) + cache->sp_offset;
1758 /* Cache pc will be the frame func. */
1759 cache->pc = get_frame_pc (this_frame);
1761 /* The saved %esp will be at cache->base plus 8. */
1762 cache->saved_sp = cache->base + 8;
1764 /* The saved %eip will be at cache->base plus 4. */
1765 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
1771 i386_epilogue_frame_this_id (struct frame_info *this_frame,
1773 struct frame_id *this_id)
1775 struct i386_frame_cache *cache = i386_epilogue_frame_cache (this_frame,
1778 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
1781 static const struct frame_unwind i386_epilogue_frame_unwind =
1784 i386_epilogue_frame_this_id,
1785 i386_frame_prev_register,
1787 i386_epilogue_frame_sniffer
1791 /* Signal trampolines. */
1793 static struct i386_frame_cache *
1794 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
1796 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1797 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1798 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1799 struct i386_frame_cache *cache;
1806 cache = i386_alloc_frame_cache ();
1808 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1809 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
1811 addr = tdep->sigcontext_addr (this_frame);
1812 if (tdep->sc_reg_offset)
1816 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
1818 for (i = 0; i < tdep->sc_num_regs; i++)
1819 if (tdep->sc_reg_offset[i] != -1)
1820 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
1824 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
1825 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
1828 *this_cache = cache;
1833 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
1834 struct frame_id *this_id)
1836 struct i386_frame_cache *cache =
1837 i386_sigtramp_frame_cache (this_frame, this_cache);
1839 /* See the end of i386_push_dummy_call. */
1840 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
1843 static struct value *
1844 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
1845 void **this_cache, int regnum)
1847 /* Make sure we've initialized the cache. */
1848 i386_sigtramp_frame_cache (this_frame, this_cache);
1850 return i386_frame_prev_register (this_frame, this_cache, regnum);
1854 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
1855 struct frame_info *this_frame,
1856 void **this_prologue_cache)
1858 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
1860 /* We shouldn't even bother if we don't have a sigcontext_addr
1862 if (tdep->sigcontext_addr == NULL)
1865 if (tdep->sigtramp_p != NULL)
1867 if (tdep->sigtramp_p (this_frame))
1871 if (tdep->sigtramp_start != 0)
1873 CORE_ADDR pc = get_frame_pc (this_frame);
1875 gdb_assert (tdep->sigtramp_end != 0);
1876 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
1883 static const struct frame_unwind i386_sigtramp_frame_unwind =
1886 i386_sigtramp_frame_this_id,
1887 i386_sigtramp_frame_prev_register,
1889 i386_sigtramp_frame_sniffer
1894 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
1896 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1901 static const struct frame_base i386_frame_base =
1904 i386_frame_base_address,
1905 i386_frame_base_address,
1906 i386_frame_base_address
1909 static struct frame_id
1910 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1914 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
1916 /* See the end of i386_push_dummy_call. */
1917 return frame_id_build (fp + 8, get_frame_pc (this_frame));
1921 /* Figure out where the longjmp will land. Slurp the args out of the
1922 stack. We expect the first arg to be a pointer to the jmp_buf
1923 structure from which we extract the address that we will land at.
1924 This address is copied into PC. This routine returns non-zero on
1928 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1931 CORE_ADDR sp, jb_addr;
1932 struct gdbarch *gdbarch = get_frame_arch (frame);
1933 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1934 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
1936 /* If JB_PC_OFFSET is -1, we have no way to find out where the
1937 longjmp will land. */
1938 if (jb_pc_offset == -1)
1941 get_frame_register (frame, I386_ESP_REGNUM, buf);
1942 sp = extract_unsigned_integer (buf, 4, byte_order);
1943 if (target_read_memory (sp + 4, buf, 4))
1946 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
1947 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
1950 *pc = extract_unsigned_integer (buf, 4, byte_order);
1955 /* Check whether TYPE must be 16-byte-aligned when passed as a
1956 function argument. 16-byte vectors, _Decimal128 and structures or
1957 unions containing such types must be 16-byte-aligned; other
1958 arguments are 4-byte-aligned. */
1961 i386_16_byte_align_p (struct type *type)
1963 type = check_typedef (type);
1964 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
1965 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
1966 && TYPE_LENGTH (type) == 16)
1968 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
1969 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
1970 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1971 || TYPE_CODE (type) == TYPE_CODE_UNION)
1974 for (i = 0; i < TYPE_NFIELDS (type); i++)
1976 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
1984 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1985 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
1986 struct value **args, CORE_ADDR sp, int struct_return,
1987 CORE_ADDR struct_addr)
1989 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1995 /* Determine the total space required for arguments and struct
1996 return address in a first pass (allowing for 16-byte-aligned
1997 arguments), then push arguments in a second pass. */
1999 for (write_pass = 0; write_pass < 2; write_pass++)
2001 int args_space_used = 0;
2002 int have_16_byte_aligned_arg = 0;
2008 /* Push value address. */
2009 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2010 write_memory (sp, buf, 4);
2011 args_space_used += 4;
2017 for (i = 0; i < nargs; i++)
2019 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2023 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2024 args_space_used = align_up (args_space_used, 16);
2026 write_memory (sp + args_space_used,
2027 value_contents_all (args[i]), len);
2028 /* The System V ABI says that:
2030 "An argument's size is increased, if necessary, to make it a
2031 multiple of [32-bit] words. This may require tail padding,
2032 depending on the size of the argument."
2034 This makes sure the stack stays word-aligned. */
2035 args_space_used += align_up (len, 4);
2039 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2041 args_space = align_up (args_space, 16);
2042 have_16_byte_aligned_arg = 1;
2044 args_space += align_up (len, 4);
2050 if (have_16_byte_aligned_arg)
2051 args_space = align_up (args_space, 16);
2056 /* Store return address. */
2058 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2059 write_memory (sp, buf, 4);
2061 /* Finally, update the stack pointer... */
2062 store_unsigned_integer (buf, 4, byte_order, sp);
2063 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
2065 /* ...and fake a frame pointer. */
2066 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
2068 /* MarkK wrote: This "+ 8" is all over the place:
2069 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2070 i386_dummy_id). It's there, since all frame unwinders for
2071 a given target have to agree (within a certain margin) on the
2072 definition of the stack address of a frame. Otherwise frame id
2073 comparison might not work correctly. Since DWARF2/GCC uses the
2074 stack address *before* the function call as a frame's CFA. On
2075 the i386, when %ebp is used as a frame pointer, the offset
2076 between the contents %ebp and the CFA as defined by GCC. */
2080 /* These registers are used for returning integers (and on some
2081 targets also for returning `struct' and `union' values when their
2082 size and alignment match an integer type). */
2083 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2084 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2086 /* Read, for architecture GDBARCH, a function return value of TYPE
2087 from REGCACHE, and copy that into VALBUF. */
2090 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2091 struct regcache *regcache, gdb_byte *valbuf)
2093 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2094 int len = TYPE_LENGTH (type);
2095 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2097 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2099 if (tdep->st0_regnum < 0)
2101 warning (_("Cannot find floating-point return value."));
2102 memset (valbuf, 0, len);
2106 /* Floating-point return values can be found in %st(0). Convert
2107 its contents to the desired type. This is probably not
2108 exactly how it would happen on the target itself, but it is
2109 the best we can do. */
2110 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2111 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
2115 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2116 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2118 if (len <= low_size)
2120 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2121 memcpy (valbuf, buf, len);
2123 else if (len <= (low_size + high_size))
2125 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2126 memcpy (valbuf, buf, low_size);
2127 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2128 memcpy (valbuf + low_size, buf, len - low_size);
2131 internal_error (__FILE__, __LINE__,
2132 _("Cannot extract return value of %d bytes long."), len);
2136 /* Write, for architecture GDBARCH, a function return value of TYPE
2137 from VALBUF into REGCACHE. */
2140 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2141 struct regcache *regcache, const gdb_byte *valbuf)
2143 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2144 int len = TYPE_LENGTH (type);
2146 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2149 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2151 if (tdep->st0_regnum < 0)
2153 warning (_("Cannot set floating-point return value."));
2157 /* Returning floating-point values is a bit tricky. Apart from
2158 storing the return value in %st(0), we have to simulate the
2159 state of the FPU at function return point. */
2161 /* Convert the value found in VALBUF to the extended
2162 floating-point format used by the FPU. This is probably
2163 not exactly how it would happen on the target itself, but
2164 it is the best we can do. */
2165 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
2166 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2168 /* Set the top of the floating-point register stack to 7. The
2169 actual value doesn't really matter, but 7 is what a normal
2170 function return would end up with if the program started out
2171 with a freshly initialized FPU. */
2172 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2174 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2176 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2177 the floating-point register stack to 7, the appropriate value
2178 for the tag word is 0x3fff. */
2179 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2183 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2184 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2186 if (len <= low_size)
2187 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2188 else if (len <= (low_size + high_size))
2190 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2191 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
2192 len - low_size, valbuf + low_size);
2195 internal_error (__FILE__, __LINE__,
2196 _("Cannot store return value of %d bytes long."), len);
2201 /* This is the variable that is set with "set struct-convention", and
2202 its legitimate values. */
2203 static const char default_struct_convention[] = "default";
2204 static const char pcc_struct_convention[] = "pcc";
2205 static const char reg_struct_convention[] = "reg";
2206 static const char *valid_conventions[] =
2208 default_struct_convention,
2209 pcc_struct_convention,
2210 reg_struct_convention,
2213 static const char *struct_convention = default_struct_convention;
2215 /* Return non-zero if TYPE, which is assumed to be a structure,
2216 a union type, or an array type, should be returned in registers
2217 for architecture GDBARCH. */
2220 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2222 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2223 enum type_code code = TYPE_CODE (type);
2224 int len = TYPE_LENGTH (type);
2226 gdb_assert (code == TYPE_CODE_STRUCT
2227 || code == TYPE_CODE_UNION
2228 || code == TYPE_CODE_ARRAY);
2230 if (struct_convention == pcc_struct_convention
2231 || (struct_convention == default_struct_convention
2232 && tdep->struct_return == pcc_struct_return))
2235 /* Structures consisting of a single `float', `double' or 'long
2236 double' member are returned in %st(0). */
2237 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2239 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2240 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2241 return (len == 4 || len == 8 || len == 12);
2244 return (len == 1 || len == 2 || len == 4 || len == 8);
2247 /* Determine, for architecture GDBARCH, how a return value of TYPE
2248 should be returned. If it is supposed to be returned in registers,
2249 and READBUF is non-zero, read the appropriate value from REGCACHE,
2250 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2251 from WRITEBUF into REGCACHE. */
2253 static enum return_value_convention
2254 i386_return_value (struct gdbarch *gdbarch, struct type *func_type,
2255 struct type *type, struct regcache *regcache,
2256 gdb_byte *readbuf, const gdb_byte *writebuf)
2258 enum type_code code = TYPE_CODE (type);
2260 if (((code == TYPE_CODE_STRUCT
2261 || code == TYPE_CODE_UNION
2262 || code == TYPE_CODE_ARRAY)
2263 && !i386_reg_struct_return_p (gdbarch, type))
2264 /* 128-bit decimal float uses the struct return convention. */
2265 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2267 /* The System V ABI says that:
2269 "A function that returns a structure or union also sets %eax
2270 to the value of the original address of the caller's area
2271 before it returns. Thus when the caller receives control
2272 again, the address of the returned object resides in register
2273 %eax and can be used to access the object."
2275 So the ABI guarantees that we can always find the return
2276 value just after the function has returned. */
2278 /* Note that the ABI doesn't mention functions returning arrays,
2279 which is something possible in certain languages such as Ada.
2280 In this case, the value is returned as if it was wrapped in
2281 a record, so the convention applied to records also applies
2288 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2289 read_memory (addr, readbuf, TYPE_LENGTH (type));
2292 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2295 /* This special case is for structures consisting of a single
2296 `float', `double' or 'long double' member. These structures are
2297 returned in %st(0). For these structures, we call ourselves
2298 recursively, changing TYPE into the type of the first member of
2299 the structure. Since that should work for all structures that
2300 have only one member, we don't bother to check the member's type
2302 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2304 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2305 return i386_return_value (gdbarch, func_type, type, regcache,
2310 i386_extract_return_value (gdbarch, type, regcache, readbuf);
2312 i386_store_return_value (gdbarch, type, regcache, writebuf);
2314 return RETURN_VALUE_REGISTER_CONVENTION;
2319 i387_ext_type (struct gdbarch *gdbarch)
2321 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2323 if (!tdep->i387_ext_type)
2325 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
2326 gdb_assert (tdep->i387_ext_type != NULL);
2329 return tdep->i387_ext_type;
2332 /* Construct vector type for pseudo YMM registers. We can't use
2333 tdesc_find_type since YMM isn't described in target description. */
2335 static struct type *
2336 i386_ymm_type (struct gdbarch *gdbarch)
2338 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2340 if (!tdep->i386_ymm_type)
2342 const struct builtin_type *bt = builtin_type (gdbarch);
2344 /* The type we're building is this: */
2346 union __gdb_builtin_type_vec256i
2348 int128_t uint128[2];
2349 int64_t v2_int64[4];
2350 int32_t v4_int32[8];
2351 int16_t v8_int16[16];
2352 int8_t v16_int8[32];
2353 double v2_double[4];
2360 t = arch_composite_type (gdbarch,
2361 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
2362 append_composite_type_field (t, "v8_float",
2363 init_vector_type (bt->builtin_float, 8));
2364 append_composite_type_field (t, "v4_double",
2365 init_vector_type (bt->builtin_double, 4));
2366 append_composite_type_field (t, "v32_int8",
2367 init_vector_type (bt->builtin_int8, 32));
2368 append_composite_type_field (t, "v16_int16",
2369 init_vector_type (bt->builtin_int16, 16));
2370 append_composite_type_field (t, "v8_int32",
2371 init_vector_type (bt->builtin_int32, 8));
2372 append_composite_type_field (t, "v4_int64",
2373 init_vector_type (bt->builtin_int64, 4));
2374 append_composite_type_field (t, "v2_int128",
2375 init_vector_type (bt->builtin_int128, 2));
2377 TYPE_VECTOR (t) = 1;
2378 TYPE_NAME (t) = "builtin_type_vec128i";
2379 tdep->i386_ymm_type = t;
2382 return tdep->i386_ymm_type;
2385 /* Construct vector type for MMX registers. */
2386 static struct type *
2387 i386_mmx_type (struct gdbarch *gdbarch)
2389 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2391 if (!tdep->i386_mmx_type)
2393 const struct builtin_type *bt = builtin_type (gdbarch);
2395 /* The type we're building is this: */
2397 union __gdb_builtin_type_vec64i
2400 int32_t v2_int32[2];
2401 int16_t v4_int16[4];
2408 t = arch_composite_type (gdbarch,
2409 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
2411 append_composite_type_field (t, "uint64", bt->builtin_int64);
2412 append_composite_type_field (t, "v2_int32",
2413 init_vector_type (bt->builtin_int32, 2));
2414 append_composite_type_field (t, "v4_int16",
2415 init_vector_type (bt->builtin_int16, 4));
2416 append_composite_type_field (t, "v8_int8",
2417 init_vector_type (bt->builtin_int8, 8));
2419 TYPE_VECTOR (t) = 1;
2420 TYPE_NAME (t) = "builtin_type_vec64i";
2421 tdep->i386_mmx_type = t;
2424 return tdep->i386_mmx_type;
2427 /* Return the GDB type object for the "standard" data type of data in
2430 static struct type *
2431 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2433 if (i386_mmx_regnum_p (gdbarch, regnum))
2434 return i386_mmx_type (gdbarch);
2435 else if (i386_ymm_regnum_p (gdbarch, regnum))
2436 return i386_ymm_type (gdbarch);
2439 const struct builtin_type *bt = builtin_type (gdbarch);
2440 if (i386_byte_regnum_p (gdbarch, regnum))
2441 return bt->builtin_int8;
2442 else if (i386_word_regnum_p (gdbarch, regnum))
2443 return bt->builtin_int16;
2444 else if (i386_dword_regnum_p (gdbarch, regnum))
2445 return bt->builtin_int32;
2448 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2451 /* Map a cooked register onto a raw register or memory. For the i386,
2452 the MMX registers need to be mapped onto floating point registers. */
2455 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
2457 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
2462 mmxreg = regnum - tdep->mm0_regnum;
2463 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2464 tos = (fstat >> 11) & 0x7;
2465 fpreg = (mmxreg + tos) % 8;
2467 return (I387_ST0_REGNUM (tdep) + fpreg);
2471 i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2472 int regnum, gdb_byte *buf)
2474 gdb_byte raw_buf[MAX_REGISTER_SIZE];
2476 if (i386_mmx_regnum_p (gdbarch, regnum))
2478 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2480 /* Extract (always little endian). */
2481 regcache_raw_read (regcache, fpnum, raw_buf);
2482 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
2486 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2488 if (i386_ymm_regnum_p (gdbarch, regnum))
2490 regnum -= tdep->ymm0_regnum;
2492 /* Extract (always little endian). Read lower 128bits. */
2493 regcache_raw_read (regcache,
2494 I387_XMM0_REGNUM (tdep) + regnum,
2496 memcpy (buf, raw_buf, 16);
2497 /* Read upper 128bits. */
2498 regcache_raw_read (regcache,
2499 tdep->ymm0h_regnum + regnum,
2501 memcpy (buf + 16, raw_buf, 16);
2503 else if (i386_word_regnum_p (gdbarch, regnum))
2505 int gpnum = regnum - tdep->ax_regnum;
2507 /* Extract (always little endian). */
2508 regcache_raw_read (regcache, gpnum, raw_buf);
2509 memcpy (buf, raw_buf, 2);
2511 else if (i386_byte_regnum_p (gdbarch, regnum))
2513 /* Check byte pseudo registers last since this function will
2514 be called from amd64_pseudo_register_read, which handles
2515 byte pseudo registers differently. */
2516 int gpnum = regnum - tdep->al_regnum;
2518 /* Extract (always little endian). We read both lower and
2520 regcache_raw_read (regcache, gpnum % 4, raw_buf);
2522 memcpy (buf, raw_buf + 1, 1);
2524 memcpy (buf, raw_buf, 1);
2527 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2532 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2533 int regnum, const gdb_byte *buf)
2535 gdb_byte raw_buf[MAX_REGISTER_SIZE];
2537 if (i386_mmx_regnum_p (gdbarch, regnum))
2539 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2542 regcache_raw_read (regcache, fpnum, raw_buf);
2543 /* ... Modify ... (always little endian). */
2544 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
2546 regcache_raw_write (regcache, fpnum, raw_buf);
2550 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2552 if (i386_ymm_regnum_p (gdbarch, regnum))
2554 regnum -= tdep->ymm0_regnum;
2556 /* ... Write lower 128bits. */
2557 regcache_raw_write (regcache,
2558 I387_XMM0_REGNUM (tdep) + regnum,
2560 /* ... Write upper 128bits. */
2561 regcache_raw_write (regcache,
2562 tdep->ymm0h_regnum + regnum,
2565 else if (i386_word_regnum_p (gdbarch, regnum))
2567 int gpnum = regnum - tdep->ax_regnum;
2570 regcache_raw_read (regcache, gpnum, raw_buf);
2571 /* ... Modify ... (always little endian). */
2572 memcpy (raw_buf, buf, 2);
2574 regcache_raw_write (regcache, gpnum, raw_buf);
2576 else if (i386_byte_regnum_p (gdbarch, regnum))
2578 /* Check byte pseudo registers last since this function will
2579 be called from amd64_pseudo_register_read, which handles
2580 byte pseudo registers differently. */
2581 int gpnum = regnum - tdep->al_regnum;
2583 /* Read ... We read both lower and upper registers. */
2584 regcache_raw_read (regcache, gpnum % 4, raw_buf);
2585 /* ... Modify ... (always little endian). */
2587 memcpy (raw_buf + 1, buf, 1);
2589 memcpy (raw_buf, buf, 1);
2591 regcache_raw_write (regcache, gpnum % 4, raw_buf);
2594 internal_error (__FILE__, __LINE__, _("invalid regnum"));
2599 /* Return the register number of the register allocated by GCC after
2600 REGNUM, or -1 if there is no such register. */
2603 i386_next_regnum (int regnum)
2605 /* GCC allocates the registers in the order:
2607 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2609 Since storing a variable in %esp doesn't make any sense we return
2610 -1 for %ebp and for %esp itself. */
2611 static int next_regnum[] =
2613 I386_EDX_REGNUM, /* Slot for %eax. */
2614 I386_EBX_REGNUM, /* Slot for %ecx. */
2615 I386_ECX_REGNUM, /* Slot for %edx. */
2616 I386_ESI_REGNUM, /* Slot for %ebx. */
2617 -1, -1, /* Slots for %esp and %ebp. */
2618 I386_EDI_REGNUM, /* Slot for %esi. */
2619 I386_EBP_REGNUM /* Slot for %edi. */
2622 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
2623 return next_regnum[regnum];
2628 /* Return nonzero if a value of type TYPE stored in register REGNUM
2629 needs any special handling. */
2632 i386_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type)
2634 int len = TYPE_LENGTH (type);
2636 /* Values may be spread across multiple registers. Most debugging
2637 formats aren't expressive enough to specify the locations, so
2638 some heuristics is involved. Right now we only handle types that
2639 have a length that is a multiple of the word size, since GCC
2640 doesn't seem to put any other types into registers. */
2641 if (len > 4 && len % 4 == 0)
2643 int last_regnum = regnum;
2647 last_regnum = i386_next_regnum (last_regnum);
2651 if (last_regnum != -1)
2655 return i387_convert_register_p (gdbarch, regnum, type);
2658 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2659 return its contents in TO. */
2662 i386_register_to_value (struct frame_info *frame, int regnum,
2663 struct type *type, gdb_byte *to)
2665 struct gdbarch *gdbarch = get_frame_arch (frame);
2666 int len = TYPE_LENGTH (type);
2668 /* FIXME: kettenis/20030609: What should we do if REGNUM isn't
2669 available in FRAME (i.e. if it wasn't saved)? */
2671 if (i386_fp_regnum_p (gdbarch, regnum))
2673 i387_register_to_value (frame, regnum, type, to);
2677 /* Read a value spread across multiple registers. */
2679 gdb_assert (len > 4 && len % 4 == 0);
2683 gdb_assert (regnum != -1);
2684 gdb_assert (register_size (gdbarch, regnum) == 4);
2686 get_frame_register (frame, regnum, to);
2687 regnum = i386_next_regnum (regnum);
2693 /* Write the contents FROM of a value of type TYPE into register
2694 REGNUM in frame FRAME. */
2697 i386_value_to_register (struct frame_info *frame, int regnum,
2698 struct type *type, const gdb_byte *from)
2700 int len = TYPE_LENGTH (type);
2702 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
2704 i387_value_to_register (frame, regnum, type, from);
2708 /* Write a value spread across multiple registers. */
2710 gdb_assert (len > 4 && len % 4 == 0);
2714 gdb_assert (regnum != -1);
2715 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
2717 put_frame_register (frame, regnum, from);
2718 regnum = i386_next_regnum (regnum);
2724 /* Supply register REGNUM from the buffer specified by GREGS and LEN
2725 in the general-purpose register set REGSET to register cache
2726 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2729 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
2730 int regnum, const void *gregs, size_t len)
2732 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2733 const gdb_byte *regs = gregs;
2736 gdb_assert (len == tdep->sizeof_gregset);
2738 for (i = 0; i < tdep->gregset_num_regs; i++)
2740 if ((regnum == i || regnum == -1)
2741 && tdep->gregset_reg_offset[i] != -1)
2742 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
2746 /* Collect register REGNUM from the register cache REGCACHE and store
2747 it in the buffer specified by GREGS and LEN as described by the
2748 general-purpose register set REGSET. If REGNUM is -1, do this for
2749 all registers in REGSET. */
2752 i386_collect_gregset (const struct regset *regset,
2753 const struct regcache *regcache,
2754 int regnum, void *gregs, size_t len)
2756 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2757 gdb_byte *regs = gregs;
2760 gdb_assert (len == tdep->sizeof_gregset);
2762 for (i = 0; i < tdep->gregset_num_regs; i++)
2764 if ((regnum == i || regnum == -1)
2765 && tdep->gregset_reg_offset[i] != -1)
2766 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
2770 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2771 in the floating-point register set REGSET to register cache
2772 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2775 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
2776 int regnum, const void *fpregs, size_t len)
2778 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2780 if (len == I387_SIZEOF_FXSAVE)
2782 i387_supply_fxsave (regcache, regnum, fpregs);
2786 gdb_assert (len == tdep->sizeof_fpregset);
2787 i387_supply_fsave (regcache, regnum, fpregs);
2790 /* Collect register REGNUM from the register cache REGCACHE and store
2791 it in the buffer specified by FPREGS and LEN as described by the
2792 floating-point register set REGSET. If REGNUM is -1, do this for
2793 all registers in REGSET. */
2796 i386_collect_fpregset (const struct regset *regset,
2797 const struct regcache *regcache,
2798 int regnum, void *fpregs, size_t len)
2800 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2802 if (len == I387_SIZEOF_FXSAVE)
2804 i387_collect_fxsave (regcache, regnum, fpregs);
2808 gdb_assert (len == tdep->sizeof_fpregset);
2809 i387_collect_fsave (regcache, regnum, fpregs);
2812 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
2815 i386_supply_xstateregset (const struct regset *regset,
2816 struct regcache *regcache, int regnum,
2817 const void *xstateregs, size_t len)
2819 i387_supply_xsave (regcache, regnum, xstateregs);
2822 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
2825 i386_collect_xstateregset (const struct regset *regset,
2826 const struct regcache *regcache,
2827 int regnum, void *xstateregs, size_t len)
2829 i387_collect_xsave (regcache, regnum, xstateregs, 1);
2832 /* Return the appropriate register set for the core section identified
2833 by SECT_NAME and SECT_SIZE. */
2835 const struct regset *
2836 i386_regset_from_core_section (struct gdbarch *gdbarch,
2837 const char *sect_name, size_t sect_size)
2839 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2841 if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset)
2843 if (tdep->gregset == NULL)
2844 tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset,
2845 i386_collect_gregset);
2846 return tdep->gregset;
2849 if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
2850 || (strcmp (sect_name, ".reg-xfp") == 0
2851 && sect_size == I387_SIZEOF_FXSAVE))
2853 if (tdep->fpregset == NULL)
2854 tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset,
2855 i386_collect_fpregset);
2856 return tdep->fpregset;
2859 if (strcmp (sect_name, ".reg-xstate") == 0)
2861 if (tdep->xstateregset == NULL)
2862 tdep->xstateregset = regset_alloc (gdbarch,
2863 i386_supply_xstateregset,
2864 i386_collect_xstateregset);
2866 return tdep->xstateregset;
2873 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
2876 i386_pe_skip_trampoline_code (struct frame_info *frame,
2877 CORE_ADDR pc, char *name)
2879 struct gdbarch *gdbarch = get_frame_arch (frame);
2880 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2883 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
2885 unsigned long indirect =
2886 read_memory_unsigned_integer (pc + 2, 4, byte_order);
2887 struct minimal_symbol *indsym =
2888 indirect ? lookup_minimal_symbol_by_pc (indirect) : 0;
2889 char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0;
2893 if (strncmp (symname, "__imp_", 6) == 0
2894 || strncmp (symname, "_imp_", 5) == 0)
2896 read_memory_unsigned_integer (indirect, 4, byte_order);
2899 return 0; /* Not a trampoline. */
2903 /* Return whether the THIS_FRAME corresponds to a sigtramp
2907 i386_sigtramp_p (struct frame_info *this_frame)
2909 CORE_ADDR pc = get_frame_pc (this_frame);
2912 find_pc_partial_function (pc, &name, NULL, NULL);
2913 return (name && strcmp ("_sigtramp", name) == 0);
2917 /* We have two flavours of disassembly. The machinery on this page
2918 deals with switching between those. */
2921 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
2923 gdb_assert (disassembly_flavor == att_flavor
2924 || disassembly_flavor == intel_flavor);
2926 /* FIXME: kettenis/20020915: Until disassembler_options is properly
2927 constified, cast to prevent a compiler warning. */
2928 info->disassembler_options = (char *) disassembly_flavor;
2930 return print_insn_i386 (pc, info);
2934 /* There are a few i386 architecture variants that differ only
2935 slightly from the generic i386 target. For now, we don't give them
2936 their own source file, but include them here. As a consequence,
2937 they'll always be included. */
2939 /* System V Release 4 (SVR4). */
2941 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
2945 i386_svr4_sigtramp_p (struct frame_info *this_frame)
2947 CORE_ADDR pc = get_frame_pc (this_frame);
2950 /* UnixWare uses _sigacthandler. The origin of the other symbols is
2951 currently unknown. */
2952 find_pc_partial_function (pc, &name, NULL, NULL);
2953 return (name && (strcmp ("_sigreturn", name) == 0
2954 || strcmp ("_sigacthandler", name) == 0
2955 || strcmp ("sigvechandler", name) == 0));
2958 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
2959 address of the associated sigcontext (ucontext) structure. */
2962 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
2964 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2965 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2969 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2970 sp = extract_unsigned_integer (buf, 4, byte_order);
2972 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
2979 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2981 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
2982 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
2985 /* System V Release 4 (SVR4). */
2988 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2990 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2992 /* System V Release 4 uses ELF. */
2993 i386_elf_init_abi (info, gdbarch);
2995 /* System V Release 4 has shared libraries. */
2996 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
2998 tdep->sigtramp_p = i386_svr4_sigtramp_p;
2999 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
3000 tdep->sc_pc_offset = 36 + 14 * 4;
3001 tdep->sc_sp_offset = 36 + 17 * 4;
3003 tdep->jb_pc_offset = 20;
3009 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3011 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3013 /* DJGPP doesn't have any special frames for signal handlers. */
3014 tdep->sigtramp_p = NULL;
3016 tdep->jb_pc_offset = 36;
3018 /* DJGPP does not support the SSE registers. */
3019 if (! tdesc_has_registers (info.target_desc))
3020 tdep->tdesc = tdesc_i386_mmx;
3022 /* Native compiler is GCC, which uses the SVR4 register numbering
3023 even in COFF and STABS. See the comment in i386_gdbarch_init,
3024 before the calls to set_gdbarch_stab_reg_to_regnum and
3025 set_gdbarch_sdb_reg_to_regnum. */
3026 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3027 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
3029 set_gdbarch_has_dos_based_file_system (gdbarch, 1);
3033 /* i386 register groups. In addition to the normal groups, add "mmx"
3036 static struct reggroup *i386_sse_reggroup;
3037 static struct reggroup *i386_mmx_reggroup;
3040 i386_init_reggroups (void)
3042 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
3043 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
3047 i386_add_reggroups (struct gdbarch *gdbarch)
3049 reggroup_add (gdbarch, i386_sse_reggroup);
3050 reggroup_add (gdbarch, i386_mmx_reggroup);
3051 reggroup_add (gdbarch, general_reggroup);
3052 reggroup_add (gdbarch, float_reggroup);
3053 reggroup_add (gdbarch, all_reggroup);
3054 reggroup_add (gdbarch, save_reggroup);
3055 reggroup_add (gdbarch, restore_reggroup);
3056 reggroup_add (gdbarch, vector_reggroup);
3057 reggroup_add (gdbarch, system_reggroup);
3061 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
3062 struct reggroup *group)
3064 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3065 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
3066 ymm_regnum_p, ymmh_regnum_p;
3068 /* Don't include pseudo registers, except for MMX, in any register
3070 if (i386_byte_regnum_p (gdbarch, regnum))
3073 if (i386_word_regnum_p (gdbarch, regnum))
3076 if (i386_dword_regnum_p (gdbarch, regnum))
3079 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
3080 if (group == i386_mmx_reggroup)
3081 return mmx_regnum_p;
3083 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
3084 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
3085 if (group == i386_sse_reggroup)
3086 return xmm_regnum_p || mxcsr_regnum_p;
3088 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
3089 if (group == vector_reggroup)
3090 return (mmx_regnum_p
3094 && ((tdep->xcr0 & I386_XSTATE_AVX_MASK)
3095 == I386_XSTATE_SSE_MASK)));
3097 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
3098 || i386_fpc_regnum_p (gdbarch, regnum));
3099 if (group == float_reggroup)
3102 /* For "info reg all", don't include upper YMM registers nor XMM
3103 registers when AVX is supported. */
3104 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
3105 if (group == all_reggroup
3107 && (tdep->xcr0 & I386_XSTATE_AVX))
3111 if (group == general_reggroup)
3112 return (!fp_regnum_p
3119 return default_register_reggroup_p (gdbarch, regnum, group);
3123 /* Get the ARGIth function argument for the current function. */
3126 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
3129 struct gdbarch *gdbarch = get_frame_arch (frame);
3130 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3131 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
3132 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
3136 i386_skip_permanent_breakpoint (struct regcache *regcache)
3138 CORE_ADDR current_pc = regcache_read_pc (regcache);
3140 /* On i386, breakpoint is exactly 1 byte long, so we just
3141 adjust the PC in the regcache. */
3143 regcache_write_pc (regcache, current_pc);
3147 #define PREFIX_REPZ 0x01
3148 #define PREFIX_REPNZ 0x02
3149 #define PREFIX_LOCK 0x04
3150 #define PREFIX_DATA 0x08
3151 #define PREFIX_ADDR 0x10
3163 /* i386 arith/logic operations */
3176 struct i386_record_s
3178 struct gdbarch *gdbarch;
3179 struct regcache *regcache;
3180 CORE_ADDR orig_addr;
3186 uint8_t mod, reg, rm;
3195 /* Parse "modrm" part in current memory address that irp->addr point to
3196 Return -1 if something wrong. */
3199 i386_record_modrm (struct i386_record_s *irp)
3201 struct gdbarch *gdbarch = irp->gdbarch;
3203 if (target_read_memory (irp->addr, &irp->modrm, 1))
3206 printf_unfiltered (_("Process record: error reading memory at "
3207 "addr %s len = 1.\n"),
3208 paddress (gdbarch, irp->addr));
3212 irp->mod = (irp->modrm >> 6) & 3;
3213 irp->reg = (irp->modrm >> 3) & 7;
3214 irp->rm = irp->modrm & 7;
3219 /* Get the memory address that current instruction write to and set it to
3220 the argument "addr".
3221 Return -1 if something wrong. */
3224 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
3226 struct gdbarch *gdbarch = irp->gdbarch;
3227 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3239 uint8_t base = irp->rm;
3244 if (target_read_memory (irp->addr, &byte, 1))
3247 printf_unfiltered (_("Process record: error reading memory "
3248 "at addr %s len = 1.\n"),
3249 paddress (gdbarch, irp->addr));
3253 scale = (byte >> 6) & 3;
3254 index = ((byte >> 3) & 7) | irp->rex_x;
3262 if ((base & 7) == 5)
3265 if (target_read_memory (irp->addr, buf, 4))
3268 printf_unfiltered (_("Process record: error reading "
3269 "memory at addr %s len = 4.\n"),
3270 paddress (gdbarch, irp->addr));
3274 *addr = extract_signed_integer (buf, 4, byte_order);
3275 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
3276 *addr += irp->addr + irp->rip_offset;
3280 if (target_read_memory (irp->addr, buf, 1))
3283 printf_unfiltered (_("Process record: error reading memory "
3284 "at addr %s len = 1.\n"),
3285 paddress (gdbarch, irp->addr));
3289 *addr = (int8_t) buf[0];
3292 if (target_read_memory (irp->addr, buf, 4))
3295 printf_unfiltered (_("Process record: error reading memory "
3296 "at addr %s len = 4.\n"),
3297 paddress (gdbarch, irp->addr));
3300 *addr = extract_signed_integer (buf, 4, byte_order);
3308 if (base == 4 && irp->popl_esp_hack)
3309 *addr += irp->popl_esp_hack;
3310 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
3313 if (irp->aflag == 2)
3318 *addr = (uint32_t) (offset64 + *addr);
3320 if (havesib && (index != 4 || scale != 0))
3322 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
3324 if (irp->aflag == 2)
3325 *addr += offset64 << scale;
3327 *addr = (uint32_t) (*addr + (offset64 << scale));
3338 if (target_read_memory (irp->addr, buf, 2))
3341 printf_unfiltered (_("Process record: error reading "
3342 "memory at addr %s len = 2.\n"),
3343 paddress (gdbarch, irp->addr));
3347 *addr = extract_signed_integer (buf, 2, byte_order);
3353 if (target_read_memory (irp->addr, buf, 1))
3356 printf_unfiltered (_("Process record: error reading memory "
3357 "at addr %s len = 1.\n"),
3358 paddress (gdbarch, irp->addr));
3362 *addr = (int8_t) buf[0];
3365 if (target_read_memory (irp->addr, buf, 2))
3368 printf_unfiltered (_("Process record: error reading memory "
3369 "at addr %s len = 2.\n"),
3370 paddress (gdbarch, irp->addr));
3374 *addr = extract_signed_integer (buf, 2, byte_order);
3381 regcache_raw_read_unsigned (irp->regcache,
3382 irp->regmap[X86_RECORD_REBX_REGNUM],
3384 *addr = (uint32_t) (*addr + offset64);
3385 regcache_raw_read_unsigned (irp->regcache,
3386 irp->regmap[X86_RECORD_RESI_REGNUM],
3388 *addr = (uint32_t) (*addr + offset64);
3391 regcache_raw_read_unsigned (irp->regcache,
3392 irp->regmap[X86_RECORD_REBX_REGNUM],
3394 *addr = (uint32_t) (*addr + offset64);
3395 regcache_raw_read_unsigned (irp->regcache,
3396 irp->regmap[X86_RECORD_REDI_REGNUM],
3398 *addr = (uint32_t) (*addr + offset64);
3401 regcache_raw_read_unsigned (irp->regcache,
3402 irp->regmap[X86_RECORD_REBP_REGNUM],
3404 *addr = (uint32_t) (*addr + offset64);
3405 regcache_raw_read_unsigned (irp->regcache,
3406 irp->regmap[X86_RECORD_RESI_REGNUM],
3408 *addr = (uint32_t) (*addr + offset64);
3411 regcache_raw_read_unsigned (irp->regcache,
3412 irp->regmap[X86_RECORD_REBP_REGNUM],
3414 *addr = (uint32_t) (*addr + offset64);
3415 regcache_raw_read_unsigned (irp->regcache,
3416 irp->regmap[X86_RECORD_REDI_REGNUM],
3418 *addr = (uint32_t) (*addr + offset64);
3421 regcache_raw_read_unsigned (irp->regcache,
3422 irp->regmap[X86_RECORD_RESI_REGNUM],
3424 *addr = (uint32_t) (*addr + offset64);
3427 regcache_raw_read_unsigned (irp->regcache,
3428 irp->regmap[X86_RECORD_REDI_REGNUM],
3430 *addr = (uint32_t) (*addr + offset64);
3433 regcache_raw_read_unsigned (irp->regcache,
3434 irp->regmap[X86_RECORD_REBP_REGNUM],
3436 *addr = (uint32_t) (*addr + offset64);
3439 regcache_raw_read_unsigned (irp->regcache,
3440 irp->regmap[X86_RECORD_REBX_REGNUM],
3442 *addr = (uint32_t) (*addr + offset64);
3452 /* Record the value of the memory that willbe changed in current instruction
3453 to "record_arch_list".
3454 Return -1 if something wrong. */
3457 i386_record_lea_modrm (struct i386_record_s *irp)
3459 struct gdbarch *gdbarch = irp->gdbarch;
3462 if (irp->override >= 0)
3464 warning (_("Process record ignores the memory change "
3465 "of instruction at address %s because it "
3466 "can't get the value of the segment register."),
3467 paddress (gdbarch, irp->orig_addr));
3471 if (i386_record_lea_modrm_addr (irp, &addr))
3474 if (record_arch_list_add_mem (addr, 1 << irp->ot))
3480 /* Record the push operation to "record_arch_list".
3481 Return -1 if something wrong. */
3484 i386_record_push (struct i386_record_s *irp, int size)
3488 if (record_arch_list_add_reg (irp->regcache,
3489 irp->regmap[X86_RECORD_RESP_REGNUM]))
3491 regcache_raw_read_unsigned (irp->regcache,
3492 irp->regmap[X86_RECORD_RESP_REGNUM],
3494 if (record_arch_list_add_mem ((CORE_ADDR) addr - size, size))
3501 /* Defines contents to record. */
3502 #define I386_SAVE_FPU_REGS 0xfffd
3503 #define I386_SAVE_FPU_ENV 0xfffe
3504 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3506 /* Record the value of floating point registers which will be changed by the
3507 current instruction to "record_arch_list". Return -1 if something is wrong.
3510 static int i386_record_floats (struct gdbarch *gdbarch,
3511 struct i386_record_s *ir,
3514 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3517 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3518 happen. Currently we store st0-st7 registers, but we need not store all
3519 registers all the time, in future we use ftag register and record only
3520 those who are not marked as an empty. */
3522 if (I386_SAVE_FPU_REGS == iregnum)
3524 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
3526 if (record_arch_list_add_reg (ir->regcache, i))
3530 else if (I386_SAVE_FPU_ENV == iregnum)
3532 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3534 if (record_arch_list_add_reg (ir->regcache, i))
3538 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
3540 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3542 if (record_arch_list_add_reg (ir->regcache, i))
3546 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
3547 (iregnum <= I387_FOP_REGNUM (tdep)))
3549 if (record_arch_list_add_reg (ir->regcache,iregnum))
3554 /* Parameter error. */
3557 if(I386_SAVE_FPU_ENV != iregnum)
3559 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
3561 if (record_arch_list_add_reg (ir->regcache, i))
3568 /* Parse the current instruction and record the values of the registers and
3569 memory that will be changed in current instruction to "record_arch_list".
3570 Return -1 if something wrong. */
3572 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3573 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3576 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
3577 CORE_ADDR input_addr)
3579 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3585 gdb_byte buf[MAX_REGISTER_SIZE];
3586 struct i386_record_s ir;
3587 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3592 memset (&ir, 0, sizeof (struct i386_record_s));
3593 ir.regcache = regcache;
3594 ir.addr = input_addr;
3595 ir.orig_addr = input_addr;
3599 ir.popl_esp_hack = 0;
3600 ir.regmap = tdep->record_regmap;
3601 ir.gdbarch = gdbarch;
3603 if (record_debug > 1)
3604 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
3606 paddress (gdbarch, ir.addr));
3611 if (target_read_memory (ir.addr, &opcode8, 1))
3614 printf_unfiltered (_("Process record: error reading memory at "
3615 "addr %s len = 1.\n"),
3616 paddress (gdbarch, ir.addr));
3620 switch (opcode8) /* Instruction prefixes */
3622 case REPE_PREFIX_OPCODE:
3623 prefixes |= PREFIX_REPZ;
3625 case REPNE_PREFIX_OPCODE:
3626 prefixes |= PREFIX_REPNZ;
3628 case LOCK_PREFIX_OPCODE:
3629 prefixes |= PREFIX_LOCK;
3631 case CS_PREFIX_OPCODE:
3632 ir.override = X86_RECORD_CS_REGNUM;
3634 case SS_PREFIX_OPCODE:
3635 ir.override = X86_RECORD_SS_REGNUM;
3637 case DS_PREFIX_OPCODE:
3638 ir.override = X86_RECORD_DS_REGNUM;
3640 case ES_PREFIX_OPCODE:
3641 ir.override = X86_RECORD_ES_REGNUM;
3643 case FS_PREFIX_OPCODE:
3644 ir.override = X86_RECORD_FS_REGNUM;
3646 case GS_PREFIX_OPCODE:
3647 ir.override = X86_RECORD_GS_REGNUM;
3649 case DATA_PREFIX_OPCODE:
3650 prefixes |= PREFIX_DATA;
3652 case ADDR_PREFIX_OPCODE:
3653 prefixes |= PREFIX_ADDR;
3655 case 0x40: /* i386 inc %eax */
3656 case 0x41: /* i386 inc %ecx */
3657 case 0x42: /* i386 inc %edx */
3658 case 0x43: /* i386 inc %ebx */
3659 case 0x44: /* i386 inc %esp */
3660 case 0x45: /* i386 inc %ebp */
3661 case 0x46: /* i386 inc %esi */
3662 case 0x47: /* i386 inc %edi */
3663 case 0x48: /* i386 dec %eax */
3664 case 0x49: /* i386 dec %ecx */
3665 case 0x4a: /* i386 dec %edx */
3666 case 0x4b: /* i386 dec %ebx */
3667 case 0x4c: /* i386 dec %esp */
3668 case 0x4d: /* i386 dec %ebp */
3669 case 0x4e: /* i386 dec %esi */
3670 case 0x4f: /* i386 dec %edi */
3671 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
3675 rex_w = (opcode8 >> 3) & 1;
3676 rex_r = (opcode8 & 0x4) << 1;
3677 ir.rex_x = (opcode8 & 0x2) << 2;
3678 ir.rex_b = (opcode8 & 0x1) << 3;
3680 else /* 32 bit target */
3689 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
3695 if (prefixes & PREFIX_DATA)
3698 if (prefixes & PREFIX_ADDR)
3700 else if (ir.regmap[X86_RECORD_R8_REGNUM])
3703 /* now check op code */
3704 opcode = (uint32_t) opcode8;
3709 if (target_read_memory (ir.addr, &opcode8, 1))
3712 printf_unfiltered (_("Process record: error reading memory at "
3713 "addr %s len = 1.\n"),
3714 paddress (gdbarch, ir.addr));
3718 opcode = (uint32_t) opcode8 | 0x0f00;
3722 case 0x00: /* arith & logic */
3770 if (((opcode >> 3) & 7) != OP_CMPL)
3772 if ((opcode & 1) == 0)
3775 ir.ot = ir.dflag + OT_WORD;
3777 switch ((opcode >> 1) & 3)
3779 case 0: /* OP Ev, Gv */
3780 if (i386_record_modrm (&ir))
3784 if (i386_record_lea_modrm (&ir))
3790 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3792 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
3795 case 1: /* OP Gv, Ev */
3796 if (i386_record_modrm (&ir))
3799 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3801 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
3803 case 2: /* OP A, Iv */
3804 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
3808 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3811 case 0x80: /* GRP1 */
3815 if (i386_record_modrm (&ir))
3818 if (ir.reg != OP_CMPL)
3820 if ((opcode & 1) == 0)
3823 ir.ot = ir.dflag + OT_WORD;
3830 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
3831 if (i386_record_lea_modrm (&ir))
3835 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
3837 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3840 case 0x40: /* inc */
3849 case 0x48: /* dec */
3858 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7);
3859 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3862 case 0xf6: /* GRP3 */
3864 if ((opcode & 1) == 0)
3867 ir.ot = ir.dflag + OT_WORD;
3868 if (i386_record_modrm (&ir))
3871 if (ir.mod != 3 && ir.reg == 0)
3872 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
3877 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3883 if (i386_record_lea_modrm (&ir))
3889 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3891 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
3893 if (ir.reg == 3) /* neg */
3894 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3900 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
3901 if (ir.ot != OT_BYTE)
3902 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
3903 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3907 opcode = opcode << 8 | ir.modrm;
3913 case 0xfe: /* GRP4 */
3914 case 0xff: /* GRP5 */
3915 if (i386_record_modrm (&ir))
3917 if (ir.reg >= 2 && opcode == 0xfe)
3920 opcode = opcode << 8 | ir.modrm;
3927 if ((opcode & 1) == 0)
3930 ir.ot = ir.dflag + OT_WORD;
3933 if (i386_record_lea_modrm (&ir))
3939 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
3941 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
3943 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3946 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
3948 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
3950 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3953 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
3954 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
3956 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3960 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3963 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
3965 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
3970 opcode = opcode << 8 | ir.modrm;
3976 case 0x84: /* test */
3980 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
3983 case 0x98: /* CWDE/CBW */
3984 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
3987 case 0x99: /* CDQ/CWD */
3988 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
3989 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
3992 case 0x0faf: /* imul */
3995 ir.ot = ir.dflag + OT_WORD;
3996 if (i386_record_modrm (&ir))
3999 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4000 else if (opcode == 0x6b)
4003 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4005 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4006 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4009 case 0x0fc0: /* xadd */
4011 if ((opcode & 1) == 0)
4014 ir.ot = ir.dflag + OT_WORD;
4015 if (i386_record_modrm (&ir))
4020 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4022 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4023 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4025 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4029 if (i386_record_lea_modrm (&ir))
4031 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4033 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4035 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4038 case 0x0fb0: /* cmpxchg */
4040 if ((opcode & 1) == 0)
4043 ir.ot = ir.dflag + OT_WORD;
4044 if (i386_record_modrm (&ir))
4049 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4050 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4052 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4056 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4057 if (i386_record_lea_modrm (&ir))
4060 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4063 case 0x0fc7: /* cmpxchg8b */
4064 if (i386_record_modrm (&ir))
4069 opcode = opcode << 8 | ir.modrm;
4072 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4073 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
4074 if (i386_record_lea_modrm (&ir))
4076 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4079 case 0x50: /* push */
4089 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4091 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4095 case 0x06: /* push es */
4096 case 0x0e: /* push cs */
4097 case 0x16: /* push ss */
4098 case 0x1e: /* push ds */
4099 if (ir.regmap[X86_RECORD_R8_REGNUM])
4104 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4108 case 0x0fa0: /* push fs */
4109 case 0x0fa8: /* push gs */
4110 if (ir.regmap[X86_RECORD_R8_REGNUM])
4115 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4119 case 0x60: /* pusha */
4120 if (ir.regmap[X86_RECORD_R8_REGNUM])
4125 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
4129 case 0x58: /* pop */
4137 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4138 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
4141 case 0x61: /* popa */
4142 if (ir.regmap[X86_RECORD_R8_REGNUM])
4147 for (regnum = X86_RECORD_REAX_REGNUM;
4148 regnum <= X86_RECORD_REDI_REGNUM;
4150 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
4153 case 0x8f: /* pop */
4154 if (ir.regmap[X86_RECORD_R8_REGNUM])
4155 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
4157 ir.ot = ir.dflag + OT_WORD;
4158 if (i386_record_modrm (&ir))
4161 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
4164 ir.popl_esp_hack = 1 << ir.ot;
4165 if (i386_record_lea_modrm (&ir))
4168 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4171 case 0xc8: /* enter */
4172 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
4173 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
4175 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
4179 case 0xc9: /* leave */
4180 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4181 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
4184 case 0x07: /* pop es */
4185 if (ir.regmap[X86_RECORD_R8_REGNUM])
4190 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4191 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
4192 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4195 case 0x17: /* pop ss */
4196 if (ir.regmap[X86_RECORD_R8_REGNUM])
4201 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4202 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
4203 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4206 case 0x1f: /* pop ds */
4207 if (ir.regmap[X86_RECORD_R8_REGNUM])
4212 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4213 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
4214 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4217 case 0x0fa1: /* pop fs */
4218 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4219 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
4220 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4223 case 0x0fa9: /* pop gs */
4224 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
4225 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
4226 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4229 case 0x88: /* mov */
4233 if ((opcode & 1) == 0)
4236 ir.ot = ir.dflag + OT_WORD;
4238 if (i386_record_modrm (&ir))
4243 if (opcode == 0xc6 || opcode == 0xc7)
4244 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
4245 if (i386_record_lea_modrm (&ir))
4250 if (opcode == 0xc6 || opcode == 0xc7)
4252 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4254 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4258 case 0x8a: /* mov */
4260 if ((opcode & 1) == 0)
4263 ir.ot = ir.dflag + OT_WORD;
4264 if (i386_record_modrm (&ir))
4267 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4269 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4272 case 0x8c: /* mov seg */
4273 if (i386_record_modrm (&ir))
4278 opcode = opcode << 8 | ir.modrm;
4283 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4287 if (i386_record_lea_modrm (&ir))
4292 case 0x8e: /* mov seg */
4293 if (i386_record_modrm (&ir))
4298 regnum = X86_RECORD_ES_REGNUM;
4301 regnum = X86_RECORD_SS_REGNUM;
4304 regnum = X86_RECORD_DS_REGNUM;
4307 regnum = X86_RECORD_FS_REGNUM;
4310 regnum = X86_RECORD_GS_REGNUM;
4314 opcode = opcode << 8 | ir.modrm;
4318 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
4319 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4322 case 0x0fb6: /* movzbS */
4323 case 0x0fb7: /* movzwS */
4324 case 0x0fbe: /* movsbS */
4325 case 0x0fbf: /* movswS */
4326 if (i386_record_modrm (&ir))
4328 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
4331 case 0x8d: /* lea */
4332 if (i386_record_modrm (&ir))
4337 opcode = opcode << 8 | ir.modrm;
4342 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4344 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4347 case 0xa0: /* mov EAX */
4350 case 0xd7: /* xlat */
4351 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4354 case 0xa2: /* mov EAX */
4356 if (ir.override >= 0)
4358 warning (_("Process record ignores the memory change "
4359 "of instruction at address %s because "
4360 "it can't get the value of the segment "
4362 paddress (gdbarch, ir.orig_addr));
4366 if ((opcode & 1) == 0)
4369 ir.ot = ir.dflag + OT_WORD;
4372 if (target_read_memory (ir.addr, buf, 8))
4375 printf_unfiltered (_("Process record: error reading "
4376 "memory at addr 0x%s len = 8.\n"),
4377 paddress (gdbarch, ir.addr));
4381 addr = extract_unsigned_integer (buf, 8, byte_order);
4385 if (target_read_memory (ir.addr, buf, 4))
4388 printf_unfiltered (_("Process record: error reading "
4389 "memory at addr 0x%s len = 4.\n"),
4390 paddress (gdbarch, ir.addr));
4394 addr = extract_unsigned_integer (buf, 4, byte_order);
4398 if (target_read_memory (ir.addr, buf, 2))
4401 printf_unfiltered (_("Process record: error reading "
4402 "memory at addr 0x%s len = 2.\n"),
4403 paddress (gdbarch, ir.addr));
4407 addr = extract_unsigned_integer (buf, 2, byte_order);
4409 if (record_arch_list_add_mem (addr, 1 << ir.ot))
4414 case 0xb0: /* mov R, Ib */
4422 I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
4423 ? ((opcode & 0x7) | ir.rex_b)
4424 : ((opcode & 0x7) & 0x3));
4427 case 0xb8: /* mov R, Iv */
4435 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
4438 case 0x91: /* xchg R, EAX */
4445 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
4446 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7);
4449 case 0x86: /* xchg Ev, Gv */
4451 if ((opcode & 1) == 0)
4454 ir.ot = ir.dflag + OT_WORD;
4455 if (i386_record_modrm (&ir))
4460 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4462 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4466 if (i386_record_lea_modrm (&ir))
4470 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4472 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
4475 case 0xc4: /* les Gv */
4476 case 0xc5: /* lds Gv */
4477 if (ir.regmap[X86_RECORD_R8_REGNUM])
4482 case 0x0fb2: /* lss Gv */
4483 case 0x0fb4: /* lfs Gv */
4484 case 0x0fb5: /* lgs Gv */
4485 if (i386_record_modrm (&ir))
4493 opcode = opcode << 8 | ir.modrm;
4498 case 0xc4: /* les Gv */
4499 regnum = X86_RECORD_ES_REGNUM;
4501 case 0xc5: /* lds Gv */
4502 regnum = X86_RECORD_DS_REGNUM;
4504 case 0x0fb2: /* lss Gv */
4505 regnum = X86_RECORD_SS_REGNUM;
4507 case 0x0fb4: /* lfs Gv */
4508 regnum = X86_RECORD_FS_REGNUM;
4510 case 0x0fb5: /* lgs Gv */
4511 regnum = X86_RECORD_GS_REGNUM;
4514 I386_RECORD_ARCH_LIST_ADD_REG (regnum);
4515 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
4516 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4519 case 0xc0: /* shifts */
4525 if ((opcode & 1) == 0)
4528 ir.ot = ir.dflag + OT_WORD;
4529 if (i386_record_modrm (&ir))
4531 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
4533 if (i386_record_lea_modrm (&ir))
4539 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
4541 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
4543 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
4550 if (i386_record_modrm (&ir))
4554 if (record_arch_list_add_reg (ir.regcache, ir.rm))
4559 if (i386_record_lea_modrm (&ir))
4564 case 0xd8: /* Floats. */
4572 if (i386_record_modrm (&ir))
4574 ir.reg |= ((opcode & 7) << 3);
4580 if (i386_record_lea_modrm_addr (&ir, &addr64))
4588 /* For fcom, ficom nothing to do. */
4594 /* For fcomp, ficomp pop FPU stack, store all. */
4595 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4622 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
4623 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
4624 of code, always affects st(0) register. */
4625 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
4649 /* Handling fld, fild. */
4650 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4654 switch (ir.reg >> 4)
4657 if (record_arch_list_add_mem (addr64, 4))
4661 if (record_arch_list_add_mem (addr64, 8))
4667 if (record_arch_list_add_mem (addr64, 2))
4673 switch (ir.reg >> 4)
4676 if (record_arch_list_add_mem (addr64, 4))
4678 if (3 == (ir.reg & 7))
4680 /* For fstp m32fp. */
4681 if (i386_record_floats (gdbarch, &ir,
4682 I386_SAVE_FPU_REGS))
4687 if (record_arch_list_add_mem (addr64, 4))
4689 if ((3 == (ir.reg & 7))
4690 || (5 == (ir.reg & 7))
4691 || (7 == (ir.reg & 7)))
4693 /* For fstp insn. */
4694 if (i386_record_floats (gdbarch, &ir,
4695 I386_SAVE_FPU_REGS))
4700 if (record_arch_list_add_mem (addr64, 8))
4702 if (3 == (ir.reg & 7))
4704 /* For fstp m64fp. */
4705 if (i386_record_floats (gdbarch, &ir,
4706 I386_SAVE_FPU_REGS))
4711 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
4713 /* For fistp, fbld, fild, fbstp. */
4714 if (i386_record_floats (gdbarch, &ir,
4715 I386_SAVE_FPU_REGS))
4720 if (record_arch_list_add_mem (addr64, 2))
4729 if (i386_record_floats (gdbarch, &ir,
4730 I386_SAVE_FPU_ENV_REG_STACK))
4735 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
4740 if (i386_record_floats (gdbarch, &ir,
4741 I386_SAVE_FPU_ENV_REG_STACK))
4747 if (record_arch_list_add_mem (addr64, 28))
4752 if (record_arch_list_add_mem (addr64, 14))
4758 if (record_arch_list_add_mem (addr64, 2))
4760 /* Insn fstp, fbstp. */
4761 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4766 if (record_arch_list_add_mem (addr64, 10))
4772 if (record_arch_list_add_mem (addr64, 28))
4778 if (record_arch_list_add_mem (addr64, 14))
4782 if (record_arch_list_add_mem (addr64, 80))
4785 if (i386_record_floats (gdbarch, &ir,
4786 I386_SAVE_FPU_ENV_REG_STACK))
4790 if (record_arch_list_add_mem (addr64, 8))
4793 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4798 opcode = opcode << 8 | ir.modrm;
4803 /* Opcode is an extension of modR/M byte. */
4809 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
4813 if (0x0c == (ir.modrm >> 4))
4815 if ((ir.modrm & 0x0f) <= 7)
4817 if (i386_record_floats (gdbarch, &ir,
4818 I386_SAVE_FPU_REGS))
4823 if (i386_record_floats (gdbarch, &ir,
4824 I387_ST0_REGNUM (tdep)))
4826 /* If only st(0) is changing, then we have already
4828 if ((ir.modrm & 0x0f) - 0x08)
4830 if (i386_record_floats (gdbarch, &ir,
4831 I387_ST0_REGNUM (tdep) +
4832 ((ir.modrm & 0x0f) - 0x08)))
4850 if (i386_record_floats (gdbarch, &ir,
4851 I387_ST0_REGNUM (tdep)))
4869 if (i386_record_floats (gdbarch, &ir,
4870 I386_SAVE_FPU_REGS))
4874 if (i386_record_floats (gdbarch, &ir,
4875 I387_ST0_REGNUM (tdep)))
4877 if (i386_record_floats (gdbarch, &ir,
4878 I387_ST0_REGNUM (tdep) + 1))
4885 if (0xe9 == ir.modrm)
4887 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4890 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
4892 if (i386_record_floats (gdbarch, &ir,
4893 I387_ST0_REGNUM (tdep)))
4895 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
4897 if (i386_record_floats (gdbarch, &ir,
4898 I387_ST0_REGNUM (tdep) +
4902 else if ((ir.modrm & 0x0f) - 0x08)
4904 if (i386_record_floats (gdbarch, &ir,
4905 I387_ST0_REGNUM (tdep) +
4906 ((ir.modrm & 0x0f) - 0x08)))
4912 if (0xe3 == ir.modrm)
4914 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
4917 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
4919 if (i386_record_floats (gdbarch, &ir,
4920 I387_ST0_REGNUM (tdep)))
4922 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
4924 if (i386_record_floats (gdbarch, &ir,
4925 I387_ST0_REGNUM (tdep) +
4929 else if ((ir.modrm & 0x0f) - 0x08)
4931 if (i386_record_floats (gdbarch, &ir,
4932 I387_ST0_REGNUM (tdep) +
4933 ((ir.modrm & 0x0f) - 0x08)))
4939 if ((0x0c == ir.modrm >> 4)
4940 || (0x0d == ir.modrm >> 4)
4941 || (0x0f == ir.modrm >> 4))
4943 if ((ir.modrm & 0x0f) <= 7)
4945 if (i386_record_floats (gdbarch, &ir,
4946 I387_ST0_REGNUM (tdep) +
4952 if (i386_record_floats (gdbarch, &ir,
4953 I387_ST0_REGNUM (tdep) +
4954 ((ir.modrm & 0x0f) - 0x08)))
4960 if (0x0c == ir.modrm >> 4)
4962 if (i386_record_floats (gdbarch, &ir,
4963 I387_FTAG_REGNUM (tdep)))
4966 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
4968 if ((ir.modrm & 0x0f) <= 7)
4970 if (i386_record_floats (gdbarch, &ir,
4971 I387_ST0_REGNUM (tdep) +
4977 if (i386_record_floats (gdbarch, &ir,
4978 I386_SAVE_FPU_REGS))
4984 if ((0x0c == ir.modrm >> 4)
4985 || (0x0e == ir.modrm >> 4)
4986 || (0x0f == ir.modrm >> 4)
4987 || (0xd9 == ir.modrm))
4989 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
4994 if (0xe0 == ir.modrm)
4996 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
4999 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
5001 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5009 case 0xa4: /* movsS */
5011 case 0xaa: /* stosS */
5013 case 0x6c: /* insS */
5015 regcache_raw_read_unsigned (ir.regcache,
5016 ir.regmap[X86_RECORD_RECX_REGNUM],
5022 if ((opcode & 1) == 0)
5025 ir.ot = ir.dflag + OT_WORD;
5026 regcache_raw_read_unsigned (ir.regcache,
5027 ir.regmap[X86_RECORD_REDI_REGNUM],
5030 regcache_raw_read_unsigned (ir.regcache,
5031 ir.regmap[X86_RECORD_ES_REGNUM],
5033 regcache_raw_read_unsigned (ir.regcache,
5034 ir.regmap[X86_RECORD_DS_REGNUM],
5036 if (ir.aflag && (es != ds))
5038 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5039 warning (_("Process record ignores the memory "
5040 "change of instruction at address %s "
5041 "because it can't get the value of the "
5042 "ES segment register."),
5043 paddress (gdbarch, ir.orig_addr));
5047 if (record_arch_list_add_mem (addr, 1 << ir.ot))
5051 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5052 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5053 if (opcode == 0xa4 || opcode == 0xa5)
5054 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5055 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5056 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5060 case 0xa6: /* cmpsS */
5062 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5063 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5064 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5065 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5066 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5069 case 0xac: /* lodsS */
5071 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5072 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5073 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5074 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5075 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5078 case 0xae: /* scasS */
5080 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5081 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5082 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5083 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5086 case 0x6e: /* outsS */
5088 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5089 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
5090 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5091 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5094 case 0xe4: /* port I/O */
5098 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5099 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5109 case 0xc2: /* ret im */
5110 case 0xc3: /* ret */
5111 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5112 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5115 case 0xca: /* lret im */
5116 case 0xcb: /* lret */
5117 case 0xcf: /* iret */
5118 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5119 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5120 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5123 case 0xe8: /* call im */
5124 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5126 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5130 case 0x9a: /* lcall im */
5131 if (ir.regmap[X86_RECORD_R8_REGNUM])
5136 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5137 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5141 case 0xe9: /* jmp im */
5142 case 0xea: /* ljmp im */
5143 case 0xeb: /* jmp Jb */
5144 case 0x70: /* jcc Jb */
5160 case 0x0f80: /* jcc Jv */
5178 case 0x0f90: /* setcc Gv */
5194 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5196 if (i386_record_modrm (&ir))
5199 I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
5203 if (i386_record_lea_modrm (&ir))
5208 case 0x0f40: /* cmov Gv, Ev */
5224 if (i386_record_modrm (&ir))
5227 if (ir.dflag == OT_BYTE)
5229 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
5233 case 0x9c: /* pushf */
5234 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5235 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5237 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5241 case 0x9d: /* popf */
5242 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5243 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5246 case 0x9e: /* sahf */
5247 if (ir.regmap[X86_RECORD_R8_REGNUM])
5252 case 0xf5: /* cmc */
5253 case 0xf8: /* clc */
5254 case 0xf9: /* stc */
5255 case 0xfc: /* cld */
5256 case 0xfd: /* std */
5257 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5260 case 0x9f: /* lahf */
5261 if (ir.regmap[X86_RECORD_R8_REGNUM])
5266 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5267 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5270 /* bit operations */
5271 case 0x0fba: /* bt/bts/btr/btc Gv, im */
5272 ir.ot = ir.dflag + OT_WORD;
5273 if (i386_record_modrm (&ir))
5278 opcode = opcode << 8 | ir.modrm;
5284 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5287 if (i386_record_lea_modrm (&ir))
5291 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5294 case 0x0fa3: /* bt Gv, Ev */
5295 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5298 case 0x0fab: /* bts */
5299 case 0x0fb3: /* btr */
5300 case 0x0fbb: /* btc */
5301 ir.ot = ir.dflag + OT_WORD;
5302 if (i386_record_modrm (&ir))
5305 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5309 if (i386_record_lea_modrm_addr (&ir, &addr64))
5311 regcache_raw_read_unsigned (ir.regcache,
5312 ir.regmap[ir.reg | rex_r],
5317 addr64 += ((int16_t) addr >> 4) << 4;
5320 addr64 += ((int32_t) addr >> 5) << 5;
5323 addr64 += ((int64_t) addr >> 6) << 6;
5326 if (record_arch_list_add_mem (addr64, 1 << ir.ot))
5328 if (i386_record_lea_modrm (&ir))
5331 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5334 case 0x0fbc: /* bsf */
5335 case 0x0fbd: /* bsr */
5336 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5337 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5341 case 0x27: /* daa */
5342 case 0x2f: /* das */
5343 case 0x37: /* aaa */
5344 case 0x3f: /* aas */
5345 case 0xd4: /* aam */
5346 case 0xd5: /* aad */
5347 if (ir.regmap[X86_RECORD_R8_REGNUM])
5352 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5353 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5357 case 0x90: /* nop */
5358 if (prefixes & PREFIX_LOCK)
5365 case 0x9b: /* fwait */
5366 if (target_read_memory (ir.addr, &opcode8, 1))
5369 printf_unfiltered (_("Process record: error reading memory at "
5370 "addr 0x%s len = 1.\n"),
5371 paddress (gdbarch, ir.addr));
5374 opcode = (uint32_t) opcode8;
5380 case 0xcc: /* int3 */
5381 printf_unfiltered (_("Process record does not support instruction "
5388 case 0xcd: /* int */
5392 if (target_read_memory (ir.addr, &interrupt, 1))
5395 printf_unfiltered (_("Process record: error reading memory "
5396 "at addr %s len = 1.\n"),
5397 paddress (gdbarch, ir.addr));
5401 if (interrupt != 0x80
5402 || tdep->i386_intx80_record == NULL)
5404 printf_unfiltered (_("Process record does not support "
5405 "instruction int 0x%02x.\n"),
5410 ret = tdep->i386_intx80_record (ir.regcache);
5417 case 0xce: /* into */
5418 printf_unfiltered (_("Process record does not support "
5419 "instruction into.\n"));
5424 case 0xfa: /* cli */
5425 case 0xfb: /* sti */
5428 case 0x62: /* bound */
5429 printf_unfiltered (_("Process record does not support "
5430 "instruction bound.\n"));
5435 case 0x0fc8: /* bswap reg */
5443 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
5446 case 0xd6: /* salc */
5447 if (ir.regmap[X86_RECORD_R8_REGNUM])
5452 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5453 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5456 case 0xe0: /* loopnz */
5457 case 0xe1: /* loopz */
5458 case 0xe2: /* loop */
5459 case 0xe3: /* jecxz */
5460 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5461 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5464 case 0x0f30: /* wrmsr */
5465 printf_unfiltered (_("Process record does not support "
5466 "instruction wrmsr.\n"));
5471 case 0x0f32: /* rdmsr */
5472 printf_unfiltered (_("Process record does not support "
5473 "instruction rdmsr.\n"));
5478 case 0x0f31: /* rdtsc */
5479 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5480 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5483 case 0x0f34: /* sysenter */
5486 if (ir.regmap[X86_RECORD_R8_REGNUM])
5491 if (tdep->i386_sysenter_record == NULL)
5493 printf_unfiltered (_("Process record does not support "
5494 "instruction sysenter.\n"));
5498 ret = tdep->i386_sysenter_record (ir.regcache);
5504 case 0x0f35: /* sysexit */
5505 printf_unfiltered (_("Process record does not support "
5506 "instruction sysexit.\n"));
5511 case 0x0f05: /* syscall */
5514 if (tdep->i386_syscall_record == NULL)
5516 printf_unfiltered (_("Process record does not support "
5517 "instruction syscall.\n"));
5521 ret = tdep->i386_syscall_record (ir.regcache);
5527 case 0x0f07: /* sysret */
5528 printf_unfiltered (_("Process record does not support "
5529 "instruction sysret.\n"));
5534 case 0x0fa2: /* cpuid */
5535 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5536 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5537 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5538 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
5541 case 0xf4: /* hlt */
5542 printf_unfiltered (_("Process record does not support "
5543 "instruction hlt.\n"));
5549 if (i386_record_modrm (&ir))
5556 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5560 if (i386_record_lea_modrm (&ir))
5569 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5573 opcode = opcode << 8 | ir.modrm;
5580 if (i386_record_modrm (&ir))
5591 opcode = opcode << 8 | ir.modrm;
5594 if (ir.override >= 0)
5596 warning (_("Process record ignores the memory "
5597 "change of instruction at "
5598 "address %s because it can't get "
5599 "the value of the segment "
5601 paddress (gdbarch, ir.orig_addr));
5605 if (i386_record_lea_modrm_addr (&ir, &addr64))
5607 if (record_arch_list_add_mem (addr64, 2))
5610 if (ir.regmap[X86_RECORD_R8_REGNUM])
5612 if (record_arch_list_add_mem (addr64, 8))
5617 if (record_arch_list_add_mem (addr64, 4))
5628 case 0: /* monitor */
5631 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5635 opcode = opcode << 8 | ir.modrm;
5643 if (ir.override >= 0)
5645 warning (_("Process record ignores the memory "
5646 "change of instruction at "
5647 "address %s because it can't get "
5648 "the value of the segment "
5650 paddress (gdbarch, ir.orig_addr));
5656 if (i386_record_lea_modrm_addr (&ir, &addr64))
5658 if (record_arch_list_add_mem (addr64, 2))
5661 if (ir.regmap[X86_RECORD_R8_REGNUM])
5663 if (record_arch_list_add_mem (addr64, 8))
5668 if (record_arch_list_add_mem (addr64, 4))
5680 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5681 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5685 else if (ir.rm == 1)
5692 opcode = opcode << 8 | ir.modrm;
5699 if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
5705 if (i386_record_lea_modrm (&ir))
5708 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5711 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5713 case 7: /* invlpg */
5716 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
5717 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
5721 opcode = opcode << 8 | ir.modrm;
5726 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5730 opcode = opcode << 8 | ir.modrm;
5736 case 0x0f08: /* invd */
5737 case 0x0f09: /* wbinvd */
5740 case 0x63: /* arpl */
5741 if (i386_record_modrm (&ir))
5743 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
5745 I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
5746 ? (ir.reg | rex_r) : ir.rm);
5750 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
5751 if (i386_record_lea_modrm (&ir))
5754 if (!ir.regmap[X86_RECORD_R8_REGNUM])
5755 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5758 case 0x0f02: /* lar */
5759 case 0x0f03: /* lsl */
5760 if (i386_record_modrm (&ir))
5762 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5763 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5767 if (i386_record_modrm (&ir))
5769 if (ir.mod == 3 && ir.reg == 3)
5772 opcode = opcode << 8 | ir.modrm;
5784 /* nop (multi byte) */
5787 case 0x0f20: /* mov reg, crN */
5788 case 0x0f22: /* mov crN, reg */
5789 if (i386_record_modrm (&ir))
5791 if ((ir.modrm & 0xc0) != 0xc0)
5794 opcode = opcode << 8 | ir.modrm;
5805 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5807 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5811 opcode = opcode << 8 | ir.modrm;
5817 case 0x0f21: /* mov reg, drN */
5818 case 0x0f23: /* mov drN, reg */
5819 if (i386_record_modrm (&ir))
5821 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
5822 || ir.reg == 5 || ir.reg >= 8)
5825 opcode = opcode << 8 | ir.modrm;
5829 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5831 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5834 case 0x0f06: /* clts */
5835 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5838 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
5840 case 0x0f0d: /* 3DNow! prefetch */
5843 case 0x0f0e: /* 3DNow! femms */
5844 case 0x0f77: /* emms */
5845 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
5847 record_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
5850 case 0x0f0f: /* 3DNow! data */
5851 if (i386_record_modrm (&ir))
5853 if (target_read_memory (ir.addr, &opcode8, 1))
5855 printf_unfiltered (_("Process record: error reading memory at "
5856 "addr %s len = 1.\n"),
5857 paddress (gdbarch, ir.addr));
5863 case 0x0c: /* 3DNow! pi2fw */
5864 case 0x0d: /* 3DNow! pi2fd */
5865 case 0x1c: /* 3DNow! pf2iw */
5866 case 0x1d: /* 3DNow! pf2id */
5867 case 0x8a: /* 3DNow! pfnacc */
5868 case 0x8e: /* 3DNow! pfpnacc */
5869 case 0x90: /* 3DNow! pfcmpge */
5870 case 0x94: /* 3DNow! pfmin */
5871 case 0x96: /* 3DNow! pfrcp */
5872 case 0x97: /* 3DNow! pfrsqrt */
5873 case 0x9a: /* 3DNow! pfsub */
5874 case 0x9e: /* 3DNow! pfadd */
5875 case 0xa0: /* 3DNow! pfcmpgt */
5876 case 0xa4: /* 3DNow! pfmax */
5877 case 0xa6: /* 3DNow! pfrcpit1 */
5878 case 0xa7: /* 3DNow! pfrsqit1 */
5879 case 0xaa: /* 3DNow! pfsubr */
5880 case 0xae: /* 3DNow! pfacc */
5881 case 0xb0: /* 3DNow! pfcmpeq */
5882 case 0xb4: /* 3DNow! pfmul */
5883 case 0xb6: /* 3DNow! pfrcpit2 */
5884 case 0xb7: /* 3DNow! pmulhrw */
5885 case 0xbb: /* 3DNow! pswapd */
5886 case 0xbf: /* 3DNow! pavgusb */
5887 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
5888 goto no_support_3dnow_data;
5889 record_arch_list_add_reg (ir.regcache, ir.reg);
5893 no_support_3dnow_data:
5894 opcode = (opcode << 8) | opcode8;
5900 case 0x0faa: /* rsm */
5901 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5902 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5903 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
5904 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5905 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
5906 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5907 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5908 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
5909 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
5913 if (i386_record_modrm (&ir))
5917 case 0: /* fxsave */
5921 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5922 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
5924 if (record_arch_list_add_mem (tmpu64, 512))
5929 case 1: /* fxrstor */
5933 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5935 for (i = I387_MM0_REGNUM (tdep);
5936 i386_mmx_regnum_p (gdbarch, i); i++)
5937 record_arch_list_add_reg (ir.regcache, i);
5939 for (i = I387_XMM0_REGNUM (tdep);
5940 i386_xmm_regnum_p (gdbarch, i); i++)
5941 record_arch_list_add_reg (ir.regcache, i);
5943 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
5944 record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
5946 for (i = I387_ST0_REGNUM (tdep);
5947 i386_fp_regnum_p (gdbarch, i); i++)
5948 record_arch_list_add_reg (ir.regcache, i);
5950 for (i = I387_FCTRL_REGNUM (tdep);
5951 i386_fpc_regnum_p (gdbarch, i); i++)
5952 record_arch_list_add_reg (ir.regcache, i);
5956 case 2: /* ldmxcsr */
5957 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
5959 record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
5962 case 3: /* stmxcsr */
5964 if (i386_record_lea_modrm (&ir))
5968 case 5: /* lfence */
5969 case 6: /* mfence */
5970 case 7: /* sfence clflush */
5974 opcode = (opcode << 8) | ir.modrm;
5980 case 0x0fc3: /* movnti */
5981 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
5982 if (i386_record_modrm (&ir))
5987 if (i386_record_lea_modrm (&ir))
5991 /* Add prefix to opcode. */
6118 reswitch_prefix_add:
6126 if (target_read_memory (ir.addr, &opcode8, 1))
6128 printf_unfiltered (_("Process record: error reading memory at "
6129 "addr %s len = 1.\n"),
6130 paddress (gdbarch, ir.addr));
6134 opcode = (uint32_t) opcode8 | opcode << 8;
6135 goto reswitch_prefix_add;
6138 case 0x0f10: /* movups */
6139 case 0x660f10: /* movupd */
6140 case 0xf30f10: /* movss */
6141 case 0xf20f10: /* movsd */
6142 case 0x0f12: /* movlps */
6143 case 0x660f12: /* movlpd */
6144 case 0xf30f12: /* movsldup */
6145 case 0xf20f12: /* movddup */
6146 case 0x0f14: /* unpcklps */
6147 case 0x660f14: /* unpcklpd */
6148 case 0x0f15: /* unpckhps */
6149 case 0x660f15: /* unpckhpd */
6150 case 0x0f16: /* movhps */
6151 case 0x660f16: /* movhpd */
6152 case 0xf30f16: /* movshdup */
6153 case 0x0f28: /* movaps */
6154 case 0x660f28: /* movapd */
6155 case 0x0f2a: /* cvtpi2ps */
6156 case 0x660f2a: /* cvtpi2pd */
6157 case 0xf30f2a: /* cvtsi2ss */
6158 case 0xf20f2a: /* cvtsi2sd */
6159 case 0x0f2c: /* cvttps2pi */
6160 case 0x660f2c: /* cvttpd2pi */
6161 case 0x0f2d: /* cvtps2pi */
6162 case 0x660f2d: /* cvtpd2pi */
6163 case 0x660f3800: /* pshufb */
6164 case 0x660f3801: /* phaddw */
6165 case 0x660f3802: /* phaddd */
6166 case 0x660f3803: /* phaddsw */
6167 case 0x660f3804: /* pmaddubsw */
6168 case 0x660f3805: /* phsubw */
6169 case 0x660f3806: /* phsubd */
6170 case 0x660f3807: /* phaddsw */
6171 case 0x660f3808: /* psignb */
6172 case 0x660f3809: /* psignw */
6173 case 0x660f380a: /* psignd */
6174 case 0x660f380b: /* pmulhrsw */
6175 case 0x660f3810: /* pblendvb */
6176 case 0x660f3814: /* blendvps */
6177 case 0x660f3815: /* blendvpd */
6178 case 0x660f381c: /* pabsb */
6179 case 0x660f381d: /* pabsw */
6180 case 0x660f381e: /* pabsd */
6181 case 0x660f3820: /* pmovsxbw */
6182 case 0x660f3821: /* pmovsxbd */
6183 case 0x660f3822: /* pmovsxbq */
6184 case 0x660f3823: /* pmovsxwd */
6185 case 0x660f3824: /* pmovsxwq */
6186 case 0x660f3825: /* pmovsxdq */
6187 case 0x660f3828: /* pmuldq */
6188 case 0x660f3829: /* pcmpeqq */
6189 case 0x660f382a: /* movntdqa */
6190 case 0x660f3a08: /* roundps */
6191 case 0x660f3a09: /* roundpd */
6192 case 0x660f3a0a: /* roundss */
6193 case 0x660f3a0b: /* roundsd */
6194 case 0x660f3a0c: /* blendps */
6195 case 0x660f3a0d: /* blendpd */
6196 case 0x660f3a0e: /* pblendw */
6197 case 0x660f3a0f: /* palignr */
6198 case 0x660f3a20: /* pinsrb */
6199 case 0x660f3a21: /* insertps */
6200 case 0x660f3a22: /* pinsrd pinsrq */
6201 case 0x660f3a40: /* dpps */
6202 case 0x660f3a41: /* dppd */
6203 case 0x660f3a42: /* mpsadbw */
6204 case 0x660f3a60: /* pcmpestrm */
6205 case 0x660f3a61: /* pcmpestri */
6206 case 0x660f3a62: /* pcmpistrm */
6207 case 0x660f3a63: /* pcmpistri */
6208 case 0x0f51: /* sqrtps */
6209 case 0x660f51: /* sqrtpd */
6210 case 0xf20f51: /* sqrtsd */
6211 case 0xf30f51: /* sqrtss */
6212 case 0x0f52: /* rsqrtps */
6213 case 0xf30f52: /* rsqrtss */
6214 case 0x0f53: /* rcpps */
6215 case 0xf30f53: /* rcpss */
6216 case 0x0f54: /* andps */
6217 case 0x660f54: /* andpd */
6218 case 0x0f55: /* andnps */
6219 case 0x660f55: /* andnpd */
6220 case 0x0f56: /* orps */
6221 case 0x660f56: /* orpd */
6222 case 0x0f57: /* xorps */
6223 case 0x660f57: /* xorpd */
6224 case 0x0f58: /* addps */
6225 case 0x660f58: /* addpd */
6226 case 0xf20f58: /* addsd */
6227 case 0xf30f58: /* addss */
6228 case 0x0f59: /* mulps */
6229 case 0x660f59: /* mulpd */
6230 case 0xf20f59: /* mulsd */
6231 case 0xf30f59: /* mulss */
6232 case 0x0f5a: /* cvtps2pd */
6233 case 0x660f5a: /* cvtpd2ps */
6234 case 0xf20f5a: /* cvtsd2ss */
6235 case 0xf30f5a: /* cvtss2sd */
6236 case 0x0f5b: /* cvtdq2ps */
6237 case 0x660f5b: /* cvtps2dq */
6238 case 0xf30f5b: /* cvttps2dq */
6239 case 0x0f5c: /* subps */
6240 case 0x660f5c: /* subpd */
6241 case 0xf20f5c: /* subsd */
6242 case 0xf30f5c: /* subss */
6243 case 0x0f5d: /* minps */
6244 case 0x660f5d: /* minpd */
6245 case 0xf20f5d: /* minsd */
6246 case 0xf30f5d: /* minss */
6247 case 0x0f5e: /* divps */
6248 case 0x660f5e: /* divpd */
6249 case 0xf20f5e: /* divsd */
6250 case 0xf30f5e: /* divss */
6251 case 0x0f5f: /* maxps */
6252 case 0x660f5f: /* maxpd */
6253 case 0xf20f5f: /* maxsd */
6254 case 0xf30f5f: /* maxss */
6255 case 0x660f60: /* punpcklbw */
6256 case 0x660f61: /* punpcklwd */
6257 case 0x660f62: /* punpckldq */
6258 case 0x660f63: /* packsswb */
6259 case 0x660f64: /* pcmpgtb */
6260 case 0x660f65: /* pcmpgtw */
6261 case 0x660f66: /* pcmpgtl */
6262 case 0x660f67: /* packuswb */
6263 case 0x660f68: /* punpckhbw */
6264 case 0x660f69: /* punpckhwd */
6265 case 0x660f6a: /* punpckhdq */
6266 case 0x660f6b: /* packssdw */
6267 case 0x660f6c: /* punpcklqdq */
6268 case 0x660f6d: /* punpckhqdq */
6269 case 0x660f6e: /* movd */
6270 case 0x660f6f: /* movdqa */
6271 case 0xf30f6f: /* movdqu */
6272 case 0x660f70: /* pshufd */
6273 case 0xf20f70: /* pshuflw */
6274 case 0xf30f70: /* pshufhw */
6275 case 0x660f74: /* pcmpeqb */
6276 case 0x660f75: /* pcmpeqw */
6277 case 0x660f76: /* pcmpeql */
6278 case 0x660f7c: /* haddpd */
6279 case 0xf20f7c: /* haddps */
6280 case 0x660f7d: /* hsubpd */
6281 case 0xf20f7d: /* hsubps */
6282 case 0xf30f7e: /* movq */
6283 case 0x0fc2: /* cmpps */
6284 case 0x660fc2: /* cmppd */
6285 case 0xf20fc2: /* cmpsd */
6286 case 0xf30fc2: /* cmpss */
6287 case 0x660fc4: /* pinsrw */
6288 case 0x0fc6: /* shufps */
6289 case 0x660fc6: /* shufpd */
6290 case 0x660fd0: /* addsubpd */
6291 case 0xf20fd0: /* addsubps */
6292 case 0x660fd1: /* psrlw */
6293 case 0x660fd2: /* psrld */
6294 case 0x660fd3: /* psrlq */
6295 case 0x660fd4: /* paddq */
6296 case 0x660fd5: /* pmullw */
6297 case 0xf30fd6: /* movq2dq */
6298 case 0x660fd8: /* psubusb */
6299 case 0x660fd9: /* psubusw */
6300 case 0x660fda: /* pminub */
6301 case 0x660fdb: /* pand */
6302 case 0x660fdc: /* paddusb */
6303 case 0x660fdd: /* paddusw */
6304 case 0x660fde: /* pmaxub */
6305 case 0x660fdf: /* pandn */
6306 case 0x660fe0: /* pavgb */
6307 case 0x660fe1: /* psraw */
6308 case 0x660fe2: /* psrad */
6309 case 0x660fe3: /* pavgw */
6310 case 0x660fe4: /* pmulhuw */
6311 case 0x660fe5: /* pmulhw */
6312 case 0x660fe6: /* cvttpd2dq */
6313 case 0xf20fe6: /* cvtpd2dq */
6314 case 0xf30fe6: /* cvtdq2pd */
6315 case 0x660fe8: /* psubsb */
6316 case 0x660fe9: /* psubsw */
6317 case 0x660fea: /* pminsw */
6318 case 0x660feb: /* por */
6319 case 0x660fec: /* paddsb */
6320 case 0x660fed: /* paddsw */
6321 case 0x660fee: /* pmaxsw */
6322 case 0x660fef: /* pxor */
6323 case 0x660ff0: /* lddqu */
6324 case 0x660ff1: /* psllw */
6325 case 0x660ff2: /* pslld */
6326 case 0x660ff3: /* psllq */
6327 case 0x660ff4: /* pmuludq */
6328 case 0x660ff5: /* pmaddwd */
6329 case 0x660ff6: /* psadbw */
6330 case 0x660ff8: /* psubb */
6331 case 0x660ff9: /* psubw */
6332 case 0x660ffa: /* psubl */
6333 case 0x660ffb: /* psubq */
6334 case 0x660ffc: /* paddb */
6335 case 0x660ffd: /* paddw */
6336 case 0x660ffe: /* paddl */
6337 if (i386_record_modrm (&ir))
6340 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
6342 record_arch_list_add_reg (ir.regcache,
6343 I387_XMM0_REGNUM (tdep) + ir.reg);
6344 if ((opcode & 0xfffffffc) == 0x660f3a60)
6345 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6348 case 0x0f11: /* movups */
6349 case 0x660f11: /* movupd */
6350 case 0xf30f11: /* movss */
6351 case 0xf20f11: /* movsd */
6352 case 0x0f13: /* movlps */
6353 case 0x660f13: /* movlpd */
6354 case 0x0f17: /* movhps */
6355 case 0x660f17: /* movhpd */
6356 case 0x0f29: /* movaps */
6357 case 0x660f29: /* movapd */
6358 case 0x660f3a14: /* pextrb */
6359 case 0x660f3a15: /* pextrw */
6360 case 0x660f3a16: /* pextrd pextrq */
6361 case 0x660f3a17: /* extractps */
6362 case 0x660f7f: /* movdqa */
6363 case 0xf30f7f: /* movdqu */
6364 if (i386_record_modrm (&ir))
6368 if (opcode == 0x0f13 || opcode == 0x660f13
6369 || opcode == 0x0f17 || opcode == 0x660f17)
6372 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
6374 record_arch_list_add_reg (ir.regcache,
6375 I387_XMM0_REGNUM (tdep) + ir.rm);
6397 if (i386_record_lea_modrm (&ir))
6402 case 0x0f2b: /* movntps */
6403 case 0x660f2b: /* movntpd */
6404 case 0x0fe7: /* movntq */
6405 case 0x660fe7: /* movntdq */
6408 if (opcode == 0x0fe7)
6412 if (i386_record_lea_modrm (&ir))
6416 case 0xf30f2c: /* cvttss2si */
6417 case 0xf20f2c: /* cvttsd2si */
6418 case 0xf30f2d: /* cvtss2si */
6419 case 0xf20f2d: /* cvtsd2si */
6420 case 0xf20f38f0: /* crc32 */
6421 case 0xf20f38f1: /* crc32 */
6422 case 0x0f50: /* movmskps */
6423 case 0x660f50: /* movmskpd */
6424 case 0x0fc5: /* pextrw */
6425 case 0x660fc5: /* pextrw */
6426 case 0x0fd7: /* pmovmskb */
6427 case 0x660fd7: /* pmovmskb */
6428 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6431 case 0x0f3800: /* pshufb */
6432 case 0x0f3801: /* phaddw */
6433 case 0x0f3802: /* phaddd */
6434 case 0x0f3803: /* phaddsw */
6435 case 0x0f3804: /* pmaddubsw */
6436 case 0x0f3805: /* phsubw */
6437 case 0x0f3806: /* phsubd */
6438 case 0x0f3807: /* phaddsw */
6439 case 0x0f3808: /* psignb */
6440 case 0x0f3809: /* psignw */
6441 case 0x0f380a: /* psignd */
6442 case 0x0f380b: /* pmulhrsw */
6443 case 0x0f381c: /* pabsb */
6444 case 0x0f381d: /* pabsw */
6445 case 0x0f381e: /* pabsd */
6446 case 0x0f382b: /* packusdw */
6447 case 0x0f3830: /* pmovzxbw */
6448 case 0x0f3831: /* pmovzxbd */
6449 case 0x0f3832: /* pmovzxbq */
6450 case 0x0f3833: /* pmovzxwd */
6451 case 0x0f3834: /* pmovzxwq */
6452 case 0x0f3835: /* pmovzxdq */
6453 case 0x0f3837: /* pcmpgtq */
6454 case 0x0f3838: /* pminsb */
6455 case 0x0f3839: /* pminsd */
6456 case 0x0f383a: /* pminuw */
6457 case 0x0f383b: /* pminud */
6458 case 0x0f383c: /* pmaxsb */
6459 case 0x0f383d: /* pmaxsd */
6460 case 0x0f383e: /* pmaxuw */
6461 case 0x0f383f: /* pmaxud */
6462 case 0x0f3840: /* pmulld */
6463 case 0x0f3841: /* phminposuw */
6464 case 0x0f3a0f: /* palignr */
6465 case 0x0f60: /* punpcklbw */
6466 case 0x0f61: /* punpcklwd */
6467 case 0x0f62: /* punpckldq */
6468 case 0x0f63: /* packsswb */
6469 case 0x0f64: /* pcmpgtb */
6470 case 0x0f65: /* pcmpgtw */
6471 case 0x0f66: /* pcmpgtl */
6472 case 0x0f67: /* packuswb */
6473 case 0x0f68: /* punpckhbw */
6474 case 0x0f69: /* punpckhwd */
6475 case 0x0f6a: /* punpckhdq */
6476 case 0x0f6b: /* packssdw */
6477 case 0x0f6e: /* movd */
6478 case 0x0f6f: /* movq */
6479 case 0x0f70: /* pshufw */
6480 case 0x0f74: /* pcmpeqb */
6481 case 0x0f75: /* pcmpeqw */
6482 case 0x0f76: /* pcmpeql */
6483 case 0x0fc4: /* pinsrw */
6484 case 0x0fd1: /* psrlw */
6485 case 0x0fd2: /* psrld */
6486 case 0x0fd3: /* psrlq */
6487 case 0x0fd4: /* paddq */
6488 case 0x0fd5: /* pmullw */
6489 case 0xf20fd6: /* movdq2q */
6490 case 0x0fd8: /* psubusb */
6491 case 0x0fd9: /* psubusw */
6492 case 0x0fda: /* pminub */
6493 case 0x0fdb: /* pand */
6494 case 0x0fdc: /* paddusb */
6495 case 0x0fdd: /* paddusw */
6496 case 0x0fde: /* pmaxub */
6497 case 0x0fdf: /* pandn */
6498 case 0x0fe0: /* pavgb */
6499 case 0x0fe1: /* psraw */
6500 case 0x0fe2: /* psrad */
6501 case 0x0fe3: /* pavgw */
6502 case 0x0fe4: /* pmulhuw */
6503 case 0x0fe5: /* pmulhw */
6504 case 0x0fe8: /* psubsb */
6505 case 0x0fe9: /* psubsw */
6506 case 0x0fea: /* pminsw */
6507 case 0x0feb: /* por */
6508 case 0x0fec: /* paddsb */
6509 case 0x0fed: /* paddsw */
6510 case 0x0fee: /* pmaxsw */
6511 case 0x0fef: /* pxor */
6512 case 0x0ff1: /* psllw */
6513 case 0x0ff2: /* pslld */
6514 case 0x0ff3: /* psllq */
6515 case 0x0ff4: /* pmuludq */
6516 case 0x0ff5: /* pmaddwd */
6517 case 0x0ff6: /* psadbw */
6518 case 0x0ff8: /* psubb */
6519 case 0x0ff9: /* psubw */
6520 case 0x0ffa: /* psubl */
6521 case 0x0ffb: /* psubq */
6522 case 0x0ffc: /* paddb */
6523 case 0x0ffd: /* paddw */
6524 case 0x0ffe: /* paddl */
6525 if (i386_record_modrm (&ir))
6527 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
6529 record_arch_list_add_reg (ir.regcache,
6530 I387_MM0_REGNUM (tdep) + ir.reg);
6533 case 0x0f71: /* psllw */
6534 case 0x0f72: /* pslld */
6535 case 0x0f73: /* psllq */
6536 if (i386_record_modrm (&ir))
6538 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
6540 record_arch_list_add_reg (ir.regcache,
6541 I387_MM0_REGNUM (tdep) + ir.rm);
6544 case 0x660f71: /* psllw */
6545 case 0x660f72: /* pslld */
6546 case 0x660f73: /* psllq */
6547 if (i386_record_modrm (&ir))
6550 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
6552 record_arch_list_add_reg (ir.regcache,
6553 I387_XMM0_REGNUM (tdep) + ir.rm);
6556 case 0x0f7e: /* movd */
6557 case 0x660f7e: /* movd */
6558 if (i386_record_modrm (&ir))
6561 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6568 if (i386_record_lea_modrm (&ir))
6573 case 0x0f7f: /* movq */
6574 if (i386_record_modrm (&ir))
6578 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
6580 record_arch_list_add_reg (ir.regcache,
6581 I387_MM0_REGNUM (tdep) + ir.rm);
6586 if (i386_record_lea_modrm (&ir))
6591 case 0xf30fb8: /* popcnt */
6592 if (i386_record_modrm (&ir))
6594 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
6595 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6598 case 0x660fd6: /* movq */
6599 if (i386_record_modrm (&ir))
6604 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
6606 record_arch_list_add_reg (ir.regcache,
6607 I387_XMM0_REGNUM (tdep) + ir.rm);
6612 if (i386_record_lea_modrm (&ir))
6617 case 0x660f3817: /* ptest */
6618 case 0x0f2e: /* ucomiss */
6619 case 0x660f2e: /* ucomisd */
6620 case 0x0f2f: /* comiss */
6621 case 0x660f2f: /* comisd */
6622 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6625 case 0x0ff7: /* maskmovq */
6626 regcache_raw_read_unsigned (ir.regcache,
6627 ir.regmap[X86_RECORD_REDI_REGNUM],
6629 if (record_arch_list_add_mem (addr, 64))
6633 case 0x660ff7: /* maskmovdqu */
6634 regcache_raw_read_unsigned (ir.regcache,
6635 ir.regmap[X86_RECORD_REDI_REGNUM],
6637 if (record_arch_list_add_mem (addr, 128))
6652 /* In the future, maybe still need to deal with need_dasm. */
6653 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
6654 if (record_arch_list_add_end ())
6660 printf_unfiltered (_("Process record does not support instruction 0x%02x "
6661 "at address %s.\n"),
6662 (unsigned int) (opcode),
6663 paddress (gdbarch, ir.orig_addr));
6667 static const int i386_record_regmap[] =
6669 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
6670 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
6671 0, 0, 0, 0, 0, 0, 0, 0,
6672 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
6673 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
6676 /* Check that the given address appears suitable for a fast
6677 tracepoint, which on x86 means that we need an instruction of at
6678 least 5 bytes, so that we can overwrite it with a 4-byte-offset
6679 jump and not have to worry about program jumps to an address in the
6680 middle of the tracepoint jump. Returns 1 if OK, and writes a size
6681 of instruction to replace, and 0 if not, plus an explanatory
6685 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch,
6686 CORE_ADDR addr, int *isize, char **msg)
6689 static struct ui_file *gdb_null = NULL;
6691 /* This is based on the target agent using a 4-byte relative jump.
6692 Alternate future possibilities include 8-byte offset for x86-84,
6693 or 3-byte jumps if the program has trampoline space close by. */
6696 /* Dummy file descriptor for the disassembler. */
6698 gdb_null = ui_file_new ();
6700 /* Check for fit. */
6701 len = gdb_print_insn (gdbarch, addr, gdb_null, NULL);
6704 /* Return a bit of target-specific detail to add to the caller's
6705 generic failure message. */
6707 *msg = xstrprintf (_("; instruction is only %d bytes long, need at least %d bytes for the jump"),
6720 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
6721 struct tdesc_arch_data *tdesc_data)
6723 const struct target_desc *tdesc = tdep->tdesc;
6724 const struct tdesc_feature *feature_core;
6725 const struct tdesc_feature *feature_sse, *feature_avx;
6726 int i, num_regs, valid_p;
6728 if (! tdesc_has_registers (tdesc))
6731 /* Get core registers. */
6732 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
6733 if (feature_core == NULL)
6736 /* Get SSE registers. */
6737 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
6739 /* Try AVX registers. */
6740 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
6744 /* The XCR0 bits. */
6747 /* AVX register description requires SSE register description. */
6751 tdep->xcr0 = I386_XSTATE_AVX_MASK;
6753 /* It may have been set by OSABI initialization function. */
6754 if (tdep->num_ymm_regs == 0)
6756 tdep->ymmh_register_names = i386_ymmh_names;
6757 tdep->num_ymm_regs = 8;
6758 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
6761 for (i = 0; i < tdep->num_ymm_regs; i++)
6762 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
6763 tdep->ymm0h_regnum + i,
6764 tdep->ymmh_register_names[i]);
6766 else if (feature_sse)
6767 tdep->xcr0 = I386_XSTATE_SSE_MASK;
6770 tdep->xcr0 = I386_XSTATE_X87_MASK;
6771 tdep->num_xmm_regs = 0;
6774 num_regs = tdep->num_core_regs;
6775 for (i = 0; i < num_regs; i++)
6776 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
6777 tdep->register_names[i]);
6781 /* Need to include %mxcsr, so add one. */
6782 num_regs += tdep->num_xmm_regs + 1;
6783 for (; i < num_regs; i++)
6784 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
6785 tdep->register_names[i]);
6792 static struct gdbarch *
6793 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
6795 struct gdbarch_tdep *tdep;
6796 struct gdbarch *gdbarch;
6797 struct tdesc_arch_data *tdesc_data;
6798 const struct target_desc *tdesc;
6802 /* If there is already a candidate, use it. */
6803 arches = gdbarch_list_lookup_by_info (arches, &info);
6805 return arches->gdbarch;
6807 /* Allocate space for the new architecture. */
6808 tdep = XCALLOC (1, struct gdbarch_tdep);
6809 gdbarch = gdbarch_alloc (&info, tdep);
6811 /* General-purpose registers. */
6812 tdep->gregset = NULL;
6813 tdep->gregset_reg_offset = NULL;
6814 tdep->gregset_num_regs = I386_NUM_GREGS;
6815 tdep->sizeof_gregset = 0;
6817 /* Floating-point registers. */
6818 tdep->fpregset = NULL;
6819 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
6821 tdep->xstateregset = NULL;
6823 /* The default settings include the FPU registers, the MMX registers
6824 and the SSE registers. This can be overridden for a specific ABI
6825 by adjusting the members `st0_regnum', `mm0_regnum' and
6826 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
6827 will show up in the output of "info all-registers". */
6829 tdep->st0_regnum = I386_ST0_REGNUM;
6831 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
6832 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
6834 tdep->jb_pc_offset = -1;
6835 tdep->struct_return = pcc_struct_return;
6836 tdep->sigtramp_start = 0;
6837 tdep->sigtramp_end = 0;
6838 tdep->sigtramp_p = i386_sigtramp_p;
6839 tdep->sigcontext_addr = NULL;
6840 tdep->sc_reg_offset = NULL;
6841 tdep->sc_pc_offset = -1;
6842 tdep->sc_sp_offset = -1;
6844 tdep->xsave_xcr0_offset = -1;
6846 tdep->record_regmap = i386_record_regmap;
6848 /* The format used for `long double' on almost all i386 targets is
6849 the i387 extended floating-point format. In fact, of all targets
6850 in the GCC 2.95 tree, only OSF/1 does it different, and insists
6851 on having a `long double' that's not `long' at all. */
6852 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
6854 /* Although the i387 extended floating-point has only 80 significant
6855 bits, a `long double' actually takes up 96, probably to enforce
6857 set_gdbarch_long_double_bit (gdbarch, 96);
6859 /* Register numbers of various important registers. */
6860 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
6861 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
6862 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
6863 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
6865 /* NOTE: kettenis/20040418: GCC does have two possible register
6866 numbering schemes on the i386: dbx and SVR4. These schemes
6867 differ in how they number %ebp, %esp, %eflags, and the
6868 floating-point registers, and are implemented by the arrays
6869 dbx_register_map[] and svr4_dbx_register_map in
6870 gcc/config/i386.c. GCC also defines a third numbering scheme in
6871 gcc/config/i386.c, which it designates as the "default" register
6872 map used in 64bit mode. This last register numbering scheme is
6873 implemented in dbx64_register_map, and is used for AMD64; see
6876 Currently, each GCC i386 target always uses the same register
6877 numbering scheme across all its supported debugging formats
6878 i.e. SDB (COFF), stabs and DWARF 2. This is because
6879 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
6880 DBX_REGISTER_NUMBER macro which is defined by each target's
6881 respective config header in a manner independent of the requested
6882 output debugging format.
6884 This does not match the arrangement below, which presumes that
6885 the SDB and stabs numbering schemes differ from the DWARF and
6886 DWARF 2 ones. The reason for this arrangement is that it is
6887 likely to get the numbering scheme for the target's
6888 default/native debug format right. For targets where GCC is the
6889 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
6890 targets where the native toolchain uses a different numbering
6891 scheme for a particular debug format (stabs-in-ELF on Solaris)
6892 the defaults below will have to be overridden, like
6893 i386_elf_init_abi() does. */
6895 /* Use the dbx register numbering scheme for stabs and COFF. */
6896 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
6897 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
6899 /* Use the SVR4 register numbering scheme for DWARF 2. */
6900 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
6902 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
6903 be in use on any of the supported i386 targets. */
6905 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
6907 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
6909 /* Call dummy code. */
6910 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
6912 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
6913 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
6914 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
6916 set_gdbarch_return_value (gdbarch, i386_return_value);
6918 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
6920 /* Stack grows downward. */
6921 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
6923 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc);
6924 set_gdbarch_decr_pc_after_break (gdbarch, 1);
6925 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
6927 set_gdbarch_frame_args_skip (gdbarch, 8);
6929 set_gdbarch_print_insn (gdbarch, i386_print_insn);
6931 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
6933 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
6935 /* Add the i386 register groups. */
6936 i386_add_reggroups (gdbarch);
6937 tdep->register_reggroup_p = i386_register_reggroup_p;
6939 /* Helper for function argument information. */
6940 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
6942 /* Hook the function epilogue frame unwinder. This unwinder is
6943 appended to the list first, so that it supercedes the Dwarf
6944 unwinder in function epilogues (where the Dwarf unwinder
6945 currently fails). */
6946 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
6948 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
6949 to the list before the prologue-based unwinders, so that Dwarf
6950 CFI info will be used if it is available. */
6951 dwarf2_append_unwinders (gdbarch);
6953 frame_base_set_default (gdbarch, &i386_frame_base);
6955 /* Pseudo registers may be changed by amd64_init_abi. */
6956 set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read);
6957 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
6959 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
6960 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
6962 /* Override the normal target description method to make the AVX
6963 upper halves anonymous. */
6964 set_gdbarch_register_name (gdbarch, i386_register_name);
6966 /* Even though the default ABI only includes general-purpose registers,
6967 floating-point registers and the SSE registers, we have to leave a
6968 gap for the upper AVX registers. */
6969 set_gdbarch_num_regs (gdbarch, I386_AVX_NUM_REGS);
6971 /* Get the x86 target description from INFO. */
6972 tdesc = info.target_desc;
6973 if (! tdesc_has_registers (tdesc))
6975 tdep->tdesc = tdesc;
6977 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
6978 tdep->register_names = i386_register_names;
6980 /* No upper YMM registers. */
6981 tdep->ymmh_register_names = NULL;
6982 tdep->ymm0h_regnum = -1;
6984 tdep->num_byte_regs = 8;
6985 tdep->num_word_regs = 8;
6986 tdep->num_dword_regs = 0;
6987 tdep->num_mmx_regs = 8;
6988 tdep->num_ymm_regs = 0;
6990 tdesc_data = tdesc_data_alloc ();
6992 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
6994 /* Hook in ABI-specific overrides, if they have been registered. */
6995 info.tdep_info = (void *) tdesc_data;
6996 gdbarch_init_osabi (info, gdbarch);
6998 if (!i386_validate_tdesc_p (tdep, tdesc_data))
7000 tdesc_data_cleanup (tdesc_data);
7002 gdbarch_free (gdbarch);
7006 /* Wire in pseudo registers. Number of pseudo registers may be
7008 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
7009 + tdep->num_word_regs
7010 + tdep->num_dword_regs
7011 + tdep->num_mmx_regs
7012 + tdep->num_ymm_regs));
7014 /* Target description may be changed. */
7015 tdesc = tdep->tdesc;
7017 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
7019 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7020 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
7022 /* Make %al the first pseudo-register. */
7023 tdep->al_regnum = gdbarch_num_regs (gdbarch);
7024 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
7026 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
7027 if (tdep->num_dword_regs)
7029 /* Support dword pseudo-registesr if it hasn't been disabled, */
7030 tdep->eax_regnum = ymm0_regnum;
7031 ymm0_regnum += tdep->num_dword_regs;
7034 tdep->eax_regnum = -1;
7036 mm0_regnum = ymm0_regnum;
7037 if (tdep->num_ymm_regs)
7039 /* Support YMM pseudo-registesr if it is available, */
7040 tdep->ymm0_regnum = ymm0_regnum;
7041 mm0_regnum += tdep->num_ymm_regs;
7044 tdep->ymm0_regnum = -1;
7046 if (tdep->num_mmx_regs != 0)
7048 /* Support MMX pseudo-registesr if MMX hasn't been disabled, */
7049 tdep->mm0_regnum = mm0_regnum;
7052 tdep->mm0_regnum = -1;
7054 /* Hook in the legacy prologue-based unwinders last (fallback). */
7055 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
7056 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
7058 /* If we have a register mapping, enable the generic core file
7059 support, unless it has already been enabled. */
7060 if (tdep->gregset_reg_offset
7061 && !gdbarch_regset_from_core_section_p (gdbarch))
7062 set_gdbarch_regset_from_core_section (gdbarch,
7063 i386_regset_from_core_section);
7065 set_gdbarch_skip_permanent_breakpoint (gdbarch,
7066 i386_skip_permanent_breakpoint);
7068 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
7069 i386_fast_tracepoint_valid_at);
7074 static enum gdb_osabi
7075 i386_coff_osabi_sniffer (bfd *abfd)
7077 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
7078 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
7079 return GDB_OSABI_GO32;
7081 return GDB_OSABI_UNKNOWN;
7085 /* Provide a prototype to silence -Wmissing-prototypes. */
7086 void _initialize_i386_tdep (void);
7089 _initialize_i386_tdep (void)
7091 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
7093 /* Add the variable that controls the disassembly flavor. */
7094 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
7095 &disassembly_flavor, _("\
7096 Set the disassembly flavor."), _("\
7097 Show the disassembly flavor."), _("\
7098 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7100 NULL, /* FIXME: i18n: */
7101 &setlist, &showlist);
7103 /* Add the variable that controls the convention for returning
7105 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
7106 &struct_convention, _("\
7107 Set the convention for returning small structs."), _("\
7108 Show the convention for returning small structs."), _("\
7109 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7112 NULL, /* FIXME: i18n: */
7113 &setlist, &showlist);
7115 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
7116 i386_coff_osabi_sniffer);
7118 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
7119 i386_svr4_init_abi);
7120 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
7121 i386_go32_init_abi);
7123 /* Initialize the i386-specific register groups. */
7124 i386_init_reggroups ();
7126 /* Initialize the standard target descriptions. */
7127 initialize_tdesc_i386 ();
7128 initialize_tdesc_i386_mmx ();
7129 initialize_tdesc_i386_avx ();
7131 /* Tell remote stub that we support XML target description. */
7132 register_remote_support_xml ("i386");