1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2019 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
27 #include "frame-base.h"
28 #include "frame-unwind.h"
37 #include "reggroups.h"
42 #include "target-float.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "common/x86-xstate.h"
53 #include "record-full.h"
54 #include "target-descriptions.h"
55 #include "arch/i386.h"
60 #include "stap-probe.h"
61 #include "user-regs.h"
62 #include "cli/cli-utils.h"
63 #include "expression.h"
64 #include "parser-defs.h"
67 #include <unordered_set>
71 static const char *i386_register_names[] =
73 "eax", "ecx", "edx", "ebx",
74 "esp", "ebp", "esi", "edi",
75 "eip", "eflags", "cs", "ss",
76 "ds", "es", "fs", "gs",
77 "st0", "st1", "st2", "st3",
78 "st4", "st5", "st6", "st7",
79 "fctrl", "fstat", "ftag", "fiseg",
80 "fioff", "foseg", "fooff", "fop",
81 "xmm0", "xmm1", "xmm2", "xmm3",
82 "xmm4", "xmm5", "xmm6", "xmm7",
86 static const char *i386_zmm_names[] =
88 "zmm0", "zmm1", "zmm2", "zmm3",
89 "zmm4", "zmm5", "zmm6", "zmm7"
92 static const char *i386_zmmh_names[] =
94 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
95 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
98 static const char *i386_k_names[] =
100 "k0", "k1", "k2", "k3",
101 "k4", "k5", "k6", "k7"
104 static const char *i386_ymm_names[] =
106 "ymm0", "ymm1", "ymm2", "ymm3",
107 "ymm4", "ymm5", "ymm6", "ymm7",
110 static const char *i386_ymmh_names[] =
112 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
113 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
116 static const char *i386_mpx_names[] =
118 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
121 static const char* i386_pkeys_names[] =
126 /* Register names for MPX pseudo-registers. */
128 static const char *i386_bnd_names[] =
130 "bnd0", "bnd1", "bnd2", "bnd3"
133 /* Register names for MMX pseudo-registers. */
135 static const char *i386_mmx_names[] =
137 "mm0", "mm1", "mm2", "mm3",
138 "mm4", "mm5", "mm6", "mm7"
141 /* Register names for byte pseudo-registers. */
143 static const char *i386_byte_names[] =
145 "al", "cl", "dl", "bl",
146 "ah", "ch", "dh", "bh"
149 /* Register names for word pseudo-registers. */
151 static const char *i386_word_names[] =
153 "ax", "cx", "dx", "bx",
157 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
158 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
159 we have 16 upper ZMM regs that have to be handled differently. */
161 const int num_lower_zmm_regs = 16;
166 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
168 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
169 int mm0_regnum = tdep->mm0_regnum;
174 regnum -= mm0_regnum;
175 return regnum >= 0 && regnum < tdep->num_mmx_regs;
181 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
183 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
185 regnum -= tdep->al_regnum;
186 return regnum >= 0 && regnum < tdep->num_byte_regs;
192 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
194 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
196 regnum -= tdep->ax_regnum;
197 return regnum >= 0 && regnum < tdep->num_word_regs;
200 /* Dword register? */
203 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
205 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
206 int eax_regnum = tdep->eax_regnum;
211 regnum -= eax_regnum;
212 return regnum >= 0 && regnum < tdep->num_dword_regs;
215 /* AVX512 register? */
218 i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum)
220 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
221 int zmm0h_regnum = tdep->zmm0h_regnum;
223 if (zmm0h_regnum < 0)
226 regnum -= zmm0h_regnum;
227 return regnum >= 0 && regnum < tdep->num_zmm_regs;
231 i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum)
233 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
234 int zmm0_regnum = tdep->zmm0_regnum;
239 regnum -= zmm0_regnum;
240 return regnum >= 0 && regnum < tdep->num_zmm_regs;
244 i386_k_regnum_p (struct gdbarch *gdbarch, int regnum)
246 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
247 int k0_regnum = tdep->k0_regnum;
253 return regnum >= 0 && regnum < I387_NUM_K_REGS;
257 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
259 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
260 int ymm0h_regnum = tdep->ymm0h_regnum;
262 if (ymm0h_regnum < 0)
265 regnum -= ymm0h_regnum;
266 return regnum >= 0 && regnum < tdep->num_ymm_regs;
272 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
274 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
275 int ymm0_regnum = tdep->ymm0_regnum;
280 regnum -= ymm0_regnum;
281 return regnum >= 0 && regnum < tdep->num_ymm_regs;
285 i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
287 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
288 int ymm16h_regnum = tdep->ymm16h_regnum;
290 if (ymm16h_regnum < 0)
293 regnum -= ymm16h_regnum;
294 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
298 i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
300 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
301 int ymm16_regnum = tdep->ymm16_regnum;
303 if (ymm16_regnum < 0)
306 regnum -= ymm16_regnum;
307 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
313 i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum)
315 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
316 int bnd0_regnum = tdep->bnd0_regnum;
321 regnum -= bnd0_regnum;
322 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
328 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
330 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
331 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
333 if (num_xmm_regs == 0)
336 regnum -= I387_XMM0_REGNUM (tdep);
337 return regnum >= 0 && regnum < num_xmm_regs;
340 /* XMM_512 register? */
343 i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
345 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
346 int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep);
348 if (num_xmm_avx512_regs == 0)
351 regnum -= I387_XMM16_REGNUM (tdep);
352 return regnum >= 0 && regnum < num_xmm_avx512_regs;
356 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
358 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
360 if (I387_NUM_XMM_REGS (tdep) == 0)
363 return (regnum == I387_MXCSR_REGNUM (tdep));
369 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
371 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
373 if (I387_ST0_REGNUM (tdep) < 0)
376 return (I387_ST0_REGNUM (tdep) <= regnum
377 && regnum < I387_FCTRL_REGNUM (tdep));
381 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
383 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
385 if (I387_ST0_REGNUM (tdep) < 0)
388 return (I387_FCTRL_REGNUM (tdep) <= regnum
389 && regnum < I387_XMM0_REGNUM (tdep));
392 /* BNDr (raw) register? */
395 i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum)
397 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
399 if (I387_BND0R_REGNUM (tdep) < 0)
402 regnum -= tdep->bnd0r_regnum;
403 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
406 /* BND control register? */
409 i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum)
411 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
413 if (I387_BNDCFGU_REGNUM (tdep) < 0)
416 regnum -= I387_BNDCFGU_REGNUM (tdep);
417 return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS;
423 i386_pkru_regnum_p (struct gdbarch *gdbarch, int regnum)
425 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
426 int pkru_regnum = tdep->pkru_regnum;
431 regnum -= pkru_regnum;
432 return regnum >= 0 && regnum < I387_NUM_PKEYS_REGS;
435 /* Return the name of register REGNUM, or the empty string if it is
436 an anonymous register. */
439 i386_register_name (struct gdbarch *gdbarch, int regnum)
441 /* Hide the upper YMM registers. */
442 if (i386_ymmh_regnum_p (gdbarch, regnum))
445 /* Hide the upper YMM16-31 registers. */
446 if (i386_ymmh_avx512_regnum_p (gdbarch, regnum))
449 /* Hide the upper ZMM registers. */
450 if (i386_zmmh_regnum_p (gdbarch, regnum))
453 return tdesc_register_name (gdbarch, regnum);
456 /* Return the name of register REGNUM. */
459 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
461 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
462 if (i386_bnd_regnum_p (gdbarch, regnum))
463 return i386_bnd_names[regnum - tdep->bnd0_regnum];
464 if (i386_mmx_regnum_p (gdbarch, regnum))
465 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
466 else if (i386_ymm_regnum_p (gdbarch, regnum))
467 return i386_ymm_names[regnum - tdep->ymm0_regnum];
468 else if (i386_zmm_regnum_p (gdbarch, regnum))
469 return i386_zmm_names[regnum - tdep->zmm0_regnum];
470 else if (i386_byte_regnum_p (gdbarch, regnum))
471 return i386_byte_names[regnum - tdep->al_regnum];
472 else if (i386_word_regnum_p (gdbarch, regnum))
473 return i386_word_names[regnum - tdep->ax_regnum];
475 internal_error (__FILE__, __LINE__, _("invalid regnum"));
478 /* Convert a dbx register number REG to the appropriate register
479 number used by GDB. */
482 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
484 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
486 /* This implements what GCC calls the "default" register map
487 (dbx_register_map[]). */
489 if (reg >= 0 && reg <= 7)
491 /* General-purpose registers. The debug info calls %ebp
492 register 4, and %esp register 5. */
499 else if (reg >= 12 && reg <= 19)
501 /* Floating-point registers. */
502 return reg - 12 + I387_ST0_REGNUM (tdep);
504 else if (reg >= 21 && reg <= 28)
507 int ymm0_regnum = tdep->ymm0_regnum;
510 && i386_xmm_regnum_p (gdbarch, reg))
511 return reg - 21 + ymm0_regnum;
513 return reg - 21 + I387_XMM0_REGNUM (tdep);
515 else if (reg >= 29 && reg <= 36)
518 return reg - 29 + I387_MM0_REGNUM (tdep);
521 /* This will hopefully provoke a warning. */
522 return gdbarch_num_cooked_regs (gdbarch);
525 /* Convert SVR4 DWARF register number REG to the appropriate register number
529 i386_svr4_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
531 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
533 /* This implements the GCC register map that tries to be compatible
534 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
536 /* The SVR4 register numbering includes %eip and %eflags, and
537 numbers the floating point registers differently. */
538 if (reg >= 0 && reg <= 9)
540 /* General-purpose registers. */
543 else if (reg >= 11 && reg <= 18)
545 /* Floating-point registers. */
546 return reg - 11 + I387_ST0_REGNUM (tdep);
548 else if (reg >= 21 && reg <= 36)
550 /* The SSE and MMX registers have the same numbers as with dbx. */
551 return i386_dbx_reg_to_regnum (gdbarch, reg);
556 case 37: return I387_FCTRL_REGNUM (tdep);
557 case 38: return I387_FSTAT_REGNUM (tdep);
558 case 39: return I387_MXCSR_REGNUM (tdep);
559 case 40: return I386_ES_REGNUM;
560 case 41: return I386_CS_REGNUM;
561 case 42: return I386_SS_REGNUM;
562 case 43: return I386_DS_REGNUM;
563 case 44: return I386_FS_REGNUM;
564 case 45: return I386_GS_REGNUM;
570 /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return
571 num_regs + num_pseudo_regs for other debug formats. */
574 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
576 int regnum = i386_svr4_dwarf_reg_to_regnum (gdbarch, reg);
579 return gdbarch_num_cooked_regs (gdbarch);
585 /* This is the variable that is set with "set disassembly-flavor", and
586 its legitimate values. */
587 static const char att_flavor[] = "att";
588 static const char intel_flavor[] = "intel";
589 static const char *const valid_flavors[] =
595 static const char *disassembly_flavor = att_flavor;
598 /* Use the program counter to determine the contents and size of a
599 breakpoint instruction. Return a pointer to a string of bytes that
600 encode a breakpoint instruction, store the length of the string in
601 *LEN and optionally adjust *PC to point to the correct memory
602 location for inserting the breakpoint.
604 On the i386 we have a single breakpoint that fits in a single byte
605 and can be inserted anywhere.
607 This function is 64-bit safe. */
609 constexpr gdb_byte i386_break_insn[] = { 0xcc }; /* int 3 */
611 typedef BP_MANIPULATION (i386_break_insn) i386_breakpoint;
614 /* Displaced instruction handling. */
616 /* Skip the legacy instruction prefixes in INSN.
617 Not all prefixes are valid for any particular insn
618 but we needn't care, the insn will fault if it's invalid.
619 The result is a pointer to the first opcode byte,
620 or NULL if we run off the end of the buffer. */
623 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
625 gdb_byte *end = insn + max_len;
631 case DATA_PREFIX_OPCODE:
632 case ADDR_PREFIX_OPCODE:
633 case CS_PREFIX_OPCODE:
634 case DS_PREFIX_OPCODE:
635 case ES_PREFIX_OPCODE:
636 case FS_PREFIX_OPCODE:
637 case GS_PREFIX_OPCODE:
638 case SS_PREFIX_OPCODE:
639 case LOCK_PREFIX_OPCODE:
640 case REPE_PREFIX_OPCODE:
641 case REPNE_PREFIX_OPCODE:
653 i386_absolute_jmp_p (const gdb_byte *insn)
655 /* jmp far (absolute address in operand). */
661 /* jump near, absolute indirect (/4). */
662 if ((insn[1] & 0x38) == 0x20)
665 /* jump far, absolute indirect (/5). */
666 if ((insn[1] & 0x38) == 0x28)
673 /* Return non-zero if INSN is a jump, zero otherwise. */
676 i386_jmp_p (const gdb_byte *insn)
678 /* jump short, relative. */
682 /* jump near, relative. */
686 return i386_absolute_jmp_p (insn);
690 i386_absolute_call_p (const gdb_byte *insn)
692 /* call far, absolute. */
698 /* Call near, absolute indirect (/2). */
699 if ((insn[1] & 0x38) == 0x10)
702 /* Call far, absolute indirect (/3). */
703 if ((insn[1] & 0x38) == 0x18)
711 i386_ret_p (const gdb_byte *insn)
715 case 0xc2: /* ret near, pop N bytes. */
716 case 0xc3: /* ret near */
717 case 0xca: /* ret far, pop N bytes. */
718 case 0xcb: /* ret far */
719 case 0xcf: /* iret */
728 i386_call_p (const gdb_byte *insn)
730 if (i386_absolute_call_p (insn))
733 /* call near, relative. */
740 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
741 length in bytes. Otherwise, return zero. */
744 i386_syscall_p (const gdb_byte *insn, int *lengthp)
746 /* Is it 'int $0x80'? */
747 if ((insn[0] == 0xcd && insn[1] == 0x80)
748 /* Or is it 'sysenter'? */
749 || (insn[0] == 0x0f && insn[1] == 0x34)
750 /* Or is it 'syscall'? */
751 || (insn[0] == 0x0f && insn[1] == 0x05))
760 /* The gdbarch insn_is_call method. */
763 i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
765 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
767 read_code (addr, buf, I386_MAX_INSN_LEN);
768 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
770 return i386_call_p (insn);
773 /* The gdbarch insn_is_ret method. */
776 i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
778 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
780 read_code (addr, buf, I386_MAX_INSN_LEN);
781 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
783 return i386_ret_p (insn);
786 /* The gdbarch insn_is_jump method. */
789 i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
791 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
793 read_code (addr, buf, I386_MAX_INSN_LEN);
794 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
796 return i386_jmp_p (insn);
799 /* Some kernels may run one past a syscall insn, so we have to cope. */
801 struct displaced_step_closure *
802 i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
803 CORE_ADDR from, CORE_ADDR to,
804 struct regcache *regs)
806 size_t len = gdbarch_max_insn_length (gdbarch);
807 i386_displaced_step_closure *closure = new i386_displaced_step_closure (len);
808 gdb_byte *buf = closure->buf.data ();
810 read_memory (from, buf, len);
812 /* GDB may get control back after the insn after the syscall.
813 Presumably this is a kernel bug.
814 If this is a syscall, make sure there's a nop afterwards. */
819 insn = i386_skip_prefixes (buf, len);
820 if (insn != NULL && i386_syscall_p (insn, &syscall_length))
821 insn[syscall_length] = NOP_OPCODE;
824 write_memory (to, buf, len);
828 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
829 paddress (gdbarch, from), paddress (gdbarch, to));
830 displaced_step_dump_bytes (gdb_stdlog, buf, len);
836 /* Fix up the state of registers and memory after having single-stepped
837 a displaced instruction. */
840 i386_displaced_step_fixup (struct gdbarch *gdbarch,
841 struct displaced_step_closure *closure_,
842 CORE_ADDR from, CORE_ADDR to,
843 struct regcache *regs)
845 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
847 /* The offset we applied to the instruction's address.
848 This could well be negative (when viewed as a signed 32-bit
849 value), but ULONGEST won't reflect that, so take care when
851 ULONGEST insn_offset = to - from;
853 i386_displaced_step_closure *closure
854 = (i386_displaced_step_closure *) closure_;
855 gdb_byte *insn = closure->buf.data ();
856 /* The start of the insn, needed in case we see some prefixes. */
857 gdb_byte *insn_start = insn;
860 fprintf_unfiltered (gdb_stdlog,
861 "displaced: fixup (%s, %s), "
862 "insn = 0x%02x 0x%02x ...\n",
863 paddress (gdbarch, from), paddress (gdbarch, to),
866 /* The list of issues to contend with here is taken from
867 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
868 Yay for Free Software! */
870 /* Relocate the %eip, if necessary. */
872 /* The instruction recognizers we use assume any leading prefixes
873 have been skipped. */
875 /* This is the size of the buffer in closure. */
876 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
877 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
878 /* If there are too many prefixes, just ignore the insn.
879 It will fault when run. */
884 /* Except in the case of absolute or indirect jump or call
885 instructions, or a return instruction, the new eip is relative to
886 the displaced instruction; make it relative. Well, signal
887 handler returns don't need relocation either, but we use the
888 value of %eip to recognize those; see below. */
889 if (! i386_absolute_jmp_p (insn)
890 && ! i386_absolute_call_p (insn)
891 && ! i386_ret_p (insn))
896 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
898 /* A signal trampoline system call changes the %eip, resuming
899 execution of the main program after the signal handler has
900 returned. That makes them like 'return' instructions; we
901 shouldn't relocate %eip.
903 But most system calls don't, and we do need to relocate %eip.
905 Our heuristic for distinguishing these cases: if stepping
906 over the system call instruction left control directly after
907 the instruction, the we relocate --- control almost certainly
908 doesn't belong in the displaced copy. Otherwise, we assume
909 the instruction has put control where it belongs, and leave
910 it unrelocated. Goodness help us if there are PC-relative
912 if (i386_syscall_p (insn, &insn_len)
913 && orig_eip != to + (insn - insn_start) + insn_len
914 /* GDB can get control back after the insn after the syscall.
915 Presumably this is a kernel bug.
916 i386_displaced_step_copy_insn ensures its a nop,
917 we add one to the length for it. */
918 && orig_eip != to + (insn - insn_start) + insn_len + 1)
921 fprintf_unfiltered (gdb_stdlog,
922 "displaced: syscall changed %%eip; "
927 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
929 /* If we just stepped over a breakpoint insn, we don't backup
930 the pc on purpose; this is to match behaviour without
933 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
936 fprintf_unfiltered (gdb_stdlog,
938 "relocated %%eip from %s to %s\n",
939 paddress (gdbarch, orig_eip),
940 paddress (gdbarch, eip));
944 /* If the instruction was PUSHFL, then the TF bit will be set in the
945 pushed value, and should be cleared. We'll leave this for later,
946 since GDB already messes up the TF flag when stepping over a
949 /* If the instruction was a call, the return address now atop the
950 stack is the address following the copied instruction. We need
951 to make it the address following the original instruction. */
952 if (i386_call_p (insn))
956 const ULONGEST retaddr_len = 4;
958 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
959 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
960 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
961 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
964 fprintf_unfiltered (gdb_stdlog,
965 "displaced: relocated return addr at %s to %s\n",
966 paddress (gdbarch, esp),
967 paddress (gdbarch, retaddr));
972 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
974 target_write_memory (*to, buf, len);
979 i386_relocate_instruction (struct gdbarch *gdbarch,
980 CORE_ADDR *to, CORE_ADDR oldloc)
982 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
983 gdb_byte buf[I386_MAX_INSN_LEN];
984 int offset = 0, rel32, newrel;
986 gdb_byte *insn = buf;
988 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
990 insn_length = gdb_buffered_insn_length (gdbarch, insn,
991 I386_MAX_INSN_LEN, oldloc);
993 /* Get past the prefixes. */
994 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
996 /* Adjust calls with 32-bit relative addresses as push/jump, with
997 the address pushed being the location where the original call in
998 the user program would return to. */
1001 gdb_byte push_buf[16];
1002 unsigned int ret_addr;
1004 /* Where "ret" in the original code will return to. */
1005 ret_addr = oldloc + insn_length;
1006 push_buf[0] = 0x68; /* pushq $... */
1007 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
1008 /* Push the push. */
1009 append_insns (to, 5, push_buf);
1011 /* Convert the relative call to a relative jump. */
1014 /* Adjust the destination offset. */
1015 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1016 newrel = (oldloc - *to) + rel32;
1017 store_signed_integer (insn + 1, 4, byte_order, newrel);
1019 if (debug_displaced)
1020 fprintf_unfiltered (gdb_stdlog,
1021 "Adjusted insn rel32=%s at %s to"
1022 " rel32=%s at %s\n",
1023 hex_string (rel32), paddress (gdbarch, oldloc),
1024 hex_string (newrel), paddress (gdbarch, *to));
1026 /* Write the adjusted jump into its displaced location. */
1027 append_insns (to, 5, insn);
1031 /* Adjust jumps with 32-bit relative addresses. Calls are already
1033 if (insn[0] == 0xe9)
1035 /* Adjust conditional jumps. */
1036 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1041 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1042 newrel = (oldloc - *to) + rel32;
1043 store_signed_integer (insn + offset, 4, byte_order, newrel);
1044 if (debug_displaced)
1045 fprintf_unfiltered (gdb_stdlog,
1046 "Adjusted insn rel32=%s at %s to"
1047 " rel32=%s at %s\n",
1048 hex_string (rel32), paddress (gdbarch, oldloc),
1049 hex_string (newrel), paddress (gdbarch, *to));
1052 /* Write the adjusted instructions into their displaced
1054 append_insns (to, insn_length, buf);
1058 #ifdef I386_REGNO_TO_SYMMETRY
1059 #error "The Sequent Symmetry is no longer supported."
1062 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1063 and %esp "belong" to the calling function. Therefore these
1064 registers should be saved if they're going to be modified. */
1066 /* The maximum number of saved registers. This should include all
1067 registers mentioned above, and %eip. */
1068 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1070 struct i386_frame_cache
1078 /* Saved registers. */
1079 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
1084 /* Stack space reserved for local variables. */
1088 /* Allocate and initialize a frame cache. */
1090 static struct i386_frame_cache *
1091 i386_alloc_frame_cache (void)
1093 struct i386_frame_cache *cache;
1096 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
1101 cache->sp_offset = -4;
1104 /* Saved registers. We initialize these to -1 since zero is a valid
1105 offset (that's where %ebp is supposed to be stored). */
1106 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1107 cache->saved_regs[i] = -1;
1108 cache->saved_sp = 0;
1109 cache->saved_sp_reg = -1;
1110 cache->pc_in_eax = 0;
1112 /* Frameless until proven otherwise. */
1118 /* If the instruction at PC is a jump, return the address of its
1119 target. Otherwise, return PC. */
1122 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
1124 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1129 if (target_read_code (pc, &op, 1))
1136 op = read_code_unsigned_integer (pc + 1, 1, byte_order);
1142 /* Relative jump: if data16 == 0, disp32, else disp16. */
1145 delta = read_memory_integer (pc + 2, 2, byte_order);
1147 /* Include the size of the jmp instruction (including the
1153 delta = read_memory_integer (pc + 1, 4, byte_order);
1155 /* Include the size of the jmp instruction. */
1160 /* Relative jump, disp8 (ignore data16). */
1161 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
1163 delta += data16 + 2;
1170 /* Check whether PC points at a prologue for a function returning a
1171 structure or union. If so, it updates CACHE and returns the
1172 address of the first instruction after the code sequence that
1173 removes the "hidden" argument from the stack or CURRENT_PC,
1174 whichever is smaller. Otherwise, return PC. */
1177 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
1178 struct i386_frame_cache *cache)
1180 /* Functions that return a structure or union start with:
1183 xchgl %eax, (%esp) 0x87 0x04 0x24
1184 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1186 (the System V compiler puts out the second `xchg' instruction,
1187 and the assembler doesn't try to optimize it, so the 'sib' form
1188 gets generated). This sequence is used to get the address of the
1189 return buffer for a function that returns a structure. */
1190 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
1191 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
1195 if (current_pc <= pc)
1198 if (target_read_code (pc, &op, 1))
1201 if (op != 0x58) /* popl %eax */
1204 if (target_read_code (pc + 1, buf, 4))
1207 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
1210 if (current_pc == pc)
1212 cache->sp_offset += 4;
1216 if (current_pc == pc + 1)
1218 cache->pc_in_eax = 1;
1222 if (buf[1] == proto1[1])
1229 i386_skip_probe (CORE_ADDR pc)
1231 /* A function may start with
1245 if (target_read_code (pc, &op, 1))
1248 if (op == 0x68 || op == 0x6a)
1252 /* Skip past the `pushl' instruction; it has either a one-byte or a
1253 four-byte operand, depending on the opcode. */
1259 /* Read the following 8 bytes, which should be `call _probe' (6
1260 bytes) followed by `addl $4,%esp' (2 bytes). */
1261 read_memory (pc + delta, buf, sizeof (buf));
1262 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
1263 pc += delta + sizeof (buf);
1269 /* GCC 4.1 and later, can put code in the prologue to realign the
1270 stack pointer. Check whether PC points to such code, and update
1271 CACHE accordingly. Return the first instruction after the code
1272 sequence or CURRENT_PC, whichever is smaller. If we don't
1273 recognize the code, return PC. */
1276 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1277 struct i386_frame_cache *cache)
1279 /* There are 2 code sequences to re-align stack before the frame
1282 1. Use a caller-saved saved register:
1288 2. Use a callee-saved saved register:
1295 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1297 0x83 0xe4 0xf0 andl $-16, %esp
1298 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1303 int offset, offset_and;
1304 static int regnums[8] = {
1305 I386_EAX_REGNUM, /* %eax */
1306 I386_ECX_REGNUM, /* %ecx */
1307 I386_EDX_REGNUM, /* %edx */
1308 I386_EBX_REGNUM, /* %ebx */
1309 I386_ESP_REGNUM, /* %esp */
1310 I386_EBP_REGNUM, /* %ebp */
1311 I386_ESI_REGNUM, /* %esi */
1312 I386_EDI_REGNUM /* %edi */
1315 if (target_read_code (pc, buf, sizeof buf))
1318 /* Check caller-saved saved register. The first instruction has
1319 to be "leal 4(%esp), %reg". */
1320 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1322 /* MOD must be binary 10 and R/M must be binary 100. */
1323 if ((buf[1] & 0xc7) != 0x44)
1326 /* REG has register number. */
1327 reg = (buf[1] >> 3) & 7;
1332 /* Check callee-saved saved register. The first instruction
1333 has to be "pushl %reg". */
1334 if ((buf[0] & 0xf8) != 0x50)
1340 /* The next instruction has to be "leal 8(%esp), %reg". */
1341 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1344 /* MOD must be binary 10 and R/M must be binary 100. */
1345 if ((buf[2] & 0xc7) != 0x44)
1348 /* REG has register number. Registers in pushl and leal have to
1350 if (reg != ((buf[2] >> 3) & 7))
1356 /* Rigister can't be %esp nor %ebp. */
1357 if (reg == 4 || reg == 5)
1360 /* The next instruction has to be "andl $-XXX, %esp". */
1361 if (buf[offset + 1] != 0xe4
1362 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1365 offset_and = offset;
1366 offset += buf[offset] == 0x81 ? 6 : 3;
1368 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1369 0xfc. REG must be binary 110 and MOD must be binary 01. */
1370 if (buf[offset] != 0xff
1371 || buf[offset + 2] != 0xfc
1372 || (buf[offset + 1] & 0xf8) != 0x70)
1375 /* R/M has register. Registers in leal and pushl have to be the
1377 if (reg != (buf[offset + 1] & 7))
1380 if (current_pc > pc + offset_and)
1381 cache->saved_sp_reg = regnums[reg];
1383 return std::min (pc + offset + 3, current_pc);
1386 /* Maximum instruction length we need to handle. */
1387 #define I386_MAX_MATCHED_INSN_LEN 6
1389 /* Instruction description. */
1393 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
1394 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
1397 /* Return whether instruction at PC matches PATTERN. */
1400 i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern)
1404 if (target_read_code (pc, &op, 1))
1407 if ((op & pattern.mask[0]) == pattern.insn[0])
1409 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1410 int insn_matched = 1;
1413 gdb_assert (pattern.len > 1);
1414 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN);
1416 if (target_read_code (pc + 1, buf, pattern.len - 1))
1419 for (i = 1; i < pattern.len; i++)
1421 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i])
1424 return insn_matched;
1429 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1430 the first instruction description that matches. Otherwise, return
1433 static struct i386_insn *
1434 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns)
1436 struct i386_insn *pattern;
1438 for (pattern = insn_patterns; pattern->len > 0; pattern++)
1440 if (i386_match_pattern (pc, *pattern))
1447 /* Return whether PC points inside a sequence of instructions that
1448 matches INSN_PATTERNS. */
1451 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns)
1453 CORE_ADDR current_pc;
1455 struct i386_insn *insn;
1457 insn = i386_match_insn (pc, insn_patterns);
1462 ix = insn - insn_patterns;
1463 for (i = ix - 1; i >= 0; i--)
1465 current_pc -= insn_patterns[i].len;
1467 if (!i386_match_pattern (current_pc, insn_patterns[i]))
1471 current_pc = pc + insn->len;
1472 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++)
1474 if (!i386_match_pattern (current_pc, *insn))
1477 current_pc += insn->len;
1483 /* Some special instructions that might be migrated by GCC into the
1484 part of the prologue that sets up the new stack frame. Because the
1485 stack frame hasn't been setup yet, no registers have been saved
1486 yet, and only the scratch registers %eax, %ecx and %edx can be
1489 struct i386_insn i386_frame_setup_skip_insns[] =
1491 /* Check for `movb imm8, r' and `movl imm32, r'.
1493 ??? Should we handle 16-bit operand-sizes here? */
1495 /* `movb imm8, %al' and `movb imm8, %ah' */
1496 /* `movb imm8, %cl' and `movb imm8, %ch' */
1497 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1498 /* `movb imm8, %dl' and `movb imm8, %dh' */
1499 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1500 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1501 { 5, { 0xb8 }, { 0xfe } },
1502 /* `movl imm32, %edx' */
1503 { 5, { 0xba }, { 0xff } },
1505 /* Check for `mov imm32, r32'. Note that there is an alternative
1506 encoding for `mov m32, %eax'.
1508 ??? Should we handle SIB adressing here?
1509 ??? Should we handle 16-bit operand-sizes here? */
1511 /* `movl m32, %eax' */
1512 { 5, { 0xa1 }, { 0xff } },
1513 /* `movl m32, %eax' and `mov; m32, %ecx' */
1514 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1515 /* `movl m32, %edx' */
1516 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1518 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1519 Because of the symmetry, there are actually two ways to encode
1520 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1521 opcode bytes 0x31 and 0x33 for `xorl'. */
1523 /* `subl %eax, %eax' */
1524 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1525 /* `subl %ecx, %ecx' */
1526 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1527 /* `subl %edx, %edx' */
1528 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1529 /* `xorl %eax, %eax' */
1530 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1531 /* `xorl %ecx, %ecx' */
1532 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1533 /* `xorl %edx, %edx' */
1534 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1539 /* Check whether PC points to a no-op instruction. */
1541 i386_skip_noop (CORE_ADDR pc)
1546 if (target_read_code (pc, &op, 1))
1552 /* Ignore `nop' instruction. */
1556 if (target_read_code (pc, &op, 1))
1560 /* Ignore no-op instruction `mov %edi, %edi'.
1561 Microsoft system dlls often start with
1562 a `mov %edi,%edi' instruction.
1563 The 5 bytes before the function start are
1564 filled with `nop' instructions.
1565 This pattern can be used for hot-patching:
1566 The `mov %edi, %edi' instruction can be replaced by a
1567 near jump to the location of the 5 `nop' instructions
1568 which can be replaced by a 32-bit jump to anywhere
1569 in the 32-bit address space. */
1571 else if (op == 0x8b)
1573 if (target_read_code (pc + 1, &op, 1))
1579 if (target_read_code (pc, &op, 1))
1589 /* Check whether PC points at a code that sets up a new stack frame.
1590 If so, it updates CACHE and returns the address of the first
1591 instruction after the sequence that sets up the frame or LIMIT,
1592 whichever is smaller. If we don't recognize the code, return PC. */
1595 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1596 CORE_ADDR pc, CORE_ADDR limit,
1597 struct i386_frame_cache *cache)
1599 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1600 struct i386_insn *insn;
1607 if (target_read_code (pc, &op, 1))
1610 if (op == 0x55) /* pushl %ebp */
1612 /* Take into account that we've executed the `pushl %ebp' that
1613 starts this instruction sequence. */
1614 cache->saved_regs[I386_EBP_REGNUM] = 0;
1615 cache->sp_offset += 4;
1618 /* If that's all, return now. */
1622 /* Check for some special instructions that might be migrated by
1623 GCC into the prologue and skip them. At this point in the
1624 prologue, code should only touch the scratch registers %eax,
1625 %ecx and %edx, so while the number of posibilities is sheer,
1628 Make sure we only skip these instructions if we later see the
1629 `movl %esp, %ebp' that actually sets up the frame. */
1630 while (pc + skip < limit)
1632 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1639 /* If that's all, return now. */
1640 if (limit <= pc + skip)
1643 if (target_read_code (pc + skip, &op, 1))
1646 /* The i386 prologue looks like
1652 and a different prologue can be generated for atom.
1656 lea -0x10(%esp),%esp
1658 We handle both of them here. */
1662 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1664 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1670 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1675 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1676 if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order)
1685 /* OK, we actually have a frame. We just don't know how large
1686 it is yet. Set its size to zero. We'll adjust it if
1687 necessary. We also now commit to skipping the special
1688 instructions mentioned before. */
1691 /* If that's all, return now. */
1695 /* Check for stack adjustment
1701 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1702 reg, so we don't have to worry about a data16 prefix. */
1703 if (target_read_code (pc, &op, 1))
1707 /* `subl' with 8-bit immediate. */
1708 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1709 /* Some instruction starting with 0x83 other than `subl'. */
1712 /* `subl' with signed 8-bit immediate (though it wouldn't
1713 make sense to be negative). */
1714 cache->locals = read_code_integer (pc + 2, 1, byte_order);
1717 else if (op == 0x81)
1719 /* Maybe it is `subl' with a 32-bit immediate. */
1720 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1721 /* Some instruction starting with 0x81 other than `subl'. */
1724 /* It is `subl' with a 32-bit immediate. */
1725 cache->locals = read_code_integer (pc + 2, 4, byte_order);
1728 else if (op == 0x8d)
1730 /* The ModR/M byte is 0x64. */
1731 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64)
1733 /* 'lea' with 8-bit displacement. */
1734 cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order);
1739 /* Some instruction other than `subl' nor 'lea'. */
1743 else if (op == 0xc8) /* enter */
1745 cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order);
1752 /* Check whether PC points at code that saves registers on the stack.
1753 If so, it updates CACHE and returns the address of the first
1754 instruction after the register saves or CURRENT_PC, whichever is
1755 smaller. Otherwise, return PC. */
1758 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1759 struct i386_frame_cache *cache)
1761 CORE_ADDR offset = 0;
1765 if (cache->locals > 0)
1766 offset -= cache->locals;
1767 for (i = 0; i < 8 && pc < current_pc; i++)
1769 if (target_read_code (pc, &op, 1))
1771 if (op < 0x50 || op > 0x57)
1775 cache->saved_regs[op - 0x50] = offset;
1776 cache->sp_offset += 4;
1783 /* Do a full analysis of the prologue at PC and update CACHE
1784 accordingly. Bail out early if CURRENT_PC is reached. Return the
1785 address where the analysis stopped.
1787 We handle these cases:
1789 The startup sequence can be at the start of the function, or the
1790 function can start with a branch to startup code at the end.
1792 %ebp can be set up with either the 'enter' instruction, or "pushl
1793 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1794 once used in the System V compiler).
1796 Local space is allocated just below the saved %ebp by either the
1797 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1798 16-bit unsigned argument for space to allocate, and the 'addl'
1799 instruction could have either a signed byte, or 32-bit immediate.
1801 Next, the registers used by this function are pushed. With the
1802 System V compiler they will always be in the order: %edi, %esi,
1803 %ebx (and sometimes a harmless bug causes it to also save but not
1804 restore %eax); however, the code below is willing to see the pushes
1805 in any order, and will handle up to 8 of them.
1807 If the setup sequence is at the end of the function, then the next
1808 instruction will be a branch back to the start. */
1811 i386_analyze_prologue (struct gdbarch *gdbarch,
1812 CORE_ADDR pc, CORE_ADDR current_pc,
1813 struct i386_frame_cache *cache)
1815 pc = i386_skip_noop (pc);
1816 pc = i386_follow_jump (gdbarch, pc);
1817 pc = i386_analyze_struct_return (pc, current_pc, cache);
1818 pc = i386_skip_probe (pc);
1819 pc = i386_analyze_stack_align (pc, current_pc, cache);
1820 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1821 return i386_analyze_register_saves (pc, current_pc, cache);
1824 /* Return PC of first real instruction. */
1827 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1829 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1831 static gdb_byte pic_pat[6] =
1833 0xe8, 0, 0, 0, 0, /* call 0x0 */
1834 0x5b, /* popl %ebx */
1836 struct i386_frame_cache cache;
1840 CORE_ADDR func_addr;
1842 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
1844 CORE_ADDR post_prologue_pc
1845 = skip_prologue_using_sal (gdbarch, func_addr);
1846 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
1848 /* Clang always emits a line note before the prologue and another
1849 one after. We trust clang to emit usable line notes. */
1850 if (post_prologue_pc
1852 && COMPUNIT_PRODUCER (cust) != NULL
1853 && startswith (COMPUNIT_PRODUCER (cust), "clang ")))
1854 return std::max (start_pc, post_prologue_pc);
1858 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1859 if (cache.locals < 0)
1862 /* Found valid frame setup. */
1864 /* The native cc on SVR4 in -K PIC mode inserts the following code
1865 to get the address of the global offset table (GOT) into register
1870 movl %ebx,x(%ebp) (optional)
1873 This code is with the rest of the prologue (at the end of the
1874 function), so we have to skip it to get to the first real
1875 instruction at the start of the function. */
1877 for (i = 0; i < 6; i++)
1879 if (target_read_code (pc + i, &op, 1))
1882 if (pic_pat[i] != op)
1889 if (target_read_code (pc + delta, &op, 1))
1892 if (op == 0x89) /* movl %ebx, x(%ebp) */
1894 op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order);
1896 if (op == 0x5d) /* One byte offset from %ebp. */
1898 else if (op == 0x9d) /* Four byte offset from %ebp. */
1900 else /* Unexpected instruction. */
1903 if (target_read_code (pc + delta, &op, 1))
1908 if (delta > 0 && op == 0x81
1909 && read_code_unsigned_integer (pc + delta + 1, 1, byte_order)
1916 /* If the function starts with a branch (to startup code at the end)
1917 the last instruction should bring us back to the first
1918 instruction of the real code. */
1919 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1920 pc = i386_follow_jump (gdbarch, pc);
1925 /* Check that the code pointed to by PC corresponds to a call to
1926 __main, skip it if so. Return PC otherwise. */
1929 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1931 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1934 if (target_read_code (pc, &op, 1))
1940 if (target_read_code (pc + 1, buf, sizeof buf) == 0)
1942 /* Make sure address is computed correctly as a 32bit
1943 integer even if CORE_ADDR is 64 bit wide. */
1944 struct bound_minimal_symbol s;
1945 CORE_ADDR call_dest;
1947 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1948 call_dest = call_dest & 0xffffffffU;
1949 s = lookup_minimal_symbol_by_pc (call_dest);
1950 if (s.minsym != NULL
1951 && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL
1952 && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0)
1960 /* This function is 64-bit safe. */
1963 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1967 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1968 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1972 /* Normal frames. */
1975 i386_frame_cache_1 (struct frame_info *this_frame,
1976 struct i386_frame_cache *cache)
1978 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1979 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1983 cache->pc = get_frame_func (this_frame);
1985 /* In principle, for normal frames, %ebp holds the frame pointer,
1986 which holds the base address for the current stack frame.
1987 However, for functions that don't need it, the frame pointer is
1988 optional. For these "frameless" functions the frame pointer is
1989 actually the frame pointer of the calling frame. Signal
1990 trampolines are just a special case of a "frameless" function.
1991 They (usually) share their frame pointer with the frame that was
1992 in progress when the signal occurred. */
1994 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1995 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1996 if (cache->base == 0)
2002 /* For normal frames, %eip is stored at 4(%ebp). */
2003 cache->saved_regs[I386_EIP_REGNUM] = 4;
2006 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
2009 if (cache->locals < 0)
2011 /* We didn't find a valid frame, which means that CACHE->base
2012 currently holds the frame pointer for our calling frame. If
2013 we're at the start of a function, or somewhere half-way its
2014 prologue, the function's frame probably hasn't been fully
2015 setup yet. Try to reconstruct the base address for the stack
2016 frame by looking at the stack pointer. For truly "frameless"
2017 functions this might work too. */
2019 if (cache->saved_sp_reg != -1)
2021 /* Saved stack pointer has been saved. */
2022 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2023 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2025 /* We're halfway aligning the stack. */
2026 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
2027 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
2029 /* This will be added back below. */
2030 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
2032 else if (cache->pc != 0
2033 || target_read_code (get_frame_pc (this_frame), buf, 1))
2035 /* We're in a known function, but did not find a frame
2036 setup. Assume that the function does not use %ebp.
2037 Alternatively, we may have jumped to an invalid
2038 address; in that case there is definitely no new
2040 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2041 cache->base = extract_unsigned_integer (buf, 4, byte_order)
2045 /* We're in an unknown function. We could not find the start
2046 of the function to analyze the prologue; our best option is
2047 to assume a typical frame layout with the caller's %ebp
2049 cache->saved_regs[I386_EBP_REGNUM] = 0;
2052 if (cache->saved_sp_reg != -1)
2054 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2055 register may be unavailable). */
2056 if (cache->saved_sp == 0
2057 && deprecated_frame_register_read (this_frame,
2058 cache->saved_sp_reg, buf))
2059 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2061 /* Now that we have the base address for the stack frame we can
2062 calculate the value of %esp in the calling frame. */
2063 else if (cache->saved_sp == 0)
2064 cache->saved_sp = cache->base + 8;
2066 /* Adjust all the saved registers such that they contain addresses
2067 instead of offsets. */
2068 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
2069 if (cache->saved_regs[i] != -1)
2070 cache->saved_regs[i] += cache->base;
2075 static struct i386_frame_cache *
2076 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
2078 struct i386_frame_cache *cache;
2081 return (struct i386_frame_cache *) *this_cache;
2083 cache = i386_alloc_frame_cache ();
2084 *this_cache = cache;
2088 i386_frame_cache_1 (this_frame, cache);
2090 CATCH (ex, RETURN_MASK_ERROR)
2092 if (ex.error != NOT_AVAILABLE_ERROR)
2093 throw_exception (ex);
2101 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
2102 struct frame_id *this_id)
2104 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2107 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2108 else if (cache->base == 0)
2110 /* This marks the outermost frame. */
2114 /* See the end of i386_push_dummy_call. */
2115 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2119 static enum unwind_stop_reason
2120 i386_frame_unwind_stop_reason (struct frame_info *this_frame,
2123 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2126 return UNWIND_UNAVAILABLE;
2128 /* This marks the outermost frame. */
2129 if (cache->base == 0)
2130 return UNWIND_OUTERMOST;
2132 return UNWIND_NO_REASON;
2135 static struct value *
2136 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2139 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2141 gdb_assert (regnum >= 0);
2143 /* The System V ABI says that:
2145 "The flags register contains the system flags, such as the
2146 direction flag and the carry flag. The direction flag must be
2147 set to the forward (that is, zero) direction before entry and
2148 upon exit from a function. Other user flags have no specified
2149 role in the standard calling sequence and are not preserved."
2151 To guarantee the "upon exit" part of that statement we fake a
2152 saved flags register that has its direction flag cleared.
2154 Note that GCC doesn't seem to rely on the fact that the direction
2155 flag is cleared after a function return; it always explicitly
2156 clears the flag before operations where it matters.
2158 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2159 right thing to do. The way we fake the flags register here makes
2160 it impossible to change it. */
2162 if (regnum == I386_EFLAGS_REGNUM)
2166 val = get_frame_register_unsigned (this_frame, regnum);
2168 return frame_unwind_got_constant (this_frame, regnum, val);
2171 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
2172 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
2174 if (regnum == I386_ESP_REGNUM
2175 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1))
2177 /* If the SP has been saved, but we don't know where, then this
2178 means that SAVED_SP_REG register was found unavailable back
2179 when we built the cache. */
2180 if (cache->saved_sp == 0)
2181 return frame_unwind_got_register (this_frame, regnum,
2182 cache->saved_sp_reg);
2184 return frame_unwind_got_constant (this_frame, regnum,
2188 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2189 return frame_unwind_got_memory (this_frame, regnum,
2190 cache->saved_regs[regnum]);
2192 return frame_unwind_got_register (this_frame, regnum, regnum);
2195 static const struct frame_unwind i386_frame_unwind =
2198 i386_frame_unwind_stop_reason,
2200 i386_frame_prev_register,
2202 default_frame_sniffer
2205 /* Normal frames, but in a function epilogue. */
2207 /* Implement the stack_frame_destroyed_p gdbarch method.
2209 The epilogue is defined here as the 'ret' instruction, which will
2210 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2211 the function's stack frame. */
2214 i386_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2217 struct compunit_symtab *cust;
2219 cust = find_pc_compunit_symtab (pc);
2220 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
2223 if (target_read_memory (pc, &insn, 1))
2224 return 0; /* Can't read memory at pc. */
2226 if (insn != 0xc3) /* 'ret' instruction. */
2233 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
2234 struct frame_info *this_frame,
2235 void **this_prologue_cache)
2237 if (frame_relative_level (this_frame) == 0)
2238 return i386_stack_frame_destroyed_p (get_frame_arch (this_frame),
2239 get_frame_pc (this_frame));
2244 static struct i386_frame_cache *
2245 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2247 struct i386_frame_cache *cache;
2251 return (struct i386_frame_cache *) *this_cache;
2253 cache = i386_alloc_frame_cache ();
2254 *this_cache = cache;
2258 cache->pc = get_frame_func (this_frame);
2260 /* At this point the stack looks as if we just entered the
2261 function, with the return address at the top of the
2263 sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM);
2264 cache->base = sp + cache->sp_offset;
2265 cache->saved_sp = cache->base + 8;
2266 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
2270 CATCH (ex, RETURN_MASK_ERROR)
2272 if (ex.error != NOT_AVAILABLE_ERROR)
2273 throw_exception (ex);
2280 static enum unwind_stop_reason
2281 i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2284 struct i386_frame_cache *cache =
2285 i386_epilogue_frame_cache (this_frame, this_cache);
2288 return UNWIND_UNAVAILABLE;
2290 return UNWIND_NO_REASON;
2294 i386_epilogue_frame_this_id (struct frame_info *this_frame,
2296 struct frame_id *this_id)
2298 struct i386_frame_cache *cache =
2299 i386_epilogue_frame_cache (this_frame, this_cache);
2302 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2304 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2307 static struct value *
2308 i386_epilogue_frame_prev_register (struct frame_info *this_frame,
2309 void **this_cache, int regnum)
2311 /* Make sure we've initialized the cache. */
2312 i386_epilogue_frame_cache (this_frame, this_cache);
2314 return i386_frame_prev_register (this_frame, this_cache, regnum);
2317 static const struct frame_unwind i386_epilogue_frame_unwind =
2320 i386_epilogue_frame_unwind_stop_reason,
2321 i386_epilogue_frame_this_id,
2322 i386_epilogue_frame_prev_register,
2324 i386_epilogue_frame_sniffer
2328 /* Stack-based trampolines. */
2330 /* These trampolines are used on cross x86 targets, when taking the
2331 address of a nested function. When executing these trampolines,
2332 no stack frame is set up, so we are in a similar situation as in
2333 epilogues and i386_epilogue_frame_this_id can be re-used. */
2335 /* Static chain passed in register. */
2337 struct i386_insn i386_tramp_chain_in_reg_insns[] =
2339 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2340 { 5, { 0xb8 }, { 0xfe } },
2343 { 5, { 0xe9 }, { 0xff } },
2348 /* Static chain passed on stack (when regparm=3). */
2350 struct i386_insn i386_tramp_chain_on_stack_insns[] =
2353 { 5, { 0x68 }, { 0xff } },
2356 { 5, { 0xe9 }, { 0xff } },
2361 /* Return whether PC points inside a stack trampoline. */
2364 i386_in_stack_tramp_p (CORE_ADDR pc)
2369 /* A stack trampoline is detected if no name is associated
2370 to the current pc and if it points inside a trampoline
2373 find_pc_partial_function (pc, &name, NULL, NULL);
2377 if (target_read_memory (pc, &insn, 1))
2380 if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns)
2381 && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns))
2388 i386_stack_tramp_frame_sniffer (const struct frame_unwind *self,
2389 struct frame_info *this_frame,
2392 if (frame_relative_level (this_frame) == 0)
2393 return i386_in_stack_tramp_p (get_frame_pc (this_frame));
2398 static const struct frame_unwind i386_stack_tramp_frame_unwind =
2401 i386_epilogue_frame_unwind_stop_reason,
2402 i386_epilogue_frame_this_id,
2403 i386_epilogue_frame_prev_register,
2405 i386_stack_tramp_frame_sniffer
2408 /* Generate a bytecode expression to get the value of the saved PC. */
2411 i386_gen_return_address (struct gdbarch *gdbarch,
2412 struct agent_expr *ax, struct axs_value *value,
2415 /* The following sequence assumes the traditional use of the base
2417 ax_reg (ax, I386_EBP_REGNUM);
2419 ax_simple (ax, aop_add);
2420 value->type = register_type (gdbarch, I386_EIP_REGNUM);
2421 value->kind = axs_lvalue_memory;
2425 /* Signal trampolines. */
2427 static struct i386_frame_cache *
2428 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2430 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2431 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2432 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2433 struct i386_frame_cache *cache;
2438 return (struct i386_frame_cache *) *this_cache;
2440 cache = i386_alloc_frame_cache ();
2444 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2445 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
2447 addr = tdep->sigcontext_addr (this_frame);
2448 if (tdep->sc_reg_offset)
2452 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
2454 for (i = 0; i < tdep->sc_num_regs; i++)
2455 if (tdep->sc_reg_offset[i] != -1)
2456 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2460 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
2461 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
2466 CATCH (ex, RETURN_MASK_ERROR)
2468 if (ex.error != NOT_AVAILABLE_ERROR)
2469 throw_exception (ex);
2473 *this_cache = cache;
2477 static enum unwind_stop_reason
2478 i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2481 struct i386_frame_cache *cache =
2482 i386_sigtramp_frame_cache (this_frame, this_cache);
2485 return UNWIND_UNAVAILABLE;
2487 return UNWIND_NO_REASON;
2491 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
2492 struct frame_id *this_id)
2494 struct i386_frame_cache *cache =
2495 i386_sigtramp_frame_cache (this_frame, this_cache);
2498 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2501 /* See the end of i386_push_dummy_call. */
2502 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
2506 static struct value *
2507 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
2508 void **this_cache, int regnum)
2510 /* Make sure we've initialized the cache. */
2511 i386_sigtramp_frame_cache (this_frame, this_cache);
2513 return i386_frame_prev_register (this_frame, this_cache, regnum);
2517 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
2518 struct frame_info *this_frame,
2519 void **this_prologue_cache)
2521 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2523 /* We shouldn't even bother if we don't have a sigcontext_addr
2525 if (tdep->sigcontext_addr == NULL)
2528 if (tdep->sigtramp_p != NULL)
2530 if (tdep->sigtramp_p (this_frame))
2534 if (tdep->sigtramp_start != 0)
2536 CORE_ADDR pc = get_frame_pc (this_frame);
2538 gdb_assert (tdep->sigtramp_end != 0);
2539 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2546 static const struct frame_unwind i386_sigtramp_frame_unwind =
2549 i386_sigtramp_frame_unwind_stop_reason,
2550 i386_sigtramp_frame_this_id,
2551 i386_sigtramp_frame_prev_register,
2553 i386_sigtramp_frame_sniffer
2558 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
2560 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2565 static const struct frame_base i386_frame_base =
2568 i386_frame_base_address,
2569 i386_frame_base_address,
2570 i386_frame_base_address
2573 static struct frame_id
2574 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2578 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
2580 /* See the end of i386_push_dummy_call. */
2581 return frame_id_build (fp + 8, get_frame_pc (this_frame));
2584 /* _Decimal128 function return values need 16-byte alignment on the
2588 i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2590 return sp & -(CORE_ADDR)16;
2594 /* Figure out where the longjmp will land. Slurp the args out of the
2595 stack. We expect the first arg to be a pointer to the jmp_buf
2596 structure from which we extract the address that we will land at.
2597 This address is copied into PC. This routine returns non-zero on
2601 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2604 CORE_ADDR sp, jb_addr;
2605 struct gdbarch *gdbarch = get_frame_arch (frame);
2606 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2607 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2609 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2610 longjmp will land. */
2611 if (jb_pc_offset == -1)
2614 get_frame_register (frame, I386_ESP_REGNUM, buf);
2615 sp = extract_unsigned_integer (buf, 4, byte_order);
2616 if (target_read_memory (sp + 4, buf, 4))
2619 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
2620 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
2623 *pc = extract_unsigned_integer (buf, 4, byte_order);
2628 /* Check whether TYPE must be 16-byte-aligned when passed as a
2629 function argument. 16-byte vectors, _Decimal128 and structures or
2630 unions containing such types must be 16-byte-aligned; other
2631 arguments are 4-byte-aligned. */
2634 i386_16_byte_align_p (struct type *type)
2636 type = check_typedef (type);
2637 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
2638 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
2639 && TYPE_LENGTH (type) == 16)
2641 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2642 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
2643 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2644 || TYPE_CODE (type) == TYPE_CODE_UNION)
2647 for (i = 0; i < TYPE_NFIELDS (type); i++)
2649 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
2656 /* Implementation for set_gdbarch_push_dummy_code. */
2659 i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
2660 struct value **args, int nargs, struct type *value_type,
2661 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
2662 struct regcache *regcache)
2664 /* Use 0xcc breakpoint - 1 byte. */
2668 /* Keep the stack aligned. */
2673 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2674 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2675 struct value **args, CORE_ADDR sp,
2676 function_call_return_method return_method,
2677 CORE_ADDR struct_addr)
2679 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2685 /* BND registers can be in arbitrary values at the moment of the
2686 inferior call. This can cause boundary violations that are not
2687 due to a real bug or even desired by the user. The best to be done
2688 is set the BND registers to allow access to the whole memory, INIT
2689 state, before pushing the inferior call. */
2690 i387_reset_bnd_regs (gdbarch, regcache);
2692 /* Determine the total space required for arguments and struct
2693 return address in a first pass (allowing for 16-byte-aligned
2694 arguments), then push arguments in a second pass. */
2696 for (write_pass = 0; write_pass < 2; write_pass++)
2698 int args_space_used = 0;
2700 if (return_method == return_method_struct)
2704 /* Push value address. */
2705 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2706 write_memory (sp, buf, 4);
2707 args_space_used += 4;
2713 for (i = 0; i < nargs; i++)
2715 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2719 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2720 args_space_used = align_up (args_space_used, 16);
2722 write_memory (sp + args_space_used,
2723 value_contents_all (args[i]), len);
2724 /* The System V ABI says that:
2726 "An argument's size is increased, if necessary, to make it a
2727 multiple of [32-bit] words. This may require tail padding,
2728 depending on the size of the argument."
2730 This makes sure the stack stays word-aligned. */
2731 args_space_used += align_up (len, 4);
2735 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2736 args_space = align_up (args_space, 16);
2737 args_space += align_up (len, 4);
2745 /* The original System V ABI only requires word alignment,
2746 but modern incarnations need 16-byte alignment in order
2747 to support SSE. Since wasting a few bytes here isn't
2748 harmful we unconditionally enforce 16-byte alignment. */
2753 /* Store return address. */
2755 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2756 write_memory (sp, buf, 4);
2758 /* Finally, update the stack pointer... */
2759 store_unsigned_integer (buf, 4, byte_order, sp);
2760 regcache->cooked_write (I386_ESP_REGNUM, buf);
2762 /* ...and fake a frame pointer. */
2763 regcache->cooked_write (I386_EBP_REGNUM, buf);
2765 /* MarkK wrote: This "+ 8" is all over the place:
2766 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2767 i386_dummy_id). It's there, since all frame unwinders for
2768 a given target have to agree (within a certain margin) on the
2769 definition of the stack address of a frame. Otherwise frame id
2770 comparison might not work correctly. Since DWARF2/GCC uses the
2771 stack address *before* the function call as a frame's CFA. On
2772 the i386, when %ebp is used as a frame pointer, the offset
2773 between the contents %ebp and the CFA as defined by GCC. */
2777 /* These registers are used for returning integers (and on some
2778 targets also for returning `struct' and `union' values when their
2779 size and alignment match an integer type). */
2780 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2781 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2783 /* Read, for architecture GDBARCH, a function return value of TYPE
2784 from REGCACHE, and copy that into VALBUF. */
2787 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2788 struct regcache *regcache, gdb_byte *valbuf)
2790 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2791 int len = TYPE_LENGTH (type);
2792 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2794 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2796 if (tdep->st0_regnum < 0)
2798 warning (_("Cannot find floating-point return value."));
2799 memset (valbuf, 0, len);
2803 /* Floating-point return values can be found in %st(0). Convert
2804 its contents to the desired type. This is probably not
2805 exactly how it would happen on the target itself, but it is
2806 the best we can do. */
2807 regcache->raw_read (I386_ST0_REGNUM, buf);
2808 target_float_convert (buf, i387_ext_type (gdbarch), valbuf, type);
2812 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2813 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2815 if (len <= low_size)
2817 regcache->raw_read (LOW_RETURN_REGNUM, buf);
2818 memcpy (valbuf, buf, len);
2820 else if (len <= (low_size + high_size))
2822 regcache->raw_read (LOW_RETURN_REGNUM, buf);
2823 memcpy (valbuf, buf, low_size);
2824 regcache->raw_read (HIGH_RETURN_REGNUM, buf);
2825 memcpy (valbuf + low_size, buf, len - low_size);
2828 internal_error (__FILE__, __LINE__,
2829 _("Cannot extract return value of %d bytes long."),
2834 /* Write, for architecture GDBARCH, a function return value of TYPE
2835 from VALBUF into REGCACHE. */
2838 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2839 struct regcache *regcache, const gdb_byte *valbuf)
2841 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2842 int len = TYPE_LENGTH (type);
2844 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2847 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2849 if (tdep->st0_regnum < 0)
2851 warning (_("Cannot set floating-point return value."));
2855 /* Returning floating-point values is a bit tricky. Apart from
2856 storing the return value in %st(0), we have to simulate the
2857 state of the FPU at function return point. */
2859 /* Convert the value found in VALBUF to the extended
2860 floating-point format used by the FPU. This is probably
2861 not exactly how it would happen on the target itself, but
2862 it is the best we can do. */
2863 target_float_convert (valbuf, type, buf, i387_ext_type (gdbarch));
2864 regcache->raw_write (I386_ST0_REGNUM, buf);
2866 /* Set the top of the floating-point register stack to 7. The
2867 actual value doesn't really matter, but 7 is what a normal
2868 function return would end up with if the program started out
2869 with a freshly initialized FPU. */
2870 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2872 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2874 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2875 the floating-point register stack to 7, the appropriate value
2876 for the tag word is 0x3fff. */
2877 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2881 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2882 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2884 if (len <= low_size)
2885 regcache->raw_write_part (LOW_RETURN_REGNUM, 0, len, valbuf);
2886 else if (len <= (low_size + high_size))
2888 regcache->raw_write (LOW_RETURN_REGNUM, valbuf);
2889 regcache->raw_write_part (HIGH_RETURN_REGNUM, 0, len - low_size,
2893 internal_error (__FILE__, __LINE__,
2894 _("Cannot store return value of %d bytes long."), len);
2899 /* This is the variable that is set with "set struct-convention", and
2900 its legitimate values. */
2901 static const char default_struct_convention[] = "default";
2902 static const char pcc_struct_convention[] = "pcc";
2903 static const char reg_struct_convention[] = "reg";
2904 static const char *const valid_conventions[] =
2906 default_struct_convention,
2907 pcc_struct_convention,
2908 reg_struct_convention,
2911 static const char *struct_convention = default_struct_convention;
2913 /* Return non-zero if TYPE, which is assumed to be a structure,
2914 a union type, or an array type, should be returned in registers
2915 for architecture GDBARCH. */
2918 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2920 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2921 enum type_code code = TYPE_CODE (type);
2922 int len = TYPE_LENGTH (type);
2924 gdb_assert (code == TYPE_CODE_STRUCT
2925 || code == TYPE_CODE_UNION
2926 || code == TYPE_CODE_ARRAY);
2928 if (struct_convention == pcc_struct_convention
2929 || (struct_convention == default_struct_convention
2930 && tdep->struct_return == pcc_struct_return))
2933 /* Structures consisting of a single `float', `double' or 'long
2934 double' member are returned in %st(0). */
2935 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2937 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2938 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2939 return (len == 4 || len == 8 || len == 12);
2942 return (len == 1 || len == 2 || len == 4 || len == 8);
2945 /* Determine, for architecture GDBARCH, how a return value of TYPE
2946 should be returned. If it is supposed to be returned in registers,
2947 and READBUF is non-zero, read the appropriate value from REGCACHE,
2948 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2949 from WRITEBUF into REGCACHE. */
2951 static enum return_value_convention
2952 i386_return_value (struct gdbarch *gdbarch, struct value *function,
2953 struct type *type, struct regcache *regcache,
2954 gdb_byte *readbuf, const gdb_byte *writebuf)
2956 enum type_code code = TYPE_CODE (type);
2958 if (((code == TYPE_CODE_STRUCT
2959 || code == TYPE_CODE_UNION
2960 || code == TYPE_CODE_ARRAY)
2961 && !i386_reg_struct_return_p (gdbarch, type))
2962 /* Complex double and long double uses the struct return covention. */
2963 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16)
2964 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24)
2965 /* 128-bit decimal float uses the struct return convention. */
2966 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2968 /* The System V ABI says that:
2970 "A function that returns a structure or union also sets %eax
2971 to the value of the original address of the caller's area
2972 before it returns. Thus when the caller receives control
2973 again, the address of the returned object resides in register
2974 %eax and can be used to access the object."
2976 So the ABI guarantees that we can always find the return
2977 value just after the function has returned. */
2979 /* Note that the ABI doesn't mention functions returning arrays,
2980 which is something possible in certain languages such as Ada.
2981 In this case, the value is returned as if it was wrapped in
2982 a record, so the convention applied to records also applies
2989 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2990 read_memory (addr, readbuf, TYPE_LENGTH (type));
2993 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2996 /* This special case is for structures consisting of a single
2997 `float', `double' or 'long double' member. These structures are
2998 returned in %st(0). For these structures, we call ourselves
2999 recursively, changing TYPE into the type of the first member of
3000 the structure. Since that should work for all structures that
3001 have only one member, we don't bother to check the member's type
3003 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
3005 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
3006 return i386_return_value (gdbarch, function, type, regcache,
3011 i386_extract_return_value (gdbarch, type, regcache, readbuf);
3013 i386_store_return_value (gdbarch, type, regcache, writebuf);
3015 return RETURN_VALUE_REGISTER_CONVENTION;
3020 i387_ext_type (struct gdbarch *gdbarch)
3022 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3024 if (!tdep->i387_ext_type)
3026 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
3027 gdb_assert (tdep->i387_ext_type != NULL);
3030 return tdep->i387_ext_type;
3033 /* Construct type for pseudo BND registers. We can't use
3034 tdesc_find_type since a complement of one value has to be used
3035 to describe the upper bound. */
3037 static struct type *
3038 i386_bnd_type (struct gdbarch *gdbarch)
3040 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3043 if (!tdep->i386_bnd_type)
3046 const struct builtin_type *bt = builtin_type (gdbarch);
3048 /* The type we're building is described bellow: */
3053 void *ubound; /* One complement of raw ubound field. */
3057 t = arch_composite_type (gdbarch,
3058 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT);
3060 append_composite_type_field (t, "lbound", bt->builtin_data_ptr);
3061 append_composite_type_field (t, "ubound", bt->builtin_data_ptr);
3063 TYPE_NAME (t) = "builtin_type_bound128";
3064 tdep->i386_bnd_type = t;
3067 return tdep->i386_bnd_type;
3070 /* Construct vector type for pseudo ZMM registers. We can't use
3071 tdesc_find_type since ZMM isn't described in target description. */
3073 static struct type *
3074 i386_zmm_type (struct gdbarch *gdbarch)
3076 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3078 if (!tdep->i386_zmm_type)
3080 const struct builtin_type *bt = builtin_type (gdbarch);
3082 /* The type we're building is this: */
3084 union __gdb_builtin_type_vec512i
3086 int128_t uint128[4];
3087 int64_t v4_int64[8];
3088 int32_t v8_int32[16];
3089 int16_t v16_int16[32];
3090 int8_t v32_int8[64];
3091 double v4_double[8];
3098 t = arch_composite_type (gdbarch,
3099 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION);
3100 append_composite_type_field (t, "v16_float",
3101 init_vector_type (bt->builtin_float, 16));
3102 append_composite_type_field (t, "v8_double",
3103 init_vector_type (bt->builtin_double, 8));
3104 append_composite_type_field (t, "v64_int8",
3105 init_vector_type (bt->builtin_int8, 64));
3106 append_composite_type_field (t, "v32_int16",
3107 init_vector_type (bt->builtin_int16, 32));
3108 append_composite_type_field (t, "v16_int32",
3109 init_vector_type (bt->builtin_int32, 16));
3110 append_composite_type_field (t, "v8_int64",
3111 init_vector_type (bt->builtin_int64, 8));
3112 append_composite_type_field (t, "v4_int128",
3113 init_vector_type (bt->builtin_int128, 4));
3115 TYPE_VECTOR (t) = 1;
3116 TYPE_NAME (t) = "builtin_type_vec512i";
3117 tdep->i386_zmm_type = t;
3120 return tdep->i386_zmm_type;
3123 /* Construct vector type for pseudo YMM registers. We can't use
3124 tdesc_find_type since YMM isn't described in target description. */
3126 static struct type *
3127 i386_ymm_type (struct gdbarch *gdbarch)
3129 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3131 if (!tdep->i386_ymm_type)
3133 const struct builtin_type *bt = builtin_type (gdbarch);
3135 /* The type we're building is this: */
3137 union __gdb_builtin_type_vec256i
3139 int128_t uint128[2];
3140 int64_t v2_int64[4];
3141 int32_t v4_int32[8];
3142 int16_t v8_int16[16];
3143 int8_t v16_int8[32];
3144 double v2_double[4];
3151 t = arch_composite_type (gdbarch,
3152 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
3153 append_composite_type_field (t, "v8_float",
3154 init_vector_type (bt->builtin_float, 8));
3155 append_composite_type_field (t, "v4_double",
3156 init_vector_type (bt->builtin_double, 4));
3157 append_composite_type_field (t, "v32_int8",
3158 init_vector_type (bt->builtin_int8, 32));
3159 append_composite_type_field (t, "v16_int16",
3160 init_vector_type (bt->builtin_int16, 16));
3161 append_composite_type_field (t, "v8_int32",
3162 init_vector_type (bt->builtin_int32, 8));
3163 append_composite_type_field (t, "v4_int64",
3164 init_vector_type (bt->builtin_int64, 4));
3165 append_composite_type_field (t, "v2_int128",
3166 init_vector_type (bt->builtin_int128, 2));
3168 TYPE_VECTOR (t) = 1;
3169 TYPE_NAME (t) = "builtin_type_vec256i";
3170 tdep->i386_ymm_type = t;
3173 return tdep->i386_ymm_type;
3176 /* Construct vector type for MMX registers. */
3177 static struct type *
3178 i386_mmx_type (struct gdbarch *gdbarch)
3180 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3182 if (!tdep->i386_mmx_type)
3184 const struct builtin_type *bt = builtin_type (gdbarch);
3186 /* The type we're building is this: */
3188 union __gdb_builtin_type_vec64i
3191 int32_t v2_int32[2];
3192 int16_t v4_int16[4];
3199 t = arch_composite_type (gdbarch,
3200 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
3202 append_composite_type_field (t, "uint64", bt->builtin_int64);
3203 append_composite_type_field (t, "v2_int32",
3204 init_vector_type (bt->builtin_int32, 2));
3205 append_composite_type_field (t, "v4_int16",
3206 init_vector_type (bt->builtin_int16, 4));
3207 append_composite_type_field (t, "v8_int8",
3208 init_vector_type (bt->builtin_int8, 8));
3210 TYPE_VECTOR (t) = 1;
3211 TYPE_NAME (t) = "builtin_type_vec64i";
3212 tdep->i386_mmx_type = t;
3215 return tdep->i386_mmx_type;
3218 /* Return the GDB type object for the "standard" data type of data in
3222 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3224 if (i386_bnd_regnum_p (gdbarch, regnum))
3225 return i386_bnd_type (gdbarch);
3226 if (i386_mmx_regnum_p (gdbarch, regnum))
3227 return i386_mmx_type (gdbarch);
3228 else if (i386_ymm_regnum_p (gdbarch, regnum))
3229 return i386_ymm_type (gdbarch);
3230 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3231 return i386_ymm_type (gdbarch);
3232 else if (i386_zmm_regnum_p (gdbarch, regnum))
3233 return i386_zmm_type (gdbarch);
3236 const struct builtin_type *bt = builtin_type (gdbarch);
3237 if (i386_byte_regnum_p (gdbarch, regnum))
3238 return bt->builtin_int8;
3239 else if (i386_word_regnum_p (gdbarch, regnum))
3240 return bt->builtin_int16;
3241 else if (i386_dword_regnum_p (gdbarch, regnum))
3242 return bt->builtin_int32;
3243 else if (i386_k_regnum_p (gdbarch, regnum))
3244 return bt->builtin_int64;
3247 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3250 /* Map a cooked register onto a raw register or memory. For the i386,
3251 the MMX registers need to be mapped onto floating point registers. */
3254 i386_mmx_regnum_to_fp_regnum (readable_regcache *regcache, int regnum)
3256 struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ());
3261 mmxreg = regnum - tdep->mm0_regnum;
3262 regcache->raw_read (I387_FSTAT_REGNUM (tdep), &fstat);
3263 tos = (fstat >> 11) & 0x7;
3264 fpreg = (mmxreg + tos) % 8;
3266 return (I387_ST0_REGNUM (tdep) + fpreg);
3269 /* A helper function for us by i386_pseudo_register_read_value and
3270 amd64_pseudo_register_read_value. It does all the work but reads
3271 the data into an already-allocated value. */
3274 i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
3275 readable_regcache *regcache,
3277 struct value *result_value)
3279 gdb_byte raw_buf[I386_MAX_REGISTER_SIZE];
3280 enum register_status status;
3281 gdb_byte *buf = value_contents_raw (result_value);
3283 if (i386_mmx_regnum_p (gdbarch, regnum))
3285 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3287 /* Extract (always little endian). */
3288 status = regcache->raw_read (fpnum, raw_buf);
3289 if (status != REG_VALID)
3290 mark_value_bytes_unavailable (result_value, 0,
3291 TYPE_LENGTH (value_type (result_value)));
3293 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
3297 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3298 if (i386_bnd_regnum_p (gdbarch, regnum))
3300 regnum -= tdep->bnd0_regnum;
3302 /* Extract (always little endian). Read lower 128bits. */
3303 status = regcache->raw_read (I387_BND0R_REGNUM (tdep) + regnum,
3305 if (status != REG_VALID)
3306 mark_value_bytes_unavailable (result_value, 0, 16);
3309 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3310 LONGEST upper, lower;
3311 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3313 lower = extract_unsigned_integer (raw_buf, 8, byte_order);
3314 upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order);
3317 memcpy (buf, &lower, size);
3318 memcpy (buf + size, &upper, size);
3321 else if (i386_k_regnum_p (gdbarch, regnum))
3323 regnum -= tdep->k0_regnum;
3325 /* Extract (always little endian). */
3326 status = regcache->raw_read (tdep->k0_regnum + regnum, raw_buf);
3327 if (status != REG_VALID)
3328 mark_value_bytes_unavailable (result_value, 0, 8);
3330 memcpy (buf, raw_buf, 8);
3332 else if (i386_zmm_regnum_p (gdbarch, regnum))
3334 regnum -= tdep->zmm0_regnum;
3336 if (regnum < num_lower_zmm_regs)
3338 /* Extract (always little endian). Read lower 128bits. */
3339 status = regcache->raw_read (I387_XMM0_REGNUM (tdep) + regnum,
3341 if (status != REG_VALID)
3342 mark_value_bytes_unavailable (result_value, 0, 16);
3344 memcpy (buf, raw_buf, 16);
3346 /* Extract (always little endian). Read upper 128bits. */
3347 status = regcache->raw_read (tdep->ymm0h_regnum + regnum,
3349 if (status != REG_VALID)
3350 mark_value_bytes_unavailable (result_value, 16, 16);
3352 memcpy (buf + 16, raw_buf, 16);
3356 /* Extract (always little endian). Read lower 128bits. */
3357 status = regcache->raw_read (I387_XMM16_REGNUM (tdep) + regnum
3358 - num_lower_zmm_regs,
3360 if (status != REG_VALID)
3361 mark_value_bytes_unavailable (result_value, 0, 16);
3363 memcpy (buf, raw_buf, 16);
3365 /* Extract (always little endian). Read upper 128bits. */
3366 status = regcache->raw_read (I387_YMM16H_REGNUM (tdep) + regnum
3367 - num_lower_zmm_regs,
3369 if (status != REG_VALID)
3370 mark_value_bytes_unavailable (result_value, 16, 16);
3372 memcpy (buf + 16, raw_buf, 16);
3375 /* Read upper 256bits. */
3376 status = regcache->raw_read (tdep->zmm0h_regnum + regnum,
3378 if (status != REG_VALID)
3379 mark_value_bytes_unavailable (result_value, 32, 32);
3381 memcpy (buf + 32, raw_buf, 32);
3383 else if (i386_ymm_regnum_p (gdbarch, regnum))
3385 regnum -= tdep->ymm0_regnum;
3387 /* Extract (always little endian). Read lower 128bits. */
3388 status = regcache->raw_read (I387_XMM0_REGNUM (tdep) + regnum,
3390 if (status != REG_VALID)
3391 mark_value_bytes_unavailable (result_value, 0, 16);
3393 memcpy (buf, raw_buf, 16);
3394 /* Read upper 128bits. */
3395 status = regcache->raw_read (tdep->ymm0h_regnum + regnum,
3397 if (status != REG_VALID)
3398 mark_value_bytes_unavailable (result_value, 16, 32);
3400 memcpy (buf + 16, raw_buf, 16);
3402 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3404 regnum -= tdep->ymm16_regnum;
3405 /* Extract (always little endian). Read lower 128bits. */
3406 status = regcache->raw_read (I387_XMM16_REGNUM (tdep) + regnum,
3408 if (status != REG_VALID)
3409 mark_value_bytes_unavailable (result_value, 0, 16);
3411 memcpy (buf, raw_buf, 16);
3412 /* Read upper 128bits. */
3413 status = regcache->raw_read (tdep->ymm16h_regnum + regnum,
3415 if (status != REG_VALID)
3416 mark_value_bytes_unavailable (result_value, 16, 16);
3418 memcpy (buf + 16, raw_buf, 16);
3420 else if (i386_word_regnum_p (gdbarch, regnum))
3422 int gpnum = regnum - tdep->ax_regnum;
3424 /* Extract (always little endian). */
3425 status = regcache->raw_read (gpnum, raw_buf);
3426 if (status != REG_VALID)
3427 mark_value_bytes_unavailable (result_value, 0,
3428 TYPE_LENGTH (value_type (result_value)));
3430 memcpy (buf, raw_buf, 2);
3432 else if (i386_byte_regnum_p (gdbarch, regnum))
3434 int gpnum = regnum - tdep->al_regnum;
3436 /* Extract (always little endian). We read both lower and
3438 status = regcache->raw_read (gpnum % 4, raw_buf);
3439 if (status != REG_VALID)
3440 mark_value_bytes_unavailable (result_value, 0,
3441 TYPE_LENGTH (value_type (result_value)));
3442 else if (gpnum >= 4)
3443 memcpy (buf, raw_buf + 1, 1);
3445 memcpy (buf, raw_buf, 1);
3448 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3452 static struct value *
3453 i386_pseudo_register_read_value (struct gdbarch *gdbarch,
3454 readable_regcache *regcache,
3457 struct value *result;
3459 result = allocate_value (register_type (gdbarch, regnum));
3460 VALUE_LVAL (result) = lval_register;
3461 VALUE_REGNUM (result) = regnum;
3463 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result);
3469 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3470 int regnum, const gdb_byte *buf)
3472 gdb_byte raw_buf[I386_MAX_REGISTER_SIZE];
3474 if (i386_mmx_regnum_p (gdbarch, regnum))
3476 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3479 regcache->raw_read (fpnum, raw_buf);
3480 /* ... Modify ... (always little endian). */
3481 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
3483 regcache->raw_write (fpnum, raw_buf);
3487 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3489 if (i386_bnd_regnum_p (gdbarch, regnum))
3491 ULONGEST upper, lower;
3492 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3493 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3495 /* New values from input value. */
3496 regnum -= tdep->bnd0_regnum;
3497 lower = extract_unsigned_integer (buf, size, byte_order);
3498 upper = extract_unsigned_integer (buf + size, size, byte_order);
3500 /* Fetching register buffer. */
3501 regcache->raw_read (I387_BND0R_REGNUM (tdep) + regnum,
3506 /* Set register bits. */
3507 memcpy (raw_buf, &lower, 8);
3508 memcpy (raw_buf + 8, &upper, 8);
3510 regcache->raw_write (I387_BND0R_REGNUM (tdep) + regnum, raw_buf);
3512 else if (i386_k_regnum_p (gdbarch, regnum))
3514 regnum -= tdep->k0_regnum;
3516 regcache->raw_write (tdep->k0_regnum + regnum, buf);
3518 else if (i386_zmm_regnum_p (gdbarch, regnum))
3520 regnum -= tdep->zmm0_regnum;
3522 if (regnum < num_lower_zmm_regs)
3524 /* Write lower 128bits. */
3525 regcache->raw_write (I387_XMM0_REGNUM (tdep) + regnum, buf);
3526 /* Write upper 128bits. */
3527 regcache->raw_write (I387_YMM0_REGNUM (tdep) + regnum, buf + 16);
3531 /* Write lower 128bits. */
3532 regcache->raw_write (I387_XMM16_REGNUM (tdep) + regnum
3533 - num_lower_zmm_regs, buf);
3534 /* Write upper 128bits. */
3535 regcache->raw_write (I387_YMM16H_REGNUM (tdep) + regnum
3536 - num_lower_zmm_regs, buf + 16);
3538 /* Write upper 256bits. */
3539 regcache->raw_write (tdep->zmm0h_regnum + regnum, buf + 32);
3541 else if (i386_ymm_regnum_p (gdbarch, regnum))
3543 regnum -= tdep->ymm0_regnum;
3545 /* ... Write lower 128bits. */
3546 regcache->raw_write (I387_XMM0_REGNUM (tdep) + regnum, buf);
3547 /* ... Write upper 128bits. */
3548 regcache->raw_write (tdep->ymm0h_regnum + regnum, buf + 16);
3550 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3552 regnum -= tdep->ymm16_regnum;
3554 /* ... Write lower 128bits. */
3555 regcache->raw_write (I387_XMM16_REGNUM (tdep) + regnum, buf);
3556 /* ... Write upper 128bits. */
3557 regcache->raw_write (tdep->ymm16h_regnum + regnum, buf + 16);
3559 else if (i386_word_regnum_p (gdbarch, regnum))
3561 int gpnum = regnum - tdep->ax_regnum;
3564 regcache->raw_read (gpnum, raw_buf);
3565 /* ... Modify ... (always little endian). */
3566 memcpy (raw_buf, buf, 2);
3568 regcache->raw_write (gpnum, raw_buf);
3570 else if (i386_byte_regnum_p (gdbarch, regnum))
3572 int gpnum = regnum - tdep->al_regnum;
3574 /* Read ... We read both lower and upper registers. */
3575 regcache->raw_read (gpnum % 4, raw_buf);
3576 /* ... Modify ... (always little endian). */
3578 memcpy (raw_buf + 1, buf, 1);
3580 memcpy (raw_buf, buf, 1);
3582 regcache->raw_write (gpnum % 4, raw_buf);
3585 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3589 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
3592 i386_ax_pseudo_register_collect (struct gdbarch *gdbarch,
3593 struct agent_expr *ax, int regnum)
3595 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3597 if (i386_mmx_regnum_p (gdbarch, regnum))
3599 /* MMX to FPU register mapping depends on current TOS. Let's just
3600 not care and collect everything... */
3603 ax_reg_mask (ax, I387_FSTAT_REGNUM (tdep));
3604 for (i = 0; i < 8; i++)
3605 ax_reg_mask (ax, I387_ST0_REGNUM (tdep) + i);
3608 else if (i386_bnd_regnum_p (gdbarch, regnum))
3610 regnum -= tdep->bnd0_regnum;
3611 ax_reg_mask (ax, I387_BND0R_REGNUM (tdep) + regnum);
3614 else if (i386_k_regnum_p (gdbarch, regnum))
3616 regnum -= tdep->k0_regnum;
3617 ax_reg_mask (ax, tdep->k0_regnum + regnum);
3620 else if (i386_zmm_regnum_p (gdbarch, regnum))
3622 regnum -= tdep->zmm0_regnum;
3623 if (regnum < num_lower_zmm_regs)
3625 ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum);
3626 ax_reg_mask (ax, tdep->ymm0h_regnum + regnum);
3630 ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum
3631 - num_lower_zmm_regs);
3632 ax_reg_mask (ax, I387_YMM16H_REGNUM (tdep) + regnum
3633 - num_lower_zmm_regs);
3635 ax_reg_mask (ax, tdep->zmm0h_regnum + regnum);
3638 else if (i386_ymm_regnum_p (gdbarch, regnum))
3640 regnum -= tdep->ymm0_regnum;
3641 ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum);
3642 ax_reg_mask (ax, tdep->ymm0h_regnum + regnum);
3645 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3647 regnum -= tdep->ymm16_regnum;
3648 ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum);
3649 ax_reg_mask (ax, tdep->ymm16h_regnum + regnum);
3652 else if (i386_word_regnum_p (gdbarch, regnum))
3654 int gpnum = regnum - tdep->ax_regnum;
3656 ax_reg_mask (ax, gpnum);
3659 else if (i386_byte_regnum_p (gdbarch, regnum))
3661 int gpnum = regnum - tdep->al_regnum;
3663 ax_reg_mask (ax, gpnum % 4);
3667 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3672 /* Return the register number of the register allocated by GCC after
3673 REGNUM, or -1 if there is no such register. */
3676 i386_next_regnum (int regnum)
3678 /* GCC allocates the registers in the order:
3680 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3682 Since storing a variable in %esp doesn't make any sense we return
3683 -1 for %ebp and for %esp itself. */
3684 static int next_regnum[] =
3686 I386_EDX_REGNUM, /* Slot for %eax. */
3687 I386_EBX_REGNUM, /* Slot for %ecx. */
3688 I386_ECX_REGNUM, /* Slot for %edx. */
3689 I386_ESI_REGNUM, /* Slot for %ebx. */
3690 -1, -1, /* Slots for %esp and %ebp. */
3691 I386_EDI_REGNUM, /* Slot for %esi. */
3692 I386_EBP_REGNUM /* Slot for %edi. */
3695 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
3696 return next_regnum[regnum];
3701 /* Return nonzero if a value of type TYPE stored in register REGNUM
3702 needs any special handling. */
3705 i386_convert_register_p (struct gdbarch *gdbarch,
3706 int regnum, struct type *type)
3708 int len = TYPE_LENGTH (type);
3710 /* Values may be spread across multiple registers. Most debugging
3711 formats aren't expressive enough to specify the locations, so
3712 some heuristics is involved. Right now we only handle types that
3713 have a length that is a multiple of the word size, since GCC
3714 doesn't seem to put any other types into registers. */
3715 if (len > 4 && len % 4 == 0)
3717 int last_regnum = regnum;
3721 last_regnum = i386_next_regnum (last_regnum);
3725 if (last_regnum != -1)
3729 return i387_convert_register_p (gdbarch, regnum, type);
3732 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3733 return its contents in TO. */
3736 i386_register_to_value (struct frame_info *frame, int regnum,
3737 struct type *type, gdb_byte *to,
3738 int *optimizedp, int *unavailablep)
3740 struct gdbarch *gdbarch = get_frame_arch (frame);
3741 int len = TYPE_LENGTH (type);
3743 if (i386_fp_regnum_p (gdbarch, regnum))
3744 return i387_register_to_value (frame, regnum, type, to,
3745 optimizedp, unavailablep);
3747 /* Read a value spread across multiple registers. */
3749 gdb_assert (len > 4 && len % 4 == 0);
3753 gdb_assert (regnum != -1);
3754 gdb_assert (register_size (gdbarch, regnum) == 4);
3756 if (!get_frame_register_bytes (frame, regnum, 0,
3757 register_size (gdbarch, regnum),
3758 to, optimizedp, unavailablep))
3761 regnum = i386_next_regnum (regnum);
3766 *optimizedp = *unavailablep = 0;
3770 /* Write the contents FROM of a value of type TYPE into register
3771 REGNUM in frame FRAME. */
3774 i386_value_to_register (struct frame_info *frame, int regnum,
3775 struct type *type, const gdb_byte *from)
3777 int len = TYPE_LENGTH (type);
3779 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
3781 i387_value_to_register (frame, regnum, type, from);
3785 /* Write a value spread across multiple registers. */
3787 gdb_assert (len > 4 && len % 4 == 0);
3791 gdb_assert (regnum != -1);
3792 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
3794 put_frame_register (frame, regnum, from);
3795 regnum = i386_next_regnum (regnum);
3801 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3802 in the general-purpose register set REGSET to register cache
3803 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3806 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
3807 int regnum, const void *gregs, size_t len)
3809 struct gdbarch *gdbarch = regcache->arch ();
3810 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3811 const gdb_byte *regs = (const gdb_byte *) gregs;
3814 gdb_assert (len >= tdep->sizeof_gregset);
3816 for (i = 0; i < tdep->gregset_num_regs; i++)
3818 if ((regnum == i || regnum == -1)
3819 && tdep->gregset_reg_offset[i] != -1)
3820 regcache->raw_supply (i, regs + tdep->gregset_reg_offset[i]);
3824 /* Collect register REGNUM from the register cache REGCACHE and store
3825 it in the buffer specified by GREGS and LEN as described by the
3826 general-purpose register set REGSET. If REGNUM is -1, do this for
3827 all registers in REGSET. */
3830 i386_collect_gregset (const struct regset *regset,
3831 const struct regcache *regcache,
3832 int regnum, void *gregs, size_t len)
3834 struct gdbarch *gdbarch = regcache->arch ();
3835 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3836 gdb_byte *regs = (gdb_byte *) gregs;
3839 gdb_assert (len >= tdep->sizeof_gregset);
3841 for (i = 0; i < tdep->gregset_num_regs; i++)
3843 if ((regnum == i || regnum == -1)
3844 && tdep->gregset_reg_offset[i] != -1)
3845 regcache->raw_collect (i, regs + tdep->gregset_reg_offset[i]);
3849 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3850 in the floating-point register set REGSET to register cache
3851 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3854 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
3855 int regnum, const void *fpregs, size_t len)
3857 struct gdbarch *gdbarch = regcache->arch ();
3858 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3860 if (len == I387_SIZEOF_FXSAVE)
3862 i387_supply_fxsave (regcache, regnum, fpregs);
3866 gdb_assert (len >= tdep->sizeof_fpregset);
3867 i387_supply_fsave (regcache, regnum, fpregs);
3870 /* Collect register REGNUM from the register cache REGCACHE and store
3871 it in the buffer specified by FPREGS and LEN as described by the
3872 floating-point register set REGSET. If REGNUM is -1, do this for
3873 all registers in REGSET. */
3876 i386_collect_fpregset (const struct regset *regset,
3877 const struct regcache *regcache,
3878 int regnum, void *fpregs, size_t len)
3880 struct gdbarch *gdbarch = regcache->arch ();
3881 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3883 if (len == I387_SIZEOF_FXSAVE)
3885 i387_collect_fxsave (regcache, regnum, fpregs);
3889 gdb_assert (len >= tdep->sizeof_fpregset);
3890 i387_collect_fsave (regcache, regnum, fpregs);
3893 /* Register set definitions. */
3895 const struct regset i386_gregset =
3897 NULL, i386_supply_gregset, i386_collect_gregset
3900 const struct regset i386_fpregset =
3902 NULL, i386_supply_fpregset, i386_collect_fpregset
3905 /* Default iterator over core file register note sections. */
3908 i386_iterate_over_regset_sections (struct gdbarch *gdbarch,
3909 iterate_over_regset_sections_cb *cb,
3911 const struct regcache *regcache)
3913 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3915 cb (".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, &i386_gregset, NULL,
3917 if (tdep->sizeof_fpregset)
3918 cb (".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset,
3923 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3926 i386_pe_skip_trampoline_code (struct frame_info *frame,
3927 CORE_ADDR pc, char *name)
3929 struct gdbarch *gdbarch = get_frame_arch (frame);
3930 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3933 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
3935 unsigned long indirect =
3936 read_memory_unsigned_integer (pc + 2, 4, byte_order);
3937 struct minimal_symbol *indsym =
3938 indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0;
3939 const char *symname = indsym ? MSYMBOL_LINKAGE_NAME (indsym) : 0;
3943 if (startswith (symname, "__imp_")
3944 || startswith (symname, "_imp_"))
3946 read_memory_unsigned_integer (indirect, 4, byte_order);
3949 return 0; /* Not a trampoline. */
3953 /* Return whether the THIS_FRAME corresponds to a sigtramp
3957 i386_sigtramp_p (struct frame_info *this_frame)
3959 CORE_ADDR pc = get_frame_pc (this_frame);
3962 find_pc_partial_function (pc, &name, NULL, NULL);
3963 return (name && strcmp ("_sigtramp", name) == 0);
3967 /* We have two flavours of disassembly. The machinery on this page
3968 deals with switching between those. */
3971 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
3973 gdb_assert (disassembly_flavor == att_flavor
3974 || disassembly_flavor == intel_flavor);
3976 info->disassembler_options = disassembly_flavor;
3978 return default_print_insn (pc, info);
3982 /* There are a few i386 architecture variants that differ only
3983 slightly from the generic i386 target. For now, we don't give them
3984 their own source file, but include them here. As a consequence,
3985 they'll always be included. */
3987 /* System V Release 4 (SVR4). */
3989 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3993 i386_svr4_sigtramp_p (struct frame_info *this_frame)
3995 CORE_ADDR pc = get_frame_pc (this_frame);
3998 /* The origin of these symbols is currently unknown. */
3999 find_pc_partial_function (pc, &name, NULL, NULL);
4000 return (name && (strcmp ("_sigreturn", name) == 0
4001 || strcmp ("sigvechandler", name) == 0));
4004 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
4005 address of the associated sigcontext (ucontext) structure. */
4008 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
4010 struct gdbarch *gdbarch = get_frame_arch (this_frame);
4011 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4015 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
4016 sp = extract_unsigned_integer (buf, 4, byte_order);
4018 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
4023 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
4027 i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s)
4029 return (*s == '$' /* Literal number. */
4030 || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */
4031 || (*s == '(' && s[1] == '%') /* Register indirection. */
4032 || (*s == '%' && isalpha (s[1]))); /* Register access. */
4035 /* Helper function for i386_stap_parse_special_token.
4037 This function parses operands of the form `-8+3+1(%rbp)', which
4038 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
4040 Return 1 if the operand was parsed successfully, zero
4044 i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch,
4045 struct stap_parse_info *p)
4047 const char *s = p->arg;
4049 if (isdigit (*s) || *s == '-' || *s == '+')
4053 long displacements[3];
4069 if (!isdigit ((unsigned char) *s))
4072 displacements[0] = strtol (s, &endp, 10);
4075 if (*s != '+' && *s != '-')
4077 /* We are not dealing with a triplet. */
4090 if (!isdigit ((unsigned char) *s))
4093 displacements[1] = strtol (s, &endp, 10);
4096 if (*s != '+' && *s != '-')
4098 /* We are not dealing with a triplet. */
4111 if (!isdigit ((unsigned char) *s))
4114 displacements[2] = strtol (s, &endp, 10);
4117 if (*s != '(' || s[1] != '%')
4123 while (isalnum (*s))
4129 len = s - start - 1;
4130 regname = (char *) alloca (len + 1);
4132 strncpy (regname, start, len);
4133 regname[len] = '\0';
4135 if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1)
4136 error (_("Invalid register name `%s' on expression `%s'."),
4137 regname, p->saved_arg);
4139 for (i = 0; i < 3; i++)
4141 write_exp_elt_opcode (&p->pstate, OP_LONG);
4143 (&p->pstate, builtin_type (gdbarch)->builtin_long);
4144 write_exp_elt_longcst (&p->pstate, displacements[i]);
4145 write_exp_elt_opcode (&p->pstate, OP_LONG);
4147 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4150 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4153 write_exp_string (&p->pstate, str);
4154 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4156 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4157 write_exp_elt_type (&p->pstate,
4158 builtin_type (gdbarch)->builtin_data_ptr);
4159 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4161 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4162 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4163 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4165 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4166 write_exp_elt_type (&p->pstate,
4167 lookup_pointer_type (p->arg_type));
4168 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4170 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4180 /* Helper function for i386_stap_parse_special_token.
4182 This function parses operands of the form `register base +
4183 (register index * size) + offset', as represented in
4184 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4186 Return 1 if the operand was parsed successfully, zero
4190 i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch,
4191 struct stap_parse_info *p)
4193 const char *s = p->arg;
4195 if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+')
4197 int offset_minus = 0;
4206 struct stoken base_token, index_token;
4216 if (offset_minus && !isdigit (*s))
4223 offset = strtol (s, &endp, 10);
4227 if (*s != '(' || s[1] != '%')
4233 while (isalnum (*s))
4236 if (*s != ',' || s[1] != '%')
4239 len_base = s - start;
4240 base = (char *) alloca (len_base + 1);
4241 strncpy (base, start, len_base);
4242 base[len_base] = '\0';
4244 if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1)
4245 error (_("Invalid register name `%s' on expression `%s'."),
4246 base, p->saved_arg);
4251 while (isalnum (*s))
4254 len_index = s - start;
4255 index = (char *) alloca (len_index + 1);
4256 strncpy (index, start, len_index);
4257 index[len_index] = '\0';
4259 if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1)
4260 error (_("Invalid register name `%s' on expression `%s'."),
4261 index, p->saved_arg);
4263 if (*s != ',' && *s != ')')
4279 size = strtol (s, &endp, 10);
4290 write_exp_elt_opcode (&p->pstate, OP_LONG);
4291 write_exp_elt_type (&p->pstate,
4292 builtin_type (gdbarch)->builtin_long);
4293 write_exp_elt_longcst (&p->pstate, offset);
4294 write_exp_elt_opcode (&p->pstate, OP_LONG);
4296 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4299 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4300 base_token.ptr = base;
4301 base_token.length = len_base;
4302 write_exp_string (&p->pstate, base_token);
4303 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4306 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4308 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4309 index_token.ptr = index;
4310 index_token.length = len_index;
4311 write_exp_string (&p->pstate, index_token);
4312 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4316 write_exp_elt_opcode (&p->pstate, OP_LONG);
4317 write_exp_elt_type (&p->pstate,
4318 builtin_type (gdbarch)->builtin_long);
4319 write_exp_elt_longcst (&p->pstate, size);
4320 write_exp_elt_opcode (&p->pstate, OP_LONG);
4322 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4323 write_exp_elt_opcode (&p->pstate, BINOP_MUL);
4326 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4328 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4329 write_exp_elt_type (&p->pstate,
4330 lookup_pointer_type (p->arg_type));
4331 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4333 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4343 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4347 i386_stap_parse_special_token (struct gdbarch *gdbarch,
4348 struct stap_parse_info *p)
4350 /* In order to parse special tokens, we use a state-machine that go
4351 through every known token and try to get a match. */
4355 THREE_ARG_DISPLACEMENT,
4360 current_state = TRIPLET;
4362 /* The special tokens to be parsed here are:
4364 - `register base + (register index * size) + offset', as represented
4365 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4367 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4368 `*(-8 + 3 - 1 + (void *) $eax)'. */
4370 while (current_state != DONE)
4372 switch (current_state)
4375 if (i386_stap_parse_special_token_triplet (gdbarch, p))
4379 case THREE_ARG_DISPLACEMENT:
4380 if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p))
4385 /* Advancing to the next state. */
4392 /* Implementation of 'gdbarch_stap_adjust_register', as defined in
4396 i386_stap_adjust_register (struct gdbarch *gdbarch, struct stap_parse_info *p,
4397 std::string ®name, int regnum)
4399 static const std::unordered_set<std::string> reg_assoc
4400 = { "ax", "bx", "cx", "dx",
4401 "si", "di", "bp", "sp" };
4403 if (register_size (gdbarch, regnum) >= TYPE_LENGTH (p->arg_type))
4405 /* If we're dealing with a register whose size is greater or
4406 equal than the size specified by the "[-]N@" prefix, then we
4407 don't need to do anything. */
4411 if (reg_assoc.find (regname) != reg_assoc.end ())
4413 /* Use the extended version of the register. */
4414 regname = "e" + regname;
4420 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always
4421 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */
4424 i386_gnu_triplet_regexp (struct gdbarch *gdbarch)
4426 return "(x86_64|i.86)";
4431 /* Implement the "in_indirect_branch_thunk" gdbarch function. */
4434 i386_in_indirect_branch_thunk (struct gdbarch *gdbarch, CORE_ADDR pc)
4436 return x86_in_indirect_branch_thunk (pc, i386_register_names,
4437 I386_EAX_REGNUM, I386_EIP_REGNUM);
4443 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4445 static const char *const stap_integer_prefixes[] = { "$", NULL };
4446 static const char *const stap_register_prefixes[] = { "%", NULL };
4447 static const char *const stap_register_indirection_prefixes[] = { "(",
4449 static const char *const stap_register_indirection_suffixes[] = { ")",
4452 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4453 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4455 /* Registering SystemTap handlers. */
4456 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
4457 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
4458 set_gdbarch_stap_register_indirection_prefixes (gdbarch,
4459 stap_register_indirection_prefixes);
4460 set_gdbarch_stap_register_indirection_suffixes (gdbarch,
4461 stap_register_indirection_suffixes);
4462 set_gdbarch_stap_is_single_operand (gdbarch,
4463 i386_stap_is_single_operand);
4464 set_gdbarch_stap_parse_special_token (gdbarch,
4465 i386_stap_parse_special_token);
4466 set_gdbarch_stap_adjust_register (gdbarch,
4467 i386_stap_adjust_register);
4469 set_gdbarch_in_indirect_branch_thunk (gdbarch,
4470 i386_in_indirect_branch_thunk);
4473 /* System V Release 4 (SVR4). */
4476 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4478 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4480 /* System V Release 4 uses ELF. */
4481 i386_elf_init_abi (info, gdbarch);
4483 /* System V Release 4 has shared libraries. */
4484 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
4486 tdep->sigtramp_p = i386_svr4_sigtramp_p;
4487 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
4488 tdep->sc_pc_offset = 36 + 14 * 4;
4489 tdep->sc_sp_offset = 36 + 17 * 4;
4491 tdep->jb_pc_offset = 20;
4496 /* i386 register groups. In addition to the normal groups, add "mmx"
4499 static struct reggroup *i386_sse_reggroup;
4500 static struct reggroup *i386_mmx_reggroup;
4503 i386_init_reggroups (void)
4505 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
4506 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
4510 i386_add_reggroups (struct gdbarch *gdbarch)
4512 reggroup_add (gdbarch, i386_sse_reggroup);
4513 reggroup_add (gdbarch, i386_mmx_reggroup);
4514 reggroup_add (gdbarch, general_reggroup);
4515 reggroup_add (gdbarch, float_reggroup);
4516 reggroup_add (gdbarch, all_reggroup);
4517 reggroup_add (gdbarch, save_reggroup);
4518 reggroup_add (gdbarch, restore_reggroup);
4519 reggroup_add (gdbarch, vector_reggroup);
4520 reggroup_add (gdbarch, system_reggroup);
4524 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
4525 struct reggroup *group)
4527 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4528 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
4529 ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p,
4530 bndr_regnum_p, bnd_regnum_p, zmm_regnum_p, zmmh_regnum_p,
4531 mpx_ctrl_regnum_p, xmm_avx512_regnum_p,
4532 avx512_p, avx_p, sse_p, pkru_regnum_p;
4534 /* Don't include pseudo registers, except for MMX, in any register
4536 if (i386_byte_regnum_p (gdbarch, regnum))
4539 if (i386_word_regnum_p (gdbarch, regnum))
4542 if (i386_dword_regnum_p (gdbarch, regnum))
4545 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
4546 if (group == i386_mmx_reggroup)
4547 return mmx_regnum_p;
4549 pkru_regnum_p = i386_pkru_regnum_p(gdbarch, regnum);
4550 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
4551 xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum);
4552 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
4553 if (group == i386_sse_reggroup)
4554 return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p;
4556 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
4557 ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum);
4558 zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum);
4560 avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK)
4561 == X86_XSTATE_AVX_AVX512_MASK);
4562 avx_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK)
4563 == X86_XSTATE_AVX_MASK) && !avx512_p;
4564 sse_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK)
4565 == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p;
4567 if (group == vector_reggroup)
4568 return (mmx_regnum_p
4569 || (zmm_regnum_p && avx512_p)
4570 || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p)
4571 || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p)
4574 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
4575 || i386_fpc_regnum_p (gdbarch, regnum));
4576 if (group == float_reggroup)
4579 /* For "info reg all", don't include upper YMM registers nor XMM
4580 registers when AVX is supported. */
4581 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
4582 ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum);
4583 zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum);
4584 if (group == all_reggroup
4585 && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p)
4586 || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p)
4588 || ymmh_avx512_regnum_p
4592 bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum);
4593 if (group == all_reggroup
4594 && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4595 return bnd_regnum_p;
4597 bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum);
4598 if (group == all_reggroup
4599 && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4602 mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum);
4603 if (group == all_reggroup
4604 && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4605 return mpx_ctrl_regnum_p;
4607 if (group == general_reggroup)
4608 return (!fp_regnum_p
4612 && !xmm_avx512_regnum_p
4615 && !ymm_avx512_regnum_p
4616 && !ymmh_avx512_regnum_p
4619 && !mpx_ctrl_regnum_p
4624 return default_register_reggroup_p (gdbarch, regnum, group);
4628 /* Get the ARGIth function argument for the current function. */
4631 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
4634 struct gdbarch *gdbarch = get_frame_arch (frame);
4635 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4636 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
4637 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
4640 #define PREFIX_REPZ 0x01
4641 #define PREFIX_REPNZ 0x02
4642 #define PREFIX_LOCK 0x04
4643 #define PREFIX_DATA 0x08
4644 #define PREFIX_ADDR 0x10
4656 /* i386 arith/logic operations */
4669 struct i386_record_s
4671 struct gdbarch *gdbarch;
4672 struct regcache *regcache;
4673 CORE_ADDR orig_addr;
4679 uint8_t mod, reg, rm;
4688 /* Parse the "modrm" part of the memory address irp->addr points at.
4689 Returns -1 if something goes wrong, 0 otherwise. */
4692 i386_record_modrm (struct i386_record_s *irp)
4694 struct gdbarch *gdbarch = irp->gdbarch;
4696 if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1))
4700 irp->mod = (irp->modrm >> 6) & 3;
4701 irp->reg = (irp->modrm >> 3) & 7;
4702 irp->rm = irp->modrm & 7;
4707 /* Extract the memory address that the current instruction writes to,
4708 and return it in *ADDR. Return -1 if something goes wrong. */
4711 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
4713 struct gdbarch *gdbarch = irp->gdbarch;
4714 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4719 if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM])
4726 uint8_t base = irp->rm;
4731 if (record_read_memory (gdbarch, irp->addr, &byte, 1))
4734 scale = (byte >> 6) & 3;
4735 index = ((byte >> 3) & 7) | irp->rex_x;
4743 if ((base & 7) == 5)
4746 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4749 *addr = extract_signed_integer (buf, 4, byte_order);
4750 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
4751 *addr += irp->addr + irp->rip_offset;
4755 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4758 *addr = (int8_t) buf[0];
4761 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4763 *addr = extract_signed_integer (buf, 4, byte_order);
4771 if (base == 4 && irp->popl_esp_hack)
4772 *addr += irp->popl_esp_hack;
4773 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
4776 if (irp->aflag == 2)
4781 *addr = (uint32_t) (offset64 + *addr);
4783 if (havesib && (index != 4 || scale != 0))
4785 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
4787 if (irp->aflag == 2)
4788 *addr += offset64 << scale;
4790 *addr = (uint32_t) (*addr + (offset64 << scale));
4795 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4796 address from 32-bit to 64-bit. */
4797 *addr = (uint32_t) *addr;
4808 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4811 *addr = extract_signed_integer (buf, 2, byte_order);
4817 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4820 *addr = (int8_t) buf[0];
4823 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4826 *addr = extract_signed_integer (buf, 2, byte_order);
4833 regcache_raw_read_unsigned (irp->regcache,
4834 irp->regmap[X86_RECORD_REBX_REGNUM],
4836 *addr = (uint32_t) (*addr + offset64);
4837 regcache_raw_read_unsigned (irp->regcache,
4838 irp->regmap[X86_RECORD_RESI_REGNUM],
4840 *addr = (uint32_t) (*addr + offset64);
4843 regcache_raw_read_unsigned (irp->regcache,
4844 irp->regmap[X86_RECORD_REBX_REGNUM],
4846 *addr = (uint32_t) (*addr + offset64);
4847 regcache_raw_read_unsigned (irp->regcache,
4848 irp->regmap[X86_RECORD_REDI_REGNUM],
4850 *addr = (uint32_t) (*addr + offset64);
4853 regcache_raw_read_unsigned (irp->regcache,
4854 irp->regmap[X86_RECORD_REBP_REGNUM],
4856 *addr = (uint32_t) (*addr + offset64);
4857 regcache_raw_read_unsigned (irp->regcache,
4858 irp->regmap[X86_RECORD_RESI_REGNUM],
4860 *addr = (uint32_t) (*addr + offset64);
4863 regcache_raw_read_unsigned (irp->regcache,
4864 irp->regmap[X86_RECORD_REBP_REGNUM],
4866 *addr = (uint32_t) (*addr + offset64);
4867 regcache_raw_read_unsigned (irp->regcache,
4868 irp->regmap[X86_RECORD_REDI_REGNUM],
4870 *addr = (uint32_t) (*addr + offset64);
4873 regcache_raw_read_unsigned (irp->regcache,
4874 irp->regmap[X86_RECORD_RESI_REGNUM],
4876 *addr = (uint32_t) (*addr + offset64);
4879 regcache_raw_read_unsigned (irp->regcache,
4880 irp->regmap[X86_RECORD_REDI_REGNUM],
4882 *addr = (uint32_t) (*addr + offset64);
4885 regcache_raw_read_unsigned (irp->regcache,
4886 irp->regmap[X86_RECORD_REBP_REGNUM],
4888 *addr = (uint32_t) (*addr + offset64);
4891 regcache_raw_read_unsigned (irp->regcache,
4892 irp->regmap[X86_RECORD_REBX_REGNUM],
4894 *addr = (uint32_t) (*addr + offset64);
4904 /* Record the address and contents of the memory that will be changed
4905 by the current instruction. Return -1 if something goes wrong, 0
4909 i386_record_lea_modrm (struct i386_record_s *irp)
4911 struct gdbarch *gdbarch = irp->gdbarch;
4914 if (irp->override >= 0)
4916 if (record_full_memory_query)
4919 Process record ignores the memory change of instruction at address %s\n\
4920 because it can't get the value of the segment register.\n\
4921 Do you want to stop the program?"),
4922 paddress (gdbarch, irp->orig_addr)))
4929 if (i386_record_lea_modrm_addr (irp, &addr))
4932 if (record_full_arch_list_add_mem (addr, 1 << irp->ot))
4938 /* Record the effects of a push operation. Return -1 if something
4939 goes wrong, 0 otherwise. */
4942 i386_record_push (struct i386_record_s *irp, int size)
4946 if (record_full_arch_list_add_reg (irp->regcache,
4947 irp->regmap[X86_RECORD_RESP_REGNUM]))
4949 regcache_raw_read_unsigned (irp->regcache,
4950 irp->regmap[X86_RECORD_RESP_REGNUM],
4952 if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size))
4959 /* Defines contents to record. */
4960 #define I386_SAVE_FPU_REGS 0xfffd
4961 #define I386_SAVE_FPU_ENV 0xfffe
4962 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4964 /* Record the values of the floating point registers which will be
4965 changed by the current instruction. Returns -1 if something is
4966 wrong, 0 otherwise. */
4968 static int i386_record_floats (struct gdbarch *gdbarch,
4969 struct i386_record_s *ir,
4972 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4975 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4976 happen. Currently we store st0-st7 registers, but we need not store all
4977 registers all the time, in future we use ftag register and record only
4978 those who are not marked as an empty. */
4980 if (I386_SAVE_FPU_REGS == iregnum)
4982 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
4984 if (record_full_arch_list_add_reg (ir->regcache, i))
4988 else if (I386_SAVE_FPU_ENV == iregnum)
4990 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4992 if (record_full_arch_list_add_reg (ir->regcache, i))
4996 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
4998 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
5000 if (record_full_arch_list_add_reg (ir->regcache, i))
5004 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
5005 (iregnum <= I387_FOP_REGNUM (tdep)))
5007 if (record_full_arch_list_add_reg (ir->regcache,iregnum))
5012 /* Parameter error. */
5015 if(I386_SAVE_FPU_ENV != iregnum)
5017 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
5019 if (record_full_arch_list_add_reg (ir->regcache, i))
5026 /* Parse the current instruction, and record the values of the
5027 registers and memory that will be changed by the current
5028 instruction. Returns -1 if something goes wrong, 0 otherwise. */
5030 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
5031 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
5034 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
5035 CORE_ADDR input_addr)
5037 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5043 gdb_byte buf[I386_MAX_REGISTER_SIZE];
5044 struct i386_record_s ir;
5045 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5049 memset (&ir, 0, sizeof (struct i386_record_s));
5050 ir.regcache = regcache;
5051 ir.addr = input_addr;
5052 ir.orig_addr = input_addr;
5056 ir.popl_esp_hack = 0;
5057 ir.regmap = tdep->record_regmap;
5058 ir.gdbarch = gdbarch;
5060 if (record_debug > 1)
5061 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
5063 paddress (gdbarch, ir.addr));
5068 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5071 switch (opcode8) /* Instruction prefixes */
5073 case REPE_PREFIX_OPCODE:
5074 prefixes |= PREFIX_REPZ;
5076 case REPNE_PREFIX_OPCODE:
5077 prefixes |= PREFIX_REPNZ;
5079 case LOCK_PREFIX_OPCODE:
5080 prefixes |= PREFIX_LOCK;
5082 case CS_PREFIX_OPCODE:
5083 ir.override = X86_RECORD_CS_REGNUM;
5085 case SS_PREFIX_OPCODE:
5086 ir.override = X86_RECORD_SS_REGNUM;
5088 case DS_PREFIX_OPCODE:
5089 ir.override = X86_RECORD_DS_REGNUM;
5091 case ES_PREFIX_OPCODE:
5092 ir.override = X86_RECORD_ES_REGNUM;
5094 case FS_PREFIX_OPCODE:
5095 ir.override = X86_RECORD_FS_REGNUM;
5097 case GS_PREFIX_OPCODE:
5098 ir.override = X86_RECORD_GS_REGNUM;
5100 case DATA_PREFIX_OPCODE:
5101 prefixes |= PREFIX_DATA;
5103 case ADDR_PREFIX_OPCODE:
5104 prefixes |= PREFIX_ADDR;
5106 case 0x40: /* i386 inc %eax */
5107 case 0x41: /* i386 inc %ecx */
5108 case 0x42: /* i386 inc %edx */
5109 case 0x43: /* i386 inc %ebx */
5110 case 0x44: /* i386 inc %esp */
5111 case 0x45: /* i386 inc %ebp */
5112 case 0x46: /* i386 inc %esi */
5113 case 0x47: /* i386 inc %edi */
5114 case 0x48: /* i386 dec %eax */
5115 case 0x49: /* i386 dec %ecx */
5116 case 0x4a: /* i386 dec %edx */
5117 case 0x4b: /* i386 dec %ebx */
5118 case 0x4c: /* i386 dec %esp */
5119 case 0x4d: /* i386 dec %ebp */
5120 case 0x4e: /* i386 dec %esi */
5121 case 0x4f: /* i386 dec %edi */
5122 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
5125 rex_w = (opcode8 >> 3) & 1;
5126 rex_r = (opcode8 & 0x4) << 1;
5127 ir.rex_x = (opcode8 & 0x2) << 2;
5128 ir.rex_b = (opcode8 & 0x1) << 3;
5130 else /* 32 bit target */
5139 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
5145 if (prefixes & PREFIX_DATA)
5148 if (prefixes & PREFIX_ADDR)
5150 else if (ir.regmap[X86_RECORD_R8_REGNUM])
5153 /* Now check op code. */
5154 opcode = (uint32_t) opcode8;
5159 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5162 opcode = (uint32_t) opcode8 | 0x0f00;
5166 case 0x00: /* arith & logic */
5214 if (((opcode >> 3) & 7) != OP_CMPL)
5216 if ((opcode & 1) == 0)
5219 ir.ot = ir.dflag + OT_WORD;
5221 switch ((opcode >> 1) & 3)
5223 case 0: /* OP Ev, Gv */
5224 if (i386_record_modrm (&ir))
5228 if (i386_record_lea_modrm (&ir))
5234 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5236 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5239 case 1: /* OP Gv, Ev */
5240 if (i386_record_modrm (&ir))
5243 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5245 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5247 case 2: /* OP A, Iv */
5248 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5252 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5255 case 0x80: /* GRP1 */
5259 if (i386_record_modrm (&ir))
5262 if (ir.reg != OP_CMPL)
5264 if ((opcode & 1) == 0)
5267 ir.ot = ir.dflag + OT_WORD;
5274 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5275 if (i386_record_lea_modrm (&ir))
5279 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5281 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5284 case 0x40: /* inc */
5293 case 0x48: /* dec */
5302 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7);
5303 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5306 case 0xf6: /* GRP3 */
5308 if ((opcode & 1) == 0)
5311 ir.ot = ir.dflag + OT_WORD;
5312 if (i386_record_modrm (&ir))
5315 if (ir.mod != 3 && ir.reg == 0)
5316 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5321 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5327 if (i386_record_lea_modrm (&ir))
5333 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5335 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5337 if (ir.reg == 3) /* neg */
5338 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5344 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5345 if (ir.ot != OT_BYTE)
5346 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5347 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5351 opcode = opcode << 8 | ir.modrm;
5357 case 0xfe: /* GRP4 */
5358 case 0xff: /* GRP5 */
5359 if (i386_record_modrm (&ir))
5361 if (ir.reg >= 2 && opcode == 0xfe)
5364 opcode = opcode << 8 | ir.modrm;
5371 if ((opcode & 1) == 0)
5374 ir.ot = ir.dflag + OT_WORD;
5377 if (i386_record_lea_modrm (&ir))
5383 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5385 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5387 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5390 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5392 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5394 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5397 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5398 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5400 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5404 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5407 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5409 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5414 opcode = opcode << 8 | ir.modrm;
5420 case 0x84: /* test */
5424 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5427 case 0x98: /* CWDE/CBW */
5428 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5431 case 0x99: /* CDQ/CWD */
5432 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5433 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5436 case 0x0faf: /* imul */
5439 ir.ot = ir.dflag + OT_WORD;
5440 if (i386_record_modrm (&ir))
5443 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5444 else if (opcode == 0x6b)
5447 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5449 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5450 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5453 case 0x0fc0: /* xadd */
5455 if ((opcode & 1) == 0)
5458 ir.ot = ir.dflag + OT_WORD;
5459 if (i386_record_modrm (&ir))
5464 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5466 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5467 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5469 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5473 if (i386_record_lea_modrm (&ir))
5475 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5477 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5479 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5482 case 0x0fb0: /* cmpxchg */
5484 if ((opcode & 1) == 0)
5487 ir.ot = ir.dflag + OT_WORD;
5488 if (i386_record_modrm (&ir))
5493 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5494 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5496 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5500 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5501 if (i386_record_lea_modrm (&ir))
5504 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5507 case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */
5508 if (i386_record_modrm (&ir))
5512 /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as
5513 an extended opcode. rdrand has bits 110 (/6) and rdseed
5514 has bits 111 (/7). */
5515 if (ir.reg == 6 || ir.reg == 7)
5517 /* The storage register is described by the 3 R/M bits, but the
5518 REX.B prefix may be used to give access to registers
5519 R8~R15. In this case ir.rex_b + R/M will give us the register
5520 in the range R8~R15.
5522 REX.W may also be used to access 64-bit registers, but we
5523 already record entire registers and not just partial bits
5525 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b + ir.rm);
5526 /* These instructions also set conditional bits. */
5527 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5532 /* We don't handle this particular instruction yet. */
5534 opcode = opcode << 8 | ir.modrm;
5538 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5539 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5540 if (i386_record_lea_modrm (&ir))
5542 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5545 case 0x50: /* push */
5555 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5557 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5561 case 0x06: /* push es */
5562 case 0x0e: /* push cs */
5563 case 0x16: /* push ss */
5564 case 0x1e: /* push ds */
5565 if (ir.regmap[X86_RECORD_R8_REGNUM])
5570 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5574 case 0x0fa0: /* push fs */
5575 case 0x0fa8: /* push gs */
5576 if (ir.regmap[X86_RECORD_R8_REGNUM])
5581 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5585 case 0x60: /* pusha */
5586 if (ir.regmap[X86_RECORD_R8_REGNUM])
5591 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
5595 case 0x58: /* pop */
5603 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5604 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5607 case 0x61: /* popa */
5608 if (ir.regmap[X86_RECORD_R8_REGNUM])
5613 for (regnum = X86_RECORD_REAX_REGNUM;
5614 regnum <= X86_RECORD_REDI_REGNUM;
5616 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5619 case 0x8f: /* pop */
5620 if (ir.regmap[X86_RECORD_R8_REGNUM])
5621 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
5623 ir.ot = ir.dflag + OT_WORD;
5624 if (i386_record_modrm (&ir))
5627 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5630 ir.popl_esp_hack = 1 << ir.ot;
5631 if (i386_record_lea_modrm (&ir))
5634 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5637 case 0xc8: /* enter */
5638 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5639 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5641 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5645 case 0xc9: /* leave */
5646 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5647 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5650 case 0x07: /* pop es */
5651 if (ir.regmap[X86_RECORD_R8_REGNUM])
5656 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5657 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
5658 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5661 case 0x17: /* pop ss */
5662 if (ir.regmap[X86_RECORD_R8_REGNUM])
5667 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5668 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
5669 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5672 case 0x1f: /* pop ds */
5673 if (ir.regmap[X86_RECORD_R8_REGNUM])
5678 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5679 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
5680 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5683 case 0x0fa1: /* pop fs */
5684 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5685 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
5686 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5689 case 0x0fa9: /* pop gs */
5690 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5691 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
5692 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5695 case 0x88: /* mov */
5699 if ((opcode & 1) == 0)
5702 ir.ot = ir.dflag + OT_WORD;
5704 if (i386_record_modrm (&ir))
5709 if (opcode == 0xc6 || opcode == 0xc7)
5710 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5711 if (i386_record_lea_modrm (&ir))
5716 if (opcode == 0xc6 || opcode == 0xc7)
5718 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5720 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5724 case 0x8a: /* mov */
5726 if ((opcode & 1) == 0)
5729 ir.ot = ir.dflag + OT_WORD;
5730 if (i386_record_modrm (&ir))
5733 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5735 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5738 case 0x8c: /* mov seg */
5739 if (i386_record_modrm (&ir))
5744 opcode = opcode << 8 | ir.modrm;
5749 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5753 if (i386_record_lea_modrm (&ir))
5758 case 0x8e: /* mov seg */
5759 if (i386_record_modrm (&ir))
5764 regnum = X86_RECORD_ES_REGNUM;
5767 regnum = X86_RECORD_SS_REGNUM;
5770 regnum = X86_RECORD_DS_REGNUM;
5773 regnum = X86_RECORD_FS_REGNUM;
5776 regnum = X86_RECORD_GS_REGNUM;
5780 opcode = opcode << 8 | ir.modrm;
5784 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5785 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5788 case 0x0fb6: /* movzbS */
5789 case 0x0fb7: /* movzwS */
5790 case 0x0fbe: /* movsbS */
5791 case 0x0fbf: /* movswS */
5792 if (i386_record_modrm (&ir))
5794 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5797 case 0x8d: /* lea */
5798 if (i386_record_modrm (&ir))
5803 opcode = opcode << 8 | ir.modrm;
5808 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5810 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5813 case 0xa0: /* mov EAX */
5816 case 0xd7: /* xlat */
5817 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5820 case 0xa2: /* mov EAX */
5822 if (ir.override >= 0)
5824 if (record_full_memory_query)
5827 Process record ignores the memory change of instruction at address %s\n\
5828 because it can't get the value of the segment register.\n\
5829 Do you want to stop the program?"),
5830 paddress (gdbarch, ir.orig_addr)))
5836 if ((opcode & 1) == 0)
5839 ir.ot = ir.dflag + OT_WORD;
5842 if (record_read_memory (gdbarch, ir.addr, buf, 8))
5845 addr = extract_unsigned_integer (buf, 8, byte_order);
5849 if (record_read_memory (gdbarch, ir.addr, buf, 4))
5852 addr = extract_unsigned_integer (buf, 4, byte_order);
5856 if (record_read_memory (gdbarch, ir.addr, buf, 2))
5859 addr = extract_unsigned_integer (buf, 2, byte_order);
5861 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
5866 case 0xb0: /* mov R, Ib */
5874 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
5875 ? ((opcode & 0x7) | ir.rex_b)
5876 : ((opcode & 0x7) & 0x3));
5879 case 0xb8: /* mov R, Iv */
5887 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5890 case 0x91: /* xchg R, EAX */
5897 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5898 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7);
5901 case 0x86: /* xchg Ev, Gv */
5903 if ((opcode & 1) == 0)
5906 ir.ot = ir.dflag + OT_WORD;
5907 if (i386_record_modrm (&ir))
5912 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5914 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5918 if (i386_record_lea_modrm (&ir))
5922 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5924 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5927 case 0xc4: /* les Gv */
5928 case 0xc5: /* lds Gv */
5929 if (ir.regmap[X86_RECORD_R8_REGNUM])
5935 case 0x0fb2: /* lss Gv */
5936 case 0x0fb4: /* lfs Gv */
5937 case 0x0fb5: /* lgs Gv */
5938 if (i386_record_modrm (&ir))
5946 opcode = opcode << 8 | ir.modrm;
5951 case 0xc4: /* les Gv */
5952 regnum = X86_RECORD_ES_REGNUM;
5954 case 0xc5: /* lds Gv */
5955 regnum = X86_RECORD_DS_REGNUM;
5957 case 0x0fb2: /* lss Gv */
5958 regnum = X86_RECORD_SS_REGNUM;
5960 case 0x0fb4: /* lfs Gv */
5961 regnum = X86_RECORD_FS_REGNUM;
5963 case 0x0fb5: /* lgs Gv */
5964 regnum = X86_RECORD_GS_REGNUM;
5967 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5968 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5969 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5972 case 0xc0: /* shifts */
5978 if ((opcode & 1) == 0)
5981 ir.ot = ir.dflag + OT_WORD;
5982 if (i386_record_modrm (&ir))
5984 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
5986 if (i386_record_lea_modrm (&ir))
5992 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5994 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5996 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6003 if (i386_record_modrm (&ir))
6007 if (record_full_arch_list_add_reg (ir.regcache, ir.rm))
6012 if (i386_record_lea_modrm (&ir))
6017 case 0xd8: /* Floats. */
6025 if (i386_record_modrm (&ir))
6027 ir.reg |= ((opcode & 7) << 3);
6033 if (i386_record_lea_modrm_addr (&ir, &addr64))
6041 /* For fcom, ficom nothing to do. */
6047 /* For fcomp, ficomp pop FPU stack, store all. */
6048 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6075 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
6076 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
6077 of code, always affects st(0) register. */
6078 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6102 /* Handling fld, fild. */
6103 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6107 switch (ir.reg >> 4)
6110 if (record_full_arch_list_add_mem (addr64, 4))
6114 if (record_full_arch_list_add_mem (addr64, 8))
6120 if (record_full_arch_list_add_mem (addr64, 2))
6126 switch (ir.reg >> 4)
6129 if (record_full_arch_list_add_mem (addr64, 4))
6131 if (3 == (ir.reg & 7))
6133 /* For fstp m32fp. */
6134 if (i386_record_floats (gdbarch, &ir,
6135 I386_SAVE_FPU_REGS))
6140 if (record_full_arch_list_add_mem (addr64, 4))
6142 if ((3 == (ir.reg & 7))
6143 || (5 == (ir.reg & 7))
6144 || (7 == (ir.reg & 7)))
6146 /* For fstp insn. */
6147 if (i386_record_floats (gdbarch, &ir,
6148 I386_SAVE_FPU_REGS))
6153 if (record_full_arch_list_add_mem (addr64, 8))
6155 if (3 == (ir.reg & 7))
6157 /* For fstp m64fp. */
6158 if (i386_record_floats (gdbarch, &ir,
6159 I386_SAVE_FPU_REGS))
6164 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
6166 /* For fistp, fbld, fild, fbstp. */
6167 if (i386_record_floats (gdbarch, &ir,
6168 I386_SAVE_FPU_REGS))
6173 if (record_full_arch_list_add_mem (addr64, 2))
6182 if (i386_record_floats (gdbarch, &ir,
6183 I386_SAVE_FPU_ENV_REG_STACK))
6188 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
6193 if (i386_record_floats (gdbarch, &ir,
6194 I386_SAVE_FPU_ENV_REG_STACK))
6200 if (record_full_arch_list_add_mem (addr64, 28))
6205 if (record_full_arch_list_add_mem (addr64, 14))
6211 if (record_full_arch_list_add_mem (addr64, 2))
6213 /* Insn fstp, fbstp. */
6214 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6219 if (record_full_arch_list_add_mem (addr64, 10))
6225 if (record_full_arch_list_add_mem (addr64, 28))
6231 if (record_full_arch_list_add_mem (addr64, 14))
6235 if (record_full_arch_list_add_mem (addr64, 80))
6238 if (i386_record_floats (gdbarch, &ir,
6239 I386_SAVE_FPU_ENV_REG_STACK))
6243 if (record_full_arch_list_add_mem (addr64, 8))
6246 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6251 opcode = opcode << 8 | ir.modrm;
6256 /* Opcode is an extension of modR/M byte. */
6262 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6266 if (0x0c == (ir.modrm >> 4))
6268 if ((ir.modrm & 0x0f) <= 7)
6270 if (i386_record_floats (gdbarch, &ir,
6271 I386_SAVE_FPU_REGS))
6276 if (i386_record_floats (gdbarch, &ir,
6277 I387_ST0_REGNUM (tdep)))
6279 /* If only st(0) is changing, then we have already
6281 if ((ir.modrm & 0x0f) - 0x08)
6283 if (i386_record_floats (gdbarch, &ir,
6284 I387_ST0_REGNUM (tdep) +
6285 ((ir.modrm & 0x0f) - 0x08)))
6303 if (i386_record_floats (gdbarch, &ir,
6304 I387_ST0_REGNUM (tdep)))
6322 if (i386_record_floats (gdbarch, &ir,
6323 I386_SAVE_FPU_REGS))
6327 if (i386_record_floats (gdbarch, &ir,
6328 I387_ST0_REGNUM (tdep)))
6330 if (i386_record_floats (gdbarch, &ir,
6331 I387_ST0_REGNUM (tdep) + 1))
6338 if (0xe9 == ir.modrm)
6340 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6343 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6345 if (i386_record_floats (gdbarch, &ir,
6346 I387_ST0_REGNUM (tdep)))
6348 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6350 if (i386_record_floats (gdbarch, &ir,
6351 I387_ST0_REGNUM (tdep) +
6355 else if ((ir.modrm & 0x0f) - 0x08)
6357 if (i386_record_floats (gdbarch, &ir,
6358 I387_ST0_REGNUM (tdep) +
6359 ((ir.modrm & 0x0f) - 0x08)))
6365 if (0xe3 == ir.modrm)
6367 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
6370 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6372 if (i386_record_floats (gdbarch, &ir,
6373 I387_ST0_REGNUM (tdep)))
6375 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6377 if (i386_record_floats (gdbarch, &ir,
6378 I387_ST0_REGNUM (tdep) +
6382 else if ((ir.modrm & 0x0f) - 0x08)
6384 if (i386_record_floats (gdbarch, &ir,
6385 I387_ST0_REGNUM (tdep) +
6386 ((ir.modrm & 0x0f) - 0x08)))
6392 if ((0x0c == ir.modrm >> 4)
6393 || (0x0d == ir.modrm >> 4)
6394 || (0x0f == ir.modrm >> 4))
6396 if ((ir.modrm & 0x0f) <= 7)
6398 if (i386_record_floats (gdbarch, &ir,
6399 I387_ST0_REGNUM (tdep) +
6405 if (i386_record_floats (gdbarch, &ir,
6406 I387_ST0_REGNUM (tdep) +
6407 ((ir.modrm & 0x0f) - 0x08)))
6413 if (0x0c == ir.modrm >> 4)
6415 if (i386_record_floats (gdbarch, &ir,
6416 I387_FTAG_REGNUM (tdep)))
6419 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6421 if ((ir.modrm & 0x0f) <= 7)
6423 if (i386_record_floats (gdbarch, &ir,
6424 I387_ST0_REGNUM (tdep) +
6430 if (i386_record_floats (gdbarch, &ir,
6431 I386_SAVE_FPU_REGS))
6437 if ((0x0c == ir.modrm >> 4)
6438 || (0x0e == ir.modrm >> 4)
6439 || (0x0f == ir.modrm >> 4)
6440 || (0xd9 == ir.modrm))
6442 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6447 if (0xe0 == ir.modrm)
6449 if (record_full_arch_list_add_reg (ir.regcache,
6453 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6455 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6463 case 0xa4: /* movsS */
6465 case 0xaa: /* stosS */
6467 case 0x6c: /* insS */
6469 regcache_raw_read_unsigned (ir.regcache,
6470 ir.regmap[X86_RECORD_RECX_REGNUM],
6476 if ((opcode & 1) == 0)
6479 ir.ot = ir.dflag + OT_WORD;
6480 regcache_raw_read_unsigned (ir.regcache,
6481 ir.regmap[X86_RECORD_REDI_REGNUM],
6484 regcache_raw_read_unsigned (ir.regcache,
6485 ir.regmap[X86_RECORD_ES_REGNUM],
6487 regcache_raw_read_unsigned (ir.regcache,
6488 ir.regmap[X86_RECORD_DS_REGNUM],
6490 if (ir.aflag && (es != ds))
6492 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6493 if (record_full_memory_query)
6496 Process record ignores the memory change of instruction at address %s\n\
6497 because it can't get the value of the segment register.\n\
6498 Do you want to stop the program?"),
6499 paddress (gdbarch, ir.orig_addr)))
6505 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
6509 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6510 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6511 if (opcode == 0xa4 || opcode == 0xa5)
6512 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6513 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6514 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6518 case 0xa6: /* cmpsS */
6520 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6521 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6522 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6523 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6524 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6527 case 0xac: /* lodsS */
6529 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6530 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6531 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6532 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6533 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6536 case 0xae: /* scasS */
6538 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6539 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6540 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6541 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6544 case 0x6e: /* outsS */
6546 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6547 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6548 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6549 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6552 case 0xe4: /* port I/O */
6556 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6557 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6567 case 0xc2: /* ret im */
6568 case 0xc3: /* ret */
6569 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6570 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6573 case 0xca: /* lret im */
6574 case 0xcb: /* lret */
6575 case 0xcf: /* iret */
6576 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6577 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6578 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6581 case 0xe8: /* call im */
6582 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6584 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6588 case 0x9a: /* lcall im */
6589 if (ir.regmap[X86_RECORD_R8_REGNUM])
6594 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6595 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6599 case 0xe9: /* jmp im */
6600 case 0xea: /* ljmp im */
6601 case 0xeb: /* jmp Jb */
6602 case 0x70: /* jcc Jb */
6618 case 0x0f80: /* jcc Jv */
6636 case 0x0f90: /* setcc Gv */
6652 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6654 if (i386_record_modrm (&ir))
6657 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
6661 if (i386_record_lea_modrm (&ir))
6666 case 0x0f40: /* cmov Gv, Ev */
6682 if (i386_record_modrm (&ir))
6685 if (ir.dflag == OT_BYTE)
6687 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
6691 case 0x9c: /* pushf */
6692 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6693 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6695 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6699 case 0x9d: /* popf */
6700 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6701 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6704 case 0x9e: /* sahf */
6705 if (ir.regmap[X86_RECORD_R8_REGNUM])
6711 case 0xf5: /* cmc */
6712 case 0xf8: /* clc */
6713 case 0xf9: /* stc */
6714 case 0xfc: /* cld */
6715 case 0xfd: /* std */
6716 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6719 case 0x9f: /* lahf */
6720 if (ir.regmap[X86_RECORD_R8_REGNUM])
6725 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6726 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6729 /* bit operations */
6730 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6731 ir.ot = ir.dflag + OT_WORD;
6732 if (i386_record_modrm (&ir))
6737 opcode = opcode << 8 | ir.modrm;
6743 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6746 if (i386_record_lea_modrm (&ir))
6750 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6753 case 0x0fa3: /* bt Gv, Ev */
6754 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6757 case 0x0fab: /* bts */
6758 case 0x0fb3: /* btr */
6759 case 0x0fbb: /* btc */
6760 ir.ot = ir.dflag + OT_WORD;
6761 if (i386_record_modrm (&ir))
6764 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6768 if (i386_record_lea_modrm_addr (&ir, &addr64))
6770 regcache_raw_read_unsigned (ir.regcache,
6771 ir.regmap[ir.reg | rex_r],
6776 addr64 += ((int16_t) addr >> 4) << 4;
6779 addr64 += ((int32_t) addr >> 5) << 5;
6782 addr64 += ((int64_t) addr >> 6) << 6;
6785 if (record_full_arch_list_add_mem (addr64, 1 << ir.ot))
6787 if (i386_record_lea_modrm (&ir))
6790 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6793 case 0x0fbc: /* bsf */
6794 case 0x0fbd: /* bsr */
6795 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6796 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6800 case 0x27: /* daa */
6801 case 0x2f: /* das */
6802 case 0x37: /* aaa */
6803 case 0x3f: /* aas */
6804 case 0xd4: /* aam */
6805 case 0xd5: /* aad */
6806 if (ir.regmap[X86_RECORD_R8_REGNUM])
6811 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6812 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6816 case 0x90: /* nop */
6817 if (prefixes & PREFIX_LOCK)
6824 case 0x9b: /* fwait */
6825 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
6827 opcode = (uint32_t) opcode8;
6833 case 0xcc: /* int3 */
6834 printf_unfiltered (_("Process record does not support instruction "
6841 case 0xcd: /* int */
6845 if (record_read_memory (gdbarch, ir.addr, &interrupt, 1))
6848 if (interrupt != 0x80
6849 || tdep->i386_intx80_record == NULL)
6851 printf_unfiltered (_("Process record does not support "
6852 "instruction int 0x%02x.\n"),
6857 ret = tdep->i386_intx80_record (ir.regcache);
6864 case 0xce: /* into */
6865 printf_unfiltered (_("Process record does not support "
6866 "instruction into.\n"));
6871 case 0xfa: /* cli */
6872 case 0xfb: /* sti */
6875 case 0x62: /* bound */
6876 printf_unfiltered (_("Process record does not support "
6877 "instruction bound.\n"));
6882 case 0x0fc8: /* bswap reg */
6890 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
6893 case 0xd6: /* salc */
6894 if (ir.regmap[X86_RECORD_R8_REGNUM])
6899 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6900 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6903 case 0xe0: /* loopnz */
6904 case 0xe1: /* loopz */
6905 case 0xe2: /* loop */
6906 case 0xe3: /* jecxz */
6907 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6908 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6911 case 0x0f30: /* wrmsr */
6912 printf_unfiltered (_("Process record does not support "
6913 "instruction wrmsr.\n"));
6918 case 0x0f32: /* rdmsr */
6919 printf_unfiltered (_("Process record does not support "
6920 "instruction rdmsr.\n"));
6925 case 0x0f31: /* rdtsc */
6926 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6927 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6930 case 0x0f34: /* sysenter */
6933 if (ir.regmap[X86_RECORD_R8_REGNUM])
6938 if (tdep->i386_sysenter_record == NULL)
6940 printf_unfiltered (_("Process record does not support "
6941 "instruction sysenter.\n"));
6945 ret = tdep->i386_sysenter_record (ir.regcache);
6951 case 0x0f35: /* sysexit */
6952 printf_unfiltered (_("Process record does not support "
6953 "instruction sysexit.\n"));
6958 case 0x0f05: /* syscall */
6961 if (tdep->i386_syscall_record == NULL)
6963 printf_unfiltered (_("Process record does not support "
6964 "instruction syscall.\n"));
6968 ret = tdep->i386_syscall_record (ir.regcache);
6974 case 0x0f07: /* sysret */
6975 printf_unfiltered (_("Process record does not support "
6976 "instruction sysret.\n"));
6981 case 0x0fa2: /* cpuid */
6982 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6983 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6984 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6985 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
6988 case 0xf4: /* hlt */
6989 printf_unfiltered (_("Process record does not support "
6990 "instruction hlt.\n"));
6996 if (i386_record_modrm (&ir))
7003 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7007 if (i386_record_lea_modrm (&ir))
7016 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7020 opcode = opcode << 8 | ir.modrm;
7027 if (i386_record_modrm (&ir))
7038 opcode = opcode << 8 | ir.modrm;
7041 if (ir.override >= 0)
7043 if (record_full_memory_query)
7046 Process record ignores the memory change of instruction at address %s\n\
7047 because it can't get the value of the segment register.\n\
7048 Do you want to stop the program?"),
7049 paddress (gdbarch, ir.orig_addr)))
7055 if (i386_record_lea_modrm_addr (&ir, &addr64))
7057 if (record_full_arch_list_add_mem (addr64, 2))
7060 if (ir.regmap[X86_RECORD_R8_REGNUM])
7062 if (record_full_arch_list_add_mem (addr64, 8))
7067 if (record_full_arch_list_add_mem (addr64, 4))
7078 case 0: /* monitor */
7081 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7085 opcode = opcode << 8 | ir.modrm;
7093 if (ir.override >= 0)
7095 if (record_full_memory_query)
7098 Process record ignores the memory change of instruction at address %s\n\
7099 because it can't get the value of the segment register.\n\
7100 Do you want to stop the program?"),
7101 paddress (gdbarch, ir.orig_addr)))
7109 if (i386_record_lea_modrm_addr (&ir, &addr64))
7111 if (record_full_arch_list_add_mem (addr64, 2))
7114 if (ir.regmap[X86_RECORD_R8_REGNUM])
7116 if (record_full_arch_list_add_mem (addr64, 8))
7121 if (record_full_arch_list_add_mem (addr64, 4))
7133 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7134 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7138 else if (ir.rm == 1)
7146 opcode = opcode << 8 | ir.modrm;
7153 if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
7159 if (i386_record_lea_modrm (&ir))
7162 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7165 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7167 case 7: /* invlpg */
7170 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
7171 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
7175 opcode = opcode << 8 | ir.modrm;
7180 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7184 opcode = opcode << 8 | ir.modrm;
7190 case 0x0f08: /* invd */
7191 case 0x0f09: /* wbinvd */
7194 case 0x63: /* arpl */
7195 if (i386_record_modrm (&ir))
7197 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
7199 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
7200 ? (ir.reg | rex_r) : ir.rm);
7204 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
7205 if (i386_record_lea_modrm (&ir))
7208 if (!ir.regmap[X86_RECORD_R8_REGNUM])
7209 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7212 case 0x0f02: /* lar */
7213 case 0x0f03: /* lsl */
7214 if (i386_record_modrm (&ir))
7216 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7217 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7221 if (i386_record_modrm (&ir))
7223 if (ir.mod == 3 && ir.reg == 3)
7226 opcode = opcode << 8 | ir.modrm;
7238 /* nop (multi byte) */
7241 case 0x0f20: /* mov reg, crN */
7242 case 0x0f22: /* mov crN, reg */
7243 if (i386_record_modrm (&ir))
7245 if ((ir.modrm & 0xc0) != 0xc0)
7248 opcode = opcode << 8 | ir.modrm;
7259 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7261 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7265 opcode = opcode << 8 | ir.modrm;
7271 case 0x0f21: /* mov reg, drN */
7272 case 0x0f23: /* mov drN, reg */
7273 if (i386_record_modrm (&ir))
7275 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
7276 || ir.reg == 5 || ir.reg >= 8)
7279 opcode = opcode << 8 | ir.modrm;
7283 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7285 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7288 case 0x0f06: /* clts */
7289 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7292 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7294 case 0x0f0d: /* 3DNow! prefetch */
7297 case 0x0f0e: /* 3DNow! femms */
7298 case 0x0f77: /* emms */
7299 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
7301 record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
7304 case 0x0f0f: /* 3DNow! data */
7305 if (i386_record_modrm (&ir))
7307 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7312 case 0x0c: /* 3DNow! pi2fw */
7313 case 0x0d: /* 3DNow! pi2fd */
7314 case 0x1c: /* 3DNow! pf2iw */
7315 case 0x1d: /* 3DNow! pf2id */
7316 case 0x8a: /* 3DNow! pfnacc */
7317 case 0x8e: /* 3DNow! pfpnacc */
7318 case 0x90: /* 3DNow! pfcmpge */
7319 case 0x94: /* 3DNow! pfmin */
7320 case 0x96: /* 3DNow! pfrcp */
7321 case 0x97: /* 3DNow! pfrsqrt */
7322 case 0x9a: /* 3DNow! pfsub */
7323 case 0x9e: /* 3DNow! pfadd */
7324 case 0xa0: /* 3DNow! pfcmpgt */
7325 case 0xa4: /* 3DNow! pfmax */
7326 case 0xa6: /* 3DNow! pfrcpit1 */
7327 case 0xa7: /* 3DNow! pfrsqit1 */
7328 case 0xaa: /* 3DNow! pfsubr */
7329 case 0xae: /* 3DNow! pfacc */
7330 case 0xb0: /* 3DNow! pfcmpeq */
7331 case 0xb4: /* 3DNow! pfmul */
7332 case 0xb6: /* 3DNow! pfrcpit2 */
7333 case 0xb7: /* 3DNow! pmulhrw */
7334 case 0xbb: /* 3DNow! pswapd */
7335 case 0xbf: /* 3DNow! pavgusb */
7336 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7337 goto no_support_3dnow_data;
7338 record_full_arch_list_add_reg (ir.regcache, ir.reg);
7342 no_support_3dnow_data:
7343 opcode = (opcode << 8) | opcode8;
7349 case 0x0faa: /* rsm */
7350 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7351 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7352 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
7353 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7354 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
7355 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
7356 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
7357 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
7358 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
7362 if (i386_record_modrm (&ir))
7366 case 0: /* fxsave */
7370 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7371 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
7373 if (record_full_arch_list_add_mem (tmpu64, 512))
7378 case 1: /* fxrstor */
7382 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7384 for (i = I387_MM0_REGNUM (tdep);
7385 i386_mmx_regnum_p (gdbarch, i); i++)
7386 record_full_arch_list_add_reg (ir.regcache, i);
7388 for (i = I387_XMM0_REGNUM (tdep);
7389 i386_xmm_regnum_p (gdbarch, i); i++)
7390 record_full_arch_list_add_reg (ir.regcache, i);
7392 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7393 record_full_arch_list_add_reg (ir.regcache,
7394 I387_MXCSR_REGNUM(tdep));
7396 for (i = I387_ST0_REGNUM (tdep);
7397 i386_fp_regnum_p (gdbarch, i); i++)
7398 record_full_arch_list_add_reg (ir.regcache, i);
7400 for (i = I387_FCTRL_REGNUM (tdep);
7401 i386_fpc_regnum_p (gdbarch, i); i++)
7402 record_full_arch_list_add_reg (ir.regcache, i);
7406 case 2: /* ldmxcsr */
7407 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7409 record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
7412 case 3: /* stmxcsr */
7414 if (i386_record_lea_modrm (&ir))
7418 case 5: /* lfence */
7419 case 6: /* mfence */
7420 case 7: /* sfence clflush */
7424 opcode = (opcode << 8) | ir.modrm;
7430 case 0x0fc3: /* movnti */
7431 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
7432 if (i386_record_modrm (&ir))
7437 if (i386_record_lea_modrm (&ir))
7441 /* Add prefix to opcode. */
7556 /* Mask out PREFIX_ADDR. */
7557 switch ((prefixes & ~PREFIX_ADDR))
7569 reswitch_prefix_add:
7577 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7580 opcode = (uint32_t) opcode8 | opcode << 8;
7581 goto reswitch_prefix_add;
7584 case 0x0f10: /* movups */
7585 case 0x660f10: /* movupd */
7586 case 0xf30f10: /* movss */
7587 case 0xf20f10: /* movsd */
7588 case 0x0f12: /* movlps */
7589 case 0x660f12: /* movlpd */
7590 case 0xf30f12: /* movsldup */
7591 case 0xf20f12: /* movddup */
7592 case 0x0f14: /* unpcklps */
7593 case 0x660f14: /* unpcklpd */
7594 case 0x0f15: /* unpckhps */
7595 case 0x660f15: /* unpckhpd */
7596 case 0x0f16: /* movhps */
7597 case 0x660f16: /* movhpd */
7598 case 0xf30f16: /* movshdup */
7599 case 0x0f28: /* movaps */
7600 case 0x660f28: /* movapd */
7601 case 0x0f2a: /* cvtpi2ps */
7602 case 0x660f2a: /* cvtpi2pd */
7603 case 0xf30f2a: /* cvtsi2ss */
7604 case 0xf20f2a: /* cvtsi2sd */
7605 case 0x0f2c: /* cvttps2pi */
7606 case 0x660f2c: /* cvttpd2pi */
7607 case 0x0f2d: /* cvtps2pi */
7608 case 0x660f2d: /* cvtpd2pi */
7609 case 0x660f3800: /* pshufb */
7610 case 0x660f3801: /* phaddw */
7611 case 0x660f3802: /* phaddd */
7612 case 0x660f3803: /* phaddsw */
7613 case 0x660f3804: /* pmaddubsw */
7614 case 0x660f3805: /* phsubw */
7615 case 0x660f3806: /* phsubd */
7616 case 0x660f3807: /* phsubsw */
7617 case 0x660f3808: /* psignb */
7618 case 0x660f3809: /* psignw */
7619 case 0x660f380a: /* psignd */
7620 case 0x660f380b: /* pmulhrsw */
7621 case 0x660f3810: /* pblendvb */
7622 case 0x660f3814: /* blendvps */
7623 case 0x660f3815: /* blendvpd */
7624 case 0x660f381c: /* pabsb */
7625 case 0x660f381d: /* pabsw */
7626 case 0x660f381e: /* pabsd */
7627 case 0x660f3820: /* pmovsxbw */
7628 case 0x660f3821: /* pmovsxbd */
7629 case 0x660f3822: /* pmovsxbq */
7630 case 0x660f3823: /* pmovsxwd */
7631 case 0x660f3824: /* pmovsxwq */
7632 case 0x660f3825: /* pmovsxdq */
7633 case 0x660f3828: /* pmuldq */
7634 case 0x660f3829: /* pcmpeqq */
7635 case 0x660f382a: /* movntdqa */
7636 case 0x660f3a08: /* roundps */
7637 case 0x660f3a09: /* roundpd */
7638 case 0x660f3a0a: /* roundss */
7639 case 0x660f3a0b: /* roundsd */
7640 case 0x660f3a0c: /* blendps */
7641 case 0x660f3a0d: /* blendpd */
7642 case 0x660f3a0e: /* pblendw */
7643 case 0x660f3a0f: /* palignr */
7644 case 0x660f3a20: /* pinsrb */
7645 case 0x660f3a21: /* insertps */
7646 case 0x660f3a22: /* pinsrd pinsrq */
7647 case 0x660f3a40: /* dpps */
7648 case 0x660f3a41: /* dppd */
7649 case 0x660f3a42: /* mpsadbw */
7650 case 0x660f3a60: /* pcmpestrm */
7651 case 0x660f3a61: /* pcmpestri */
7652 case 0x660f3a62: /* pcmpistrm */
7653 case 0x660f3a63: /* pcmpistri */
7654 case 0x0f51: /* sqrtps */
7655 case 0x660f51: /* sqrtpd */
7656 case 0xf20f51: /* sqrtsd */
7657 case 0xf30f51: /* sqrtss */
7658 case 0x0f52: /* rsqrtps */
7659 case 0xf30f52: /* rsqrtss */
7660 case 0x0f53: /* rcpps */
7661 case 0xf30f53: /* rcpss */
7662 case 0x0f54: /* andps */
7663 case 0x660f54: /* andpd */
7664 case 0x0f55: /* andnps */
7665 case 0x660f55: /* andnpd */
7666 case 0x0f56: /* orps */
7667 case 0x660f56: /* orpd */
7668 case 0x0f57: /* xorps */
7669 case 0x660f57: /* xorpd */
7670 case 0x0f58: /* addps */
7671 case 0x660f58: /* addpd */
7672 case 0xf20f58: /* addsd */
7673 case 0xf30f58: /* addss */
7674 case 0x0f59: /* mulps */
7675 case 0x660f59: /* mulpd */
7676 case 0xf20f59: /* mulsd */
7677 case 0xf30f59: /* mulss */
7678 case 0x0f5a: /* cvtps2pd */
7679 case 0x660f5a: /* cvtpd2ps */
7680 case 0xf20f5a: /* cvtsd2ss */
7681 case 0xf30f5a: /* cvtss2sd */
7682 case 0x0f5b: /* cvtdq2ps */
7683 case 0x660f5b: /* cvtps2dq */
7684 case 0xf30f5b: /* cvttps2dq */
7685 case 0x0f5c: /* subps */
7686 case 0x660f5c: /* subpd */
7687 case 0xf20f5c: /* subsd */
7688 case 0xf30f5c: /* subss */
7689 case 0x0f5d: /* minps */
7690 case 0x660f5d: /* minpd */
7691 case 0xf20f5d: /* minsd */
7692 case 0xf30f5d: /* minss */
7693 case 0x0f5e: /* divps */
7694 case 0x660f5e: /* divpd */
7695 case 0xf20f5e: /* divsd */
7696 case 0xf30f5e: /* divss */
7697 case 0x0f5f: /* maxps */
7698 case 0x660f5f: /* maxpd */
7699 case 0xf20f5f: /* maxsd */
7700 case 0xf30f5f: /* maxss */
7701 case 0x660f60: /* punpcklbw */
7702 case 0x660f61: /* punpcklwd */
7703 case 0x660f62: /* punpckldq */
7704 case 0x660f63: /* packsswb */
7705 case 0x660f64: /* pcmpgtb */
7706 case 0x660f65: /* pcmpgtw */
7707 case 0x660f66: /* pcmpgtd */
7708 case 0x660f67: /* packuswb */
7709 case 0x660f68: /* punpckhbw */
7710 case 0x660f69: /* punpckhwd */
7711 case 0x660f6a: /* punpckhdq */
7712 case 0x660f6b: /* packssdw */
7713 case 0x660f6c: /* punpcklqdq */
7714 case 0x660f6d: /* punpckhqdq */
7715 case 0x660f6e: /* movd */
7716 case 0x660f6f: /* movdqa */
7717 case 0xf30f6f: /* movdqu */
7718 case 0x660f70: /* pshufd */
7719 case 0xf20f70: /* pshuflw */
7720 case 0xf30f70: /* pshufhw */
7721 case 0x660f74: /* pcmpeqb */
7722 case 0x660f75: /* pcmpeqw */
7723 case 0x660f76: /* pcmpeqd */
7724 case 0x660f7c: /* haddpd */
7725 case 0xf20f7c: /* haddps */
7726 case 0x660f7d: /* hsubpd */
7727 case 0xf20f7d: /* hsubps */
7728 case 0xf30f7e: /* movq */
7729 case 0x0fc2: /* cmpps */
7730 case 0x660fc2: /* cmppd */
7731 case 0xf20fc2: /* cmpsd */
7732 case 0xf30fc2: /* cmpss */
7733 case 0x660fc4: /* pinsrw */
7734 case 0x0fc6: /* shufps */
7735 case 0x660fc6: /* shufpd */
7736 case 0x660fd0: /* addsubpd */
7737 case 0xf20fd0: /* addsubps */
7738 case 0x660fd1: /* psrlw */
7739 case 0x660fd2: /* psrld */
7740 case 0x660fd3: /* psrlq */
7741 case 0x660fd4: /* paddq */
7742 case 0x660fd5: /* pmullw */
7743 case 0xf30fd6: /* movq2dq */
7744 case 0x660fd8: /* psubusb */
7745 case 0x660fd9: /* psubusw */
7746 case 0x660fda: /* pminub */
7747 case 0x660fdb: /* pand */
7748 case 0x660fdc: /* paddusb */
7749 case 0x660fdd: /* paddusw */
7750 case 0x660fde: /* pmaxub */
7751 case 0x660fdf: /* pandn */
7752 case 0x660fe0: /* pavgb */
7753 case 0x660fe1: /* psraw */
7754 case 0x660fe2: /* psrad */
7755 case 0x660fe3: /* pavgw */
7756 case 0x660fe4: /* pmulhuw */
7757 case 0x660fe5: /* pmulhw */
7758 case 0x660fe6: /* cvttpd2dq */
7759 case 0xf20fe6: /* cvtpd2dq */
7760 case 0xf30fe6: /* cvtdq2pd */
7761 case 0x660fe8: /* psubsb */
7762 case 0x660fe9: /* psubsw */
7763 case 0x660fea: /* pminsw */
7764 case 0x660feb: /* por */
7765 case 0x660fec: /* paddsb */
7766 case 0x660fed: /* paddsw */
7767 case 0x660fee: /* pmaxsw */
7768 case 0x660fef: /* pxor */
7769 case 0xf20ff0: /* lddqu */
7770 case 0x660ff1: /* psllw */
7771 case 0x660ff2: /* pslld */
7772 case 0x660ff3: /* psllq */
7773 case 0x660ff4: /* pmuludq */
7774 case 0x660ff5: /* pmaddwd */
7775 case 0x660ff6: /* psadbw */
7776 case 0x660ff8: /* psubb */
7777 case 0x660ff9: /* psubw */
7778 case 0x660ffa: /* psubd */
7779 case 0x660ffb: /* psubq */
7780 case 0x660ffc: /* paddb */
7781 case 0x660ffd: /* paddw */
7782 case 0x660ffe: /* paddd */
7783 if (i386_record_modrm (&ir))
7786 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
7788 record_full_arch_list_add_reg (ir.regcache,
7789 I387_XMM0_REGNUM (tdep) + ir.reg);
7790 if ((opcode & 0xfffffffc) == 0x660f3a60)
7791 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7794 case 0x0f11: /* movups */
7795 case 0x660f11: /* movupd */
7796 case 0xf30f11: /* movss */
7797 case 0xf20f11: /* movsd */
7798 case 0x0f13: /* movlps */
7799 case 0x660f13: /* movlpd */
7800 case 0x0f17: /* movhps */
7801 case 0x660f17: /* movhpd */
7802 case 0x0f29: /* movaps */
7803 case 0x660f29: /* movapd */
7804 case 0x660f3a14: /* pextrb */
7805 case 0x660f3a15: /* pextrw */
7806 case 0x660f3a16: /* pextrd pextrq */
7807 case 0x660f3a17: /* extractps */
7808 case 0x660f7f: /* movdqa */
7809 case 0xf30f7f: /* movdqu */
7810 if (i386_record_modrm (&ir))
7814 if (opcode == 0x0f13 || opcode == 0x660f13
7815 || opcode == 0x0f17 || opcode == 0x660f17)
7818 if (!i386_xmm_regnum_p (gdbarch,
7819 I387_XMM0_REGNUM (tdep) + ir.rm))
7821 record_full_arch_list_add_reg (ir.regcache,
7822 I387_XMM0_REGNUM (tdep) + ir.rm);
7844 if (i386_record_lea_modrm (&ir))
7849 case 0x0f2b: /* movntps */
7850 case 0x660f2b: /* movntpd */
7851 case 0x0fe7: /* movntq */
7852 case 0x660fe7: /* movntdq */
7855 if (opcode == 0x0fe7)
7859 if (i386_record_lea_modrm (&ir))
7863 case 0xf30f2c: /* cvttss2si */
7864 case 0xf20f2c: /* cvttsd2si */
7865 case 0xf30f2d: /* cvtss2si */
7866 case 0xf20f2d: /* cvtsd2si */
7867 case 0xf20f38f0: /* crc32 */
7868 case 0xf20f38f1: /* crc32 */
7869 case 0x0f50: /* movmskps */
7870 case 0x660f50: /* movmskpd */
7871 case 0x0fc5: /* pextrw */
7872 case 0x660fc5: /* pextrw */
7873 case 0x0fd7: /* pmovmskb */
7874 case 0x660fd7: /* pmovmskb */
7875 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7878 case 0x0f3800: /* pshufb */
7879 case 0x0f3801: /* phaddw */
7880 case 0x0f3802: /* phaddd */
7881 case 0x0f3803: /* phaddsw */
7882 case 0x0f3804: /* pmaddubsw */
7883 case 0x0f3805: /* phsubw */
7884 case 0x0f3806: /* phsubd */
7885 case 0x0f3807: /* phsubsw */
7886 case 0x0f3808: /* psignb */
7887 case 0x0f3809: /* psignw */
7888 case 0x0f380a: /* psignd */
7889 case 0x0f380b: /* pmulhrsw */
7890 case 0x0f381c: /* pabsb */
7891 case 0x0f381d: /* pabsw */
7892 case 0x0f381e: /* pabsd */
7893 case 0x0f382b: /* packusdw */
7894 case 0x0f3830: /* pmovzxbw */
7895 case 0x0f3831: /* pmovzxbd */
7896 case 0x0f3832: /* pmovzxbq */
7897 case 0x0f3833: /* pmovzxwd */
7898 case 0x0f3834: /* pmovzxwq */
7899 case 0x0f3835: /* pmovzxdq */
7900 case 0x0f3837: /* pcmpgtq */
7901 case 0x0f3838: /* pminsb */
7902 case 0x0f3839: /* pminsd */
7903 case 0x0f383a: /* pminuw */
7904 case 0x0f383b: /* pminud */
7905 case 0x0f383c: /* pmaxsb */
7906 case 0x0f383d: /* pmaxsd */
7907 case 0x0f383e: /* pmaxuw */
7908 case 0x0f383f: /* pmaxud */
7909 case 0x0f3840: /* pmulld */
7910 case 0x0f3841: /* phminposuw */
7911 case 0x0f3a0f: /* palignr */
7912 case 0x0f60: /* punpcklbw */
7913 case 0x0f61: /* punpcklwd */
7914 case 0x0f62: /* punpckldq */
7915 case 0x0f63: /* packsswb */
7916 case 0x0f64: /* pcmpgtb */
7917 case 0x0f65: /* pcmpgtw */
7918 case 0x0f66: /* pcmpgtd */
7919 case 0x0f67: /* packuswb */
7920 case 0x0f68: /* punpckhbw */
7921 case 0x0f69: /* punpckhwd */
7922 case 0x0f6a: /* punpckhdq */
7923 case 0x0f6b: /* packssdw */
7924 case 0x0f6e: /* movd */
7925 case 0x0f6f: /* movq */
7926 case 0x0f70: /* pshufw */
7927 case 0x0f74: /* pcmpeqb */
7928 case 0x0f75: /* pcmpeqw */
7929 case 0x0f76: /* pcmpeqd */
7930 case 0x0fc4: /* pinsrw */
7931 case 0x0fd1: /* psrlw */
7932 case 0x0fd2: /* psrld */
7933 case 0x0fd3: /* psrlq */
7934 case 0x0fd4: /* paddq */
7935 case 0x0fd5: /* pmullw */
7936 case 0xf20fd6: /* movdq2q */
7937 case 0x0fd8: /* psubusb */
7938 case 0x0fd9: /* psubusw */
7939 case 0x0fda: /* pminub */
7940 case 0x0fdb: /* pand */
7941 case 0x0fdc: /* paddusb */
7942 case 0x0fdd: /* paddusw */
7943 case 0x0fde: /* pmaxub */
7944 case 0x0fdf: /* pandn */
7945 case 0x0fe0: /* pavgb */
7946 case 0x0fe1: /* psraw */
7947 case 0x0fe2: /* psrad */
7948 case 0x0fe3: /* pavgw */
7949 case 0x0fe4: /* pmulhuw */
7950 case 0x0fe5: /* pmulhw */
7951 case 0x0fe8: /* psubsb */
7952 case 0x0fe9: /* psubsw */
7953 case 0x0fea: /* pminsw */
7954 case 0x0feb: /* por */
7955 case 0x0fec: /* paddsb */
7956 case 0x0fed: /* paddsw */
7957 case 0x0fee: /* pmaxsw */
7958 case 0x0fef: /* pxor */
7959 case 0x0ff1: /* psllw */
7960 case 0x0ff2: /* pslld */
7961 case 0x0ff3: /* psllq */
7962 case 0x0ff4: /* pmuludq */
7963 case 0x0ff5: /* pmaddwd */
7964 case 0x0ff6: /* psadbw */
7965 case 0x0ff8: /* psubb */
7966 case 0x0ff9: /* psubw */
7967 case 0x0ffa: /* psubd */
7968 case 0x0ffb: /* psubq */
7969 case 0x0ffc: /* paddb */
7970 case 0x0ffd: /* paddw */
7971 case 0x0ffe: /* paddd */
7972 if (i386_record_modrm (&ir))
7974 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7976 record_full_arch_list_add_reg (ir.regcache,
7977 I387_MM0_REGNUM (tdep) + ir.reg);
7980 case 0x0f71: /* psllw */
7981 case 0x0f72: /* pslld */
7982 case 0x0f73: /* psllq */
7983 if (i386_record_modrm (&ir))
7985 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7987 record_full_arch_list_add_reg (ir.regcache,
7988 I387_MM0_REGNUM (tdep) + ir.rm);
7991 case 0x660f71: /* psllw */
7992 case 0x660f72: /* pslld */
7993 case 0x660f73: /* psllq */
7994 if (i386_record_modrm (&ir))
7997 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
7999 record_full_arch_list_add_reg (ir.regcache,
8000 I387_XMM0_REGNUM (tdep) + ir.rm);
8003 case 0x0f7e: /* movd */
8004 case 0x660f7e: /* movd */
8005 if (i386_record_modrm (&ir))
8008 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
8015 if (i386_record_lea_modrm (&ir))
8020 case 0x0f7f: /* movq */
8021 if (i386_record_modrm (&ir))
8025 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
8027 record_full_arch_list_add_reg (ir.regcache,
8028 I387_MM0_REGNUM (tdep) + ir.rm);
8033 if (i386_record_lea_modrm (&ir))
8038 case 0xf30fb8: /* popcnt */
8039 if (i386_record_modrm (&ir))
8041 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
8042 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
8045 case 0x660fd6: /* movq */
8046 if (i386_record_modrm (&ir))
8051 if (!i386_xmm_regnum_p (gdbarch,
8052 I387_XMM0_REGNUM (tdep) + ir.rm))
8054 record_full_arch_list_add_reg (ir.regcache,
8055 I387_XMM0_REGNUM (tdep) + ir.rm);
8060 if (i386_record_lea_modrm (&ir))
8065 case 0x660f3817: /* ptest */
8066 case 0x0f2e: /* ucomiss */
8067 case 0x660f2e: /* ucomisd */
8068 case 0x0f2f: /* comiss */
8069 case 0x660f2f: /* comisd */
8070 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
8073 case 0x0ff7: /* maskmovq */
8074 regcache_raw_read_unsigned (ir.regcache,
8075 ir.regmap[X86_RECORD_REDI_REGNUM],
8077 if (record_full_arch_list_add_mem (addr, 64))
8081 case 0x660ff7: /* maskmovdqu */
8082 regcache_raw_read_unsigned (ir.regcache,
8083 ir.regmap[X86_RECORD_REDI_REGNUM],
8085 if (record_full_arch_list_add_mem (addr, 128))
8100 /* In the future, maybe still need to deal with need_dasm. */
8101 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
8102 if (record_full_arch_list_add_end ())
8108 printf_unfiltered (_("Process record does not support instruction 0x%02x "
8109 "at address %s.\n"),
8110 (unsigned int) (opcode),
8111 paddress (gdbarch, ir.orig_addr));
8115 static const int i386_record_regmap[] =
8117 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
8118 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
8119 0, 0, 0, 0, 0, 0, 0, 0,
8120 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
8121 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
8124 /* Check that the given address appears suitable for a fast
8125 tracepoint, which on x86-64 means that we need an instruction of at
8126 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8127 jump and not have to worry about program jumps to an address in the
8128 middle of the tracepoint jump. On x86, it may be possible to use
8129 4-byte jumps with a 2-byte offset to a trampoline located in the
8130 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8131 of instruction to replace, and 0 if not, plus an explanatory
8135 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, CORE_ADDR addr,
8140 /* Ask the target for the minimum instruction length supported. */
8141 jumplen = target_get_min_fast_tracepoint_insn_len ();
8145 /* If the target does not support the get_min_fast_tracepoint_insn_len
8146 operation, assume that fast tracepoints will always be implemented
8147 using 4-byte relative jumps on both x86 and x86-64. */
8150 else if (jumplen == 0)
8152 /* If the target does support get_min_fast_tracepoint_insn_len but
8153 returns zero, then the IPA has not loaded yet. In this case,
8154 we optimistically assume that truncated 2-byte relative jumps
8155 will be available on x86, and compensate later if this assumption
8156 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8157 jumps will always be used. */
8158 jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4;
8161 /* Check for fit. */
8162 len = gdb_insn_length (gdbarch, addr);
8166 /* Return a bit of target-specific detail to add to the caller's
8167 generic failure message. */
8169 *msg = string_printf (_("; instruction is only %d bytes long, "
8170 "need at least %d bytes for the jump"),
8182 /* Return a floating-point format for a floating-point variable of
8183 length LEN in bits. If non-NULL, NAME is the name of its type.
8184 If no suitable type is found, return NULL. */
8186 const struct floatformat **
8187 i386_floatformat_for_type (struct gdbarch *gdbarch,
8188 const char *name, int len)
8190 if (len == 128 && name)
8191 if (strcmp (name, "__float128") == 0
8192 || strcmp (name, "_Float128") == 0
8193 || strcmp (name, "complex _Float128") == 0)
8194 return floatformats_ia64_quad;
8196 return default_floatformat_for_type (gdbarch, name, len);
8200 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
8201 struct tdesc_arch_data *tdesc_data)
8203 const struct target_desc *tdesc = tdep->tdesc;
8204 const struct tdesc_feature *feature_core;
8206 const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx,
8207 *feature_avx512, *feature_pkeys;
8208 int i, num_regs, valid_p;
8210 if (! tdesc_has_registers (tdesc))
8213 /* Get core registers. */
8214 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
8215 if (feature_core == NULL)
8218 /* Get SSE registers. */
8219 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
8221 /* Try AVX registers. */
8222 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
8224 /* Try MPX registers. */
8225 feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx");
8227 /* Try AVX512 registers. */
8228 feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512");
8231 feature_pkeys = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys");
8235 /* The XCR0 bits. */
8238 /* AVX512 register description requires AVX register description. */
8242 tdep->xcr0 = X86_XSTATE_AVX_AVX512_MASK;
8244 /* It may have been set by OSABI initialization function. */
8245 if (tdep->k0_regnum < 0)
8247 tdep->k_register_names = i386_k_names;
8248 tdep->k0_regnum = I386_K0_REGNUM;
8251 for (i = 0; i < I387_NUM_K_REGS; i++)
8252 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8253 tdep->k0_regnum + i,
8256 if (tdep->num_zmm_regs == 0)
8258 tdep->zmmh_register_names = i386_zmmh_names;
8259 tdep->num_zmm_regs = 8;
8260 tdep->zmm0h_regnum = I386_ZMM0H_REGNUM;
8263 for (i = 0; i < tdep->num_zmm_regs; i++)
8264 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8265 tdep->zmm0h_regnum + i,
8266 tdep->zmmh_register_names[i]);
8268 for (i = 0; i < tdep->num_xmm_avx512_regs; i++)
8269 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8270 tdep->xmm16_regnum + i,
8271 tdep->xmm_avx512_register_names[i]);
8273 for (i = 0; i < tdep->num_ymm_avx512_regs; i++)
8274 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8275 tdep->ymm16h_regnum + i,
8276 tdep->ymm16h_register_names[i]);
8280 /* AVX register description requires SSE register description. */
8284 if (!feature_avx512)
8285 tdep->xcr0 = X86_XSTATE_AVX_MASK;
8287 /* It may have been set by OSABI initialization function. */
8288 if (tdep->num_ymm_regs == 0)
8290 tdep->ymmh_register_names = i386_ymmh_names;
8291 tdep->num_ymm_regs = 8;
8292 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
8295 for (i = 0; i < tdep->num_ymm_regs; i++)
8296 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
8297 tdep->ymm0h_regnum + i,
8298 tdep->ymmh_register_names[i]);
8300 else if (feature_sse)
8301 tdep->xcr0 = X86_XSTATE_SSE_MASK;
8304 tdep->xcr0 = X86_XSTATE_X87_MASK;
8305 tdep->num_xmm_regs = 0;
8308 num_regs = tdep->num_core_regs;
8309 for (i = 0; i < num_regs; i++)
8310 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
8311 tdep->register_names[i]);
8315 /* Need to include %mxcsr, so add one. */
8316 num_regs += tdep->num_xmm_regs + 1;
8317 for (; i < num_regs; i++)
8318 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
8319 tdep->register_names[i]);
8324 tdep->xcr0 |= X86_XSTATE_MPX_MASK;
8326 if (tdep->bnd0r_regnum < 0)
8328 tdep->mpx_register_names = i386_mpx_names;
8329 tdep->bnd0r_regnum = I386_BND0R_REGNUM;
8330 tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM;
8333 for (i = 0; i < I387_NUM_MPX_REGS; i++)
8334 valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data,
8335 I387_BND0R_REGNUM (tdep) + i,
8336 tdep->mpx_register_names[i]);
8341 tdep->xcr0 |= X86_XSTATE_PKRU;
8342 if (tdep->pkru_regnum < 0)
8344 tdep->pkeys_register_names = i386_pkeys_names;
8345 tdep->pkru_regnum = I386_PKRU_REGNUM;
8346 tdep->num_pkeys_regs = 1;
8349 for (i = 0; i < I387_NUM_PKEYS_REGS; i++)
8350 valid_p &= tdesc_numbered_register (feature_pkeys, tdesc_data,
8351 I387_PKRU_REGNUM (tdep) + i,
8352 tdep->pkeys_register_names[i]);
8360 /* Implement the type_align gdbarch function. */
8363 i386_type_align (struct gdbarch *gdbarch, struct type *type)
8365 type = check_typedef (type);
8367 if (gdbarch_ptr_bit (gdbarch) == 32)
8369 if ((TYPE_CODE (type) == TYPE_CODE_INT
8370 || TYPE_CODE (type) == TYPE_CODE_FLT)
8371 && TYPE_LENGTH (type) > 4)
8374 /* Handle x86's funny long double. */
8375 if (TYPE_CODE (type) == TYPE_CODE_FLT
8376 && gdbarch_long_double_bit (gdbarch) == TYPE_LENGTH (type) * 8)
8380 return TYPE_LENGTH (type);
8384 /* Note: This is called for both i386 and amd64. */
8386 static struct gdbarch *
8387 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8389 struct gdbarch_tdep *tdep;
8390 struct gdbarch *gdbarch;
8391 struct tdesc_arch_data *tdesc_data;
8392 const struct target_desc *tdesc;
8398 /* If there is already a candidate, use it. */
8399 arches = gdbarch_list_lookup_by_info (arches, &info);
8401 return arches->gdbarch;
8403 /* Allocate space for the new architecture. Assume i386 for now. */
8404 tdep = XCNEW (struct gdbarch_tdep);
8405 gdbarch = gdbarch_alloc (&info, tdep);
8407 /* General-purpose registers. */
8408 tdep->gregset_reg_offset = NULL;
8409 tdep->gregset_num_regs = I386_NUM_GREGS;
8410 tdep->sizeof_gregset = 0;
8412 /* Floating-point registers. */
8413 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
8414 tdep->fpregset = &i386_fpregset;
8416 /* The default settings include the FPU registers, the MMX registers
8417 and the SSE registers. This can be overridden for a specific ABI
8418 by adjusting the members `st0_regnum', `mm0_regnum' and
8419 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8420 will show up in the output of "info all-registers". */
8422 tdep->st0_regnum = I386_ST0_REGNUM;
8424 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8425 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
8427 tdep->jb_pc_offset = -1;
8428 tdep->struct_return = pcc_struct_return;
8429 tdep->sigtramp_start = 0;
8430 tdep->sigtramp_end = 0;
8431 tdep->sigtramp_p = i386_sigtramp_p;
8432 tdep->sigcontext_addr = NULL;
8433 tdep->sc_reg_offset = NULL;
8434 tdep->sc_pc_offset = -1;
8435 tdep->sc_sp_offset = -1;
8437 tdep->xsave_xcr0_offset = -1;
8439 tdep->record_regmap = i386_record_regmap;
8441 set_gdbarch_type_align (gdbarch, i386_type_align);
8443 /* The format used for `long double' on almost all i386 targets is
8444 the i387 extended floating-point format. In fact, of all targets
8445 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8446 on having a `long double' that's not `long' at all. */
8447 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
8449 /* Although the i387 extended floating-point has only 80 significant
8450 bits, a `long double' actually takes up 96, probably to enforce
8452 set_gdbarch_long_double_bit (gdbarch, 96);
8454 /* Support for floating-point data type variants. */
8455 set_gdbarch_floatformat_for_type (gdbarch, i386_floatformat_for_type);
8457 /* Register numbers of various important registers. */
8458 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
8459 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
8460 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
8461 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
8463 /* NOTE: kettenis/20040418: GCC does have two possible register
8464 numbering schemes on the i386: dbx and SVR4. These schemes
8465 differ in how they number %ebp, %esp, %eflags, and the
8466 floating-point registers, and are implemented by the arrays
8467 dbx_register_map[] and svr4_dbx_register_map in
8468 gcc/config/i386.c. GCC also defines a third numbering scheme in
8469 gcc/config/i386.c, which it designates as the "default" register
8470 map used in 64bit mode. This last register numbering scheme is
8471 implemented in dbx64_register_map, and is used for AMD64; see
8474 Currently, each GCC i386 target always uses the same register
8475 numbering scheme across all its supported debugging formats
8476 i.e. SDB (COFF), stabs and DWARF 2. This is because
8477 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8478 DBX_REGISTER_NUMBER macro which is defined by each target's
8479 respective config header in a manner independent of the requested
8480 output debugging format.
8482 This does not match the arrangement below, which presumes that
8483 the SDB and stabs numbering schemes differ from the DWARF and
8484 DWARF 2 ones. The reason for this arrangement is that it is
8485 likely to get the numbering scheme for the target's
8486 default/native debug format right. For targets where GCC is the
8487 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8488 targets where the native toolchain uses a different numbering
8489 scheme for a particular debug format (stabs-in-ELF on Solaris)
8490 the defaults below will have to be overridden, like
8491 i386_elf_init_abi() does. */
8493 /* Use the dbx register numbering scheme for stabs and COFF. */
8494 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8495 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8497 /* Use the SVR4 register numbering scheme for DWARF 2. */
8498 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_dwarf_reg_to_regnum);
8500 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8501 be in use on any of the supported i386 targets. */
8503 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
8505 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
8507 /* Call dummy code. */
8508 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
8509 set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code);
8510 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
8511 set_gdbarch_frame_align (gdbarch, i386_frame_align);
8513 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
8514 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
8515 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
8517 set_gdbarch_return_value (gdbarch, i386_return_value);
8519 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
8521 /* Stack grows downward. */
8522 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8524 set_gdbarch_breakpoint_kind_from_pc (gdbarch, i386_breakpoint::kind_from_pc);
8525 set_gdbarch_sw_breakpoint_from_kind (gdbarch, i386_breakpoint::bp_from_kind);
8527 set_gdbarch_decr_pc_after_break (gdbarch, 1);
8528 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
8530 set_gdbarch_frame_args_skip (gdbarch, 8);
8532 set_gdbarch_print_insn (gdbarch, i386_print_insn);
8534 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
8536 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
8538 /* Add the i386 register groups. */
8539 i386_add_reggroups (gdbarch);
8540 tdep->register_reggroup_p = i386_register_reggroup_p;
8542 /* Helper for function argument information. */
8543 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
8545 /* Hook the function epilogue frame unwinder. This unwinder is
8546 appended to the list first, so that it supercedes the DWARF
8547 unwinder in function epilogues (where the DWARF unwinder
8548 currently fails). */
8549 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
8551 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8552 to the list before the prologue-based unwinders, so that DWARF
8553 CFI info will be used if it is available. */
8554 dwarf2_append_unwinders (gdbarch);
8556 frame_base_set_default (gdbarch, &i386_frame_base);
8558 /* Pseudo registers may be changed by amd64_init_abi. */
8559 set_gdbarch_pseudo_register_read_value (gdbarch,
8560 i386_pseudo_register_read_value);
8561 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
8562 set_gdbarch_ax_pseudo_register_collect (gdbarch,
8563 i386_ax_pseudo_register_collect);
8565 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
8566 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
8568 /* Override the normal target description method to make the AVX
8569 upper halves anonymous. */
8570 set_gdbarch_register_name (gdbarch, i386_register_name);
8572 /* Even though the default ABI only includes general-purpose registers,
8573 floating-point registers and the SSE registers, we have to leave a
8574 gap for the upper AVX, MPX and AVX512 registers. */
8575 set_gdbarch_num_regs (gdbarch, I386_PKEYS_NUM_REGS);
8577 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
8579 /* Get the x86 target description from INFO. */
8580 tdesc = info.target_desc;
8581 if (! tdesc_has_registers (tdesc))
8582 tdesc = i386_target_description (X86_XSTATE_SSE_MASK);
8583 tdep->tdesc = tdesc;
8585 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
8586 tdep->register_names = i386_register_names;
8588 /* No upper YMM registers. */
8589 tdep->ymmh_register_names = NULL;
8590 tdep->ymm0h_regnum = -1;
8592 /* No upper ZMM registers. */
8593 tdep->zmmh_register_names = NULL;
8594 tdep->zmm0h_regnum = -1;
8596 /* No high XMM registers. */
8597 tdep->xmm_avx512_register_names = NULL;
8598 tdep->xmm16_regnum = -1;
8600 /* No upper YMM16-31 registers. */
8601 tdep->ymm16h_register_names = NULL;
8602 tdep->ymm16h_regnum = -1;
8604 tdep->num_byte_regs = 8;
8605 tdep->num_word_regs = 8;
8606 tdep->num_dword_regs = 0;
8607 tdep->num_mmx_regs = 8;
8608 tdep->num_ymm_regs = 0;
8610 /* No MPX registers. */
8611 tdep->bnd0r_regnum = -1;
8612 tdep->bndcfgu_regnum = -1;
8614 /* No AVX512 registers. */
8615 tdep->k0_regnum = -1;
8616 tdep->num_zmm_regs = 0;
8617 tdep->num_ymm_avx512_regs = 0;
8618 tdep->num_xmm_avx512_regs = 0;
8620 /* No PKEYS registers */
8621 tdep->pkru_regnum = -1;
8622 tdep->num_pkeys_regs = 0;
8624 tdesc_data = tdesc_data_alloc ();
8626 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
8628 set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address);
8630 set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call);
8631 set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret);
8632 set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump);
8634 /* Hook in ABI-specific overrides, if they have been registered.
8635 Note: If INFO specifies a 64 bit arch, this is where we turn
8636 a 32-bit i386 into a 64-bit amd64. */
8637 info.tdesc_data = tdesc_data;
8638 gdbarch_init_osabi (info, gdbarch);
8640 if (!i386_validate_tdesc_p (tdep, tdesc_data))
8642 tdesc_data_cleanup (tdesc_data);
8644 gdbarch_free (gdbarch);
8648 num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0);
8650 /* Wire in pseudo registers. Number of pseudo registers may be
8652 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
8653 + tdep->num_word_regs
8654 + tdep->num_dword_regs
8655 + tdep->num_mmx_regs
8656 + tdep->num_ymm_regs
8658 + tdep->num_ymm_avx512_regs
8659 + tdep->num_zmm_regs));
8661 /* Target description may be changed. */
8662 tdesc = tdep->tdesc;
8664 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
8666 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8667 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
8669 /* Make %al the first pseudo-register. */
8670 tdep->al_regnum = gdbarch_num_regs (gdbarch);
8671 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
8673 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
8674 if (tdep->num_dword_regs)
8676 /* Support dword pseudo-register if it hasn't been disabled. */
8677 tdep->eax_regnum = ymm0_regnum;
8678 ymm0_regnum += tdep->num_dword_regs;
8681 tdep->eax_regnum = -1;
8683 mm0_regnum = ymm0_regnum;
8684 if (tdep->num_ymm_regs)
8686 /* Support YMM pseudo-register if it is available. */
8687 tdep->ymm0_regnum = ymm0_regnum;
8688 mm0_regnum += tdep->num_ymm_regs;
8691 tdep->ymm0_regnum = -1;
8693 if (tdep->num_ymm_avx512_regs)
8695 /* Support YMM16-31 pseudo registers if available. */
8696 tdep->ymm16_regnum = mm0_regnum;
8697 mm0_regnum += tdep->num_ymm_avx512_regs;
8700 tdep->ymm16_regnum = -1;
8702 if (tdep->num_zmm_regs)
8704 /* Support ZMM pseudo-register if it is available. */
8705 tdep->zmm0_regnum = mm0_regnum;
8706 mm0_regnum += tdep->num_zmm_regs;
8709 tdep->zmm0_regnum = -1;
8711 bnd0_regnum = mm0_regnum;
8712 if (tdep->num_mmx_regs != 0)
8714 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8715 tdep->mm0_regnum = mm0_regnum;
8716 bnd0_regnum += tdep->num_mmx_regs;
8719 tdep->mm0_regnum = -1;
8721 if (tdep->bnd0r_regnum > 0)
8722 tdep->bnd0_regnum = bnd0_regnum;
8724 tdep-> bnd0_regnum = -1;
8726 /* Hook in the legacy prologue-based unwinders last (fallback). */
8727 frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind);
8728 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
8729 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
8731 /* If we have a register mapping, enable the generic core file
8732 support, unless it has already been enabled. */
8733 if (tdep->gregset_reg_offset
8734 && !gdbarch_iterate_over_regset_sections_p (gdbarch))
8735 set_gdbarch_iterate_over_regset_sections
8736 (gdbarch, i386_iterate_over_regset_sections);
8738 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
8739 i386_fast_tracepoint_valid_at);
8746 /* Return the target description for a specified XSAVE feature mask. */
8748 const struct target_desc *
8749 i386_target_description (uint64_t xcr0)
8751 static target_desc *i386_tdescs \
8752 [2/*SSE*/][2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/] = {};
8753 target_desc **tdesc;
8755 tdesc = &i386_tdescs[(xcr0 & X86_XSTATE_SSE) ? 1 : 0]
8756 [(xcr0 & X86_XSTATE_AVX) ? 1 : 0]
8757 [(xcr0 & X86_XSTATE_MPX) ? 1 : 0]
8758 [(xcr0 & X86_XSTATE_AVX512) ? 1 : 0]
8759 [(xcr0 & X86_XSTATE_PKRU) ? 1 : 0];
8762 *tdesc = i386_create_target_description (xcr0, false);
8767 #define MPX_BASE_MASK (~(ULONGEST) 0xfff)
8769 /* Find the bound directory base address. */
8771 static unsigned long
8772 i386_mpx_bd_base (void)
8774 struct regcache *rcache;
8775 struct gdbarch_tdep *tdep;
8777 enum register_status regstatus;
8779 rcache = get_current_regcache ();
8780 tdep = gdbarch_tdep (rcache->arch ());
8782 regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret);
8784 if (regstatus != REG_VALID)
8785 error (_("BNDCFGU register invalid, read status %d."), regstatus);
8787 return ret & MPX_BASE_MASK;
8791 i386_mpx_enabled (void)
8793 const struct gdbarch_tdep *tdep = gdbarch_tdep (get_current_arch ());
8794 const struct target_desc *tdesc = tdep->tdesc;
8796 return (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL);
8799 #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */
8800 #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */
8801 #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */
8802 #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */
8804 /* Find the bound table entry given the pointer location and the base
8805 address of the table. */
8808 i386_mpx_get_bt_entry (CORE_ADDR ptr, CORE_ADDR bd_base)
8812 CORE_ADDR mpx_bd_mask, bd_ptr_r_shift, bd_ptr_l_shift;
8813 CORE_ADDR bt_mask, bt_select_r_shift, bt_select_l_shift;
8814 CORE_ADDR bd_entry_addr;
8817 struct gdbarch *gdbarch = get_current_arch ();
8818 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8821 if (gdbarch_ptr_bit (gdbarch) == 64)
8823 mpx_bd_mask = (CORE_ADDR) MPX_BD_MASK;
8824 bd_ptr_r_shift = 20;
8826 bt_select_r_shift = 3;
8827 bt_select_l_shift = 5;
8828 bt_mask = (CORE_ADDR) MPX_BT_MASK;
8830 if ( sizeof (CORE_ADDR) == 4)
8831 error (_("bound table examination not supported\
8832 for 64-bit process with 32-bit GDB"));
8836 mpx_bd_mask = MPX_BD_MASK_32;
8837 bd_ptr_r_shift = 12;
8839 bt_select_r_shift = 2;
8840 bt_select_l_shift = 4;
8841 bt_mask = MPX_BT_MASK_32;
8844 offset1 = ((ptr & mpx_bd_mask) >> bd_ptr_r_shift) << bd_ptr_l_shift;
8845 bd_entry_addr = bd_base + offset1;
8846 bd_entry = read_memory_typed_address (bd_entry_addr, data_ptr_type);
8848 if ((bd_entry & 0x1) == 0)
8849 error (_("Invalid bounds directory entry at %s."),
8850 paddress (get_current_arch (), bd_entry_addr));
8852 /* Clearing status bit. */
8854 bt_addr = bd_entry & ~bt_select_r_shift;
8855 offset2 = ((ptr & bt_mask) >> bt_select_r_shift) << bt_select_l_shift;
8857 return bt_addr + offset2;
8860 /* Print routine for the mpx bounds. */
8863 i386_mpx_print_bounds (const CORE_ADDR bt_entry[4])
8865 struct ui_out *uiout = current_uiout;
8867 struct gdbarch *gdbarch = get_current_arch ();
8868 CORE_ADDR onecompl = ~((CORE_ADDR) 0);
8869 int bounds_in_map = ((~bt_entry[1] == 0 && bt_entry[0] == onecompl) ? 1 : 0);
8871 if (bounds_in_map == 1)
8873 uiout->text ("Null bounds on map:");
8874 uiout->text (" pointer value = ");
8875 uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]);
8881 uiout->text ("{lbound = ");
8882 uiout->field_core_addr ("lower-bound", gdbarch, bt_entry[0]);
8883 uiout->text (", ubound = ");
8885 /* The upper bound is stored in 1's complement. */
8886 uiout->field_core_addr ("upper-bound", gdbarch, ~bt_entry[1]);
8887 uiout->text ("}: pointer value = ");
8888 uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]);
8890 if (gdbarch_ptr_bit (gdbarch) == 64)
8891 size = ( (~(int64_t) bt_entry[1]) - (int64_t) bt_entry[0]);
8893 size = ( ~((int32_t) bt_entry[1]) - (int32_t) bt_entry[0]);
8895 /* In case the bounds are 0x0 and 0xffff... the difference will be -1.
8896 -1 represents in this sense full memory access, and there is no need
8899 size = (size > -1 ? size + 1 : size);
8900 uiout->text (", size = ");
8901 uiout->field_fmt ("size", "%s", plongest (size));
8903 uiout->text (", metadata = ");
8904 uiout->field_core_addr ("metadata", gdbarch, bt_entry[3]);
8909 /* Implement the command "show mpx bound". */
8912 i386_mpx_info_bounds (const char *args, int from_tty)
8914 CORE_ADDR bd_base = 0;
8916 CORE_ADDR bt_entry_addr = 0;
8917 CORE_ADDR bt_entry[4];
8919 struct gdbarch *gdbarch = get_current_arch ();
8920 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8922 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386
8923 || !i386_mpx_enabled ())
8925 printf_unfiltered (_("Intel Memory Protection Extensions not "
8926 "supported on this target.\n"));
8932 printf_unfiltered (_("Address of pointer variable expected.\n"));
8936 addr = parse_and_eval_address (args);
8938 bd_base = i386_mpx_bd_base ();
8939 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8941 memset (bt_entry, 0, sizeof (bt_entry));
8943 for (i = 0; i < 4; i++)
8944 bt_entry[i] = read_memory_typed_address (bt_entry_addr
8945 + i * TYPE_LENGTH (data_ptr_type),
8948 i386_mpx_print_bounds (bt_entry);
8951 /* Implement the command "set mpx bound". */
8954 i386_mpx_set_bounds (const char *args, int from_tty)
8956 CORE_ADDR bd_base = 0;
8957 CORE_ADDR addr, lower, upper;
8958 CORE_ADDR bt_entry_addr = 0;
8959 CORE_ADDR bt_entry[2];
8960 const char *input = args;
8962 struct gdbarch *gdbarch = get_current_arch ();
8963 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8964 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8966 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386
8967 || !i386_mpx_enabled ())
8968 error (_("Intel Memory Protection Extensions not supported\
8972 error (_("Pointer value expected."));
8974 addr = value_as_address (parse_to_comma_and_eval (&input));
8976 if (input[0] == ',')
8978 if (input[0] == '\0')
8979 error (_("wrong number of arguments: missing lower and upper bound."));
8980 lower = value_as_address (parse_to_comma_and_eval (&input));
8982 if (input[0] == ',')
8984 if (input[0] == '\0')
8985 error (_("Wrong number of arguments; Missing upper bound."));
8986 upper = value_as_address (parse_to_comma_and_eval (&input));
8988 bd_base = i386_mpx_bd_base ();
8989 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8990 for (i = 0; i < 2; i++)
8991 bt_entry[i] = read_memory_typed_address (bt_entry_addr
8992 + i * TYPE_LENGTH (data_ptr_type),
8994 bt_entry[0] = (uint64_t) lower;
8995 bt_entry[1] = ~(uint64_t) upper;
8997 for (i = 0; i < 2; i++)
8998 write_memory_unsigned_integer (bt_entry_addr
8999 + i * TYPE_LENGTH (data_ptr_type),
9000 TYPE_LENGTH (data_ptr_type), byte_order,
9004 static struct cmd_list_element *mpx_set_cmdlist, *mpx_show_cmdlist;
9006 /* Helper function for the CLI commands. */
9009 set_mpx_cmd (const char *args, int from_tty)
9011 help_list (mpx_set_cmdlist, "set mpx ", all_commands, gdb_stdout);
9014 /* Helper function for the CLI commands. */
9017 show_mpx_cmd (const char *args, int from_tty)
9019 cmd_show_list (mpx_show_cmdlist, from_tty, "");
9023 _initialize_i386_tdep (void)
9025 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
9027 /* Add the variable that controls the disassembly flavor. */
9028 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
9029 &disassembly_flavor, _("\
9030 Set the disassembly flavor."), _("\
9031 Show the disassembly flavor."), _("\
9032 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
9034 NULL, /* FIXME: i18n: */
9035 &setlist, &showlist);
9037 /* Add the variable that controls the convention for returning
9039 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
9040 &struct_convention, _("\
9041 Set the convention for returning small structs."), _("\
9042 Show the convention for returning small structs."), _("\
9043 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
9046 NULL, /* FIXME: i18n: */
9047 &setlist, &showlist);
9049 /* Add "mpx" prefix for the set commands. */
9051 add_prefix_cmd ("mpx", class_support, set_mpx_cmd, _("\
9052 Set Intel Memory Protection Extensions specific variables."),
9053 &mpx_set_cmdlist, "set mpx ",
9054 0 /* allow-unknown */, &setlist);
9056 /* Add "mpx" prefix for the show commands. */
9058 add_prefix_cmd ("mpx", class_support, show_mpx_cmd, _("\
9059 Show Intel Memory Protection Extensions specific variables."),
9060 &mpx_show_cmdlist, "show mpx ",
9061 0 /* allow-unknown */, &showlist);
9063 /* Add "bound" command for the show mpx commands list. */
9065 add_cmd ("bound", no_class, i386_mpx_info_bounds,
9066 "Show the memory bounds for a given array/pointer storage\
9067 in the bound table.",
9070 /* Add "bound" command for the set mpx commands list. */
9072 add_cmd ("bound", no_class, i386_mpx_set_bounds,
9073 "Set the memory bounds for a given array/pointer storage\
9074 in the bound table.",
9077 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
9078 i386_svr4_init_abi);
9080 /* Initialize the i386-specific register groups. */
9081 i386_init_reggroups ();
9083 /* Tell remote stub that we support XML target description. */
9084 register_remote_support_xml ("i386");
9092 { "i386/i386.xml", X86_XSTATE_SSE_MASK },
9093 { "i386/i386-mmx.xml", X86_XSTATE_X87_MASK },
9094 { "i386/i386-avx.xml", X86_XSTATE_AVX_MASK },
9095 { "i386/i386-mpx.xml", X86_XSTATE_MPX_MASK },
9096 { "i386/i386-avx-mpx.xml", X86_XSTATE_AVX_MPX_MASK },
9097 { "i386/i386-avx-avx512.xml", X86_XSTATE_AVX_AVX512_MASK },
9098 { "i386/i386-avx-mpx-avx512-pku.xml",
9099 X86_XSTATE_AVX_MPX_AVX512_PKU_MASK },
9102 for (auto &a : xml_masks)
9104 auto tdesc = i386_target_description (a.mask);
9106 selftests::record_xml_tdesc (a.xml, tdesc);
9108 #endif /* GDB_SELF_TEST */