1 /* Native-dependent code for the i386.
3 Copyright (C) 2001, 2004-2005, 2007-2012 Free Software Foundation,
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "breakpoint.h"
27 #include "gdb_assert.h"
30 /* Support for hardware watchpoints and breakpoints using the i386
33 This provides several functions for inserting and removing
34 hardware-assisted breakpoints and watchpoints, testing if one or
35 more of the watchpoints triggered and at what address, checking
36 whether a given region can be watched, etc.
38 The functions below implement debug registers sharing by reference
39 counts, and allow to watch regions up to 16 bytes long. */
41 struct i386_dr_low_type i386_dr_low;
44 /* Support for 8-byte wide hw watchpoints. */
45 #define TARGET_HAS_DR_LEN_8 (i386_dr_low.debug_register_length == 8)
47 /* DR7 Debug Control register fields. */
49 /* How many bits to skip in DR7 to get to R/W and LEN fields. */
50 #define DR_CONTROL_SHIFT 16
51 /* How many bits in DR7 per R/W and LEN field for each watchpoint. */
52 #define DR_CONTROL_SIZE 4
54 /* Watchpoint/breakpoint read/write fields in DR7. */
55 #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */
56 #define DR_RW_WRITE (0x1) /* Break on data writes. */
57 #define DR_RW_READ (0x3) /* Break on data reads or writes. */
59 /* This is here for completeness. No platform supports this
60 functionality yet (as of March 2001). Note that the DE flag in the
61 CR4 register needs to be set to support this. */
63 #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */
66 /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift
67 is so we could OR this with the read/write field defined above. */
68 #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */
69 #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */
70 #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */
71 #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */
73 /* Local and Global Enable flags in DR7.
75 When the Local Enable flag is set, the breakpoint/watchpoint is
76 enabled only for the current task; the processor automatically
77 clears this flag on every task switch. When the Global Enable flag
78 is set, the breakpoint/watchpoint is enabled for all tasks; the
79 processor never clears this flag.
81 Currently, all watchpoint are locally enabled. If you need to
82 enable them globally, read the comment which pertains to this in
83 i386_insert_aligned_watchpoint below. */
84 #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */
85 #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */
86 #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */
88 /* Local and global exact breakpoint enable flags (a.k.a. slowdown
89 flags). These are only required on i386, to allow detection of the
90 exact instruction which caused a watchpoint to break; i486 and
91 later processors do that automatically. We set these flags for
92 backwards compatibility. */
93 #define DR_LOCAL_SLOWDOWN (0x100)
94 #define DR_GLOBAL_SLOWDOWN (0x200)
96 /* Fields reserved by Intel. This includes the GD (General Detect
97 Enable) flag, which causes a debug exception to be generated when a
98 MOV instruction accesses one of the debug registers.
100 FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */
101 #define DR_CONTROL_RESERVED (0xFC00)
103 /* Auxiliary helper macros. */
105 /* A value that masks all fields in DR7 that are reserved by Intel. */
106 #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED)
108 /* The I'th debug register is vacant if its Local and Global Enable
109 bits are reset in the Debug Control register. */
110 #define I386_DR_VACANT(state, i) \
111 (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
113 /* Locally enable the break/watchpoint in the I'th debug register. */
114 #define I386_DR_LOCAL_ENABLE(state, i) \
116 (state)->dr_control_mirror |= \
117 (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
120 /* Globally enable the break/watchpoint in the I'th debug register. */
121 #define I386_DR_GLOBAL_ENABLE(state, i) \
123 (state)->dr_control_mirror |= \
124 (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
127 /* Disable the break/watchpoint in the I'th debug register. */
128 #define I386_DR_DISABLE(state, i) \
130 (state)->dr_control_mirror &= \
131 ~(3 << (DR_ENABLE_SIZE * (i))); \
134 /* Set in DR7 the RW and LEN fields for the I'th debug register. */
135 #define I386_DR_SET_RW_LEN(state, i, rwlen) \
137 (state)->dr_control_mirror &= \
138 ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
139 (state)->dr_control_mirror |= \
140 ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
143 /* Get from DR7 the RW and LEN fields for the I'th debug register. */
144 #define I386_DR_GET_RW_LEN(dr7, i) \
146 >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
148 /* Mask that this I'th watchpoint has triggered. */
149 #define I386_DR_WATCH_MASK(i) (1 << (i))
151 /* Did the watchpoint whose address is in the I'th register break? */
152 #define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i)))
154 /* A macro to loop over all debug registers. */
155 #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++)
157 /* Clear the reference counts and forget everything we knew about the
161 i386_init_dregs (struct i386_debug_reg_state *state)
165 ALL_DEBUG_REGISTERS (i)
167 state->dr_mirror[i] = 0;
168 state->dr_ref_count[i] = 0;
170 state->dr_control_mirror = 0;
171 state->dr_status_mirror = 0;
174 /* Per-inferior data key. */
175 static const struct inferior_data *i386_inferior_data;
177 /* Per-inferior data. */
178 struct i386_inferior_data
180 /* Copy of i386 hardware debug registers for performance reasons. */
181 struct i386_debug_reg_state state;
184 /* Get data specific for INFERIOR_PTID LWP. Return special data area
185 for processes being detached. */
187 static struct i386_inferior_data *
188 i386_inferior_data_get (void)
190 /* Intermediate patch stub. */
191 static struct i386_inferior_data inf_data_local;
192 struct inferior *inf = current_inferior ();
193 struct i386_inferior_data *inf_data = &inf_data_local;
195 if (inf->pid != ptid_get_pid (inferior_ptid))
197 /* INFERIOR_PTID is being detached from the inferior INF.
198 Provide local cache specific for the detached LWP. */
200 static struct i386_inferior_data detached_inf_data_local;
201 static int detached_inf_pid = -1;
203 if (detached_inf_pid != ptid_get_pid (inferior_ptid))
205 /* Reinitialize the local cache if INFERIOR_PTID is
206 different from the LWP last detached.
208 Linux kernel before 2.6.33 commit
209 72f674d203cd230426437cdcf7dd6f681dad8b0d
210 will inherit hardware debug registers from parent
211 on fork/vfork/clone. Newer Linux kernels create such tasks with
212 zeroed debug registers.
214 GDB will remove all breakpoints (and watchpoints) from the forked
215 off process. We also need to reset the debug registers in that
216 process to be compatible with the older Linux kernels.
218 Copy the debug registers mirrors into the new process so that all
219 breakpoints and watchpoints can be removed together. The debug
220 registers mirror will become zeroed in the end before detaching
221 the forked off process. */
223 detached_inf_pid = ptid_get_pid (inferior_ptid);
224 detached_inf_data_local = *inf_data;
227 return &detached_inf_data_local;
233 /* Get debug registers state for INFERIOR_PTID, see
234 i386_inferior_data_get. */
236 struct i386_debug_reg_state *
237 i386_debug_reg_state (void)
239 return &i386_inferior_data_get ()->state;
242 /* Whether or not to print the mirrored debug registers. */
243 static int maint_show_dr;
245 /* Types of operations supported by i386_handle_nonaligned_watchpoint. */
246 typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t;
248 /* Internal functions. */
250 /* Return the value of a 4-bit field for DR7 suitable for watching a
251 region of LEN bytes for accesses of type TYPE. LEN is assumed to
252 have the value of 1, 2, or 4. */
253 static unsigned i386_length_and_rw_bits (int len, enum target_hw_bp_type type);
255 /* Insert a watchpoint at address ADDR, which is assumed to be aligned
256 according to the length of the region to watch. LEN_RW_BITS is the
257 value of the bit-field from DR7 which describes the length and
258 access type of the region to be watched by this watchpoint. Return
259 0 on success, -1 on failure. */
260 static int i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state,
262 unsigned len_rw_bits);
264 /* Remove a watchpoint at address ADDR, which is assumed to be aligned
265 according to the length of the region to watch. LEN_RW_BITS is the
266 value of the bits from DR7 which describes the length and access
267 type of the region watched by this watchpoint. Return 0 on
268 success, -1 on failure. */
269 static int i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state,
271 unsigned len_rw_bits);
273 /* Insert or remove a (possibly non-aligned) watchpoint, or count the
274 number of debug registers required to watch a region at address
275 ADDR whose length is LEN for accesses of type TYPE. Return 0 on
276 successful insertion or removal, a positive number when queried
277 about the number of registers, or -1 on failure. If WHAT is not a
278 valid value, bombs through internal_error. */
279 static int i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state,
281 CORE_ADDR addr, int len,
282 enum target_hw_bp_type type);
284 /* Implementation. */
286 /* Clear the reference counts and forget everything we knew about the
290 i386_cleanup_dregs (void)
292 struct i386_debug_reg_state *state = i386_debug_reg_state ();
294 i386_init_dregs (state);
297 /* Print the values of the mirrored debug registers. This is called
298 when maint_show_dr is non-zero. To set that up, type "maint
299 show-debug-regs" at GDB's prompt. */
302 i386_show_dr (struct i386_debug_reg_state *state,
303 const char *func, CORE_ADDR addr,
304 int len, enum target_hw_bp_type type)
306 int addr_size = gdbarch_addr_bit (target_gdbarch) / 8;
309 puts_unfiltered (func);
311 printf_unfiltered (" (addr=%lx, len=%d, type=%s)",
312 /* This code is for ia32, so casting CORE_ADDR
313 to unsigned long should be okay. */
314 (unsigned long)addr, len,
315 type == hw_write ? "data-write"
316 : (type == hw_read ? "data-read"
317 : (type == hw_access ? "data-read/write"
318 : (type == hw_execute ? "instruction-execute"
319 /* FIXME: if/when I/O read/write
320 watchpoints are supported, add them
323 puts_unfiltered (":\n");
324 printf_unfiltered ("\tCONTROL (DR7): %s STATUS (DR6): %s\n",
325 phex (state->dr_control_mirror, 8),
326 phex (state->dr_status_mirror, 8));
327 ALL_DEBUG_REGISTERS(i)
329 printf_unfiltered ("\
330 \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n",
331 i, phex (state->dr_mirror[i], addr_size),
332 state->dr_ref_count[i],
333 i + 1, phex (state->dr_mirror[i + 1], addr_size),
334 state->dr_ref_count[i+1]);
339 /* Return the value of a 4-bit field for DR7 suitable for watching a
340 region of LEN bytes for accesses of type TYPE. LEN is assumed to
341 have the value of 1, 2, or 4. */
344 i386_length_and_rw_bits (int len, enum target_hw_bp_type type)
357 internal_error (__FILE__, __LINE__,
358 _("The i386 doesn't support "
359 "data-read watchpoints.\n"));
364 /* Not yet supported. */
370 internal_error (__FILE__, __LINE__, _("\
371 Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n"),
378 return (DR_LEN_1 | rw);
380 return (DR_LEN_2 | rw);
382 return (DR_LEN_4 | rw);
384 if (TARGET_HAS_DR_LEN_8)
385 return (DR_LEN_8 | rw);
386 /* ELSE FALL THROUGH */
388 internal_error (__FILE__, __LINE__, _("\
389 Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n"), len);
393 /* Insert a watchpoint at address ADDR, which is assumed to be aligned
394 according to the length of the region to watch. LEN_RW_BITS is the
395 value of the bits from DR7 which describes the length and access
396 type of the region to be watched by this watchpoint. Return 0 on
397 success, -1 on failure. */
400 i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state,
401 CORE_ADDR addr, unsigned len_rw_bits)
405 if (!i386_dr_low.set_addr || !i386_dr_low.set_control)
408 /* First, look for an occupied debug register with the same address
409 and the same RW and LEN definitions. If we find one, we can
410 reuse it for this watchpoint as well (and save a register). */
411 ALL_DEBUG_REGISTERS(i)
413 if (!I386_DR_VACANT (state, i)
414 && state->dr_mirror[i] == addr
415 && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits)
417 state->dr_ref_count[i]++;
422 /* Next, look for a vacant debug register. */
423 ALL_DEBUG_REGISTERS(i)
425 if (I386_DR_VACANT (state, i))
429 /* No more debug registers! */
433 /* Now set up the register I to watch our region. */
435 /* Record the info in our local mirrored array. */
436 state->dr_mirror[i] = addr;
437 state->dr_ref_count[i] = 1;
438 I386_DR_SET_RW_LEN (state, i, len_rw_bits);
439 /* Note: we only enable the watchpoint locally, i.e. in the current
440 task. Currently, no i386 target allows or supports global
441 watchpoints; however, if any target would want that in the
442 future, GDB should probably provide a command to control whether
443 to enable watchpoints globally or locally, and the code below
444 should use global or local enable and slow-down flags as
446 I386_DR_LOCAL_ENABLE (state, i);
447 state->dr_control_mirror |= DR_LOCAL_SLOWDOWN;
448 state->dr_control_mirror &= I386_DR_CONTROL_MASK;
453 /* Remove a watchpoint at address ADDR, which is assumed to be aligned
454 according to the length of the region to watch. LEN_RW_BITS is the
455 value of the bits from DR7 which describes the length and access
456 type of the region watched by this watchpoint. Return 0 on
457 success, -1 on failure. */
460 i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state,
461 CORE_ADDR addr, unsigned len_rw_bits)
465 ALL_DEBUG_REGISTERS(i)
467 if (!I386_DR_VACANT (state, i)
468 && state->dr_mirror[i] == addr
469 && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits)
471 if (--state->dr_ref_count[i] == 0) /* no longer in use? */
473 /* Reset our mirror. */
474 state->dr_mirror[i] = 0;
475 I386_DR_DISABLE (state, i);
484 /* Insert or remove a (possibly non-aligned) watchpoint, or count the
485 number of debug registers required to watch a region at address
486 ADDR whose length is LEN for accesses of type TYPE. Return 0 on
487 successful insertion or removal, a positive number when queried
488 about the number of registers, or -1 on failure. If WHAT is not a
489 valid value, bombs through internal_error. */
492 i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state,
493 i386_wp_op_t what, CORE_ADDR addr, int len,
494 enum target_hw_bp_type type)
497 int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4;
499 static int size_try_array[8][8] =
501 {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */
502 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */
503 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */
504 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */
505 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */
506 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */
507 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */
508 {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */
513 int align = addr % max_wp_len;
514 /* Four (eight on AMD64) is the maximum length a debug register
516 int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1);
517 int size = size_try_array[try][align];
519 if (what == WP_COUNT)
521 /* size_try_array[] is defined such that each iteration
522 through the loop is guaranteed to produce an address and a
523 size that can be watched with a single debug register.
524 Thus, for counting the registers required to watch a
525 region, we simply need to increment the count on each
531 unsigned len_rw = i386_length_and_rw_bits (size, type);
533 if (what == WP_INSERT)
534 retval = i386_insert_aligned_watchpoint (state, addr, len_rw);
535 else if (what == WP_REMOVE)
536 retval = i386_remove_aligned_watchpoint (state, addr, len_rw);
538 internal_error (__FILE__, __LINE__, _("\
539 Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"),
552 /* Update the inferior's debug registers with the new debug registers
553 state, in NEW_STATE, and then update our local mirror to match. */
556 i386_update_inferior_debug_regs (struct i386_debug_reg_state *new_state)
558 struct i386_debug_reg_state *state = i386_debug_reg_state ();
561 ALL_DEBUG_REGISTERS (i)
563 if (I386_DR_VACANT (new_state, i) != I386_DR_VACANT (state, i))
564 i386_dr_low.set_addr (i, new_state->dr_mirror[i]);
566 gdb_assert (new_state->dr_mirror[i] == state->dr_mirror[i]);
569 if (new_state->dr_control_mirror != state->dr_control_mirror)
570 i386_dr_low.set_control (new_state->dr_control_mirror);
575 /* Insert a watchpoint to watch a memory region which starts at
576 address ADDR and whose length is LEN bytes. Watch memory accesses
577 of the type TYPE. Return 0 on success, -1 on failure. */
580 i386_insert_watchpoint (CORE_ADDR addr, int len, int type,
581 struct expression *cond)
583 struct i386_debug_reg_state *state = i386_debug_reg_state ();
585 /* Work on a local copy of the debug registers, and on success,
586 commit the change back to the inferior. */
587 struct i386_debug_reg_state local_state = *state;
590 return 1; /* unsupported */
592 if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8))
594 retval = i386_handle_nonaligned_watchpoint (&local_state,
595 WP_INSERT, addr, len, type);
598 unsigned len_rw = i386_length_and_rw_bits (len, type);
600 retval = i386_insert_aligned_watchpoint (&local_state,
605 i386_update_inferior_debug_regs (&local_state);
608 i386_show_dr (state, "insert_watchpoint", addr, len, type);
613 /* Remove a watchpoint that watched the memory region which starts at
614 address ADDR, whose length is LEN bytes, and for accesses of the
615 type TYPE. Return 0 on success, -1 on failure. */
617 i386_remove_watchpoint (CORE_ADDR addr, int len, int type,
618 struct expression *cond)
620 struct i386_debug_reg_state *state = i386_debug_reg_state ();
622 /* Work on a local copy of the debug registers, and on success,
623 commit the change back to the inferior. */
624 struct i386_debug_reg_state local_state = *state;
626 if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8))
628 retval = i386_handle_nonaligned_watchpoint (&local_state,
629 WP_REMOVE, addr, len, type);
632 unsigned len_rw = i386_length_and_rw_bits (len, type);
634 retval = i386_remove_aligned_watchpoint (&local_state,
639 i386_update_inferior_debug_regs (&local_state);
642 i386_show_dr (state, "remove_watchpoint", addr, len, type);
647 /* Return non-zero if we can watch a memory region that starts at
648 address ADDR and whose length is LEN bytes. */
651 i386_region_ok_for_watchpoint (CORE_ADDR addr, int len)
653 struct i386_debug_reg_state *state = i386_debug_reg_state ();
656 /* Compute how many aligned watchpoints we would need to cover this
658 nregs = i386_handle_nonaligned_watchpoint (state,
659 WP_COUNT, addr, len, hw_write);
660 return nregs <= DR_NADDR ? 1 : 0;
663 /* If the inferior has some watchpoint that triggered, set the
664 address associated with that watchpoint and return non-zero.
665 Otherwise, return zero. */
668 i386_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p)
670 struct i386_debug_reg_state *state = i386_debug_reg_state ();
674 /* The current thread's DR_STATUS. We always need to read this to
675 check whether some watchpoint caused the trap. */
677 /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a
678 data breakpoint trap. Only fetch it when necessary, to avoid an
679 unnecessary extra syscall when no watchpoint triggered. */
681 unsigned control = 0;
683 /* In non-stop/async, threads can be running while we change the
684 STATE (and friends). Say, we set a watchpoint, and let threads
685 resume. Now, say you delete the watchpoint, or add/remove
686 watchpoints such that STATE changes while threads are running.
687 On targets that support non-stop, inserting/deleting watchpoints
688 updates the STATE only. It does not update the real thread's
689 debug registers; that's only done prior to resume. Instead, if
690 threads are running when the mirror changes, a temporary and
691 transparent stop on all threads is forced so they can get their
692 copy of the debug registers updated on re-resume. Now, say,
693 a thread hit a watchpoint before having been updated with the new
694 STATE contents, and we haven't yet handled the corresponding
695 SIGTRAP. If we trusted STATE below, we'd mistake the real
696 trapped address (from the last time we had updated debug
697 registers in the thread) with whatever was currently in STATE.
698 So to fix this, STATE always represents intention, what we _want_
699 threads to have in debug registers. To get at the address and
700 cause of the trap, we need to read the state the thread still has
701 in its debug registers.
703 In sum, always get the current debug register values the current
704 thread has, instead of trusting the global mirror. If the thread
705 was running when we last changed watchpoints, the mirror no
706 longer represents what was set in this thread's debug
708 status = i386_dr_low.get_status ();
710 ALL_DEBUG_REGISTERS(i)
712 if (!I386_DR_WATCH_HIT (status, i))
717 control = i386_dr_low.get_control ();
721 /* This second condition makes sure DRi is set up for a data
722 watchpoint, not a hardware breakpoint. The reason is that
723 GDB doesn't call the target_stopped_data_address method
724 except for data watchpoints. In other words, I'm being
726 if (I386_DR_GET_RW_LEN (control, i) != 0)
728 addr = i386_dr_low.get_addr (i);
731 i386_show_dr (state, "watchpoint_hit", addr, -1, hw_write);
734 if (maint_show_dr && addr == 0)
735 i386_show_dr (state, "stopped_data_addr", 0, 0, hw_write);
743 i386_stopped_by_watchpoint (void)
746 return i386_stopped_data_address (¤t_target, &addr);
749 /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address.
750 Return 0 on success, EBUSY on failure. */
752 i386_insert_hw_breakpoint (struct gdbarch *gdbarch,
753 struct bp_target_info *bp_tgt)
755 struct i386_debug_reg_state *state = i386_debug_reg_state ();
756 unsigned len_rw = i386_length_and_rw_bits (1, hw_execute);
757 CORE_ADDR addr = bp_tgt->placed_address;
758 /* Work on a local copy of the debug registers, and on success,
759 commit the change back to the inferior. */
760 struct i386_debug_reg_state local_state = *state;
761 int retval = i386_insert_aligned_watchpoint (&local_state,
762 addr, len_rw) ? EBUSY : 0;
765 i386_update_inferior_debug_regs (&local_state);
768 i386_show_dr (state, "insert_hwbp", addr, 1, hw_execute);
773 /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address.
774 Return 0 on success, -1 on failure. */
777 i386_remove_hw_breakpoint (struct gdbarch *gdbarch,
778 struct bp_target_info *bp_tgt)
780 struct i386_debug_reg_state *state = i386_debug_reg_state ();
781 unsigned len_rw = i386_length_and_rw_bits (1, hw_execute);
782 CORE_ADDR addr = bp_tgt->placed_address;
783 /* Work on a local copy of the debug registers, and on success,
784 commit the change back to the inferior. */
785 struct i386_debug_reg_state local_state = *state;
786 int retval = i386_remove_aligned_watchpoint (&local_state,
790 i386_update_inferior_debug_regs (&local_state);
793 i386_show_dr (state, "remove_hwbp", addr, 1, hw_execute);
798 /* Returns the number of hardware watchpoints of type TYPE that we can
799 set. Value is positive if we can set CNT watchpoints, zero if
800 setting watchpoints of type TYPE is not supported, and negative if
801 CNT is more than the maximum number of watchpoints of type TYPE
802 that we can support. TYPE is one of bp_hardware_watchpoint,
803 bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint.
804 CNT is the number of such watchpoints used so far (including this
805 one). OTHERTYPE is non-zero if other types of watchpoints are
808 We always return 1 here because we don't have enough information
809 about possible overlap of addresses that they want to watch. As an
810 extreme example, consider the case where all the watchpoints watch
811 the same address and the same region length: then we can handle a
812 virtually unlimited number of watchpoints, due to debug register
813 sharing implemented via reference counts in i386-nat.c. */
816 i386_can_use_hw_breakpoint (int type, int cnt, int othertype)
822 add_show_debug_regs_command (void)
824 /* A maintenance command to enable printing the internal DRi mirror
826 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance,
828 Set whether to show variables that mirror the x86 debug registers."), _("\
829 Show whether to show variables that mirror the x86 debug registers."), _("\
830 Use \"on\" to enable, \"off\" to disable.\n\
831 If enabled, the debug registers values are shown when GDB inserts\n\
832 or removes a hardware breakpoint or watchpoint, and when the inferior\n\
833 triggers a breakpoint or watchpoint."),
836 &maintenance_set_cmdlist,
837 &maintenance_show_cmdlist);
840 /* There are only two global functions left. */
843 i386_use_watchpoints (struct target_ops *t)
845 /* After a watchpoint trap, the PC points to the instruction after the
846 one that caused the trap. Therefore we don't need to step over it.
847 But we do need to reset the status register to avoid another trap. */
848 t->to_have_continuable_watchpoint = 1;
850 t->to_can_use_hw_breakpoint = i386_can_use_hw_breakpoint;
851 t->to_region_ok_for_hw_watchpoint = i386_region_ok_for_watchpoint;
852 t->to_stopped_by_watchpoint = i386_stopped_by_watchpoint;
853 t->to_stopped_data_address = i386_stopped_data_address;
854 t->to_insert_watchpoint = i386_insert_watchpoint;
855 t->to_remove_watchpoint = i386_remove_watchpoint;
856 t->to_insert_hw_breakpoint = i386_insert_hw_breakpoint;
857 t->to_remove_hw_breakpoint = i386_remove_hw_breakpoint;
861 i386_set_debug_register_length (int len)
863 /* This function should be called only once for each native target. */
864 gdb_assert (i386_dr_low.debug_register_length == 0);
865 gdb_assert (len == 4 || len == 8);
866 i386_dr_low.debug_register_length = len;
867 add_show_debug_regs_command ();