1 /* Native-dependent code for the i386.
3 Copyright (C) 2001, 2004, 2005, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "breakpoint.h"
27 #include "gdb_assert.h"
29 /* Support for hardware watchpoints and breakpoints using the i386
32 This provides several functions for inserting and removing
33 hardware-assisted breakpoints and watchpoints, testing if one or
34 more of the watchpoints triggered and at what address, checking
35 whether a given region can be watched, etc.
37 The functions below implement debug registers sharing by reference
38 counts, and allow to watch regions up to 16 bytes long. */
40 struct i386_dr_low_type i386_dr_low;
43 /* Support for 8-byte wide hw watchpoints. */
44 #define TARGET_HAS_DR_LEN_8 (i386_dr_low.debug_register_length == 8)
46 /* Debug registers' indices. */
47 #define DR_NADDR 4 /* The number of debug address registers. */
48 #define DR_STATUS 6 /* Index of debug status register (DR6). */
49 #define DR_CONTROL 7 /* Index of debug control register (DR7). */
51 /* DR7 Debug Control register fields. */
53 /* How many bits to skip in DR7 to get to R/W and LEN fields. */
54 #define DR_CONTROL_SHIFT 16
55 /* How many bits in DR7 per R/W and LEN field for each watchpoint. */
56 #define DR_CONTROL_SIZE 4
58 /* Watchpoint/breakpoint read/write fields in DR7. */
59 #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */
60 #define DR_RW_WRITE (0x1) /* Break on data writes. */
61 #define DR_RW_READ (0x3) /* Break on data reads or writes. */
63 /* This is here for completeness. No platform supports this
64 functionality yet (as of March 2001). Note that the DE flag in the
65 CR4 register needs to be set to support this. */
67 #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */
70 /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift
71 is so we could OR this with the read/write field defined above. */
72 #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */
73 #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */
74 #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */
75 #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */
77 /* Local and Global Enable flags in DR7.
79 When the Local Enable flag is set, the breakpoint/watchpoint is
80 enabled only for the current task; the processor automatically
81 clears this flag on every task switch. When the Global Enable flag
82 is set, the breakpoint/watchpoint is enabled for all tasks; the
83 processor never clears this flag.
85 Currently, all watchpoint are locally enabled. If you need to
86 enable them globally, read the comment which pertains to this in
87 i386_insert_aligned_watchpoint below. */
88 #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */
89 #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */
90 #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */
92 /* Local and global exact breakpoint enable flags (a.k.a. slowdown
93 flags). These are only required on i386, to allow detection of the
94 exact instruction which caused a watchpoint to break; i486 and
95 later processors do that automatically. We set these flags for
96 backwards compatibility. */
97 #define DR_LOCAL_SLOWDOWN (0x100)
98 #define DR_GLOBAL_SLOWDOWN (0x200)
100 /* Fields reserved by Intel. This includes the GD (General Detect
101 Enable) flag, which causes a debug exception to be generated when a
102 MOV instruction accesses one of the debug registers.
104 FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */
105 #define DR_CONTROL_RESERVED (0xFC00)
107 /* Auxiliary helper macros. */
109 /* A value that masks all fields in DR7 that are reserved by Intel. */
110 #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED)
112 /* The I'th debug register is vacant if its Local and Global Enable
113 bits are reset in the Debug Control register. */
114 #define I386_DR_VACANT(state, i) \
115 (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
117 /* Locally enable the break/watchpoint in the I'th debug register. */
118 #define I386_DR_LOCAL_ENABLE(state, i) \
120 (state)->dr_control_mirror |= \
121 (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
124 /* Globally enable the break/watchpoint in the I'th debug register. */
125 #define I386_DR_GLOBAL_ENABLE(state, i) \
127 (state)->dr_control_mirror |= \
128 (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
131 /* Disable the break/watchpoint in the I'th debug register. */
132 #define I386_DR_DISABLE(state, i) \
134 (state)->dr_control_mirror &= \
135 ~(3 << (DR_ENABLE_SIZE * (i))); \
138 /* Set in DR7 the RW and LEN fields for the I'th debug register. */
139 #define I386_DR_SET_RW_LEN(state, i, rwlen) \
141 (state)->dr_control_mirror &= \
142 ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
143 (state)->dr_control_mirror |= \
144 ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
147 /* Get from DR7 the RW and LEN fields for the I'th debug register. */
148 #define I386_DR_GET_RW_LEN(dr7, i) \
150 >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
152 /* Mask that this I'th watchpoint has triggered. */
153 #define I386_DR_WATCH_MASK(i) (1 << (i))
155 /* Did the watchpoint whose address is in the I'th register break? */
156 #define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i)))
158 /* A macro to loop over all debug registers. */
159 #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++)
162 /* Global state needed to track h/w watchpoints. */
164 struct i386_debug_reg_state
166 /* Mirror the inferior's DRi registers. We keep the status and
167 control registers separated because they don't hold addresses.
168 Note that since we can change these mirrors while threads are
169 running, we never trust them to explain a cause of a trap.
170 For that, we need to peek directly in the inferior registers. */
171 CORE_ADDR dr_mirror[DR_NADDR];
172 unsigned dr_status_mirror, dr_control_mirror;
174 /* Reference counts for each debug register. */
175 int dr_ref_count[DR_NADDR];
178 /* Clear the reference counts and forget everything we knew about the
182 i386_init_dregs (struct i386_debug_reg_state *state)
186 ALL_DEBUG_REGISTERS (i)
188 state->dr_mirror[i] = 0;
189 state->dr_ref_count[i] = 0;
191 state->dr_control_mirror = 0;
192 state->dr_status_mirror = 0;
195 static struct i386_debug_reg_state dr_mirror;
197 /* Reference counts for each debug register. */
198 static int dr_ref_count[DR_NADDR];
200 /* Whether or not to print the mirrored debug registers. */
201 static int maint_show_dr;
203 /* Types of operations supported by i386_handle_nonaligned_watchpoint. */
204 typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t;
206 /* Internal functions. */
208 /* Return the value of a 4-bit field for DR7 suitable for watching a
209 region of LEN bytes for accesses of type TYPE. LEN is assumed to
210 have the value of 1, 2, or 4. */
211 static unsigned i386_length_and_rw_bits (int len, enum target_hw_bp_type type);
213 /* Insert a watchpoint at address ADDR, which is assumed to be aligned
214 according to the length of the region to watch. LEN_RW_BITS is the
215 value of the bit-field from DR7 which describes the length and
216 access type of the region to be watched by this watchpoint. Return
217 0 on success, -1 on failure. */
218 static int i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state,
220 unsigned len_rw_bits);
222 /* Remove a watchpoint at address ADDR, which is assumed to be aligned
223 according to the length of the region to watch. LEN_RW_BITS is the
224 value of the bits from DR7 which describes the length and access
225 type of the region watched by this watchpoint. Return 0 on
226 success, -1 on failure. */
227 static int i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state,
229 unsigned len_rw_bits);
231 /* Insert or remove a (possibly non-aligned) watchpoint, or count the
232 number of debug registers required to watch a region at address
233 ADDR whose length is LEN for accesses of type TYPE. Return 0 on
234 successful insertion or removal, a positive number when queried
235 about the number of registers, or -1 on failure. If WHAT is not a
236 valid value, bombs through internal_error. */
237 static int i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state,
239 CORE_ADDR addr, int len,
240 enum target_hw_bp_type type);
242 /* Implementation. */
244 /* Clear the reference counts and forget everything we knew about the
248 i386_cleanup_dregs (void)
250 i386_init_dregs (&dr_mirror);
253 /* Print the values of the mirrored debug registers. This is called
254 when maint_show_dr is non-zero. To set that up, type "maint
255 show-debug-regs" at GDB's prompt. */
258 i386_show_dr (struct i386_debug_reg_state *state,
259 const char *func, CORE_ADDR addr,
260 int len, enum target_hw_bp_type type)
262 int addr_size = gdbarch_addr_bit (target_gdbarch) / 8;
265 puts_unfiltered (func);
267 printf_unfiltered (" (addr=%lx, len=%d, type=%s)",
268 /* This code is for ia32, so casting CORE_ADDR
269 to unsigned long should be okay. */
270 (unsigned long)addr, len,
271 type == hw_write ? "data-write"
272 : (type == hw_read ? "data-read"
273 : (type == hw_access ? "data-read/write"
274 : (type == hw_execute ? "instruction-execute"
275 /* FIXME: if/when I/O read/write
276 watchpoints are supported, add them
279 puts_unfiltered (":\n");
280 printf_unfiltered ("\tCONTROL (DR7): %s STATUS (DR6): %s\n",
281 phex (state->dr_control_mirror, 8),
282 phex (state->dr_status_mirror, 8));
283 ALL_DEBUG_REGISTERS(i)
285 printf_unfiltered ("\
286 \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n",
287 i, phex (state->dr_mirror[i], addr_size),
288 state->dr_ref_count[i],
289 i + 1, phex (state->dr_mirror[i + 1], addr_size),
290 state->dr_ref_count[i+1]);
295 /* Return the value of a 4-bit field for DR7 suitable for watching a
296 region of LEN bytes for accesses of type TYPE. LEN is assumed to
297 have the value of 1, 2, or 4. */
300 i386_length_and_rw_bits (int len, enum target_hw_bp_type type)
313 internal_error (__FILE__, __LINE__,
314 _("The i386 doesn't support "
315 "data-read watchpoints.\n"));
320 /* Not yet supported. */
326 internal_error (__FILE__, __LINE__, _("\
327 Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n"),
334 return (DR_LEN_1 | rw);
336 return (DR_LEN_2 | rw);
338 return (DR_LEN_4 | rw);
340 if (TARGET_HAS_DR_LEN_8)
341 return (DR_LEN_8 | rw);
342 /* ELSE FALL THROUGH */
344 internal_error (__FILE__, __LINE__, _("\
345 Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n"), len);
349 /* Insert a watchpoint at address ADDR, which is assumed to be aligned
350 according to the length of the region to watch. LEN_RW_BITS is the
351 value of the bits from DR7 which describes the length and access
352 type of the region to be watched by this watchpoint. Return 0 on
353 success, -1 on failure. */
356 i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state,
357 CORE_ADDR addr, unsigned len_rw_bits)
361 if (!i386_dr_low.set_addr || !i386_dr_low.set_control)
364 /* First, look for an occupied debug register with the same address
365 and the same RW and LEN definitions. If we find one, we can
366 reuse it for this watchpoint as well (and save a register). */
367 ALL_DEBUG_REGISTERS(i)
369 if (!I386_DR_VACANT (state, i)
370 && state->dr_mirror[i] == addr
371 && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits)
373 state->dr_ref_count[i]++;
378 /* Next, look for a vacant debug register. */
379 ALL_DEBUG_REGISTERS(i)
381 if (I386_DR_VACANT (state, i))
385 /* No more debug registers! */
389 /* Now set up the register I to watch our region. */
391 /* Record the info in our local mirrored array. */
392 state->dr_mirror[i] = addr;
393 state->dr_ref_count[i] = 1;
394 I386_DR_SET_RW_LEN (state, i, len_rw_bits);
395 /* Note: we only enable the watchpoint locally, i.e. in the current
396 task. Currently, no i386 target allows or supports global
397 watchpoints; however, if any target would want that in the
398 future, GDB should probably provide a command to control whether
399 to enable watchpoints globally or locally, and the code below
400 should use global or local enable and slow-down flags as
402 I386_DR_LOCAL_ENABLE (state, i);
403 state->dr_control_mirror |= DR_LOCAL_SLOWDOWN;
404 state->dr_control_mirror &= I386_DR_CONTROL_MASK;
409 /* Remove a watchpoint at address ADDR, which is assumed to be aligned
410 according to the length of the region to watch. LEN_RW_BITS is the
411 value of the bits from DR7 which describes the length and access
412 type of the region watched by this watchpoint. Return 0 on
413 success, -1 on failure. */
416 i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state,
417 CORE_ADDR addr, unsigned len_rw_bits)
421 ALL_DEBUG_REGISTERS(i)
423 if (!I386_DR_VACANT (state, i)
424 && state->dr_mirror[i] == addr
425 && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits)
427 if (--state->dr_ref_count[i] == 0) /* no longer in use? */
429 /* Reset our mirror. */
430 state->dr_mirror[i] = 0;
431 I386_DR_DISABLE (state, i);
440 /* Insert or remove a (possibly non-aligned) watchpoint, or count the
441 number of debug registers required to watch a region at address
442 ADDR whose length is LEN for accesses of type TYPE. Return 0 on
443 successful insertion or removal, a positive number when queried
444 about the number of registers, or -1 on failure. If WHAT is not a
445 valid value, bombs through internal_error. */
448 i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state,
449 i386_wp_op_t what, CORE_ADDR addr, int len,
450 enum target_hw_bp_type type)
453 int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4;
455 static int size_try_array[8][8] =
457 {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */
458 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */
459 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */
460 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */
461 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */
462 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */
463 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */
464 {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */
469 int align = addr % max_wp_len;
470 /* Four (eight on AMD64) is the maximum length a debug register
472 int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1);
473 int size = size_try_array[try][align];
475 if (what == WP_COUNT)
477 /* size_try_array[] is defined such that each iteration
478 through the loop is guaranteed to produce an address and a
479 size that can be watched with a single debug register.
480 Thus, for counting the registers required to watch a
481 region, we simply need to increment the count on each
487 unsigned len_rw = i386_length_and_rw_bits (size, type);
489 if (what == WP_INSERT)
490 retval = i386_insert_aligned_watchpoint (state, addr, len_rw);
491 else if (what == WP_REMOVE)
492 retval = i386_remove_aligned_watchpoint (state, addr, len_rw);
494 internal_error (__FILE__, __LINE__, _("\
495 Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"),
508 /* Update the inferior's debug registers with the new debug registers
509 state, in NEW_STATE, and then update our local mirror to match. */
512 i386_update_inferior_debug_regs (struct i386_debug_reg_state *new_state)
516 ALL_DEBUG_REGISTERS (i)
518 if (I386_DR_VACANT (new_state, i) != I386_DR_VACANT (&dr_mirror, i))
520 if (!I386_DR_VACANT (new_state, i))
522 i386_dr_low.set_addr (i, new_state->dr_mirror[i]);
524 /* Only a sanity check for leftover bits (set possibly only
526 if (i386_dr_low.unset_status)
527 i386_dr_low.unset_status (I386_DR_WATCH_MASK (i));
531 if (i386_dr_low.reset_addr)
532 i386_dr_low.reset_addr (i);
536 gdb_assert (new_state->dr_mirror[i] == dr_mirror.dr_mirror[i]);
539 if (new_state->dr_control_mirror != dr_mirror.dr_control_mirror)
540 i386_dr_low.set_control (new_state->dr_control_mirror);
542 dr_mirror = *new_state;
545 /* Insert a watchpoint to watch a memory region which starts at
546 address ADDR and whose length is LEN bytes. Watch memory accesses
547 of the type TYPE. Return 0 on success, -1 on failure. */
550 i386_insert_watchpoint (CORE_ADDR addr, int len, int type,
551 struct expression *cond)
554 /* Work on a local copy of the debug registers, and on success,
555 commit the change back to the inferior. */
556 struct i386_debug_reg_state local_state = dr_mirror;
559 return 1; /* unsupported */
561 if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8))
563 retval = i386_handle_nonaligned_watchpoint (&local_state,
564 WP_INSERT, addr, len, type);
567 unsigned len_rw = i386_length_and_rw_bits (len, type);
569 retval = i386_insert_aligned_watchpoint (&local_state,
574 i386_update_inferior_debug_regs (&local_state);
577 i386_show_dr (&dr_mirror, "insert_watchpoint", addr, len, type);
582 /* Remove a watchpoint that watched the memory region which starts at
583 address ADDR, whose length is LEN bytes, and for accesses of the
584 type TYPE. Return 0 on success, -1 on failure. */
586 i386_remove_watchpoint (CORE_ADDR addr, int len, int type,
587 struct expression *cond)
590 /* Work on a local copy of the debug registers, and on success,
591 commit the change back to the inferior. */
592 struct i386_debug_reg_state local_state = dr_mirror;
594 if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8))
596 retval = i386_handle_nonaligned_watchpoint (&local_state,
597 WP_REMOVE, addr, len, type);
600 unsigned len_rw = i386_length_and_rw_bits (len, type);
602 retval = i386_remove_aligned_watchpoint (&local_state,
607 i386_update_inferior_debug_regs (&local_state);
610 i386_show_dr (&dr_mirror, "remove_watchpoint", addr, len, type);
615 /* Return non-zero if we can watch a memory region that starts at
616 address ADDR and whose length is LEN bytes. */
619 i386_region_ok_for_watchpoint (CORE_ADDR addr, int len)
623 /* Compute how many aligned watchpoints we would need to cover this
625 nregs = i386_handle_nonaligned_watchpoint (&dr_mirror,
626 WP_COUNT, addr, len, hw_write);
627 return nregs <= DR_NADDR ? 1 : 0;
630 /* If the inferior has some watchpoint that triggered, set the
631 address associated with that watchpoint and return non-zero.
632 Otherwise, return zero. */
635 i386_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p)
642 struct i386_debug_reg_state *state = &dr_mirror;
644 dr_mirror.dr_status_mirror = i386_dr_low.get_status ();
645 status = dr_mirror.dr_status_mirror;
646 control = dr_mirror.dr_control_mirror;
648 ALL_DEBUG_REGISTERS(i)
650 if (I386_DR_WATCH_HIT (status, i)
651 /* This second condition makes sure DRi is set up for a data
652 watchpoint, not a hardware breakpoint. The reason is
653 that GDB doesn't call the target_stopped_data_address
654 method except for data watchpoints. In other words, I'm
656 && I386_DR_GET_RW_LEN (control, i) != 0
657 /* This third condition makes sure DRi is not vacant, this
658 avoids false positives in windows-nat.c. */
659 && !I386_DR_VACANT (state, i))
661 addr = state->dr_mirror[i];
664 i386_show_dr (&dr_mirror, "watchpoint_hit", addr, -1, hw_write);
667 if (maint_show_dr && addr == 0)
668 i386_show_dr (&dr_mirror, "stopped_data_addr", 0, 0, hw_write);
676 i386_stopped_by_watchpoint (void)
679 return i386_stopped_data_address (¤t_target, &addr);
682 /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address.
683 Return 0 on success, EBUSY on failure. */
685 i386_insert_hw_breakpoint (struct gdbarch *gdbarch,
686 struct bp_target_info *bp_tgt)
688 unsigned len_rw = i386_length_and_rw_bits (1, hw_execute);
689 CORE_ADDR addr = bp_tgt->placed_address;
690 int retval = i386_insert_aligned_watchpoint (&dr_mirror,
691 addr, len_rw) ? EBUSY : 0;
694 i386_show_dr (&dr_mirror, "insert_hwbp", addr, 1, hw_execute);
699 /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address.
700 Return 0 on success, -1 on failure. */
703 i386_remove_hw_breakpoint (struct gdbarch *gdbarch,
704 struct bp_target_info *bp_tgt)
706 unsigned len_rw = i386_length_and_rw_bits (1, hw_execute);
707 CORE_ADDR addr = bp_tgt->placed_address;
708 int retval = i386_remove_aligned_watchpoint (&dr_mirror,
712 i386_show_dr (&dr_mirror, "remove_hwbp", addr, 1, hw_execute);
717 /* Returns the number of hardware watchpoints of type TYPE that we can
718 set. Value is positive if we can set CNT watchpoints, zero if
719 setting watchpoints of type TYPE is not supported, and negative if
720 CNT is more than the maximum number of watchpoints of type TYPE
721 that we can support. TYPE is one of bp_hardware_watchpoint,
722 bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint.
723 CNT is the number of such watchpoints used so far (including this
724 one). OTHERTYPE is non-zero if other types of watchpoints are
727 We always return 1 here because we don't have enough information
728 about possible overlap of addresses that they want to watch. As an
729 extreme example, consider the case where all the watchpoints watch
730 the same address and the same region length: then we can handle a
731 virtually unlimited number of watchpoints, due to debug register
732 sharing implemented via reference counts in i386-nat.c. */
735 i386_can_use_hw_breakpoint (int type, int cnt, int othertype)
741 add_show_debug_regs_command (void)
743 /* A maintenance command to enable printing the internal DRi mirror
745 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance,
747 Set whether to show variables that mirror the x86 debug registers."), _("\
748 Show whether to show variables that mirror the x86 debug registers."), _("\
749 Use \"on\" to enable, \"off\" to disable.\n\
750 If enabled, the debug registers values are shown when GDB inserts\n\
751 or removes a hardware breakpoint or watchpoint, and when the inferior\n\
752 triggers a breakpoint or watchpoint."),
755 &maintenance_set_cmdlist,
756 &maintenance_show_cmdlist);
759 /* There are only two global functions left. */
762 i386_use_watchpoints (struct target_ops *t)
764 /* After a watchpoint trap, the PC points to the instruction after the
765 one that caused the trap. Therefore we don't need to step over it.
766 But we do need to reset the status register to avoid another trap. */
767 t->to_have_continuable_watchpoint = 1;
769 t->to_can_use_hw_breakpoint = i386_can_use_hw_breakpoint;
770 t->to_region_ok_for_hw_watchpoint = i386_region_ok_for_watchpoint;
771 t->to_stopped_by_watchpoint = i386_stopped_by_watchpoint;
772 t->to_stopped_data_address = i386_stopped_data_address;
773 t->to_insert_watchpoint = i386_insert_watchpoint;
774 t->to_remove_watchpoint = i386_remove_watchpoint;
775 t->to_insert_hw_breakpoint = i386_insert_hw_breakpoint;
776 t->to_remove_hw_breakpoint = i386_remove_hw_breakpoint;
780 i386_set_debug_register_length (int len)
782 /* This function should be called only once for each native target. */
783 gdb_assert (i386_dr_low.debug_register_length == 0);
784 gdb_assert (len == 4 || len == 8);
785 i386_dr_low.debug_register_length = len;
786 add_show_debug_regs_command ();