1 /* GNU/Linux/PowerPC specific low level interface, for the remote server for
3 Copyright (C) 1995, 1996, 1998, 1999, 2000, 2001, 2002, 2005, 2007, 2008,
4 2009 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "linux-low.h"
25 #include <asm/ptrace.h>
27 /* These are in <asm/cputable.h> in current kernels. */
28 #define PPC_FEATURE_HAS_VSX 0x00000080
29 #define PPC_FEATURE_HAS_ALTIVEC 0x10000000
30 #define PPC_FEATURE_HAS_SPE 0x00800000
31 #define PPC_FEATURE_HAS_DFP 0x00000400
33 static unsigned long ppc_hwcap;
36 /* Defined in auto-generated file powerpc-32l.c. */
37 void init_registers_powerpc_32l (void);
38 /* Defined in auto-generated file powerpc-altivec32l.c. */
39 void init_registers_powerpc_altivec32l (void);
40 /* Defined in auto-generated file powerpc-vsx32l.c. */
41 void init_registers_powerpc_vsx32l (void);
42 /* Defined in auto-generated file powerpc-isa205-32l.c. */
43 void init_registers_powerpc_isa205_32l (void);
44 /* Defined in auto-generated file powerpc-isa205-altivec32l.c. */
45 void init_registers_powerpc_isa205_altivec32l (void);
46 /* Defined in auto-generated file powerpc-isa205-vsx32l.c. */
47 void init_registers_powerpc_isa205_vsx32l (void);
48 /* Defined in auto-generated file powerpc-e500l.c. */
49 void init_registers_powerpc_e500l (void);
50 /* Defined in auto-generated file powerpc-64l.c. */
51 void init_registers_powerpc_64l (void);
52 /* Defined in auto-generated file powerpc-altivec64l.c. */
53 void init_registers_powerpc_altivec64l (void);
54 /* Defined in auto-generated file powerpc-vsx64l.c. */
55 void init_registers_powerpc_vsx64l (void);
56 /* Defined in auto-generated file powerpc-isa205-64l.c. */
57 void init_registers_powerpc_isa205_64l (void);
58 /* Defined in auto-generated file powerpc-isa205-altivec64l.c. */
59 void init_registers_powerpc_isa205_altivec64l (void);
60 /* Defined in auto-generated file powerpc-isa205-vsx64l.c. */
61 void init_registers_powerpc_isa205_vsx64l (void);
63 #define ppc_num_regs 73
65 /* This sometimes isn't defined. */
74 /* We use a constant for FPSCR instead of PT_FPSCR, because
75 many shipped PPC64 kernels had the wrong value in ptrace.h. */
76 static int ppc_regmap[] =
77 {PT_R0 * 8, PT_R1 * 8, PT_R2 * 8, PT_R3 * 8,
78 PT_R4 * 8, PT_R5 * 8, PT_R6 * 8, PT_R7 * 8,
79 PT_R8 * 8, PT_R9 * 8, PT_R10 * 8, PT_R11 * 8,
80 PT_R12 * 8, PT_R13 * 8, PT_R14 * 8, PT_R15 * 8,
81 PT_R16 * 8, PT_R17 * 8, PT_R18 * 8, PT_R19 * 8,
82 PT_R20 * 8, PT_R21 * 8, PT_R22 * 8, PT_R23 * 8,
83 PT_R24 * 8, PT_R25 * 8, PT_R26 * 8, PT_R27 * 8,
84 PT_R28 * 8, PT_R29 * 8, PT_R30 * 8, PT_R31 * 8,
85 PT_FPR0*8, PT_FPR0*8 + 8, PT_FPR0*8+16, PT_FPR0*8+24,
86 PT_FPR0*8+32, PT_FPR0*8+40, PT_FPR0*8+48, PT_FPR0*8+56,
87 PT_FPR0*8+64, PT_FPR0*8+72, PT_FPR0*8+80, PT_FPR0*8+88,
88 PT_FPR0*8+96, PT_FPR0*8+104, PT_FPR0*8+112, PT_FPR0*8+120,
89 PT_FPR0*8+128, PT_FPR0*8+136, PT_FPR0*8+144, PT_FPR0*8+152,
90 PT_FPR0*8+160, PT_FPR0*8+168, PT_FPR0*8+176, PT_FPR0*8+184,
91 PT_FPR0*8+192, PT_FPR0*8+200, PT_FPR0*8+208, PT_FPR0*8+216,
92 PT_FPR0*8+224, PT_FPR0*8+232, PT_FPR0*8+240, PT_FPR0*8+248,
93 PT_NIP * 8, PT_MSR * 8, PT_CCR * 8, PT_LNK * 8,
94 PT_CTR * 8, PT_XER * 8, PT_FPR0*8 + 256,
95 PT_ORIG_R3 * 8, PT_TRAP * 8 };
97 /* Currently, don't check/send MQ. */
98 static int ppc_regmap[] =
99 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
100 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
101 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
102 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
103 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
104 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
105 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
106 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
107 PT_FPR0*4, PT_FPR0*4 + 8, PT_FPR0*4+16, PT_FPR0*4+24,
108 PT_FPR0*4+32, PT_FPR0*4+40, PT_FPR0*4+48, PT_FPR0*4+56,
109 PT_FPR0*4+64, PT_FPR0*4+72, PT_FPR0*4+80, PT_FPR0*4+88,
110 PT_FPR0*4+96, PT_FPR0*4+104, PT_FPR0*4+112, PT_FPR0*4+120,
111 PT_FPR0*4+128, PT_FPR0*4+136, PT_FPR0*4+144, PT_FPR0*4+152,
112 PT_FPR0*4+160, PT_FPR0*4+168, PT_FPR0*4+176, PT_FPR0*4+184,
113 PT_FPR0*4+192, PT_FPR0*4+200, PT_FPR0*4+208, PT_FPR0*4+216,
114 PT_FPR0*4+224, PT_FPR0*4+232, PT_FPR0*4+240, PT_FPR0*4+248,
115 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
116 PT_CTR * 4, PT_XER * 4, PT_FPSCR * 4,
117 PT_ORIG_R3 * 4, PT_TRAP * 4
120 static int ppc_regmap_e500[] =
121 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
122 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
123 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
124 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
125 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
126 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
127 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
128 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
137 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
138 PT_CTR * 4, PT_XER * 4, -1,
139 PT_ORIG_R3 * 4, PT_TRAP * 4
144 ppc_cannot_store_register (int regno)
146 #ifndef __powerpc64__
147 /* Some kernels do not allow us to store fpscr. */
148 if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE) && regno == find_regno ("fpscr"))
152 /* Some kernels do not allow us to store orig_r3 or trap. */
153 if (regno == find_regno ("orig_r3")
154 || regno == find_regno ("trap"))
161 ppc_cannot_fetch_register (int regno)
167 ppc_collect_ptrace_register (int regno, char *buf)
169 int size = register_size (regno);
171 memset (buf, 0, sizeof (long));
173 if (size < sizeof (long))
174 collect_register (regno, buf + sizeof (long) - size);
176 collect_register (regno, buf);
180 ppc_supply_ptrace_register (int regno, const char *buf)
182 int size = register_size (regno);
183 if (size < sizeof (long))
184 supply_register (regno, buf + sizeof (long) - size);
186 supply_register (regno, buf);
192 if (register_size (0) == 4)
195 collect_register_by_name ("pc", &pc);
196 return (CORE_ADDR) pc;
201 collect_register_by_name ("pc", &pc);
202 return (CORE_ADDR) pc;
207 ppc_set_pc (CORE_ADDR pc)
209 if (register_size (0) == 4)
211 unsigned int newpc = pc;
212 supply_register_by_name ("pc", &newpc);
216 unsigned long newpc = pc;
217 supply_register_by_name ("pc", &newpc);
223 ppc_get_hwcap (unsigned long *valp)
225 int wordsize = register_size (0);
226 unsigned char *data = alloca (2 * wordsize);
229 while ((*the_target->read_auxv) (offset, data, 2 * wordsize) == 2 * wordsize)
233 unsigned int *data_p = (unsigned int *)data;
234 if (data_p[0] == AT_HWCAP)
242 unsigned long *data_p = (unsigned long *)data;
243 if (data_p[0] == AT_HWCAP)
250 offset += 2 * wordsize;
258 ppc_arch_setup (void)
263 /* On a 64-bit host, assume 64-bit inferior process with no
264 AltiVec registers. Reset ppc_hwcap to ensure that the
265 collect_register call below does not fail. */
266 init_registers_powerpc_64l ();
269 /* Only if the high bit of the MSR is set, we actually have
270 a 64-bit inferior. */
271 collect_register_by_name ("msr", &msr);
274 ppc_get_hwcap (&ppc_hwcap);
275 if (ppc_hwcap & PPC_FEATURE_HAS_VSX)
277 /* Power ISA 2.05 (implemented by Power 6 and newer processors)
278 increases the FPSCR from 32 bits to 64 bits. Even though Power 7
279 supports this ISA version, it doesn't have PPC_FEATURE_ARCH_2_05
280 set, only PPC_FEATURE_ARCH_2_06. Since for now the only bits
281 used in the higher half of the register are for Decimal Floating
282 Point, we check if that feature is available to decide the size
284 if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
285 init_registers_powerpc_isa205_vsx64l ();
287 init_registers_powerpc_vsx64l ();
289 else if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
291 if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
292 init_registers_powerpc_isa205_altivec64l ();
294 init_registers_powerpc_altivec64l ();
301 /* OK, we have a 32-bit inferior. */
302 init_registers_powerpc_32l ();
304 ppc_get_hwcap (&ppc_hwcap);
305 if (ppc_hwcap & PPC_FEATURE_HAS_VSX)
307 if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
308 init_registers_powerpc_isa205_vsx32l ();
310 init_registers_powerpc_vsx32l ();
312 else if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
314 if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
315 init_registers_powerpc_isa205_altivec32l ();
317 init_registers_powerpc_altivec32l ();
320 /* On 32-bit machines, check for SPE registers.
321 Set the low target's regmap field as appropriately. */
322 #ifndef __powerpc64__
323 the_low_target.regmap = ppc_regmap;
324 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
326 init_registers_powerpc_e500l ();
327 the_low_target.regmap = ppc_regmap_e500;
330 /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit
331 slot and not just its second word. The PT_FPSCR supplied in a
332 32-bit GDB compilation doesn't reflect this. */
333 if (register_size (70) == 8)
334 ppc_regmap[70] = (48 + 2*32) * sizeof (long);
338 /* Correct in either endianness.
339 This instruction is "twge r2, r2", which GDB uses as a software
341 static const unsigned int ppc_breakpoint = 0x7d821008;
342 #define ppc_breakpoint_len 4
345 ppc_breakpoint_at (CORE_ADDR where)
349 (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
350 if (insn == ppc_breakpoint)
352 /* If necessary, recognize more trap instructions here. GDB only uses the
357 /* Provide only a fill function for the general register set. ps_lgetregs
358 will use this for NPTL support. */
360 static void ppc_fill_gregset (void *buf)
364 for (i = 0; i < 32; i++)
365 ppc_collect_ptrace_register (i, (char *) buf + ppc_regmap[i]);
367 for (i = 64; i < 70; i++)
368 ppc_collect_ptrace_register (i, (char *) buf + ppc_regmap[i]);
370 for (i = 71; i < 73; i++)
371 ppc_collect_ptrace_register (i, (char *) buf + ppc_regmap[i]);
374 #ifndef PTRACE_GETVSXREGS
375 #define PTRACE_GETVSXREGS 27
376 #define PTRACE_SETVSXREGS 28
379 #define SIZEOF_VSXREGS 32*8
382 ppc_fill_vsxregset (void *buf)
387 if (!(ppc_hwcap & PPC_FEATURE_HAS_VSX))
390 base = find_regno ("vs0h");
391 for (i = 0; i < 32; i++)
392 collect_register (base + i, ®set[i * 8]);
396 ppc_store_vsxregset (const void *buf)
399 const char *regset = buf;
401 if (!(ppc_hwcap & PPC_FEATURE_HAS_VSX))
404 base = find_regno ("vs0h");
405 for (i = 0; i < 32; i++)
406 supply_register (base + i, ®set[i * 8]);
409 #ifndef PTRACE_GETVRREGS
410 #define PTRACE_GETVRREGS 18
411 #define PTRACE_SETVRREGS 19
414 #define SIZEOF_VRREGS 33*16+4
417 ppc_fill_vrregset (void *buf)
422 if (!(ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC))
425 base = find_regno ("vr0");
426 for (i = 0; i < 32; i++)
427 collect_register (base + i, ®set[i * 16]);
429 collect_register_by_name ("vscr", ®set[32 * 16 + 12]);
430 collect_register_by_name ("vrsave", ®set[33 * 16]);
434 ppc_store_vrregset (const void *buf)
437 const char *regset = buf;
439 if (!(ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC))
442 base = find_regno ("vr0");
443 for (i = 0; i < 32; i++)
444 supply_register (base + i, ®set[i * 16]);
446 supply_register_by_name ("vscr", ®set[32 * 16 + 12]);
447 supply_register_by_name ("vrsave", ®set[33 * 16]);
450 #ifndef PTRACE_GETEVRREGS
451 #define PTRACE_GETEVRREGS 20
452 #define PTRACE_SETEVRREGS 21
455 struct gdb_evrregset_t
457 unsigned long evr[32];
458 unsigned long long acc;
459 unsigned long spefscr;
463 ppc_fill_evrregset (void *buf)
466 struct gdb_evrregset_t *regset = buf;
468 if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE))
471 ev0 = find_regno ("ev0h");
472 for (i = 0; i < 32; i++)
473 collect_register (ev0 + i, ®set->evr[i]);
475 collect_register_by_name ("acc", ®set->acc);
476 collect_register_by_name ("spefscr", ®set->spefscr);
480 ppc_store_evrregset (const void *buf)
483 const struct gdb_evrregset_t *regset = buf;
485 if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE))
488 ev0 = find_regno ("ev0h");
489 for (i = 0; i < 32; i++)
490 supply_register (ev0 + i, ®set->evr[i]);
492 supply_register_by_name ("acc", ®set->acc);
493 supply_register_by_name ("spefscr", ®set->spefscr);
496 struct regset_info target_regsets[] = {
497 /* List the extra register sets before GENERAL_REGS. That way we will
498 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
499 general registers. Some kernels support these, but not the newer
500 PPC_PTRACE_GETREGS. */
501 { PTRACE_GETVSXREGS, PTRACE_SETVSXREGS, SIZEOF_VSXREGS, EXTENDED_REGS,
502 ppc_fill_vsxregset, ppc_store_vsxregset },
503 { PTRACE_GETVRREGS, PTRACE_SETVRREGS, SIZEOF_VRREGS, EXTENDED_REGS,
504 ppc_fill_vrregset, ppc_store_vrregset },
505 { PTRACE_GETEVRREGS, PTRACE_SETEVRREGS, 32 * 4 + 8 + 4, EXTENDED_REGS,
506 ppc_fill_evrregset, ppc_store_evrregset },
507 { 0, 0, 0, GENERAL_REGS, ppc_fill_gregset, NULL },
508 { 0, 0, -1, -1, NULL, NULL }
511 struct linux_target_ops the_low_target = {
515 ppc_cannot_fetch_register,
516 ppc_cannot_store_register,
519 (const unsigned char *) &ppc_breakpoint,
528 ppc_collect_ptrace_register,
529 ppc_supply_ptrace_register,