1 /* GNU/Linux/AArch64 specific low level interface, for the remote server for
4 Copyright (C) 2009-2015 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "linux-low.h"
24 #include "elf/common.h"
28 #include <sys/ptrace.h>
29 #include <asm/ptrace.h>
32 #include "gdb_proc_service.h"
34 /* Defined in auto-generated files. */
35 void init_registers_aarch64 (void);
36 extern const struct target_desc *tdesc_aarch64;
42 #define AARCH64_X_REGS_NUM 31
43 #define AARCH64_V_REGS_NUM 32
44 #define AARCH64_X0_REGNO 0
45 #define AARCH64_SP_REGNO 31
46 #define AARCH64_PC_REGNO 32
47 #define AARCH64_CPSR_REGNO 33
48 #define AARCH64_V0_REGNO 34
49 #define AARCH64_FPSR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM)
50 #define AARCH64_FPCR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 1)
52 #define AARCH64_NUM_REGS (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 2)
57 /* These offsets correspond to GET/SETREGSET */
59 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8,
60 8*8, 9*8, 10*8, 11*8, 12*8, 13*8, 14*8, 15*8,
61 16*8, 17*8, 18*8, 19*8, 20*8, 21*8, 22*8, 23*8,
62 24*8, 25*8, 26*8, 27*8, 28*8,
67 33*8, /* cpsr 4 bytes!*/
69 /* FP register offsets correspond to GET/SETFPREGSET */
70 0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16,
71 8*16, 9*16, 10*16, 11*16, 12*16, 13*16, 14*16, 15*16,
72 16*16, 17*16, 18*16, 19*16, 20*16, 21*16, 22*16, 23*16,
73 24*16, 25*16, 26*16, 27*16, 28*16, 29*16, 30*16, 31*16
76 /* Here starts the macro definitions, data structures, and code for
77 the hardware breakpoint and hardware watchpoint support. The
78 following is the abbreviations that are used frequently in the code
85 /* Maximum number of hardware breakpoint and watchpoint registers.
86 Neither of these values may exceed the width of dr_changed_t
89 #define AARCH64_HBP_MAX_NUM 16
90 #define AARCH64_HWP_MAX_NUM 16
92 /* Alignment requirement in bytes of hardware breakpoint and
93 watchpoint address. This is the requirement for the addresses that
94 can be written to the hardware breakpoint/watchpoint value
95 registers. The kernel currently does not do any alignment on
96 addresses when receiving a writing request (via ptrace call) to
97 these debug registers, and it will reject any address that is
99 Some limited support has been provided in this gdbserver port for
100 unaligned watchpoints, so that from a gdb user point of view, an
101 unaligned watchpoint can still be set. This is achieved by
102 minimally enlarging the watched area to meet the alignment
103 requirement, and if necessary, splitting the watchpoint over
104 several hardware watchpoint registers. */
106 #define AARCH64_HBP_ALIGNMENT 4
107 #define AARCH64_HWP_ALIGNMENT 8
109 /* The maximum length of a memory region that can be watched by one
110 hardware watchpoint register. */
112 #define AARCH64_HWP_MAX_LEN_PER_REG 8
114 /* Each bit of a variable of this type is used to indicate whether a
115 hardware breakpoint or watchpoint setting has been changed since
116 the last updating. Bit N corresponds to the Nth hardware
117 breakpoint or watchpoint setting which is managed in
118 aarch64_debug_reg_state. Where N is valid between 0 and the total
119 number of the hardware breakpoint or watchpoint debug registers
120 minus 1. When the bit N is 1, it indicates the corresponding
121 breakpoint or watchpoint setting is changed, and thus the
122 corresponding hardware debug register needs to be updated via the
125 In the per-thread arch-specific data area, we define two such
126 variables for per-thread hardware breakpoint and watchpoint
127 settings respectively.
129 This type is part of the mechanism which helps reduce the number of
130 ptrace calls to the kernel, i.e. avoid asking the kernel to write
131 to the debug registers with unchanged values. */
133 typedef unsigned long long dr_changed_t;
135 /* Set each of the lower M bits of X to 1; assert X is wide enough. */
137 #define DR_MARK_ALL_CHANGED(x, m) \
140 gdb_assert (sizeof ((x)) * 8 >= (m)); \
141 (x) = (((dr_changed_t)1 << (m)) - 1); \
144 #define DR_MARK_N_CHANGED(x, n) \
147 (x) |= ((dr_changed_t)1 << (n)); \
150 #define DR_CLEAR_CHANGED(x) \
156 #define DR_HAS_CHANGED(x) ((x) != 0)
157 #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
159 /* Structure for managing the hardware breakpoint/watchpoint resources.
160 DR_ADDR_* stores the address, DR_CTRL_* stores the control register
161 content, and DR_REF_COUNT_* counts the numbers of references to the
162 corresponding bp/wp, by which way the limited hardware resources
163 are not wasted on duplicated bp/wp settings (though so far gdb has
164 done a good job by not sending duplicated bp/wp requests). */
166 struct aarch64_debug_reg_state
168 /* hardware breakpoint */
169 CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM];
170 unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM];
171 unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM];
173 /* hardware watchpoint */
174 CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM];
175 unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM];
176 unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM];
179 /* Per-process arch-specific data we want to keep. */
181 struct arch_process_info
183 /* Hardware breakpoint/watchpoint data.
184 The reason for them to be per-process rather than per-thread is
185 due to the lack of information in the gdbserver environment;
186 gdbserver is not told that whether a requested hardware
187 breakpoint/watchpoint is thread specific or not, so it has to set
188 each hw bp/wp for every thread in the current process. The
189 higher level bp/wp management in gdb will resume a thread if a hw
190 bp/wp trap is not expected for it. Since the hw bp/wp setting is
191 same for each thread, it is reasonable for the data to live here.
193 struct aarch64_debug_reg_state debug_reg_state;
196 /* Per-thread arch-specific data we want to keep. */
200 /* When bit N is 1, it indicates the Nth hardware breakpoint or
201 watchpoint register pair needs to be updated when the thread is
202 resumed; see aarch64_linux_prepare_to_resume. */
203 dr_changed_t dr_changed_bp;
204 dr_changed_t dr_changed_wp;
207 /* Number of hardware breakpoints/watchpoints the target supports.
208 They are initialized with values obtained via the ptrace calls
209 with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */
211 static int aarch64_num_bp_regs;
212 static int aarch64_num_wp_regs;
215 aarch64_cannot_store_register (int regno)
217 return regno >= AARCH64_NUM_REGS;
221 aarch64_cannot_fetch_register (int regno)
223 return regno >= AARCH64_NUM_REGS;
227 aarch64_fill_gregset (struct regcache *regcache, void *buf)
229 struct user_pt_regs *regset = buf;
232 for (i = 0; i < AARCH64_X_REGS_NUM; i++)
233 collect_register (regcache, AARCH64_X0_REGNO + i, ®set->regs[i]);
234 collect_register (regcache, AARCH64_SP_REGNO, ®set->sp);
235 collect_register (regcache, AARCH64_PC_REGNO, ®set->pc);
236 collect_register (regcache, AARCH64_CPSR_REGNO, ®set->pstate);
240 aarch64_store_gregset (struct regcache *regcache, const void *buf)
242 const struct user_pt_regs *regset = buf;
245 for (i = 0; i < AARCH64_X_REGS_NUM; i++)
246 supply_register (regcache, AARCH64_X0_REGNO + i, ®set->regs[i]);
247 supply_register (regcache, AARCH64_SP_REGNO, ®set->sp);
248 supply_register (regcache, AARCH64_PC_REGNO, ®set->pc);
249 supply_register (regcache, AARCH64_CPSR_REGNO, ®set->pstate);
253 aarch64_fill_fpregset (struct regcache *regcache, void *buf)
255 struct user_fpsimd_state *regset = buf;
258 for (i = 0; i < AARCH64_V_REGS_NUM; i++)
259 collect_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]);
260 collect_register (regcache, AARCH64_FPSR_REGNO, ®set->fpsr);
261 collect_register (regcache, AARCH64_FPCR_REGNO, ®set->fpcr);
265 aarch64_store_fpregset (struct regcache *regcache, const void *buf)
267 const struct user_fpsimd_state *regset = buf;
270 for (i = 0; i < AARCH64_V_REGS_NUM; i++)
271 supply_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]);
272 supply_register (regcache, AARCH64_FPSR_REGNO, ®set->fpsr);
273 supply_register (regcache, AARCH64_FPCR_REGNO, ®set->fpcr);
276 /* Enable miscellaneous debugging output. The name is historical - it
277 was originally used to debug LinuxThreads support. */
278 extern int debug_threads;
281 aarch64_get_pc (struct regcache *regcache)
285 collect_register_by_name (regcache, "pc", &pc);
287 debug_printf ("stop pc is %08lx\n", pc);
292 aarch64_set_pc (struct regcache *regcache, CORE_ADDR pc)
294 unsigned long newpc = pc;
295 supply_register_by_name (regcache, "pc", &newpc);
298 #define aarch64_breakpoint_len 4
300 /* AArch64 BRK software debug mode instruction.
301 This instruction needs to match gdb/aarch64-tdep.c
302 (aarch64_default_breakpoint). */
303 static const gdb_byte aarch64_breakpoint[] = {0x00, 0x00, 0x20, 0xd4};
306 aarch64_breakpoint_at (CORE_ADDR where)
308 gdb_byte insn[aarch64_breakpoint_len];
310 (*the_target->read_memory) (where, (unsigned char *) &insn,
311 aarch64_breakpoint_len);
312 if (memcmp (insn, aarch64_breakpoint, aarch64_breakpoint_len) == 0)
318 /* Print the values of the cached breakpoint/watchpoint registers.
319 This is enabled via the "set debug-hw-points" monitor command. */
322 aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
323 const char *func, CORE_ADDR addr,
324 int len, enum target_hw_bp_type type)
328 fprintf (stderr, "%s", func);
330 fprintf (stderr, " (addr=0x%08lx, len=%d, type=%s)",
331 (unsigned long) addr, len,
332 type == hw_write ? "hw-write-watchpoint"
333 : (type == hw_read ? "hw-read-watchpoint"
334 : (type == hw_access ? "hw-access-watchpoint"
335 : (type == hw_execute ? "hw-breakpoint"
337 fprintf (stderr, ":\n");
339 fprintf (stderr, "\tBREAKPOINTs:\n");
340 for (i = 0; i < aarch64_num_bp_regs; i++)
341 fprintf (stderr, "\tBP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n",
342 i, paddress (state->dr_addr_bp[i]),
343 state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]);
345 fprintf (stderr, "\tWATCHPOINTs:\n");
346 for (i = 0; i < aarch64_num_wp_regs; i++)
347 fprintf (stderr, "\tWP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n",
348 i, paddress (state->dr_addr_wp[i]),
349 state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]);
353 aarch64_init_debug_reg_state (struct aarch64_debug_reg_state *state)
357 for (i = 0; i < AARCH64_HBP_MAX_NUM; ++i)
359 state->dr_addr_bp[i] = 0;
360 state->dr_ctrl_bp[i] = 0;
361 state->dr_ref_count_bp[i] = 0;
364 for (i = 0; i < AARCH64_HWP_MAX_NUM; ++i)
366 state->dr_addr_wp[i] = 0;
367 state->dr_ctrl_wp[i] = 0;
368 state->dr_ref_count_wp[i] = 0;
372 /* ptrace expects control registers to be formatted as follows:
375 +--------------------------------+----------+------+------+----+
376 | RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN |
377 +--------------------------------+----------+------+------+----+
379 The TYPE field is ignored for breakpoints. */
381 #define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1)
382 #define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff)
384 /* Utility function that returns the length in bytes of a watchpoint
385 according to the content of a hardware debug control register CTRL.
386 Note that the kernel currently only supports the following Byte
387 Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
388 that for a hardware watchpoint, its valid length can only be 1
389 byte, 2 bytes, 4 bytes or 8 bytes. */
391 static inline unsigned int
392 aarch64_watchpoint_length (unsigned int ctrl)
394 switch (DR_CONTROL_LENGTH (ctrl))
409 /* Given the hardware breakpoint or watchpoint type TYPE and its
410 length LEN, return the expected encoding for a hardware
411 breakpoint/watchpoint control register. */
414 aarch64_point_encode_ctrl_reg (enum target_hw_bp_type type, int len)
416 unsigned int ctrl, ttype;
434 perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
440 ctrl |= ((1 << len) - 1) << 5;
442 ctrl |= (2 << 1) | 1;
447 /* Addresses to be written to the hardware breakpoint and watchpoint
448 value registers need to be aligned; the alignment is 4-byte and
449 8-type respectively. Linux kernel rejects any non-aligned address
450 it receives from the related ptrace call. Furthermore, the kernel
451 currently only supports the following Byte Address Select (BAS)
452 values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
453 watchpoint to be accepted by the kernel (via ptrace call), its
454 valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
455 Despite these limitations, the unaligned watchpoint is supported in
458 Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */
461 aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len)
463 unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT
464 : AARCH64_HBP_ALIGNMENT;
466 if (addr & (alignment - 1))
469 if (len != 8 && len != 4 && len != 2 && len != 1)
475 /* Given the (potentially unaligned) watchpoint address in ADDR and
476 length in LEN, return the aligned address and aligned length in
477 *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned
478 aligned address and length will be valid to be written to the
479 hardware watchpoint value and control registers. See the comment
480 above aarch64_point_is_aligned for the information about the
481 alignment requirement. The given watchpoint may get truncated if
482 more than one hardware register is needed to cover the watched
483 region. *NEXT_ADDR_P and *NEXT_LEN_P, if non-NULL, will return the
484 address and length of the remaining part of the watchpoint (which
485 can be processed by calling this routine again to generate another
486 aligned address and length pair.
488 Essentially, unaligned watchpoint is achieved by minimally
489 enlarging the watched area to meet the alignment requirement, and
490 if necessary, splitting the watchpoint over several hardware
491 watchpoint registers. The trade-off is that there will be
492 false-positive hits for the read-type or the access-type hardware
493 watchpoints; for the write type, which is more commonly used, there
494 will be no such issues, as the higher-level breakpoint management
495 in gdb always examines the exact watched region for any content
496 change, and transparently resumes a thread from a watchpoint trap
497 if there is no change to the watched region.
499 Another limitation is that because the watched region is enlarged,
500 the watchpoint fault address returned by
501 aarch64_stopped_data_address may be outside of the original watched
502 region, especially when the triggering instruction is accessing a
503 larger region. When the fault address is not within any known
504 range, watchpoints_triggered in gdb will get confused, as the
505 higher-level watchpoint management is only aware of original
506 watched regions, and will think that some unknown watchpoint has
507 been triggered. In such a case, gdb may stop without displaying
508 any detailed information.
510 Once the kernel provides the full support for Byte Address Select
511 (BAS) in the hardware watchpoint control register, these
512 limitations can be largely relaxed with some further work. */
515 aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p,
516 int *aligned_len_p, CORE_ADDR *next_addr_p,
521 CORE_ADDR aligned_addr;
522 const unsigned int alignment = AARCH64_HWP_ALIGNMENT;
523 const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG;
525 /* As assumed by the algorithm. */
526 gdb_assert (alignment == max_wp_len);
531 /* Address to be put into the hardware watchpoint value register
533 offset = addr & (alignment - 1);
534 aligned_addr = addr - offset;
536 gdb_assert (offset >= 0 && offset < alignment);
537 gdb_assert (aligned_addr >= 0 && aligned_addr <= addr);
538 gdb_assert ((offset + len) > 0);
540 if (offset + len >= max_wp_len)
542 /* Need more than one watchpoint registers; truncate it at the
543 alignment boundary. */
544 aligned_len = max_wp_len;
545 len -= (max_wp_len - offset);
546 addr += (max_wp_len - offset);
547 gdb_assert ((addr & (alignment - 1)) == 0);
551 /* Find the smallest valid length that is large enough to
552 accommodate this watchpoint. */
553 static const unsigned char
554 aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] =
555 { 1, 2, 4, 4, 8, 8, 8, 8 };
557 aligned_len = aligned_len_array[offset + len - 1];
562 if (aligned_addr_p != NULL)
563 *aligned_addr_p = aligned_addr;
564 if (aligned_len_p != NULL)
565 *aligned_len_p = aligned_len;
566 if (next_addr_p != NULL)
568 if (next_len_p != NULL)
572 /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
573 registers with data from *STATE. */
576 aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state,
577 int tid, int watchpoint)
581 struct user_hwdebug_state regs;
582 const CORE_ADDR *addr;
583 const unsigned int *ctrl;
585 memset (®s, 0, sizeof (regs));
586 iov.iov_base = ®s;
587 count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs;
588 addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp;
589 ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp;
592 iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs[count - 1])
593 + sizeof (regs.dbg_regs [count - 1]));
595 for (i = 0; i < count; i++)
597 regs.dbg_regs[i].addr = addr[i];
598 regs.dbg_regs[i].ctrl = ctrl[i];
601 if (ptrace (PTRACE_SETREGSET, tid,
602 watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK,
604 error (_("Unexpected error setting hardware debug registers"));
607 struct aarch64_dr_update_callback_param
614 /* Callback function which records the information about the change of
615 one hardware breakpoint/watchpoint setting for the thread ENTRY.
616 The information is passed in via PTR.
617 N.B. The actual updating of hardware debug registers is not
618 carried out until the moment the thread is resumed. */
621 debug_reg_change_callback (struct inferior_list_entry *entry, void *ptr)
623 struct thread_info *thread = (struct thread_info *) entry;
624 struct lwp_info *lwp = get_thread_lwp (thread);
625 struct aarch64_dr_update_callback_param *param_p
626 = (struct aarch64_dr_update_callback_param *) ptr;
627 int pid = param_p->pid;
628 int idx = param_p->idx;
629 int is_watchpoint = param_p->is_watchpoint;
630 struct arch_lwp_info *info = lwp->arch_private;
631 dr_changed_t *dr_changed_ptr;
632 dr_changed_t dr_changed;
636 fprintf (stderr, "debug_reg_change_callback: \n\tOn entry:\n");
637 fprintf (stderr, "\tpid%d, tid: %ld, dr_changed_bp=0x%llx, "
638 "dr_changed_wp=0x%llx\n",
639 pid, lwpid_of (thread), info->dr_changed_bp,
640 info->dr_changed_wp);
643 dr_changed_ptr = is_watchpoint ? &info->dr_changed_wp
644 : &info->dr_changed_bp;
645 dr_changed = *dr_changed_ptr;
647 /* Only update the threads of this process. */
648 if (pid_of (thread) == pid)
651 && (idx <= (is_watchpoint ? aarch64_num_wp_regs
652 : aarch64_num_bp_regs)));
654 /* The following assertion is not right, as there can be changes
655 that have not been made to the hardware debug registers
656 before new changes overwrite the old ones. This can happen,
657 for instance, when the breakpoint/watchpoint hit one of the
658 threads and the user enters continue; then what happens is:
659 1) all breakpoints/watchpoints are removed for all threads;
660 2) a single step is carried out for the thread that was hit;
661 3) all of the points are inserted again for all threads;
662 4) all threads are resumed.
663 The 2nd step will only affect the one thread in which the
664 bp/wp was hit, which means only that one thread is resumed;
665 remember that the actual updating only happen in
666 aarch64_linux_prepare_to_resume, so other threads remain
667 stopped during the removal and insertion of bp/wp. Therefore
668 for those threads, the change of insertion of the bp/wp
669 overwrites that of the earlier removals. (The situation may
670 be different when bp/wp is steppable, or in the non-stop
672 /* gdb_assert (DR_N_HAS_CHANGED (dr_changed, idx) == 0); */
674 /* The actual update is done later just before resuming the lwp,
675 we just mark that one register pair needs updating. */
676 DR_MARK_N_CHANGED (dr_changed, idx);
677 *dr_changed_ptr = dr_changed;
679 /* If the lwp isn't stopped, force it to momentarily pause, so
680 we can update its debug registers. */
682 linux_stop_lwp (lwp);
687 fprintf (stderr, "\tOn exit:\n\tpid%d, tid: %ld, dr_changed_bp=0x%llx, "
688 "dr_changed_wp=0x%llx\n",
689 pid, lwpid_of (thread), info->dr_changed_bp,
690 info->dr_changed_wp);
696 /* Notify each thread that their IDXth breakpoint/watchpoint register
697 pair needs to be updated. The message will be recorded in each
698 thread's arch-specific data area, the actual updating will be done
699 when the thread is resumed. */
702 aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state *state,
703 int is_watchpoint, unsigned int idx)
705 struct aarch64_dr_update_callback_param param;
707 /* Only update the threads of this process. */
708 param.pid = pid_of (current_thread);
710 param.is_watchpoint = is_watchpoint;
713 find_inferior (&all_threads, debug_reg_change_callback, (void *) ¶m);
717 /* Return the pointer to the debug register state structure in the
718 current process' arch-specific data area. */
720 static struct aarch64_debug_reg_state *
721 aarch64_get_debug_reg_state ()
723 struct process_info *proc;
725 proc = current_process ();
726 return &proc->priv->arch_private->debug_reg_state;
729 /* Record the insertion of one breakpoint/watchpoint, as represented
730 by ADDR and CTRL, in the process' arch-specific data area *STATE. */
733 aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state,
734 enum target_hw_bp_type type,
735 CORE_ADDR addr, int len)
737 int i, idx, num_regs, is_watchpoint;
738 unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
739 CORE_ADDR *dr_addr_p;
741 /* Set up state pointers. */
742 is_watchpoint = (type != hw_execute);
743 gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
746 num_regs = aarch64_num_wp_regs;
747 dr_addr_p = state->dr_addr_wp;
748 dr_ctrl_p = state->dr_ctrl_wp;
749 dr_ref_count = state->dr_ref_count_wp;
753 num_regs = aarch64_num_bp_regs;
754 dr_addr_p = state->dr_addr_bp;
755 dr_ctrl_p = state->dr_ctrl_bp;
756 dr_ref_count = state->dr_ref_count_bp;
759 ctrl = aarch64_point_encode_ctrl_reg (type, len);
761 /* Find an existing or free register in our cache. */
763 for (i = 0; i < num_regs; ++i)
765 if ((dr_ctrl_p[i] & 1) == 0)
767 gdb_assert (dr_ref_count[i] == 0);
769 /* no break; continue hunting for an exising one. */
771 else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
773 gdb_assert (dr_ref_count[i] != 0);
783 /* Update our cache. */
784 if ((dr_ctrl_p[idx] & 1) == 0)
787 dr_addr_p[idx] = addr;
788 dr_ctrl_p[idx] = ctrl;
789 dr_ref_count[idx] = 1;
790 /* Notify the change. */
791 aarch64_notify_debug_reg_change (state, is_watchpoint, idx);
802 /* Record the removal of one breakpoint/watchpoint, as represented by
803 ADDR and CTRL, in the process' arch-specific data area *STATE. */
806 aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state,
807 enum target_hw_bp_type type,
808 CORE_ADDR addr, int len)
810 int i, num_regs, is_watchpoint;
811 unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
812 CORE_ADDR *dr_addr_p;
814 /* Set up state pointers. */
815 is_watchpoint = (type != hw_execute);
816 gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
819 num_regs = aarch64_num_wp_regs;
820 dr_addr_p = state->dr_addr_wp;
821 dr_ctrl_p = state->dr_ctrl_wp;
822 dr_ref_count = state->dr_ref_count_wp;
826 num_regs = aarch64_num_bp_regs;
827 dr_addr_p = state->dr_addr_bp;
828 dr_ctrl_p = state->dr_ctrl_bp;
829 dr_ref_count = state->dr_ref_count_bp;
832 ctrl = aarch64_point_encode_ctrl_reg (type, len);
834 /* Find the entry that matches the ADDR and CTRL. */
835 for (i = 0; i < num_regs; ++i)
836 if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
838 gdb_assert (dr_ref_count[i] != 0);
846 /* Clear our cache. */
847 if (--dr_ref_count[i] == 0)
849 /* Clear the enable bit. */
853 /* Notify the change. */
854 aarch64_notify_debug_reg_change (state, is_watchpoint, i);
861 aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr,
862 int len, int is_insert)
864 struct aarch64_debug_reg_state *state;
866 /* The hardware breakpoint on AArch64 should always be 4-byte
868 if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len))
871 state = aarch64_get_debug_reg_state ();
874 return aarch64_dr_state_insert_one_point (state, type, addr, len);
876 return aarch64_dr_state_remove_one_point (state, type, addr, len);
879 /* This is essentially the same as aarch64_handle_breakpoint, apart
880 from that it is an aligned watchpoint to be handled. */
883 aarch64_handle_aligned_watchpoint (enum target_hw_bp_type type,
884 CORE_ADDR addr, int len, int is_insert)
886 struct aarch64_debug_reg_state *state;
888 state = aarch64_get_debug_reg_state ();
891 return aarch64_dr_state_insert_one_point (state, type, addr, len);
893 return aarch64_dr_state_remove_one_point (state, type, addr, len);
896 /* Insert/remove unaligned watchpoint by calling
897 aarch64_align_watchpoint repeatedly until the whole watched region,
898 as represented by ADDR and LEN, has been properly aligned and ready
899 to be written to one or more hardware watchpoint registers.
900 IS_INSERT indicates whether this is an insertion or a deletion.
901 Return 0 if succeed. */
904 aarch64_handle_unaligned_watchpoint (enum target_hw_bp_type type,
905 CORE_ADDR addr, int len, int is_insert)
907 struct aarch64_debug_reg_state *state
908 = aarch64_get_debug_reg_state ();
912 CORE_ADDR aligned_addr;
913 int aligned_len, ret;
915 aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len,
919 ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr,
922 ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr,
927 "handle_unaligned_watchpoint: is_insert: %d\n"
928 " aligned_addr: 0x%s, aligned_len: %d\n"
929 " next_addr: 0x%s, next_len: %d\n",
930 is_insert, paddress (aligned_addr), aligned_len,
931 paddress (addr), len);
941 aarch64_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr,
942 int len, int is_insert)
944 if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len))
945 return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert);
947 return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert);
951 aarch64_supports_z_point_type (char z_type)
957 case Z_PACKET_WRITE_WP:
958 case Z_PACKET_READ_WP:
959 case Z_PACKET_ACCESS_WP:
966 /* Insert a hardware breakpoint/watchpoint.
967 It actually only records the info of the to-be-inserted bp/wp;
968 the actual insertion will happen when threads are resumed.
971 Return 1 if TYPE is unsupported type;
972 Return -1 if an error occurs. */
975 aarch64_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
976 int len, struct raw_breakpoint *bp)
979 enum target_hw_bp_type targ_type;
982 fprintf (stderr, "insert_point on entry (addr=0x%08lx, len=%d)\n",
983 (unsigned long) addr, len);
985 /* Determine the type from the raw breakpoint type. */
986 targ_type = raw_bkpt_type_to_target_hw_bp_type (type);
988 if (targ_type != hw_execute)
990 aarch64_handle_watchpoint (targ_type, addr, len, 1 /* is_insert */);
993 aarch64_handle_breakpoint (targ_type, addr, len, 1 /* is_insert */);
996 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
997 "insert_point", addr, len, targ_type);
1002 /* Remove a hardware breakpoint/watchpoint.
1003 It actually only records the info of the to-be-removed bp/wp,
1004 the actual removal will be done when threads are resumed.
1006 Return 0 if succeed;
1007 Return 1 if TYPE is an unsupported type;
1008 Return -1 if an error occurs. */
1011 aarch64_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
1012 int len, struct raw_breakpoint *bp)
1015 enum target_hw_bp_type targ_type;
1017 if (show_debug_regs)
1018 fprintf (stderr, "remove_point on entry (addr=0x%08lx, len=%d)\n",
1019 (unsigned long) addr, len);
1021 /* Determine the type from the raw breakpoint type. */
1022 targ_type = raw_bkpt_type_to_target_hw_bp_type (type);
1024 /* Set up state pointers. */
1025 if (targ_type != hw_execute)
1027 aarch64_handle_watchpoint (targ_type, addr, len, 0 /* is_insert */);
1030 aarch64_handle_breakpoint (targ_type, addr, len, 0 /* is_insert */);
1032 if (show_debug_regs)
1033 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
1034 "remove_point", addr, len, targ_type);
1039 /* Returns the address associated with the watchpoint that hit, if
1040 any; returns 0 otherwise. */
1043 aarch64_stopped_data_address (void)
1047 struct aarch64_debug_reg_state *state;
1049 pid = lwpid_of (current_thread);
1051 /* Get the siginfo. */
1052 if (ptrace (PTRACE_GETSIGINFO, pid, NULL, &siginfo) != 0)
1053 return (CORE_ADDR) 0;
1055 /* Need to be a hardware breakpoint/watchpoint trap. */
1056 if (siginfo.si_signo != SIGTRAP
1057 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
1058 return (CORE_ADDR) 0;
1060 /* Check if the address matches any watched address. */
1061 state = aarch64_get_debug_reg_state ();
1062 for (i = aarch64_num_wp_regs - 1; i >= 0; --i)
1064 const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]);
1065 const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr;
1066 const CORE_ADDR addr_watch = state->dr_addr_wp[i];
1067 if (state->dr_ref_count_wp[i]
1068 && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i])
1069 && addr_trap >= addr_watch
1070 && addr_trap < addr_watch + len)
1074 return (CORE_ADDR) 0;
1077 /* Returns 1 if target was stopped due to a watchpoint hit, 0
1081 aarch64_stopped_by_watchpoint (void)
1083 if (aarch64_stopped_data_address () != 0)
1089 /* Fetch the thread-local storage pointer for libthread_db. */
1092 ps_get_thread_area (const struct ps_prochandle *ph,
1093 lwpid_t lwpid, int idx, void **base)
1098 iovec.iov_base = ®
1099 iovec.iov_len = sizeof (reg);
1101 if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0)
1104 /* IDX is the bias from the thread pointer to the beginning of the
1105 thread descriptor. It has to be subtracted due to implementation
1106 quirks in libthread_db. */
1107 *base = (void *) (reg - idx);
1112 /* Called when a new process is created. */
1114 static struct arch_process_info *
1115 aarch64_linux_new_process (void)
1117 struct arch_process_info *info = xcalloc (1, sizeof (*info));
1119 aarch64_init_debug_reg_state (&info->debug_reg_state);
1124 /* Called when a new thread is detected. */
1127 aarch64_linux_new_thread (struct lwp_info *lwp)
1129 struct arch_lwp_info *info = xcalloc (1, sizeof (*info));
1131 /* Mark that all the hardware breakpoint/watchpoint register pairs
1132 for this thread need to be initialized (with data from
1133 aarch_process_info.debug_reg_state). */
1134 DR_MARK_ALL_CHANGED (info->dr_changed_bp, aarch64_num_bp_regs);
1135 DR_MARK_ALL_CHANGED (info->dr_changed_wp, aarch64_num_wp_regs);
1137 lwp->arch_private = info;
1141 aarch64_linux_new_fork (struct process_info *parent,
1142 struct process_info *child)
1144 /* These are allocated by linux_add_process. */
1145 gdb_assert (parent->priv != NULL
1146 && parent->priv->arch_private != NULL);
1147 gdb_assert (child->priv != NULL
1148 && child->priv->arch_private != NULL);
1150 /* Linux kernel before 2.6.33 commit
1151 72f674d203cd230426437cdcf7dd6f681dad8b0d
1152 will inherit hardware debug registers from parent
1153 on fork/vfork/clone. Newer Linux kernels create such tasks with
1154 zeroed debug registers.
1156 GDB core assumes the child inherits the watchpoints/hw
1157 breakpoints of the parent, and will remove them all from the
1158 forked off process. Copy the debug registers mirrors into the
1159 new process so that all breakpoints and watchpoints can be
1160 removed together. The debug registers mirror will become zeroed
1161 in the end before detaching the forked off process, thus making
1162 this compatible with older Linux kernels too. */
1164 *child->priv->arch_private = *parent->priv->arch_private;
1167 /* Called when resuming a thread.
1168 If the debug regs have changed, update the thread's copies. */
1171 aarch64_linux_prepare_to_resume (struct lwp_info *lwp)
1173 struct thread_info *thread = get_lwp_thread (lwp);
1174 ptid_t ptid = ptid_of (thread);
1175 struct arch_lwp_info *info = lwp->arch_private;
1177 if (DR_HAS_CHANGED (info->dr_changed_bp)
1178 || DR_HAS_CHANGED (info->dr_changed_wp))
1180 int tid = ptid_get_lwp (ptid);
1181 struct process_info *proc = find_process_pid (ptid_get_pid (ptid));
1182 struct aarch64_debug_reg_state *state
1183 = &proc->priv->arch_private->debug_reg_state;
1185 if (show_debug_regs)
1186 fprintf (stderr, "prepare_to_resume thread %ld\n", lwpid_of (thread));
1189 if (DR_HAS_CHANGED (info->dr_changed_wp))
1191 aarch64_linux_set_debug_regs (state, tid, 1);
1192 DR_CLEAR_CHANGED (info->dr_changed_wp);
1196 if (DR_HAS_CHANGED (info->dr_changed_bp))
1198 aarch64_linux_set_debug_regs (state, tid, 0);
1199 DR_CLEAR_CHANGED (info->dr_changed_bp);
1204 /* ptrace hardware breakpoint resource info is formatted as follows:
1207 +---------------+--------------+---------------+---------------+
1208 | RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS |
1209 +---------------+--------------+---------------+---------------+ */
1211 #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
1212 #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
1213 #define AARCH64_DEBUG_ARCH_V8 0x6
1216 aarch64_arch_setup (void)
1220 struct user_hwdebug_state dreg_state;
1222 current_process ()->tdesc = tdesc_aarch64;
1224 pid = lwpid_of (current_thread);
1225 iov.iov_base = &dreg_state;
1226 iov.iov_len = sizeof (dreg_state);
1228 /* Get hardware watchpoint register info. */
1229 if (ptrace (PTRACE_GETREGSET, pid, NT_ARM_HW_WATCH, &iov) == 0
1230 && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
1232 aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
1233 if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM)
1235 warning ("Unexpected number of hardware watchpoint registers reported"
1236 " by ptrace, got %d, expected %d.",
1237 aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM);
1238 aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM;
1243 warning ("Unable to determine the number of hardware watchpoints"
1245 aarch64_num_wp_regs = 0;
1248 /* Get hardware breakpoint register info. */
1249 if (ptrace (PTRACE_GETREGSET, pid, NT_ARM_HW_BREAK, &iov) == 0
1250 && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
1252 aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
1253 if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM)
1255 warning ("Unexpected number of hardware breakpoint registers reported"
1256 " by ptrace, got %d, expected %d.",
1257 aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM);
1258 aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM;
1263 warning ("Unable to determine the number of hardware breakpoints"
1265 aarch64_num_bp_regs = 0;
1269 static struct regset_info aarch64_regsets[] =
1271 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS,
1272 sizeof (struct user_pt_regs), GENERAL_REGS,
1273 aarch64_fill_gregset, aarch64_store_gregset },
1274 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET,
1275 sizeof (struct user_fpsimd_state), FP_REGS,
1276 aarch64_fill_fpregset, aarch64_store_fpregset
1278 { 0, 0, 0, -1, -1, NULL, NULL }
1281 static struct regsets_info aarch64_regsets_info =
1283 aarch64_regsets, /* regsets */
1284 0, /* num_regsets */
1285 NULL, /* disabled_regsets */
1288 static struct usrregs_info aarch64_usrregs_info =
1294 static struct regs_info regs_info =
1296 NULL, /* regset_bitmap */
1297 &aarch64_usrregs_info,
1298 &aarch64_regsets_info,
1301 static const struct regs_info *
1302 aarch64_regs_info (void)
1307 struct linux_target_ops the_low_target =
1311 aarch64_cannot_fetch_register,
1312 aarch64_cannot_store_register,
1316 (const unsigned char *) &aarch64_breakpoint,
1317 aarch64_breakpoint_len,
1320 aarch64_breakpoint_at,
1321 aarch64_supports_z_point_type,
1322 aarch64_insert_point,
1323 aarch64_remove_point,
1324 aarch64_stopped_by_watchpoint,
1325 aarch64_stopped_data_address,
1329 aarch64_linux_new_process,
1330 aarch64_linux_new_thread,
1331 aarch64_linux_new_fork,
1332 aarch64_linux_prepare_to_resume,
1336 initialize_low_arch (void)
1338 init_registers_aarch64 ();
1340 initialize_regsets_info (&aarch64_regsets_info);