1 /* GNU/Linux/AArch64 specific low level interface, for the remote server for
4 Copyright (C) 2009-2014 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "linux-low.h"
24 #include "elf/common.h"
28 #include <sys/ptrace.h>
31 #include "gdb_proc_service.h"
33 /* Defined in auto-generated files. */
34 void init_registers_aarch64 (void);
35 extern const struct target_desc *tdesc_aarch64;
41 #define AARCH64_X_REGS_NUM 31
42 #define AARCH64_V_REGS_NUM 32
43 #define AARCH64_X0_REGNO 0
44 #define AARCH64_SP_REGNO 31
45 #define AARCH64_PC_REGNO 32
46 #define AARCH64_CPSR_REGNO 33
47 #define AARCH64_V0_REGNO 34
49 #define AARCH64_NUM_REGS (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM)
54 /* These offsets correspond to GET/SETREGSET */
56 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8,
57 8*8, 9*8, 10*8, 11*8, 12*8, 13*8, 14*8, 15*8,
58 16*8, 17*8, 18*8, 19*8, 20*8, 21*8, 22*8, 23*8,
59 24*8, 25*8, 26*8, 27*8, 28*8,
64 33*8, /* cpsr 4 bytes!*/
66 /* FP register offsets correspond to GET/SETFPREGSET */
67 0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16,
68 8*16, 9*16, 10*16, 11*16, 12*16, 13*16, 14*16, 15*16,
69 16*16, 17*16, 18*16, 19*16, 20*16, 21*16, 22*16, 23*16,
70 24*16, 25*16, 26*16, 27*16, 28*16, 29*16, 30*16, 31*16
73 /* Here starts the macro definitions, data structures, and code for
74 the hardware breakpoint and hardware watchpoint support. The
75 following is the abbreviations that are used frequently in the code
82 /* Maximum number of hardware breakpoint and watchpoint registers.
83 Neither of these values may exceed the width of dr_changed_t
86 #define AARCH64_HBP_MAX_NUM 16
87 #define AARCH64_HWP_MAX_NUM 16
89 /* Alignment requirement in bytes of hardware breakpoint and
90 watchpoint address. This is the requirement for the addresses that
91 can be written to the hardware breakpoint/watchpoint value
92 registers. The kernel currently does not do any alignment on
93 addresses when receiving a writing request (via ptrace call) to
94 these debug registers, and it will reject any address that is
96 Some limited support has been provided in this gdbserver port for
97 unaligned watchpoints, so that from a gdb user point of view, an
98 unaligned watchpoint can still be set. This is achieved by
99 minimally enlarging the watched area to meet the alignment
100 requirement, and if necessary, splitting the watchpoint over
101 several hardware watchpoint registers. */
103 #define AARCH64_HBP_ALIGNMENT 4
104 #define AARCH64_HWP_ALIGNMENT 8
106 /* The maximum length of a memory region that can be watched by one
107 hardware watchpoint register. */
109 #define AARCH64_HWP_MAX_LEN_PER_REG 8
111 /* Each bit of a variable of this type is used to indicate whether a
112 hardware breakpoint or watchpoint setting has been changed since
113 the last updating. Bit N corresponds to the Nth hardware
114 breakpoint or watchpoint setting which is managed in
115 aarch64_debug_reg_state. Where N is valid between 0 and the total
116 number of the hardware breakpoint or watchpoint debug registers
117 minus 1. When the bit N is 1, it indicates the corresponding
118 breakpoint or watchpoint setting is changed, and thus the
119 corresponding hardware debug register needs to be updated via the
122 In the per-thread arch-specific data area, we define two such
123 variables for per-thread hardware breakpoint and watchpoint
124 settings respectively.
126 This type is part of the mechanism which helps reduce the number of
127 ptrace calls to the kernel, i.e. avoid asking the kernel to write
128 to the debug registers with unchanged values. */
130 typedef unsigned long long dr_changed_t;
132 /* Set each of the lower M bits of X to 1; assert X is wide enough. */
134 #define DR_MARK_ALL_CHANGED(x, m) \
137 gdb_assert (sizeof ((x)) * 8 >= (m)); \
138 (x) = (((dr_changed_t)1 << (m)) - 1); \
141 #define DR_MARK_N_CHANGED(x, n) \
144 (x) |= ((dr_changed_t)1 << (n)); \
147 #define DR_CLEAR_CHANGED(x) \
153 #define DR_HAS_CHANGED(x) ((x) != 0)
154 #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
156 /* Structure for managing the hardware breakpoint/watchpoint resources.
157 DR_ADDR_* stores the address, DR_CTRL_* stores the control register
158 content, and DR_REF_COUNT_* counts the numbers of references to the
159 corresponding bp/wp, by which way the limited hardware resources
160 are not wasted on duplicated bp/wp settings (though so far gdb has
161 done a good job by not sending duplicated bp/wp requests). */
163 struct aarch64_debug_reg_state
165 /* hardware breakpoint */
166 CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM];
167 unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM];
168 unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM];
170 /* hardware watchpoint */
171 CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM];
172 unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM];
173 unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM];
176 /* Per-process arch-specific data we want to keep. */
178 struct arch_process_info
180 /* Hardware breakpoint/watchpoint data.
181 The reason for them to be per-process rather than per-thread is
182 due to the lack of information in the gdbserver environment;
183 gdbserver is not told that whether a requested hardware
184 breakpoint/watchpoint is thread specific or not, so it has to set
185 each hw bp/wp for every thread in the current process. The
186 higher level bp/wp management in gdb will resume a thread if a hw
187 bp/wp trap is not expected for it. Since the hw bp/wp setting is
188 same for each thread, it is reasonable for the data to live here.
190 struct aarch64_debug_reg_state debug_reg_state;
193 /* Per-thread arch-specific data we want to keep. */
197 /* When bit N is 1, it indicates the Nth hardware breakpoint or
198 watchpoint register pair needs to be updated when the thread is
199 resumed; see aarch64_linux_prepare_to_resume. */
200 dr_changed_t dr_changed_bp;
201 dr_changed_t dr_changed_wp;
204 /* Number of hardware breakpoints/watchpoints the target supports.
205 They are initialized with values obtained via the ptrace calls
206 with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */
208 static int aarch64_num_bp_regs;
209 static int aarch64_num_wp_regs;
212 aarch64_cannot_store_register (int regno)
214 return regno >= AARCH64_NUM_REGS;
218 aarch64_cannot_fetch_register (int regno)
220 return regno >= AARCH64_NUM_REGS;
224 aarch64_fill_gregset (struct regcache *regcache, void *buf)
226 struct user_pt_regs *regset = buf;
229 for (i = 0; i < AARCH64_X_REGS_NUM; i++)
230 collect_register (regcache, AARCH64_X0_REGNO + i, ®set->regs[i]);
231 collect_register (regcache, AARCH64_SP_REGNO, ®set->sp);
232 collect_register (regcache, AARCH64_PC_REGNO, ®set->pc);
233 collect_register (regcache, AARCH64_CPSR_REGNO, ®set->pstate);
237 aarch64_store_gregset (struct regcache *regcache, const void *buf)
239 const struct user_pt_regs *regset = buf;
242 for (i = 0; i < AARCH64_X_REGS_NUM; i++)
243 supply_register (regcache, AARCH64_X0_REGNO + i, ®set->regs[i]);
244 supply_register (regcache, AARCH64_SP_REGNO, ®set->sp);
245 supply_register (regcache, AARCH64_PC_REGNO, ®set->pc);
246 supply_register (regcache, AARCH64_CPSR_REGNO, ®set->pstate);
250 aarch64_fill_fpregset (struct regcache *regcache, void *buf)
252 struct user_fpsimd_state *regset = buf;
255 for (i = 0; i < AARCH64_V_REGS_NUM; i++)
256 collect_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]);
260 aarch64_store_fpregset (struct regcache *regcache, const void *buf)
262 const struct user_fpsimd_state *regset = buf;
265 for (i = 0; i < AARCH64_V_REGS_NUM; i++)
266 supply_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]);
269 /* Debugging of hardware breakpoint/watchpoint support. */
270 extern int debug_hw_points;
272 /* Enable miscellaneous debugging output. The name is historical - it
273 was originally used to debug LinuxThreads support. */
274 extern int debug_threads;
277 aarch64_get_pc (struct regcache *regcache)
281 collect_register_by_name (regcache, "pc", &pc);
283 debug_printf ("stop pc is %08lx\n", pc);
288 aarch64_set_pc (struct regcache *regcache, CORE_ADDR pc)
290 unsigned long newpc = pc;
291 supply_register_by_name (regcache, "pc", &newpc);
294 /* Correct in either endianness. */
296 #define aarch64_breakpoint_len 4
298 static const unsigned long aarch64_breakpoint = 0x00800011;
301 aarch64_breakpoint_at (CORE_ADDR where)
305 (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
306 if (insn == aarch64_breakpoint)
312 /* Print the values of the cached breakpoint/watchpoint registers.
313 This is enabled via the "set debug-hw-points" monitor command. */
316 aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
317 const char *func, CORE_ADDR addr,
318 int len, enum target_hw_bp_type type)
322 fprintf (stderr, "%s", func);
324 fprintf (stderr, " (addr=0x%08lx, len=%d, type=%s)",
325 (unsigned long) addr, len,
326 type == hw_write ? "hw-write-watchpoint"
327 : (type == hw_read ? "hw-read-watchpoint"
328 : (type == hw_access ? "hw-access-watchpoint"
329 : (type == hw_execute ? "hw-breakpoint"
331 fprintf (stderr, ":\n");
333 fprintf (stderr, "\tBREAKPOINTs:\n");
334 for (i = 0; i < aarch64_num_bp_regs; i++)
335 fprintf (stderr, "\tBP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n",
336 i, paddress (state->dr_addr_bp[i]),
337 state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]);
339 fprintf (stderr, "\tWATCHPOINTs:\n");
340 for (i = 0; i < aarch64_num_wp_regs; i++)
341 fprintf (stderr, "\tWP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n",
342 i, paddress (state->dr_addr_wp[i]),
343 state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]);
347 aarch64_init_debug_reg_state (struct aarch64_debug_reg_state *state)
351 for (i = 0; i < AARCH64_HBP_MAX_NUM; ++i)
353 state->dr_addr_bp[i] = 0;
354 state->dr_ctrl_bp[i] = 0;
355 state->dr_ref_count_bp[i] = 0;
358 for (i = 0; i < AARCH64_HWP_MAX_NUM; ++i)
360 state->dr_addr_wp[i] = 0;
361 state->dr_ctrl_wp[i] = 0;
362 state->dr_ref_count_wp[i] = 0;
366 /* ptrace expects control registers to be formatted as follows:
369 +--------------------------------+----------+------+------+----+
370 | RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN |
371 +--------------------------------+----------+------+------+----+
373 The TYPE field is ignored for breakpoints. */
375 #define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1)
376 #define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff)
378 /* Utility function that returns the length in bytes of a watchpoint
379 according to the content of a hardware debug control register CTRL.
380 Note that the kernel currently only supports the following Byte
381 Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
382 that for a hardware watchpoint, its valid length can only be 1
383 byte, 2 bytes, 4 bytes or 8 bytes. */
385 static inline unsigned int
386 aarch64_watchpoint_length (unsigned int ctrl)
388 switch (DR_CONTROL_LENGTH (ctrl))
403 /* Given the hardware breakpoint or watchpoint type TYPE and its
404 length LEN, return the expected encoding for a hardware
405 breakpoint/watchpoint control register. */
408 aarch64_point_encode_ctrl_reg (enum target_hw_bp_type type, int len)
410 unsigned int ctrl, ttype;
428 perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
434 ctrl |= ((1 << len) - 1) << 5;
436 ctrl |= (2 << 1) | 1;
441 /* Addresses to be written to the hardware breakpoint and watchpoint
442 value registers need to be aligned; the alignment is 4-byte and
443 8-type respectively. Linux kernel rejects any non-aligned address
444 it receives from the related ptrace call. Furthermore, the kernel
445 currently only supports the following Byte Address Select (BAS)
446 values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
447 watchpoint to be accepted by the kernel (via ptrace call), its
448 valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
449 Despite these limitations, the unaligned watchpoint is supported in
452 Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */
455 aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len)
457 unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT
458 : AARCH64_HBP_ALIGNMENT;
460 if (addr & (alignment - 1))
463 if (len != 8 && len != 4 && len != 2 && len != 1)
469 /* Given the (potentially unaligned) watchpoint address in ADDR and
470 length in LEN, return the aligned address and aligned length in
471 *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned
472 aligned address and length will be valid to be written to the
473 hardware watchpoint value and control registers. See the comment
474 above aarch64_point_is_aligned for the information about the
475 alignment requirement. The given watchpoint may get truncated if
476 more than one hardware register is needed to cover the watched
477 region. *NEXT_ADDR_P and *NEXT_LEN_P, if non-NULL, will return the
478 address and length of the remaining part of the watchpoint (which
479 can be processed by calling this routine again to generate another
480 aligned address and length pair.
482 Essentially, unaligned watchpoint is achieved by minimally
483 enlarging the watched area to meet the alignment requirement, and
484 if necessary, splitting the watchpoint over several hardware
485 watchpoint registers. The trade-off is that there will be
486 false-positive hits for the read-type or the access-type hardware
487 watchpoints; for the write type, which is more commonly used, there
488 will be no such issues, as the higher-level breakpoint management
489 in gdb always examines the exact watched region for any content
490 change, and transparently resumes a thread from a watchpoint trap
491 if there is no change to the watched region.
493 Another limitation is that because the watched region is enlarged,
494 the watchpoint fault address returned by
495 aarch64_stopped_data_address may be outside of the original watched
496 region, especially when the triggering instruction is accessing a
497 larger region. When the fault address is not within any known
498 range, watchpoints_triggered in gdb will get confused, as the
499 higher-level watchpoint management is only aware of original
500 watched regions, and will think that some unknown watchpoint has
501 been triggered. In such a case, gdb may stop without displaying
502 any detailed information.
504 Once the kernel provides the full support for Byte Address Select
505 (BAS) in the hardware watchpoint control register, these
506 limitations can be largely relaxed with some further work. */
509 aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p,
510 int *aligned_len_p, CORE_ADDR *next_addr_p,
515 CORE_ADDR aligned_addr;
516 const unsigned int alignment = AARCH64_HWP_ALIGNMENT;
517 const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG;
519 /* As assumed by the algorithm. */
520 gdb_assert (alignment == max_wp_len);
525 /* Address to be put into the hardware watchpoint value register
527 offset = addr & (alignment - 1);
528 aligned_addr = addr - offset;
530 gdb_assert (offset >= 0 && offset < alignment);
531 gdb_assert (aligned_addr >= 0 && aligned_addr <= addr);
532 gdb_assert ((offset + len) > 0);
534 if (offset + len >= max_wp_len)
536 /* Need more than one watchpoint registers; truncate it at the
537 alignment boundary. */
538 aligned_len = max_wp_len;
539 len -= (max_wp_len - offset);
540 addr += (max_wp_len - offset);
541 gdb_assert ((addr & (alignment - 1)) == 0);
545 /* Find the smallest valid length that is large enough to
546 accommodate this watchpoint. */
547 static const unsigned char
548 aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] =
549 { 1, 2, 4, 4, 8, 8, 8, 8 };
551 aligned_len = aligned_len_array[offset + len - 1];
556 if (aligned_addr_p != NULL)
557 *aligned_addr_p = aligned_addr;
558 if (aligned_len_p != NULL)
559 *aligned_len_p = aligned_len;
560 if (next_addr_p != NULL)
562 if (next_len_p != NULL)
566 /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
567 registers with data from *STATE. */
570 aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state,
571 int tid, int watchpoint)
575 struct user_hwdebug_state regs;
576 const CORE_ADDR *addr;
577 const unsigned int *ctrl;
579 memset (®s, 0, sizeof (regs));
580 iov.iov_base = ®s;
581 count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs;
582 addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp;
583 ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp;
586 iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs[count - 1])
587 + sizeof (regs.dbg_regs [count - 1]));
589 for (i = 0; i < count; i++)
591 regs.dbg_regs[i].addr = addr[i];
592 regs.dbg_regs[i].ctrl = ctrl[i];
595 if (ptrace (PTRACE_SETREGSET, tid,
596 watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK,
598 error (_("Unexpected error setting hardware debug registers"));
601 struct aarch64_dr_update_callback_param
608 /* Callback function which records the information about the change of
609 one hardware breakpoint/watchpoint setting for the thread ENTRY.
610 The information is passed in via PTR.
611 N.B. The actual updating of hardware debug registers is not
612 carried out until the moment the thread is resumed. */
615 debug_reg_change_callback (struct inferior_list_entry *entry, void *ptr)
617 struct thread_info *thread = (struct thread_info *) entry;
618 struct lwp_info *lwp = get_thread_lwp (thread);
619 struct aarch64_dr_update_callback_param *param_p
620 = (struct aarch64_dr_update_callback_param *) ptr;
621 int pid = param_p->pid;
622 int idx = param_p->idx;
623 int is_watchpoint = param_p->is_watchpoint;
624 struct arch_lwp_info *info = lwp->arch_private;
625 dr_changed_t *dr_changed_ptr;
626 dr_changed_t dr_changed;
630 fprintf (stderr, "debug_reg_change_callback: \n\tOn entry:\n");
631 fprintf (stderr, "\tpid%d, tid: %ld, dr_changed_bp=0x%llx, "
632 "dr_changed_wp=0x%llx\n",
633 pid, lwpid_of (thread), info->dr_changed_bp,
634 info->dr_changed_wp);
637 dr_changed_ptr = is_watchpoint ? &info->dr_changed_wp
638 : &info->dr_changed_bp;
639 dr_changed = *dr_changed_ptr;
641 /* Only update the threads of this process. */
642 if (pid_of (thread) == pid)
645 && (idx <= (is_watchpoint ? aarch64_num_wp_regs
646 : aarch64_num_bp_regs)));
648 /* The following assertion is not right, as there can be changes
649 that have not been made to the hardware debug registers
650 before new changes overwrite the old ones. This can happen,
651 for instance, when the breakpoint/watchpoint hit one of the
652 threads and the user enters continue; then what happens is:
653 1) all breakpoints/watchpoints are removed for all threads;
654 2) a single step is carried out for the thread that was hit;
655 3) all of the points are inserted again for all threads;
656 4) all threads are resumed.
657 The 2nd step will only affect the one thread in which the
658 bp/wp was hit, which means only that one thread is resumed;
659 remember that the actual updating only happen in
660 aarch64_linux_prepare_to_resume, so other threads remain
661 stopped during the removal and insertion of bp/wp. Therefore
662 for those threads, the change of insertion of the bp/wp
663 overwrites that of the earlier removals. (The situation may
664 be different when bp/wp is steppable, or in the non-stop
666 /* gdb_assert (DR_N_HAS_CHANGED (dr_changed, idx) == 0); */
668 /* The actual update is done later just before resuming the lwp,
669 we just mark that one register pair needs updating. */
670 DR_MARK_N_CHANGED (dr_changed, idx);
671 *dr_changed_ptr = dr_changed;
673 /* If the lwp isn't stopped, force it to momentarily pause, so
674 we can update its debug registers. */
676 linux_stop_lwp (lwp);
681 fprintf (stderr, "\tOn exit:\n\tpid%d, tid: %ld, dr_changed_bp=0x%llx, "
682 "dr_changed_wp=0x%llx\n",
683 pid, lwpid_of (thread), info->dr_changed_bp,
684 info->dr_changed_wp);
690 /* Notify each thread that their IDXth breakpoint/watchpoint register
691 pair needs to be updated. The message will be recorded in each
692 thread's arch-specific data area, the actual updating will be done
693 when the thread is resumed. */
696 aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state *state,
697 int is_watchpoint, unsigned int idx)
699 struct aarch64_dr_update_callback_param param;
701 /* Only update the threads of this process. */
702 param.pid = pid_of (current_inferior);
704 param.is_watchpoint = is_watchpoint;
707 find_inferior (&all_threads, debug_reg_change_callback, (void *) ¶m);
711 /* Return the pointer to the debug register state structure in the
712 current process' arch-specific data area. */
714 static struct aarch64_debug_reg_state *
715 aarch64_get_debug_reg_state ()
717 struct process_info *proc;
719 proc = current_process ();
720 return &proc->private->arch_private->debug_reg_state;
723 /* Record the insertion of one breakpoint/watchpoint, as represented
724 by ADDR and CTRL, in the process' arch-specific data area *STATE. */
727 aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state,
728 enum target_hw_bp_type type,
729 CORE_ADDR addr, int len)
731 int i, idx, num_regs, is_watchpoint;
732 unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
733 CORE_ADDR *dr_addr_p;
735 /* Set up state pointers. */
736 is_watchpoint = (type != hw_execute);
737 gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
740 num_regs = aarch64_num_wp_regs;
741 dr_addr_p = state->dr_addr_wp;
742 dr_ctrl_p = state->dr_ctrl_wp;
743 dr_ref_count = state->dr_ref_count_wp;
747 num_regs = aarch64_num_bp_regs;
748 dr_addr_p = state->dr_addr_bp;
749 dr_ctrl_p = state->dr_ctrl_bp;
750 dr_ref_count = state->dr_ref_count_bp;
753 ctrl = aarch64_point_encode_ctrl_reg (type, len);
755 /* Find an existing or free register in our cache. */
757 for (i = 0; i < num_regs; ++i)
759 if ((dr_ctrl_p[i] & 1) == 0)
761 gdb_assert (dr_ref_count[i] == 0);
763 /* no break; continue hunting for an exising one. */
765 else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
767 gdb_assert (dr_ref_count[i] != 0);
777 /* Update our cache. */
778 if ((dr_ctrl_p[idx] & 1) == 0)
781 dr_addr_p[idx] = addr;
782 dr_ctrl_p[idx] = ctrl;
783 dr_ref_count[idx] = 1;
784 /* Notify the change. */
785 aarch64_notify_debug_reg_change (state, is_watchpoint, idx);
796 /* Record the removal of one breakpoint/watchpoint, as represented by
797 ADDR and CTRL, in the process' arch-specific data area *STATE. */
800 aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state,
801 enum target_hw_bp_type type,
802 CORE_ADDR addr, int len)
804 int i, num_regs, is_watchpoint;
805 unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
806 CORE_ADDR *dr_addr_p;
808 /* Set up state pointers. */
809 is_watchpoint = (type != hw_execute);
810 gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
813 num_regs = aarch64_num_wp_regs;
814 dr_addr_p = state->dr_addr_wp;
815 dr_ctrl_p = state->dr_ctrl_wp;
816 dr_ref_count = state->dr_ref_count_wp;
820 num_regs = aarch64_num_bp_regs;
821 dr_addr_p = state->dr_addr_bp;
822 dr_ctrl_p = state->dr_ctrl_bp;
823 dr_ref_count = state->dr_ref_count_bp;
826 ctrl = aarch64_point_encode_ctrl_reg (type, len);
828 /* Find the entry that matches the ADDR and CTRL. */
829 for (i = 0; i < num_regs; ++i)
830 if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
832 gdb_assert (dr_ref_count[i] != 0);
840 /* Clear our cache. */
841 if (--dr_ref_count[i] == 0)
843 /* Clear the enable bit. */
847 /* Notify the change. */
848 aarch64_notify_debug_reg_change (state, is_watchpoint, i);
855 aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr,
856 int len, int is_insert)
858 struct aarch64_debug_reg_state *state;
860 /* The hardware breakpoint on AArch64 should always be 4-byte
862 if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len))
865 state = aarch64_get_debug_reg_state ();
868 return aarch64_dr_state_insert_one_point (state, type, addr, len);
870 return aarch64_dr_state_remove_one_point (state, type, addr, len);
873 /* This is essentially the same as aarch64_handle_breakpoint, apart
874 from that it is an aligned watchpoint to be handled. */
877 aarch64_handle_aligned_watchpoint (enum target_hw_bp_type type,
878 CORE_ADDR addr, int len, int is_insert)
880 struct aarch64_debug_reg_state *state;
882 state = aarch64_get_debug_reg_state ();
885 return aarch64_dr_state_insert_one_point (state, type, addr, len);
887 return aarch64_dr_state_remove_one_point (state, type, addr, len);
890 /* Insert/remove unaligned watchpoint by calling
891 aarch64_align_watchpoint repeatedly until the whole watched region,
892 as represented by ADDR and LEN, has been properly aligned and ready
893 to be written to one or more hardware watchpoint registers.
894 IS_INSERT indicates whether this is an insertion or a deletion.
895 Return 0 if succeed. */
898 aarch64_handle_unaligned_watchpoint (enum target_hw_bp_type type,
899 CORE_ADDR addr, int len, int is_insert)
901 struct aarch64_debug_reg_state *state
902 = aarch64_get_debug_reg_state ();
906 CORE_ADDR aligned_addr;
907 int aligned_len, ret;
909 aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len,
913 ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr,
916 ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr,
921 "handle_unaligned_watchpoint: is_insert: %d\n"
922 " aligned_addr: 0x%s, aligned_len: %d\n"
923 " next_addr: 0x%s, next_len: %d\n",
924 is_insert, paddress (aligned_addr), aligned_len,
925 paddress (addr), len);
935 aarch64_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr,
936 int len, int is_insert)
938 if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len))
939 return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert);
941 return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert);
945 aarch64_supports_z_point_type (char z_type)
950 case Z_PACKET_WRITE_WP:
951 case Z_PACKET_READ_WP:
952 case Z_PACKET_ACCESS_WP:
955 /* Leave the handling of sw breakpoints with the gdb client. */
960 /* Insert a hardware breakpoint/watchpoint.
961 It actually only records the info of the to-be-inserted bp/wp;
962 the actual insertion will happen when threads are resumed.
965 Return 1 if TYPE is unsupported type;
966 Return -1 if an error occurs. */
969 aarch64_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
970 int len, struct raw_breakpoint *bp)
973 enum target_hw_bp_type targ_type;
976 fprintf (stderr, "insert_point on entry (addr=0x%08lx, len=%d)\n",
977 (unsigned long) addr, len);
979 /* Determine the type from the raw breakpoint type. */
980 targ_type = raw_bkpt_type_to_target_hw_bp_type (type);
982 if (targ_type != hw_execute)
984 aarch64_handle_watchpoint (targ_type, addr, len, 1 /* is_insert */);
987 aarch64_handle_breakpoint (targ_type, addr, len, 1 /* is_insert */);
989 if (debug_hw_points > 1)
990 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
991 "insert_point", addr, len, targ_type);
996 /* Remove a hardware breakpoint/watchpoint.
997 It actually only records the info of the to-be-removed bp/wp,
998 the actual removal will be done when threads are resumed.
1000 Return 0 if succeed;
1001 Return 1 if TYPE is an unsupported type;
1002 Return -1 if an error occurs. */
1005 aarch64_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
1006 int len, struct raw_breakpoint *bp)
1009 enum target_hw_bp_type targ_type;
1011 if (debug_hw_points)
1012 fprintf (stderr, "remove_point on entry (addr=0x%08lx, len=%d)\n",
1013 (unsigned long) addr, len);
1015 /* Determine the type from the raw breakpoint type. */
1016 targ_type = raw_bkpt_type_to_target_hw_bp_type (type);
1018 /* Set up state pointers. */
1019 if (targ_type != hw_execute)
1021 aarch64_handle_watchpoint (targ_type, addr, len, 0 /* is_insert */);
1024 aarch64_handle_breakpoint (targ_type, addr, len, 0 /* is_insert */);
1026 if (debug_hw_points > 1)
1027 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
1028 "remove_point", addr, len, targ_type);
1033 /* Returns the address associated with the watchpoint that hit, if
1034 any; returns 0 otherwise. */
1037 aarch64_stopped_data_address (void)
1041 struct aarch64_debug_reg_state *state;
1043 pid = lwpid_of (current_inferior);
1045 /* Get the siginfo. */
1046 if (ptrace (PTRACE_GETSIGINFO, pid, NULL, &siginfo) != 0)
1047 return (CORE_ADDR) 0;
1049 /* Need to be a hardware breakpoint/watchpoint trap. */
1050 if (siginfo.si_signo != SIGTRAP
1051 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
1052 return (CORE_ADDR) 0;
1054 /* Check if the address matches any watched address. */
1055 state = aarch64_get_debug_reg_state ();
1056 for (i = aarch64_num_wp_regs - 1; i >= 0; --i)
1058 const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]);
1059 const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr;
1060 const CORE_ADDR addr_watch = state->dr_addr_wp[i];
1061 if (state->dr_ref_count_wp[i]
1062 && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i])
1063 && addr_trap >= addr_watch
1064 && addr_trap < addr_watch + len)
1068 return (CORE_ADDR) 0;
1071 /* Returns 1 if target was stopped due to a watchpoint hit, 0
1075 aarch64_stopped_by_watchpoint (void)
1077 if (aarch64_stopped_data_address () != 0)
1083 /* Fetch the thread-local storage pointer for libthread_db. */
1086 ps_get_thread_area (const struct ps_prochandle *ph,
1087 lwpid_t lwpid, int idx, void **base)
1092 iovec.iov_base = ®
1093 iovec.iov_len = sizeof (reg);
1095 if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0)
1098 /* IDX is the bias from the thread pointer to the beginning of the
1099 thread descriptor. It has to be subtracted due to implementation
1100 quirks in libthread_db. */
1101 *base = (void *) (reg - idx);
1106 /* Called when a new process is created. */
1108 static struct arch_process_info *
1109 aarch64_linux_new_process (void)
1111 struct arch_process_info *info = xcalloc (1, sizeof (*info));
1113 aarch64_init_debug_reg_state (&info->debug_reg_state);
1118 /* Called when a new thread is detected. */
1120 static struct arch_lwp_info *
1121 aarch64_linux_new_thread (void)
1123 struct arch_lwp_info *info = xcalloc (1, sizeof (*info));
1125 /* Mark that all the hardware breakpoint/watchpoint register pairs
1126 for this thread need to be initialized (with data from
1127 aarch_process_info.debug_reg_state). */
1128 DR_MARK_ALL_CHANGED (info->dr_changed_bp, aarch64_num_bp_regs);
1129 DR_MARK_ALL_CHANGED (info->dr_changed_wp, aarch64_num_wp_regs);
1134 /* Called when resuming a thread.
1135 If the debug regs have changed, update the thread's copies. */
1138 aarch64_linux_prepare_to_resume (struct lwp_info *lwp)
1140 struct thread_info *thread = get_lwp_thread (lwp);
1141 ptid_t ptid = ptid_of (thread);
1142 struct arch_lwp_info *info = lwp->arch_private;
1144 if (DR_HAS_CHANGED (info->dr_changed_bp)
1145 || DR_HAS_CHANGED (info->dr_changed_wp))
1147 int tid = ptid_get_lwp (ptid);
1148 struct process_info *proc = find_process_pid (ptid_get_pid (ptid));
1149 struct aarch64_debug_reg_state *state
1150 = &proc->private->arch_private->debug_reg_state;
1152 if (debug_hw_points)
1153 fprintf (stderr, "prepare_to_resume thread %ld\n", lwpid_of (thread));
1156 if (DR_HAS_CHANGED (info->dr_changed_wp))
1158 aarch64_linux_set_debug_regs (state, tid, 1);
1159 DR_CLEAR_CHANGED (info->dr_changed_wp);
1163 if (DR_HAS_CHANGED (info->dr_changed_bp))
1165 aarch64_linux_set_debug_regs (state, tid, 0);
1166 DR_CLEAR_CHANGED (info->dr_changed_bp);
1171 /* ptrace hardware breakpoint resource info is formatted as follows:
1174 +---------------+--------------+---------------+---------------+
1175 | RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS |
1176 +---------------+--------------+---------------+---------------+ */
1178 #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
1179 #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
1180 #define AARCH64_DEBUG_ARCH_V8 0x6
1183 aarch64_arch_setup (void)
1187 struct user_hwdebug_state dreg_state;
1189 current_process ()->tdesc = tdesc_aarch64;
1191 pid = lwpid_of (current_inferior);
1192 iov.iov_base = &dreg_state;
1193 iov.iov_len = sizeof (dreg_state);
1195 /* Get hardware watchpoint register info. */
1196 if (ptrace (PTRACE_GETREGSET, pid, NT_ARM_HW_WATCH, &iov) == 0
1197 && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
1199 aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
1200 if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM)
1202 warning ("Unexpected number of hardware watchpoint registers reported"
1203 " by ptrace, got %d, expected %d.",
1204 aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM);
1205 aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM;
1210 warning ("Unable to determine the number of hardware watchpoints"
1212 aarch64_num_wp_regs = 0;
1215 /* Get hardware breakpoint register info. */
1216 if (ptrace (PTRACE_GETREGSET, pid, NT_ARM_HW_BREAK, &iov) == 0
1217 && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
1219 aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
1220 if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM)
1222 warning ("Unexpected number of hardware breakpoint registers reported"
1223 " by ptrace, got %d, expected %d.",
1224 aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM);
1225 aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM;
1230 warning ("Unable to determine the number of hardware breakpoints"
1232 aarch64_num_bp_regs = 0;
1236 static struct regset_info aarch64_regsets[] =
1238 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS,
1239 sizeof (struct user_pt_regs), GENERAL_REGS,
1240 aarch64_fill_gregset, aarch64_store_gregset },
1241 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET,
1242 sizeof (struct user_fpsimd_state), FP_REGS,
1243 aarch64_fill_fpregset, aarch64_store_fpregset
1245 { 0, 0, 0, -1, -1, NULL, NULL }
1248 static struct regsets_info aarch64_regsets_info =
1250 aarch64_regsets, /* regsets */
1251 0, /* num_regsets */
1252 NULL, /* disabled_regsets */
1255 static struct usrregs_info aarch64_usrregs_info =
1261 static struct regs_info regs_info =
1263 NULL, /* regset_bitmap */
1264 &aarch64_usrregs_info,
1265 &aarch64_regsets_info,
1268 static const struct regs_info *
1269 aarch64_regs_info (void)
1274 struct linux_target_ops the_low_target =
1278 aarch64_cannot_fetch_register,
1279 aarch64_cannot_store_register,
1283 (const unsigned char *) &aarch64_breakpoint,
1284 aarch64_breakpoint_len,
1287 aarch64_breakpoint_at,
1288 aarch64_supports_z_point_type,
1289 aarch64_insert_point,
1290 aarch64_remove_point,
1291 aarch64_stopped_by_watchpoint,
1292 aarch64_stopped_data_address,
1296 aarch64_linux_new_process,
1297 aarch64_linux_new_thread,
1298 aarch64_linux_prepare_to_resume,
1302 initialize_low_arch (void)
1304 init_registers_aarch64 ();
1306 initialize_regsets_info (&aarch64_regsets_info);