1 /* GNU/Linux/AArch64 specific low level interface, for the remote server for
4 Copyright (C) 2009-2015 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "linux-low.h"
24 #include "nat/aarch64-linux.h"
25 #include "nat/aarch64-linux-hw-point.h"
26 #include "arch/aarch64-insn.h"
27 #include "linux-aarch32-low.h"
28 #include "elf/common.h"
30 #include "tracepoint.h"
34 #include "nat/gdb_ptrace.h"
35 #include <asm/ptrace.h>
40 #include "gdb_proc_service.h"
42 /* Defined in auto-generated files. */
43 void init_registers_aarch64 (void);
44 extern const struct target_desc *tdesc_aarch64;
50 #define AARCH64_X_REGS_NUM 31
51 #define AARCH64_V_REGS_NUM 32
52 #define AARCH64_X0_REGNO 0
53 #define AARCH64_SP_REGNO 31
54 #define AARCH64_PC_REGNO 32
55 #define AARCH64_CPSR_REGNO 33
56 #define AARCH64_V0_REGNO 34
57 #define AARCH64_FPSR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM)
58 #define AARCH64_FPCR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 1)
60 #define AARCH64_NUM_REGS (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 2)
62 /* Per-process arch-specific data we want to keep. */
64 struct arch_process_info
66 /* Hardware breakpoint/watchpoint data.
67 The reason for them to be per-process rather than per-thread is
68 due to the lack of information in the gdbserver environment;
69 gdbserver is not told that whether a requested hardware
70 breakpoint/watchpoint is thread specific or not, so it has to set
71 each hw bp/wp for every thread in the current process. The
72 higher level bp/wp management in gdb will resume a thread if a hw
73 bp/wp trap is not expected for it. Since the hw bp/wp setting is
74 same for each thread, it is reasonable for the data to live here.
76 struct aarch64_debug_reg_state debug_reg_state;
79 /* Return true if the size of register 0 is 8 byte. */
84 struct regcache *regcache = get_thread_regcache (current_thread, 0);
86 return register_size (regcache->tdesc, 0) == 8;
89 /* Implementation of linux_target_ops method "cannot_store_register". */
92 aarch64_cannot_store_register (int regno)
94 return regno >= AARCH64_NUM_REGS;
97 /* Implementation of linux_target_ops method "cannot_fetch_register". */
100 aarch64_cannot_fetch_register (int regno)
102 return regno >= AARCH64_NUM_REGS;
106 aarch64_fill_gregset (struct regcache *regcache, void *buf)
108 struct user_pt_regs *regset = buf;
111 for (i = 0; i < AARCH64_X_REGS_NUM; i++)
112 collect_register (regcache, AARCH64_X0_REGNO + i, ®set->regs[i]);
113 collect_register (regcache, AARCH64_SP_REGNO, ®set->sp);
114 collect_register (regcache, AARCH64_PC_REGNO, ®set->pc);
115 collect_register (regcache, AARCH64_CPSR_REGNO, ®set->pstate);
119 aarch64_store_gregset (struct regcache *regcache, const void *buf)
121 const struct user_pt_regs *regset = buf;
124 for (i = 0; i < AARCH64_X_REGS_NUM; i++)
125 supply_register (regcache, AARCH64_X0_REGNO + i, ®set->regs[i]);
126 supply_register (regcache, AARCH64_SP_REGNO, ®set->sp);
127 supply_register (regcache, AARCH64_PC_REGNO, ®set->pc);
128 supply_register (regcache, AARCH64_CPSR_REGNO, ®set->pstate);
132 aarch64_fill_fpregset (struct regcache *regcache, void *buf)
134 struct user_fpsimd_state *regset = buf;
137 for (i = 0; i < AARCH64_V_REGS_NUM; i++)
138 collect_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]);
139 collect_register (regcache, AARCH64_FPSR_REGNO, ®set->fpsr);
140 collect_register (regcache, AARCH64_FPCR_REGNO, ®set->fpcr);
144 aarch64_store_fpregset (struct regcache *regcache, const void *buf)
146 const struct user_fpsimd_state *regset = buf;
149 for (i = 0; i < AARCH64_V_REGS_NUM; i++)
150 supply_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]);
151 supply_register (regcache, AARCH64_FPSR_REGNO, ®set->fpsr);
152 supply_register (regcache, AARCH64_FPCR_REGNO, ®set->fpcr);
155 /* Enable miscellaneous debugging output. The name is historical - it
156 was originally used to debug LinuxThreads support. */
157 extern int debug_threads;
159 /* Implementation of linux_target_ops method "get_pc". */
162 aarch64_get_pc (struct regcache *regcache)
164 if (register_size (regcache->tdesc, 0) == 8)
168 collect_register_by_name (regcache, "pc", &pc);
170 debug_printf ("stop pc is %08lx\n", pc);
177 collect_register_by_name (regcache, "pc", &pc);
179 debug_printf ("stop pc is %04x\n", pc);
184 /* Implementation of linux_target_ops method "set_pc". */
187 aarch64_set_pc (struct regcache *regcache, CORE_ADDR pc)
189 if (register_size (regcache->tdesc, 0) == 8)
191 unsigned long newpc = pc;
192 supply_register_by_name (regcache, "pc", &newpc);
196 unsigned int newpc = pc;
197 supply_register_by_name (regcache, "pc", &newpc);
201 #define aarch64_breakpoint_len 4
203 /* AArch64 BRK software debug mode instruction.
204 This instruction needs to match gdb/aarch64-tdep.c
205 (aarch64_default_breakpoint). */
206 static const gdb_byte aarch64_breakpoint[] = {0x00, 0x00, 0x20, 0xd4};
208 /* Implementation of linux_target_ops method "breakpoint_at". */
211 aarch64_breakpoint_at (CORE_ADDR where)
213 gdb_byte insn[aarch64_breakpoint_len];
215 (*the_target->read_memory) (where, (unsigned char *) &insn,
216 aarch64_breakpoint_len);
217 if (memcmp (insn, aarch64_breakpoint, aarch64_breakpoint_len) == 0)
224 aarch64_init_debug_reg_state (struct aarch64_debug_reg_state *state)
228 for (i = 0; i < AARCH64_HBP_MAX_NUM; ++i)
230 state->dr_addr_bp[i] = 0;
231 state->dr_ctrl_bp[i] = 0;
232 state->dr_ref_count_bp[i] = 0;
235 for (i = 0; i < AARCH64_HWP_MAX_NUM; ++i)
237 state->dr_addr_wp[i] = 0;
238 state->dr_ctrl_wp[i] = 0;
239 state->dr_ref_count_wp[i] = 0;
243 /* Return the pointer to the debug register state structure in the
244 current process' arch-specific data area. */
246 struct aarch64_debug_reg_state *
247 aarch64_get_debug_reg_state (pid_t pid)
249 struct process_info *proc = find_process_pid (pid);
251 return &proc->priv->arch_private->debug_reg_state;
254 /* Implementation of linux_target_ops method "supports_z_point_type". */
257 aarch64_supports_z_point_type (char z_type)
263 if (!extended_protocol && is_64bit_tdesc ())
265 /* Only enable Z0 packet in non-multi-arch debugging. If
266 extended protocol is used, don't enable Z0 packet because
267 GDBserver may attach to 32-bit process. */
272 /* Disable Z0 packet so that GDBserver doesn't have to handle
273 different breakpoint instructions (aarch64, arm, thumb etc)
274 in multi-arch debugging. */
279 case Z_PACKET_WRITE_WP:
280 case Z_PACKET_READ_WP:
281 case Z_PACKET_ACCESS_WP:
288 /* Implementation of linux_target_ops method "insert_point".
290 It actually only records the info of the to-be-inserted bp/wp;
291 the actual insertion will happen when threads are resumed. */
294 aarch64_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
295 int len, struct raw_breakpoint *bp)
298 enum target_hw_bp_type targ_type;
299 struct aarch64_debug_reg_state *state
300 = aarch64_get_debug_reg_state (pid_of (current_thread));
303 fprintf (stderr, "insert_point on entry (addr=0x%08lx, len=%d)\n",
304 (unsigned long) addr, len);
306 /* Determine the type from the raw breakpoint type. */
307 targ_type = raw_bkpt_type_to_target_hw_bp_type (type);
309 if (targ_type != hw_execute)
311 if (aarch64_linux_region_ok_for_watchpoint (addr, len))
312 ret = aarch64_handle_watchpoint (targ_type, addr, len,
313 1 /* is_insert */, state);
321 /* LEN is 3 means the breakpoint is set on a 32-bit thumb
322 instruction. Set it to 2 to correctly encode length bit
323 mask in hardware/watchpoint control register. */
326 ret = aarch64_handle_breakpoint (targ_type, addr, len,
327 1 /* is_insert */, state);
331 aarch64_show_debug_reg_state (state, "insert_point", addr, len,
337 /* Implementation of linux_target_ops method "remove_point".
339 It actually only records the info of the to-be-removed bp/wp,
340 the actual removal will be done when threads are resumed. */
343 aarch64_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
344 int len, struct raw_breakpoint *bp)
347 enum target_hw_bp_type targ_type;
348 struct aarch64_debug_reg_state *state
349 = aarch64_get_debug_reg_state (pid_of (current_thread));
352 fprintf (stderr, "remove_point on entry (addr=0x%08lx, len=%d)\n",
353 (unsigned long) addr, len);
355 /* Determine the type from the raw breakpoint type. */
356 targ_type = raw_bkpt_type_to_target_hw_bp_type (type);
358 /* Set up state pointers. */
359 if (targ_type != hw_execute)
361 aarch64_handle_watchpoint (targ_type, addr, len, 0 /* is_insert */,
367 /* LEN is 3 means the breakpoint is set on a 32-bit thumb
368 instruction. Set it to 2 to correctly encode length bit
369 mask in hardware/watchpoint control register. */
372 ret = aarch64_handle_breakpoint (targ_type, addr, len,
373 0 /* is_insert */, state);
377 aarch64_show_debug_reg_state (state, "remove_point", addr, len,
383 /* Implementation of linux_target_ops method "stopped_data_address". */
386 aarch64_stopped_data_address (void)
390 struct aarch64_debug_reg_state *state;
392 pid = lwpid_of (current_thread);
394 /* Get the siginfo. */
395 if (ptrace (PTRACE_GETSIGINFO, pid, NULL, &siginfo) != 0)
396 return (CORE_ADDR) 0;
398 /* Need to be a hardware breakpoint/watchpoint trap. */
399 if (siginfo.si_signo != SIGTRAP
400 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
401 return (CORE_ADDR) 0;
403 /* Check if the address matches any watched address. */
404 state = aarch64_get_debug_reg_state (pid_of (current_thread));
405 for (i = aarch64_num_wp_regs - 1; i >= 0; --i)
407 const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]);
408 const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr;
409 const CORE_ADDR addr_watch = state->dr_addr_wp[i];
410 if (state->dr_ref_count_wp[i]
411 && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i])
412 && addr_trap >= addr_watch
413 && addr_trap < addr_watch + len)
417 return (CORE_ADDR) 0;
420 /* Implementation of linux_target_ops method "stopped_by_watchpoint". */
423 aarch64_stopped_by_watchpoint (void)
425 if (aarch64_stopped_data_address () != 0)
431 /* Fetch the thread-local storage pointer for libthread_db. */
434 ps_get_thread_area (const struct ps_prochandle *ph,
435 lwpid_t lwpid, int idx, void **base)
437 return aarch64_ps_get_thread_area (ph, lwpid, idx, base,
441 /* Implementation of linux_target_ops method "siginfo_fixup". */
444 aarch64_linux_siginfo_fixup (siginfo_t *native, void *inf, int direction)
446 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
447 if (!is_64bit_tdesc ())
450 aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo *) inf,
453 aarch64_siginfo_from_compat_siginfo (native,
454 (struct compat_siginfo *) inf);
462 /* Implementation of linux_target_ops method "linux_new_process". */
464 static struct arch_process_info *
465 aarch64_linux_new_process (void)
467 struct arch_process_info *info = XCNEW (struct arch_process_info);
469 aarch64_init_debug_reg_state (&info->debug_reg_state);
474 /* Implementation of linux_target_ops method "linux_new_fork". */
477 aarch64_linux_new_fork (struct process_info *parent,
478 struct process_info *child)
480 /* These are allocated by linux_add_process. */
481 gdb_assert (parent->priv != NULL
482 && parent->priv->arch_private != NULL);
483 gdb_assert (child->priv != NULL
484 && child->priv->arch_private != NULL);
486 /* Linux kernel before 2.6.33 commit
487 72f674d203cd230426437cdcf7dd6f681dad8b0d
488 will inherit hardware debug registers from parent
489 on fork/vfork/clone. Newer Linux kernels create such tasks with
490 zeroed debug registers.
492 GDB core assumes the child inherits the watchpoints/hw
493 breakpoints of the parent, and will remove them all from the
494 forked off process. Copy the debug registers mirrors into the
495 new process so that all breakpoints and watchpoints can be
496 removed together. The debug registers mirror will become zeroed
497 in the end before detaching the forked off process, thus making
498 this compatible with older Linux kernels too. */
500 *child->priv->arch_private = *parent->priv->arch_private;
503 /* Return the right target description according to the ELF file of
506 static const struct target_desc *
507 aarch64_linux_read_description (void)
509 unsigned int machine;
513 tid = lwpid_of (current_thread);
515 is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine);
518 return tdesc_aarch64;
520 return tdesc_arm_with_neon;
523 /* Implementation of linux_target_ops method "arch_setup". */
526 aarch64_arch_setup (void)
528 current_process ()->tdesc = aarch64_linux_read_description ();
530 aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread));
533 static struct regset_info aarch64_regsets[] =
535 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS,
536 sizeof (struct user_pt_regs), GENERAL_REGS,
537 aarch64_fill_gregset, aarch64_store_gregset },
538 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET,
539 sizeof (struct user_fpsimd_state), FP_REGS,
540 aarch64_fill_fpregset, aarch64_store_fpregset
545 static struct regsets_info aarch64_regsets_info =
547 aarch64_regsets, /* regsets */
549 NULL, /* disabled_regsets */
552 static struct regs_info regs_info_aarch64 =
554 NULL, /* regset_bitmap */
556 &aarch64_regsets_info,
559 /* Implementation of linux_target_ops method "regs_info". */
561 static const struct regs_info *
562 aarch64_regs_info (void)
564 if (is_64bit_tdesc ())
565 return ®s_info_aarch64;
567 return ®s_info_aarch32;
570 /* Implementation of linux_target_ops method "supports_tracepoints". */
573 aarch64_supports_tracepoints (void)
575 if (current_thread == NULL)
579 /* We don't support tracepoints on aarch32 now. */
580 return is_64bit_tdesc ();
584 /* Implementation of linux_target_ops method "get_thread_area". */
587 aarch64_get_thread_area (int lwpid, CORE_ADDR *addrp)
592 iovec.iov_base = ®
593 iovec.iov_len = sizeof (reg);
595 if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0)
603 /* List of condition codes that we need. */
605 enum aarch64_condition_codes
616 /* Representation of an operand. At this time, it only supports register
617 and immediate types. */
619 struct aarch64_operand
621 /* Type of the operand. */
627 /* Value of the operand according to the type. */
631 struct aarch64_register reg;
635 /* List of registers that we are currently using, we can add more here as
636 we need to use them. */
638 /* General purpose scratch registers (64 bit). */
639 static const struct aarch64_register x0 = { 0, 1 };
640 static const struct aarch64_register x1 = { 1, 1 };
641 static const struct aarch64_register x2 = { 2, 1 };
642 static const struct aarch64_register x3 = { 3, 1 };
643 static const struct aarch64_register x4 = { 4, 1 };
645 /* General purpose scratch registers (32 bit). */
646 static const struct aarch64_register w0 = { 0, 0 };
647 static const struct aarch64_register w2 = { 2, 0 };
649 /* Intra-procedure scratch registers. */
650 static const struct aarch64_register ip0 = { 16, 1 };
652 /* Special purpose registers. */
653 static const struct aarch64_register fp = { 29, 1 };
654 static const struct aarch64_register lr = { 30, 1 };
655 static const struct aarch64_register sp = { 31, 1 };
656 static const struct aarch64_register xzr = { 31, 1 };
658 /* Dynamically allocate a new register. If we know the register
659 statically, we should make it a global as above instead of using this
662 static struct aarch64_register
663 aarch64_register (unsigned num, int is64)
665 return (struct aarch64_register) { num, is64 };
668 /* Helper function to create a register operand, for instructions with
669 different types of operands.
672 p += emit_mov (p, x0, register_operand (x1)); */
674 static struct aarch64_operand
675 register_operand (struct aarch64_register reg)
677 struct aarch64_operand operand;
679 operand.type = OPERAND_REGISTER;
685 /* Helper function to create an immediate operand, for instructions with
686 different types of operands.
689 p += emit_mov (p, x0, immediate_operand (12)); */
691 static struct aarch64_operand
692 immediate_operand (uint32_t imm)
694 struct aarch64_operand operand;
696 operand.type = OPERAND_IMMEDIATE;
702 /* Helper function to create an offset memory operand.
705 p += emit_ldr (p, x0, sp, offset_memory_operand (16)); */
707 static struct aarch64_memory_operand
708 offset_memory_operand (int32_t offset)
710 return (struct aarch64_memory_operand) { MEMORY_OPERAND_OFFSET, offset };
713 /* Helper function to create a pre-index memory operand.
716 p += emit_ldr (p, x0, sp, preindex_memory_operand (16)); */
718 static struct aarch64_memory_operand
719 preindex_memory_operand (int32_t index)
721 return (struct aarch64_memory_operand) { MEMORY_OPERAND_PREINDEX, index };
724 /* Helper function to create a post-index memory operand.
727 p += emit_ldr (p, x0, sp, postindex_memory_operand (16)); */
729 static struct aarch64_memory_operand
730 postindex_memory_operand (int32_t index)
732 return (struct aarch64_memory_operand) { MEMORY_OPERAND_POSTINDEX, index };
735 /* System control registers. These special registers can be written and
736 read with the MRS and MSR instructions.
738 - NZCV: Condition flags. GDB refers to this register under the CPSR
740 - FPSR: Floating-point status register.
741 - FPCR: Floating-point control registers.
742 - TPIDR_EL0: Software thread ID register. */
744 enum aarch64_system_control_registers
746 /* op0 op1 crn crm op2 */
747 NZCV = (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x2 << 3) | 0x0,
748 FPSR = (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x1,
749 FPCR = (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x0,
750 TPIDR_EL0 = (0x1 << 14) | (0x3 << 11) | (0xd << 7) | (0x0 << 3) | 0x2
753 /* Write a BLR instruction into *BUF.
757 RN is the register to branch to. */
760 emit_blr (uint32_t *buf, struct aarch64_register rn)
762 return aarch64_emit_insn (buf, BLR | ENCODE (rn.num, 5, 5));
765 /* Write a RET instruction into *BUF.
769 RN is the register to branch to. */
772 emit_ret (uint32_t *buf, struct aarch64_register rn)
774 return aarch64_emit_insn (buf, RET | ENCODE (rn.num, 5, 5));
778 emit_load_store_pair (uint32_t *buf, enum aarch64_opcodes opcode,
779 struct aarch64_register rt,
780 struct aarch64_register rt2,
781 struct aarch64_register rn,
782 struct aarch64_memory_operand operand)
789 opc = ENCODE (2, 2, 30);
791 opc = ENCODE (0, 2, 30);
793 switch (operand.type)
795 case MEMORY_OPERAND_OFFSET:
797 pre_index = ENCODE (1, 1, 24);
798 write_back = ENCODE (0, 1, 23);
801 case MEMORY_OPERAND_POSTINDEX:
803 pre_index = ENCODE (0, 1, 24);
804 write_back = ENCODE (1, 1, 23);
807 case MEMORY_OPERAND_PREINDEX:
809 pre_index = ENCODE (1, 1, 24);
810 write_back = ENCODE (1, 1, 23);
817 return aarch64_emit_insn (buf, opcode | opc | pre_index | write_back
818 | ENCODE (operand.index >> 3, 7, 15)
819 | ENCODE (rt2.num, 5, 10)
820 | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0));
823 /* Write a STP instruction into *BUF.
825 STP rt, rt2, [rn, #offset]
826 STP rt, rt2, [rn, #index]!
827 STP rt, rt2, [rn], #index
829 RT and RT2 are the registers to store.
830 RN is the base address register.
831 OFFSET is the immediate to add to the base address. It is limited to a
832 -512 .. 504 range (7 bits << 3). */
835 emit_stp (uint32_t *buf, struct aarch64_register rt,
836 struct aarch64_register rt2, struct aarch64_register rn,
837 struct aarch64_memory_operand operand)
839 return emit_load_store_pair (buf, STP, rt, rt2, rn, operand);
842 /* Write a LDP instruction into *BUF.
844 LDP rt, rt2, [rn, #offset]
845 LDP rt, rt2, [rn, #index]!
846 LDP rt, rt2, [rn], #index
848 RT and RT2 are the registers to store.
849 RN is the base address register.
850 OFFSET is the immediate to add to the base address. It is limited to a
851 -512 .. 504 range (7 bits << 3). */
854 emit_ldp (uint32_t *buf, struct aarch64_register rt,
855 struct aarch64_register rt2, struct aarch64_register rn,
856 struct aarch64_memory_operand operand)
858 return emit_load_store_pair (buf, LDP, rt, rt2, rn, operand);
861 /* Write a LDP (SIMD&VFP) instruction using Q registers into *BUF.
863 LDP qt, qt2, [rn, #offset]
865 RT and RT2 are the Q registers to store.
866 RN is the base address register.
867 OFFSET is the immediate to add to the base address. It is limited to
868 -1024 .. 1008 range (7 bits << 4). */
871 emit_ldp_q_offset (uint32_t *buf, unsigned rt, unsigned rt2,
872 struct aarch64_register rn, int32_t offset)
874 uint32_t opc = ENCODE (2, 2, 30);
875 uint32_t pre_index = ENCODE (1, 1, 24);
877 return aarch64_emit_insn (buf, LDP_SIMD_VFP | opc | pre_index
878 | ENCODE (offset >> 4, 7, 15)
879 | ENCODE (rt2, 5, 10)
880 | ENCODE (rn.num, 5, 5) | ENCODE (rt, 5, 0));
883 /* Write a STP (SIMD&VFP) instruction using Q registers into *BUF.
885 STP qt, qt2, [rn, #offset]
887 RT and RT2 are the Q registers to store.
888 RN is the base address register.
889 OFFSET is the immediate to add to the base address. It is limited to
890 -1024 .. 1008 range (7 bits << 4). */
893 emit_stp_q_offset (uint32_t *buf, unsigned rt, unsigned rt2,
894 struct aarch64_register rn, int32_t offset)
896 uint32_t opc = ENCODE (2, 2, 30);
897 uint32_t pre_index = ENCODE (1, 1, 24);
899 return aarch64_emit_insn (buf, STP_SIMD_VFP | opc | pre_index
900 | ENCODE (offset >> 4, 7, 15)
901 | ENCODE (rt2, 5, 10)
902 | ENCODE (rn.num, 5, 5) | ENCODE (rt, 5, 0));
905 /* Write a LDRH instruction into *BUF.
907 LDRH wt, [xn, #offset]
908 LDRH wt, [xn, #index]!
909 LDRH wt, [xn], #index
911 RT is the register to store.
912 RN is the base address register.
913 OFFSET is the immediate to add to the base address. It is limited to
914 0 .. 32760 range (12 bits << 3). */
917 emit_ldrh (uint32_t *buf, struct aarch64_register rt,
918 struct aarch64_register rn,
919 struct aarch64_memory_operand operand)
921 return aarch64_emit_load_store (buf, 1, LDR, rt, rn, operand);
924 /* Write a LDRB instruction into *BUF.
926 LDRB wt, [xn, #offset]
927 LDRB wt, [xn, #index]!
928 LDRB wt, [xn], #index
930 RT is the register to store.
931 RN is the base address register.
932 OFFSET is the immediate to add to the base address. It is limited to
933 0 .. 32760 range (12 bits << 3). */
936 emit_ldrb (uint32_t *buf, struct aarch64_register rt,
937 struct aarch64_register rn,
938 struct aarch64_memory_operand operand)
940 return aarch64_emit_load_store (buf, 0, LDR, rt, rn, operand);
945 /* Write a STR instruction into *BUF.
947 STR rt, [rn, #offset]
948 STR rt, [rn, #index]!
951 RT is the register to store.
952 RN is the base address register.
953 OFFSET is the immediate to add to the base address. It is limited to
954 0 .. 32760 range (12 bits << 3). */
957 emit_str (uint32_t *buf, struct aarch64_register rt,
958 struct aarch64_register rn,
959 struct aarch64_memory_operand operand)
961 return aarch64_emit_load_store (buf, rt.is64 ? 3 : 2, STR, rt, rn, operand);
964 /* Helper function emitting an exclusive load or store instruction. */
967 emit_load_store_exclusive (uint32_t *buf, uint32_t size,
968 enum aarch64_opcodes opcode,
969 struct aarch64_register rs,
970 struct aarch64_register rt,
971 struct aarch64_register rt2,
972 struct aarch64_register rn)
974 return aarch64_emit_insn (buf, opcode | ENCODE (size, 2, 30)
975 | ENCODE (rs.num, 5, 16) | ENCODE (rt2.num, 5, 10)
976 | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0));
979 /* Write a LAXR instruction into *BUF.
983 RT is the destination register.
984 RN is the base address register. */
987 emit_ldaxr (uint32_t *buf, struct aarch64_register rt,
988 struct aarch64_register rn)
990 return emit_load_store_exclusive (buf, rt.is64 ? 3 : 2, LDAXR, xzr, rt,
994 /* Write a STXR instruction into *BUF.
998 RS is the result register, it indicates if the store succeeded or not.
999 RT is the destination register.
1000 RN is the base address register. */
1003 emit_stxr (uint32_t *buf, struct aarch64_register rs,
1004 struct aarch64_register rt, struct aarch64_register rn)
1006 return emit_load_store_exclusive (buf, rt.is64 ? 3 : 2, STXR, rs, rt,
1010 /* Write a STLR instruction into *BUF.
1014 RT is the register to store.
1015 RN is the base address register. */
1018 emit_stlr (uint32_t *buf, struct aarch64_register rt,
1019 struct aarch64_register rn)
1021 return emit_load_store_exclusive (buf, rt.is64 ? 3 : 2, STLR, xzr, rt,
1025 /* Helper function for data processing instructions with register sources. */
1028 emit_data_processing_reg (uint32_t *buf, enum aarch64_opcodes opcode,
1029 struct aarch64_register rd,
1030 struct aarch64_register rn,
1031 struct aarch64_register rm)
1033 uint32_t size = ENCODE (rd.is64, 1, 31);
1035 return aarch64_emit_insn (buf, opcode | size | ENCODE (rm.num, 5, 16)
1036 | ENCODE (rn.num, 5, 5) | ENCODE (rd.num, 5, 0));
1039 /* Helper function for data processing instructions taking either a register
1043 emit_data_processing (uint32_t *buf, enum aarch64_opcodes opcode,
1044 struct aarch64_register rd,
1045 struct aarch64_register rn,
1046 struct aarch64_operand operand)
1048 uint32_t size = ENCODE (rd.is64, 1, 31);
1049 /* The opcode is different for register and immediate source operands. */
1050 uint32_t operand_opcode;
1052 if (operand.type == OPERAND_IMMEDIATE)
1054 /* xxx1 000x xxxx xxxx xxxx xxxx xxxx xxxx */
1055 operand_opcode = ENCODE (8, 4, 25);
1057 return aarch64_emit_insn (buf, opcode | operand_opcode | size
1058 | ENCODE (operand.imm, 12, 10)
1059 | ENCODE (rn.num, 5, 5)
1060 | ENCODE (rd.num, 5, 0));
1064 /* xxx0 101x xxxx xxxx xxxx xxxx xxxx xxxx */
1065 operand_opcode = ENCODE (5, 4, 25);
1067 return emit_data_processing_reg (buf, opcode | operand_opcode, rd,
1072 /* Write an ADD instruction into *BUF.
1077 This function handles both an immediate and register add.
1079 RD is the destination register.
1080 RN is the input register.
1081 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
1082 OPERAND_REGISTER. */
1085 emit_add (uint32_t *buf, struct aarch64_register rd,
1086 struct aarch64_register rn, struct aarch64_operand operand)
1088 return emit_data_processing (buf, ADD, rd, rn, operand);
1091 /* Write a SUB instruction into *BUF.
1096 This function handles both an immediate and register sub.
1098 RD is the destination register.
1099 RN is the input register.
1100 IMM is the immediate to substract to RN. */
1103 emit_sub (uint32_t *buf, struct aarch64_register rd,
1104 struct aarch64_register rn, struct aarch64_operand operand)
1106 return emit_data_processing (buf, SUB, rd, rn, operand);
1109 /* Write a MOV instruction into *BUF.
1114 This function handles both a wide immediate move and a register move,
1115 with the condition that the source register is not xzr. xzr and the
1116 stack pointer share the same encoding and this function only supports
1119 RD is the destination register.
1120 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
1121 OPERAND_REGISTER. */
1124 emit_mov (uint32_t *buf, struct aarch64_register rd,
1125 struct aarch64_operand operand)
1127 if (operand.type == OPERAND_IMMEDIATE)
1129 uint32_t size = ENCODE (rd.is64, 1, 31);
1130 /* Do not shift the immediate. */
1131 uint32_t shift = ENCODE (0, 2, 21);
1133 return aarch64_emit_insn (buf, MOV | size | shift
1134 | ENCODE (operand.imm, 16, 5)
1135 | ENCODE (rd.num, 5, 0));
1138 return emit_add (buf, rd, operand.reg, immediate_operand (0));
1141 /* Write a MOVK instruction into *BUF.
1143 MOVK rd, #imm, lsl #shift
1145 RD is the destination register.
1146 IMM is the immediate.
1147 SHIFT is the logical shift left to apply to IMM. */
1150 emit_movk (uint32_t *buf, struct aarch64_register rd, uint32_t imm,
1153 uint32_t size = ENCODE (rd.is64, 1, 31);
1155 return aarch64_emit_insn (buf, MOVK | size | ENCODE (shift, 2, 21) |
1156 ENCODE (imm, 16, 5) | ENCODE (rd.num, 5, 0));
1159 /* Write instructions into *BUF in order to move ADDR into a register.
1160 ADDR can be a 64-bit value.
1162 This function will emit a series of MOV and MOVK instructions, such as:
1165 MOVK xd, #(addr >> 16), lsl #16
1166 MOVK xd, #(addr >> 32), lsl #32
1167 MOVK xd, #(addr >> 48), lsl #48 */
1170 emit_mov_addr (uint32_t *buf, struct aarch64_register rd, CORE_ADDR addr)
1174 /* The MOV (wide immediate) instruction clears to top bits of the
1176 p += emit_mov (p, rd, immediate_operand (addr & 0xffff));
1178 if ((addr >> 16) != 0)
1179 p += emit_movk (p, rd, (addr >> 16) & 0xffff, 1);
1183 if ((addr >> 32) != 0)
1184 p += emit_movk (p, rd, (addr >> 32) & 0xffff, 2);
1188 if ((addr >> 48) != 0)
1189 p += emit_movk (p, rd, (addr >> 48) & 0xffff, 3);
1194 /* Write a SUBS instruction into *BUF.
1198 This instruction update the condition flags.
1200 RD is the destination register.
1201 RN and RM are the source registers. */
1204 emit_subs (uint32_t *buf, struct aarch64_register rd,
1205 struct aarch64_register rn, struct aarch64_operand operand)
1207 return emit_data_processing (buf, SUBS, rd, rn, operand);
1210 /* Write a CMP instruction into *BUF.
1214 This instruction is an alias of SUBS xzr, rn, rm.
1216 RN and RM are the registers to compare. */
1219 emit_cmp (uint32_t *buf, struct aarch64_register rn,
1220 struct aarch64_operand operand)
1222 return emit_subs (buf, xzr, rn, operand);
1225 /* Write a AND instruction into *BUF.
1229 RD is the destination register.
1230 RN and RM are the source registers. */
1233 emit_and (uint32_t *buf, struct aarch64_register rd,
1234 struct aarch64_register rn, struct aarch64_register rm)
1236 return emit_data_processing_reg (buf, AND, rd, rn, rm);
1239 /* Write a ORR instruction into *BUF.
1243 RD is the destination register.
1244 RN and RM are the source registers. */
1247 emit_orr (uint32_t *buf, struct aarch64_register rd,
1248 struct aarch64_register rn, struct aarch64_register rm)
1250 return emit_data_processing_reg (buf, ORR, rd, rn, rm);
1253 /* Write a ORN instruction into *BUF.
1257 RD is the destination register.
1258 RN and RM are the source registers. */
1261 emit_orn (uint32_t *buf, struct aarch64_register rd,
1262 struct aarch64_register rn, struct aarch64_register rm)
1264 return emit_data_processing_reg (buf, ORN, rd, rn, rm);
1267 /* Write a EOR instruction into *BUF.
1271 RD is the destination register.
1272 RN and RM are the source registers. */
1275 emit_eor (uint32_t *buf, struct aarch64_register rd,
1276 struct aarch64_register rn, struct aarch64_register rm)
1278 return emit_data_processing_reg (buf, EOR, rd, rn, rm);
1281 /* Write a MVN instruction into *BUF.
1285 This is an alias for ORN rd, xzr, rm.
1287 RD is the destination register.
1288 RM is the source register. */
1291 emit_mvn (uint32_t *buf, struct aarch64_register rd,
1292 struct aarch64_register rm)
1294 return emit_orn (buf, rd, xzr, rm);
1297 /* Write a LSLV instruction into *BUF.
1301 RD is the destination register.
1302 RN and RM are the source registers. */
1305 emit_lslv (uint32_t *buf, struct aarch64_register rd,
1306 struct aarch64_register rn, struct aarch64_register rm)
1308 return emit_data_processing_reg (buf, LSLV, rd, rn, rm);
1311 /* Write a LSRV instruction into *BUF.
1315 RD is the destination register.
1316 RN and RM are the source registers. */
1319 emit_lsrv (uint32_t *buf, struct aarch64_register rd,
1320 struct aarch64_register rn, struct aarch64_register rm)
1322 return emit_data_processing_reg (buf, LSRV, rd, rn, rm);
1325 /* Write a ASRV instruction into *BUF.
1329 RD is the destination register.
1330 RN and RM are the source registers. */
1333 emit_asrv (uint32_t *buf, struct aarch64_register rd,
1334 struct aarch64_register rn, struct aarch64_register rm)
1336 return emit_data_processing_reg (buf, ASRV, rd, rn, rm);
1339 /* Write a MUL instruction into *BUF.
1343 RD is the destination register.
1344 RN and RM are the source registers. */
1347 emit_mul (uint32_t *buf, struct aarch64_register rd,
1348 struct aarch64_register rn, struct aarch64_register rm)
1350 return emit_data_processing_reg (buf, MUL, rd, rn, rm);
1353 /* Write a MRS instruction into *BUF. The register size is 64-bit.
1357 RT is the destination register.
1358 SYSTEM_REG is special purpose register to read. */
1361 emit_mrs (uint32_t *buf, struct aarch64_register rt,
1362 enum aarch64_system_control_registers system_reg)
1364 return aarch64_emit_insn (buf, MRS | ENCODE (system_reg, 15, 5)
1365 | ENCODE (rt.num, 5, 0));
1368 /* Write a MSR instruction into *BUF. The register size is 64-bit.
1372 SYSTEM_REG is special purpose register to write.
1373 RT is the input register. */
1376 emit_msr (uint32_t *buf, enum aarch64_system_control_registers system_reg,
1377 struct aarch64_register rt)
1379 return aarch64_emit_insn (buf, MSR | ENCODE (system_reg, 15, 5)
1380 | ENCODE (rt.num, 5, 0));
1383 /* Write a SEVL instruction into *BUF.
1385 This is a hint instruction telling the hardware to trigger an event. */
1388 emit_sevl (uint32_t *buf)
1390 return aarch64_emit_insn (buf, SEVL);
1393 /* Write a WFE instruction into *BUF.
1395 This is a hint instruction telling the hardware to wait for an event. */
1398 emit_wfe (uint32_t *buf)
1400 return aarch64_emit_insn (buf, WFE);
1403 /* Write a SBFM instruction into *BUF.
1405 SBFM rd, rn, #immr, #imms
1407 This instruction moves the bits from #immr to #imms into the
1408 destination, sign extending the result.
1410 RD is the destination register.
1411 RN is the source register.
1412 IMMR is the bit number to start at (least significant bit).
1413 IMMS is the bit number to stop at (most significant bit). */
1416 emit_sbfm (uint32_t *buf, struct aarch64_register rd,
1417 struct aarch64_register rn, uint32_t immr, uint32_t imms)
1419 uint32_t size = ENCODE (rd.is64, 1, 31);
1420 uint32_t n = ENCODE (rd.is64, 1, 22);
1422 return aarch64_emit_insn (buf, SBFM | size | n | ENCODE (immr, 6, 16)
1423 | ENCODE (imms, 6, 10) | ENCODE (rn.num, 5, 5)
1424 | ENCODE (rd.num, 5, 0));
1427 /* Write a SBFX instruction into *BUF.
1429 SBFX rd, rn, #lsb, #width
1431 This instruction moves #width bits from #lsb into the destination, sign
1432 extending the result. This is an alias for:
1434 SBFM rd, rn, #lsb, #(lsb + width - 1)
1436 RD is the destination register.
1437 RN is the source register.
1438 LSB is the bit number to start at (least significant bit).
1439 WIDTH is the number of bits to move. */
1442 emit_sbfx (uint32_t *buf, struct aarch64_register rd,
1443 struct aarch64_register rn, uint32_t lsb, uint32_t width)
1445 return emit_sbfm (buf, rd, rn, lsb, lsb + width - 1);
1448 /* Write a UBFM instruction into *BUF.
1450 UBFM rd, rn, #immr, #imms
1452 This instruction moves the bits from #immr to #imms into the
1453 destination, extending the result with zeros.
1455 RD is the destination register.
1456 RN is the source register.
1457 IMMR is the bit number to start at (least significant bit).
1458 IMMS is the bit number to stop at (most significant bit). */
1461 emit_ubfm (uint32_t *buf, struct aarch64_register rd,
1462 struct aarch64_register rn, uint32_t immr, uint32_t imms)
1464 uint32_t size = ENCODE (rd.is64, 1, 31);
1465 uint32_t n = ENCODE (rd.is64, 1, 22);
1467 return aarch64_emit_insn (buf, UBFM | size | n | ENCODE (immr, 6, 16)
1468 | ENCODE (imms, 6, 10) | ENCODE (rn.num, 5, 5)
1469 | ENCODE (rd.num, 5, 0));
1472 /* Write a UBFX instruction into *BUF.
1474 UBFX rd, rn, #lsb, #width
1476 This instruction moves #width bits from #lsb into the destination,
1477 extending the result with zeros. This is an alias for:
1479 UBFM rd, rn, #lsb, #(lsb + width - 1)
1481 RD is the destination register.
1482 RN is the source register.
1483 LSB is the bit number to start at (least significant bit).
1484 WIDTH is the number of bits to move. */
1487 emit_ubfx (uint32_t *buf, struct aarch64_register rd,
1488 struct aarch64_register rn, uint32_t lsb, uint32_t width)
1490 return emit_ubfm (buf, rd, rn, lsb, lsb + width - 1);
1493 /* Write a CSINC instruction into *BUF.
1495 CSINC rd, rn, rm, cond
1497 This instruction conditionally increments rn or rm and places the result
1498 in rd. rn is chosen is the condition is true.
1500 RD is the destination register.
1501 RN and RM are the source registers.
1502 COND is the encoded condition. */
1505 emit_csinc (uint32_t *buf, struct aarch64_register rd,
1506 struct aarch64_register rn, struct aarch64_register rm,
1509 uint32_t size = ENCODE (rd.is64, 1, 31);
1511 return aarch64_emit_insn (buf, CSINC | size | ENCODE (rm.num, 5, 16)
1512 | ENCODE (cond, 4, 12) | ENCODE (rn.num, 5, 5)
1513 | ENCODE (rd.num, 5, 0));
1516 /* Write a CSET instruction into *BUF.
1520 This instruction conditionally write 1 or 0 in the destination register.
1521 1 is written if the condition is true. This is an alias for:
1523 CSINC rd, xzr, xzr, !cond
1525 Note that the condition needs to be inverted.
1527 RD is the destination register.
1528 RN and RM are the source registers.
1529 COND is the encoded condition. */
1532 emit_cset (uint32_t *buf, struct aarch64_register rd, unsigned cond)
1534 /* The least significant bit of the condition needs toggling in order to
1536 return emit_csinc (buf, rd, xzr, xzr, cond ^ 0x1);
1539 /* Write LEN instructions from BUF into the inferior memory at *TO.
1541 Note instructions are always little endian on AArch64, unlike data. */
1544 append_insns (CORE_ADDR *to, size_t len, const uint32_t *buf)
1546 size_t byte_len = len * sizeof (uint32_t);
1547 #if (__BYTE_ORDER == __BIG_ENDIAN)
1548 uint32_t *le_buf = xmalloc (byte_len);
1551 for (i = 0; i < len; i++)
1552 le_buf[i] = htole32 (buf[i]);
1554 write_inferior_memory (*to, (const unsigned char *) le_buf, byte_len);
1558 write_inferior_memory (*to, (const unsigned char *) buf, byte_len);
1564 /* Sub-class of struct aarch64_insn_data, store information of
1565 instruction relocation for fast tracepoint. Visitor can
1566 relocate an instruction from BASE.INSN_ADDR to NEW_ADDR and save
1567 the relocated instructions in buffer pointed by INSN_PTR. */
1569 struct aarch64_insn_relocation_data
1571 struct aarch64_insn_data base;
1573 /* The new address the instruction is relocated to. */
1575 /* Pointer to the buffer of relocated instruction(s). */
1579 /* Implementation of aarch64_insn_visitor method "b". */
1582 aarch64_ftrace_insn_reloc_b (const int is_bl, const int32_t offset,
1583 struct aarch64_insn_data *data)
1585 struct aarch64_insn_relocation_data *insn_reloc
1586 = (struct aarch64_insn_relocation_data *) data;
1588 = insn_reloc->base.insn_addr - insn_reloc->new_addr + offset;
1590 if (can_encode_int32 (new_offset, 28))
1591 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, is_bl, new_offset);
1594 /* Implementation of aarch64_insn_visitor method "b_cond". */
1597 aarch64_ftrace_insn_reloc_b_cond (const unsigned cond, const int32_t offset,
1598 struct aarch64_insn_data *data)
1600 struct aarch64_insn_relocation_data *insn_reloc
1601 = (struct aarch64_insn_relocation_data *) data;
1603 = insn_reloc->base.insn_addr - insn_reloc->new_addr + offset;
1605 if (can_encode_int32 (new_offset, 21))
1607 insn_reloc->insn_ptr += emit_bcond (insn_reloc->insn_ptr, cond,
1610 else if (can_encode_int32 (new_offset, 28))
1612 /* The offset is out of range for a conditional branch
1613 instruction but not for a unconditional branch. We can use
1614 the following instructions instead:
1616 B.COND TAKEN ; If cond is true, then jump to TAKEN.
1617 B NOT_TAKEN ; Else jump over TAKEN and continue.
1624 insn_reloc->insn_ptr += emit_bcond (insn_reloc->insn_ptr, cond, 8);
1625 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0, 8);
1626 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0, new_offset - 8);
1630 /* Implementation of aarch64_insn_visitor method "cb". */
1633 aarch64_ftrace_insn_reloc_cb (const int32_t offset, const int is_cbnz,
1634 const unsigned rn, int is64,
1635 struct aarch64_insn_data *data)
1637 struct aarch64_insn_relocation_data *insn_reloc
1638 = (struct aarch64_insn_relocation_data *) data;
1640 = insn_reloc->base.insn_addr - insn_reloc->new_addr + offset;
1642 if (can_encode_int32 (new_offset, 21))
1644 insn_reloc->insn_ptr += emit_cb (insn_reloc->insn_ptr, is_cbnz,
1645 aarch64_register (rn, is64), new_offset);
1647 else if (can_encode_int32 (new_offset, 28))
1649 /* The offset is out of range for a compare and branch
1650 instruction but not for a unconditional branch. We can use
1651 the following instructions instead:
1653 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
1654 B NOT_TAKEN ; Else jump over TAKEN and continue.
1660 insn_reloc->insn_ptr += emit_cb (insn_reloc->insn_ptr, is_cbnz,
1661 aarch64_register (rn, is64), 8);
1662 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0, 8);
1663 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0, new_offset - 8);
1667 /* Implementation of aarch64_insn_visitor method "tb". */
1670 aarch64_ftrace_insn_reloc_tb (const int32_t offset, int is_tbnz,
1671 const unsigned rt, unsigned bit,
1672 struct aarch64_insn_data *data)
1674 struct aarch64_insn_relocation_data *insn_reloc
1675 = (struct aarch64_insn_relocation_data *) data;
1677 = insn_reloc->base.insn_addr - insn_reloc->new_addr + offset;
1679 if (can_encode_int32 (new_offset, 16))
1681 insn_reloc->insn_ptr += emit_tb (insn_reloc->insn_ptr, is_tbnz, bit,
1682 aarch64_register (rt, 1), new_offset);
1684 else if (can_encode_int32 (new_offset, 28))
1686 /* The offset is out of range for a test bit and branch
1687 instruction but not for a unconditional branch. We can use
1688 the following instructions instead:
1690 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
1691 B NOT_TAKEN ; Else jump over TAKEN and continue.
1697 insn_reloc->insn_ptr += emit_tb (insn_reloc->insn_ptr, is_tbnz, bit,
1698 aarch64_register (rt, 1), 8);
1699 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0, 8);
1700 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0,
1705 /* Implementation of aarch64_insn_visitor method "adr". */
1708 aarch64_ftrace_insn_reloc_adr (const int32_t offset, const unsigned rd,
1710 struct aarch64_insn_data *data)
1712 struct aarch64_insn_relocation_data *insn_reloc
1713 = (struct aarch64_insn_relocation_data *) data;
1714 /* We know exactly the address the ADR{P,} instruction will compute.
1715 We can just write it to the destination register. */
1716 CORE_ADDR address = data->insn_addr + offset;
1720 /* Clear the lower 12 bits of the offset to get the 4K page. */
1721 insn_reloc->insn_ptr += emit_mov_addr (insn_reloc->insn_ptr,
1722 aarch64_register (rd, 1),
1726 insn_reloc->insn_ptr += emit_mov_addr (insn_reloc->insn_ptr,
1727 aarch64_register (rd, 1), address);
1730 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
1733 aarch64_ftrace_insn_reloc_ldr_literal (const int32_t offset, const int is_sw,
1734 const unsigned rt, const int is64,
1735 struct aarch64_insn_data *data)
1737 struct aarch64_insn_relocation_data *insn_reloc
1738 = (struct aarch64_insn_relocation_data *) data;
1739 CORE_ADDR address = data->insn_addr + offset;
1741 insn_reloc->insn_ptr += emit_mov_addr (insn_reloc->insn_ptr,
1742 aarch64_register (rt, 1), address);
1744 /* We know exactly what address to load from, and what register we
1747 MOV xd, #(oldloc + offset)
1748 MOVK xd, #((oldloc + offset) >> 16), lsl #16
1751 LDR xd, [xd] ; or LDRSW xd, [xd]
1756 insn_reloc->insn_ptr += emit_ldrsw (insn_reloc->insn_ptr,
1757 aarch64_register (rt, 1),
1758 aarch64_register (rt, 1),
1759 offset_memory_operand (0));
1761 insn_reloc->insn_ptr += emit_ldr (insn_reloc->insn_ptr,
1762 aarch64_register (rt, is64),
1763 aarch64_register (rt, 1),
1764 offset_memory_operand (0));
1767 /* Implementation of aarch64_insn_visitor method "others". */
1770 aarch64_ftrace_insn_reloc_others (const uint32_t insn,
1771 struct aarch64_insn_data *data)
1773 struct aarch64_insn_relocation_data *insn_reloc
1774 = (struct aarch64_insn_relocation_data *) data;
1776 /* The instruction is not PC relative. Just re-emit it at the new
1778 insn_reloc->insn_ptr += aarch64_emit_insn (insn_reloc->insn_ptr, insn);
1781 static const struct aarch64_insn_visitor visitor =
1783 aarch64_ftrace_insn_reloc_b,
1784 aarch64_ftrace_insn_reloc_b_cond,
1785 aarch64_ftrace_insn_reloc_cb,
1786 aarch64_ftrace_insn_reloc_tb,
1787 aarch64_ftrace_insn_reloc_adr,
1788 aarch64_ftrace_insn_reloc_ldr_literal,
1789 aarch64_ftrace_insn_reloc_others,
1792 /* Implementation of linux_target_ops method
1793 "install_fast_tracepoint_jump_pad". */
1796 aarch64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint,
1798 CORE_ADDR collector,
1801 CORE_ADDR *jump_entry,
1802 CORE_ADDR *trampoline,
1803 ULONGEST *trampoline_size,
1804 unsigned char *jjump_pad_insn,
1805 ULONGEST *jjump_pad_insn_size,
1806 CORE_ADDR *adjusted_insn_addr,
1807 CORE_ADDR *adjusted_insn_addr_end,
1815 CORE_ADDR buildaddr = *jump_entry;
1816 struct aarch64_insn_relocation_data insn_data;
1818 /* We need to save the current state on the stack both to restore it
1819 later and to collect register values when the tracepoint is hit.
1821 The saved registers are pushed in a layout that needs to be in sync
1822 with aarch64_ft_collect_regmap (see linux-aarch64-ipa.c). Later on
1823 the supply_fast_tracepoint_registers function will fill in the
1824 register cache from a pointer to saved registers on the stack we build
1827 For simplicity, we set the size of each cell on the stack to 16 bytes.
1828 This way one cell can hold any register type, from system registers
1829 to the 128 bit SIMD&FP registers. Furthermore, the stack pointer
1830 has to be 16 bytes aligned anyway.
1832 Note that the CPSR register does not exist on AArch64. Instead we
1833 can access system bits describing the process state with the
1834 MRS/MSR instructions, namely the condition flags. We save them as
1835 if they are part of a CPSR register because that's how GDB
1836 interprets these system bits. At the moment, only the condition
1837 flags are saved in CPSR (NZCV).
1839 Stack layout, each cell is 16 bytes (descending):
1841 High *-------- SIMD&FP registers from 31 down to 0. --------*
1847 *---- General purpose registers from 30 down to 0. ----*
1853 *------------- Special purpose registers. -------------*
1856 | CPSR (NZCV) | 5 cells
1859 *------------- collecting_t object --------------------*
1860 | TPIDR_EL0 | struct tracepoint * |
1861 Low *------------------------------------------------------*
1863 After this stack is set up, we issue a call to the collector, passing
1864 it the saved registers at (SP + 16). */
1866 /* Push SIMD&FP registers on the stack:
1868 SUB sp, sp, #(32 * 16)
1870 STP q30, q31, [sp, #(30 * 16)]
1875 p += emit_sub (p, sp, sp, immediate_operand (32 * 16));
1876 for (i = 30; i >= 0; i -= 2)
1877 p += emit_stp_q_offset (p, i, i + 1, sp, i * 16);
1879 /* Push general puspose registers on the stack. Note that we do not need
1880 to push x31 as it represents the xzr register and not the stack
1881 pointer in a STR instruction.
1883 SUB sp, sp, #(31 * 16)
1885 STR x30, [sp, #(30 * 16)]
1890 p += emit_sub (p, sp, sp, immediate_operand (31 * 16));
1891 for (i = 30; i >= 0; i -= 1)
1892 p += emit_str (p, aarch64_register (i, 1), sp,
1893 offset_memory_operand (i * 16));
1895 /* Make space for 5 more cells.
1897 SUB sp, sp, #(5 * 16)
1900 p += emit_sub (p, sp, sp, immediate_operand (5 * 16));
1905 ADD x4, sp, #((32 + 31 + 5) * 16)
1906 STR x4, [sp, #(4 * 16)]
1909 p += emit_add (p, x4, sp, immediate_operand ((32 + 31 + 5) * 16));
1910 p += emit_str (p, x4, sp, offset_memory_operand (4 * 16));
1912 /* Save PC (tracepoint address):
1917 STR x3, [sp, #(3 * 16)]
1921 p += emit_mov_addr (p, x3, tpaddr);
1922 p += emit_str (p, x3, sp, offset_memory_operand (3 * 16));
1924 /* Save CPSR (NZCV), FPSR and FPCR:
1930 STR x2, [sp, #(2 * 16)]
1931 STR x1, [sp, #(1 * 16)]
1932 STR x0, [sp, #(0 * 16)]
1935 p += emit_mrs (p, x2, NZCV);
1936 p += emit_mrs (p, x1, FPSR);
1937 p += emit_mrs (p, x0, FPCR);
1938 p += emit_str (p, x2, sp, offset_memory_operand (2 * 16));
1939 p += emit_str (p, x1, sp, offset_memory_operand (1 * 16));
1940 p += emit_str (p, x0, sp, offset_memory_operand (0 * 16));
1942 /* Push the collecting_t object. It consist of the address of the
1943 tracepoint and an ID for the current thread. We get the latter by
1944 reading the tpidr_el0 system register. It corresponds to the
1945 NT_ARM_TLS register accessible with ptrace.
1952 STP x0, x1, [sp, #-16]!
1956 p += emit_mov_addr (p, x0, tpoint);
1957 p += emit_mrs (p, x1, TPIDR_EL0);
1958 p += emit_stp (p, x0, x1, sp, preindex_memory_operand (-16));
1962 The shared memory for the lock is at lockaddr. It will hold zero
1963 if no-one is holding the lock, otherwise it contains the address of
1964 the collecting_t object on the stack of the thread which acquired it.
1966 At this stage, the stack pointer points to this thread's collecting_t
1969 We use the following registers:
1970 - x0: Address of the lock.
1971 - x1: Pointer to collecting_t object.
1972 - x2: Scratch register.
1978 ; Trigger an event local to this core. So the following WFE
1979 ; instruction is ignored.
1982 ; Wait for an event. The event is triggered by either the SEVL
1983 ; or STLR instructions (store release).
1986 ; Atomically read at lockaddr. This marks the memory location as
1987 ; exclusive. This instruction also has memory constraints which
1988 ; make sure all previous data reads and writes are done before
1992 ; Try again if another thread holds the lock.
1995 ; We can lock it! Write the address of the collecting_t object.
1996 ; This instruction will fail if the memory location is not marked
1997 ; as exclusive anymore. If it succeeds, it will remove the
1998 ; exclusive mark on the memory location. This way, if another
1999 ; thread executes this instruction before us, we will fail and try
2006 p += emit_mov_addr (p, x0, lockaddr);
2007 p += emit_mov (p, x1, register_operand (sp));
2011 p += emit_ldaxr (p, x2, x0);
2012 p += emit_cb (p, 1, w2, -2 * 4);
2013 p += emit_stxr (p, w2, x1, x0);
2014 p += emit_cb (p, 1, x2, -4 * 4);
2016 /* Call collector (struct tracepoint *, unsigned char *):
2021 ; Saved registers start after the collecting_t object.
2024 ; We use an intra-procedure-call scratch register.
2025 MOV ip0, #(collector)
2028 ; And call back to C!
2033 p += emit_mov_addr (p, x0, tpoint);
2034 p += emit_add (p, x1, sp, immediate_operand (16));
2036 p += emit_mov_addr (p, ip0, collector);
2037 p += emit_blr (p, ip0);
2039 /* Release the lock.
2044 ; This instruction is a normal store with memory ordering
2045 ; constraints. Thanks to this we do not have to put a data
2046 ; barrier instruction to make sure all data read and writes are done
2047 ; before this instruction is executed. Furthermore, this instrucion
2048 ; will trigger an event, letting other threads know they can grab
2053 p += emit_mov_addr (p, x0, lockaddr);
2054 p += emit_stlr (p, xzr, x0);
2056 /* Free collecting_t object:
2061 p += emit_add (p, sp, sp, immediate_operand (16));
2063 /* Restore CPSR (NZCV), FPSR and FPCR. And free all special purpose
2064 registers from the stack.
2066 LDR x2, [sp, #(2 * 16)]
2067 LDR x1, [sp, #(1 * 16)]
2068 LDR x0, [sp, #(0 * 16)]
2074 ADD sp, sp #(5 * 16)
2077 p += emit_ldr (p, x2, sp, offset_memory_operand (2 * 16));
2078 p += emit_ldr (p, x1, sp, offset_memory_operand (1 * 16));
2079 p += emit_ldr (p, x0, sp, offset_memory_operand (0 * 16));
2080 p += emit_msr (p, NZCV, x2);
2081 p += emit_msr (p, FPSR, x1);
2082 p += emit_msr (p, FPCR, x0);
2084 p += emit_add (p, sp, sp, immediate_operand (5 * 16));
2086 /* Pop general purpose registers:
2090 LDR x30, [sp, #(30 * 16)]
2092 ADD sp, sp, #(31 * 16)
2095 for (i = 0; i <= 30; i += 1)
2096 p += emit_ldr (p, aarch64_register (i, 1), sp,
2097 offset_memory_operand (i * 16));
2098 p += emit_add (p, sp, sp, immediate_operand (31 * 16));
2100 /* Pop SIMD&FP registers:
2104 LDP q30, q31, [sp, #(30 * 16)]
2106 ADD sp, sp, #(32 * 16)
2109 for (i = 0; i <= 30; i += 2)
2110 p += emit_ldp_q_offset (p, i, i + 1, sp, i * 16);
2111 p += emit_add (p, sp, sp, immediate_operand (32 * 16));
2113 /* Write the code into the inferior memory. */
2114 append_insns (&buildaddr, p - buf, buf);
2116 /* Now emit the relocated instruction. */
2117 *adjusted_insn_addr = buildaddr;
2118 target_read_uint32 (tpaddr, &insn);
2120 insn_data.base.insn_addr = tpaddr;
2121 insn_data.new_addr = buildaddr;
2122 insn_data.insn_ptr = buf;
2124 aarch64_relocate_instruction (insn, &visitor,
2125 (struct aarch64_insn_data *) &insn_data);
2127 /* We may not have been able to relocate the instruction. */
2128 if (insn_data.insn_ptr == buf)
2131 "E.Could not relocate instruction from %s to %s.",
2132 core_addr_to_string_nz (tpaddr),
2133 core_addr_to_string_nz (buildaddr));
2137 append_insns (&buildaddr, insn_data.insn_ptr - buf, buf);
2138 *adjusted_insn_addr_end = buildaddr;
2140 /* Go back to the start of the buffer. */
2143 /* Emit a branch back from the jump pad. */
2144 offset = (tpaddr + orig_size - buildaddr);
2145 if (!can_encode_int32 (offset, 28))
2148 "E.Jump back from jump pad too far from tracepoint "
2149 "(offset 0x%" PRIx32 " cannot be encoded in 28 bits).",
2154 p += emit_b (p, 0, offset);
2155 append_insns (&buildaddr, p - buf, buf);
2157 /* Give the caller a branch instruction into the jump pad. */
2158 offset = (*jump_entry - tpaddr);
2159 if (!can_encode_int32 (offset, 28))
2162 "E.Jump pad too far from tracepoint "
2163 "(offset 0x%" PRIx32 " cannot be encoded in 28 bits).",
2168 emit_b ((uint32_t *) jjump_pad_insn, 0, offset);
2169 *jjump_pad_insn_size = 4;
2171 /* Return the end address of our pad. */
2172 *jump_entry = buildaddr;
2177 /* Helper function writing LEN instructions from START into
2178 current_insn_ptr. */
2181 emit_ops_insns (const uint32_t *start, int len)
2183 CORE_ADDR buildaddr = current_insn_ptr;
2186 debug_printf ("Adding %d instrucions at %s\n",
2187 len, paddress (buildaddr));
2189 append_insns (&buildaddr, len, start);
2190 current_insn_ptr = buildaddr;
2193 /* Pop a register from the stack. */
2196 emit_pop (uint32_t *buf, struct aarch64_register rt)
2198 return emit_ldr (buf, rt, sp, postindex_memory_operand (1 * 16));
2201 /* Push a register on the stack. */
2204 emit_push (uint32_t *buf, struct aarch64_register rt)
2206 return emit_str (buf, rt, sp, preindex_memory_operand (-1 * 16));
2209 /* Implementation of emit_ops method "emit_prologue". */
2212 aarch64_emit_prologue (void)
2217 /* This function emit a prologue for the following function prototype:
2219 enum eval_result_type f (unsigned char *regs,
2222 The first argument is a buffer of raw registers. The second
2223 argument is the result of
2224 evaluating the expression, which will be set to whatever is on top of
2225 the stack at the end.
2227 The stack set up by the prologue is as such:
2229 High *------------------------------------------------------*
2232 | x1 (ULONGEST *value) |
2233 | x0 (unsigned char *regs) |
2234 Low *------------------------------------------------------*
2236 As we are implementing a stack machine, each opcode can expand the
2237 stack so we never know how far we are from the data saved by this
2238 prologue. In order to be able refer to value and regs later, we save
2239 the current stack pointer in the frame pointer. This way, it is not
2240 clobbered when calling C functions.
2242 Finally, throughtout every operation, we are using register x0 as the
2243 top of the stack, and x1 as a scratch register. */
2245 p += emit_stp (p, x0, x1, sp, preindex_memory_operand (-2 * 16));
2246 p += emit_str (p, lr, sp, offset_memory_operand (3 * 8));
2247 p += emit_str (p, fp, sp, offset_memory_operand (2 * 8));
2249 p += emit_add (p, fp, sp, immediate_operand (2 * 8));
2252 emit_ops_insns (buf, p - buf);
2255 /* Implementation of emit_ops method "emit_epilogue". */
2258 aarch64_emit_epilogue (void)
2263 /* Store the result of the expression (x0) in *value. */
2264 p += emit_sub (p, x1, fp, immediate_operand (1 * 8));
2265 p += emit_ldr (p, x1, x1, offset_memory_operand (0));
2266 p += emit_str (p, x0, x1, offset_memory_operand (0));
2268 /* Restore the previous state. */
2269 p += emit_add (p, sp, fp, immediate_operand (2 * 8));
2270 p += emit_ldp (p, fp, lr, fp, offset_memory_operand (0));
2272 /* Return expr_eval_no_error. */
2273 p += emit_mov (p, x0, immediate_operand (expr_eval_no_error));
2274 p += emit_ret (p, lr);
2276 emit_ops_insns (buf, p - buf);
2279 /* Implementation of emit_ops method "emit_add". */
2282 aarch64_emit_add (void)
2287 p += emit_pop (p, x1);
2288 p += emit_add (p, x0, x0, register_operand (x1));
2290 emit_ops_insns (buf, p - buf);
2293 /* Implementation of emit_ops method "emit_sub". */
2296 aarch64_emit_sub (void)
2301 p += emit_pop (p, x1);
2302 p += emit_sub (p, x0, x0, register_operand (x1));
2304 emit_ops_insns (buf, p - buf);
2307 /* Implementation of emit_ops method "emit_mul". */
2310 aarch64_emit_mul (void)
2315 p += emit_pop (p, x1);
2316 p += emit_mul (p, x0, x1, x0);
2318 emit_ops_insns (buf, p - buf);
2321 /* Implementation of emit_ops method "emit_lsh". */
2324 aarch64_emit_lsh (void)
2329 p += emit_pop (p, x1);
2330 p += emit_lslv (p, x0, x1, x0);
2332 emit_ops_insns (buf, p - buf);
2335 /* Implementation of emit_ops method "emit_rsh_signed". */
2338 aarch64_emit_rsh_signed (void)
2343 p += emit_pop (p, x1);
2344 p += emit_asrv (p, x0, x1, x0);
2346 emit_ops_insns (buf, p - buf);
2349 /* Implementation of emit_ops method "emit_rsh_unsigned". */
2352 aarch64_emit_rsh_unsigned (void)
2357 p += emit_pop (p, x1);
2358 p += emit_lsrv (p, x0, x1, x0);
2360 emit_ops_insns (buf, p - buf);
2363 /* Implementation of emit_ops method "emit_ext". */
2366 aarch64_emit_ext (int arg)
2371 p += emit_sbfx (p, x0, x0, 0, arg);
2373 emit_ops_insns (buf, p - buf);
2376 /* Implementation of emit_ops method "emit_log_not". */
2379 aarch64_emit_log_not (void)
2384 /* If the top of the stack is 0, replace it with 1. Else replace it with
2387 p += emit_cmp (p, x0, immediate_operand (0));
2388 p += emit_cset (p, x0, EQ);
2390 emit_ops_insns (buf, p - buf);
2393 /* Implementation of emit_ops method "emit_bit_and". */
2396 aarch64_emit_bit_and (void)
2401 p += emit_pop (p, x1);
2402 p += emit_and (p, x0, x0, x1);
2404 emit_ops_insns (buf, p - buf);
2407 /* Implementation of emit_ops method "emit_bit_or". */
2410 aarch64_emit_bit_or (void)
2415 p += emit_pop (p, x1);
2416 p += emit_orr (p, x0, x0, x1);
2418 emit_ops_insns (buf, p - buf);
2421 /* Implementation of emit_ops method "emit_bit_xor". */
2424 aarch64_emit_bit_xor (void)
2429 p += emit_pop (p, x1);
2430 p += emit_eor (p, x0, x0, x1);
2432 emit_ops_insns (buf, p - buf);
2435 /* Implementation of emit_ops method "emit_bit_not". */
2438 aarch64_emit_bit_not (void)
2443 p += emit_mvn (p, x0, x0);
2445 emit_ops_insns (buf, p - buf);
2448 /* Implementation of emit_ops method "emit_equal". */
2451 aarch64_emit_equal (void)
2456 p += emit_pop (p, x1);
2457 p += emit_cmp (p, x0, register_operand (x1));
2458 p += emit_cset (p, x0, EQ);
2460 emit_ops_insns (buf, p - buf);
2463 /* Implementation of emit_ops method "emit_less_signed". */
2466 aarch64_emit_less_signed (void)
2471 p += emit_pop (p, x1);
2472 p += emit_cmp (p, x1, register_operand (x0));
2473 p += emit_cset (p, x0, LT);
2475 emit_ops_insns (buf, p - buf);
2478 /* Implementation of emit_ops method "emit_less_unsigned". */
2481 aarch64_emit_less_unsigned (void)
2486 p += emit_pop (p, x1);
2487 p += emit_cmp (p, x1, register_operand (x0));
2488 p += emit_cset (p, x0, LO);
2490 emit_ops_insns (buf, p - buf);
2493 /* Implementation of emit_ops method "emit_ref". */
2496 aarch64_emit_ref (int size)
2504 p += emit_ldrb (p, w0, x0, offset_memory_operand (0));
2507 p += emit_ldrh (p, w0, x0, offset_memory_operand (0));
2510 p += emit_ldr (p, w0, x0, offset_memory_operand (0));
2513 p += emit_ldr (p, x0, x0, offset_memory_operand (0));
2516 /* Unknown size, bail on compilation. */
2521 emit_ops_insns (buf, p - buf);
2524 /* Implementation of emit_ops method "emit_if_goto". */
2527 aarch64_emit_if_goto (int *offset_p, int *size_p)
2532 /* The Z flag is set or cleared here. */
2533 p += emit_cmp (p, x0, immediate_operand (0));
2534 /* This instruction must not change the Z flag. */
2535 p += emit_pop (p, x0);
2536 /* Branch over the next instruction if x0 == 0. */
2537 p += emit_bcond (p, EQ, 8);
2539 /* The NOP instruction will be patched with an unconditional branch. */
2541 *offset_p = (p - buf) * 4;
2546 emit_ops_insns (buf, p - buf);
2549 /* Implementation of emit_ops method "emit_goto". */
2552 aarch64_emit_goto (int *offset_p, int *size_p)
2557 /* The NOP instruction will be patched with an unconditional branch. */
2564 emit_ops_insns (buf, p - buf);
2567 /* Implementation of emit_ops method "write_goto_address". */
2570 aarch64_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
2574 emit_b (&insn, 0, to - from);
2575 append_insns (&from, 1, &insn);
2578 /* Implementation of emit_ops method "emit_const". */
2581 aarch64_emit_const (LONGEST num)
2586 p += emit_mov_addr (p, x0, num);
2588 emit_ops_insns (buf, p - buf);
2591 /* Implementation of emit_ops method "emit_call". */
2594 aarch64_emit_call (CORE_ADDR fn)
2599 p += emit_mov_addr (p, ip0, fn);
2600 p += emit_blr (p, ip0);
2602 emit_ops_insns (buf, p - buf);
2605 /* Implementation of emit_ops method "emit_reg". */
2608 aarch64_emit_reg (int reg)
2613 /* Set x0 to unsigned char *regs. */
2614 p += emit_sub (p, x0, fp, immediate_operand (2 * 8));
2615 p += emit_ldr (p, x0, x0, offset_memory_operand (0));
2616 p += emit_mov (p, x1, immediate_operand (reg));
2618 emit_ops_insns (buf, p - buf);
2620 aarch64_emit_call (get_raw_reg_func_addr ());
2623 /* Implementation of emit_ops method "emit_pop". */
2626 aarch64_emit_pop (void)
2631 p += emit_pop (p, x0);
2633 emit_ops_insns (buf, p - buf);
2636 /* Implementation of emit_ops method "emit_stack_flush". */
2639 aarch64_emit_stack_flush (void)
2644 p += emit_push (p, x0);
2646 emit_ops_insns (buf, p - buf);
2649 /* Implementation of emit_ops method "emit_zero_ext". */
2652 aarch64_emit_zero_ext (int arg)
2657 p += emit_ubfx (p, x0, x0, 0, arg);
2659 emit_ops_insns (buf, p - buf);
2662 /* Implementation of emit_ops method "emit_swap". */
2665 aarch64_emit_swap (void)
2670 p += emit_ldr (p, x1, sp, offset_memory_operand (0 * 16));
2671 p += emit_str (p, x0, sp, offset_memory_operand (0 * 16));
2672 p += emit_mov (p, x0, register_operand (x1));
2674 emit_ops_insns (buf, p - buf);
2677 /* Implementation of emit_ops method "emit_stack_adjust". */
2680 aarch64_emit_stack_adjust (int n)
2682 /* This is not needed with our design. */
2686 p += emit_add (p, sp, sp, immediate_operand (n * 16));
2688 emit_ops_insns (buf, p - buf);
2691 /* Implementation of emit_ops method "emit_int_call_1". */
2694 aarch64_emit_int_call_1 (CORE_ADDR fn, int arg1)
2699 p += emit_mov (p, x0, immediate_operand (arg1));
2701 emit_ops_insns (buf, p - buf);
2703 aarch64_emit_call (fn);
2706 /* Implementation of emit_ops method "emit_void_call_2". */
2709 aarch64_emit_void_call_2 (CORE_ADDR fn, int arg1)
2714 /* Push x0 on the stack. */
2715 aarch64_emit_stack_flush ();
2717 /* Setup arguments for the function call:
2720 x1: top of the stack
2725 p += emit_mov (p, x1, register_operand (x0));
2726 p += emit_mov (p, x0, immediate_operand (arg1));
2728 emit_ops_insns (buf, p - buf);
2730 aarch64_emit_call (fn);
2733 aarch64_emit_pop ();
2736 /* Implementation of emit_ops method "emit_eq_goto". */
2739 aarch64_emit_eq_goto (int *offset_p, int *size_p)
2744 p += emit_pop (p, x1);
2745 p += emit_cmp (p, x1, register_operand (x0));
2746 /* Branch over the next instruction if x0 != x1. */
2747 p += emit_bcond (p, NE, 8);
2748 /* The NOP instruction will be patched with an unconditional branch. */
2750 *offset_p = (p - buf) * 4;
2755 emit_ops_insns (buf, p - buf);
2758 /* Implementation of emit_ops method "emit_ne_goto". */
2761 aarch64_emit_ne_goto (int *offset_p, int *size_p)
2766 p += emit_pop (p, x1);
2767 p += emit_cmp (p, x1, register_operand (x0));
2768 /* Branch over the next instruction if x0 == x1. */
2769 p += emit_bcond (p, EQ, 8);
2770 /* The NOP instruction will be patched with an unconditional branch. */
2772 *offset_p = (p - buf) * 4;
2777 emit_ops_insns (buf, p - buf);
2780 /* Implementation of emit_ops method "emit_lt_goto". */
2783 aarch64_emit_lt_goto (int *offset_p, int *size_p)
2788 p += emit_pop (p, x1);
2789 p += emit_cmp (p, x1, register_operand (x0));
2790 /* Branch over the next instruction if x0 >= x1. */
2791 p += emit_bcond (p, GE, 8);
2792 /* The NOP instruction will be patched with an unconditional branch. */
2794 *offset_p = (p - buf) * 4;
2799 emit_ops_insns (buf, p - buf);
2802 /* Implementation of emit_ops method "emit_le_goto". */
2805 aarch64_emit_le_goto (int *offset_p, int *size_p)
2810 p += emit_pop (p, x1);
2811 p += emit_cmp (p, x1, register_operand (x0));
2812 /* Branch over the next instruction if x0 > x1. */
2813 p += emit_bcond (p, GT, 8);
2814 /* The NOP instruction will be patched with an unconditional branch. */
2816 *offset_p = (p - buf) * 4;
2821 emit_ops_insns (buf, p - buf);
2824 /* Implementation of emit_ops method "emit_gt_goto". */
2827 aarch64_emit_gt_goto (int *offset_p, int *size_p)
2832 p += emit_pop (p, x1);
2833 p += emit_cmp (p, x1, register_operand (x0));
2834 /* Branch over the next instruction if x0 <= x1. */
2835 p += emit_bcond (p, LE, 8);
2836 /* The NOP instruction will be patched with an unconditional branch. */
2838 *offset_p = (p - buf) * 4;
2843 emit_ops_insns (buf, p - buf);
2846 /* Implementation of emit_ops method "emit_ge_got". */
2849 aarch64_emit_ge_got (int *offset_p, int *size_p)
2854 p += emit_pop (p, x1);
2855 p += emit_cmp (p, x1, register_operand (x0));
2856 /* Branch over the next instruction if x0 <= x1. */
2857 p += emit_bcond (p, LT, 8);
2858 /* The NOP instruction will be patched with an unconditional branch. */
2860 *offset_p = (p - buf) * 4;
2865 emit_ops_insns (buf, p - buf);
2868 static struct emit_ops aarch64_emit_ops_impl =
2870 aarch64_emit_prologue,
2871 aarch64_emit_epilogue,
2876 aarch64_emit_rsh_signed,
2877 aarch64_emit_rsh_unsigned,
2879 aarch64_emit_log_not,
2880 aarch64_emit_bit_and,
2881 aarch64_emit_bit_or,
2882 aarch64_emit_bit_xor,
2883 aarch64_emit_bit_not,
2885 aarch64_emit_less_signed,
2886 aarch64_emit_less_unsigned,
2888 aarch64_emit_if_goto,
2890 aarch64_write_goto_address,
2895 aarch64_emit_stack_flush,
2896 aarch64_emit_zero_ext,
2898 aarch64_emit_stack_adjust,
2899 aarch64_emit_int_call_1,
2900 aarch64_emit_void_call_2,
2901 aarch64_emit_eq_goto,
2902 aarch64_emit_ne_goto,
2903 aarch64_emit_lt_goto,
2904 aarch64_emit_le_goto,
2905 aarch64_emit_gt_goto,
2906 aarch64_emit_ge_got,
2909 /* Implementation of linux_target_ops method "emit_ops". */
2911 static struct emit_ops *
2912 aarch64_emit_ops (void)
2914 return &aarch64_emit_ops_impl;
2917 /* Implementation of linux_target_ops method
2918 "get_min_fast_tracepoint_insn_len". */
2921 aarch64_get_min_fast_tracepoint_insn_len (void)
2926 /* Implementation of linux_target_ops method "supports_range_stepping". */
2929 aarch64_supports_range_stepping (void)
2934 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
2936 static const gdb_byte *
2937 aarch64_sw_breakpoint_from_kind (int kind, int *size)
2939 *size = aarch64_breakpoint_len;
2940 return aarch64_breakpoint;
2943 struct linux_target_ops the_low_target =
2947 aarch64_cannot_fetch_register,
2948 aarch64_cannot_store_register,
2949 NULL, /* fetch_register */
2952 NULL, /* breakpoint_kind_from_pc */
2953 aarch64_sw_breakpoint_from_kind,
2954 NULL, /* breakpoint_reinsert_addr */
2955 0, /* decr_pc_after_break */
2956 aarch64_breakpoint_at,
2957 aarch64_supports_z_point_type,
2958 aarch64_insert_point,
2959 aarch64_remove_point,
2960 aarch64_stopped_by_watchpoint,
2961 aarch64_stopped_data_address,
2962 NULL, /* collect_ptrace_register */
2963 NULL, /* supply_ptrace_register */
2964 aarch64_linux_siginfo_fixup,
2965 aarch64_linux_new_process,
2966 aarch64_linux_new_thread,
2967 aarch64_linux_new_fork,
2968 aarch64_linux_prepare_to_resume,
2969 NULL, /* process_qsupported */
2970 aarch64_supports_tracepoints,
2971 aarch64_get_thread_area,
2972 aarch64_install_fast_tracepoint_jump_pad,
2974 aarch64_get_min_fast_tracepoint_insn_len,
2975 aarch64_supports_range_stepping,
2979 initialize_low_arch (void)
2981 init_registers_aarch64 ();
2983 initialize_low_arch_aarch32 ();
2985 initialize_regsets_info (&aarch64_regsets_info);