1 /* GNU/Linux/AArch64 specific low level interface, for the remote server for
4 Copyright (C) 2009-2014 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "linux-low.h"
24 #include "elf/common.h"
28 #include <sys/ptrace.h>
31 #include "gdb_proc_service.h"
32 #include "break-common.h"
34 /* Defined in auto-generated files. */
35 void init_registers_aarch64 (void);
36 extern const struct target_desc *tdesc_aarch64;
42 #define AARCH64_X_REGS_NUM 31
43 #define AARCH64_V_REGS_NUM 32
44 #define AARCH64_X0_REGNO 0
45 #define AARCH64_SP_REGNO 31
46 #define AARCH64_PC_REGNO 32
47 #define AARCH64_CPSR_REGNO 33
48 #define AARCH64_V0_REGNO 34
50 #define AARCH64_NUM_REGS (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM)
55 /* These offsets correspond to GET/SETREGSET */
57 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8,
58 8*8, 9*8, 10*8, 11*8, 12*8, 13*8, 14*8, 15*8,
59 16*8, 17*8, 18*8, 19*8, 20*8, 21*8, 22*8, 23*8,
60 24*8, 25*8, 26*8, 27*8, 28*8,
65 33*8, /* cpsr 4 bytes!*/
67 /* FP register offsets correspond to GET/SETFPREGSET */
68 0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16,
69 8*16, 9*16, 10*16, 11*16, 12*16, 13*16, 14*16, 15*16,
70 16*16, 17*16, 18*16, 19*16, 20*16, 21*16, 22*16, 23*16,
71 24*16, 25*16, 26*16, 27*16, 28*16, 29*16, 30*16, 31*16
74 /* Here starts the macro definitions, data structures, and code for
75 the hardware breakpoint and hardware watchpoint support. The
76 following is the abbreviations that are used frequently in the code
83 /* Maximum number of hardware breakpoint and watchpoint registers.
84 Neither of these values may exceed the width of dr_changed_t
87 #define AARCH64_HBP_MAX_NUM 16
88 #define AARCH64_HWP_MAX_NUM 16
90 /* Alignment requirement in bytes of hardware breakpoint and
91 watchpoint address. This is the requirement for the addresses that
92 can be written to the hardware breakpoint/watchpoint value
93 registers. The kernel currently does not do any alignment on
94 addresses when receiving a writing request (via ptrace call) to
95 these debug registers, and it will reject any address that is
97 Some limited support has been provided in this gdbserver port for
98 unaligned watchpoints, so that from a gdb user point of view, an
99 unaligned watchpoint can still be set. This is achieved by
100 minimally enlarging the watched area to meet the alignment
101 requirement, and if necessary, splitting the watchpoint over
102 several hardware watchpoint registers. */
104 #define AARCH64_HBP_ALIGNMENT 4
105 #define AARCH64_HWP_ALIGNMENT 8
107 /* The maximum length of a memory region that can be watched by one
108 hardware watchpoint register. */
110 #define AARCH64_HWP_MAX_LEN_PER_REG 8
112 /* Each bit of a variable of this type is used to indicate whether a
113 hardware breakpoint or watchpoint setting has been changed since
114 the last updating. Bit N corresponds to the Nth hardware
115 breakpoint or watchpoint setting which is managed in
116 aarch64_debug_reg_state. Where N is valid between 0 and the total
117 number of the hardware breakpoint or watchpoint debug registers
118 minus 1. When the bit N is 1, it indicates the corresponding
119 breakpoint or watchpoint setting is changed, and thus the
120 corresponding hardware debug register needs to be updated via the
123 In the per-thread arch-specific data area, we define two such
124 variables for per-thread hardware breakpoint and watchpoint
125 settings respectively.
127 This type is part of the mechanism which helps reduce the number of
128 ptrace calls to the kernel, i.e. avoid asking the kernel to write
129 to the debug registers with unchanged values. */
131 typedef unsigned long long dr_changed_t;
133 /* Set each of the lower M bits of X to 1; assert X is wide enough. */
135 #define DR_MARK_ALL_CHANGED(x, m) \
138 gdb_assert (sizeof ((x)) * 8 >= (m)); \
139 (x) = (((dr_changed_t)1 << (m)) - 1); \
142 #define DR_MARK_N_CHANGED(x, n) \
145 (x) |= ((dr_changed_t)1 << (n)); \
148 #define DR_CLEAR_CHANGED(x) \
154 #define DR_HAS_CHANGED(x) ((x) != 0)
155 #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
157 /* Structure for managing the hardware breakpoint/watchpoint resources.
158 DR_ADDR_* stores the address, DR_CTRL_* stores the control register
159 content, and DR_REF_COUNT_* counts the numbers of references to the
160 corresponding bp/wp, by which way the limited hardware resources
161 are not wasted on duplicated bp/wp settings (though so far gdb has
162 done a good job by not sending duplicated bp/wp requests). */
164 struct aarch64_debug_reg_state
166 /* hardware breakpoint */
167 CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM];
168 unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM];
169 unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM];
171 /* hardware watchpoint */
172 CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM];
173 unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM];
174 unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM];
177 /* Per-process arch-specific data we want to keep. */
179 struct arch_process_info
181 /* Hardware breakpoint/watchpoint data.
182 The reason for them to be per-process rather than per-thread is
183 due to the lack of information in the gdbserver environment;
184 gdbserver is not told that whether a requested hardware
185 breakpoint/watchpoint is thread specific or not, so it has to set
186 each hw bp/wp for every thread in the current process. The
187 higher level bp/wp management in gdb will resume a thread if a hw
188 bp/wp trap is not expected for it. Since the hw bp/wp setting is
189 same for each thread, it is reasonable for the data to live here.
191 struct aarch64_debug_reg_state debug_reg_state;
194 /* Per-thread arch-specific data we want to keep. */
198 /* When bit N is 1, it indicates the Nth hardware breakpoint or
199 watchpoint register pair needs to be updated when the thread is
200 resumed; see aarch64_linux_prepare_to_resume. */
201 dr_changed_t dr_changed_bp;
202 dr_changed_t dr_changed_wp;
205 /* Number of hardware breakpoints/watchpoints the target supports.
206 They are initialized with values obtained via the ptrace calls
207 with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */
209 static int aarch64_num_bp_regs;
210 static int aarch64_num_wp_regs;
212 #define Z_PACKET_SW_BP '0'
213 #define Z_PACKET_HW_BP '1'
214 #define Z_PACKET_WRITE_WP '2'
215 #define Z_PACKET_READ_WP '3'
216 #define Z_PACKET_ACCESS_WP '4'
218 /* Map the protocol breakpoint/watchpoint type TYPE to enum
219 target_hw_bp_type. */
221 static enum target_hw_bp_type
222 Z_packet_to_target_hw_bp_type (char type)
228 case Z_PACKET_WRITE_WP:
230 case Z_PACKET_READ_WP:
232 case Z_PACKET_ACCESS_WP:
235 fatal ("bad watchpoint type %c", type);
240 aarch64_cannot_store_register (int regno)
242 return regno >= AARCH64_NUM_REGS;
246 aarch64_cannot_fetch_register (int regno)
248 return regno >= AARCH64_NUM_REGS;
252 aarch64_fill_gregset (struct regcache *regcache, void *buf)
254 struct user_pt_regs *regset = buf;
257 for (i = 0; i < AARCH64_X_REGS_NUM; i++)
258 collect_register (regcache, AARCH64_X0_REGNO + i, ®set->regs[i]);
259 collect_register (regcache, AARCH64_SP_REGNO, ®set->sp);
260 collect_register (regcache, AARCH64_PC_REGNO, ®set->pc);
261 collect_register (regcache, AARCH64_CPSR_REGNO, ®set->pstate);
265 aarch64_store_gregset (struct regcache *regcache, const void *buf)
267 const struct user_pt_regs *regset = buf;
270 for (i = 0; i < AARCH64_X_REGS_NUM; i++)
271 supply_register (regcache, AARCH64_X0_REGNO + i, ®set->regs[i]);
272 supply_register (regcache, AARCH64_SP_REGNO, ®set->sp);
273 supply_register (regcache, AARCH64_PC_REGNO, ®set->pc);
274 supply_register (regcache, AARCH64_CPSR_REGNO, ®set->pstate);
278 aarch64_fill_fpregset (struct regcache *regcache, void *buf)
280 struct user_fpsimd_state *regset = buf;
283 for (i = 0; i < AARCH64_V_REGS_NUM; i++)
284 collect_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]);
288 aarch64_store_fpregset (struct regcache *regcache, const void *buf)
290 const struct user_fpsimd_state *regset = buf;
293 for (i = 0; i < AARCH64_V_REGS_NUM; i++)
294 supply_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]);
297 /* Debugging of hardware breakpoint/watchpoint support. */
298 extern int debug_hw_points;
300 /* Enable miscellaneous debugging output. The name is historical - it
301 was originally used to debug LinuxThreads support. */
302 extern int debug_threads;
305 aarch64_get_pc (struct regcache *regcache)
309 collect_register_by_name (regcache, "pc", &pc);
311 debug_printf ("stop pc is %08lx\n", pc);
316 aarch64_set_pc (struct regcache *regcache, CORE_ADDR pc)
318 unsigned long newpc = pc;
319 supply_register_by_name (regcache, "pc", &newpc);
322 /* Correct in either endianness. */
324 #define aarch64_breakpoint_len 4
326 static const unsigned long aarch64_breakpoint = 0x00800011;
329 aarch64_breakpoint_at (CORE_ADDR where)
333 (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
334 if (insn == aarch64_breakpoint)
340 /* Print the values of the cached breakpoint/watchpoint registers.
341 This is enabled via the "set debug-hw-points" monitor command. */
344 aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
345 const char *func, CORE_ADDR addr,
346 int len, enum target_hw_bp_type type)
350 fprintf (stderr, "%s", func);
352 fprintf (stderr, " (addr=0x%08lx, len=%d, type=%s)",
353 (unsigned long) addr, len,
354 type == hw_write ? "hw-write-watchpoint"
355 : (type == hw_read ? "hw-read-watchpoint"
356 : (type == hw_access ? "hw-access-watchpoint"
357 : (type == hw_execute ? "hw-breakpoint"
359 fprintf (stderr, ":\n");
361 fprintf (stderr, "\tBREAKPOINTs:\n");
362 for (i = 0; i < aarch64_num_bp_regs; i++)
363 fprintf (stderr, "\tBP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n",
364 i, paddress (state->dr_addr_bp[i]),
365 state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]);
367 fprintf (stderr, "\tWATCHPOINTs:\n");
368 for (i = 0; i < aarch64_num_wp_regs; i++)
369 fprintf (stderr, "\tWP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n",
370 i, paddress (state->dr_addr_wp[i]),
371 state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]);
375 aarch64_init_debug_reg_state (struct aarch64_debug_reg_state *state)
379 for (i = 0; i < AARCH64_HBP_MAX_NUM; ++i)
381 state->dr_addr_bp[i] = 0;
382 state->dr_ctrl_bp[i] = 0;
383 state->dr_ref_count_bp[i] = 0;
386 for (i = 0; i < AARCH64_HWP_MAX_NUM; ++i)
388 state->dr_addr_wp[i] = 0;
389 state->dr_ctrl_wp[i] = 0;
390 state->dr_ref_count_wp[i] = 0;
394 /* ptrace expects control registers to be formatted as follows:
397 +--------------------------------+----------+------+------+----+
398 | RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN |
399 +--------------------------------+----------+------+------+----+
401 The TYPE field is ignored for breakpoints. */
403 #define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1)
404 #define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff)
406 /* Utility function that returns the length in bytes of a watchpoint
407 according to the content of a hardware debug control register CTRL.
408 Note that the kernel currently only supports the following Byte
409 Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
410 that for a hardware watchpoint, its valid length can only be 1
411 byte, 2 bytes, 4 bytes or 8 bytes. */
413 static inline unsigned int
414 aarch64_watchpoint_length (unsigned int ctrl)
416 switch (DR_CONTROL_LENGTH (ctrl))
431 /* Given the hardware breakpoint or watchpoint type TYPE and its
432 length LEN, return the expected encoding for a hardware
433 breakpoint/watchpoint control register. */
436 aarch64_point_encode_ctrl_reg (enum target_hw_bp_type type, int len)
438 unsigned int ctrl, ttype;
456 perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
462 ctrl |= ((1 << len) - 1) << 5;
464 ctrl |= (2 << 1) | 1;
469 /* Addresses to be written to the hardware breakpoint and watchpoint
470 value registers need to be aligned; the alignment is 4-byte and
471 8-type respectively. Linux kernel rejects any non-aligned address
472 it receives from the related ptrace call. Furthermore, the kernel
473 currently only supports the following Byte Address Select (BAS)
474 values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
475 watchpoint to be accepted by the kernel (via ptrace call), its
476 valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
477 Despite these limitations, the unaligned watchpoint is supported in
480 Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */
483 aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len)
485 unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT
486 : AARCH64_HBP_ALIGNMENT;
488 if (addr & (alignment - 1))
491 if (len != 8 && len != 4 && len != 2 && len != 1)
497 /* Given the (potentially unaligned) watchpoint address in ADDR and
498 length in LEN, return the aligned address and aligned length in
499 *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned
500 aligned address and length will be valid to be written to the
501 hardware watchpoint value and control registers. See the comment
502 above aarch64_point_is_aligned for the information about the
503 alignment requirement. The given watchpoint may get truncated if
504 more than one hardware register is needed to cover the watched
505 region. *NEXT_ADDR_P and *NEXT_LEN_P, if non-NULL, will return the
506 address and length of the remaining part of the watchpoint (which
507 can be processed by calling this routine again to generate another
508 aligned address and length pair.
510 Essentially, unaligned watchpoint is achieved by minimally
511 enlarging the watched area to meet the alignment requirement, and
512 if necessary, splitting the watchpoint over several hardware
513 watchpoint registers. The trade-off is that there will be
514 false-positive hits for the read-type or the access-type hardware
515 watchpoints; for the write type, which is more commonly used, there
516 will be no such issues, as the higher-level breakpoint management
517 in gdb always examines the exact watched region for any content
518 change, and transparently resumes a thread from a watchpoint trap
519 if there is no change to the watched region.
521 Another limitation is that because the watched region is enlarged,
522 the watchpoint fault address returned by
523 aarch64_stopped_data_address may be outside of the original watched
524 region, especially when the triggering instruction is accessing a
525 larger region. When the fault address is not within any known
526 range, watchpoints_triggered in gdb will get confused, as the
527 higher-level watchpoint management is only aware of original
528 watched regions, and will think that some unknown watchpoint has
529 been triggered. In such a case, gdb may stop without displaying
530 any detailed information.
532 Once the kernel provides the full support for Byte Address Select
533 (BAS) in the hardware watchpoint control register, these
534 limitations can be largely relaxed with some further work. */
537 aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p,
538 int *aligned_len_p, CORE_ADDR *next_addr_p,
543 CORE_ADDR aligned_addr;
544 const unsigned int alignment = AARCH64_HWP_ALIGNMENT;
545 const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG;
547 /* As assumed by the algorithm. */
548 gdb_assert (alignment == max_wp_len);
553 /* Address to be put into the hardware watchpoint value register
555 offset = addr & (alignment - 1);
556 aligned_addr = addr - offset;
558 gdb_assert (offset >= 0 && offset < alignment);
559 gdb_assert (aligned_addr >= 0 && aligned_addr <= addr);
560 gdb_assert ((offset + len) > 0);
562 if (offset + len >= max_wp_len)
564 /* Need more than one watchpoint registers; truncate it at the
565 alignment boundary. */
566 aligned_len = max_wp_len;
567 len -= (max_wp_len - offset);
568 addr += (max_wp_len - offset);
569 gdb_assert ((addr & (alignment - 1)) == 0);
573 /* Find the smallest valid length that is large enough to
574 accommodate this watchpoint. */
575 static const unsigned char
576 aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] =
577 { 1, 2, 4, 4, 8, 8, 8, 8 };
579 aligned_len = aligned_len_array[offset + len - 1];
584 if (aligned_addr_p != NULL)
585 *aligned_addr_p = aligned_addr;
586 if (aligned_len_p != NULL)
587 *aligned_len_p = aligned_len;
588 if (next_addr_p != NULL)
590 if (next_len_p != NULL)
594 /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
595 registers with data from *STATE. */
598 aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state,
599 int tid, int watchpoint)
603 struct user_hwdebug_state regs;
604 const CORE_ADDR *addr;
605 const unsigned int *ctrl;
607 memset (®s, 0, sizeof (regs));
608 iov.iov_base = ®s;
609 count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs;
610 addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp;
611 ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp;
614 iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs[count - 1])
615 + sizeof (regs.dbg_regs [count - 1]));
617 for (i = 0; i < count; i++)
619 regs.dbg_regs[i].addr = addr[i];
620 regs.dbg_regs[i].ctrl = ctrl[i];
623 if (ptrace (PTRACE_SETREGSET, tid,
624 watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK,
626 error (_("Unexpected error setting hardware debug registers"));
629 struct aarch64_dr_update_callback_param
636 /* Callback function which records the information about the change of
637 one hardware breakpoint/watchpoint setting for the thread ENTRY.
638 The information is passed in via PTR.
639 N.B. The actual updating of hardware debug registers is not
640 carried out until the moment the thread is resumed. */
643 debug_reg_change_callback (struct inferior_list_entry *entry, void *ptr)
645 struct thread_info *thread = (struct thread_info *) entry;
646 struct lwp_info *lwp = get_thread_lwp (thread);
647 struct aarch64_dr_update_callback_param *param_p
648 = (struct aarch64_dr_update_callback_param *) ptr;
649 int pid = param_p->pid;
650 int idx = param_p->idx;
651 int is_watchpoint = param_p->is_watchpoint;
652 struct arch_lwp_info *info = lwp->arch_private;
653 dr_changed_t *dr_changed_ptr;
654 dr_changed_t dr_changed;
658 fprintf (stderr, "debug_reg_change_callback: \n\tOn entry:\n");
659 fprintf (stderr, "\tpid%d, tid: %ld, dr_changed_bp=0x%llx, "
660 "dr_changed_wp=0x%llx\n",
661 pid, lwpid_of (thread), info->dr_changed_bp,
662 info->dr_changed_wp);
665 dr_changed_ptr = is_watchpoint ? &info->dr_changed_wp
666 : &info->dr_changed_bp;
667 dr_changed = *dr_changed_ptr;
669 /* Only update the threads of this process. */
670 if (pid_of (thread) == pid)
673 && (idx <= (is_watchpoint ? aarch64_num_wp_regs
674 : aarch64_num_bp_regs)));
676 /* The following assertion is not right, as there can be changes
677 that have not been made to the hardware debug registers
678 before new changes overwrite the old ones. This can happen,
679 for instance, when the breakpoint/watchpoint hit one of the
680 threads and the user enters continue; then what happens is:
681 1) all breakpoints/watchpoints are removed for all threads;
682 2) a single step is carried out for the thread that was hit;
683 3) all of the points are inserted again for all threads;
684 4) all threads are resumed.
685 The 2nd step will only affect the one thread in which the
686 bp/wp was hit, which means only that one thread is resumed;
687 remember that the actual updating only happen in
688 aarch64_linux_prepare_to_resume, so other threads remain
689 stopped during the removal and insertion of bp/wp. Therefore
690 for those threads, the change of insertion of the bp/wp
691 overwrites that of the earlier removals. (The situation may
692 be different when bp/wp is steppable, or in the non-stop
694 /* gdb_assert (DR_N_HAS_CHANGED (dr_changed, idx) == 0); */
696 /* The actual update is done later just before resuming the lwp,
697 we just mark that one register pair needs updating. */
698 DR_MARK_N_CHANGED (dr_changed, idx);
699 *dr_changed_ptr = dr_changed;
701 /* If the lwp isn't stopped, force it to momentarily pause, so
702 we can update its debug registers. */
704 linux_stop_lwp (lwp);
709 fprintf (stderr, "\tOn exit:\n\tpid%d, tid: %ld, dr_changed_bp=0x%llx, "
710 "dr_changed_wp=0x%llx\n",
711 pid, lwpid_of (thread), info->dr_changed_bp,
712 info->dr_changed_wp);
718 /* Notify each thread that their IDXth breakpoint/watchpoint register
719 pair needs to be updated. The message will be recorded in each
720 thread's arch-specific data area, the actual updating will be done
721 when the thread is resumed. */
724 aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state *state,
725 int is_watchpoint, unsigned int idx)
727 struct aarch64_dr_update_callback_param param;
729 /* Only update the threads of this process. */
730 param.pid = pid_of (current_inferior);
732 param.is_watchpoint = is_watchpoint;
735 find_inferior (&all_threads, debug_reg_change_callback, (void *) ¶m);
739 /* Return the pointer to the debug register state structure in the
740 current process' arch-specific data area. */
742 static struct aarch64_debug_reg_state *
743 aarch64_get_debug_reg_state ()
745 struct process_info *proc;
747 proc = current_process ();
748 return &proc->private->arch_private->debug_reg_state;
751 /* Record the insertion of one breakpoint/watchpoint, as represented
752 by ADDR and CTRL, in the process' arch-specific data area *STATE. */
755 aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state,
756 enum target_hw_bp_type type,
757 CORE_ADDR addr, int len)
759 int i, idx, num_regs, is_watchpoint;
760 unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
761 CORE_ADDR *dr_addr_p;
763 /* Set up state pointers. */
764 is_watchpoint = (type != hw_execute);
765 gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
768 num_regs = aarch64_num_wp_regs;
769 dr_addr_p = state->dr_addr_wp;
770 dr_ctrl_p = state->dr_ctrl_wp;
771 dr_ref_count = state->dr_ref_count_wp;
775 num_regs = aarch64_num_bp_regs;
776 dr_addr_p = state->dr_addr_bp;
777 dr_ctrl_p = state->dr_ctrl_bp;
778 dr_ref_count = state->dr_ref_count_bp;
781 ctrl = aarch64_point_encode_ctrl_reg (type, len);
783 /* Find an existing or free register in our cache. */
785 for (i = 0; i < num_regs; ++i)
787 if ((dr_ctrl_p[i] & 1) == 0)
789 gdb_assert (dr_ref_count[i] == 0);
791 /* no break; continue hunting for an exising one. */
793 else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
795 gdb_assert (dr_ref_count[i] != 0);
805 /* Update our cache. */
806 if ((dr_ctrl_p[idx] & 1) == 0)
809 dr_addr_p[idx] = addr;
810 dr_ctrl_p[idx] = ctrl;
811 dr_ref_count[idx] = 1;
812 /* Notify the change. */
813 aarch64_notify_debug_reg_change (state, is_watchpoint, idx);
824 /* Record the removal of one breakpoint/watchpoint, as represented by
825 ADDR and CTRL, in the process' arch-specific data area *STATE. */
828 aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state,
829 enum target_hw_bp_type type,
830 CORE_ADDR addr, int len)
832 int i, num_regs, is_watchpoint;
833 unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
834 CORE_ADDR *dr_addr_p;
836 /* Set up state pointers. */
837 is_watchpoint = (type != hw_execute);
838 gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
841 num_regs = aarch64_num_wp_regs;
842 dr_addr_p = state->dr_addr_wp;
843 dr_ctrl_p = state->dr_ctrl_wp;
844 dr_ref_count = state->dr_ref_count_wp;
848 num_regs = aarch64_num_bp_regs;
849 dr_addr_p = state->dr_addr_bp;
850 dr_ctrl_p = state->dr_ctrl_bp;
851 dr_ref_count = state->dr_ref_count_bp;
854 ctrl = aarch64_point_encode_ctrl_reg (type, len);
856 /* Find the entry that matches the ADDR and CTRL. */
857 for (i = 0; i < num_regs; ++i)
858 if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
860 gdb_assert (dr_ref_count[i] != 0);
868 /* Clear our cache. */
869 if (--dr_ref_count[i] == 0)
871 /* Clear the enable bit. */
875 /* Notify the change. */
876 aarch64_notify_debug_reg_change (state, is_watchpoint, i);
883 aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr,
884 int len, int is_insert)
886 struct aarch64_debug_reg_state *state;
888 /* The hardware breakpoint on AArch64 should always be 4-byte
890 if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len))
893 state = aarch64_get_debug_reg_state ();
896 return aarch64_dr_state_insert_one_point (state, type, addr, len);
898 return aarch64_dr_state_remove_one_point (state, type, addr, len);
901 /* This is essentially the same as aarch64_handle_breakpoint, apart
902 from that it is an aligned watchpoint to be handled. */
905 aarch64_handle_aligned_watchpoint (enum target_hw_bp_type type,
906 CORE_ADDR addr, int len, int is_insert)
908 struct aarch64_debug_reg_state *state;
910 state = aarch64_get_debug_reg_state ();
913 return aarch64_dr_state_insert_one_point (state, type, addr, len);
915 return aarch64_dr_state_remove_one_point (state, type, addr, len);
918 /* Insert/remove unaligned watchpoint by calling
919 aarch64_align_watchpoint repeatedly until the whole watched region,
920 as represented by ADDR and LEN, has been properly aligned and ready
921 to be written to one or more hardware watchpoint registers.
922 IS_INSERT indicates whether this is an insertion or a deletion.
923 Return 0 if succeed. */
926 aarch64_handle_unaligned_watchpoint (enum target_hw_bp_type type,
927 CORE_ADDR addr, int len, int is_insert)
929 struct aarch64_debug_reg_state *state
930 = aarch64_get_debug_reg_state ();
934 CORE_ADDR aligned_addr;
935 int aligned_len, ret;
937 aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len,
941 ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr,
944 ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr,
949 "handle_unaligned_watchpoint: is_insert: %d\n"
950 " aligned_addr: 0x%s, aligned_len: %d\n"
951 " next_addr: 0x%s, next_len: %d\n",
952 is_insert, paddress (aligned_addr), aligned_len,
953 paddress (addr), len);
963 aarch64_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr,
964 int len, int is_insert)
966 if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len))
967 return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert);
969 return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert);
973 aarch64_supports_z_point_type (char z_type)
978 case Z_PACKET_WRITE_WP:
979 case Z_PACKET_READ_WP:
980 case Z_PACKET_ACCESS_WP:
983 /* Leave the handling of sw breakpoints with the gdb client. */
988 /* Insert a hardware breakpoint/watchpoint.
989 It actually only records the info of the to-be-inserted bp/wp;
990 the actual insertion will happen when threads are resumed.
993 Return 1 if TYPE is unsupported type;
994 Return -1 if an error occurs. */
997 aarch64_insert_point (char type, CORE_ADDR addr, int len)
1000 enum target_hw_bp_type targ_type;
1002 if (!aarch64_supports_z_point_type (type))
1005 if (debug_hw_points)
1006 fprintf (stderr, "insert_point on entry (addr=0x%08lx, len=%d)\n",
1007 (unsigned long) addr, len);
1009 /* Determine the type from the packet. */
1010 targ_type = Z_packet_to_target_hw_bp_type (type);
1012 if (targ_type != hw_execute)
1014 aarch64_handle_watchpoint (targ_type, addr, len, 1 /* is_insert */);
1017 aarch64_handle_breakpoint (targ_type, addr, len, 1 /* is_insert */);
1019 if (debug_hw_points > 1)
1020 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
1021 "insert_point", addr, len, targ_type);
1026 /* Remove a hardware breakpoint/watchpoint.
1027 It actually only records the info of the to-be-removed bp/wp,
1028 the actual removal will be done when threads are resumed.
1030 Return 0 if succeed;
1031 Return 1 if TYPE is an unsupported type;
1032 Return -1 if an error occurs. */
1035 aarch64_remove_point (char type, CORE_ADDR addr, int len)
1038 enum target_hw_bp_type targ_type;
1040 if (!aarch64_supports_z_point_type (type))
1043 if (debug_hw_points)
1044 fprintf (stderr, "remove_point on entry (addr=0x%08lx, len=%d)\n",
1045 (unsigned long) addr, len);
1047 /* Determine the type from the packet. */
1048 targ_type = Z_packet_to_target_hw_bp_type (type);
1050 /* Set up state pointers. */
1051 if (targ_type != hw_execute)
1053 aarch64_handle_watchpoint (targ_type, addr, len, 0 /* is_insert */);
1056 aarch64_handle_breakpoint (targ_type, addr, len, 0 /* is_insert */);
1058 if (debug_hw_points > 1)
1059 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
1060 "remove_point", addr, len, targ_type);
1065 /* Returns the address associated with the watchpoint that hit, if
1066 any; returns 0 otherwise. */
1069 aarch64_stopped_data_address (void)
1073 struct aarch64_debug_reg_state *state;
1075 pid = lwpid_of (current_inferior);
1077 /* Get the siginfo. */
1078 if (ptrace (PTRACE_GETSIGINFO, pid, NULL, &siginfo) != 0)
1079 return (CORE_ADDR) 0;
1081 /* Need to be a hardware breakpoint/watchpoint trap. */
1082 if (siginfo.si_signo != SIGTRAP
1083 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
1084 return (CORE_ADDR) 0;
1086 /* Check if the address matches any watched address. */
1087 state = aarch64_get_debug_reg_state ();
1088 for (i = aarch64_num_wp_regs - 1; i >= 0; --i)
1090 const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]);
1091 const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr;
1092 const CORE_ADDR addr_watch = state->dr_addr_wp[i];
1093 if (state->dr_ref_count_wp[i]
1094 && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i])
1095 && addr_trap >= addr_watch
1096 && addr_trap < addr_watch + len)
1100 return (CORE_ADDR) 0;
1103 /* Returns 1 if target was stopped due to a watchpoint hit, 0
1107 aarch64_stopped_by_watchpoint (void)
1109 if (aarch64_stopped_data_address () != 0)
1115 /* Fetch the thread-local storage pointer for libthread_db. */
1118 ps_get_thread_area (const struct ps_prochandle *ph,
1119 lwpid_t lwpid, int idx, void **base)
1124 iovec.iov_base = ®
1125 iovec.iov_len = sizeof (reg);
1127 if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0)
1130 /* IDX is the bias from the thread pointer to the beginning of the
1131 thread descriptor. It has to be subtracted due to implementation
1132 quirks in libthread_db. */
1133 *base = (void *) (reg - idx);
1138 /* Called when a new process is created. */
1140 static struct arch_process_info *
1141 aarch64_linux_new_process (void)
1143 struct arch_process_info *info = xcalloc (1, sizeof (*info));
1145 aarch64_init_debug_reg_state (&info->debug_reg_state);
1150 /* Called when a new thread is detected. */
1152 static struct arch_lwp_info *
1153 aarch64_linux_new_thread (void)
1155 struct arch_lwp_info *info = xcalloc (1, sizeof (*info));
1157 /* Mark that all the hardware breakpoint/watchpoint register pairs
1158 for this thread need to be initialized (with data from
1159 aarch_process_info.debug_reg_state). */
1160 DR_MARK_ALL_CHANGED (info->dr_changed_bp, aarch64_num_bp_regs);
1161 DR_MARK_ALL_CHANGED (info->dr_changed_wp, aarch64_num_wp_regs);
1166 /* Called when resuming a thread.
1167 If the debug regs have changed, update the thread's copies. */
1170 aarch64_linux_prepare_to_resume (struct lwp_info *lwp)
1172 struct thread_info *thread = get_lwp_thread (lwp);
1173 ptid_t ptid = ptid_of (thread);
1174 struct arch_lwp_info *info = lwp->arch_private;
1176 if (DR_HAS_CHANGED (info->dr_changed_bp)
1177 || DR_HAS_CHANGED (info->dr_changed_wp))
1179 int tid = ptid_get_lwp (ptid);
1180 struct process_info *proc = find_process_pid (ptid_get_pid (ptid));
1181 struct aarch64_debug_reg_state *state
1182 = &proc->private->arch_private->debug_reg_state;
1184 if (debug_hw_points)
1185 fprintf (stderr, "prepare_to_resume thread %ld\n", lwpid_of (thread));
1188 if (DR_HAS_CHANGED (info->dr_changed_wp))
1190 aarch64_linux_set_debug_regs (state, tid, 1);
1191 DR_CLEAR_CHANGED (info->dr_changed_wp);
1195 if (DR_HAS_CHANGED (info->dr_changed_bp))
1197 aarch64_linux_set_debug_regs (state, tid, 0);
1198 DR_CLEAR_CHANGED (info->dr_changed_bp);
1203 /* ptrace hardware breakpoint resource info is formatted as follows:
1206 +---------------+--------------+---------------+---------------+
1207 | RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS |
1208 +---------------+--------------+---------------+---------------+ */
1210 #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
1211 #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
1212 #define AARCH64_DEBUG_ARCH_V8 0x6
1215 aarch64_arch_setup (void)
1219 struct user_hwdebug_state dreg_state;
1221 current_process ()->tdesc = tdesc_aarch64;
1223 pid = lwpid_of (current_inferior);
1224 iov.iov_base = &dreg_state;
1225 iov.iov_len = sizeof (dreg_state);
1227 /* Get hardware watchpoint register info. */
1228 if (ptrace (PTRACE_GETREGSET, pid, NT_ARM_HW_WATCH, &iov) == 0
1229 && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
1231 aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
1232 if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM)
1234 warning ("Unexpected number of hardware watchpoint registers reported"
1235 " by ptrace, got %d, expected %d.",
1236 aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM);
1237 aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM;
1242 warning ("Unable to determine the number of hardware watchpoints"
1244 aarch64_num_wp_regs = 0;
1247 /* Get hardware breakpoint register info. */
1248 if (ptrace (PTRACE_GETREGSET, pid, NT_ARM_HW_BREAK, &iov) == 0
1249 && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
1251 aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
1252 if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM)
1254 warning ("Unexpected number of hardware breakpoint registers reported"
1255 " by ptrace, got %d, expected %d.",
1256 aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM);
1257 aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM;
1262 warning ("Unable to determine the number of hardware breakpoints"
1264 aarch64_num_bp_regs = 0;
1268 static struct regset_info aarch64_regsets[] =
1270 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS,
1271 sizeof (struct user_pt_regs), GENERAL_REGS,
1272 aarch64_fill_gregset, aarch64_store_gregset },
1273 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET,
1274 sizeof (struct user_fpsimd_state), FP_REGS,
1275 aarch64_fill_fpregset, aarch64_store_fpregset
1277 { 0, 0, 0, -1, -1, NULL, NULL }
1280 static struct regsets_info aarch64_regsets_info =
1282 aarch64_regsets, /* regsets */
1283 0, /* num_regsets */
1284 NULL, /* disabled_regsets */
1287 static struct usrregs_info aarch64_usrregs_info =
1293 static struct regs_info regs_info =
1295 NULL, /* regset_bitmap */
1296 &aarch64_usrregs_info,
1297 &aarch64_regsets_info,
1300 static const struct regs_info *
1301 aarch64_regs_info (void)
1306 struct linux_target_ops the_low_target =
1310 aarch64_cannot_fetch_register,
1311 aarch64_cannot_store_register,
1315 (const unsigned char *) &aarch64_breakpoint,
1316 aarch64_breakpoint_len,
1319 aarch64_breakpoint_at,
1320 aarch64_insert_point,
1321 aarch64_remove_point,
1322 aarch64_stopped_by_watchpoint,
1323 aarch64_stopped_data_address,
1327 aarch64_linux_new_process,
1328 aarch64_linux_new_thread,
1329 aarch64_linux_prepare_to_resume,
1333 initialize_low_arch (void)
1335 init_registers_aarch64 ();
1337 initialize_regsets_info (&aarch64_regsets_info);