1 /* GNU/Linux/AArch64 specific low level interface, for the remote server for
4 Copyright (C) 2009-2017 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "linux-low.h"
24 #include "nat/aarch64-linux.h"
25 #include "nat/aarch64-linux-hw-point.h"
26 #include "arch/aarch64-insn.h"
27 #include "linux-aarch32-low.h"
28 #include "elf/common.h"
30 #include "tracepoint.h"
34 #include "nat/gdb_ptrace.h"
35 #include <asm/ptrace.h>
40 #include "gdb_proc_service.h"
42 /* Defined in auto-generated files. */
43 void init_registers_aarch64 (void);
44 extern const struct target_desc *tdesc_aarch64;
50 #define AARCH64_X_REGS_NUM 31
51 #define AARCH64_V_REGS_NUM 32
52 #define AARCH64_X0_REGNO 0
53 #define AARCH64_SP_REGNO 31
54 #define AARCH64_PC_REGNO 32
55 #define AARCH64_CPSR_REGNO 33
56 #define AARCH64_V0_REGNO 34
57 #define AARCH64_FPSR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM)
58 #define AARCH64_FPCR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 1)
60 #define AARCH64_NUM_REGS (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 2)
62 /* Per-process arch-specific data we want to keep. */
64 struct arch_process_info
66 /* Hardware breakpoint/watchpoint data.
67 The reason for them to be per-process rather than per-thread is
68 due to the lack of information in the gdbserver environment;
69 gdbserver is not told that whether a requested hardware
70 breakpoint/watchpoint is thread specific or not, so it has to set
71 each hw bp/wp for every thread in the current process. The
72 higher level bp/wp management in gdb will resume a thread if a hw
73 bp/wp trap is not expected for it. Since the hw bp/wp setting is
74 same for each thread, it is reasonable for the data to live here.
76 struct aarch64_debug_reg_state debug_reg_state;
79 /* Return true if the size of register 0 is 8 byte. */
84 struct regcache *regcache = get_thread_regcache (current_thread, 0);
86 return register_size (regcache->tdesc, 0) == 8;
89 /* Implementation of linux_target_ops method "cannot_store_register". */
92 aarch64_cannot_store_register (int regno)
94 return regno >= AARCH64_NUM_REGS;
97 /* Implementation of linux_target_ops method "cannot_fetch_register". */
100 aarch64_cannot_fetch_register (int regno)
102 return regno >= AARCH64_NUM_REGS;
106 aarch64_fill_gregset (struct regcache *regcache, void *buf)
108 struct user_pt_regs *regset = (struct user_pt_regs *) buf;
111 for (i = 0; i < AARCH64_X_REGS_NUM; i++)
112 collect_register (regcache, AARCH64_X0_REGNO + i, ®set->regs[i]);
113 collect_register (regcache, AARCH64_SP_REGNO, ®set->sp);
114 collect_register (regcache, AARCH64_PC_REGNO, ®set->pc);
115 collect_register (regcache, AARCH64_CPSR_REGNO, ®set->pstate);
119 aarch64_store_gregset (struct regcache *regcache, const void *buf)
121 const struct user_pt_regs *regset = (const struct user_pt_regs *) buf;
124 for (i = 0; i < AARCH64_X_REGS_NUM; i++)
125 supply_register (regcache, AARCH64_X0_REGNO + i, ®set->regs[i]);
126 supply_register (regcache, AARCH64_SP_REGNO, ®set->sp);
127 supply_register (regcache, AARCH64_PC_REGNO, ®set->pc);
128 supply_register (regcache, AARCH64_CPSR_REGNO, ®set->pstate);
132 aarch64_fill_fpregset (struct regcache *regcache, void *buf)
134 struct user_fpsimd_state *regset = (struct user_fpsimd_state *) buf;
137 for (i = 0; i < AARCH64_V_REGS_NUM; i++)
138 collect_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]);
139 collect_register (regcache, AARCH64_FPSR_REGNO, ®set->fpsr);
140 collect_register (regcache, AARCH64_FPCR_REGNO, ®set->fpcr);
144 aarch64_store_fpregset (struct regcache *regcache, const void *buf)
146 const struct user_fpsimd_state *regset
147 = (const struct user_fpsimd_state *) buf;
150 for (i = 0; i < AARCH64_V_REGS_NUM; i++)
151 supply_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]);
152 supply_register (regcache, AARCH64_FPSR_REGNO, ®set->fpsr);
153 supply_register (regcache, AARCH64_FPCR_REGNO, ®set->fpcr);
156 /* Enable miscellaneous debugging output. The name is historical - it
157 was originally used to debug LinuxThreads support. */
158 extern int debug_threads;
160 /* Implementation of linux_target_ops method "get_pc". */
163 aarch64_get_pc (struct regcache *regcache)
165 if (register_size (regcache->tdesc, 0) == 8)
166 return linux_get_pc_64bit (regcache);
168 return linux_get_pc_32bit (regcache);
171 /* Implementation of linux_target_ops method "set_pc". */
174 aarch64_set_pc (struct regcache *regcache, CORE_ADDR pc)
176 if (register_size (regcache->tdesc, 0) == 8)
177 linux_set_pc_64bit (regcache, pc);
179 linux_set_pc_32bit (regcache, pc);
182 #define aarch64_breakpoint_len 4
184 /* AArch64 BRK software debug mode instruction.
185 This instruction needs to match gdb/aarch64-tdep.c
186 (aarch64_default_breakpoint). */
187 static const gdb_byte aarch64_breakpoint[] = {0x00, 0x00, 0x20, 0xd4};
189 /* Implementation of linux_target_ops method "breakpoint_at". */
192 aarch64_breakpoint_at (CORE_ADDR where)
194 if (is_64bit_tdesc ())
196 gdb_byte insn[aarch64_breakpoint_len];
198 (*the_target->read_memory) (where, (unsigned char *) &insn,
199 aarch64_breakpoint_len);
200 if (memcmp (insn, aarch64_breakpoint, aarch64_breakpoint_len) == 0)
206 return arm_breakpoint_at (where);
210 aarch64_init_debug_reg_state (struct aarch64_debug_reg_state *state)
214 for (i = 0; i < AARCH64_HBP_MAX_NUM; ++i)
216 state->dr_addr_bp[i] = 0;
217 state->dr_ctrl_bp[i] = 0;
218 state->dr_ref_count_bp[i] = 0;
221 for (i = 0; i < AARCH64_HWP_MAX_NUM; ++i)
223 state->dr_addr_wp[i] = 0;
224 state->dr_ctrl_wp[i] = 0;
225 state->dr_ref_count_wp[i] = 0;
229 /* Return the pointer to the debug register state structure in the
230 current process' arch-specific data area. */
232 struct aarch64_debug_reg_state *
233 aarch64_get_debug_reg_state (pid_t pid)
235 struct process_info *proc = find_process_pid (pid);
237 return &proc->priv->arch_private->debug_reg_state;
240 /* Implementation of linux_target_ops method "supports_z_point_type". */
243 aarch64_supports_z_point_type (char z_type)
249 case Z_PACKET_WRITE_WP:
250 case Z_PACKET_READ_WP:
251 case Z_PACKET_ACCESS_WP:
258 /* Implementation of linux_target_ops method "insert_point".
260 It actually only records the info of the to-be-inserted bp/wp;
261 the actual insertion will happen when threads are resumed. */
264 aarch64_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
265 int len, struct raw_breakpoint *bp)
268 enum target_hw_bp_type targ_type;
269 struct aarch64_debug_reg_state *state
270 = aarch64_get_debug_reg_state (pid_of (current_thread));
273 fprintf (stderr, "insert_point on entry (addr=0x%08lx, len=%d)\n",
274 (unsigned long) addr, len);
276 /* Determine the type from the raw breakpoint type. */
277 targ_type = raw_bkpt_type_to_target_hw_bp_type (type);
279 if (targ_type != hw_execute)
281 if (aarch64_linux_region_ok_for_watchpoint (addr, len))
282 ret = aarch64_handle_watchpoint (targ_type, addr, len,
283 1 /* is_insert */, state);
291 /* LEN is 3 means the breakpoint is set on a 32-bit thumb
292 instruction. Set it to 2 to correctly encode length bit
293 mask in hardware/watchpoint control register. */
296 ret = aarch64_handle_breakpoint (targ_type, addr, len,
297 1 /* is_insert */, state);
301 aarch64_show_debug_reg_state (state, "insert_point", addr, len,
307 /* Implementation of linux_target_ops method "remove_point".
309 It actually only records the info of the to-be-removed bp/wp,
310 the actual removal will be done when threads are resumed. */
313 aarch64_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
314 int len, struct raw_breakpoint *bp)
317 enum target_hw_bp_type targ_type;
318 struct aarch64_debug_reg_state *state
319 = aarch64_get_debug_reg_state (pid_of (current_thread));
322 fprintf (stderr, "remove_point on entry (addr=0x%08lx, len=%d)\n",
323 (unsigned long) addr, len);
325 /* Determine the type from the raw breakpoint type. */
326 targ_type = raw_bkpt_type_to_target_hw_bp_type (type);
328 /* Set up state pointers. */
329 if (targ_type != hw_execute)
331 aarch64_handle_watchpoint (targ_type, addr, len, 0 /* is_insert */,
337 /* LEN is 3 means the breakpoint is set on a 32-bit thumb
338 instruction. Set it to 2 to correctly encode length bit
339 mask in hardware/watchpoint control register. */
342 ret = aarch64_handle_breakpoint (targ_type, addr, len,
343 0 /* is_insert */, state);
347 aarch64_show_debug_reg_state (state, "remove_point", addr, len,
353 /* Implementation of linux_target_ops method "stopped_data_address". */
356 aarch64_stopped_data_address (void)
360 struct aarch64_debug_reg_state *state;
362 pid = lwpid_of (current_thread);
364 /* Get the siginfo. */
365 if (ptrace (PTRACE_GETSIGINFO, pid, NULL, &siginfo) != 0)
366 return (CORE_ADDR) 0;
368 /* Need to be a hardware breakpoint/watchpoint trap. */
369 if (siginfo.si_signo != SIGTRAP
370 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
371 return (CORE_ADDR) 0;
373 /* Check if the address matches any watched address. */
374 state = aarch64_get_debug_reg_state (pid_of (current_thread));
375 for (i = aarch64_num_wp_regs - 1; i >= 0; --i)
377 const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]);
378 const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr;
379 const CORE_ADDR addr_watch = state->dr_addr_wp[i];
380 if (state->dr_ref_count_wp[i]
381 && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i])
382 && addr_trap >= addr_watch
383 && addr_trap < addr_watch + len)
387 return (CORE_ADDR) 0;
390 /* Implementation of linux_target_ops method "stopped_by_watchpoint". */
393 aarch64_stopped_by_watchpoint (void)
395 if (aarch64_stopped_data_address () != 0)
401 /* Fetch the thread-local storage pointer for libthread_db. */
404 ps_get_thread_area (struct ps_prochandle *ph,
405 lwpid_t lwpid, int idx, void **base)
407 return aarch64_ps_get_thread_area (ph, lwpid, idx, base,
411 /* Implementation of linux_target_ops method "siginfo_fixup". */
414 aarch64_linux_siginfo_fixup (siginfo_t *native, gdb_byte *inf, int direction)
416 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
417 if (!is_64bit_tdesc ())
420 aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo *) inf,
423 aarch64_siginfo_from_compat_siginfo (native,
424 (struct compat_siginfo *) inf);
432 /* Implementation of linux_target_ops method "linux_new_process". */
434 static struct arch_process_info *
435 aarch64_linux_new_process (void)
437 struct arch_process_info *info = XCNEW (struct arch_process_info);
439 aarch64_init_debug_reg_state (&info->debug_reg_state);
444 /* Implementation of linux_target_ops method "linux_new_fork". */
447 aarch64_linux_new_fork (struct process_info *parent,
448 struct process_info *child)
450 /* These are allocated by linux_add_process. */
451 gdb_assert (parent->priv != NULL
452 && parent->priv->arch_private != NULL);
453 gdb_assert (child->priv != NULL
454 && child->priv->arch_private != NULL);
456 /* Linux kernel before 2.6.33 commit
457 72f674d203cd230426437cdcf7dd6f681dad8b0d
458 will inherit hardware debug registers from parent
459 on fork/vfork/clone. Newer Linux kernels create such tasks with
460 zeroed debug registers.
462 GDB core assumes the child inherits the watchpoints/hw
463 breakpoints of the parent, and will remove them all from the
464 forked off process. Copy the debug registers mirrors into the
465 new process so that all breakpoints and watchpoints can be
466 removed together. The debug registers mirror will become zeroed
467 in the end before detaching the forked off process, thus making
468 this compatible with older Linux kernels too. */
470 *child->priv->arch_private = *parent->priv->arch_private;
473 /* Return the right target description according to the ELF file of
476 static const struct target_desc *
477 aarch64_linux_read_description (void)
479 unsigned int machine;
483 tid = lwpid_of (current_thread);
485 is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine);
488 return tdesc_aarch64;
490 return tdesc_arm_with_neon;
493 /* Implementation of linux_target_ops method "arch_setup". */
496 aarch64_arch_setup (void)
498 current_process ()->tdesc = aarch64_linux_read_description ();
500 aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread));
503 static struct regset_info aarch64_regsets[] =
505 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS,
506 sizeof (struct user_pt_regs), GENERAL_REGS,
507 aarch64_fill_gregset, aarch64_store_gregset },
508 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET,
509 sizeof (struct user_fpsimd_state), FP_REGS,
510 aarch64_fill_fpregset, aarch64_store_fpregset
515 static struct regsets_info aarch64_regsets_info =
517 aarch64_regsets, /* regsets */
519 NULL, /* disabled_regsets */
522 static struct regs_info regs_info_aarch64 =
524 NULL, /* regset_bitmap */
526 &aarch64_regsets_info,
529 /* Implementation of linux_target_ops method "regs_info". */
531 static const struct regs_info *
532 aarch64_regs_info (void)
534 if (is_64bit_tdesc ())
535 return ®s_info_aarch64;
537 return ®s_info_aarch32;
540 /* Implementation of linux_target_ops method "supports_tracepoints". */
543 aarch64_supports_tracepoints (void)
545 if (current_thread == NULL)
549 /* We don't support tracepoints on aarch32 now. */
550 return is_64bit_tdesc ();
554 /* Implementation of linux_target_ops method "get_thread_area". */
557 aarch64_get_thread_area (int lwpid, CORE_ADDR *addrp)
562 iovec.iov_base = ®
563 iovec.iov_len = sizeof (reg);
565 if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0)
573 /* Implementation of linux_target_ops method "get_syscall_trapinfo". */
576 aarch64_get_syscall_trapinfo (struct regcache *regcache, int *sysno)
578 int use_64bit = register_size (regcache->tdesc, 0) == 8;
584 collect_register_by_name (regcache, "x8", &l_sysno);
585 *sysno = (int) l_sysno;
588 collect_register_by_name (regcache, "r7", sysno);
591 /* List of condition codes that we need. */
593 enum aarch64_condition_codes
604 enum aarch64_operand_type
610 /* Representation of an operand. At this time, it only supports register
611 and immediate types. */
613 struct aarch64_operand
615 /* Type of the operand. */
616 enum aarch64_operand_type type;
618 /* Value of the operand according to the type. */
622 struct aarch64_register reg;
626 /* List of registers that we are currently using, we can add more here as
627 we need to use them. */
629 /* General purpose scratch registers (64 bit). */
630 static const struct aarch64_register x0 = { 0, 1 };
631 static const struct aarch64_register x1 = { 1, 1 };
632 static const struct aarch64_register x2 = { 2, 1 };
633 static const struct aarch64_register x3 = { 3, 1 };
634 static const struct aarch64_register x4 = { 4, 1 };
636 /* General purpose scratch registers (32 bit). */
637 static const struct aarch64_register w0 = { 0, 0 };
638 static const struct aarch64_register w2 = { 2, 0 };
640 /* Intra-procedure scratch registers. */
641 static const struct aarch64_register ip0 = { 16, 1 };
643 /* Special purpose registers. */
644 static const struct aarch64_register fp = { 29, 1 };
645 static const struct aarch64_register lr = { 30, 1 };
646 static const struct aarch64_register sp = { 31, 1 };
647 static const struct aarch64_register xzr = { 31, 1 };
649 /* Dynamically allocate a new register. If we know the register
650 statically, we should make it a global as above instead of using this
653 static struct aarch64_register
654 aarch64_register (unsigned num, int is64)
656 return (struct aarch64_register) { num, is64 };
659 /* Helper function to create a register operand, for instructions with
660 different types of operands.
663 p += emit_mov (p, x0, register_operand (x1)); */
665 static struct aarch64_operand
666 register_operand (struct aarch64_register reg)
668 struct aarch64_operand operand;
670 operand.type = OPERAND_REGISTER;
676 /* Helper function to create an immediate operand, for instructions with
677 different types of operands.
680 p += emit_mov (p, x0, immediate_operand (12)); */
682 static struct aarch64_operand
683 immediate_operand (uint32_t imm)
685 struct aarch64_operand operand;
687 operand.type = OPERAND_IMMEDIATE;
693 /* Helper function to create an offset memory operand.
696 p += emit_ldr (p, x0, sp, offset_memory_operand (16)); */
698 static struct aarch64_memory_operand
699 offset_memory_operand (int32_t offset)
701 return (struct aarch64_memory_operand) { MEMORY_OPERAND_OFFSET, offset };
704 /* Helper function to create a pre-index memory operand.
707 p += emit_ldr (p, x0, sp, preindex_memory_operand (16)); */
709 static struct aarch64_memory_operand
710 preindex_memory_operand (int32_t index)
712 return (struct aarch64_memory_operand) { MEMORY_OPERAND_PREINDEX, index };
715 /* Helper function to create a post-index memory operand.
718 p += emit_ldr (p, x0, sp, postindex_memory_operand (16)); */
720 static struct aarch64_memory_operand
721 postindex_memory_operand (int32_t index)
723 return (struct aarch64_memory_operand) { MEMORY_OPERAND_POSTINDEX, index };
726 /* System control registers. These special registers can be written and
727 read with the MRS and MSR instructions.
729 - NZCV: Condition flags. GDB refers to this register under the CPSR
731 - FPSR: Floating-point status register.
732 - FPCR: Floating-point control registers.
733 - TPIDR_EL0: Software thread ID register. */
735 enum aarch64_system_control_registers
737 /* op0 op1 crn crm op2 */
738 NZCV = (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x2 << 3) | 0x0,
739 FPSR = (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x1,
740 FPCR = (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x0,
741 TPIDR_EL0 = (0x1 << 14) | (0x3 << 11) | (0xd << 7) | (0x0 << 3) | 0x2
744 /* Write a BLR instruction into *BUF.
748 RN is the register to branch to. */
751 emit_blr (uint32_t *buf, struct aarch64_register rn)
753 return aarch64_emit_insn (buf, BLR | ENCODE (rn.num, 5, 5));
756 /* Write a RET instruction into *BUF.
760 RN is the register to branch to. */
763 emit_ret (uint32_t *buf, struct aarch64_register rn)
765 return aarch64_emit_insn (buf, RET | ENCODE (rn.num, 5, 5));
769 emit_load_store_pair (uint32_t *buf, enum aarch64_opcodes opcode,
770 struct aarch64_register rt,
771 struct aarch64_register rt2,
772 struct aarch64_register rn,
773 struct aarch64_memory_operand operand)
780 opc = ENCODE (2, 2, 30);
782 opc = ENCODE (0, 2, 30);
784 switch (operand.type)
786 case MEMORY_OPERAND_OFFSET:
788 pre_index = ENCODE (1, 1, 24);
789 write_back = ENCODE (0, 1, 23);
792 case MEMORY_OPERAND_POSTINDEX:
794 pre_index = ENCODE (0, 1, 24);
795 write_back = ENCODE (1, 1, 23);
798 case MEMORY_OPERAND_PREINDEX:
800 pre_index = ENCODE (1, 1, 24);
801 write_back = ENCODE (1, 1, 23);
808 return aarch64_emit_insn (buf, opcode | opc | pre_index | write_back
809 | ENCODE (operand.index >> 3, 7, 15)
810 | ENCODE (rt2.num, 5, 10)
811 | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0));
814 /* Write a STP instruction into *BUF.
816 STP rt, rt2, [rn, #offset]
817 STP rt, rt2, [rn, #index]!
818 STP rt, rt2, [rn], #index
820 RT and RT2 are the registers to store.
821 RN is the base address register.
822 OFFSET is the immediate to add to the base address. It is limited to a
823 -512 .. 504 range (7 bits << 3). */
826 emit_stp (uint32_t *buf, struct aarch64_register rt,
827 struct aarch64_register rt2, struct aarch64_register rn,
828 struct aarch64_memory_operand operand)
830 return emit_load_store_pair (buf, STP, rt, rt2, rn, operand);
833 /* Write a LDP instruction into *BUF.
835 LDP rt, rt2, [rn, #offset]
836 LDP rt, rt2, [rn, #index]!
837 LDP rt, rt2, [rn], #index
839 RT and RT2 are the registers to store.
840 RN is the base address register.
841 OFFSET is the immediate to add to the base address. It is limited to a
842 -512 .. 504 range (7 bits << 3). */
845 emit_ldp (uint32_t *buf, struct aarch64_register rt,
846 struct aarch64_register rt2, struct aarch64_register rn,
847 struct aarch64_memory_operand operand)
849 return emit_load_store_pair (buf, LDP, rt, rt2, rn, operand);
852 /* Write a LDP (SIMD&VFP) instruction using Q registers into *BUF.
854 LDP qt, qt2, [rn, #offset]
856 RT and RT2 are the Q registers to store.
857 RN is the base address register.
858 OFFSET is the immediate to add to the base address. It is limited to
859 -1024 .. 1008 range (7 bits << 4). */
862 emit_ldp_q_offset (uint32_t *buf, unsigned rt, unsigned rt2,
863 struct aarch64_register rn, int32_t offset)
865 uint32_t opc = ENCODE (2, 2, 30);
866 uint32_t pre_index = ENCODE (1, 1, 24);
868 return aarch64_emit_insn (buf, LDP_SIMD_VFP | opc | pre_index
869 | ENCODE (offset >> 4, 7, 15)
870 | ENCODE (rt2, 5, 10)
871 | ENCODE (rn.num, 5, 5) | ENCODE (rt, 5, 0));
874 /* Write a STP (SIMD&VFP) instruction using Q registers into *BUF.
876 STP qt, qt2, [rn, #offset]
878 RT and RT2 are the Q registers to store.
879 RN is the base address register.
880 OFFSET is the immediate to add to the base address. It is limited to
881 -1024 .. 1008 range (7 bits << 4). */
884 emit_stp_q_offset (uint32_t *buf, unsigned rt, unsigned rt2,
885 struct aarch64_register rn, int32_t offset)
887 uint32_t opc = ENCODE (2, 2, 30);
888 uint32_t pre_index = ENCODE (1, 1, 24);
890 return aarch64_emit_insn (buf, STP_SIMD_VFP | opc | pre_index
891 | ENCODE (offset >> 4, 7, 15)
892 | ENCODE (rt2, 5, 10)
893 | ENCODE (rn.num, 5, 5) | ENCODE (rt, 5, 0));
896 /* Write a LDRH instruction into *BUF.
898 LDRH wt, [xn, #offset]
899 LDRH wt, [xn, #index]!
900 LDRH wt, [xn], #index
902 RT is the register to store.
903 RN is the base address register.
904 OFFSET is the immediate to add to the base address. It is limited to
905 0 .. 32760 range (12 bits << 3). */
908 emit_ldrh (uint32_t *buf, struct aarch64_register rt,
909 struct aarch64_register rn,
910 struct aarch64_memory_operand operand)
912 return aarch64_emit_load_store (buf, 1, LDR, rt, rn, operand);
915 /* Write a LDRB instruction into *BUF.
917 LDRB wt, [xn, #offset]
918 LDRB wt, [xn, #index]!
919 LDRB wt, [xn], #index
921 RT is the register to store.
922 RN is the base address register.
923 OFFSET is the immediate to add to the base address. It is limited to
924 0 .. 32760 range (12 bits << 3). */
927 emit_ldrb (uint32_t *buf, struct aarch64_register rt,
928 struct aarch64_register rn,
929 struct aarch64_memory_operand operand)
931 return aarch64_emit_load_store (buf, 0, LDR, rt, rn, operand);
936 /* Write a STR instruction into *BUF.
938 STR rt, [rn, #offset]
939 STR rt, [rn, #index]!
942 RT is the register to store.
943 RN is the base address register.
944 OFFSET is the immediate to add to the base address. It is limited to
945 0 .. 32760 range (12 bits << 3). */
948 emit_str (uint32_t *buf, struct aarch64_register rt,
949 struct aarch64_register rn,
950 struct aarch64_memory_operand operand)
952 return aarch64_emit_load_store (buf, rt.is64 ? 3 : 2, STR, rt, rn, operand);
955 /* Helper function emitting an exclusive load or store instruction. */
958 emit_load_store_exclusive (uint32_t *buf, uint32_t size,
959 enum aarch64_opcodes opcode,
960 struct aarch64_register rs,
961 struct aarch64_register rt,
962 struct aarch64_register rt2,
963 struct aarch64_register rn)
965 return aarch64_emit_insn (buf, opcode | ENCODE (size, 2, 30)
966 | ENCODE (rs.num, 5, 16) | ENCODE (rt2.num, 5, 10)
967 | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0));
970 /* Write a LAXR instruction into *BUF.
974 RT is the destination register.
975 RN is the base address register. */
978 emit_ldaxr (uint32_t *buf, struct aarch64_register rt,
979 struct aarch64_register rn)
981 return emit_load_store_exclusive (buf, rt.is64 ? 3 : 2, LDAXR, xzr, rt,
985 /* Write a STXR instruction into *BUF.
989 RS is the result register, it indicates if the store succeeded or not.
990 RT is the destination register.
991 RN is the base address register. */
994 emit_stxr (uint32_t *buf, struct aarch64_register rs,
995 struct aarch64_register rt, struct aarch64_register rn)
997 return emit_load_store_exclusive (buf, rt.is64 ? 3 : 2, STXR, rs, rt,
1001 /* Write a STLR instruction into *BUF.
1005 RT is the register to store.
1006 RN is the base address register. */
1009 emit_stlr (uint32_t *buf, struct aarch64_register rt,
1010 struct aarch64_register rn)
1012 return emit_load_store_exclusive (buf, rt.is64 ? 3 : 2, STLR, xzr, rt,
1016 /* Helper function for data processing instructions with register sources. */
1019 emit_data_processing_reg (uint32_t *buf, uint32_t opcode,
1020 struct aarch64_register rd,
1021 struct aarch64_register rn,
1022 struct aarch64_register rm)
1024 uint32_t size = ENCODE (rd.is64, 1, 31);
1026 return aarch64_emit_insn (buf, opcode | size | ENCODE (rm.num, 5, 16)
1027 | ENCODE (rn.num, 5, 5) | ENCODE (rd.num, 5, 0));
1030 /* Helper function for data processing instructions taking either a register
1034 emit_data_processing (uint32_t *buf, enum aarch64_opcodes opcode,
1035 struct aarch64_register rd,
1036 struct aarch64_register rn,
1037 struct aarch64_operand operand)
1039 uint32_t size = ENCODE (rd.is64, 1, 31);
1040 /* The opcode is different for register and immediate source operands. */
1041 uint32_t operand_opcode;
1043 if (operand.type == OPERAND_IMMEDIATE)
1045 /* xxx1 000x xxxx xxxx xxxx xxxx xxxx xxxx */
1046 operand_opcode = ENCODE (8, 4, 25);
1048 return aarch64_emit_insn (buf, opcode | operand_opcode | size
1049 | ENCODE (operand.imm, 12, 10)
1050 | ENCODE (rn.num, 5, 5)
1051 | ENCODE (rd.num, 5, 0));
1055 /* xxx0 101x xxxx xxxx xxxx xxxx xxxx xxxx */
1056 operand_opcode = ENCODE (5, 4, 25);
1058 return emit_data_processing_reg (buf, opcode | operand_opcode, rd,
1063 /* Write an ADD instruction into *BUF.
1068 This function handles both an immediate and register add.
1070 RD is the destination register.
1071 RN is the input register.
1072 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
1073 OPERAND_REGISTER. */
1076 emit_add (uint32_t *buf, struct aarch64_register rd,
1077 struct aarch64_register rn, struct aarch64_operand operand)
1079 return emit_data_processing (buf, ADD, rd, rn, operand);
1082 /* Write a SUB instruction into *BUF.
1087 This function handles both an immediate and register sub.
1089 RD is the destination register.
1090 RN is the input register.
1091 IMM is the immediate to substract to RN. */
1094 emit_sub (uint32_t *buf, struct aarch64_register rd,
1095 struct aarch64_register rn, struct aarch64_operand operand)
1097 return emit_data_processing (buf, SUB, rd, rn, operand);
1100 /* Write a MOV instruction into *BUF.
1105 This function handles both a wide immediate move and a register move,
1106 with the condition that the source register is not xzr. xzr and the
1107 stack pointer share the same encoding and this function only supports
1110 RD is the destination register.
1111 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
1112 OPERAND_REGISTER. */
1115 emit_mov (uint32_t *buf, struct aarch64_register rd,
1116 struct aarch64_operand operand)
1118 if (operand.type == OPERAND_IMMEDIATE)
1120 uint32_t size = ENCODE (rd.is64, 1, 31);
1121 /* Do not shift the immediate. */
1122 uint32_t shift = ENCODE (0, 2, 21);
1124 return aarch64_emit_insn (buf, MOV | size | shift
1125 | ENCODE (operand.imm, 16, 5)
1126 | ENCODE (rd.num, 5, 0));
1129 return emit_add (buf, rd, operand.reg, immediate_operand (0));
1132 /* Write a MOVK instruction into *BUF.
1134 MOVK rd, #imm, lsl #shift
1136 RD is the destination register.
1137 IMM is the immediate.
1138 SHIFT is the logical shift left to apply to IMM. */
1141 emit_movk (uint32_t *buf, struct aarch64_register rd, uint32_t imm,
1144 uint32_t size = ENCODE (rd.is64, 1, 31);
1146 return aarch64_emit_insn (buf, MOVK | size | ENCODE (shift, 2, 21) |
1147 ENCODE (imm, 16, 5) | ENCODE (rd.num, 5, 0));
1150 /* Write instructions into *BUF in order to move ADDR into a register.
1151 ADDR can be a 64-bit value.
1153 This function will emit a series of MOV and MOVK instructions, such as:
1156 MOVK xd, #(addr >> 16), lsl #16
1157 MOVK xd, #(addr >> 32), lsl #32
1158 MOVK xd, #(addr >> 48), lsl #48 */
1161 emit_mov_addr (uint32_t *buf, struct aarch64_register rd, CORE_ADDR addr)
1165 /* The MOV (wide immediate) instruction clears to top bits of the
1167 p += emit_mov (p, rd, immediate_operand (addr & 0xffff));
1169 if ((addr >> 16) != 0)
1170 p += emit_movk (p, rd, (addr >> 16) & 0xffff, 1);
1174 if ((addr >> 32) != 0)
1175 p += emit_movk (p, rd, (addr >> 32) & 0xffff, 2);
1179 if ((addr >> 48) != 0)
1180 p += emit_movk (p, rd, (addr >> 48) & 0xffff, 3);
1185 /* Write a SUBS instruction into *BUF.
1189 This instruction update the condition flags.
1191 RD is the destination register.
1192 RN and RM are the source registers. */
1195 emit_subs (uint32_t *buf, struct aarch64_register rd,
1196 struct aarch64_register rn, struct aarch64_operand operand)
1198 return emit_data_processing (buf, SUBS, rd, rn, operand);
1201 /* Write a CMP instruction into *BUF.
1205 This instruction is an alias of SUBS xzr, rn, rm.
1207 RN and RM are the registers to compare. */
1210 emit_cmp (uint32_t *buf, struct aarch64_register rn,
1211 struct aarch64_operand operand)
1213 return emit_subs (buf, xzr, rn, operand);
1216 /* Write a AND instruction into *BUF.
1220 RD is the destination register.
1221 RN and RM are the source registers. */
1224 emit_and (uint32_t *buf, struct aarch64_register rd,
1225 struct aarch64_register rn, struct aarch64_register rm)
1227 return emit_data_processing_reg (buf, AND, rd, rn, rm);
1230 /* Write a ORR instruction into *BUF.
1234 RD is the destination register.
1235 RN and RM are the source registers. */
1238 emit_orr (uint32_t *buf, struct aarch64_register rd,
1239 struct aarch64_register rn, struct aarch64_register rm)
1241 return emit_data_processing_reg (buf, ORR, rd, rn, rm);
1244 /* Write a ORN instruction into *BUF.
1248 RD is the destination register.
1249 RN and RM are the source registers. */
1252 emit_orn (uint32_t *buf, struct aarch64_register rd,
1253 struct aarch64_register rn, struct aarch64_register rm)
1255 return emit_data_processing_reg (buf, ORN, rd, rn, rm);
1258 /* Write a EOR instruction into *BUF.
1262 RD is the destination register.
1263 RN and RM are the source registers. */
1266 emit_eor (uint32_t *buf, struct aarch64_register rd,
1267 struct aarch64_register rn, struct aarch64_register rm)
1269 return emit_data_processing_reg (buf, EOR, rd, rn, rm);
1272 /* Write a MVN instruction into *BUF.
1276 This is an alias for ORN rd, xzr, rm.
1278 RD is the destination register.
1279 RM is the source register. */
1282 emit_mvn (uint32_t *buf, struct aarch64_register rd,
1283 struct aarch64_register rm)
1285 return emit_orn (buf, rd, xzr, rm);
1288 /* Write a LSLV instruction into *BUF.
1292 RD is the destination register.
1293 RN and RM are the source registers. */
1296 emit_lslv (uint32_t *buf, struct aarch64_register rd,
1297 struct aarch64_register rn, struct aarch64_register rm)
1299 return emit_data_processing_reg (buf, LSLV, rd, rn, rm);
1302 /* Write a LSRV instruction into *BUF.
1306 RD is the destination register.
1307 RN and RM are the source registers. */
1310 emit_lsrv (uint32_t *buf, struct aarch64_register rd,
1311 struct aarch64_register rn, struct aarch64_register rm)
1313 return emit_data_processing_reg (buf, LSRV, rd, rn, rm);
1316 /* Write a ASRV instruction into *BUF.
1320 RD is the destination register.
1321 RN and RM are the source registers. */
1324 emit_asrv (uint32_t *buf, struct aarch64_register rd,
1325 struct aarch64_register rn, struct aarch64_register rm)
1327 return emit_data_processing_reg (buf, ASRV, rd, rn, rm);
1330 /* Write a MUL instruction into *BUF.
1334 RD is the destination register.
1335 RN and RM are the source registers. */
1338 emit_mul (uint32_t *buf, struct aarch64_register rd,
1339 struct aarch64_register rn, struct aarch64_register rm)
1341 return emit_data_processing_reg (buf, MUL, rd, rn, rm);
1344 /* Write a MRS instruction into *BUF. The register size is 64-bit.
1348 RT is the destination register.
1349 SYSTEM_REG is special purpose register to read. */
1352 emit_mrs (uint32_t *buf, struct aarch64_register rt,
1353 enum aarch64_system_control_registers system_reg)
1355 return aarch64_emit_insn (buf, MRS | ENCODE (system_reg, 15, 5)
1356 | ENCODE (rt.num, 5, 0));
1359 /* Write a MSR instruction into *BUF. The register size is 64-bit.
1363 SYSTEM_REG is special purpose register to write.
1364 RT is the input register. */
1367 emit_msr (uint32_t *buf, enum aarch64_system_control_registers system_reg,
1368 struct aarch64_register rt)
1370 return aarch64_emit_insn (buf, MSR | ENCODE (system_reg, 15, 5)
1371 | ENCODE (rt.num, 5, 0));
1374 /* Write a SEVL instruction into *BUF.
1376 This is a hint instruction telling the hardware to trigger an event. */
1379 emit_sevl (uint32_t *buf)
1381 return aarch64_emit_insn (buf, SEVL);
1384 /* Write a WFE instruction into *BUF.
1386 This is a hint instruction telling the hardware to wait for an event. */
1389 emit_wfe (uint32_t *buf)
1391 return aarch64_emit_insn (buf, WFE);
1394 /* Write a SBFM instruction into *BUF.
1396 SBFM rd, rn, #immr, #imms
1398 This instruction moves the bits from #immr to #imms into the
1399 destination, sign extending the result.
1401 RD is the destination register.
1402 RN is the source register.
1403 IMMR is the bit number to start at (least significant bit).
1404 IMMS is the bit number to stop at (most significant bit). */
1407 emit_sbfm (uint32_t *buf, struct aarch64_register rd,
1408 struct aarch64_register rn, uint32_t immr, uint32_t imms)
1410 uint32_t size = ENCODE (rd.is64, 1, 31);
1411 uint32_t n = ENCODE (rd.is64, 1, 22);
1413 return aarch64_emit_insn (buf, SBFM | size | n | ENCODE (immr, 6, 16)
1414 | ENCODE (imms, 6, 10) | ENCODE (rn.num, 5, 5)
1415 | ENCODE (rd.num, 5, 0));
1418 /* Write a SBFX instruction into *BUF.
1420 SBFX rd, rn, #lsb, #width
1422 This instruction moves #width bits from #lsb into the destination, sign
1423 extending the result. This is an alias for:
1425 SBFM rd, rn, #lsb, #(lsb + width - 1)
1427 RD is the destination register.
1428 RN is the source register.
1429 LSB is the bit number to start at (least significant bit).
1430 WIDTH is the number of bits to move. */
1433 emit_sbfx (uint32_t *buf, struct aarch64_register rd,
1434 struct aarch64_register rn, uint32_t lsb, uint32_t width)
1436 return emit_sbfm (buf, rd, rn, lsb, lsb + width - 1);
1439 /* Write a UBFM instruction into *BUF.
1441 UBFM rd, rn, #immr, #imms
1443 This instruction moves the bits from #immr to #imms into the
1444 destination, extending the result with zeros.
1446 RD is the destination register.
1447 RN is the source register.
1448 IMMR is the bit number to start at (least significant bit).
1449 IMMS is the bit number to stop at (most significant bit). */
1452 emit_ubfm (uint32_t *buf, struct aarch64_register rd,
1453 struct aarch64_register rn, uint32_t immr, uint32_t imms)
1455 uint32_t size = ENCODE (rd.is64, 1, 31);
1456 uint32_t n = ENCODE (rd.is64, 1, 22);
1458 return aarch64_emit_insn (buf, UBFM | size | n | ENCODE (immr, 6, 16)
1459 | ENCODE (imms, 6, 10) | ENCODE (rn.num, 5, 5)
1460 | ENCODE (rd.num, 5, 0));
1463 /* Write a UBFX instruction into *BUF.
1465 UBFX rd, rn, #lsb, #width
1467 This instruction moves #width bits from #lsb into the destination,
1468 extending the result with zeros. This is an alias for:
1470 UBFM rd, rn, #lsb, #(lsb + width - 1)
1472 RD is the destination register.
1473 RN is the source register.
1474 LSB is the bit number to start at (least significant bit).
1475 WIDTH is the number of bits to move. */
1478 emit_ubfx (uint32_t *buf, struct aarch64_register rd,
1479 struct aarch64_register rn, uint32_t lsb, uint32_t width)
1481 return emit_ubfm (buf, rd, rn, lsb, lsb + width - 1);
1484 /* Write a CSINC instruction into *BUF.
1486 CSINC rd, rn, rm, cond
1488 This instruction conditionally increments rn or rm and places the result
1489 in rd. rn is chosen is the condition is true.
1491 RD is the destination register.
1492 RN and RM are the source registers.
1493 COND is the encoded condition. */
1496 emit_csinc (uint32_t *buf, struct aarch64_register rd,
1497 struct aarch64_register rn, struct aarch64_register rm,
1500 uint32_t size = ENCODE (rd.is64, 1, 31);
1502 return aarch64_emit_insn (buf, CSINC | size | ENCODE (rm.num, 5, 16)
1503 | ENCODE (cond, 4, 12) | ENCODE (rn.num, 5, 5)
1504 | ENCODE (rd.num, 5, 0));
1507 /* Write a CSET instruction into *BUF.
1511 This instruction conditionally write 1 or 0 in the destination register.
1512 1 is written if the condition is true. This is an alias for:
1514 CSINC rd, xzr, xzr, !cond
1516 Note that the condition needs to be inverted.
1518 RD is the destination register.
1519 RN and RM are the source registers.
1520 COND is the encoded condition. */
1523 emit_cset (uint32_t *buf, struct aarch64_register rd, unsigned cond)
1525 /* The least significant bit of the condition needs toggling in order to
1527 return emit_csinc (buf, rd, xzr, xzr, cond ^ 0x1);
1530 /* Write LEN instructions from BUF into the inferior memory at *TO.
1532 Note instructions are always little endian on AArch64, unlike data. */
1535 append_insns (CORE_ADDR *to, size_t len, const uint32_t *buf)
1537 size_t byte_len = len * sizeof (uint32_t);
1538 #if (__BYTE_ORDER == __BIG_ENDIAN)
1539 uint32_t *le_buf = (uint32_t *) xmalloc (byte_len);
1542 for (i = 0; i < len; i++)
1543 le_buf[i] = htole32 (buf[i]);
1545 write_inferior_memory (*to, (const unsigned char *) le_buf, byte_len);
1549 write_inferior_memory (*to, (const unsigned char *) buf, byte_len);
1555 /* Sub-class of struct aarch64_insn_data, store information of
1556 instruction relocation for fast tracepoint. Visitor can
1557 relocate an instruction from BASE.INSN_ADDR to NEW_ADDR and save
1558 the relocated instructions in buffer pointed by INSN_PTR. */
1560 struct aarch64_insn_relocation_data
1562 struct aarch64_insn_data base;
1564 /* The new address the instruction is relocated to. */
1566 /* Pointer to the buffer of relocated instruction(s). */
1570 /* Implementation of aarch64_insn_visitor method "b". */
1573 aarch64_ftrace_insn_reloc_b (const int is_bl, const int32_t offset,
1574 struct aarch64_insn_data *data)
1576 struct aarch64_insn_relocation_data *insn_reloc
1577 = (struct aarch64_insn_relocation_data *) data;
1579 = insn_reloc->base.insn_addr - insn_reloc->new_addr + offset;
1581 if (can_encode_int32 (new_offset, 28))
1582 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, is_bl, new_offset);
1585 /* Implementation of aarch64_insn_visitor method "b_cond". */
1588 aarch64_ftrace_insn_reloc_b_cond (const unsigned cond, const int32_t offset,
1589 struct aarch64_insn_data *data)
1591 struct aarch64_insn_relocation_data *insn_reloc
1592 = (struct aarch64_insn_relocation_data *) data;
1594 = insn_reloc->base.insn_addr - insn_reloc->new_addr + offset;
1596 if (can_encode_int32 (new_offset, 21))
1598 insn_reloc->insn_ptr += emit_bcond (insn_reloc->insn_ptr, cond,
1601 else if (can_encode_int32 (new_offset, 28))
1603 /* The offset is out of range for a conditional branch
1604 instruction but not for a unconditional branch. We can use
1605 the following instructions instead:
1607 B.COND TAKEN ; If cond is true, then jump to TAKEN.
1608 B NOT_TAKEN ; Else jump over TAKEN and continue.
1615 insn_reloc->insn_ptr += emit_bcond (insn_reloc->insn_ptr, cond, 8);
1616 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0, 8);
1617 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0, new_offset - 8);
1621 /* Implementation of aarch64_insn_visitor method "cb". */
1624 aarch64_ftrace_insn_reloc_cb (const int32_t offset, const int is_cbnz,
1625 const unsigned rn, int is64,
1626 struct aarch64_insn_data *data)
1628 struct aarch64_insn_relocation_data *insn_reloc
1629 = (struct aarch64_insn_relocation_data *) data;
1631 = insn_reloc->base.insn_addr - insn_reloc->new_addr + offset;
1633 if (can_encode_int32 (new_offset, 21))
1635 insn_reloc->insn_ptr += emit_cb (insn_reloc->insn_ptr, is_cbnz,
1636 aarch64_register (rn, is64), new_offset);
1638 else if (can_encode_int32 (new_offset, 28))
1640 /* The offset is out of range for a compare and branch
1641 instruction but not for a unconditional branch. We can use
1642 the following instructions instead:
1644 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
1645 B NOT_TAKEN ; Else jump over TAKEN and continue.
1651 insn_reloc->insn_ptr += emit_cb (insn_reloc->insn_ptr, is_cbnz,
1652 aarch64_register (rn, is64), 8);
1653 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0, 8);
1654 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0, new_offset - 8);
1658 /* Implementation of aarch64_insn_visitor method "tb". */
1661 aarch64_ftrace_insn_reloc_tb (const int32_t offset, int is_tbnz,
1662 const unsigned rt, unsigned bit,
1663 struct aarch64_insn_data *data)
1665 struct aarch64_insn_relocation_data *insn_reloc
1666 = (struct aarch64_insn_relocation_data *) data;
1668 = insn_reloc->base.insn_addr - insn_reloc->new_addr + offset;
1670 if (can_encode_int32 (new_offset, 16))
1672 insn_reloc->insn_ptr += emit_tb (insn_reloc->insn_ptr, is_tbnz, bit,
1673 aarch64_register (rt, 1), new_offset);
1675 else if (can_encode_int32 (new_offset, 28))
1677 /* The offset is out of range for a test bit and branch
1678 instruction but not for a unconditional branch. We can use
1679 the following instructions instead:
1681 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
1682 B NOT_TAKEN ; Else jump over TAKEN and continue.
1688 insn_reloc->insn_ptr += emit_tb (insn_reloc->insn_ptr, is_tbnz, bit,
1689 aarch64_register (rt, 1), 8);
1690 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0, 8);
1691 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0,
1696 /* Implementation of aarch64_insn_visitor method "adr". */
1699 aarch64_ftrace_insn_reloc_adr (const int32_t offset, const unsigned rd,
1701 struct aarch64_insn_data *data)
1703 struct aarch64_insn_relocation_data *insn_reloc
1704 = (struct aarch64_insn_relocation_data *) data;
1705 /* We know exactly the address the ADR{P,} instruction will compute.
1706 We can just write it to the destination register. */
1707 CORE_ADDR address = data->insn_addr + offset;
1711 /* Clear the lower 12 bits of the offset to get the 4K page. */
1712 insn_reloc->insn_ptr += emit_mov_addr (insn_reloc->insn_ptr,
1713 aarch64_register (rd, 1),
1717 insn_reloc->insn_ptr += emit_mov_addr (insn_reloc->insn_ptr,
1718 aarch64_register (rd, 1), address);
1721 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
1724 aarch64_ftrace_insn_reloc_ldr_literal (const int32_t offset, const int is_sw,
1725 const unsigned rt, const int is64,
1726 struct aarch64_insn_data *data)
1728 struct aarch64_insn_relocation_data *insn_reloc
1729 = (struct aarch64_insn_relocation_data *) data;
1730 CORE_ADDR address = data->insn_addr + offset;
1732 insn_reloc->insn_ptr += emit_mov_addr (insn_reloc->insn_ptr,
1733 aarch64_register (rt, 1), address);
1735 /* We know exactly what address to load from, and what register we
1738 MOV xd, #(oldloc + offset)
1739 MOVK xd, #((oldloc + offset) >> 16), lsl #16
1742 LDR xd, [xd] ; or LDRSW xd, [xd]
1747 insn_reloc->insn_ptr += emit_ldrsw (insn_reloc->insn_ptr,
1748 aarch64_register (rt, 1),
1749 aarch64_register (rt, 1),
1750 offset_memory_operand (0));
1752 insn_reloc->insn_ptr += emit_ldr (insn_reloc->insn_ptr,
1753 aarch64_register (rt, is64),
1754 aarch64_register (rt, 1),
1755 offset_memory_operand (0));
1758 /* Implementation of aarch64_insn_visitor method "others". */
1761 aarch64_ftrace_insn_reloc_others (const uint32_t insn,
1762 struct aarch64_insn_data *data)
1764 struct aarch64_insn_relocation_data *insn_reloc
1765 = (struct aarch64_insn_relocation_data *) data;
1767 /* The instruction is not PC relative. Just re-emit it at the new
1769 insn_reloc->insn_ptr += aarch64_emit_insn (insn_reloc->insn_ptr, insn);
1772 static const struct aarch64_insn_visitor visitor =
1774 aarch64_ftrace_insn_reloc_b,
1775 aarch64_ftrace_insn_reloc_b_cond,
1776 aarch64_ftrace_insn_reloc_cb,
1777 aarch64_ftrace_insn_reloc_tb,
1778 aarch64_ftrace_insn_reloc_adr,
1779 aarch64_ftrace_insn_reloc_ldr_literal,
1780 aarch64_ftrace_insn_reloc_others,
1783 /* Implementation of linux_target_ops method
1784 "install_fast_tracepoint_jump_pad". */
1787 aarch64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint,
1789 CORE_ADDR collector,
1792 CORE_ADDR *jump_entry,
1793 CORE_ADDR *trampoline,
1794 ULONGEST *trampoline_size,
1795 unsigned char *jjump_pad_insn,
1796 ULONGEST *jjump_pad_insn_size,
1797 CORE_ADDR *adjusted_insn_addr,
1798 CORE_ADDR *adjusted_insn_addr_end,
1806 CORE_ADDR buildaddr = *jump_entry;
1807 struct aarch64_insn_relocation_data insn_data;
1809 /* We need to save the current state on the stack both to restore it
1810 later and to collect register values when the tracepoint is hit.
1812 The saved registers are pushed in a layout that needs to be in sync
1813 with aarch64_ft_collect_regmap (see linux-aarch64-ipa.c). Later on
1814 the supply_fast_tracepoint_registers function will fill in the
1815 register cache from a pointer to saved registers on the stack we build
1818 For simplicity, we set the size of each cell on the stack to 16 bytes.
1819 This way one cell can hold any register type, from system registers
1820 to the 128 bit SIMD&FP registers. Furthermore, the stack pointer
1821 has to be 16 bytes aligned anyway.
1823 Note that the CPSR register does not exist on AArch64. Instead we
1824 can access system bits describing the process state with the
1825 MRS/MSR instructions, namely the condition flags. We save them as
1826 if they are part of a CPSR register because that's how GDB
1827 interprets these system bits. At the moment, only the condition
1828 flags are saved in CPSR (NZCV).
1830 Stack layout, each cell is 16 bytes (descending):
1832 High *-------- SIMD&FP registers from 31 down to 0. --------*
1838 *---- General purpose registers from 30 down to 0. ----*
1844 *------------- Special purpose registers. -------------*
1847 | CPSR (NZCV) | 5 cells
1850 *------------- collecting_t object --------------------*
1851 | TPIDR_EL0 | struct tracepoint * |
1852 Low *------------------------------------------------------*
1854 After this stack is set up, we issue a call to the collector, passing
1855 it the saved registers at (SP + 16). */
1857 /* Push SIMD&FP registers on the stack:
1859 SUB sp, sp, #(32 * 16)
1861 STP q30, q31, [sp, #(30 * 16)]
1866 p += emit_sub (p, sp, sp, immediate_operand (32 * 16));
1867 for (i = 30; i >= 0; i -= 2)
1868 p += emit_stp_q_offset (p, i, i + 1, sp, i * 16);
1870 /* Push general puspose registers on the stack. Note that we do not need
1871 to push x31 as it represents the xzr register and not the stack
1872 pointer in a STR instruction.
1874 SUB sp, sp, #(31 * 16)
1876 STR x30, [sp, #(30 * 16)]
1881 p += emit_sub (p, sp, sp, immediate_operand (31 * 16));
1882 for (i = 30; i >= 0; i -= 1)
1883 p += emit_str (p, aarch64_register (i, 1), sp,
1884 offset_memory_operand (i * 16));
1886 /* Make space for 5 more cells.
1888 SUB sp, sp, #(5 * 16)
1891 p += emit_sub (p, sp, sp, immediate_operand (5 * 16));
1896 ADD x4, sp, #((32 + 31 + 5) * 16)
1897 STR x4, [sp, #(4 * 16)]
1900 p += emit_add (p, x4, sp, immediate_operand ((32 + 31 + 5) * 16));
1901 p += emit_str (p, x4, sp, offset_memory_operand (4 * 16));
1903 /* Save PC (tracepoint address):
1908 STR x3, [sp, #(3 * 16)]
1912 p += emit_mov_addr (p, x3, tpaddr);
1913 p += emit_str (p, x3, sp, offset_memory_operand (3 * 16));
1915 /* Save CPSR (NZCV), FPSR and FPCR:
1921 STR x2, [sp, #(2 * 16)]
1922 STR x1, [sp, #(1 * 16)]
1923 STR x0, [sp, #(0 * 16)]
1926 p += emit_mrs (p, x2, NZCV);
1927 p += emit_mrs (p, x1, FPSR);
1928 p += emit_mrs (p, x0, FPCR);
1929 p += emit_str (p, x2, sp, offset_memory_operand (2 * 16));
1930 p += emit_str (p, x1, sp, offset_memory_operand (1 * 16));
1931 p += emit_str (p, x0, sp, offset_memory_operand (0 * 16));
1933 /* Push the collecting_t object. It consist of the address of the
1934 tracepoint and an ID for the current thread. We get the latter by
1935 reading the tpidr_el0 system register. It corresponds to the
1936 NT_ARM_TLS register accessible with ptrace.
1943 STP x0, x1, [sp, #-16]!
1947 p += emit_mov_addr (p, x0, tpoint);
1948 p += emit_mrs (p, x1, TPIDR_EL0);
1949 p += emit_stp (p, x0, x1, sp, preindex_memory_operand (-16));
1953 The shared memory for the lock is at lockaddr. It will hold zero
1954 if no-one is holding the lock, otherwise it contains the address of
1955 the collecting_t object on the stack of the thread which acquired it.
1957 At this stage, the stack pointer points to this thread's collecting_t
1960 We use the following registers:
1961 - x0: Address of the lock.
1962 - x1: Pointer to collecting_t object.
1963 - x2: Scratch register.
1969 ; Trigger an event local to this core. So the following WFE
1970 ; instruction is ignored.
1973 ; Wait for an event. The event is triggered by either the SEVL
1974 ; or STLR instructions (store release).
1977 ; Atomically read at lockaddr. This marks the memory location as
1978 ; exclusive. This instruction also has memory constraints which
1979 ; make sure all previous data reads and writes are done before
1983 ; Try again if another thread holds the lock.
1986 ; We can lock it! Write the address of the collecting_t object.
1987 ; This instruction will fail if the memory location is not marked
1988 ; as exclusive anymore. If it succeeds, it will remove the
1989 ; exclusive mark on the memory location. This way, if another
1990 ; thread executes this instruction before us, we will fail and try
1997 p += emit_mov_addr (p, x0, lockaddr);
1998 p += emit_mov (p, x1, register_operand (sp));
2002 p += emit_ldaxr (p, x2, x0);
2003 p += emit_cb (p, 1, w2, -2 * 4);
2004 p += emit_stxr (p, w2, x1, x0);
2005 p += emit_cb (p, 1, x2, -4 * 4);
2007 /* Call collector (struct tracepoint *, unsigned char *):
2012 ; Saved registers start after the collecting_t object.
2015 ; We use an intra-procedure-call scratch register.
2016 MOV ip0, #(collector)
2019 ; And call back to C!
2024 p += emit_mov_addr (p, x0, tpoint);
2025 p += emit_add (p, x1, sp, immediate_operand (16));
2027 p += emit_mov_addr (p, ip0, collector);
2028 p += emit_blr (p, ip0);
2030 /* Release the lock.
2035 ; This instruction is a normal store with memory ordering
2036 ; constraints. Thanks to this we do not have to put a data
2037 ; barrier instruction to make sure all data read and writes are done
2038 ; before this instruction is executed. Furthermore, this instrucion
2039 ; will trigger an event, letting other threads know they can grab
2044 p += emit_mov_addr (p, x0, lockaddr);
2045 p += emit_stlr (p, xzr, x0);
2047 /* Free collecting_t object:
2052 p += emit_add (p, sp, sp, immediate_operand (16));
2054 /* Restore CPSR (NZCV), FPSR and FPCR. And free all special purpose
2055 registers from the stack.
2057 LDR x2, [sp, #(2 * 16)]
2058 LDR x1, [sp, #(1 * 16)]
2059 LDR x0, [sp, #(0 * 16)]
2065 ADD sp, sp #(5 * 16)
2068 p += emit_ldr (p, x2, sp, offset_memory_operand (2 * 16));
2069 p += emit_ldr (p, x1, sp, offset_memory_operand (1 * 16));
2070 p += emit_ldr (p, x0, sp, offset_memory_operand (0 * 16));
2071 p += emit_msr (p, NZCV, x2);
2072 p += emit_msr (p, FPSR, x1);
2073 p += emit_msr (p, FPCR, x0);
2075 p += emit_add (p, sp, sp, immediate_operand (5 * 16));
2077 /* Pop general purpose registers:
2081 LDR x30, [sp, #(30 * 16)]
2083 ADD sp, sp, #(31 * 16)
2086 for (i = 0; i <= 30; i += 1)
2087 p += emit_ldr (p, aarch64_register (i, 1), sp,
2088 offset_memory_operand (i * 16));
2089 p += emit_add (p, sp, sp, immediate_operand (31 * 16));
2091 /* Pop SIMD&FP registers:
2095 LDP q30, q31, [sp, #(30 * 16)]
2097 ADD sp, sp, #(32 * 16)
2100 for (i = 0; i <= 30; i += 2)
2101 p += emit_ldp_q_offset (p, i, i + 1, sp, i * 16);
2102 p += emit_add (p, sp, sp, immediate_operand (32 * 16));
2104 /* Write the code into the inferior memory. */
2105 append_insns (&buildaddr, p - buf, buf);
2107 /* Now emit the relocated instruction. */
2108 *adjusted_insn_addr = buildaddr;
2109 target_read_uint32 (tpaddr, &insn);
2111 insn_data.base.insn_addr = tpaddr;
2112 insn_data.new_addr = buildaddr;
2113 insn_data.insn_ptr = buf;
2115 aarch64_relocate_instruction (insn, &visitor,
2116 (struct aarch64_insn_data *) &insn_data);
2118 /* We may not have been able to relocate the instruction. */
2119 if (insn_data.insn_ptr == buf)
2122 "E.Could not relocate instruction from %s to %s.",
2123 core_addr_to_string_nz (tpaddr),
2124 core_addr_to_string_nz (buildaddr));
2128 append_insns (&buildaddr, insn_data.insn_ptr - buf, buf);
2129 *adjusted_insn_addr_end = buildaddr;
2131 /* Go back to the start of the buffer. */
2134 /* Emit a branch back from the jump pad. */
2135 offset = (tpaddr + orig_size - buildaddr);
2136 if (!can_encode_int32 (offset, 28))
2139 "E.Jump back from jump pad too far from tracepoint "
2140 "(offset 0x%" PRIx64 " cannot be encoded in 28 bits).",
2145 p += emit_b (p, 0, offset);
2146 append_insns (&buildaddr, p - buf, buf);
2148 /* Give the caller a branch instruction into the jump pad. */
2149 offset = (*jump_entry - tpaddr);
2150 if (!can_encode_int32 (offset, 28))
2153 "E.Jump pad too far from tracepoint "
2154 "(offset 0x%" PRIx64 " cannot be encoded in 28 bits).",
2159 emit_b ((uint32_t *) jjump_pad_insn, 0, offset);
2160 *jjump_pad_insn_size = 4;
2162 /* Return the end address of our pad. */
2163 *jump_entry = buildaddr;
2168 /* Helper function writing LEN instructions from START into
2169 current_insn_ptr. */
2172 emit_ops_insns (const uint32_t *start, int len)
2174 CORE_ADDR buildaddr = current_insn_ptr;
2177 debug_printf ("Adding %d instrucions at %s\n",
2178 len, paddress (buildaddr));
2180 append_insns (&buildaddr, len, start);
2181 current_insn_ptr = buildaddr;
2184 /* Pop a register from the stack. */
2187 emit_pop (uint32_t *buf, struct aarch64_register rt)
2189 return emit_ldr (buf, rt, sp, postindex_memory_operand (1 * 16));
2192 /* Push a register on the stack. */
2195 emit_push (uint32_t *buf, struct aarch64_register rt)
2197 return emit_str (buf, rt, sp, preindex_memory_operand (-1 * 16));
2200 /* Implementation of emit_ops method "emit_prologue". */
2203 aarch64_emit_prologue (void)
2208 /* This function emit a prologue for the following function prototype:
2210 enum eval_result_type f (unsigned char *regs,
2213 The first argument is a buffer of raw registers. The second
2214 argument is the result of
2215 evaluating the expression, which will be set to whatever is on top of
2216 the stack at the end.
2218 The stack set up by the prologue is as such:
2220 High *------------------------------------------------------*
2223 | x1 (ULONGEST *value) |
2224 | x0 (unsigned char *regs) |
2225 Low *------------------------------------------------------*
2227 As we are implementing a stack machine, each opcode can expand the
2228 stack so we never know how far we are from the data saved by this
2229 prologue. In order to be able refer to value and regs later, we save
2230 the current stack pointer in the frame pointer. This way, it is not
2231 clobbered when calling C functions.
2233 Finally, throughtout every operation, we are using register x0 as the
2234 top of the stack, and x1 as a scratch register. */
2236 p += emit_stp (p, x0, x1, sp, preindex_memory_operand (-2 * 16));
2237 p += emit_str (p, lr, sp, offset_memory_operand (3 * 8));
2238 p += emit_str (p, fp, sp, offset_memory_operand (2 * 8));
2240 p += emit_add (p, fp, sp, immediate_operand (2 * 8));
2243 emit_ops_insns (buf, p - buf);
2246 /* Implementation of emit_ops method "emit_epilogue". */
2249 aarch64_emit_epilogue (void)
2254 /* Store the result of the expression (x0) in *value. */
2255 p += emit_sub (p, x1, fp, immediate_operand (1 * 8));
2256 p += emit_ldr (p, x1, x1, offset_memory_operand (0));
2257 p += emit_str (p, x0, x1, offset_memory_operand (0));
2259 /* Restore the previous state. */
2260 p += emit_add (p, sp, fp, immediate_operand (2 * 8));
2261 p += emit_ldp (p, fp, lr, fp, offset_memory_operand (0));
2263 /* Return expr_eval_no_error. */
2264 p += emit_mov (p, x0, immediate_operand (expr_eval_no_error));
2265 p += emit_ret (p, lr);
2267 emit_ops_insns (buf, p - buf);
2270 /* Implementation of emit_ops method "emit_add". */
2273 aarch64_emit_add (void)
2278 p += emit_pop (p, x1);
2279 p += emit_add (p, x0, x1, register_operand (x0));
2281 emit_ops_insns (buf, p - buf);
2284 /* Implementation of emit_ops method "emit_sub". */
2287 aarch64_emit_sub (void)
2292 p += emit_pop (p, x1);
2293 p += emit_sub (p, x0, x1, register_operand (x0));
2295 emit_ops_insns (buf, p - buf);
2298 /* Implementation of emit_ops method "emit_mul". */
2301 aarch64_emit_mul (void)
2306 p += emit_pop (p, x1);
2307 p += emit_mul (p, x0, x1, x0);
2309 emit_ops_insns (buf, p - buf);
2312 /* Implementation of emit_ops method "emit_lsh". */
2315 aarch64_emit_lsh (void)
2320 p += emit_pop (p, x1);
2321 p += emit_lslv (p, x0, x1, x0);
2323 emit_ops_insns (buf, p - buf);
2326 /* Implementation of emit_ops method "emit_rsh_signed". */
2329 aarch64_emit_rsh_signed (void)
2334 p += emit_pop (p, x1);
2335 p += emit_asrv (p, x0, x1, x0);
2337 emit_ops_insns (buf, p - buf);
2340 /* Implementation of emit_ops method "emit_rsh_unsigned". */
2343 aarch64_emit_rsh_unsigned (void)
2348 p += emit_pop (p, x1);
2349 p += emit_lsrv (p, x0, x1, x0);
2351 emit_ops_insns (buf, p - buf);
2354 /* Implementation of emit_ops method "emit_ext". */
2357 aarch64_emit_ext (int arg)
2362 p += emit_sbfx (p, x0, x0, 0, arg);
2364 emit_ops_insns (buf, p - buf);
2367 /* Implementation of emit_ops method "emit_log_not". */
2370 aarch64_emit_log_not (void)
2375 /* If the top of the stack is 0, replace it with 1. Else replace it with
2378 p += emit_cmp (p, x0, immediate_operand (0));
2379 p += emit_cset (p, x0, EQ);
2381 emit_ops_insns (buf, p - buf);
2384 /* Implementation of emit_ops method "emit_bit_and". */
2387 aarch64_emit_bit_and (void)
2392 p += emit_pop (p, x1);
2393 p += emit_and (p, x0, x0, x1);
2395 emit_ops_insns (buf, p - buf);
2398 /* Implementation of emit_ops method "emit_bit_or". */
2401 aarch64_emit_bit_or (void)
2406 p += emit_pop (p, x1);
2407 p += emit_orr (p, x0, x0, x1);
2409 emit_ops_insns (buf, p - buf);
2412 /* Implementation of emit_ops method "emit_bit_xor". */
2415 aarch64_emit_bit_xor (void)
2420 p += emit_pop (p, x1);
2421 p += emit_eor (p, x0, x0, x1);
2423 emit_ops_insns (buf, p - buf);
2426 /* Implementation of emit_ops method "emit_bit_not". */
2429 aarch64_emit_bit_not (void)
2434 p += emit_mvn (p, x0, x0);
2436 emit_ops_insns (buf, p - buf);
2439 /* Implementation of emit_ops method "emit_equal". */
2442 aarch64_emit_equal (void)
2447 p += emit_pop (p, x1);
2448 p += emit_cmp (p, x0, register_operand (x1));
2449 p += emit_cset (p, x0, EQ);
2451 emit_ops_insns (buf, p - buf);
2454 /* Implementation of emit_ops method "emit_less_signed". */
2457 aarch64_emit_less_signed (void)
2462 p += emit_pop (p, x1);
2463 p += emit_cmp (p, x1, register_operand (x0));
2464 p += emit_cset (p, x0, LT);
2466 emit_ops_insns (buf, p - buf);
2469 /* Implementation of emit_ops method "emit_less_unsigned". */
2472 aarch64_emit_less_unsigned (void)
2477 p += emit_pop (p, x1);
2478 p += emit_cmp (p, x1, register_operand (x0));
2479 p += emit_cset (p, x0, LO);
2481 emit_ops_insns (buf, p - buf);
2484 /* Implementation of emit_ops method "emit_ref". */
2487 aarch64_emit_ref (int size)
2495 p += emit_ldrb (p, w0, x0, offset_memory_operand (0));
2498 p += emit_ldrh (p, w0, x0, offset_memory_operand (0));
2501 p += emit_ldr (p, w0, x0, offset_memory_operand (0));
2504 p += emit_ldr (p, x0, x0, offset_memory_operand (0));
2507 /* Unknown size, bail on compilation. */
2512 emit_ops_insns (buf, p - buf);
2515 /* Implementation of emit_ops method "emit_if_goto". */
2518 aarch64_emit_if_goto (int *offset_p, int *size_p)
2523 /* The Z flag is set or cleared here. */
2524 p += emit_cmp (p, x0, immediate_operand (0));
2525 /* This instruction must not change the Z flag. */
2526 p += emit_pop (p, x0);
2527 /* Branch over the next instruction if x0 == 0. */
2528 p += emit_bcond (p, EQ, 8);
2530 /* The NOP instruction will be patched with an unconditional branch. */
2532 *offset_p = (p - buf) * 4;
2537 emit_ops_insns (buf, p - buf);
2540 /* Implementation of emit_ops method "emit_goto". */
2543 aarch64_emit_goto (int *offset_p, int *size_p)
2548 /* The NOP instruction will be patched with an unconditional branch. */
2555 emit_ops_insns (buf, p - buf);
2558 /* Implementation of emit_ops method "write_goto_address". */
2561 aarch64_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
2565 emit_b (&insn, 0, to - from);
2566 append_insns (&from, 1, &insn);
2569 /* Implementation of emit_ops method "emit_const". */
2572 aarch64_emit_const (LONGEST num)
2577 p += emit_mov_addr (p, x0, num);
2579 emit_ops_insns (buf, p - buf);
2582 /* Implementation of emit_ops method "emit_call". */
2585 aarch64_emit_call (CORE_ADDR fn)
2590 p += emit_mov_addr (p, ip0, fn);
2591 p += emit_blr (p, ip0);
2593 emit_ops_insns (buf, p - buf);
2596 /* Implementation of emit_ops method "emit_reg". */
2599 aarch64_emit_reg (int reg)
2604 /* Set x0 to unsigned char *regs. */
2605 p += emit_sub (p, x0, fp, immediate_operand (2 * 8));
2606 p += emit_ldr (p, x0, x0, offset_memory_operand (0));
2607 p += emit_mov (p, x1, immediate_operand (reg));
2609 emit_ops_insns (buf, p - buf);
2611 aarch64_emit_call (get_raw_reg_func_addr ());
2614 /* Implementation of emit_ops method "emit_pop". */
2617 aarch64_emit_pop (void)
2622 p += emit_pop (p, x0);
2624 emit_ops_insns (buf, p - buf);
2627 /* Implementation of emit_ops method "emit_stack_flush". */
2630 aarch64_emit_stack_flush (void)
2635 p += emit_push (p, x0);
2637 emit_ops_insns (buf, p - buf);
2640 /* Implementation of emit_ops method "emit_zero_ext". */
2643 aarch64_emit_zero_ext (int arg)
2648 p += emit_ubfx (p, x0, x0, 0, arg);
2650 emit_ops_insns (buf, p - buf);
2653 /* Implementation of emit_ops method "emit_swap". */
2656 aarch64_emit_swap (void)
2661 p += emit_ldr (p, x1, sp, offset_memory_operand (0 * 16));
2662 p += emit_str (p, x0, sp, offset_memory_operand (0 * 16));
2663 p += emit_mov (p, x0, register_operand (x1));
2665 emit_ops_insns (buf, p - buf);
2668 /* Implementation of emit_ops method "emit_stack_adjust". */
2671 aarch64_emit_stack_adjust (int n)
2673 /* This is not needed with our design. */
2677 p += emit_add (p, sp, sp, immediate_operand (n * 16));
2679 emit_ops_insns (buf, p - buf);
2682 /* Implementation of emit_ops method "emit_int_call_1". */
2685 aarch64_emit_int_call_1 (CORE_ADDR fn, int arg1)
2690 p += emit_mov (p, x0, immediate_operand (arg1));
2692 emit_ops_insns (buf, p - buf);
2694 aarch64_emit_call (fn);
2697 /* Implementation of emit_ops method "emit_void_call_2". */
2700 aarch64_emit_void_call_2 (CORE_ADDR fn, int arg1)
2705 /* Push x0 on the stack. */
2706 aarch64_emit_stack_flush ();
2708 /* Setup arguments for the function call:
2711 x1: top of the stack
2716 p += emit_mov (p, x1, register_operand (x0));
2717 p += emit_mov (p, x0, immediate_operand (arg1));
2719 emit_ops_insns (buf, p - buf);
2721 aarch64_emit_call (fn);
2724 aarch64_emit_pop ();
2727 /* Implementation of emit_ops method "emit_eq_goto". */
2730 aarch64_emit_eq_goto (int *offset_p, int *size_p)
2735 p += emit_pop (p, x1);
2736 p += emit_cmp (p, x1, register_operand (x0));
2737 /* Branch over the next instruction if x0 != x1. */
2738 p += emit_bcond (p, NE, 8);
2739 /* The NOP instruction will be patched with an unconditional branch. */
2741 *offset_p = (p - buf) * 4;
2746 emit_ops_insns (buf, p - buf);
2749 /* Implementation of emit_ops method "emit_ne_goto". */
2752 aarch64_emit_ne_goto (int *offset_p, int *size_p)
2757 p += emit_pop (p, x1);
2758 p += emit_cmp (p, x1, register_operand (x0));
2759 /* Branch over the next instruction if x0 == x1. */
2760 p += emit_bcond (p, EQ, 8);
2761 /* The NOP instruction will be patched with an unconditional branch. */
2763 *offset_p = (p - buf) * 4;
2768 emit_ops_insns (buf, p - buf);
2771 /* Implementation of emit_ops method "emit_lt_goto". */
2774 aarch64_emit_lt_goto (int *offset_p, int *size_p)
2779 p += emit_pop (p, x1);
2780 p += emit_cmp (p, x1, register_operand (x0));
2781 /* Branch over the next instruction if x0 >= x1. */
2782 p += emit_bcond (p, GE, 8);
2783 /* The NOP instruction will be patched with an unconditional branch. */
2785 *offset_p = (p - buf) * 4;
2790 emit_ops_insns (buf, p - buf);
2793 /* Implementation of emit_ops method "emit_le_goto". */
2796 aarch64_emit_le_goto (int *offset_p, int *size_p)
2801 p += emit_pop (p, x1);
2802 p += emit_cmp (p, x1, register_operand (x0));
2803 /* Branch over the next instruction if x0 > x1. */
2804 p += emit_bcond (p, GT, 8);
2805 /* The NOP instruction will be patched with an unconditional branch. */
2807 *offset_p = (p - buf) * 4;
2812 emit_ops_insns (buf, p - buf);
2815 /* Implementation of emit_ops method "emit_gt_goto". */
2818 aarch64_emit_gt_goto (int *offset_p, int *size_p)
2823 p += emit_pop (p, x1);
2824 p += emit_cmp (p, x1, register_operand (x0));
2825 /* Branch over the next instruction if x0 <= x1. */
2826 p += emit_bcond (p, LE, 8);
2827 /* The NOP instruction will be patched with an unconditional branch. */
2829 *offset_p = (p - buf) * 4;
2834 emit_ops_insns (buf, p - buf);
2837 /* Implementation of emit_ops method "emit_ge_got". */
2840 aarch64_emit_ge_got (int *offset_p, int *size_p)
2845 p += emit_pop (p, x1);
2846 p += emit_cmp (p, x1, register_operand (x0));
2847 /* Branch over the next instruction if x0 <= x1. */
2848 p += emit_bcond (p, LT, 8);
2849 /* The NOP instruction will be patched with an unconditional branch. */
2851 *offset_p = (p - buf) * 4;
2856 emit_ops_insns (buf, p - buf);
2859 static struct emit_ops aarch64_emit_ops_impl =
2861 aarch64_emit_prologue,
2862 aarch64_emit_epilogue,
2867 aarch64_emit_rsh_signed,
2868 aarch64_emit_rsh_unsigned,
2870 aarch64_emit_log_not,
2871 aarch64_emit_bit_and,
2872 aarch64_emit_bit_or,
2873 aarch64_emit_bit_xor,
2874 aarch64_emit_bit_not,
2876 aarch64_emit_less_signed,
2877 aarch64_emit_less_unsigned,
2879 aarch64_emit_if_goto,
2881 aarch64_write_goto_address,
2886 aarch64_emit_stack_flush,
2887 aarch64_emit_zero_ext,
2889 aarch64_emit_stack_adjust,
2890 aarch64_emit_int_call_1,
2891 aarch64_emit_void_call_2,
2892 aarch64_emit_eq_goto,
2893 aarch64_emit_ne_goto,
2894 aarch64_emit_lt_goto,
2895 aarch64_emit_le_goto,
2896 aarch64_emit_gt_goto,
2897 aarch64_emit_ge_got,
2900 /* Implementation of linux_target_ops method "emit_ops". */
2902 static struct emit_ops *
2903 aarch64_emit_ops (void)
2905 return &aarch64_emit_ops_impl;
2908 /* Implementation of linux_target_ops method
2909 "get_min_fast_tracepoint_insn_len". */
2912 aarch64_get_min_fast_tracepoint_insn_len (void)
2917 /* Implementation of linux_target_ops method "supports_range_stepping". */
2920 aarch64_supports_range_stepping (void)
2925 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
2927 static const gdb_byte *
2928 aarch64_sw_breakpoint_from_kind (int kind, int *size)
2930 if (is_64bit_tdesc ())
2932 *size = aarch64_breakpoint_len;
2933 return aarch64_breakpoint;
2936 return arm_sw_breakpoint_from_kind (kind, size);
2939 /* Implementation of linux_target_ops method "breakpoint_kind_from_pc". */
2942 aarch64_breakpoint_kind_from_pc (CORE_ADDR *pcptr)
2944 if (is_64bit_tdesc ())
2945 return aarch64_breakpoint_len;
2947 return arm_breakpoint_kind_from_pc (pcptr);
2950 /* Implementation of the linux_target_ops method
2951 "breakpoint_kind_from_current_state". */
2954 aarch64_breakpoint_kind_from_current_state (CORE_ADDR *pcptr)
2956 if (is_64bit_tdesc ())
2957 return aarch64_breakpoint_len;
2959 return arm_breakpoint_kind_from_current_state (pcptr);
2962 /* Support for hardware single step. */
2965 aarch64_supports_hardware_single_step (void)
2970 struct linux_target_ops the_low_target =
2974 aarch64_cannot_fetch_register,
2975 aarch64_cannot_store_register,
2976 NULL, /* fetch_register */
2979 aarch64_breakpoint_kind_from_pc,
2980 aarch64_sw_breakpoint_from_kind,
2981 NULL, /* get_next_pcs */
2982 0, /* decr_pc_after_break */
2983 aarch64_breakpoint_at,
2984 aarch64_supports_z_point_type,
2985 aarch64_insert_point,
2986 aarch64_remove_point,
2987 aarch64_stopped_by_watchpoint,
2988 aarch64_stopped_data_address,
2989 NULL, /* collect_ptrace_register */
2990 NULL, /* supply_ptrace_register */
2991 aarch64_linux_siginfo_fixup,
2992 aarch64_linux_new_process,
2993 aarch64_linux_new_thread,
2994 aarch64_linux_delete_thread,
2995 aarch64_linux_new_fork,
2996 aarch64_linux_prepare_to_resume,
2997 NULL, /* process_qsupported */
2998 aarch64_supports_tracepoints,
2999 aarch64_get_thread_area,
3000 aarch64_install_fast_tracepoint_jump_pad,
3002 aarch64_get_min_fast_tracepoint_insn_len,
3003 aarch64_supports_range_stepping,
3004 aarch64_breakpoint_kind_from_current_state,
3005 aarch64_supports_hardware_single_step,
3006 aarch64_get_syscall_trapinfo,
3010 initialize_low_arch (void)
3012 init_registers_aarch64 ();
3014 initialize_low_arch_aarch32 ();
3016 initialize_regsets_info (&aarch64_regsets_info);