1 /* GNU/Linux/AArch64 specific low level interface, for the remote server for
4 Copyright (C) 2009-2015 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "linux-low.h"
24 #include "elf/common.h"
28 #include <sys/ptrace.h>
29 #include <asm/ptrace.h>
32 #include "gdb_proc_service.h"
34 /* Defined in auto-generated files. */
35 void init_registers_aarch64 (void);
36 extern const struct target_desc *tdesc_aarch64;
42 #define AARCH64_X_REGS_NUM 31
43 #define AARCH64_V_REGS_NUM 32
44 #define AARCH64_X0_REGNO 0
45 #define AARCH64_SP_REGNO 31
46 #define AARCH64_PC_REGNO 32
47 #define AARCH64_CPSR_REGNO 33
48 #define AARCH64_V0_REGNO 34
49 #define AARCH64_FPSR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM)
50 #define AARCH64_FPCR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 1)
52 #define AARCH64_NUM_REGS (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 2)
57 /* These offsets correspond to GET/SETREGSET */
59 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8,
60 8*8, 9*8, 10*8, 11*8, 12*8, 13*8, 14*8, 15*8,
61 16*8, 17*8, 18*8, 19*8, 20*8, 21*8, 22*8, 23*8,
62 24*8, 25*8, 26*8, 27*8, 28*8,
67 33*8, /* cpsr 4 bytes!*/
69 /* FP register offsets correspond to GET/SETFPREGSET */
70 0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16,
71 8*16, 9*16, 10*16, 11*16, 12*16, 13*16, 14*16, 15*16,
72 16*16, 17*16, 18*16, 19*16, 20*16, 21*16, 22*16, 23*16,
73 24*16, 25*16, 26*16, 27*16, 28*16, 29*16, 30*16, 31*16
76 /* Here starts the macro definitions, data structures, and code for
77 the hardware breakpoint and hardware watchpoint support. The
78 following is the abbreviations that are used frequently in the code
85 /* Maximum number of hardware breakpoint and watchpoint registers.
86 Neither of these values may exceed the width of dr_changed_t
89 #define AARCH64_HBP_MAX_NUM 16
90 #define AARCH64_HWP_MAX_NUM 16
92 /* Alignment requirement in bytes of hardware breakpoint and
93 watchpoint address. This is the requirement for the addresses that
94 can be written to the hardware breakpoint/watchpoint value
95 registers. The kernel currently does not do any alignment on
96 addresses when receiving a writing request (via ptrace call) to
97 these debug registers, and it will reject any address that is
99 Some limited support has been provided in this gdbserver port for
100 unaligned watchpoints, so that from a gdb user point of view, an
101 unaligned watchpoint can still be set. This is achieved by
102 minimally enlarging the watched area to meet the alignment
103 requirement, and if necessary, splitting the watchpoint over
104 several hardware watchpoint registers. */
106 #define AARCH64_HBP_ALIGNMENT 4
107 #define AARCH64_HWP_ALIGNMENT 8
109 /* The maximum length of a memory region that can be watched by one
110 hardware watchpoint register. */
112 #define AARCH64_HWP_MAX_LEN_PER_REG 8
114 /* Each bit of a variable of this type is used to indicate whether a
115 hardware breakpoint or watchpoint setting has been changed since
116 the last updating. Bit N corresponds to the Nth hardware
117 breakpoint or watchpoint setting which is managed in
118 aarch64_debug_reg_state. Where N is valid between 0 and the total
119 number of the hardware breakpoint or watchpoint debug registers
120 minus 1. When the bit N is 1, it indicates the corresponding
121 breakpoint or watchpoint setting is changed, and thus the
122 corresponding hardware debug register needs to be updated via the
125 In the per-thread arch-specific data area, we define two such
126 variables for per-thread hardware breakpoint and watchpoint
127 settings respectively.
129 This type is part of the mechanism which helps reduce the number of
130 ptrace calls to the kernel, i.e. avoid asking the kernel to write
131 to the debug registers with unchanged values. */
133 typedef unsigned long long dr_changed_t;
135 /* Set each of the lower M bits of X to 1; assert X is wide enough. */
137 #define DR_MARK_ALL_CHANGED(x, m) \
140 gdb_assert (sizeof ((x)) * 8 >= (m)); \
141 (x) = (((dr_changed_t)1 << (m)) - 1); \
144 #define DR_MARK_N_CHANGED(x, n) \
147 (x) |= ((dr_changed_t)1 << (n)); \
150 #define DR_CLEAR_CHANGED(x) \
156 #define DR_HAS_CHANGED(x) ((x) != 0)
157 #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
159 /* Structure for managing the hardware breakpoint/watchpoint resources.
160 DR_ADDR_* stores the address, DR_CTRL_* stores the control register
161 content, and DR_REF_COUNT_* counts the numbers of references to the
162 corresponding bp/wp, by which way the limited hardware resources
163 are not wasted on duplicated bp/wp settings (though so far gdb has
164 done a good job by not sending duplicated bp/wp requests). */
166 struct aarch64_debug_reg_state
168 /* hardware breakpoint */
169 CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM];
170 unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM];
171 unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM];
173 /* hardware watchpoint */
174 CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM];
175 unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM];
176 unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM];
179 /* Per-process arch-specific data we want to keep. */
181 struct arch_process_info
183 /* Hardware breakpoint/watchpoint data.
184 The reason for them to be per-process rather than per-thread is
185 due to the lack of information in the gdbserver environment;
186 gdbserver is not told that whether a requested hardware
187 breakpoint/watchpoint is thread specific or not, so it has to set
188 each hw bp/wp for every thread in the current process. The
189 higher level bp/wp management in gdb will resume a thread if a hw
190 bp/wp trap is not expected for it. Since the hw bp/wp setting is
191 same for each thread, it is reasonable for the data to live here.
193 struct aarch64_debug_reg_state debug_reg_state;
196 /* Per-thread arch-specific data we want to keep. */
200 /* When bit N is 1, it indicates the Nth hardware breakpoint or
201 watchpoint register pair needs to be updated when the thread is
202 resumed; see aarch64_linux_prepare_to_resume. */
203 dr_changed_t dr_changed_bp;
204 dr_changed_t dr_changed_wp;
207 /* Number of hardware breakpoints/watchpoints the target supports.
208 They are initialized with values obtained via the ptrace calls
209 with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */
211 static int aarch64_num_bp_regs;
212 static int aarch64_num_wp_regs;
215 aarch64_cannot_store_register (int regno)
217 return regno >= AARCH64_NUM_REGS;
221 aarch64_cannot_fetch_register (int regno)
223 return regno >= AARCH64_NUM_REGS;
227 aarch64_fill_gregset (struct regcache *regcache, void *buf)
229 struct user_pt_regs *regset = buf;
232 for (i = 0; i < AARCH64_X_REGS_NUM; i++)
233 collect_register (regcache, AARCH64_X0_REGNO + i, ®set->regs[i]);
234 collect_register (regcache, AARCH64_SP_REGNO, ®set->sp);
235 collect_register (regcache, AARCH64_PC_REGNO, ®set->pc);
236 collect_register (regcache, AARCH64_CPSR_REGNO, ®set->pstate);
240 aarch64_store_gregset (struct regcache *regcache, const void *buf)
242 const struct user_pt_regs *regset = buf;
245 for (i = 0; i < AARCH64_X_REGS_NUM; i++)
246 supply_register (regcache, AARCH64_X0_REGNO + i, ®set->regs[i]);
247 supply_register (regcache, AARCH64_SP_REGNO, ®set->sp);
248 supply_register (regcache, AARCH64_PC_REGNO, ®set->pc);
249 supply_register (regcache, AARCH64_CPSR_REGNO, ®set->pstate);
253 aarch64_fill_fpregset (struct regcache *regcache, void *buf)
255 struct user_fpsimd_state *regset = buf;
258 for (i = 0; i < AARCH64_V_REGS_NUM; i++)
259 collect_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]);
260 collect_register (regcache, AARCH64_FPSR_REGNO, ®set->fpsr);
261 collect_register (regcache, AARCH64_FPCR_REGNO, ®set->fpcr);
265 aarch64_store_fpregset (struct regcache *regcache, const void *buf)
267 const struct user_fpsimd_state *regset = buf;
270 for (i = 0; i < AARCH64_V_REGS_NUM; i++)
271 supply_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]);
272 supply_register (regcache, AARCH64_FPSR_REGNO, ®set->fpsr);
273 supply_register (regcache, AARCH64_FPCR_REGNO, ®set->fpcr);
276 /* Enable miscellaneous debugging output. The name is historical - it
277 was originally used to debug LinuxThreads support. */
278 extern int debug_threads;
281 aarch64_get_pc (struct regcache *regcache)
285 collect_register_by_name (regcache, "pc", &pc);
287 debug_printf ("stop pc is %08lx\n", pc);
292 aarch64_set_pc (struct regcache *regcache, CORE_ADDR pc)
294 unsigned long newpc = pc;
295 supply_register_by_name (regcache, "pc", &newpc);
298 /* Correct in either endianness. */
300 #define aarch64_breakpoint_len 4
302 static const unsigned long aarch64_breakpoint = 0x00800011;
305 aarch64_breakpoint_at (CORE_ADDR where)
309 (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
310 if (insn == aarch64_breakpoint)
316 /* Print the values of the cached breakpoint/watchpoint registers.
317 This is enabled via the "set debug-hw-points" monitor command. */
320 aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
321 const char *func, CORE_ADDR addr,
322 int len, enum target_hw_bp_type type)
326 fprintf (stderr, "%s", func);
328 fprintf (stderr, " (addr=0x%08lx, len=%d, type=%s)",
329 (unsigned long) addr, len,
330 type == hw_write ? "hw-write-watchpoint"
331 : (type == hw_read ? "hw-read-watchpoint"
332 : (type == hw_access ? "hw-access-watchpoint"
333 : (type == hw_execute ? "hw-breakpoint"
335 fprintf (stderr, ":\n");
337 fprintf (stderr, "\tBREAKPOINTs:\n");
338 for (i = 0; i < aarch64_num_bp_regs; i++)
339 fprintf (stderr, "\tBP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n",
340 i, paddress (state->dr_addr_bp[i]),
341 state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]);
343 fprintf (stderr, "\tWATCHPOINTs:\n");
344 for (i = 0; i < aarch64_num_wp_regs; i++)
345 fprintf (stderr, "\tWP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n",
346 i, paddress (state->dr_addr_wp[i]),
347 state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]);
351 aarch64_init_debug_reg_state (struct aarch64_debug_reg_state *state)
355 for (i = 0; i < AARCH64_HBP_MAX_NUM; ++i)
357 state->dr_addr_bp[i] = 0;
358 state->dr_ctrl_bp[i] = 0;
359 state->dr_ref_count_bp[i] = 0;
362 for (i = 0; i < AARCH64_HWP_MAX_NUM; ++i)
364 state->dr_addr_wp[i] = 0;
365 state->dr_ctrl_wp[i] = 0;
366 state->dr_ref_count_wp[i] = 0;
370 /* ptrace expects control registers to be formatted as follows:
373 +--------------------------------+----------+------+------+----+
374 | RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN |
375 +--------------------------------+----------+------+------+----+
377 The TYPE field is ignored for breakpoints. */
379 #define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1)
380 #define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff)
382 /* Utility function that returns the length in bytes of a watchpoint
383 according to the content of a hardware debug control register CTRL.
384 Note that the kernel currently only supports the following Byte
385 Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
386 that for a hardware watchpoint, its valid length can only be 1
387 byte, 2 bytes, 4 bytes or 8 bytes. */
389 static inline unsigned int
390 aarch64_watchpoint_length (unsigned int ctrl)
392 switch (DR_CONTROL_LENGTH (ctrl))
407 /* Given the hardware breakpoint or watchpoint type TYPE and its
408 length LEN, return the expected encoding for a hardware
409 breakpoint/watchpoint control register. */
412 aarch64_point_encode_ctrl_reg (enum target_hw_bp_type type, int len)
414 unsigned int ctrl, ttype;
432 perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
438 ctrl |= ((1 << len) - 1) << 5;
440 ctrl |= (2 << 1) | 1;
445 /* Addresses to be written to the hardware breakpoint and watchpoint
446 value registers need to be aligned; the alignment is 4-byte and
447 8-type respectively. Linux kernel rejects any non-aligned address
448 it receives from the related ptrace call. Furthermore, the kernel
449 currently only supports the following Byte Address Select (BAS)
450 values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
451 watchpoint to be accepted by the kernel (via ptrace call), its
452 valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
453 Despite these limitations, the unaligned watchpoint is supported in
456 Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */
459 aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len)
461 unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT
462 : AARCH64_HBP_ALIGNMENT;
464 if (addr & (alignment - 1))
467 if (len != 8 && len != 4 && len != 2 && len != 1)
473 /* Given the (potentially unaligned) watchpoint address in ADDR and
474 length in LEN, return the aligned address and aligned length in
475 *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned
476 aligned address and length will be valid to be written to the
477 hardware watchpoint value and control registers. See the comment
478 above aarch64_point_is_aligned for the information about the
479 alignment requirement. The given watchpoint may get truncated if
480 more than one hardware register is needed to cover the watched
481 region. *NEXT_ADDR_P and *NEXT_LEN_P, if non-NULL, will return the
482 address and length of the remaining part of the watchpoint (which
483 can be processed by calling this routine again to generate another
484 aligned address and length pair.
486 Essentially, unaligned watchpoint is achieved by minimally
487 enlarging the watched area to meet the alignment requirement, and
488 if necessary, splitting the watchpoint over several hardware
489 watchpoint registers. The trade-off is that there will be
490 false-positive hits for the read-type or the access-type hardware
491 watchpoints; for the write type, which is more commonly used, there
492 will be no such issues, as the higher-level breakpoint management
493 in gdb always examines the exact watched region for any content
494 change, and transparently resumes a thread from a watchpoint trap
495 if there is no change to the watched region.
497 Another limitation is that because the watched region is enlarged,
498 the watchpoint fault address returned by
499 aarch64_stopped_data_address may be outside of the original watched
500 region, especially when the triggering instruction is accessing a
501 larger region. When the fault address is not within any known
502 range, watchpoints_triggered in gdb will get confused, as the
503 higher-level watchpoint management is only aware of original
504 watched regions, and will think that some unknown watchpoint has
505 been triggered. In such a case, gdb may stop without displaying
506 any detailed information.
508 Once the kernel provides the full support for Byte Address Select
509 (BAS) in the hardware watchpoint control register, these
510 limitations can be largely relaxed with some further work. */
513 aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p,
514 int *aligned_len_p, CORE_ADDR *next_addr_p,
519 CORE_ADDR aligned_addr;
520 const unsigned int alignment = AARCH64_HWP_ALIGNMENT;
521 const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG;
523 /* As assumed by the algorithm. */
524 gdb_assert (alignment == max_wp_len);
529 /* Address to be put into the hardware watchpoint value register
531 offset = addr & (alignment - 1);
532 aligned_addr = addr - offset;
534 gdb_assert (offset >= 0 && offset < alignment);
535 gdb_assert (aligned_addr >= 0 && aligned_addr <= addr);
536 gdb_assert ((offset + len) > 0);
538 if (offset + len >= max_wp_len)
540 /* Need more than one watchpoint registers; truncate it at the
541 alignment boundary. */
542 aligned_len = max_wp_len;
543 len -= (max_wp_len - offset);
544 addr += (max_wp_len - offset);
545 gdb_assert ((addr & (alignment - 1)) == 0);
549 /* Find the smallest valid length that is large enough to
550 accommodate this watchpoint. */
551 static const unsigned char
552 aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] =
553 { 1, 2, 4, 4, 8, 8, 8, 8 };
555 aligned_len = aligned_len_array[offset + len - 1];
560 if (aligned_addr_p != NULL)
561 *aligned_addr_p = aligned_addr;
562 if (aligned_len_p != NULL)
563 *aligned_len_p = aligned_len;
564 if (next_addr_p != NULL)
566 if (next_len_p != NULL)
570 /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
571 registers with data from *STATE. */
574 aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state,
575 int tid, int watchpoint)
579 struct user_hwdebug_state regs;
580 const CORE_ADDR *addr;
581 const unsigned int *ctrl;
583 memset (®s, 0, sizeof (regs));
584 iov.iov_base = ®s;
585 count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs;
586 addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp;
587 ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp;
590 iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs[count - 1])
591 + sizeof (regs.dbg_regs [count - 1]));
593 for (i = 0; i < count; i++)
595 regs.dbg_regs[i].addr = addr[i];
596 regs.dbg_regs[i].ctrl = ctrl[i];
599 if (ptrace (PTRACE_SETREGSET, tid,
600 watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK,
602 error (_("Unexpected error setting hardware debug registers"));
605 struct aarch64_dr_update_callback_param
612 /* Callback function which records the information about the change of
613 one hardware breakpoint/watchpoint setting for the thread ENTRY.
614 The information is passed in via PTR.
615 N.B. The actual updating of hardware debug registers is not
616 carried out until the moment the thread is resumed. */
619 debug_reg_change_callback (struct inferior_list_entry *entry, void *ptr)
621 struct thread_info *thread = (struct thread_info *) entry;
622 struct lwp_info *lwp = get_thread_lwp (thread);
623 struct aarch64_dr_update_callback_param *param_p
624 = (struct aarch64_dr_update_callback_param *) ptr;
625 int pid = param_p->pid;
626 int idx = param_p->idx;
627 int is_watchpoint = param_p->is_watchpoint;
628 struct arch_lwp_info *info = lwp->arch_private;
629 dr_changed_t *dr_changed_ptr;
630 dr_changed_t dr_changed;
634 fprintf (stderr, "debug_reg_change_callback: \n\tOn entry:\n");
635 fprintf (stderr, "\tpid%d, tid: %ld, dr_changed_bp=0x%llx, "
636 "dr_changed_wp=0x%llx\n",
637 pid, lwpid_of (thread), info->dr_changed_bp,
638 info->dr_changed_wp);
641 dr_changed_ptr = is_watchpoint ? &info->dr_changed_wp
642 : &info->dr_changed_bp;
643 dr_changed = *dr_changed_ptr;
645 /* Only update the threads of this process. */
646 if (pid_of (thread) == pid)
649 && (idx <= (is_watchpoint ? aarch64_num_wp_regs
650 : aarch64_num_bp_regs)));
652 /* The following assertion is not right, as there can be changes
653 that have not been made to the hardware debug registers
654 before new changes overwrite the old ones. This can happen,
655 for instance, when the breakpoint/watchpoint hit one of the
656 threads and the user enters continue; then what happens is:
657 1) all breakpoints/watchpoints are removed for all threads;
658 2) a single step is carried out for the thread that was hit;
659 3) all of the points are inserted again for all threads;
660 4) all threads are resumed.
661 The 2nd step will only affect the one thread in which the
662 bp/wp was hit, which means only that one thread is resumed;
663 remember that the actual updating only happen in
664 aarch64_linux_prepare_to_resume, so other threads remain
665 stopped during the removal and insertion of bp/wp. Therefore
666 for those threads, the change of insertion of the bp/wp
667 overwrites that of the earlier removals. (The situation may
668 be different when bp/wp is steppable, or in the non-stop
670 /* gdb_assert (DR_N_HAS_CHANGED (dr_changed, idx) == 0); */
672 /* The actual update is done later just before resuming the lwp,
673 we just mark that one register pair needs updating. */
674 DR_MARK_N_CHANGED (dr_changed, idx);
675 *dr_changed_ptr = dr_changed;
677 /* If the lwp isn't stopped, force it to momentarily pause, so
678 we can update its debug registers. */
680 linux_stop_lwp (lwp);
685 fprintf (stderr, "\tOn exit:\n\tpid%d, tid: %ld, dr_changed_bp=0x%llx, "
686 "dr_changed_wp=0x%llx\n",
687 pid, lwpid_of (thread), info->dr_changed_bp,
688 info->dr_changed_wp);
694 /* Notify each thread that their IDXth breakpoint/watchpoint register
695 pair needs to be updated. The message will be recorded in each
696 thread's arch-specific data area, the actual updating will be done
697 when the thread is resumed. */
700 aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state *state,
701 int is_watchpoint, unsigned int idx)
703 struct aarch64_dr_update_callback_param param;
705 /* Only update the threads of this process. */
706 param.pid = pid_of (current_thread);
708 param.is_watchpoint = is_watchpoint;
711 find_inferior (&all_threads, debug_reg_change_callback, (void *) ¶m);
715 /* Return the pointer to the debug register state structure in the
716 current process' arch-specific data area. */
718 static struct aarch64_debug_reg_state *
719 aarch64_get_debug_reg_state ()
721 struct process_info *proc;
723 proc = current_process ();
724 return &proc->priv->arch_private->debug_reg_state;
727 /* Record the insertion of one breakpoint/watchpoint, as represented
728 by ADDR and CTRL, in the process' arch-specific data area *STATE. */
731 aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state,
732 enum target_hw_bp_type type,
733 CORE_ADDR addr, int len)
735 int i, idx, num_regs, is_watchpoint;
736 unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
737 CORE_ADDR *dr_addr_p;
739 /* Set up state pointers. */
740 is_watchpoint = (type != hw_execute);
741 gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
744 num_regs = aarch64_num_wp_regs;
745 dr_addr_p = state->dr_addr_wp;
746 dr_ctrl_p = state->dr_ctrl_wp;
747 dr_ref_count = state->dr_ref_count_wp;
751 num_regs = aarch64_num_bp_regs;
752 dr_addr_p = state->dr_addr_bp;
753 dr_ctrl_p = state->dr_ctrl_bp;
754 dr_ref_count = state->dr_ref_count_bp;
757 ctrl = aarch64_point_encode_ctrl_reg (type, len);
759 /* Find an existing or free register in our cache. */
761 for (i = 0; i < num_regs; ++i)
763 if ((dr_ctrl_p[i] & 1) == 0)
765 gdb_assert (dr_ref_count[i] == 0);
767 /* no break; continue hunting for an exising one. */
769 else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
771 gdb_assert (dr_ref_count[i] != 0);
781 /* Update our cache. */
782 if ((dr_ctrl_p[idx] & 1) == 0)
785 dr_addr_p[idx] = addr;
786 dr_ctrl_p[idx] = ctrl;
787 dr_ref_count[idx] = 1;
788 /* Notify the change. */
789 aarch64_notify_debug_reg_change (state, is_watchpoint, idx);
800 /* Record the removal of one breakpoint/watchpoint, as represented by
801 ADDR and CTRL, in the process' arch-specific data area *STATE. */
804 aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state,
805 enum target_hw_bp_type type,
806 CORE_ADDR addr, int len)
808 int i, num_regs, is_watchpoint;
809 unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
810 CORE_ADDR *dr_addr_p;
812 /* Set up state pointers. */
813 is_watchpoint = (type != hw_execute);
814 gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
817 num_regs = aarch64_num_wp_regs;
818 dr_addr_p = state->dr_addr_wp;
819 dr_ctrl_p = state->dr_ctrl_wp;
820 dr_ref_count = state->dr_ref_count_wp;
824 num_regs = aarch64_num_bp_regs;
825 dr_addr_p = state->dr_addr_bp;
826 dr_ctrl_p = state->dr_ctrl_bp;
827 dr_ref_count = state->dr_ref_count_bp;
830 ctrl = aarch64_point_encode_ctrl_reg (type, len);
832 /* Find the entry that matches the ADDR and CTRL. */
833 for (i = 0; i < num_regs; ++i)
834 if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
836 gdb_assert (dr_ref_count[i] != 0);
844 /* Clear our cache. */
845 if (--dr_ref_count[i] == 0)
847 /* Clear the enable bit. */
851 /* Notify the change. */
852 aarch64_notify_debug_reg_change (state, is_watchpoint, i);
859 aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr,
860 int len, int is_insert)
862 struct aarch64_debug_reg_state *state;
864 /* The hardware breakpoint on AArch64 should always be 4-byte
866 if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len))
869 state = aarch64_get_debug_reg_state ();
872 return aarch64_dr_state_insert_one_point (state, type, addr, len);
874 return aarch64_dr_state_remove_one_point (state, type, addr, len);
877 /* This is essentially the same as aarch64_handle_breakpoint, apart
878 from that it is an aligned watchpoint to be handled. */
881 aarch64_handle_aligned_watchpoint (enum target_hw_bp_type type,
882 CORE_ADDR addr, int len, int is_insert)
884 struct aarch64_debug_reg_state *state;
886 state = aarch64_get_debug_reg_state ();
889 return aarch64_dr_state_insert_one_point (state, type, addr, len);
891 return aarch64_dr_state_remove_one_point (state, type, addr, len);
894 /* Insert/remove unaligned watchpoint by calling
895 aarch64_align_watchpoint repeatedly until the whole watched region,
896 as represented by ADDR and LEN, has been properly aligned and ready
897 to be written to one or more hardware watchpoint registers.
898 IS_INSERT indicates whether this is an insertion or a deletion.
899 Return 0 if succeed. */
902 aarch64_handle_unaligned_watchpoint (enum target_hw_bp_type type,
903 CORE_ADDR addr, int len, int is_insert)
905 struct aarch64_debug_reg_state *state
906 = aarch64_get_debug_reg_state ();
910 CORE_ADDR aligned_addr;
911 int aligned_len, ret;
913 aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len,
917 ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr,
920 ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr,
925 "handle_unaligned_watchpoint: is_insert: %d\n"
926 " aligned_addr: 0x%s, aligned_len: %d\n"
927 " next_addr: 0x%s, next_len: %d\n",
928 is_insert, paddress (aligned_addr), aligned_len,
929 paddress (addr), len);
939 aarch64_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr,
940 int len, int is_insert)
942 if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len))
943 return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert);
945 return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert);
949 aarch64_supports_z_point_type (char z_type)
954 case Z_PACKET_WRITE_WP:
955 case Z_PACKET_READ_WP:
956 case Z_PACKET_ACCESS_WP:
959 /* Leave the handling of sw breakpoints with the gdb client. */
964 /* Insert a hardware breakpoint/watchpoint.
965 It actually only records the info of the to-be-inserted bp/wp;
966 the actual insertion will happen when threads are resumed.
969 Return 1 if TYPE is unsupported type;
970 Return -1 if an error occurs. */
973 aarch64_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
974 int len, struct raw_breakpoint *bp)
977 enum target_hw_bp_type targ_type;
980 fprintf (stderr, "insert_point on entry (addr=0x%08lx, len=%d)\n",
981 (unsigned long) addr, len);
983 /* Determine the type from the raw breakpoint type. */
984 targ_type = raw_bkpt_type_to_target_hw_bp_type (type);
986 if (targ_type != hw_execute)
988 aarch64_handle_watchpoint (targ_type, addr, len, 1 /* is_insert */);
991 aarch64_handle_breakpoint (targ_type, addr, len, 1 /* is_insert */);
994 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
995 "insert_point", addr, len, targ_type);
1000 /* Remove a hardware breakpoint/watchpoint.
1001 It actually only records the info of the to-be-removed bp/wp,
1002 the actual removal will be done when threads are resumed.
1004 Return 0 if succeed;
1005 Return 1 if TYPE is an unsupported type;
1006 Return -1 if an error occurs. */
1009 aarch64_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
1010 int len, struct raw_breakpoint *bp)
1013 enum target_hw_bp_type targ_type;
1015 if (show_debug_regs)
1016 fprintf (stderr, "remove_point on entry (addr=0x%08lx, len=%d)\n",
1017 (unsigned long) addr, len);
1019 /* Determine the type from the raw breakpoint type. */
1020 targ_type = raw_bkpt_type_to_target_hw_bp_type (type);
1022 /* Set up state pointers. */
1023 if (targ_type != hw_execute)
1025 aarch64_handle_watchpoint (targ_type, addr, len, 0 /* is_insert */);
1028 aarch64_handle_breakpoint (targ_type, addr, len, 0 /* is_insert */);
1030 if (show_debug_regs)
1031 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
1032 "remove_point", addr, len, targ_type);
1037 /* Returns the address associated with the watchpoint that hit, if
1038 any; returns 0 otherwise. */
1041 aarch64_stopped_data_address (void)
1045 struct aarch64_debug_reg_state *state;
1047 pid = lwpid_of (current_thread);
1049 /* Get the siginfo. */
1050 if (ptrace (PTRACE_GETSIGINFO, pid, NULL, &siginfo) != 0)
1051 return (CORE_ADDR) 0;
1053 /* Need to be a hardware breakpoint/watchpoint trap. */
1054 if (siginfo.si_signo != SIGTRAP
1055 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
1056 return (CORE_ADDR) 0;
1058 /* Check if the address matches any watched address. */
1059 state = aarch64_get_debug_reg_state ();
1060 for (i = aarch64_num_wp_regs - 1; i >= 0; --i)
1062 const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]);
1063 const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr;
1064 const CORE_ADDR addr_watch = state->dr_addr_wp[i];
1065 if (state->dr_ref_count_wp[i]
1066 && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i])
1067 && addr_trap >= addr_watch
1068 && addr_trap < addr_watch + len)
1072 return (CORE_ADDR) 0;
1075 /* Returns 1 if target was stopped due to a watchpoint hit, 0
1079 aarch64_stopped_by_watchpoint (void)
1081 if (aarch64_stopped_data_address () != 0)
1087 /* Fetch the thread-local storage pointer for libthread_db. */
1090 ps_get_thread_area (const struct ps_prochandle *ph,
1091 lwpid_t lwpid, int idx, void **base)
1096 iovec.iov_base = ®
1097 iovec.iov_len = sizeof (reg);
1099 if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0)
1102 /* IDX is the bias from the thread pointer to the beginning of the
1103 thread descriptor. It has to be subtracted due to implementation
1104 quirks in libthread_db. */
1105 *base = (void *) (reg - idx);
1110 /* Called when a new process is created. */
1112 static struct arch_process_info *
1113 aarch64_linux_new_process (void)
1115 struct arch_process_info *info = xcalloc (1, sizeof (*info));
1117 aarch64_init_debug_reg_state (&info->debug_reg_state);
1122 /* Called when a new thread is detected. */
1125 aarch64_linux_new_thread (struct lwp_info *lwp)
1127 struct arch_lwp_info *info = xcalloc (1, sizeof (*info));
1129 /* Mark that all the hardware breakpoint/watchpoint register pairs
1130 for this thread need to be initialized (with data from
1131 aarch_process_info.debug_reg_state). */
1132 DR_MARK_ALL_CHANGED (info->dr_changed_bp, aarch64_num_bp_regs);
1133 DR_MARK_ALL_CHANGED (info->dr_changed_wp, aarch64_num_wp_regs);
1135 lwp->arch_private = info;
1139 aarch64_linux_new_fork (struct process_info *parent,
1140 struct process_info *child)
1142 /* These are allocated by linux_add_process. */
1143 gdb_assert (parent->private != NULL
1144 && parent->private->arch_private != NULL);
1145 gdb_assert (child->private != NULL
1146 && child->private->arch_private != NULL);
1148 /* Linux kernel before 2.6.33 commit
1149 72f674d203cd230426437cdcf7dd6f681dad8b0d
1150 will inherit hardware debug registers from parent
1151 on fork/vfork/clone. Newer Linux kernels create such tasks with
1152 zeroed debug registers.
1154 GDB core assumes the child inherits the watchpoints/hw
1155 breakpoints of the parent, and will remove them all from the
1156 forked off process. Copy the debug registers mirrors into the
1157 new process so that all breakpoints and watchpoints can be
1158 removed together. The debug registers mirror will become zeroed
1159 in the end before detaching the forked off process, thus making
1160 this compatible with older Linux kernels too. */
1162 *child->private->arch_private = *parent->private->arch_private;
1165 /* Called when resuming a thread.
1166 If the debug regs have changed, update the thread's copies. */
1169 aarch64_linux_prepare_to_resume (struct lwp_info *lwp)
1171 struct thread_info *thread = get_lwp_thread (lwp);
1172 ptid_t ptid = ptid_of (thread);
1173 struct arch_lwp_info *info = lwp->arch_private;
1175 if (DR_HAS_CHANGED (info->dr_changed_bp)
1176 || DR_HAS_CHANGED (info->dr_changed_wp))
1178 int tid = ptid_get_lwp (ptid);
1179 struct process_info *proc = find_process_pid (ptid_get_pid (ptid));
1180 struct aarch64_debug_reg_state *state
1181 = &proc->priv->arch_private->debug_reg_state;
1183 if (show_debug_regs)
1184 fprintf (stderr, "prepare_to_resume thread %ld\n", lwpid_of (thread));
1187 if (DR_HAS_CHANGED (info->dr_changed_wp))
1189 aarch64_linux_set_debug_regs (state, tid, 1);
1190 DR_CLEAR_CHANGED (info->dr_changed_wp);
1194 if (DR_HAS_CHANGED (info->dr_changed_bp))
1196 aarch64_linux_set_debug_regs (state, tid, 0);
1197 DR_CLEAR_CHANGED (info->dr_changed_bp);
1202 /* ptrace hardware breakpoint resource info is formatted as follows:
1205 +---------------+--------------+---------------+---------------+
1206 | RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS |
1207 +---------------+--------------+---------------+---------------+ */
1209 #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
1210 #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
1211 #define AARCH64_DEBUG_ARCH_V8 0x6
1214 aarch64_arch_setup (void)
1218 struct user_hwdebug_state dreg_state;
1220 current_process ()->tdesc = tdesc_aarch64;
1222 pid = lwpid_of (current_thread);
1223 iov.iov_base = &dreg_state;
1224 iov.iov_len = sizeof (dreg_state);
1226 /* Get hardware watchpoint register info. */
1227 if (ptrace (PTRACE_GETREGSET, pid, NT_ARM_HW_WATCH, &iov) == 0
1228 && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
1230 aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
1231 if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM)
1233 warning ("Unexpected number of hardware watchpoint registers reported"
1234 " by ptrace, got %d, expected %d.",
1235 aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM);
1236 aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM;
1241 warning ("Unable to determine the number of hardware watchpoints"
1243 aarch64_num_wp_regs = 0;
1246 /* Get hardware breakpoint register info. */
1247 if (ptrace (PTRACE_GETREGSET, pid, NT_ARM_HW_BREAK, &iov) == 0
1248 && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
1250 aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
1251 if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM)
1253 warning ("Unexpected number of hardware breakpoint registers reported"
1254 " by ptrace, got %d, expected %d.",
1255 aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM);
1256 aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM;
1261 warning ("Unable to determine the number of hardware breakpoints"
1263 aarch64_num_bp_regs = 0;
1267 static struct regset_info aarch64_regsets[] =
1269 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS,
1270 sizeof (struct user_pt_regs), GENERAL_REGS,
1271 aarch64_fill_gregset, aarch64_store_gregset },
1272 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET,
1273 sizeof (struct user_fpsimd_state), FP_REGS,
1274 aarch64_fill_fpregset, aarch64_store_fpregset
1276 { 0, 0, 0, -1, -1, NULL, NULL }
1279 static struct regsets_info aarch64_regsets_info =
1281 aarch64_regsets, /* regsets */
1282 0, /* num_regsets */
1283 NULL, /* disabled_regsets */
1286 static struct usrregs_info aarch64_usrregs_info =
1292 static struct regs_info regs_info =
1294 NULL, /* regset_bitmap */
1295 &aarch64_usrregs_info,
1296 &aarch64_regsets_info,
1299 static const struct regs_info *
1300 aarch64_regs_info (void)
1305 struct linux_target_ops the_low_target =
1309 aarch64_cannot_fetch_register,
1310 aarch64_cannot_store_register,
1314 (const unsigned char *) &aarch64_breakpoint,
1315 aarch64_breakpoint_len,
1318 aarch64_breakpoint_at,
1319 aarch64_supports_z_point_type,
1320 aarch64_insert_point,
1321 aarch64_remove_point,
1322 aarch64_stopped_by_watchpoint,
1323 aarch64_stopped_data_address,
1327 aarch64_linux_new_process,
1328 aarch64_linux_new_thread,
1329 aarch64_linux_new_fork,
1330 aarch64_linux_prepare_to_resume,
1334 initialize_low_arch (void)
1336 init_registers_aarch64 ();
1338 initialize_regsets_info (&aarch64_regsets_info);