1 /* GNU/Linux/AArch64 specific low level interface, for the remote server for
4 Copyright (C) 2009-2015 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "linux-low.h"
24 #include "elf/common.h"
28 #include <sys/ptrace.h>
29 #include <asm/ptrace.h>
32 #include "gdb_proc_service.h"
34 /* Defined in auto-generated files. */
35 void init_registers_aarch64 (void);
36 extern const struct target_desc *tdesc_aarch64;
42 #define AARCH64_X_REGS_NUM 31
43 #define AARCH64_V_REGS_NUM 32
44 #define AARCH64_X0_REGNO 0
45 #define AARCH64_SP_REGNO 31
46 #define AARCH64_PC_REGNO 32
47 #define AARCH64_CPSR_REGNO 33
48 #define AARCH64_V0_REGNO 34
49 #define AARCH64_FPSR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM)
50 #define AARCH64_FPCR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 1)
52 #define AARCH64_NUM_REGS (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 2)
54 /* Here starts the macro definitions, data structures, and code for
55 the hardware breakpoint and hardware watchpoint support. The
56 following is the abbreviations that are used frequently in the code
63 /* Maximum number of hardware breakpoint and watchpoint registers.
64 Neither of these values may exceed the width of dr_changed_t
67 #define AARCH64_HBP_MAX_NUM 16
68 #define AARCH64_HWP_MAX_NUM 16
70 /* Alignment requirement in bytes of hardware breakpoint and
71 watchpoint address. This is the requirement for the addresses that
72 can be written to the hardware breakpoint/watchpoint value
73 registers. The kernel currently does not do any alignment on
74 addresses when receiving a writing request (via ptrace call) to
75 these debug registers, and it will reject any address that is
77 Some limited support has been provided in this gdbserver port for
78 unaligned watchpoints, so that from a gdb user point of view, an
79 unaligned watchpoint can still be set. This is achieved by
80 minimally enlarging the watched area to meet the alignment
81 requirement, and if necessary, splitting the watchpoint over
82 several hardware watchpoint registers. */
84 #define AARCH64_HBP_ALIGNMENT 4
85 #define AARCH64_HWP_ALIGNMENT 8
87 /* The maximum length of a memory region that can be watched by one
88 hardware watchpoint register. */
90 #define AARCH64_HWP_MAX_LEN_PER_REG 8
92 /* Each bit of a variable of this type is used to indicate whether a
93 hardware breakpoint or watchpoint setting has been changed since
94 the last updating. Bit N corresponds to the Nth hardware
95 breakpoint or watchpoint setting which is managed in
96 aarch64_debug_reg_state. Where N is valid between 0 and the total
97 number of the hardware breakpoint or watchpoint debug registers
98 minus 1. When the bit N is 1, it indicates the corresponding
99 breakpoint or watchpoint setting is changed, and thus the
100 corresponding hardware debug register needs to be updated via the
103 In the per-thread arch-specific data area, we define two such
104 variables for per-thread hardware breakpoint and watchpoint
105 settings respectively.
107 This type is part of the mechanism which helps reduce the number of
108 ptrace calls to the kernel, i.e. avoid asking the kernel to write
109 to the debug registers with unchanged values. */
111 typedef unsigned long long dr_changed_t;
113 /* Set each of the lower M bits of X to 1; assert X is wide enough. */
115 #define DR_MARK_ALL_CHANGED(x, m) \
118 gdb_assert (sizeof ((x)) * 8 >= (m)); \
119 (x) = (((dr_changed_t)1 << (m)) - 1); \
122 #define DR_MARK_N_CHANGED(x, n) \
125 (x) |= ((dr_changed_t)1 << (n)); \
128 #define DR_CLEAR_CHANGED(x) \
134 #define DR_HAS_CHANGED(x) ((x) != 0)
135 #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
137 /* Structure for managing the hardware breakpoint/watchpoint resources.
138 DR_ADDR_* stores the address, DR_CTRL_* stores the control register
139 content, and DR_REF_COUNT_* counts the numbers of references to the
140 corresponding bp/wp, by which way the limited hardware resources
141 are not wasted on duplicated bp/wp settings (though so far gdb has
142 done a good job by not sending duplicated bp/wp requests). */
144 struct aarch64_debug_reg_state
146 /* hardware breakpoint */
147 CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM];
148 unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM];
149 unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM];
151 /* hardware watchpoint */
152 CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM];
153 unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM];
154 unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM];
157 /* Per-process arch-specific data we want to keep. */
159 struct arch_process_info
161 /* Hardware breakpoint/watchpoint data.
162 The reason for them to be per-process rather than per-thread is
163 due to the lack of information in the gdbserver environment;
164 gdbserver is not told that whether a requested hardware
165 breakpoint/watchpoint is thread specific or not, so it has to set
166 each hw bp/wp for every thread in the current process. The
167 higher level bp/wp management in gdb will resume a thread if a hw
168 bp/wp trap is not expected for it. Since the hw bp/wp setting is
169 same for each thread, it is reasonable for the data to live here.
171 struct aarch64_debug_reg_state debug_reg_state;
174 /* Per-thread arch-specific data we want to keep. */
178 /* When bit N is 1, it indicates the Nth hardware breakpoint or
179 watchpoint register pair needs to be updated when the thread is
180 resumed; see aarch64_linux_prepare_to_resume. */
181 dr_changed_t dr_changed_bp;
182 dr_changed_t dr_changed_wp;
185 /* Number of hardware breakpoints/watchpoints the target supports.
186 They are initialized with values obtained via the ptrace calls
187 with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */
189 static int aarch64_num_bp_regs;
190 static int aarch64_num_wp_regs;
192 /* Implementation of linux_target_ops method "cannot_store_register". */
195 aarch64_cannot_store_register (int regno)
197 return regno >= AARCH64_NUM_REGS;
200 /* Implementation of linux_target_ops method "cannot_fetch_register". */
203 aarch64_cannot_fetch_register (int regno)
205 return regno >= AARCH64_NUM_REGS;
209 aarch64_fill_gregset (struct regcache *regcache, void *buf)
211 struct user_pt_regs *regset = buf;
214 for (i = 0; i < AARCH64_X_REGS_NUM; i++)
215 collect_register (regcache, AARCH64_X0_REGNO + i, ®set->regs[i]);
216 collect_register (regcache, AARCH64_SP_REGNO, ®set->sp);
217 collect_register (regcache, AARCH64_PC_REGNO, ®set->pc);
218 collect_register (regcache, AARCH64_CPSR_REGNO, ®set->pstate);
222 aarch64_store_gregset (struct regcache *regcache, const void *buf)
224 const struct user_pt_regs *regset = buf;
227 for (i = 0; i < AARCH64_X_REGS_NUM; i++)
228 supply_register (regcache, AARCH64_X0_REGNO + i, ®set->regs[i]);
229 supply_register (regcache, AARCH64_SP_REGNO, ®set->sp);
230 supply_register (regcache, AARCH64_PC_REGNO, ®set->pc);
231 supply_register (regcache, AARCH64_CPSR_REGNO, ®set->pstate);
235 aarch64_fill_fpregset (struct regcache *regcache, void *buf)
237 struct user_fpsimd_state *regset = buf;
240 for (i = 0; i < AARCH64_V_REGS_NUM; i++)
241 collect_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]);
242 collect_register (regcache, AARCH64_FPSR_REGNO, ®set->fpsr);
243 collect_register (regcache, AARCH64_FPCR_REGNO, ®set->fpcr);
247 aarch64_store_fpregset (struct regcache *regcache, const void *buf)
249 const struct user_fpsimd_state *regset = buf;
252 for (i = 0; i < AARCH64_V_REGS_NUM; i++)
253 supply_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]);
254 supply_register (regcache, AARCH64_FPSR_REGNO, ®set->fpsr);
255 supply_register (regcache, AARCH64_FPCR_REGNO, ®set->fpcr);
258 /* Enable miscellaneous debugging output. The name is historical - it
259 was originally used to debug LinuxThreads support. */
260 extern int debug_threads;
262 /* Implementation of linux_target_ops method "get_pc". */
265 aarch64_get_pc (struct regcache *regcache)
269 collect_register_by_name (regcache, "pc", &pc);
271 debug_printf ("stop pc is %08lx\n", pc);
275 /* Implementation of linux_target_ops method "set_pc". */
278 aarch64_set_pc (struct regcache *regcache, CORE_ADDR pc)
280 unsigned long newpc = pc;
281 supply_register_by_name (regcache, "pc", &newpc);
284 #define aarch64_breakpoint_len 4
286 /* AArch64 BRK software debug mode instruction.
287 This instruction needs to match gdb/aarch64-tdep.c
288 (aarch64_default_breakpoint). */
289 static const gdb_byte aarch64_breakpoint[] = {0x00, 0x00, 0x20, 0xd4};
291 /* Implementation of linux_target_ops method "breakpoint_at". */
294 aarch64_breakpoint_at (CORE_ADDR where)
296 gdb_byte insn[aarch64_breakpoint_len];
298 (*the_target->read_memory) (where, (unsigned char *) &insn,
299 aarch64_breakpoint_len);
300 if (memcmp (insn, aarch64_breakpoint, aarch64_breakpoint_len) == 0)
306 /* Print the values of the cached breakpoint/watchpoint registers.
307 This is enabled via the "set debug-hw-points" monitor command. */
310 aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
311 const char *func, CORE_ADDR addr,
312 int len, enum target_hw_bp_type type)
316 debug_printf ("%s", func);
318 debug_printf (" (addr=0x%08lx, len=%d, type=%s)",
319 (unsigned long) addr, len,
320 type == hw_write ? "hw-write-watchpoint"
321 : (type == hw_read ? "hw-read-watchpoint"
322 : (type == hw_access ? "hw-access-watchpoint"
323 : (type == hw_execute ? "hw-breakpoint"
325 debug_printf (":\n");
327 debug_printf ("\tBREAKPOINTs:\n");
328 for (i = 0; i < aarch64_num_bp_regs; i++)
329 debug_printf ("\tBP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n",
330 i, paddress (state->dr_addr_bp[i]),
331 state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]);
333 debug_printf ("\tWATCHPOINTs:\n");
334 for (i = 0; i < aarch64_num_wp_regs; i++)
335 debug_printf ("\tWP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n",
336 i, paddress (state->dr_addr_wp[i]),
337 state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]);
341 aarch64_init_debug_reg_state (struct aarch64_debug_reg_state *state)
345 for (i = 0; i < AARCH64_HBP_MAX_NUM; ++i)
347 state->dr_addr_bp[i] = 0;
348 state->dr_ctrl_bp[i] = 0;
349 state->dr_ref_count_bp[i] = 0;
352 for (i = 0; i < AARCH64_HWP_MAX_NUM; ++i)
354 state->dr_addr_wp[i] = 0;
355 state->dr_ctrl_wp[i] = 0;
356 state->dr_ref_count_wp[i] = 0;
360 /* ptrace expects control registers to be formatted as follows:
363 +--------------------------------+----------+------+------+----+
364 | RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN |
365 +--------------------------------+----------+------+------+----+
367 The TYPE field is ignored for breakpoints. */
369 #define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1)
370 #define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff)
372 /* Utility function that returns the length in bytes of a watchpoint
373 according to the content of a hardware debug control register CTRL.
374 Note that the kernel currently only supports the following Byte
375 Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
376 that for a hardware watchpoint, its valid length can only be 1
377 byte, 2 bytes, 4 bytes or 8 bytes. */
379 static inline unsigned int
380 aarch64_watchpoint_length (unsigned int ctrl)
382 switch (DR_CONTROL_LENGTH (ctrl))
397 /* Given the hardware breakpoint or watchpoint type TYPE and its
398 length LEN, return the expected encoding for a hardware
399 breakpoint/watchpoint control register. */
402 aarch64_point_encode_ctrl_reg (enum target_hw_bp_type type, int len)
404 unsigned int ctrl, ttype;
422 perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
428 ctrl |= ((1 << len) - 1) << 5;
430 ctrl |= (2 << 1) | 1;
435 /* Addresses to be written to the hardware breakpoint and watchpoint
436 value registers need to be aligned; the alignment is 4-byte and
437 8-type respectively. Linux kernel rejects any non-aligned address
438 it receives from the related ptrace call. Furthermore, the kernel
439 currently only supports the following Byte Address Select (BAS)
440 values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
441 watchpoint to be accepted by the kernel (via ptrace call), its
442 valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
443 Despite these limitations, the unaligned watchpoint is supported in
446 Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */
449 aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len)
451 unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT
452 : AARCH64_HBP_ALIGNMENT;
454 if (addr & (alignment - 1))
457 if (len != 8 && len != 4 && len != 2 && len != 1)
463 /* Given the (potentially unaligned) watchpoint address in ADDR and
464 length in LEN, return the aligned address and aligned length in
465 *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned
466 aligned address and length will be valid to be written to the
467 hardware watchpoint value and control registers. See the comment
468 above aarch64_point_is_aligned for the information about the
469 alignment requirement. The given watchpoint may get truncated if
470 more than one hardware register is needed to cover the watched
471 region. *NEXT_ADDR_P and *NEXT_LEN_P, if non-NULL, will return the
472 address and length of the remaining part of the watchpoint (which
473 can be processed by calling this routine again to generate another
474 aligned address and length pair.
476 Essentially, unaligned watchpoint is achieved by minimally
477 enlarging the watched area to meet the alignment requirement, and
478 if necessary, splitting the watchpoint over several hardware
479 watchpoint registers. The trade-off is that there will be
480 false-positive hits for the read-type or the access-type hardware
481 watchpoints; for the write type, which is more commonly used, there
482 will be no such issues, as the higher-level breakpoint management
483 in gdb always examines the exact watched region for any content
484 change, and transparently resumes a thread from a watchpoint trap
485 if there is no change to the watched region.
487 Another limitation is that because the watched region is enlarged,
488 the watchpoint fault address returned by
489 aarch64_stopped_data_address may be outside of the original watched
490 region, especially when the triggering instruction is accessing a
491 larger region. When the fault address is not within any known
492 range, watchpoints_triggered in gdb will get confused, as the
493 higher-level watchpoint management is only aware of original
494 watched regions, and will think that some unknown watchpoint has
495 been triggered. In such a case, gdb may stop without displaying
496 any detailed information.
498 Once the kernel provides the full support for Byte Address Select
499 (BAS) in the hardware watchpoint control register, these
500 limitations can be largely relaxed with some further work. */
503 aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p,
504 int *aligned_len_p, CORE_ADDR *next_addr_p,
509 CORE_ADDR aligned_addr;
510 const unsigned int alignment = AARCH64_HWP_ALIGNMENT;
511 const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG;
513 /* As assumed by the algorithm. */
514 gdb_assert (alignment == max_wp_len);
519 /* Address to be put into the hardware watchpoint value register
521 offset = addr & (alignment - 1);
522 aligned_addr = addr - offset;
524 gdb_assert (offset >= 0 && offset < alignment);
525 gdb_assert (aligned_addr >= 0 && aligned_addr <= addr);
526 gdb_assert ((offset + len) > 0);
528 if (offset + len >= max_wp_len)
530 /* Need more than one watchpoint registers; truncate it at the
531 alignment boundary. */
532 aligned_len = max_wp_len;
533 len -= (max_wp_len - offset);
534 addr += (max_wp_len - offset);
535 gdb_assert ((addr & (alignment - 1)) == 0);
539 /* Find the smallest valid length that is large enough to
540 accommodate this watchpoint. */
541 static const unsigned char
542 aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] =
543 { 1, 2, 4, 4, 8, 8, 8, 8 };
545 aligned_len = aligned_len_array[offset + len - 1];
550 if (aligned_addr_p != NULL)
551 *aligned_addr_p = aligned_addr;
552 if (aligned_len_p != NULL)
553 *aligned_len_p = aligned_len;
554 if (next_addr_p != NULL)
556 if (next_len_p != NULL)
560 /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
561 registers with data from *STATE. */
564 aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state,
565 int tid, int watchpoint)
569 struct user_hwdebug_state regs;
570 const CORE_ADDR *addr;
571 const unsigned int *ctrl;
573 memset (®s, 0, sizeof (regs));
574 iov.iov_base = ®s;
575 count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs;
576 addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp;
577 ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp;
580 iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs[count - 1])
581 + sizeof (regs.dbg_regs [count - 1]));
583 for (i = 0; i < count; i++)
585 regs.dbg_regs[i].addr = addr[i];
586 regs.dbg_regs[i].ctrl = ctrl[i];
589 if (ptrace (PTRACE_SETREGSET, tid,
590 watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK,
592 error (_("Unexpected error setting hardware debug registers"));
595 struct aarch64_dr_update_callback_param
602 /* Callback function which records the information about the change of
603 one hardware breakpoint/watchpoint setting for the thread ENTRY.
604 The information is passed in via PTR.
605 N.B. The actual updating of hardware debug registers is not
606 carried out until the moment the thread is resumed. */
609 debug_reg_change_callback (struct inferior_list_entry *entry, void *ptr)
611 struct thread_info *thread = (struct thread_info *) entry;
612 struct lwp_info *lwp = get_thread_lwp (thread);
613 struct aarch64_dr_update_callback_param *param_p
614 = (struct aarch64_dr_update_callback_param *) ptr;
615 int pid = param_p->pid;
616 int idx = param_p->idx;
617 int is_watchpoint = param_p->is_watchpoint;
618 struct arch_lwp_info *info = lwp->arch_private;
619 dr_changed_t *dr_changed_ptr;
620 dr_changed_t dr_changed;
624 fprintf (stderr, "debug_reg_change_callback: \n\tOn entry:\n");
625 fprintf (stderr, "\tpid%d, tid: %ld, dr_changed_bp=0x%llx, "
626 "dr_changed_wp=0x%llx\n",
627 pid, lwpid_of (thread), info->dr_changed_bp,
628 info->dr_changed_wp);
631 dr_changed_ptr = is_watchpoint ? &info->dr_changed_wp
632 : &info->dr_changed_bp;
633 dr_changed = *dr_changed_ptr;
635 /* Only update the threads of this process. */
636 if (pid_of (thread) == pid)
639 && (idx <= (is_watchpoint ? aarch64_num_wp_regs
640 : aarch64_num_bp_regs)));
642 /* The following assertion is not right, as there can be changes
643 that have not been made to the hardware debug registers
644 before new changes overwrite the old ones. This can happen,
645 for instance, when the breakpoint/watchpoint hit one of the
646 threads and the user enters continue; then what happens is:
647 1) all breakpoints/watchpoints are removed for all threads;
648 2) a single step is carried out for the thread that was hit;
649 3) all of the points are inserted again for all threads;
650 4) all threads are resumed.
651 The 2nd step will only affect the one thread in which the
652 bp/wp was hit, which means only that one thread is resumed;
653 remember that the actual updating only happen in
654 aarch64_linux_prepare_to_resume, so other threads remain
655 stopped during the removal and insertion of bp/wp. Therefore
656 for those threads, the change of insertion of the bp/wp
657 overwrites that of the earlier removals. (The situation may
658 be different when bp/wp is steppable, or in the non-stop
660 /* gdb_assert (DR_N_HAS_CHANGED (dr_changed, idx) == 0); */
662 /* The actual update is done later just before resuming the lwp,
663 we just mark that one register pair needs updating. */
664 DR_MARK_N_CHANGED (dr_changed, idx);
665 *dr_changed_ptr = dr_changed;
667 /* If the lwp isn't stopped, force it to momentarily pause, so
668 we can update its debug registers. */
670 linux_stop_lwp (lwp);
675 fprintf (stderr, "\tOn exit:\n\tpid%d, tid: %ld, dr_changed_bp=0x%llx, "
676 "dr_changed_wp=0x%llx\n",
677 pid, lwpid_of (thread), info->dr_changed_bp,
678 info->dr_changed_wp);
684 /* Notify each thread that their IDXth breakpoint/watchpoint register
685 pair needs to be updated. The message will be recorded in each
686 thread's arch-specific data area, the actual updating will be done
687 when the thread is resumed. */
690 aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state *state,
691 int is_watchpoint, unsigned int idx)
693 struct aarch64_dr_update_callback_param param;
695 /* Only update the threads of this process. */
696 param.pid = pid_of (current_thread);
698 param.is_watchpoint = is_watchpoint;
701 find_inferior (&all_threads, debug_reg_change_callback, (void *) ¶m);
705 /* Return the pointer to the debug register state structure in the
706 current process' arch-specific data area. */
708 static struct aarch64_debug_reg_state *
709 aarch64_get_debug_reg_state ()
711 struct process_info *proc;
713 proc = current_process ();
714 return &proc->priv->arch_private->debug_reg_state;
717 /* Record the insertion of one breakpoint/watchpoint, as represented
718 by ADDR and CTRL, in the process' arch-specific data area *STATE. */
721 aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state,
722 enum target_hw_bp_type type,
723 CORE_ADDR addr, int len)
725 int i, idx, num_regs, is_watchpoint;
726 unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
727 CORE_ADDR *dr_addr_p;
729 /* Set up state pointers. */
730 is_watchpoint = (type != hw_execute);
731 gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
734 num_regs = aarch64_num_wp_regs;
735 dr_addr_p = state->dr_addr_wp;
736 dr_ctrl_p = state->dr_ctrl_wp;
737 dr_ref_count = state->dr_ref_count_wp;
741 num_regs = aarch64_num_bp_regs;
742 dr_addr_p = state->dr_addr_bp;
743 dr_ctrl_p = state->dr_ctrl_bp;
744 dr_ref_count = state->dr_ref_count_bp;
747 ctrl = aarch64_point_encode_ctrl_reg (type, len);
749 /* Find an existing or free register in our cache. */
751 for (i = 0; i < num_regs; ++i)
753 if ((dr_ctrl_p[i] & 1) == 0)
755 gdb_assert (dr_ref_count[i] == 0);
757 /* no break; continue hunting for an exising one. */
759 else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
761 gdb_assert (dr_ref_count[i] != 0);
771 /* Update our cache. */
772 if ((dr_ctrl_p[idx] & 1) == 0)
775 dr_addr_p[idx] = addr;
776 dr_ctrl_p[idx] = ctrl;
777 dr_ref_count[idx] = 1;
778 /* Notify the change. */
779 aarch64_notify_debug_reg_change (state, is_watchpoint, idx);
790 /* Record the removal of one breakpoint/watchpoint, as represented by
791 ADDR and CTRL, in the process' arch-specific data area *STATE. */
794 aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state,
795 enum target_hw_bp_type type,
796 CORE_ADDR addr, int len)
798 int i, num_regs, is_watchpoint;
799 unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
800 CORE_ADDR *dr_addr_p;
802 /* Set up state pointers. */
803 is_watchpoint = (type != hw_execute);
804 gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
807 num_regs = aarch64_num_wp_regs;
808 dr_addr_p = state->dr_addr_wp;
809 dr_ctrl_p = state->dr_ctrl_wp;
810 dr_ref_count = state->dr_ref_count_wp;
814 num_regs = aarch64_num_bp_regs;
815 dr_addr_p = state->dr_addr_bp;
816 dr_ctrl_p = state->dr_ctrl_bp;
817 dr_ref_count = state->dr_ref_count_bp;
820 ctrl = aarch64_point_encode_ctrl_reg (type, len);
822 /* Find the entry that matches the ADDR and CTRL. */
823 for (i = 0; i < num_regs; ++i)
824 if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
826 gdb_assert (dr_ref_count[i] != 0);
834 /* Clear our cache. */
835 if (--dr_ref_count[i] == 0)
837 /* Clear the enable bit. */
841 /* Notify the change. */
842 aarch64_notify_debug_reg_change (state, is_watchpoint, i);
849 aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr,
850 int len, int is_insert)
852 struct aarch64_debug_reg_state *state;
854 /* The hardware breakpoint on AArch64 should always be 4-byte
856 if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len))
859 state = aarch64_get_debug_reg_state ();
862 return aarch64_dr_state_insert_one_point (state, type, addr, len);
864 return aarch64_dr_state_remove_one_point (state, type, addr, len);
867 /* This is essentially the same as aarch64_handle_breakpoint, apart
868 from that it is an aligned watchpoint to be handled. */
871 aarch64_handle_aligned_watchpoint (enum target_hw_bp_type type,
872 CORE_ADDR addr, int len, int is_insert)
874 struct aarch64_debug_reg_state *state;
876 state = aarch64_get_debug_reg_state ();
879 return aarch64_dr_state_insert_one_point (state, type, addr, len);
881 return aarch64_dr_state_remove_one_point (state, type, addr, len);
884 /* Insert/remove unaligned watchpoint by calling
885 aarch64_align_watchpoint repeatedly until the whole watched region,
886 as represented by ADDR and LEN, has been properly aligned and ready
887 to be written to one or more hardware watchpoint registers.
888 IS_INSERT indicates whether this is an insertion or a deletion.
889 Return 0 if succeed. */
892 aarch64_handle_unaligned_watchpoint (enum target_hw_bp_type type,
893 CORE_ADDR addr, int len, int is_insert)
895 struct aarch64_debug_reg_state *state
896 = aarch64_get_debug_reg_state ();
900 CORE_ADDR aligned_addr;
901 int aligned_len, ret;
903 aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len,
907 ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr,
910 ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr,
915 "handle_unaligned_watchpoint: is_insert: %d\n"
916 " aligned_addr: 0x%s, aligned_len: %d\n"
917 " next_addr: 0x%s, next_len: %d\n",
918 is_insert, paddress (aligned_addr), aligned_len,
919 paddress (addr), len);
929 aarch64_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr,
930 int len, int is_insert)
932 if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len))
933 return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert);
935 return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert);
938 /* Implementation of linux_target_ops method "supports_z_point_type". */
941 aarch64_supports_z_point_type (char z_type)
947 case Z_PACKET_WRITE_WP:
948 case Z_PACKET_READ_WP:
949 case Z_PACKET_ACCESS_WP:
956 /* Implementation of linux_target_ops method "insert_point".
958 It actually only records the info of the to-be-inserted bp/wp;
959 the actual insertion will happen when threads are resumed. */
962 aarch64_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
963 int len, struct raw_breakpoint *bp)
966 enum target_hw_bp_type targ_type;
969 fprintf (stderr, "insert_point on entry (addr=0x%08lx, len=%d)\n",
970 (unsigned long) addr, len);
972 /* Determine the type from the raw breakpoint type. */
973 targ_type = raw_bkpt_type_to_target_hw_bp_type (type);
975 if (targ_type != hw_execute)
977 aarch64_handle_watchpoint (targ_type, addr, len, 1 /* is_insert */);
980 aarch64_handle_breakpoint (targ_type, addr, len, 1 /* is_insert */);
983 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
984 "insert_point", addr, len, targ_type);
989 /* Implementation of linux_target_ops method "remove_point".
991 It actually only records the info of the to-be-removed bp/wp,
992 the actual removal will be done when threads are resumed. */
995 aarch64_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
996 int len, struct raw_breakpoint *bp)
999 enum target_hw_bp_type targ_type;
1001 if (show_debug_regs)
1002 fprintf (stderr, "remove_point on entry (addr=0x%08lx, len=%d)\n",
1003 (unsigned long) addr, len);
1005 /* Determine the type from the raw breakpoint type. */
1006 targ_type = raw_bkpt_type_to_target_hw_bp_type (type);
1008 /* Set up state pointers. */
1009 if (targ_type != hw_execute)
1011 aarch64_handle_watchpoint (targ_type, addr, len, 0 /* is_insert */);
1014 aarch64_handle_breakpoint (targ_type, addr, len, 0 /* is_insert */);
1016 if (show_debug_regs)
1017 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
1018 "remove_point", addr, len, targ_type);
1023 /* Implementation of linux_target_ops method "stopped_data_address". */
1026 aarch64_stopped_data_address (void)
1030 struct aarch64_debug_reg_state *state;
1032 pid = lwpid_of (current_thread);
1034 /* Get the siginfo. */
1035 if (ptrace (PTRACE_GETSIGINFO, pid, NULL, &siginfo) != 0)
1036 return (CORE_ADDR) 0;
1038 /* Need to be a hardware breakpoint/watchpoint trap. */
1039 if (siginfo.si_signo != SIGTRAP
1040 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
1041 return (CORE_ADDR) 0;
1043 /* Check if the address matches any watched address. */
1044 state = aarch64_get_debug_reg_state ();
1045 for (i = aarch64_num_wp_regs - 1; i >= 0; --i)
1047 const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]);
1048 const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr;
1049 const CORE_ADDR addr_watch = state->dr_addr_wp[i];
1050 if (state->dr_ref_count_wp[i]
1051 && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i])
1052 && addr_trap >= addr_watch
1053 && addr_trap < addr_watch + len)
1057 return (CORE_ADDR) 0;
1060 /* Implementation of linux_target_ops method "stopped_by_watchpoint". */
1063 aarch64_stopped_by_watchpoint (void)
1065 if (aarch64_stopped_data_address () != 0)
1071 /* Fetch the thread-local storage pointer for libthread_db. */
1074 ps_get_thread_area (const struct ps_prochandle *ph,
1075 lwpid_t lwpid, int idx, void **base)
1080 iovec.iov_base = ®
1081 iovec.iov_len = sizeof (reg);
1083 if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0)
1086 /* IDX is the bias from the thread pointer to the beginning of the
1087 thread descriptor. It has to be subtracted due to implementation
1088 quirks in libthread_db. */
1089 *base = (void *) (reg - idx);
1094 /* Implementation of linux_target_ops method "linux_new_process". */
1096 static struct arch_process_info *
1097 aarch64_linux_new_process (void)
1099 struct arch_process_info *info = xcalloc (1, sizeof (*info));
1101 aarch64_init_debug_reg_state (&info->debug_reg_state);
1106 /* Implementation of linux_target_ops method "linux_new_thread". */
1109 aarch64_linux_new_thread (struct lwp_info *lwp)
1111 struct arch_lwp_info *info = xcalloc (1, sizeof (*info));
1113 /* Mark that all the hardware breakpoint/watchpoint register pairs
1114 for this thread need to be initialized (with data from
1115 aarch_process_info.debug_reg_state). */
1116 DR_MARK_ALL_CHANGED (info->dr_changed_bp, aarch64_num_bp_regs);
1117 DR_MARK_ALL_CHANGED (info->dr_changed_wp, aarch64_num_wp_regs);
1119 lwp->arch_private = info;
1122 /* Implementation of linux_target_ops method "linux_new_fork". */
1125 aarch64_linux_new_fork (struct process_info *parent,
1126 struct process_info *child)
1128 /* These are allocated by linux_add_process. */
1129 gdb_assert (parent->priv != NULL
1130 && parent->priv->arch_private != NULL);
1131 gdb_assert (child->priv != NULL
1132 && child->priv->arch_private != NULL);
1134 /* Linux kernel before 2.6.33 commit
1135 72f674d203cd230426437cdcf7dd6f681dad8b0d
1136 will inherit hardware debug registers from parent
1137 on fork/vfork/clone. Newer Linux kernels create such tasks with
1138 zeroed debug registers.
1140 GDB core assumes the child inherits the watchpoints/hw
1141 breakpoints of the parent, and will remove them all from the
1142 forked off process. Copy the debug registers mirrors into the
1143 new process so that all breakpoints and watchpoints can be
1144 removed together. The debug registers mirror will become zeroed
1145 in the end before detaching the forked off process, thus making
1146 this compatible with older Linux kernels too. */
1148 *child->priv->arch_private = *parent->priv->arch_private;
1151 /* Implementation of linux_target_ops method "linux_prepare_to_resume".
1153 If the debug regs have changed, update the thread's copies. */
1156 aarch64_linux_prepare_to_resume (struct lwp_info *lwp)
1158 struct thread_info *thread = get_lwp_thread (lwp);
1159 ptid_t ptid = ptid_of (thread);
1160 struct arch_lwp_info *info = lwp->arch_private;
1162 if (DR_HAS_CHANGED (info->dr_changed_bp)
1163 || DR_HAS_CHANGED (info->dr_changed_wp))
1165 int tid = ptid_get_lwp (ptid);
1166 struct process_info *proc = find_process_pid (ptid_get_pid (ptid));
1167 struct aarch64_debug_reg_state *state
1168 = &proc->priv->arch_private->debug_reg_state;
1170 if (show_debug_regs)
1171 fprintf (stderr, "prepare_to_resume thread %ld\n", lwpid_of (thread));
1174 if (DR_HAS_CHANGED (info->dr_changed_wp))
1176 aarch64_linux_set_debug_regs (state, tid, 1);
1177 DR_CLEAR_CHANGED (info->dr_changed_wp);
1181 if (DR_HAS_CHANGED (info->dr_changed_bp))
1183 aarch64_linux_set_debug_regs (state, tid, 0);
1184 DR_CLEAR_CHANGED (info->dr_changed_bp);
1189 /* ptrace hardware breakpoint resource info is formatted as follows:
1192 +---------------+--------------+---------------+---------------+
1193 | RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS |
1194 +---------------+--------------+---------------+---------------+ */
1196 #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
1197 #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
1198 #define AARCH64_DEBUG_ARCH_V8 0x6
1200 /* Implementation of linux_target_ops method "arch_setup". */
1203 aarch64_arch_setup (void)
1207 struct user_hwdebug_state dreg_state;
1209 current_process ()->tdesc = tdesc_aarch64;
1211 pid = lwpid_of (current_thread);
1212 iov.iov_base = &dreg_state;
1213 iov.iov_len = sizeof (dreg_state);
1215 /* Get hardware watchpoint register info. */
1216 if (ptrace (PTRACE_GETREGSET, pid, NT_ARM_HW_WATCH, &iov) == 0
1217 && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
1219 aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
1220 if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM)
1222 warning ("Unexpected number of hardware watchpoint registers reported"
1223 " by ptrace, got %d, expected %d.",
1224 aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM);
1225 aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM;
1230 warning ("Unable to determine the number of hardware watchpoints"
1232 aarch64_num_wp_regs = 0;
1235 /* Get hardware breakpoint register info. */
1236 if (ptrace (PTRACE_GETREGSET, pid, NT_ARM_HW_BREAK, &iov) == 0
1237 && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
1239 aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
1240 if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM)
1242 warning ("Unexpected number of hardware breakpoint registers reported"
1243 " by ptrace, got %d, expected %d.",
1244 aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM);
1245 aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM;
1250 warning ("Unable to determine the number of hardware breakpoints"
1252 aarch64_num_bp_regs = 0;
1256 static struct regset_info aarch64_regsets[] =
1258 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS,
1259 sizeof (struct user_pt_regs), GENERAL_REGS,
1260 aarch64_fill_gregset, aarch64_store_gregset },
1261 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET,
1262 sizeof (struct user_fpsimd_state), FP_REGS,
1263 aarch64_fill_fpregset, aarch64_store_fpregset
1265 { 0, 0, 0, -1, -1, NULL, NULL }
1268 static struct regsets_info aarch64_regsets_info =
1270 aarch64_regsets, /* regsets */
1271 0, /* num_regsets */
1272 NULL, /* disabled_regsets */
1275 static struct regs_info regs_info =
1277 NULL, /* regset_bitmap */
1279 &aarch64_regsets_info,
1282 /* Implementation of linux_target_ops method "regs_info". */
1284 static const struct regs_info *
1285 aarch64_regs_info (void)
1290 /* Implementation of linux_target_ops method "supports_tracepoints". */
1293 aarch64_supports_tracepoints (void)
1298 /* Implementation of linux_target_ops method "supports_range_stepping". */
1301 aarch64_supports_range_stepping (void)
1306 struct linux_target_ops the_low_target =
1310 aarch64_cannot_fetch_register,
1311 aarch64_cannot_store_register,
1312 NULL, /* fetch_register */
1315 (const unsigned char *) &aarch64_breakpoint,
1316 aarch64_breakpoint_len,
1317 NULL, /* breakpoint_reinsert_addr */
1318 0, /* decr_pc_after_break */
1319 aarch64_breakpoint_at,
1320 aarch64_supports_z_point_type,
1321 aarch64_insert_point,
1322 aarch64_remove_point,
1323 aarch64_stopped_by_watchpoint,
1324 aarch64_stopped_data_address,
1325 NULL, /* collect_ptrace_register */
1326 NULL, /* supply_ptrace_register */
1327 NULL, /* siginfo_fixup */
1328 aarch64_linux_new_process,
1329 aarch64_linux_new_thread,
1330 aarch64_linux_new_fork,
1331 aarch64_linux_prepare_to_resume,
1332 NULL, /* process_qsupported */
1333 aarch64_supports_tracepoints,
1334 NULL, /* get_thread_area */
1335 NULL, /* install_fast_tracepoint_jump_pad */
1336 NULL, /* emit_ops */
1337 NULL, /* get_min_fast_tracepoint_insn_len */
1338 aarch64_supports_range_stepping,
1342 initialize_low_arch (void)
1344 init_registers_aarch64 ();
1346 initialize_regsets_info (&aarch64_regsets_info);