1 /* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger.
2 Copyright 2002, 2003 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 #include "gdb_string.h"
24 #include "symfile.h" /* for entry_point_address */
26 #include "arch-utils.h"
29 #include "frame-unwind.h"
30 #include "frame-base.h"
31 #include "trad-frame.h"
33 #include "gdb_assert.h"
34 #include "sim-regno.h"
35 #include "gdb/sim-frv.h"
36 #include "opcodes/frv-desc.h" /* for the H_SPR_... enums */
38 extern void _initialize_frv_tdep (void);
40 static gdbarch_init_ftype frv_gdbarch_init;
42 static gdbarch_register_name_ftype frv_register_name;
43 static gdbarch_breakpoint_from_pc_ftype frv_breakpoint_from_pc;
44 static gdbarch_adjust_breakpoint_address_ftype frv_gdbarch_adjust_breakpoint_address;
45 static gdbarch_skip_prologue_ftype frv_skip_prologue;
46 static gdbarch_frameless_function_invocation_ftype frv_frameless_function_invocation;
48 /* Register numbers. The order in which these appear define the
49 remote protocol, so take care in changing them. */
51 /* Register numbers 0 -- 63 are always reserved for general-purpose
52 registers. The chip at hand may have less. */
56 struct_return_regnum = 3,
59 /* Register numbers 64 -- 127 are always reserved for floating-point
60 registers. The chip at hand may have less. */
61 first_fpr_regnum = 64,
62 last_fpr_regnum = 127,
64 /* The PC register. */
67 /* Register numbers 129 on up are always reserved for special-purpose
69 first_spr_regnum = 129,
83 last_spr_regnum = 148,
85 /* The total number of registers we know exist. */
86 frv_num_regs = last_spr_regnum + 1,
88 /* Pseudo registers */
89 first_pseudo_regnum = frv_num_regs,
91 /* iacc0 - the 64-bit concatenation of iacc0h and iacc0l. */
92 iacc0_regnum = first_pseudo_regnum + 0,
94 last_pseudo_regnum = iacc0_regnum,
95 frv_num_pseudo_regs = last_pseudo_regnum - first_pseudo_regnum + 1,
98 static LONGEST frv_call_dummy_words[] =
102 struct frv_unwind_cache /* was struct frame_extra_info */
104 /* The previous frame's inner-most stack address. Used as this
105 frame ID's stack_addr. */
108 /* The frame's base, optionally used by the high-level debug info. */
111 /* Table indicating the location of each and every register. */
112 struct trad_frame_saved_reg *saved_regs;
116 /* A structure describing a particular variant of the FRV.
117 We allocate and initialize one of these structures when we create
118 the gdbarch object for a variant.
120 At the moment, all the FR variants we support differ only in which
121 registers are present; the portable code of GDB knows that
122 registers whose names are the empty string don't exist, so the
123 `register_names' array captures all the per-variant information we
126 in the future, if we need to have per-variant maps for raw size,
127 virtual type, etc., we should replace register_names with an array
128 of structures, each of which gives all the necessary info for one
129 register. Don't stick parallel arrays in here --- that's so
133 /* How many general-purpose registers does this variant have? */
136 /* How many floating-point registers does this variant have? */
139 /* How many hardware watchpoints can it support? */
140 int num_hw_watchpoints;
142 /* How many hardware breakpoints can it support? */
143 int num_hw_breakpoints;
145 /* Register names. */
146 char **register_names;
149 #define CURRENT_VARIANT (gdbarch_tdep (current_gdbarch))
152 /* Allocate a new variant structure, and set up default values for all
154 static struct gdbarch_tdep *
157 struct gdbarch_tdep *var;
161 var = xmalloc (sizeof (*var));
162 memset (var, 0, sizeof (*var));
166 var->num_hw_watchpoints = 0;
167 var->num_hw_breakpoints = 0;
169 /* By default, don't supply any general-purpose or floating-point
172 = (char **) xmalloc ((frv_num_regs + frv_num_pseudo_regs)
174 for (r = 0; r < frv_num_regs + frv_num_pseudo_regs; r++)
175 var->register_names[r] = "";
177 /* Do, however, supply default names for the known special-purpose
180 var->register_names[pc_regnum] = "pc";
181 var->register_names[lr_regnum] = "lr";
182 var->register_names[lcr_regnum] = "lcr";
184 var->register_names[psr_regnum] = "psr";
185 var->register_names[ccr_regnum] = "ccr";
186 var->register_names[cccr_regnum] = "cccr";
187 var->register_names[tbr_regnum] = "tbr";
189 /* Debug registers. */
190 var->register_names[brr_regnum] = "brr";
191 var->register_names[dbar0_regnum] = "dbar0";
192 var->register_names[dbar1_regnum] = "dbar1";
193 var->register_names[dbar2_regnum] = "dbar2";
194 var->register_names[dbar3_regnum] = "dbar3";
196 /* iacc0 (Only found on MB93405.) */
197 var->register_names[iacc0h_regnum] = "iacc0h";
198 var->register_names[iacc0l_regnum] = "iacc0l";
199 var->register_names[iacc0_regnum] = "iacc0";
205 /* Indicate that the variant VAR has NUM_GPRS general-purpose
206 registers, and fill in the names array appropriately. */
208 set_variant_num_gprs (struct gdbarch_tdep *var, int num_gprs)
212 var->num_gprs = num_gprs;
214 for (r = 0; r < num_gprs; ++r)
218 sprintf (buf, "gr%d", r);
219 var->register_names[first_gpr_regnum + r] = xstrdup (buf);
224 /* Indicate that the variant VAR has NUM_FPRS floating-point
225 registers, and fill in the names array appropriately. */
227 set_variant_num_fprs (struct gdbarch_tdep *var, int num_fprs)
231 var->num_fprs = num_fprs;
233 for (r = 0; r < num_fprs; ++r)
237 sprintf (buf, "fr%d", r);
238 var->register_names[first_fpr_regnum + r] = xstrdup (buf);
244 frv_register_name (int reg)
248 if (reg >= frv_num_regs + frv_num_pseudo_regs)
251 return CURRENT_VARIANT->register_names[reg];
256 frv_register_type (struct gdbarch *gdbarch, int reg)
258 if (reg >= first_fpr_regnum && reg <= last_fpr_regnum)
259 return builtin_type_float;
260 else if (reg == iacc0_regnum)
261 return builtin_type_int64;
263 return builtin_type_int32;
267 frv_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
268 int reg, void *buffer)
270 if (reg == iacc0_regnum)
272 regcache_raw_read (regcache, iacc0h_regnum, buffer);
273 regcache_raw_read (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4);
278 frv_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
279 int reg, const void *buffer)
281 if (reg == iacc0_regnum)
283 regcache_raw_write (regcache, iacc0h_regnum, buffer);
284 regcache_raw_write (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4);
289 frv_register_sim_regno (int reg)
291 static const int spr_map[] =
293 H_SPR_PSR, /* psr_regnum */
294 H_SPR_CCR, /* ccr_regnum */
295 H_SPR_CCCR, /* cccr_regnum */
299 H_SPR_TBR, /* tbr_regnum */
300 H_SPR_BRR, /* brr_regnum */
301 H_SPR_DBAR0, /* dbar0_regnum */
302 H_SPR_DBAR1, /* dbar1_regnum */
303 H_SPR_DBAR2, /* dbar2_regnum */
304 H_SPR_DBAR3, /* dbar3_regnum */
309 H_SPR_LR, /* lr_regnum */
310 H_SPR_LCR, /* lcr_regnum */
311 H_SPR_IACC0H, /* iacc0h_regnum */
312 H_SPR_IACC0L /* iacc0l_regnum */
315 gdb_assert (reg >= 0 && reg < NUM_REGS);
317 if (first_gpr_regnum <= reg && reg <= last_gpr_regnum)
318 return reg - first_gpr_regnum + SIM_FRV_GR0_REGNUM;
319 else if (first_fpr_regnum <= reg && reg <= last_fpr_regnum)
320 return reg - first_fpr_regnum + SIM_FRV_FR0_REGNUM;
321 else if (pc_regnum == reg)
322 return SIM_FRV_PC_REGNUM;
323 else if (reg >= first_spr_regnum
324 && reg < first_spr_regnum + sizeof (spr_map) / sizeof (spr_map[0]))
326 int spr_reg_offset = spr_map[reg - first_spr_regnum];
328 if (spr_reg_offset < 0)
329 return SIM_REGNO_DOES_NOT_EXIST;
331 return SIM_FRV_SPR0_REGNUM + spr_reg_offset;
334 internal_error (__FILE__, __LINE__, "Bad register number %d", reg);
337 static const unsigned char *
338 frv_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenp)
340 static unsigned char breakpoint[] = {0xc0, 0x70, 0x00, 0x01};
341 *lenp = sizeof (breakpoint);
345 /* Define the maximum number of instructions which may be packed into a
346 bundle (VLIW instruction). */
347 static const int max_instrs_per_bundle = 8;
349 /* Define the size (in bytes) of an FR-V instruction. */
350 static const int frv_instr_size = 4;
352 /* Adjust a breakpoint's address to account for the FR-V architecture's
353 constraint that a break instruction must not appear as any but the
354 first instruction in the bundle. */
356 frv_gdbarch_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
358 int count = max_instrs_per_bundle;
359 CORE_ADDR addr = bpaddr - frv_instr_size;
360 CORE_ADDR func_start = get_pc_function_start (bpaddr);
362 /* Find the end of the previous packing sequence. This will be indicated
363 by either attempting to access some inaccessible memory or by finding
364 an instruction word whose packing bit is set to one. */
365 while (count-- > 0 && addr >= func_start)
367 char instr[frv_instr_size];
370 status = read_memory_nobpt (addr, instr, sizeof instr);
375 /* This is a big endian architecture, so byte zero will have most
376 significant byte. The most significant bit of this byte is the
381 addr -= frv_instr_size;
385 bpaddr = addr + frv_instr_size;
391 /* Return true if REG is a caller-saves ("scratch") register,
394 is_caller_saves_reg (int reg)
396 return ((4 <= reg && reg <= 7)
397 || (14 <= reg && reg <= 15)
398 || (32 <= reg && reg <= 47));
402 /* Return true if REG is a callee-saves register, false otherwise. */
404 is_callee_saves_reg (int reg)
406 return ((16 <= reg && reg <= 31)
407 || (48 <= reg && reg <= 63));
411 /* Return true if REG is an argument register, false otherwise. */
413 is_argument_reg (int reg)
415 return (8 <= reg && reg <= 13);
418 /* Given PC at the function's start address, attempt to find the
419 prologue end using SAL information. Return zero if the skip fails.
421 A non-optimized prologue traditionally has one SAL for the function
422 and a second for the function body. A single line function has
423 them both pointing at the same line.
425 An optimized prologue is similar but the prologue may contain
426 instructions (SALs) from the instruction body. Need to skip those
427 while not getting into the function body.
429 The functions end point and an increasing SAL line are used as
430 indicators of the prologue's endpoint.
432 This code is based on the function refine_prologue_limit (versions
433 found in both ia64 and ppc). */
436 skip_prologue_using_sal (CORE_ADDR func_addr)
438 struct symtab_and_line prologue_sal;
442 /* Get an initial range for the function. */
443 find_pc_partial_function (func_addr, NULL, &start_pc, &end_pc);
444 start_pc += FUNCTION_START_OFFSET;
446 prologue_sal = find_pc_line (start_pc, 0);
447 if (prologue_sal.line != 0)
449 while (prologue_sal.end < end_pc)
451 struct symtab_and_line sal;
453 sal = find_pc_line (prologue_sal.end, 0);
456 /* Assume that a consecutive SAL for the same (or larger)
457 line mark the prologue -> body transition. */
458 if (sal.line >= prologue_sal.line)
460 /* The case in which compiler's optimizer/scheduler has
461 moved instructions into the prologue. We look ahead in
462 the function looking for address ranges whose
463 corresponding line number is less the first one that we
464 found for the function. This is more conservative then
465 refine_prologue_limit which scans a large number of SALs
466 looking for any in the prologue */
470 return prologue_sal.end;
474 /* Scan an FR-V prologue, starting at PC, until frame->PC.
475 If FRAME is non-zero, fill in its saved_regs with appropriate addresses.
476 We assume FRAME's saved_regs array has already been allocated and cleared.
477 Return the first PC value after the prologue.
479 Note that, for unoptimized code, we almost don't need this function
480 at all; all arguments and locals live on the stack, so we just need
481 the FP to find everything. The catch: structures passed by value
482 have their addresses living in registers; they're never spilled to
483 the stack. So if you ever want to be able to get to these
484 arguments in any frame but the top, you'll need to do this serious
485 prologue analysis. */
487 frv_analyze_prologue (CORE_ADDR pc, struct frame_info *next_frame,
488 struct frv_unwind_cache *info)
490 /* When writing out instruction bitpatterns, we use the following
491 letters to label instruction fields:
492 P - The parallel bit. We don't use this.
493 J - The register number of GRj in the instruction description.
494 K - The register number of GRk in the instruction description.
495 I - The register number of GRi.
496 S - a signed imediate offset.
497 U - an unsigned immediate offset.
499 The dots below the numbers indicate where hex digit boundaries
500 fall, to make it easier to check the numbers. */
502 /* Non-zero iff we've seen the instruction that initializes the
503 frame pointer for this function's frame. */
506 /* If fp_set is non_zero, then this is the distance from
507 the stack pointer to frame pointer: fp = sp + fp_offset. */
510 /* Total size of frame prior to any alloca operations. */
513 /* Flag indicating if lr has been saved on the stack. */
514 int lr_saved_on_stack = 0;
516 /* The number of the general-purpose register we saved the return
517 address ("link register") in, or -1 if we haven't moved it yet. */
518 int lr_save_reg = -1;
520 /* Offset (from sp) at which lr has been saved on the stack. */
522 int lr_sp_offset = 0;
524 /* If gr_saved[i] is non-zero, then we've noticed that general
525 register i has been saved at gr_sp_offset[i] from the stack
528 int gr_sp_offset[64];
530 /* The address of the most recently scanned prologue instruction. */
531 CORE_ADDR last_prologue_pc;
533 /* The address of the next instruction. */
536 /* The upper bound to of the pc values to scan. */
539 memset (gr_saved, 0, sizeof (gr_saved));
541 last_prologue_pc = pc;
543 /* Try to compute an upper limit (on how far to scan) based on the
545 lim_pc = skip_prologue_using_sal (pc);
546 /* If there's no line number info, lim_pc will be 0. In that case,
547 set the limit to be 100 instructions away from pc. Hopefully, this
548 will be far enough away to account for the entire prologue. Don't
549 worry about overshooting the end of the function. The scan loop
550 below contains some checks to avoid scanning unreasonably far. */
554 /* If we have a frame, we don't want to scan past the frame's pc. This
555 will catch those cases where the pc is in the prologue. */
558 CORE_ADDR frame_pc = frame_pc_unwind (next_frame);
559 if (frame_pc < lim_pc)
563 /* Scan the prologue. */
566 LONGEST op = read_memory_integer (pc, 4);
569 /* The tests in this chain of ifs should be in order of
570 decreasing selectivity, so that more particular patterns get
571 to fire before less particular patterns. */
573 /* Some sort of control transfer instruction: stop scanning prologue.
574 Integer Conditional Branch:
575 X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX
576 Floating-point / media Conditional Branch:
577 X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX
578 LCR Conditional Branch to LR
579 X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX
580 Integer conditional Branches to LR
581 X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX
582 X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX
583 Floating-point/Media Branches to LR
584 X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX
585 X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX
587 X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX
588 X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX
590 X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX
592 X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX
593 Integer Conditional Trap
594 X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX
595 X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX
596 Floating-point /media Conditional Trap
597 X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX
598 X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX
600 X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX
602 X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */
603 if ((op & 0x01d80000) == 0x00180000 /* Conditional branches and Call */
604 || (op & 0x01f80000) == 0x00300000 /* Jump and Link */
605 || (op & 0x01f80000) == 0x00100000 /* Return from Trap, Trap */
606 || (op & 0x01f80000) == 0x00700000) /* Trap immediate */
608 /* Stop scanning; not in prologue any longer. */
612 /* Loading something from memory into fp probably means that
613 we're in the epilogue. Stop scanning the prologue.
615 X 000010 0000010 XXXXXX 000100 XXXXXX
617 X 000010 0110010 XXXXXX XXXXXXXXXXXX */
618 else if ((op & 0x7ffc0fc0) == 0x04080100
619 || (op & 0x7ffc0000) == 0x04c80000)
624 /* Setting the FP from the SP:
626 P 000010 0100010 000001 000000000000 = 0x04881000
627 0 111111 1111111 111111 111111111111 = 0x7fffffff
629 We treat this as part of the prologue. */
630 else if ((op & 0x7fffffff) == 0x04881000)
634 last_prologue_pc = next_pc;
637 /* Move the link register to the scratch register grJ, before saving:
639 P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0
640 0 111111 1111111 111111 111111 000000 = 0x7fffffc0
642 We treat this as part of the prologue. */
643 else if ((op & 0x7fffffc0) == 0x080d01c0)
645 int gr_j = op & 0x3f;
647 /* If we're moving it to a scratch register, that's fine. */
648 if (is_caller_saves_reg (gr_j))
651 last_prologue_pc = next_pc;
655 /* To save multiple callee-saves registers on the stack, at
659 P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0
660 0 000000 1111111 111111 111111 111111 = 0x01ffffff
663 P KKKKKK 0000011 000001 000100 000000 = 0x000c1100
664 0 000000 1111111 111111 111111 111111 = 0x01ffffff
666 We treat this as part of the prologue, and record the register's
667 saved address in the frame structure. */
668 else if ((op & 0x01ffffff) == 0x000c10c0
669 || (op & 0x01ffffff) == 0x000c1100)
671 int gr_k = ((op >> 25) & 0x3f);
672 int ope = ((op >> 6) & 0x3f);
676 /* Is it an std or an stq? */
682 /* Is it really a callee-saves register? */
683 if (is_callee_saves_reg (gr_k))
685 for (i = 0; i < count; i++)
687 gr_saved[gr_k + i] = 1;
688 gr_sp_offset[gr_k + i] = 4 * i;
690 last_prologue_pc = next_pc;
694 /* Adjusting the stack pointer. (The stack pointer is GR1.)
696 P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000
697 0 111111 1111111 111111 000000000000 = 0x7ffff000
699 We treat this as part of the prologue. */
700 else if ((op & 0x7ffff000) == 0x02401000)
704 /* Sign-extend the twelve-bit field.
705 (Isn't there a better way to do this?) */
706 int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
709 last_prologue_pc = pc;
713 /* If the prologue is being adjusted again, we've
714 likely gone too far; i.e. we're probably in the
720 /* Setting the FP to a constant distance from the SP:
722 P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000
723 0 111111 1111111 111111 000000000000 = 0x7ffff000
725 We treat this as part of the prologue. */
726 else if ((op & 0x7ffff000) == 0x04401000)
728 /* Sign-extend the twelve-bit field.
729 (Isn't there a better way to do this?) */
730 int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
733 last_prologue_pc = pc;
736 /* To spill an argument register to a scratch register:
738 P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000
739 0 000000 1111111 000000 111111111111 = 0x01fc0fff
741 For the time being, we treat this as a prologue instruction,
742 assuming that GRi is an argument register. This one's kind
743 of suspicious, because it seems like it could be part of a
744 legitimate body instruction. But we only come here when the
745 source info wasn't helpful, so we have to do the best we can.
746 Hopefully once GCC and GDB agree on how to emit line number
747 info for prologues, then this code will never come into play. */
748 else if ((op & 0x01fc0fff) == 0x00880000)
750 int gr_i = ((op >> 12) & 0x3f);
752 /* Make sure that the source is an arg register; if it is, we'll
753 treat it as a prologue instruction. */
754 if (is_argument_reg (gr_i))
755 last_prologue_pc = next_pc;
758 /* To spill 16-bit values to the stack:
760 P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000
761 0 000000 1111111 111111 000000000000 = 0x01fff000
763 And for 8-bit values, we use STB instructions.
765 P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000
766 0 000000 1111111 111111 000000000000 = 0x01fff000
768 We check that GRk is really an argument register, and treat
769 all such as part of the prologue. */
770 else if ( (op & 0x01fff000) == 0x01442000
771 || (op & 0x01fff000) == 0x01402000)
773 int gr_k = ((op >> 25) & 0x3f);
775 /* Make sure that GRk is really an argument register; treat
776 it as a prologue instruction if so. */
777 if (is_argument_reg (gr_k))
778 last_prologue_pc = next_pc;
781 /* To save multiple callee-saves register on the stack, at a
785 P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000
786 0 000000 1111111 111111 000000000000 = 0x01fff000
789 P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000
790 0 000000 1111111 111111 000000000000 = 0x01fff000
792 We treat this as part of the prologue, and record the register's
793 saved address in the frame structure. */
794 else if ((op & 0x01fff000) == 0x014c1000
795 || (op & 0x01fff000) == 0x01501000)
797 int gr_k = ((op >> 25) & 0x3f);
801 /* Is it a stdi or a stqi? */
802 if ((op & 0x01fff000) == 0x014c1000)
807 /* Is it really a callee-saves register? */
808 if (is_callee_saves_reg (gr_k))
810 /* Sign-extend the twelve-bit field.
811 (Isn't there a better way to do this?) */
812 int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
814 for (i = 0; i < count; i++)
816 gr_saved[gr_k + i] = 1;
817 gr_sp_offset[gr_k + i] = s + (4 * i);
819 last_prologue_pc = next_pc;
823 /* Storing any kind of integer register at any constant offset
824 from any other register.
827 P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080
828 0 000000 1111111 000000 111111 111111 = 0x01fc0fff
831 P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000
832 0 000000 1111111 000000 000000000000 = 0x01fc0000
834 These could be almost anything, but a lot of prologue
835 instructions fall into this pattern, so let's decode the
836 instruction once, and then work at a higher level. */
837 else if (((op & 0x01fc0fff) == 0x000c0080)
838 || ((op & 0x01fc0000) == 0x01480000))
840 int gr_k = ((op >> 25) & 0x3f);
841 int gr_i = ((op >> 12) & 0x3f);
844 /* Are we storing with gr0 as an offset, or using an
846 if ((op & 0x01fc0fff) == 0x000c0080)
849 offset = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
851 /* If the address isn't relative to the SP or FP, it's not a
852 prologue instruction. */
853 if (gr_i != sp_regnum && gr_i != fp_regnum)
855 /* Do nothing; not a prologue instruction. */
858 /* Saving the old FP in the new frame (relative to the SP). */
859 else if (gr_k == fp_regnum && gr_i == sp_regnum)
861 gr_saved[fp_regnum] = 1;
862 gr_sp_offset[fp_regnum] = offset;
863 last_prologue_pc = next_pc;
866 /* Saving callee-saves register(s) on the stack, relative to
868 else if (gr_i == sp_regnum
869 && is_callee_saves_reg (gr_k))
872 if (gr_i == sp_regnum)
873 gr_sp_offset[gr_k] = offset;
875 gr_sp_offset[gr_k] = offset + fp_offset;
876 last_prologue_pc = next_pc;
879 /* Saving the scratch register holding the return address. */
880 else if (lr_save_reg != -1
881 && gr_k == lr_save_reg)
883 lr_saved_on_stack = 1;
884 if (gr_i == sp_regnum)
885 lr_sp_offset = offset;
887 lr_sp_offset = offset + fp_offset;
888 last_prologue_pc = next_pc;
891 /* Spilling int-sized arguments to the stack. */
892 else if (is_argument_reg (gr_k))
893 last_prologue_pc = next_pc;
898 if (next_frame && info)
903 /* If we know the relationship between the stack and frame
904 pointers, record the addresses of the registers we noticed.
905 Note that we have to do this as a separate step at the end,
906 because instructions may save relative to the SP, but we need
907 their addresses relative to the FP. */
909 frame_unwind_unsigned_register (next_frame, fp_regnum, &this_base);
911 frame_unwind_unsigned_register (next_frame, sp_regnum, &this_base);
913 for (i = 0; i < 64; i++)
915 info->saved_regs[i].addr = this_base - fp_offset + gr_sp_offset[i];
917 info->prev_sp = this_base - fp_offset + framesize;
918 info->base = this_base;
920 /* If LR was saved on the stack, record its location. */
921 if (lr_saved_on_stack)
922 info->saved_regs[lr_regnum].addr = this_base - fp_offset + lr_sp_offset;
924 /* The call instruction moves the caller's PC in the callee's LR.
925 Since this is an unwind, do the reverse. Copy the location of LR
926 into PC (the address / regnum) so that a request for PC will be
927 converted into a request for the LR. */
928 info->saved_regs[pc_regnum] = info->saved_regs[lr_regnum];
930 /* Save the previous frame's computed SP value. */
931 trad_frame_set_value (info->saved_regs, sp_regnum, info->prev_sp);
934 return last_prologue_pc;
939 frv_skip_prologue (CORE_ADDR pc)
941 CORE_ADDR func_addr, func_end, new_pc;
945 /* If the line table has entry for a line *within* the function
946 (i.e., not in the prologue, and not past the end), then that's
948 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
950 struct symtab_and_line sal;
952 sal = find_pc_line (func_addr, 0);
954 if (sal.line != 0 && sal.end < func_end)
960 /* The FR-V prologue is at least five instructions long (twenty bytes).
961 If we didn't find a real source location past that, then
962 do a full analysis of the prologue. */
963 if (new_pc < pc + 20)
964 new_pc = frv_analyze_prologue (pc, 0, 0);
970 static struct frv_unwind_cache *
971 frv_frame_unwind_cache (struct frame_info *next_frame,
972 void **this_prologue_cache)
974 struct gdbarch *gdbarch = get_frame_arch (next_frame);
978 struct frv_unwind_cache *info;
980 if ((*this_prologue_cache))
981 return (*this_prologue_cache);
983 info = FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache);
984 (*this_prologue_cache) = info;
985 info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
987 /* Prologue analysis does the rest... */
988 frv_analyze_prologue (frame_func_unwind (next_frame), next_frame, info);
994 frv_extract_return_value (struct type *type, struct regcache *regcache,
997 int len = TYPE_LENGTH (type);
1002 regcache_cooked_read_unsigned (regcache, 8, &gpr8_val);
1003 store_unsigned_integer (valbuf, len, gpr8_val);
1008 regcache_cooked_read_unsigned (regcache, 8, ®val);
1009 store_unsigned_integer (valbuf, 4, regval);
1010 regcache_cooked_read_unsigned (regcache, 9, ®val);
1011 store_unsigned_integer ((bfd_byte *) valbuf + 4, 4, regval);
1014 internal_error (__FILE__, __LINE__, "Illegal return value length: %d", len);
1018 frv_extract_struct_value_address (struct regcache *regcache)
1021 regcache_cooked_read_unsigned (regcache, struct_return_regnum, &addr);
1026 frv_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
1028 write_register (struct_return_regnum, addr);
1032 frv_frameless_function_invocation (struct frame_info *frame)
1034 return frameless_look_for_prologue (frame);
1038 frv_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1040 /* Require dword alignment. */
1041 return align_down (sp, 8);
1045 frv_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
1046 struct regcache *regcache, CORE_ADDR bp_addr,
1047 int nargs, struct value **args, CORE_ADDR sp,
1048 int struct_return, CORE_ADDR struct_addr)
1055 struct type *arg_type;
1057 enum type_code typecode;
1063 printf("Push %d args at sp = %x, struct_return=%d (%x)\n",
1064 nargs, (int) sp, struct_return, struct_addr);
1068 for (argnum = 0; argnum < nargs; ++argnum)
1069 stack_space += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), 4);
1071 stack_space -= (6 * 4);
1072 if (stack_space > 0)
1075 /* Make sure stack is dword aligned. */
1076 sp = align_down (sp, 8);
1083 regcache_cooked_write_unsigned (regcache, struct_return_regnum,
1086 for (argnum = 0; argnum < nargs; ++argnum)
1089 arg_type = check_typedef (VALUE_TYPE (arg));
1090 len = TYPE_LENGTH (arg_type);
1091 typecode = TYPE_CODE (arg_type);
1093 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
1095 store_unsigned_integer (valbuf, 4, VALUE_ADDRESS (arg));
1096 typecode = TYPE_CODE_PTR;
1102 val = (char *) VALUE_CONTENTS (arg);
1107 int partial_len = (len < 4 ? len : 4);
1111 regval = extract_unsigned_integer (val, partial_len);
1113 printf(" Argnum %d data %x -> reg %d\n",
1114 argnum, (int) regval, argreg);
1116 regcache_cooked_write_unsigned (regcache, argreg, regval);
1122 printf(" Argnum %d data %x -> offset %d (%x)\n",
1123 argnum, *((int *)val), stack_offset, (int) (sp + stack_offset));
1125 write_memory (sp + stack_offset, val, partial_len);
1126 stack_offset += align_up (partial_len, 4);
1133 /* Set the return address. For the frv, the return breakpoint is
1134 always at BP_ADDR. */
1135 regcache_cooked_write_unsigned (regcache, lr_regnum, bp_addr);
1137 /* Finally, update the SP register. */
1138 regcache_cooked_write_unsigned (regcache, sp_regnum, sp);
1144 frv_store_return_value (struct type *type, struct regcache *regcache,
1147 int len = TYPE_LENGTH (type);
1152 memset (val, 0, sizeof (val));
1153 memcpy (val + (4 - len), valbuf, len);
1154 regcache_cooked_write (regcache, 8, val);
1158 regcache_cooked_write (regcache, 8, valbuf);
1159 regcache_cooked_write (regcache, 9, (bfd_byte *) valbuf + 4);
1162 internal_error (__FILE__, __LINE__,
1163 "Don't know how to return a %d-byte value.", len);
1167 /* Hardware watchpoint / breakpoint support for the FR500
1171 frv_check_watch_resources (int type, int cnt, int ot)
1173 struct gdbarch_tdep *var = CURRENT_VARIANT;
1175 /* Watchpoints not supported on simulator. */
1176 if (strcmp (target_shortname, "sim") == 0)
1179 if (type == bp_hardware_breakpoint)
1181 if (var->num_hw_breakpoints == 0)
1183 else if (cnt <= var->num_hw_breakpoints)
1188 if (var->num_hw_watchpoints == 0)
1192 else if (cnt <= var->num_hw_watchpoints)
1200 frv_stopped_data_address (void)
1202 CORE_ADDR brr, dbar0, dbar1, dbar2, dbar3;
1204 brr = read_register (brr_regnum);
1205 dbar0 = read_register (dbar0_regnum);
1206 dbar1 = read_register (dbar1_regnum);
1207 dbar2 = read_register (dbar2_regnum);
1208 dbar3 = read_register (dbar3_regnum);
1212 else if (brr & (1<<10))
1214 else if (brr & (1<<9))
1216 else if (brr & (1<<8))
1223 frv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1225 return frame_unwind_register_unsigned (next_frame, pc_regnum);
1228 /* Given a GDB frame, determine the address of the calling function's
1229 frame. This will be used to create a new GDB frame struct. */
1232 frv_frame_this_id (struct frame_info *next_frame,
1233 void **this_prologue_cache, struct frame_id *this_id)
1235 struct frv_unwind_cache *info
1236 = frv_frame_unwind_cache (next_frame, this_prologue_cache);
1239 struct minimal_symbol *msym_stack;
1242 /* The FUNC is easy. */
1243 func = frame_func_unwind (next_frame);
1245 /* Check if the stack is empty. */
1246 msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL);
1247 if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack))
1250 /* Hopefully the prologue analysis either correctly determined the
1251 frame's base (which is the SP from the previous frame), or set
1252 that base to "NULL". */
1253 base = info->prev_sp;
1257 id = frame_id_build (base, func);
1259 /* Check that we're not going round in circles with the same frame
1260 ID (but avoid applying the test to sentinel frames which do go
1261 round in circles). Can't use frame_id_eq() as that doesn't yet
1262 compare the frame's PC value. */
1263 if (frame_relative_level (next_frame) >= 0
1264 && get_frame_type (next_frame) != DUMMY_FRAME
1265 && frame_id_eq (get_frame_id (next_frame), id))
1272 frv_frame_prev_register (struct frame_info *next_frame,
1273 void **this_prologue_cache,
1274 int regnum, int *optimizedp,
1275 enum lval_type *lvalp, CORE_ADDR *addrp,
1276 int *realnump, void *bufferp)
1278 struct frv_unwind_cache *info
1279 = frv_frame_unwind_cache (next_frame, this_prologue_cache);
1280 trad_frame_prev_register (next_frame, info->saved_regs, regnum,
1281 optimizedp, lvalp, addrp, realnump, bufferp);
1284 static const struct frame_unwind frv_frame_unwind = {
1287 frv_frame_prev_register
1290 static const struct frame_unwind *
1291 frv_frame_sniffer (struct frame_info *next_frame)
1293 return &frv_frame_unwind;
1297 frv_frame_base_address (struct frame_info *next_frame, void **this_cache)
1299 struct frv_unwind_cache *info
1300 = frv_frame_unwind_cache (next_frame, this_cache);
1304 static const struct frame_base frv_frame_base = {
1306 frv_frame_base_address,
1307 frv_frame_base_address,
1308 frv_frame_base_address
1312 frv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1314 return frame_unwind_register_unsigned (next_frame, sp_regnum);
1318 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1319 dummy frame. The frame ID's base needs to match the TOS value
1320 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1323 static struct frame_id
1324 frv_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1326 return frame_id_build (frv_unwind_sp (gdbarch, next_frame),
1327 frame_pc_unwind (next_frame));
1331 static struct gdbarch *
1332 frv_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1334 struct gdbarch *gdbarch;
1335 struct gdbarch_tdep *var;
1337 /* Check to see if we've already built an appropriate architecture
1338 object for this executable. */
1339 arches = gdbarch_list_lookup_by_info (arches, &info);
1341 return arches->gdbarch;
1343 /* Select the right tdep structure for this variant. */
1344 var = new_variant ();
1345 switch (info.bfd_arch_info->mach)
1348 case bfd_mach_frvsimple:
1349 case bfd_mach_fr500:
1350 case bfd_mach_frvtomcat:
1351 case bfd_mach_fr550:
1352 set_variant_num_gprs (var, 64);
1353 set_variant_num_fprs (var, 64);
1356 case bfd_mach_fr400:
1357 set_variant_num_gprs (var, 32);
1358 set_variant_num_fprs (var, 32);
1362 /* Never heard of this variant. */
1366 gdbarch = gdbarch_alloc (&info, var);
1368 set_gdbarch_short_bit (gdbarch, 16);
1369 set_gdbarch_int_bit (gdbarch, 32);
1370 set_gdbarch_long_bit (gdbarch, 32);
1371 set_gdbarch_long_long_bit (gdbarch, 64);
1372 set_gdbarch_float_bit (gdbarch, 32);
1373 set_gdbarch_double_bit (gdbarch, 64);
1374 set_gdbarch_long_double_bit (gdbarch, 64);
1375 set_gdbarch_ptr_bit (gdbarch, 32);
1377 set_gdbarch_num_regs (gdbarch, frv_num_regs);
1378 set_gdbarch_num_pseudo_regs (gdbarch, frv_num_pseudo_regs);
1380 set_gdbarch_sp_regnum (gdbarch, sp_regnum);
1381 set_gdbarch_deprecated_fp_regnum (gdbarch, fp_regnum);
1382 set_gdbarch_pc_regnum (gdbarch, pc_regnum);
1384 set_gdbarch_register_name (gdbarch, frv_register_name);
1385 set_gdbarch_register_type (gdbarch, frv_register_type);
1386 set_gdbarch_register_sim_regno (gdbarch, frv_register_sim_regno);
1388 set_gdbarch_pseudo_register_read (gdbarch, frv_pseudo_register_read);
1389 set_gdbarch_pseudo_register_write (gdbarch, frv_pseudo_register_write);
1391 set_gdbarch_skip_prologue (gdbarch, frv_skip_prologue);
1392 set_gdbarch_breakpoint_from_pc (gdbarch, frv_breakpoint_from_pc);
1393 set_gdbarch_adjust_breakpoint_address (gdbarch, frv_gdbarch_adjust_breakpoint_address);
1395 set_gdbarch_frame_args_skip (gdbarch, 0);
1396 set_gdbarch_frameless_function_invocation (gdbarch, frv_frameless_function_invocation);
1398 set_gdbarch_use_struct_convention (gdbarch, always_use_struct_convention);
1399 set_gdbarch_extract_return_value (gdbarch, frv_extract_return_value);
1401 set_gdbarch_deprecated_store_struct_return (gdbarch, frv_store_struct_return);
1402 set_gdbarch_store_return_value (gdbarch, frv_store_return_value);
1403 set_gdbarch_extract_struct_value_address (gdbarch, frv_extract_struct_value_address);
1406 set_gdbarch_unwind_pc (gdbarch, frv_unwind_pc);
1407 set_gdbarch_unwind_sp (gdbarch, frv_unwind_sp);
1408 set_gdbarch_frame_align (gdbarch, frv_frame_align);
1409 frame_unwind_append_sniffer (gdbarch, frv_frame_sniffer);
1410 frame_base_set_default (gdbarch, &frv_frame_base);
1412 /* Settings for calling functions in the inferior. */
1413 set_gdbarch_push_dummy_call (gdbarch, frv_push_dummy_call);
1414 set_gdbarch_unwind_dummy_id (gdbarch, frv_unwind_dummy_id);
1416 /* Settings that should be unnecessary. */
1417 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1419 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
1421 set_gdbarch_remote_translate_xfer_address
1422 (gdbarch, generic_remote_translate_xfer_address);
1424 /* Hardware watchpoint / breakpoint support. */
1425 switch (info.bfd_arch_info->mach)
1428 case bfd_mach_frvsimple:
1429 case bfd_mach_fr500:
1430 case bfd_mach_frvtomcat:
1431 /* fr500-style hardware debugging support. */
1432 var->num_hw_watchpoints = 4;
1433 var->num_hw_breakpoints = 4;
1436 case bfd_mach_fr400:
1437 /* fr400-style hardware debugging support. */
1438 var->num_hw_watchpoints = 2;
1439 var->num_hw_breakpoints = 4;
1443 /* Otherwise, assume we don't have hardware debugging support. */
1444 var->num_hw_watchpoints = 0;
1445 var->num_hw_breakpoints = 0;
1449 set_gdbarch_print_insn (gdbarch, print_insn_frv);
1455 _initialize_frv_tdep (void)
1457 register_gdbarch_init (bfd_arch_frv, frv_gdbarch_init);