1 /* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger.
2 Copyright 2002, 2003 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 #include "gdb_string.h"
24 #include "symfile.h" /* for entry_point_address */
26 #include "arch-utils.h"
29 #include "frame-unwind.h"
30 #include "frame-base.h"
31 #include "trad-frame.h"
33 #include "gdb_assert.h"
34 #include "sim-regno.h"
35 #include "gdb/sim-frv.h"
36 #include "opcodes/frv-desc.h" /* for the H_SPR_... enums */
38 extern void _initialize_frv_tdep (void);
40 static gdbarch_init_ftype frv_gdbarch_init;
42 static gdbarch_register_name_ftype frv_register_name;
43 static gdbarch_breakpoint_from_pc_ftype frv_breakpoint_from_pc;
44 static gdbarch_adjust_breakpoint_address_ftype frv_gdbarch_adjust_breakpoint_address;
45 static gdbarch_skip_prologue_ftype frv_skip_prologue;
46 static gdbarch_frameless_function_invocation_ftype frv_frameless_function_invocation;
47 static gdbarch_deprecated_push_arguments_ftype frv_push_arguments;
48 static gdbarch_deprecated_saved_pc_after_call_ftype frv_saved_pc_after_call;
50 /* Register numbers. The order in which these appear define the
51 remote protocol, so take care in changing them. */
53 /* Register numbers 0 -- 63 are always reserved for general-purpose
54 registers. The chip at hand may have less. */
58 struct_return_regnum = 3,
61 /* Register numbers 64 -- 127 are always reserved for floating-point
62 registers. The chip at hand may have less. */
63 first_fpr_regnum = 64,
64 last_fpr_regnum = 127,
66 /* The PC register. */
69 /* Register numbers 129 on up are always reserved for special-purpose
71 first_spr_regnum = 129,
85 last_spr_regnum = 148,
87 /* The total number of registers we know exist. */
88 frv_num_regs = last_spr_regnum + 1,
90 /* Pseudo registers */
91 first_pseudo_regnum = frv_num_regs,
93 /* iacc0 - the 64-bit concatenation of iacc0h and iacc0l. */
94 iacc0_regnum = first_pseudo_regnum + 0,
96 last_pseudo_regnum = iacc0_regnum,
97 frv_num_pseudo_regs = last_pseudo_regnum - first_pseudo_regnum + 1,
100 static LONGEST frv_call_dummy_words[] =
104 struct frv_unwind_cache /* was struct frame_extra_info */
106 /* The previous frame's inner-most stack address. Used as this
107 frame ID's stack_addr. */
110 /* The frame's base, optionally used by the high-level debug info. */
113 /* Table indicating the location of each and every register. */
114 struct trad_frame_saved_reg *saved_regs;
118 /* A structure describing a particular variant of the FRV.
119 We allocate and initialize one of these structures when we create
120 the gdbarch object for a variant.
122 At the moment, all the FR variants we support differ only in which
123 registers are present; the portable code of GDB knows that
124 registers whose names are the empty string don't exist, so the
125 `register_names' array captures all the per-variant information we
128 in the future, if we need to have per-variant maps for raw size,
129 virtual type, etc., we should replace register_names with an array
130 of structures, each of which gives all the necessary info for one
131 register. Don't stick parallel arrays in here --- that's so
135 /* How many general-purpose registers does this variant have? */
138 /* How many floating-point registers does this variant have? */
141 /* How many hardware watchpoints can it support? */
142 int num_hw_watchpoints;
144 /* How many hardware breakpoints can it support? */
145 int num_hw_breakpoints;
147 /* Register names. */
148 char **register_names;
151 #define CURRENT_VARIANT (gdbarch_tdep (current_gdbarch))
154 /* Allocate a new variant structure, and set up default values for all
156 static struct gdbarch_tdep *
159 struct gdbarch_tdep *var;
163 var = xmalloc (sizeof (*var));
164 memset (var, 0, sizeof (*var));
168 var->num_hw_watchpoints = 0;
169 var->num_hw_breakpoints = 0;
171 /* By default, don't supply any general-purpose or floating-point
174 = (char **) xmalloc ((frv_num_regs + frv_num_pseudo_regs)
176 for (r = 0; r < frv_num_regs + frv_num_pseudo_regs; r++)
177 var->register_names[r] = "";
179 /* Do, however, supply default names for the known special-purpose
182 var->register_names[pc_regnum] = "pc";
183 var->register_names[lr_regnum] = "lr";
184 var->register_names[lcr_regnum] = "lcr";
186 var->register_names[psr_regnum] = "psr";
187 var->register_names[ccr_regnum] = "ccr";
188 var->register_names[cccr_regnum] = "cccr";
189 var->register_names[tbr_regnum] = "tbr";
191 /* Debug registers. */
192 var->register_names[brr_regnum] = "brr";
193 var->register_names[dbar0_regnum] = "dbar0";
194 var->register_names[dbar1_regnum] = "dbar1";
195 var->register_names[dbar2_regnum] = "dbar2";
196 var->register_names[dbar3_regnum] = "dbar3";
198 /* iacc0 (Only found on MB93405.) */
199 var->register_names[iacc0h_regnum] = "iacc0h";
200 var->register_names[iacc0l_regnum] = "iacc0l";
201 var->register_names[iacc0_regnum] = "iacc0";
207 /* Indicate that the variant VAR has NUM_GPRS general-purpose
208 registers, and fill in the names array appropriately. */
210 set_variant_num_gprs (struct gdbarch_tdep *var, int num_gprs)
214 var->num_gprs = num_gprs;
216 for (r = 0; r < num_gprs; ++r)
220 sprintf (buf, "gr%d", r);
221 var->register_names[first_gpr_regnum + r] = xstrdup (buf);
226 /* Indicate that the variant VAR has NUM_FPRS floating-point
227 registers, and fill in the names array appropriately. */
229 set_variant_num_fprs (struct gdbarch_tdep *var, int num_fprs)
233 var->num_fprs = num_fprs;
235 for (r = 0; r < num_fprs; ++r)
239 sprintf (buf, "fr%d", r);
240 var->register_names[first_fpr_regnum + r] = xstrdup (buf);
246 frv_register_name (int reg)
250 if (reg >= frv_num_regs + frv_num_pseudo_regs)
253 return CURRENT_VARIANT->register_names[reg];
258 frv_register_type (struct gdbarch *gdbarch, int reg)
260 if (reg >= first_fpr_regnum && reg <= last_fpr_regnum)
261 return builtin_type_float;
262 else if (reg == iacc0_regnum)
263 return builtin_type_int64;
265 return builtin_type_int32;
269 frv_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
270 int reg, void *buffer)
272 if (reg == iacc0_regnum)
274 regcache_raw_read (regcache, iacc0h_regnum, buffer);
275 regcache_raw_read (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4);
280 frv_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
281 int reg, const void *buffer)
283 if (reg == iacc0_regnum)
285 regcache_raw_write (regcache, iacc0h_regnum, buffer);
286 regcache_raw_write (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4);
291 frv_register_sim_regno (int reg)
293 static const int spr_map[] =
295 H_SPR_PSR, /* psr_regnum */
296 H_SPR_CCR, /* ccr_regnum */
297 H_SPR_CCCR, /* cccr_regnum */
301 H_SPR_TBR, /* tbr_regnum */
302 H_SPR_BRR, /* brr_regnum */
303 H_SPR_DBAR0, /* dbar0_regnum */
304 H_SPR_DBAR1, /* dbar1_regnum */
305 H_SPR_DBAR2, /* dbar2_regnum */
306 H_SPR_DBAR3, /* dbar3_regnum */
311 H_SPR_LR, /* lr_regnum */
312 H_SPR_LCR, /* lcr_regnum */
313 H_SPR_IACC0H, /* iacc0h_regnum */
314 H_SPR_IACC0L /* iacc0l_regnum */
317 gdb_assert (reg >= 0 && reg < NUM_REGS);
319 if (first_gpr_regnum <= reg && reg <= last_gpr_regnum)
320 return reg - first_gpr_regnum + SIM_FRV_GR0_REGNUM;
321 else if (first_fpr_regnum <= reg && reg <= last_fpr_regnum)
322 return reg - first_fpr_regnum + SIM_FRV_FR0_REGNUM;
323 else if (pc_regnum == reg)
324 return SIM_FRV_PC_REGNUM;
325 else if (reg >= first_spr_regnum
326 && reg < first_spr_regnum + sizeof (spr_map) / sizeof (spr_map[0]))
328 int spr_reg_offset = spr_map[reg - first_spr_regnum];
330 if (spr_reg_offset < 0)
331 return SIM_REGNO_DOES_NOT_EXIST;
333 return SIM_FRV_SPR0_REGNUM + spr_reg_offset;
336 internal_error (__FILE__, __LINE__, "Bad register number %d", reg);
339 static const unsigned char *
340 frv_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenp)
342 static unsigned char breakpoint[] = {0xc0, 0x70, 0x00, 0x01};
343 *lenp = sizeof (breakpoint);
347 /* Define the maximum number of instructions which may be packed into a
348 bundle (VLIW instruction). */
349 static const int max_instrs_per_bundle = 8;
351 /* Define the size (in bytes) of an FR-V instruction. */
352 static const int frv_instr_size = 4;
354 /* Adjust a breakpoint's address to account for the FR-V architecture's
355 constraint that a break instruction must not appear as any but the
356 first instruction in the bundle. */
358 frv_gdbarch_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
360 int count = max_instrs_per_bundle;
361 CORE_ADDR addr = bpaddr - frv_instr_size;
362 CORE_ADDR func_start = get_pc_function_start (bpaddr);
364 /* Find the end of the previous packing sequence. This will be indicated
365 by either attempting to access some inaccessible memory or by finding
366 an instruction word whose packing bit is set to one. */
367 while (count-- > 0 && addr >= func_start)
369 char instr[frv_instr_size];
372 status = read_memory_nobpt (addr, instr, sizeof instr);
377 /* This is a big endian architecture, so byte zero will have most
378 significant byte. The most significant bit of this byte is the
383 addr -= frv_instr_size;
387 bpaddr = addr + frv_instr_size;
393 /* Return true if REG is a caller-saves ("scratch") register,
396 is_caller_saves_reg (int reg)
398 return ((4 <= reg && reg <= 7)
399 || (14 <= reg && reg <= 15)
400 || (32 <= reg && reg <= 47));
404 /* Return true if REG is a callee-saves register, false otherwise. */
406 is_callee_saves_reg (int reg)
408 return ((16 <= reg && reg <= 31)
409 || (48 <= reg && reg <= 63));
413 /* Return true if REG is an argument register, false otherwise. */
415 is_argument_reg (int reg)
417 return (8 <= reg && reg <= 13);
420 /* Given PC at the function's start address, attempt to find the
421 prologue end using SAL information. Return zero if the skip fails.
423 A non-optimized prologue traditionally has one SAL for the function
424 and a second for the function body. A single line function has
425 them both pointing at the same line.
427 An optimized prologue is similar but the prologue may contain
428 instructions (SALs) from the instruction body. Need to skip those
429 while not getting into the function body.
431 The functions end point and an increasing SAL line are used as
432 indicators of the prologue's endpoint.
434 This code is based on the function refine_prologue_limit (versions
435 found in both ia64 and ppc). */
438 skip_prologue_using_sal (CORE_ADDR func_addr)
440 struct symtab_and_line prologue_sal;
444 /* Get an initial range for the function. */
445 find_pc_partial_function (func_addr, NULL, &start_pc, &end_pc);
446 start_pc += FUNCTION_START_OFFSET;
448 prologue_sal = find_pc_line (start_pc, 0);
449 if (prologue_sal.line != 0)
451 while (prologue_sal.end < end_pc)
453 struct symtab_and_line sal;
455 sal = find_pc_line (prologue_sal.end, 0);
458 /* Assume that a consecutive SAL for the same (or larger)
459 line mark the prologue -> body transition. */
460 if (sal.line >= prologue_sal.line)
462 /* The case in which compiler's optimizer/scheduler has
463 moved instructions into the prologue. We look ahead in
464 the function looking for address ranges whose
465 corresponding line number is less the first one that we
466 found for the function. This is more conservative then
467 refine_prologue_limit which scans a large number of SALs
468 looking for any in the prologue */
472 return prologue_sal.end;
476 /* Scan an FR-V prologue, starting at PC, until frame->PC.
477 If FRAME is non-zero, fill in its saved_regs with appropriate addresses.
478 We assume FRAME's saved_regs array has already been allocated and cleared.
479 Return the first PC value after the prologue.
481 Note that, for unoptimized code, we almost don't need this function
482 at all; all arguments and locals live on the stack, so we just need
483 the FP to find everything. The catch: structures passed by value
484 have their addresses living in registers; they're never spilled to
485 the stack. So if you ever want to be able to get to these
486 arguments in any frame but the top, you'll need to do this serious
487 prologue analysis. */
489 frv_analyze_prologue (CORE_ADDR pc, struct frame_info *next_frame,
490 struct frv_unwind_cache *info)
492 /* When writing out instruction bitpatterns, we use the following
493 letters to label instruction fields:
494 P - The parallel bit. We don't use this.
495 J - The register number of GRj in the instruction description.
496 K - The register number of GRk in the instruction description.
497 I - The register number of GRi.
498 S - a signed imediate offset.
499 U - an unsigned immediate offset.
501 The dots below the numbers indicate where hex digit boundaries
502 fall, to make it easier to check the numbers. */
504 /* Non-zero iff we've seen the instruction that initializes the
505 frame pointer for this function's frame. */
508 /* If fp_set is non_zero, then this is the distance from
509 the stack pointer to frame pointer: fp = sp + fp_offset. */
512 /* Total size of frame prior to any alloca operations. */
515 /* Flag indicating if lr has been saved on the stack. */
516 int lr_saved_on_stack = 0;
518 /* The number of the general-purpose register we saved the return
519 address ("link register") in, or -1 if we haven't moved it yet. */
520 int lr_save_reg = -1;
522 /* Offset (from sp) at which lr has been saved on the stack. */
524 int lr_sp_offset = 0;
526 /* If gr_saved[i] is non-zero, then we've noticed that general
527 register i has been saved at gr_sp_offset[i] from the stack
530 int gr_sp_offset[64];
532 /* The address of the most recently scanned prologue instruction. */
533 CORE_ADDR last_prologue_pc;
535 /* The address of the next instruction. */
538 /* The upper bound to of the pc values to scan. */
541 memset (gr_saved, 0, sizeof (gr_saved));
543 last_prologue_pc = pc;
545 /* Try to compute an upper limit (on how far to scan) based on the
547 lim_pc = skip_prologue_using_sal (pc);
548 /* If there's no line number info, lim_pc will be 0. In that case,
549 set the limit to be 100 instructions away from pc. Hopefully, this
550 will be far enough away to account for the entire prologue. Don't
551 worry about overshooting the end of the function. The scan loop
552 below contains some checks to avoid scanning unreasonably far. */
556 /* If we have a frame, we don't want to scan past the frame's pc. This
557 will catch those cases where the pc is in the prologue. */
560 CORE_ADDR frame_pc = frame_pc_unwind (next_frame);
561 if (frame_pc < lim_pc)
565 /* Scan the prologue. */
568 LONGEST op = read_memory_integer (pc, 4);
571 /* The tests in this chain of ifs should be in order of
572 decreasing selectivity, so that more particular patterns get
573 to fire before less particular patterns. */
575 /* Some sort of control transfer instruction: stop scanning prologue.
576 Integer Conditional Branch:
577 X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX
578 Floating-point / media Conditional Branch:
579 X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX
580 LCR Conditional Branch to LR
581 X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX
582 Integer conditional Branches to LR
583 X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX
584 X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX
585 Floating-point/Media Branches to LR
586 X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX
587 X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX
589 X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX
590 X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX
592 X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX
594 X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX
595 Integer Conditional Trap
596 X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX
597 X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX
598 Floating-point /media Conditional Trap
599 X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX
600 X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX
602 X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX
604 X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */
605 if ((op & 0x01d80000) == 0x00180000 /* Conditional branches and Call */
606 || (op & 0x01f80000) == 0x00300000 /* Jump and Link */
607 || (op & 0x01f80000) == 0x00100000 /* Return from Trap, Trap */
608 || (op & 0x01f80000) == 0x00700000) /* Trap immediate */
610 /* Stop scanning; not in prologue any longer. */
614 /* Loading something from memory into fp probably means that
615 we're in the epilogue. Stop scanning the prologue.
617 X 000010 0000010 XXXXXX 000100 XXXXXX
619 X 000010 0110010 XXXXXX XXXXXXXXXXXX */
620 else if ((op & 0x7ffc0fc0) == 0x04080100
621 || (op & 0x7ffc0000) == 0x04c80000)
626 /* Setting the FP from the SP:
628 P 000010 0100010 000001 000000000000 = 0x04881000
629 0 111111 1111111 111111 111111111111 = 0x7fffffff
631 We treat this as part of the prologue. */
632 else if ((op & 0x7fffffff) == 0x04881000)
636 last_prologue_pc = next_pc;
639 /* Move the link register to the scratch register grJ, before saving:
641 P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0
642 0 111111 1111111 111111 111111 000000 = 0x7fffffc0
644 We treat this as part of the prologue. */
645 else if ((op & 0x7fffffc0) == 0x080d01c0)
647 int gr_j = op & 0x3f;
649 /* If we're moving it to a scratch register, that's fine. */
650 if (is_caller_saves_reg (gr_j))
653 last_prologue_pc = next_pc;
657 /* To save multiple callee-saves registers on the stack, at
661 P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0
662 0 000000 1111111 111111 111111 111111 = 0x01ffffff
665 P KKKKKK 0000011 000001 000100 000000 = 0x000c1100
666 0 000000 1111111 111111 111111 111111 = 0x01ffffff
668 We treat this as part of the prologue, and record the register's
669 saved address in the frame structure. */
670 else if ((op & 0x01ffffff) == 0x000c10c0
671 || (op & 0x01ffffff) == 0x000c1100)
673 int gr_k = ((op >> 25) & 0x3f);
674 int ope = ((op >> 6) & 0x3f);
678 /* Is it an std or an stq? */
684 /* Is it really a callee-saves register? */
685 if (is_callee_saves_reg (gr_k))
687 for (i = 0; i < count; i++)
689 gr_saved[gr_k + i] = 1;
690 gr_sp_offset[gr_k + i] = 4 * i;
692 last_prologue_pc = next_pc;
696 /* Adjusting the stack pointer. (The stack pointer is GR1.)
698 P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000
699 0 111111 1111111 111111 000000000000 = 0x7ffff000
701 We treat this as part of the prologue. */
702 else if ((op & 0x7ffff000) == 0x02401000)
706 /* Sign-extend the twelve-bit field.
707 (Isn't there a better way to do this?) */
708 int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
711 last_prologue_pc = pc;
715 /* If the prologue is being adjusted again, we've
716 likely gone too far; i.e. we're probably in the
722 /* Setting the FP to a constant distance from the SP:
724 P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000
725 0 111111 1111111 111111 000000000000 = 0x7ffff000
727 We treat this as part of the prologue. */
728 else if ((op & 0x7ffff000) == 0x04401000)
730 /* Sign-extend the twelve-bit field.
731 (Isn't there a better way to do this?) */
732 int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
735 last_prologue_pc = pc;
738 /* To spill an argument register to a scratch register:
740 P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000
741 0 000000 1111111 000000 111111111111 = 0x01fc0fff
743 For the time being, we treat this as a prologue instruction,
744 assuming that GRi is an argument register. This one's kind
745 of suspicious, because it seems like it could be part of a
746 legitimate body instruction. But we only come here when the
747 source info wasn't helpful, so we have to do the best we can.
748 Hopefully once GCC and GDB agree on how to emit line number
749 info for prologues, then this code will never come into play. */
750 else if ((op & 0x01fc0fff) == 0x00880000)
752 int gr_i = ((op >> 12) & 0x3f);
754 /* Make sure that the source is an arg register; if it is, we'll
755 treat it as a prologue instruction. */
756 if (is_argument_reg (gr_i))
757 last_prologue_pc = next_pc;
760 /* To spill 16-bit values to the stack:
762 P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000
763 0 000000 1111111 111111 000000000000 = 0x01fff000
765 And for 8-bit values, we use STB instructions.
767 P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000
768 0 000000 1111111 111111 000000000000 = 0x01fff000
770 We check that GRk is really an argument register, and treat
771 all such as part of the prologue. */
772 else if ( (op & 0x01fff000) == 0x01442000
773 || (op & 0x01fff000) == 0x01402000)
775 int gr_k = ((op >> 25) & 0x3f);
777 /* Make sure that GRk is really an argument register; treat
778 it as a prologue instruction if so. */
779 if (is_argument_reg (gr_k))
780 last_prologue_pc = next_pc;
783 /* To save multiple callee-saves register on the stack, at a
787 P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000
788 0 000000 1111111 111111 000000000000 = 0x01fff000
791 P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000
792 0 000000 1111111 111111 000000000000 = 0x01fff000
794 We treat this as part of the prologue, and record the register's
795 saved address in the frame structure. */
796 else if ((op & 0x01fff000) == 0x014c1000
797 || (op & 0x01fff000) == 0x01501000)
799 int gr_k = ((op >> 25) & 0x3f);
803 /* Is it a stdi or a stqi? */
804 if ((op & 0x01fff000) == 0x014c1000)
809 /* Is it really a callee-saves register? */
810 if (is_callee_saves_reg (gr_k))
812 /* Sign-extend the twelve-bit field.
813 (Isn't there a better way to do this?) */
814 int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
816 for (i = 0; i < count; i++)
818 gr_saved[gr_k + i] = 1;
819 gr_sp_offset[gr_k + i] = s + (4 * i);
821 last_prologue_pc = next_pc;
825 /* Storing any kind of integer register at any constant offset
826 from any other register.
829 P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080
830 0 000000 1111111 000000 111111 111111 = 0x01fc0fff
833 P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000
834 0 000000 1111111 000000 000000000000 = 0x01fc0000
836 These could be almost anything, but a lot of prologue
837 instructions fall into this pattern, so let's decode the
838 instruction once, and then work at a higher level. */
839 else if (((op & 0x01fc0fff) == 0x000c0080)
840 || ((op & 0x01fc0000) == 0x01480000))
842 int gr_k = ((op >> 25) & 0x3f);
843 int gr_i = ((op >> 12) & 0x3f);
846 /* Are we storing with gr0 as an offset, or using an
848 if ((op & 0x01fc0fff) == 0x000c0080)
851 offset = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
853 /* If the address isn't relative to the SP or FP, it's not a
854 prologue instruction. */
855 if (gr_i != sp_regnum && gr_i != fp_regnum)
857 /* Do nothing; not a prologue instruction. */
860 /* Saving the old FP in the new frame (relative to the SP). */
861 else if (gr_k == fp_regnum && gr_i == sp_regnum)
863 gr_saved[fp_regnum] = 1;
864 gr_sp_offset[fp_regnum] = offset;
865 last_prologue_pc = next_pc;
868 /* Saving callee-saves register(s) on the stack, relative to
870 else if (gr_i == sp_regnum
871 && is_callee_saves_reg (gr_k))
874 if (gr_i == sp_regnum)
875 gr_sp_offset[gr_k] = offset;
877 gr_sp_offset[gr_k] = offset + fp_offset;
878 last_prologue_pc = next_pc;
881 /* Saving the scratch register holding the return address. */
882 else if (lr_save_reg != -1
883 && gr_k == lr_save_reg)
885 lr_saved_on_stack = 1;
886 if (gr_i == sp_regnum)
887 lr_sp_offset = offset;
889 lr_sp_offset = offset + fp_offset;
890 last_prologue_pc = next_pc;
893 /* Spilling int-sized arguments to the stack. */
894 else if (is_argument_reg (gr_k))
895 last_prologue_pc = next_pc;
900 if (next_frame && info)
905 /* If we know the relationship between the stack and frame
906 pointers, record the addresses of the registers we noticed.
907 Note that we have to do this as a separate step at the end,
908 because instructions may save relative to the SP, but we need
909 their addresses relative to the FP. */
911 frame_unwind_unsigned_register (next_frame, fp_regnum, &this_base);
913 frame_unwind_unsigned_register (next_frame, sp_regnum, &this_base);
915 for (i = 0; i < 64; i++)
917 info->saved_regs[i].addr = this_base - fp_offset + gr_sp_offset[i];
919 info->prev_sp = this_base - fp_offset + framesize;
920 info->base = this_base;
922 /* If LR was saved on the stack, record its location. */
923 if (lr_saved_on_stack)
924 info->saved_regs[lr_regnum].addr = this_base - fp_offset + lr_sp_offset;
926 /* The call instruction moves the caller's PC in the callee's LR.
927 Since this is an unwind, do the reverse. Copy the location of LR
928 into PC (the address / regnum) so that a request for PC will be
929 converted into a request for the LR. */
930 info->saved_regs[pc_regnum] = info->saved_regs[lr_regnum];
932 /* Save the previous frame's computed SP value. */
933 trad_frame_set_value (info->saved_regs, sp_regnum, info->prev_sp);
936 return last_prologue_pc;
941 frv_skip_prologue (CORE_ADDR pc)
943 CORE_ADDR func_addr, func_end, new_pc;
947 /* If the line table has entry for a line *within* the function
948 (i.e., not in the prologue, and not past the end), then that's
950 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
952 struct symtab_and_line sal;
954 sal = find_pc_line (func_addr, 0);
956 if (sal.line != 0 && sal.end < func_end)
962 /* The FR-V prologue is at least five instructions long (twenty bytes).
963 If we didn't find a real source location past that, then
964 do a full analysis of the prologue. */
965 if (new_pc < pc + 20)
966 new_pc = frv_analyze_prologue (pc, 0, 0);
972 static struct frv_unwind_cache *
973 frv_frame_unwind_cache (struct frame_info *next_frame,
974 void **this_prologue_cache)
976 struct gdbarch *gdbarch = get_frame_arch (next_frame);
980 struct frv_unwind_cache *info;
982 if ((*this_prologue_cache))
983 return (*this_prologue_cache);
985 info = FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache);
986 (*this_prologue_cache) = info;
987 info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
989 /* Prologue analysis does the rest... */
990 frv_analyze_prologue (frame_func_unwind (next_frame), next_frame, info);
996 frv_extract_return_value (struct type *type, struct regcache *regcache,
999 int len = TYPE_LENGTH (type);
1004 regcache_cooked_read_unsigned (regcache, 8, &gpr8_val);
1005 store_unsigned_integer (valbuf, len, gpr8_val);
1010 regcache_cooked_read_unsigned (regcache, 8, ®val);
1011 store_unsigned_integer (valbuf, 4, regval);
1012 regcache_cooked_read_unsigned (regcache, 9, ®val);
1013 store_unsigned_integer ((bfd_byte *) valbuf + 4, 4, regval);
1016 internal_error (__FILE__, __LINE__, "Illegal return value length: %d", len);
1020 frv_extract_struct_value_address (struct regcache *regcache)
1023 regcache_cooked_read_unsigned (regcache, struct_return_regnum, &addr);
1028 frv_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
1030 write_register (struct_return_regnum, addr);
1034 frv_frameless_function_invocation (struct frame_info *frame)
1036 return frameless_look_for_prologue (frame);
1040 frv_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1042 /* Require dword alignment. */
1043 return align_down (sp, 8);
1047 frv_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
1048 struct regcache *regcache, CORE_ADDR bp_addr,
1049 int nargs, struct value **args, CORE_ADDR sp,
1050 int struct_return, CORE_ADDR struct_addr)
1057 struct type *arg_type;
1059 enum type_code typecode;
1065 printf("Push %d args at sp = %x, struct_return=%d (%x)\n",
1066 nargs, (int) sp, struct_return, struct_addr);
1070 for (argnum = 0; argnum < nargs; ++argnum)
1071 stack_space += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), 4);
1073 stack_space -= (6 * 4);
1074 if (stack_space > 0)
1077 /* Make sure stack is dword aligned. */
1078 sp = align_down (sp, 8);
1085 regcache_cooked_write_unsigned (regcache, struct_return_regnum,
1088 for (argnum = 0; argnum < nargs; ++argnum)
1091 arg_type = check_typedef (VALUE_TYPE (arg));
1092 len = TYPE_LENGTH (arg_type);
1093 typecode = TYPE_CODE (arg_type);
1095 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
1097 store_unsigned_integer (valbuf, 4, VALUE_ADDRESS (arg));
1098 typecode = TYPE_CODE_PTR;
1104 val = (char *) VALUE_CONTENTS (arg);
1109 int partial_len = (len < 4 ? len : 4);
1113 regval = extract_unsigned_integer (val, partial_len);
1115 printf(" Argnum %d data %x -> reg %d\n",
1116 argnum, (int) regval, argreg);
1118 regcache_cooked_write_unsigned (regcache, argreg, regval);
1124 printf(" Argnum %d data %x -> offset %d (%x)\n",
1125 argnum, *((int *)val), stack_offset, (int) (sp + stack_offset));
1127 write_memory (sp + stack_offset, val, partial_len);
1128 stack_offset += align_up (partial_len, 4);
1135 /* Set the return address. For the frv, the return breakpoint is
1136 always at BP_ADDR. */
1137 regcache_cooked_write_unsigned (regcache, lr_regnum, bp_addr);
1139 /* Finally, update the SP register. */
1140 regcache_cooked_write_unsigned (regcache, sp_regnum, sp);
1146 frv_store_return_value (struct type *type, struct regcache *regcache,
1149 int len = TYPE_LENGTH (type);
1154 memset (val, 0, sizeof (val));
1155 memcpy (val + (4 - len), valbuf, len);
1156 regcache_cooked_write (regcache, 8, val);
1160 regcache_cooked_write (regcache, 8, valbuf);
1161 regcache_cooked_write (regcache, 9, (bfd_byte *) valbuf + 4);
1164 internal_error (__FILE__, __LINE__,
1165 "Don't know how to return a %d-byte value.", len);
1169 /* Hardware watchpoint / breakpoint support for the FR500
1173 frv_check_watch_resources (int type, int cnt, int ot)
1175 struct gdbarch_tdep *var = CURRENT_VARIANT;
1177 /* Watchpoints not supported on simulator. */
1178 if (strcmp (target_shortname, "sim") == 0)
1181 if (type == bp_hardware_breakpoint)
1183 if (var->num_hw_breakpoints == 0)
1185 else if (cnt <= var->num_hw_breakpoints)
1190 if (var->num_hw_watchpoints == 0)
1194 else if (cnt <= var->num_hw_watchpoints)
1202 frv_stopped_data_address (void)
1204 CORE_ADDR brr, dbar0, dbar1, dbar2, dbar3;
1206 brr = read_register (brr_regnum);
1207 dbar0 = read_register (dbar0_regnum);
1208 dbar1 = read_register (dbar1_regnum);
1209 dbar2 = read_register (dbar2_regnum);
1210 dbar3 = read_register (dbar3_regnum);
1214 else if (brr & (1<<10))
1216 else if (brr & (1<<9))
1218 else if (brr & (1<<8))
1225 frv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1227 return frame_unwind_register_unsigned (next_frame, pc_regnum);
1230 /* Given a GDB frame, determine the address of the calling function's
1231 frame. This will be used to create a new GDB frame struct. */
1234 frv_frame_this_id (struct frame_info *next_frame,
1235 void **this_prologue_cache, struct frame_id *this_id)
1237 struct frv_unwind_cache *info
1238 = frv_frame_unwind_cache (next_frame, this_prologue_cache);
1241 struct minimal_symbol *msym_stack;
1244 /* The FUNC is easy. */
1245 func = frame_func_unwind (next_frame);
1247 /* Check if the stack is empty. */
1248 msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL);
1249 if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack))
1252 /* Hopefully the prologue analysis either correctly determined the
1253 frame's base (which is the SP from the previous frame), or set
1254 that base to "NULL". */
1255 base = info->prev_sp;
1259 id = frame_id_build (base, func);
1261 /* Check that we're not going round in circles with the same frame
1262 ID (but avoid applying the test to sentinel frames which do go
1263 round in circles). Can't use frame_id_eq() as that doesn't yet
1264 compare the frame's PC value. */
1265 if (frame_relative_level (next_frame) >= 0
1266 && get_frame_type (next_frame) != DUMMY_FRAME
1267 && frame_id_eq (get_frame_id (next_frame), id))
1274 frv_frame_prev_register (struct frame_info *next_frame,
1275 void **this_prologue_cache,
1276 int regnum, int *optimizedp,
1277 enum lval_type *lvalp, CORE_ADDR *addrp,
1278 int *realnump, void *bufferp)
1280 struct frv_unwind_cache *info
1281 = frv_frame_unwind_cache (next_frame, this_prologue_cache);
1282 trad_frame_prev_register (next_frame, info->saved_regs, regnum,
1283 optimizedp, lvalp, addrp, realnump, bufferp);
1286 static const struct frame_unwind frv_frame_unwind = {
1289 frv_frame_prev_register
1292 static const struct frame_unwind *
1293 frv_frame_sniffer (struct frame_info *next_frame)
1295 return &frv_frame_unwind;
1299 frv_frame_base_address (struct frame_info *next_frame, void **this_cache)
1301 struct frv_unwind_cache *info
1302 = frv_frame_unwind_cache (next_frame, this_cache);
1306 static const struct frame_base frv_frame_base = {
1308 frv_frame_base_address,
1309 frv_frame_base_address,
1310 frv_frame_base_address
1314 frv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1316 return frame_unwind_register_unsigned (next_frame, sp_regnum);
1320 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1321 dummy frame. The frame ID's base needs to match the TOS value
1322 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1325 static struct frame_id
1326 frv_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1328 return frame_id_build (frv_unwind_sp (gdbarch, next_frame),
1329 frame_pc_unwind (next_frame));
1333 static struct gdbarch *
1334 frv_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1336 struct gdbarch *gdbarch;
1337 struct gdbarch_tdep *var;
1339 /* Check to see if we've already built an appropriate architecture
1340 object for this executable. */
1341 arches = gdbarch_list_lookup_by_info (arches, &info);
1343 return arches->gdbarch;
1345 /* Select the right tdep structure for this variant. */
1346 var = new_variant ();
1347 switch (info.bfd_arch_info->mach)
1350 case bfd_mach_frvsimple:
1351 case bfd_mach_fr500:
1352 case bfd_mach_frvtomcat:
1353 case bfd_mach_fr550:
1354 set_variant_num_gprs (var, 64);
1355 set_variant_num_fprs (var, 64);
1358 case bfd_mach_fr400:
1359 set_variant_num_gprs (var, 32);
1360 set_variant_num_fprs (var, 32);
1364 /* Never heard of this variant. */
1368 gdbarch = gdbarch_alloc (&info, var);
1370 set_gdbarch_short_bit (gdbarch, 16);
1371 set_gdbarch_int_bit (gdbarch, 32);
1372 set_gdbarch_long_bit (gdbarch, 32);
1373 set_gdbarch_long_long_bit (gdbarch, 64);
1374 set_gdbarch_float_bit (gdbarch, 32);
1375 set_gdbarch_double_bit (gdbarch, 64);
1376 set_gdbarch_long_double_bit (gdbarch, 64);
1377 set_gdbarch_ptr_bit (gdbarch, 32);
1379 set_gdbarch_num_regs (gdbarch, frv_num_regs);
1380 set_gdbarch_num_pseudo_regs (gdbarch, frv_num_pseudo_regs);
1382 set_gdbarch_sp_regnum (gdbarch, sp_regnum);
1383 set_gdbarch_deprecated_fp_regnum (gdbarch, fp_regnum);
1384 set_gdbarch_pc_regnum (gdbarch, pc_regnum);
1386 set_gdbarch_register_name (gdbarch, frv_register_name);
1387 set_gdbarch_register_type (gdbarch, frv_register_type);
1388 set_gdbarch_register_sim_regno (gdbarch, frv_register_sim_regno);
1390 set_gdbarch_pseudo_register_read (gdbarch, frv_pseudo_register_read);
1391 set_gdbarch_pseudo_register_write (gdbarch, frv_pseudo_register_write);
1393 set_gdbarch_skip_prologue (gdbarch, frv_skip_prologue);
1394 set_gdbarch_breakpoint_from_pc (gdbarch, frv_breakpoint_from_pc);
1395 set_gdbarch_adjust_breakpoint_address (gdbarch, frv_gdbarch_adjust_breakpoint_address);
1397 set_gdbarch_frame_args_skip (gdbarch, 0);
1398 set_gdbarch_frameless_function_invocation (gdbarch, frv_frameless_function_invocation);
1400 set_gdbarch_use_struct_convention (gdbarch, always_use_struct_convention);
1401 set_gdbarch_extract_return_value (gdbarch, frv_extract_return_value);
1403 set_gdbarch_deprecated_store_struct_return (gdbarch, frv_store_struct_return);
1404 set_gdbarch_store_return_value (gdbarch, frv_store_return_value);
1405 set_gdbarch_extract_struct_value_address (gdbarch, frv_extract_struct_value_address);
1408 set_gdbarch_unwind_pc (gdbarch, frv_unwind_pc);
1409 set_gdbarch_unwind_sp (gdbarch, frv_unwind_sp);
1410 set_gdbarch_frame_align (gdbarch, frv_frame_align);
1411 frame_unwind_append_sniffer (gdbarch, frv_frame_sniffer);
1412 frame_base_set_default (gdbarch, &frv_frame_base);
1414 /* Settings for calling functions in the inferior. */
1415 set_gdbarch_push_dummy_call (gdbarch, frv_push_dummy_call);
1416 set_gdbarch_unwind_dummy_id (gdbarch, frv_unwind_dummy_id);
1418 /* Settings that should be unnecessary. */
1419 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1421 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
1423 set_gdbarch_remote_translate_xfer_address
1424 (gdbarch, generic_remote_translate_xfer_address);
1426 /* Hardware watchpoint / breakpoint support. */
1427 switch (info.bfd_arch_info->mach)
1430 case bfd_mach_frvsimple:
1431 case bfd_mach_fr500:
1432 case bfd_mach_frvtomcat:
1433 /* fr500-style hardware debugging support. */
1434 var->num_hw_watchpoints = 4;
1435 var->num_hw_breakpoints = 4;
1438 case bfd_mach_fr400:
1439 /* fr400-style hardware debugging support. */
1440 var->num_hw_watchpoints = 2;
1441 var->num_hw_breakpoints = 4;
1445 /* Otherwise, assume we don't have hardware debugging support. */
1446 var->num_hw_watchpoints = 0;
1447 var->num_hw_breakpoints = 0;
1451 set_gdbarch_print_insn (gdbarch, print_insn_frv);
1457 _initialize_frv_tdep (void)
1459 register_gdbarch_init (bfd_arch_frv, frv_gdbarch_init);