1 /* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger.
3 Copyright (C) 2002-2005, 2007-2012 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "gdb_string.h"
24 #include "arch-utils.h"
27 #include "frame-unwind.h"
28 #include "frame-base.h"
29 #include "trad-frame.h"
31 #include "gdb_assert.h"
32 #include "sim-regno.h"
33 #include "gdb/sim-frv.h"
34 #include "opcodes/frv-desc.h" /* for the H_SPR_... enums */
43 extern void _initialize_frv_tdep (void);
45 struct frv_unwind_cache /* was struct frame_extra_info */
47 /* The previous frame's inner-most stack address. Used as this
48 frame ID's stack_addr. */
51 /* The frame's base, optionally used by the high-level debug info. */
54 /* Table indicating the location of each and every register. */
55 struct trad_frame_saved_reg *saved_regs;
58 /* A structure describing a particular variant of the FRV.
59 We allocate and initialize one of these structures when we create
60 the gdbarch object for a variant.
62 At the moment, all the FR variants we support differ only in which
63 registers are present; the portable code of GDB knows that
64 registers whose names are the empty string don't exist, so the
65 `register_names' array captures all the per-variant information we
68 in the future, if we need to have per-variant maps for raw size,
69 virtual type, etc., we should replace register_names with an array
70 of structures, each of which gives all the necessary info for one
71 register. Don't stick parallel arrays in here --- that's so
75 /* Which ABI is in use? */
78 /* How many general-purpose registers does this variant have? */
81 /* How many floating-point registers does this variant have? */
84 /* How many hardware watchpoints can it support? */
85 int num_hw_watchpoints;
87 /* How many hardware breakpoints can it support? */
88 int num_hw_breakpoints;
91 char **register_names;
94 /* Return the FR-V ABI associated with GDBARCH. */
96 frv_abi (struct gdbarch *gdbarch)
98 return gdbarch_tdep (gdbarch)->frv_abi;
101 /* Fetch the interpreter and executable loadmap addresses (for shared
102 library support) for the FDPIC ABI. Return 0 if successful, -1 if
103 not. (E.g, -1 will be returned if the ABI isn't the FDPIC ABI.) */
105 frv_fdpic_loadmap_addresses (struct gdbarch *gdbarch, CORE_ADDR *interp_addr,
106 CORE_ADDR *exec_addr)
108 if (frv_abi (gdbarch) != FRV_ABI_FDPIC)
112 struct regcache *regcache = get_current_regcache ();
114 if (interp_addr != NULL)
117 regcache_cooked_read_unsigned (regcache,
118 fdpic_loadmap_interp_regnum, &val);
121 if (exec_addr != NULL)
124 regcache_cooked_read_unsigned (regcache,
125 fdpic_loadmap_exec_regnum, &val);
132 /* Allocate a new variant structure, and set up default values for all
134 static struct gdbarch_tdep *
137 struct gdbarch_tdep *var;
141 var = xmalloc (sizeof (*var));
142 memset (var, 0, sizeof (*var));
144 var->frv_abi = FRV_ABI_EABI;
147 var->num_hw_watchpoints = 0;
148 var->num_hw_breakpoints = 0;
150 /* By default, don't supply any general-purpose or floating-point
153 = (char **) xmalloc ((frv_num_regs + frv_num_pseudo_regs)
155 for (r = 0; r < frv_num_regs + frv_num_pseudo_regs; r++)
156 var->register_names[r] = "";
158 /* Do, however, supply default names for the known special-purpose
161 var->register_names[pc_regnum] = "pc";
162 var->register_names[lr_regnum] = "lr";
163 var->register_names[lcr_regnum] = "lcr";
165 var->register_names[psr_regnum] = "psr";
166 var->register_names[ccr_regnum] = "ccr";
167 var->register_names[cccr_regnum] = "cccr";
168 var->register_names[tbr_regnum] = "tbr";
170 /* Debug registers. */
171 var->register_names[brr_regnum] = "brr";
172 var->register_names[dbar0_regnum] = "dbar0";
173 var->register_names[dbar1_regnum] = "dbar1";
174 var->register_names[dbar2_regnum] = "dbar2";
175 var->register_names[dbar3_regnum] = "dbar3";
177 /* iacc0 (Only found on MB93405.) */
178 var->register_names[iacc0h_regnum] = "iacc0h";
179 var->register_names[iacc0l_regnum] = "iacc0l";
180 var->register_names[iacc0_regnum] = "iacc0";
182 /* fsr0 (Found on FR555 and FR501.) */
183 var->register_names[fsr0_regnum] = "fsr0";
185 /* acc0 - acc7. The architecture provides for the possibility of many
186 more (up to 64 total), but we don't want to make that big of a hole
187 in the G packet. If we need more in the future, we'll add them
189 for (r = acc0_regnum; r <= acc7_regnum; r++)
192 buf = xstrprintf ("acc%d", r - acc0_regnum);
193 var->register_names[r] = buf;
196 /* accg0 - accg7: These are one byte registers. The remote protocol
197 provides the raw values packed four into a slot. accg0123 and
198 accg4567 correspond to accg0 - accg3 and accg4-accg7 respectively.
199 We don't provide names for accg0123 and accg4567 since the user will
200 likely not want to see these raw values. */
202 for (r = accg0_regnum; r <= accg7_regnum; r++)
205 buf = xstrprintf ("accg%d", r - accg0_regnum);
206 var->register_names[r] = buf;
211 var->register_names[msr0_regnum] = "msr0";
212 var->register_names[msr1_regnum] = "msr1";
214 /* gner and fner registers. */
215 var->register_names[gner0_regnum] = "gner0";
216 var->register_names[gner1_regnum] = "gner1";
217 var->register_names[fner0_regnum] = "fner0";
218 var->register_names[fner1_regnum] = "fner1";
224 /* Indicate that the variant VAR has NUM_GPRS general-purpose
225 registers, and fill in the names array appropriately. */
227 set_variant_num_gprs (struct gdbarch_tdep *var, int num_gprs)
231 var->num_gprs = num_gprs;
233 for (r = 0; r < num_gprs; ++r)
237 sprintf (buf, "gr%d", r);
238 var->register_names[first_gpr_regnum + r] = xstrdup (buf);
243 /* Indicate that the variant VAR has NUM_FPRS floating-point
244 registers, and fill in the names array appropriately. */
246 set_variant_num_fprs (struct gdbarch_tdep *var, int num_fprs)
250 var->num_fprs = num_fprs;
252 for (r = 0; r < num_fprs; ++r)
256 sprintf (buf, "fr%d", r);
257 var->register_names[first_fpr_regnum + r] = xstrdup (buf);
262 set_variant_abi_fdpic (struct gdbarch_tdep *var)
264 var->frv_abi = FRV_ABI_FDPIC;
265 var->register_names[fdpic_loadmap_exec_regnum] = xstrdup ("loadmap_exec");
266 var->register_names[fdpic_loadmap_interp_regnum]
267 = xstrdup ("loadmap_interp");
271 set_variant_scratch_registers (struct gdbarch_tdep *var)
273 var->register_names[scr0_regnum] = xstrdup ("scr0");
274 var->register_names[scr1_regnum] = xstrdup ("scr1");
275 var->register_names[scr2_regnum] = xstrdup ("scr2");
276 var->register_names[scr3_regnum] = xstrdup ("scr3");
280 frv_register_name (struct gdbarch *gdbarch, int reg)
284 if (reg >= frv_num_regs + frv_num_pseudo_regs)
287 return gdbarch_tdep (gdbarch)->register_names[reg];
292 frv_register_type (struct gdbarch *gdbarch, int reg)
294 if (reg >= first_fpr_regnum && reg <= last_fpr_regnum)
295 return builtin_type (gdbarch)->builtin_float;
296 else if (reg == iacc0_regnum)
297 return builtin_type (gdbarch)->builtin_int64;
299 return builtin_type (gdbarch)->builtin_int32;
302 static enum register_status
303 frv_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
304 int reg, gdb_byte *buffer)
306 enum register_status status;
308 if (reg == iacc0_regnum)
310 status = regcache_raw_read (regcache, iacc0h_regnum, buffer);
311 if (status == REG_VALID)
312 status = regcache_raw_read (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4);
314 else if (accg0_regnum <= reg && reg <= accg7_regnum)
316 /* The accg raw registers have four values in each slot with the
317 lowest register number occupying the first byte. */
319 int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4;
320 int byte_num = (reg - accg0_regnum) % 4;
323 status = regcache_raw_read (regcache, raw_regnum, buf);
324 if (status == REG_VALID)
326 memset (buffer, 0, 4);
327 /* FR-V is big endian, so put the requested byte in the
328 first byte of the buffer allocated to hold the
330 buffer[0] = buf[byte_num];
334 gdb_assert_not_reached ("invalid pseudo register number");
340 frv_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
341 int reg, const gdb_byte *buffer)
343 if (reg == iacc0_regnum)
345 regcache_raw_write (regcache, iacc0h_regnum, buffer);
346 regcache_raw_write (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4);
348 else if (accg0_regnum <= reg && reg <= accg7_regnum)
350 /* The accg raw registers have four values in each slot with the
351 lowest register number occupying the first byte. */
353 int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4;
354 int byte_num = (reg - accg0_regnum) % 4;
357 regcache_raw_read (regcache, raw_regnum, buf);
358 buf[byte_num] = ((bfd_byte *) buffer)[0];
359 regcache_raw_write (regcache, raw_regnum, buf);
364 frv_register_sim_regno (struct gdbarch *gdbarch, int reg)
366 static const int spr_map[] =
368 H_SPR_PSR, /* psr_regnum */
369 H_SPR_CCR, /* ccr_regnum */
370 H_SPR_CCCR, /* cccr_regnum */
371 -1, /* fdpic_loadmap_exec_regnum */
372 -1, /* fdpic_loadmap_interp_regnum */
374 H_SPR_TBR, /* tbr_regnum */
375 H_SPR_BRR, /* brr_regnum */
376 H_SPR_DBAR0, /* dbar0_regnum */
377 H_SPR_DBAR1, /* dbar1_regnum */
378 H_SPR_DBAR2, /* dbar2_regnum */
379 H_SPR_DBAR3, /* dbar3_regnum */
380 H_SPR_SCR0, /* scr0_regnum */
381 H_SPR_SCR1, /* scr1_regnum */
382 H_SPR_SCR2, /* scr2_regnum */
383 H_SPR_SCR3, /* scr3_regnum */
384 H_SPR_LR, /* lr_regnum */
385 H_SPR_LCR, /* lcr_regnum */
386 H_SPR_IACC0H, /* iacc0h_regnum */
387 H_SPR_IACC0L, /* iacc0l_regnum */
388 H_SPR_FSR0, /* fsr0_regnum */
389 /* FIXME: Add infrastructure for fetching/setting ACC and ACCG regs. */
390 -1, /* acc0_regnum */
391 -1, /* acc1_regnum */
392 -1, /* acc2_regnum */
393 -1, /* acc3_regnum */
394 -1, /* acc4_regnum */
395 -1, /* acc5_regnum */
396 -1, /* acc6_regnum */
397 -1, /* acc7_regnum */
398 -1, /* acc0123_regnum */
399 -1, /* acc4567_regnum */
400 H_SPR_MSR0, /* msr0_regnum */
401 H_SPR_MSR1, /* msr1_regnum */
402 H_SPR_GNER0, /* gner0_regnum */
403 H_SPR_GNER1, /* gner1_regnum */
404 H_SPR_FNER0, /* fner0_regnum */
405 H_SPR_FNER1, /* fner1_regnum */
408 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
410 if (first_gpr_regnum <= reg && reg <= last_gpr_regnum)
411 return reg - first_gpr_regnum + SIM_FRV_GR0_REGNUM;
412 else if (first_fpr_regnum <= reg && reg <= last_fpr_regnum)
413 return reg - first_fpr_regnum + SIM_FRV_FR0_REGNUM;
414 else if (pc_regnum == reg)
415 return SIM_FRV_PC_REGNUM;
416 else if (reg >= first_spr_regnum
417 && reg < first_spr_regnum + sizeof (spr_map) / sizeof (spr_map[0]))
419 int spr_reg_offset = spr_map[reg - first_spr_regnum];
421 if (spr_reg_offset < 0)
422 return SIM_REGNO_DOES_NOT_EXIST;
424 return SIM_FRV_SPR0_REGNUM + spr_reg_offset;
427 internal_error (__FILE__, __LINE__, _("Bad register number %d"), reg);
430 static const unsigned char *
431 frv_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenp)
433 static unsigned char breakpoint[] = {0xc0, 0x70, 0x00, 0x01};
434 *lenp = sizeof (breakpoint);
438 /* Define the maximum number of instructions which may be packed into a
439 bundle (VLIW instruction). */
440 static const int max_instrs_per_bundle = 8;
442 /* Define the size (in bytes) of an FR-V instruction. */
443 static const int frv_instr_size = 4;
445 /* Adjust a breakpoint's address to account for the FR-V architecture's
446 constraint that a break instruction must not appear as any but the
447 first instruction in the bundle. */
449 frv_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
451 int count = max_instrs_per_bundle;
452 CORE_ADDR addr = bpaddr - frv_instr_size;
453 CORE_ADDR func_start = get_pc_function_start (bpaddr);
455 /* Find the end of the previous packing sequence. This will be indicated
456 by either attempting to access some inaccessible memory or by finding
457 an instruction word whose packing bit is set to one. */
458 while (count-- > 0 && addr >= func_start)
460 char instr[frv_instr_size];
463 status = target_read_memory (addr, instr, sizeof instr);
468 /* This is a big endian architecture, so byte zero will have most
469 significant byte. The most significant bit of this byte is the
474 addr -= frv_instr_size;
478 bpaddr = addr + frv_instr_size;
484 /* Return true if REG is a caller-saves ("scratch") register,
487 is_caller_saves_reg (int reg)
489 return ((4 <= reg && reg <= 7)
490 || (14 <= reg && reg <= 15)
491 || (32 <= reg && reg <= 47));
495 /* Return true if REG is a callee-saves register, false otherwise. */
497 is_callee_saves_reg (int reg)
499 return ((16 <= reg && reg <= 31)
500 || (48 <= reg && reg <= 63));
504 /* Return true if REG is an argument register, false otherwise. */
506 is_argument_reg (int reg)
508 return (8 <= reg && reg <= 13);
511 /* Scan an FR-V prologue, starting at PC, until frame->PC.
512 If FRAME is non-zero, fill in its saved_regs with appropriate addresses.
513 We assume FRAME's saved_regs array has already been allocated and cleared.
514 Return the first PC value after the prologue.
516 Note that, for unoptimized code, we almost don't need this function
517 at all; all arguments and locals live on the stack, so we just need
518 the FP to find everything. The catch: structures passed by value
519 have their addresses living in registers; they're never spilled to
520 the stack. So if you ever want to be able to get to these
521 arguments in any frame but the top, you'll need to do this serious
522 prologue analysis. */
524 frv_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
525 struct frame_info *this_frame,
526 struct frv_unwind_cache *info)
528 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
530 /* When writing out instruction bitpatterns, we use the following
531 letters to label instruction fields:
532 P - The parallel bit. We don't use this.
533 J - The register number of GRj in the instruction description.
534 K - The register number of GRk in the instruction description.
535 I - The register number of GRi.
536 S - a signed imediate offset.
537 U - an unsigned immediate offset.
539 The dots below the numbers indicate where hex digit boundaries
540 fall, to make it easier to check the numbers. */
542 /* Non-zero iff we've seen the instruction that initializes the
543 frame pointer for this function's frame. */
546 /* If fp_set is non_zero, then this is the distance from
547 the stack pointer to frame pointer: fp = sp + fp_offset. */
550 /* Total size of frame prior to any alloca operations. */
553 /* Flag indicating if lr has been saved on the stack. */
554 int lr_saved_on_stack = 0;
556 /* The number of the general-purpose register we saved the return
557 address ("link register") in, or -1 if we haven't moved it yet. */
558 int lr_save_reg = -1;
560 /* Offset (from sp) at which lr has been saved on the stack. */
562 int lr_sp_offset = 0;
564 /* If gr_saved[i] is non-zero, then we've noticed that general
565 register i has been saved at gr_sp_offset[i] from the stack
568 int gr_sp_offset[64];
570 /* The address of the most recently scanned prologue instruction. */
571 CORE_ADDR last_prologue_pc;
573 /* The address of the next instruction. */
576 /* The upper bound to of the pc values to scan. */
579 memset (gr_saved, 0, sizeof (gr_saved));
581 last_prologue_pc = pc;
583 /* Try to compute an upper limit (on how far to scan) based on the
585 lim_pc = skip_prologue_using_sal (gdbarch, pc);
586 /* If there's no line number info, lim_pc will be 0. In that case,
587 set the limit to be 100 instructions away from pc. Hopefully, this
588 will be far enough away to account for the entire prologue. Don't
589 worry about overshooting the end of the function. The scan loop
590 below contains some checks to avoid scanning unreasonably far. */
594 /* If we have a frame, we don't want to scan past the frame's pc. This
595 will catch those cases where the pc is in the prologue. */
598 CORE_ADDR frame_pc = get_frame_pc (this_frame);
599 if (frame_pc < lim_pc)
603 /* Scan the prologue. */
606 char buf[frv_instr_size];
609 if (target_read_memory (pc, buf, sizeof buf) != 0)
611 op = extract_signed_integer (buf, sizeof buf, byte_order);
615 /* The tests in this chain of ifs should be in order of
616 decreasing selectivity, so that more particular patterns get
617 to fire before less particular patterns. */
619 /* Some sort of control transfer instruction: stop scanning prologue.
620 Integer Conditional Branch:
621 X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX
622 Floating-point / media Conditional Branch:
623 X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX
624 LCR Conditional Branch to LR
625 X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX
626 Integer conditional Branches to LR
627 X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX
628 X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX
629 Floating-point/Media Branches to LR
630 X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX
631 X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX
633 X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX
634 X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX
636 X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX
638 X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX
639 Integer Conditional Trap
640 X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX
641 X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX
642 Floating-point /media Conditional Trap
643 X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX
644 X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX
646 X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX
648 X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */
649 if ((op & 0x01d80000) == 0x00180000 /* Conditional branches and Call */
650 || (op & 0x01f80000) == 0x00300000 /* Jump and Link */
651 || (op & 0x01f80000) == 0x00100000 /* Return from Trap, Trap */
652 || (op & 0x01f80000) == 0x00700000) /* Trap immediate */
654 /* Stop scanning; not in prologue any longer. */
658 /* Loading something from memory into fp probably means that
659 we're in the epilogue. Stop scanning the prologue.
661 X 000010 0000010 XXXXXX 000100 XXXXXX
663 X 000010 0110010 XXXXXX XXXXXXXXXXXX */
664 else if ((op & 0x7ffc0fc0) == 0x04080100
665 || (op & 0x7ffc0000) == 0x04c80000)
670 /* Setting the FP from the SP:
672 P 000010 0100010 000001 000000000000 = 0x04881000
673 0 111111 1111111 111111 111111111111 = 0x7fffffff
675 We treat this as part of the prologue. */
676 else if ((op & 0x7fffffff) == 0x04881000)
680 last_prologue_pc = next_pc;
683 /* Move the link register to the scratch register grJ, before saving:
685 P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0
686 0 111111 1111111 111111 111111 000000 = 0x7fffffc0
688 We treat this as part of the prologue. */
689 else if ((op & 0x7fffffc0) == 0x080d01c0)
691 int gr_j = op & 0x3f;
693 /* If we're moving it to a scratch register, that's fine. */
694 if (is_caller_saves_reg (gr_j))
697 last_prologue_pc = next_pc;
701 /* To save multiple callee-saves registers on the stack, at
705 P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0
706 0 000000 1111111 111111 111111 111111 = 0x01ffffff
709 P KKKKKK 0000011 000001 000100 000000 = 0x000c1100
710 0 000000 1111111 111111 111111 111111 = 0x01ffffff
712 We treat this as part of the prologue, and record the register's
713 saved address in the frame structure. */
714 else if ((op & 0x01ffffff) == 0x000c10c0
715 || (op & 0x01ffffff) == 0x000c1100)
717 int gr_k = ((op >> 25) & 0x3f);
718 int ope = ((op >> 6) & 0x3f);
722 /* Is it an std or an stq? */
728 /* Is it really a callee-saves register? */
729 if (is_callee_saves_reg (gr_k))
731 for (i = 0; i < count; i++)
733 gr_saved[gr_k + i] = 1;
734 gr_sp_offset[gr_k + i] = 4 * i;
736 last_prologue_pc = next_pc;
740 /* Adjusting the stack pointer. (The stack pointer is GR1.)
742 P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000
743 0 111111 1111111 111111 000000000000 = 0x7ffff000
745 We treat this as part of the prologue. */
746 else if ((op & 0x7ffff000) == 0x02401000)
750 /* Sign-extend the twelve-bit field.
751 (Isn't there a better way to do this?) */
752 int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
755 last_prologue_pc = pc;
759 /* If the prologue is being adjusted again, we've
760 likely gone too far; i.e. we're probably in the
766 /* Setting the FP to a constant distance from the SP:
768 P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000
769 0 111111 1111111 111111 000000000000 = 0x7ffff000
771 We treat this as part of the prologue. */
772 else if ((op & 0x7ffff000) == 0x04401000)
774 /* Sign-extend the twelve-bit field.
775 (Isn't there a better way to do this?) */
776 int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
779 last_prologue_pc = pc;
782 /* To spill an argument register to a scratch register:
784 P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000
785 0 000000 1111111 000000 111111111111 = 0x01fc0fff
787 For the time being, we treat this as a prologue instruction,
788 assuming that GRi is an argument register. This one's kind
789 of suspicious, because it seems like it could be part of a
790 legitimate body instruction. But we only come here when the
791 source info wasn't helpful, so we have to do the best we can.
792 Hopefully once GCC and GDB agree on how to emit line number
793 info for prologues, then this code will never come into play. */
794 else if ((op & 0x01fc0fff) == 0x00880000)
796 int gr_i = ((op >> 12) & 0x3f);
798 /* Make sure that the source is an arg register; if it is, we'll
799 treat it as a prologue instruction. */
800 if (is_argument_reg (gr_i))
801 last_prologue_pc = next_pc;
804 /* To spill 16-bit values to the stack:
806 P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000
807 0 000000 1111111 111111 000000000000 = 0x01fff000
809 And for 8-bit values, we use STB instructions.
811 P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000
812 0 000000 1111111 111111 000000000000 = 0x01fff000
814 We check that GRk is really an argument register, and treat
815 all such as part of the prologue. */
816 else if ( (op & 0x01fff000) == 0x01442000
817 || (op & 0x01fff000) == 0x01402000)
819 int gr_k = ((op >> 25) & 0x3f);
821 /* Make sure that GRk is really an argument register; treat
822 it as a prologue instruction if so. */
823 if (is_argument_reg (gr_k))
824 last_prologue_pc = next_pc;
827 /* To save multiple callee-saves register on the stack, at a
831 P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000
832 0 000000 1111111 111111 000000000000 = 0x01fff000
835 P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000
836 0 000000 1111111 111111 000000000000 = 0x01fff000
838 We treat this as part of the prologue, and record the register's
839 saved address in the frame structure. */
840 else if ((op & 0x01fff000) == 0x014c1000
841 || (op & 0x01fff000) == 0x01501000)
843 int gr_k = ((op >> 25) & 0x3f);
847 /* Is it a stdi or a stqi? */
848 if ((op & 0x01fff000) == 0x014c1000)
853 /* Is it really a callee-saves register? */
854 if (is_callee_saves_reg (gr_k))
856 /* Sign-extend the twelve-bit field.
857 (Isn't there a better way to do this?) */
858 int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
860 for (i = 0; i < count; i++)
862 gr_saved[gr_k + i] = 1;
863 gr_sp_offset[gr_k + i] = s + (4 * i);
865 last_prologue_pc = next_pc;
869 /* Storing any kind of integer register at any constant offset
870 from any other register.
873 P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080
874 0 000000 1111111 000000 111111 111111 = 0x01fc0fff
877 P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000
878 0 000000 1111111 000000 000000000000 = 0x01fc0000
880 These could be almost anything, but a lot of prologue
881 instructions fall into this pattern, so let's decode the
882 instruction once, and then work at a higher level. */
883 else if (((op & 0x01fc0fff) == 0x000c0080)
884 || ((op & 0x01fc0000) == 0x01480000))
886 int gr_k = ((op >> 25) & 0x3f);
887 int gr_i = ((op >> 12) & 0x3f);
890 /* Are we storing with gr0 as an offset, or using an
892 if ((op & 0x01fc0fff) == 0x000c0080)
895 offset = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
897 /* If the address isn't relative to the SP or FP, it's not a
898 prologue instruction. */
899 if (gr_i != sp_regnum && gr_i != fp_regnum)
901 /* Do nothing; not a prologue instruction. */
904 /* Saving the old FP in the new frame (relative to the SP). */
905 else if (gr_k == fp_regnum && gr_i == sp_regnum)
907 gr_saved[fp_regnum] = 1;
908 gr_sp_offset[fp_regnum] = offset;
909 last_prologue_pc = next_pc;
912 /* Saving callee-saves register(s) on the stack, relative to
914 else if (gr_i == sp_regnum
915 && is_callee_saves_reg (gr_k))
918 if (gr_i == sp_regnum)
919 gr_sp_offset[gr_k] = offset;
921 gr_sp_offset[gr_k] = offset + fp_offset;
922 last_prologue_pc = next_pc;
925 /* Saving the scratch register holding the return address. */
926 else if (lr_save_reg != -1
927 && gr_k == lr_save_reg)
929 lr_saved_on_stack = 1;
930 if (gr_i == sp_regnum)
931 lr_sp_offset = offset;
933 lr_sp_offset = offset + fp_offset;
934 last_prologue_pc = next_pc;
937 /* Spilling int-sized arguments to the stack. */
938 else if (is_argument_reg (gr_k))
939 last_prologue_pc = next_pc;
944 if (this_frame && info)
949 /* If we know the relationship between the stack and frame
950 pointers, record the addresses of the registers we noticed.
951 Note that we have to do this as a separate step at the end,
952 because instructions may save relative to the SP, but we need
953 their addresses relative to the FP. */
955 this_base = get_frame_register_unsigned (this_frame, fp_regnum);
957 this_base = get_frame_register_unsigned (this_frame, sp_regnum);
959 for (i = 0; i < 64; i++)
961 info->saved_regs[i].addr = this_base - fp_offset + gr_sp_offset[i];
963 info->prev_sp = this_base - fp_offset + framesize;
964 info->base = this_base;
966 /* If LR was saved on the stack, record its location. */
967 if (lr_saved_on_stack)
968 info->saved_regs[lr_regnum].addr
969 = this_base - fp_offset + lr_sp_offset;
971 /* The call instruction moves the caller's PC in the callee's LR.
972 Since this is an unwind, do the reverse. Copy the location of LR
973 into PC (the address / regnum) so that a request for PC will be
974 converted into a request for the LR. */
975 info->saved_regs[pc_regnum] = info->saved_regs[lr_regnum];
977 /* Save the previous frame's computed SP value. */
978 trad_frame_set_value (info->saved_regs, sp_regnum, info->prev_sp);
981 return last_prologue_pc;
986 frv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
988 CORE_ADDR func_addr, func_end, new_pc;
992 /* If the line table has entry for a line *within* the function
993 (i.e., not in the prologue, and not past the end), then that's
995 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
997 struct symtab_and_line sal;
999 sal = find_pc_line (func_addr, 0);
1001 if (sal.line != 0 && sal.end < func_end)
1007 /* The FR-V prologue is at least five instructions long (twenty bytes).
1008 If we didn't find a real source location past that, then
1009 do a full analysis of the prologue. */
1010 if (new_pc < pc + 20)
1011 new_pc = frv_analyze_prologue (gdbarch, pc, 0, 0);
1017 /* Examine the instruction pointed to by PC. If it corresponds to
1018 a call to __main, return the address of the next instruction.
1019 Otherwise, return PC. */
1022 frv_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1024 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1027 CORE_ADDR orig_pc = pc;
1029 if (target_read_memory (pc, buf, 4))
1031 op = extract_unsigned_integer (buf, 4, byte_order);
1033 /* In PIC code, GR15 may be loaded from some offset off of FP prior
1034 to the call instruction.
1036 Skip over this instruction if present. It won't be present in
1037 non-PIC code, and even in PIC code, it might not be present.
1038 (This is due to the fact that GR15, the FDPIC register, already
1039 contains the correct value.)
1041 The general form of the LDI is given first, followed by the
1042 specific instruction with the GRi and GRk filled in as FP and
1045 ldi @(GRi, d12), GRk
1046 P KKKKKK 0110010 IIIIII SSSSSSSSSSSS = 0x00c80000
1047 0 000000 1111111 000000 000000000000 = 0x01fc0000
1049 ldi @(FP, d12), GR15
1050 P KKKKKK 0110010 IIIIII SSSSSSSSSSSS = 0x1ec82000
1051 0 001111 1111111 000010 000000000000 = 0x7ffff000
1054 if ((op & 0x7ffff000) == 0x1ec82000)
1057 if (target_read_memory (pc, buf, 4))
1059 op = extract_unsigned_integer (buf, 4, byte_order);
1062 /* The format of an FRV CALL instruction is as follows:
1065 P HHHHHH 0001111 LLLLLLLLLLLLLLLLLL = 0x003c0000
1066 0 000000 1111111 000000000000000000 = 0x01fc0000
1069 where label24 is constructed by concatenating the H bits with the
1070 L bits. The call target is PC + (4 * sign_ext(label24)). */
1072 if ((op & 0x01fc0000) == 0x003c0000)
1075 CORE_ADDR call_dest;
1076 struct minimal_symbol *s;
1078 displ = ((op & 0xfe000000) >> 7) | (op & 0x0003ffff);
1079 if ((displ & 0x00800000) != 0)
1080 displ |= ~((LONGEST) 0x00ffffff);
1082 call_dest = pc + 4 * displ;
1083 s = lookup_minimal_symbol_by_pc (call_dest);
1086 && SYMBOL_LINKAGE_NAME (s) != NULL
1087 && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0)
1097 static struct frv_unwind_cache *
1098 frv_frame_unwind_cache (struct frame_info *this_frame,
1099 void **this_prologue_cache)
1101 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1104 struct frv_unwind_cache *info;
1106 if ((*this_prologue_cache))
1107 return (*this_prologue_cache);
1109 info = FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache);
1110 (*this_prologue_cache) = info;
1111 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1113 /* Prologue analysis does the rest... */
1114 frv_analyze_prologue (gdbarch,
1115 get_frame_func (this_frame), this_frame, info);
1121 frv_extract_return_value (struct type *type, struct regcache *regcache,
1124 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1125 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1126 int len = TYPE_LENGTH (type);
1131 regcache_cooked_read_unsigned (regcache, 8, &gpr8_val);
1132 store_unsigned_integer (valbuf, len, byte_order, gpr8_val);
1138 regcache_cooked_read_unsigned (regcache, 8, ®val);
1139 store_unsigned_integer (valbuf, 4, byte_order, regval);
1140 regcache_cooked_read_unsigned (regcache, 9, ®val);
1141 store_unsigned_integer ((bfd_byte *) valbuf + 4, 4, byte_order, regval);
1144 internal_error (__FILE__, __LINE__,
1145 _("Illegal return value length: %d"), len);
1149 frv_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1151 /* Require dword alignment. */
1152 return align_down (sp, 8);
1156 find_func_descr (struct gdbarch *gdbarch, CORE_ADDR entry_point)
1158 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1161 CORE_ADDR start_addr;
1163 /* If we can't find the function in the symbol table, then we assume
1164 that the function address is already in descriptor form. */
1165 if (!find_pc_partial_function (entry_point, NULL, &start_addr, NULL)
1166 || entry_point != start_addr)
1169 descr = frv_fdpic_find_canonical_descriptor (entry_point);
1174 /* Construct a non-canonical descriptor from space allocated on
1177 descr = value_as_long (value_allocate_space_in_inferior (8));
1178 store_unsigned_integer (valbuf, 4, byte_order, entry_point);
1179 write_memory (descr, valbuf, 4);
1180 store_unsigned_integer (valbuf, 4, byte_order,
1181 frv_fdpic_find_global_pointer (entry_point));
1182 write_memory (descr + 4, valbuf, 4);
1187 frv_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr,
1188 struct target_ops *targ)
1190 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1191 CORE_ADDR entry_point;
1192 CORE_ADDR got_address;
1194 entry_point = get_target_memory_unsigned (targ, addr, 4, byte_order);
1195 got_address = get_target_memory_unsigned (targ, addr + 4, 4, byte_order);
1197 if (got_address == frv_fdpic_find_global_pointer (entry_point))
1204 frv_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1205 struct regcache *regcache, CORE_ADDR bp_addr,
1206 int nargs, struct value **args, CORE_ADDR sp,
1207 int struct_return, CORE_ADDR struct_addr)
1209 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1215 struct type *arg_type;
1217 enum type_code typecode;
1221 enum frv_abi abi = frv_abi (gdbarch);
1222 CORE_ADDR func_addr = find_function_addr (function, NULL);
1225 printf("Push %d args at sp = %x, struct_return=%d (%x)\n",
1226 nargs, (int) sp, struct_return, struct_addr);
1230 for (argnum = 0; argnum < nargs; ++argnum)
1231 stack_space += align_up (TYPE_LENGTH (value_type (args[argnum])), 4);
1233 stack_space -= (6 * 4);
1234 if (stack_space > 0)
1237 /* Make sure stack is dword aligned. */
1238 sp = align_down (sp, 8);
1245 regcache_cooked_write_unsigned (regcache, struct_return_regnum,
1248 for (argnum = 0; argnum < nargs; ++argnum)
1251 arg_type = check_typedef (value_type (arg));
1252 len = TYPE_LENGTH (arg_type);
1253 typecode = TYPE_CODE (arg_type);
1255 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
1257 store_unsigned_integer (valbuf, 4, byte_order,
1258 value_address (arg));
1259 typecode = TYPE_CODE_PTR;
1263 else if (abi == FRV_ABI_FDPIC
1265 && typecode == TYPE_CODE_PTR
1266 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC)
1268 /* The FDPIC ABI requires function descriptors to be passed instead
1270 CORE_ADDR addr = extract_unsigned_integer
1271 (value_contents (arg), 4, byte_order);
1272 addr = find_func_descr (gdbarch, addr);
1273 store_unsigned_integer (valbuf, 4, byte_order, addr);
1274 typecode = TYPE_CODE_PTR;
1280 val = (char *) value_contents (arg);
1285 int partial_len = (len < 4 ? len : 4);
1289 regval = extract_unsigned_integer (val, partial_len, byte_order);
1291 printf(" Argnum %d data %x -> reg %d\n",
1292 argnum, (int) regval, argreg);
1294 regcache_cooked_write_unsigned (regcache, argreg, regval);
1300 printf(" Argnum %d data %x -> offset %d (%x)\n",
1301 argnum, *((int *)val), stack_offset,
1302 (int) (sp + stack_offset));
1304 write_memory (sp + stack_offset, val, partial_len);
1305 stack_offset += align_up (partial_len, 4);
1312 /* Set the return address. For the frv, the return breakpoint is
1313 always at BP_ADDR. */
1314 regcache_cooked_write_unsigned (regcache, lr_regnum, bp_addr);
1316 if (abi == FRV_ABI_FDPIC)
1318 /* Set the GOT register for the FDPIC ABI. */
1319 regcache_cooked_write_unsigned
1320 (regcache, first_gpr_regnum + 15,
1321 frv_fdpic_find_global_pointer (func_addr));
1324 /* Finally, update the SP register. */
1325 regcache_cooked_write_unsigned (regcache, sp_regnum, sp);
1331 frv_store_return_value (struct type *type, struct regcache *regcache,
1332 const gdb_byte *valbuf)
1334 int len = TYPE_LENGTH (type);
1339 memset (val, 0, sizeof (val));
1340 memcpy (val + (4 - len), valbuf, len);
1341 regcache_cooked_write (regcache, 8, val);
1345 regcache_cooked_write (regcache, 8, valbuf);
1346 regcache_cooked_write (regcache, 9, (bfd_byte *) valbuf + 4);
1349 internal_error (__FILE__, __LINE__,
1350 _("Don't know how to return a %d-byte value."), len);
1353 static enum return_value_convention
1354 frv_return_value (struct gdbarch *gdbarch, struct type *func_type,
1355 struct type *valtype, struct regcache *regcache,
1356 gdb_byte *readbuf, const gdb_byte *writebuf)
1358 int struct_return = TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1359 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1360 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY;
1362 if (writebuf != NULL)
1364 gdb_assert (!struct_return);
1365 frv_store_return_value (valtype, regcache, writebuf);
1368 if (readbuf != NULL)
1370 gdb_assert (!struct_return);
1371 frv_extract_return_value (valtype, regcache, readbuf);
1375 return RETURN_VALUE_STRUCT_CONVENTION;
1377 return RETURN_VALUE_REGISTER_CONVENTION;
1381 /* Hardware watchpoint / breakpoint support for the FR500
1385 frv_check_watch_resources (struct gdbarch *gdbarch, int type, int cnt, int ot)
1387 struct gdbarch_tdep *var = gdbarch_tdep (gdbarch);
1389 /* Watchpoints not supported on simulator. */
1390 if (strcmp (target_shortname, "sim") == 0)
1393 if (type == bp_hardware_breakpoint)
1395 if (var->num_hw_breakpoints == 0)
1397 else if (cnt <= var->num_hw_breakpoints)
1402 if (var->num_hw_watchpoints == 0)
1406 else if (cnt <= var->num_hw_watchpoints)
1414 frv_stopped_data_address (CORE_ADDR *addr_p)
1416 struct frame_info *frame = get_current_frame ();
1417 CORE_ADDR brr, dbar0, dbar1, dbar2, dbar3;
1419 brr = get_frame_register_unsigned (frame, brr_regnum);
1420 dbar0 = get_frame_register_unsigned (frame, dbar0_regnum);
1421 dbar1 = get_frame_register_unsigned (frame, dbar1_regnum);
1422 dbar2 = get_frame_register_unsigned (frame, dbar2_regnum);
1423 dbar3 = get_frame_register_unsigned (frame, dbar3_regnum);
1427 else if (brr & (1<<10))
1429 else if (brr & (1<<9))
1431 else if (brr & (1<<8))
1440 frv_have_stopped_data_address (void)
1443 return frv_stopped_data_address (&addr);
1447 frv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1449 return frame_unwind_register_unsigned (next_frame, pc_regnum);
1452 /* Given a GDB frame, determine the address of the calling function's
1453 frame. This will be used to create a new GDB frame struct. */
1456 frv_frame_this_id (struct frame_info *this_frame,
1457 void **this_prologue_cache, struct frame_id *this_id)
1459 struct frv_unwind_cache *info
1460 = frv_frame_unwind_cache (this_frame, this_prologue_cache);
1463 struct minimal_symbol *msym_stack;
1466 /* The FUNC is easy. */
1467 func = get_frame_func (this_frame);
1469 /* Check if the stack is empty. */
1470 msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL);
1471 if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack))
1474 /* Hopefully the prologue analysis either correctly determined the
1475 frame's base (which is the SP from the previous frame), or set
1476 that base to "NULL". */
1477 base = info->prev_sp;
1481 id = frame_id_build (base, func);
1485 static struct value *
1486 frv_frame_prev_register (struct frame_info *this_frame,
1487 void **this_prologue_cache, int regnum)
1489 struct frv_unwind_cache *info
1490 = frv_frame_unwind_cache (this_frame, this_prologue_cache);
1491 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
1494 static const struct frame_unwind frv_frame_unwind = {
1496 default_frame_unwind_stop_reason,
1498 frv_frame_prev_register,
1500 default_frame_sniffer
1504 frv_frame_base_address (struct frame_info *this_frame, void **this_cache)
1506 struct frv_unwind_cache *info
1507 = frv_frame_unwind_cache (this_frame, this_cache);
1511 static const struct frame_base frv_frame_base = {
1513 frv_frame_base_address,
1514 frv_frame_base_address,
1515 frv_frame_base_address
1519 frv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1521 return frame_unwind_register_unsigned (next_frame, sp_regnum);
1525 /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
1526 frame. The frame ID's base needs to match the TOS value saved by
1527 save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */
1529 static struct frame_id
1530 frv_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1532 CORE_ADDR sp = get_frame_register_unsigned (this_frame, sp_regnum);
1533 return frame_id_build (sp, get_frame_pc (this_frame));
1536 static struct gdbarch *
1537 frv_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1539 struct gdbarch *gdbarch;
1540 struct gdbarch_tdep *var;
1543 /* Check to see if we've already built an appropriate architecture
1544 object for this executable. */
1545 arches = gdbarch_list_lookup_by_info (arches, &info);
1547 return arches->gdbarch;
1549 /* Select the right tdep structure for this variant. */
1550 var = new_variant ();
1551 switch (info.bfd_arch_info->mach)
1554 case bfd_mach_frvsimple:
1555 case bfd_mach_fr500:
1556 case bfd_mach_frvtomcat:
1557 case bfd_mach_fr550:
1558 set_variant_num_gprs (var, 64);
1559 set_variant_num_fprs (var, 64);
1562 case bfd_mach_fr400:
1563 case bfd_mach_fr450:
1564 set_variant_num_gprs (var, 32);
1565 set_variant_num_fprs (var, 32);
1569 /* Never heard of this variant. */
1573 /* Extract the ELF flags, if available. */
1574 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
1575 elf_flags = elf_elfheader (info.abfd)->e_flags;
1577 if (elf_flags & EF_FRV_FDPIC)
1578 set_variant_abi_fdpic (var);
1580 if (elf_flags & EF_FRV_CPU_FR450)
1581 set_variant_scratch_registers (var);
1583 gdbarch = gdbarch_alloc (&info, var);
1585 set_gdbarch_short_bit (gdbarch, 16);
1586 set_gdbarch_int_bit (gdbarch, 32);
1587 set_gdbarch_long_bit (gdbarch, 32);
1588 set_gdbarch_long_long_bit (gdbarch, 64);
1589 set_gdbarch_float_bit (gdbarch, 32);
1590 set_gdbarch_double_bit (gdbarch, 64);
1591 set_gdbarch_long_double_bit (gdbarch, 64);
1592 set_gdbarch_ptr_bit (gdbarch, 32);
1594 set_gdbarch_num_regs (gdbarch, frv_num_regs);
1595 set_gdbarch_num_pseudo_regs (gdbarch, frv_num_pseudo_regs);
1597 set_gdbarch_sp_regnum (gdbarch, sp_regnum);
1598 set_gdbarch_deprecated_fp_regnum (gdbarch, fp_regnum);
1599 set_gdbarch_pc_regnum (gdbarch, pc_regnum);
1601 set_gdbarch_register_name (gdbarch, frv_register_name);
1602 set_gdbarch_register_type (gdbarch, frv_register_type);
1603 set_gdbarch_register_sim_regno (gdbarch, frv_register_sim_regno);
1605 set_gdbarch_pseudo_register_read (gdbarch, frv_pseudo_register_read);
1606 set_gdbarch_pseudo_register_write (gdbarch, frv_pseudo_register_write);
1608 set_gdbarch_skip_prologue (gdbarch, frv_skip_prologue);
1609 set_gdbarch_skip_main_prologue (gdbarch, frv_skip_main_prologue);
1610 set_gdbarch_breakpoint_from_pc (gdbarch, frv_breakpoint_from_pc);
1611 set_gdbarch_adjust_breakpoint_address
1612 (gdbarch, frv_adjust_breakpoint_address);
1614 set_gdbarch_return_value (gdbarch, frv_return_value);
1617 set_gdbarch_unwind_pc (gdbarch, frv_unwind_pc);
1618 set_gdbarch_unwind_sp (gdbarch, frv_unwind_sp);
1619 set_gdbarch_frame_align (gdbarch, frv_frame_align);
1620 frame_base_set_default (gdbarch, &frv_frame_base);
1621 /* We set the sniffer lower down after the OSABI hooks have been
1624 /* Settings for calling functions in the inferior. */
1625 set_gdbarch_push_dummy_call (gdbarch, frv_push_dummy_call);
1626 set_gdbarch_dummy_id (gdbarch, frv_dummy_id);
1628 /* Settings that should be unnecessary. */
1629 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1631 /* Hardware watchpoint / breakpoint support. */
1632 switch (info.bfd_arch_info->mach)
1635 case bfd_mach_frvsimple:
1636 case bfd_mach_fr500:
1637 case bfd_mach_frvtomcat:
1638 /* fr500-style hardware debugging support. */
1639 var->num_hw_watchpoints = 4;
1640 var->num_hw_breakpoints = 4;
1643 case bfd_mach_fr400:
1644 case bfd_mach_fr450:
1645 /* fr400-style hardware debugging support. */
1646 var->num_hw_watchpoints = 2;
1647 var->num_hw_breakpoints = 4;
1651 /* Otherwise, assume we don't have hardware debugging support. */
1652 var->num_hw_watchpoints = 0;
1653 var->num_hw_breakpoints = 0;
1657 set_gdbarch_print_insn (gdbarch, print_insn_frv);
1658 if (frv_abi (gdbarch) == FRV_ABI_FDPIC)
1659 set_gdbarch_convert_from_func_ptr_addr (gdbarch,
1660 frv_convert_from_func_ptr_addr);
1662 set_solib_ops (gdbarch, &frv_so_ops);
1664 /* Hook in ABI-specific overrides, if they have been registered. */
1665 gdbarch_init_osabi (info, gdbarch);
1667 /* Set the fallback (prologue based) frame sniffer. */
1668 frame_unwind_append_unwinder (gdbarch, &frv_frame_unwind);
1670 /* Enable TLS support. */
1671 set_gdbarch_fetch_tls_load_module_address (gdbarch,
1672 frv_fetch_objfile_link_map);
1678 _initialize_frv_tdep (void)
1680 register_gdbarch_init (bfd_arch_frv, frv_gdbarch_init);