1 /* Target-dependent code for Mitsubishi D10V, for GDB.
3 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* Contributed by Martin Hunt, hunt@cygnus.com */
27 #include "frame-unwind.h"
28 #include "frame-base.h"
33 #include "gdb_string.h"
40 #include "arch-utils.h"
43 #include "floatformat.h"
44 #include "gdb/sim-d10v.h"
45 #include "sim-regno.h"
47 #include "gdb_assert.h"
53 unsigned long (*dmap_register) (int nr);
54 unsigned long (*imap_register) (int nr);
57 /* These are the addresses the D10V-EVA board maps data and
58 instruction memory to. */
61 DMEM_START = 0x2000000,
62 IMEM_START = 0x1000000,
63 STACK_START = 0x200bffe
66 /* d10v register names. */
81 /* d10v calling convention. */
82 ARG1_REGNUM = R0_REGNUM,
83 ARGN_REGNUM = R3_REGNUM,
84 RET1_REGNUM = R0_REGNUM,
87 #define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs)
88 #define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum)
92 extern void _initialize_d10v_tdep (void);
94 static CORE_ADDR d10v_read_sp (void);
96 static CORE_ADDR d10v_read_fp (void);
98 static void d10v_eva_prepare_to_trace (void);
100 static void d10v_eva_get_trace_data (void);
103 d10v_stack_align (CORE_ADDR len)
105 return (len + 1) & ~1;
108 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
109 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
110 and TYPE is the type (which is known to be struct, union or array).
112 The d10v returns anything less than 8 bytes in size in
116 d10v_use_struct_convention (int gcc_p, struct type *type)
120 /* The d10v only passes a struct in a register when that structure
121 has an alignment that matches the size of a register. */
122 /* If the structure doesn't fit in 4 registers, put it on the
124 if (TYPE_LENGTH (type) > 8)
126 /* If the struct contains only one field, don't put it on the stack
127 - gcc can fit it in one or more registers. */
128 if (TYPE_NFIELDS (type) == 1)
130 alignment = TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0));
131 for (i = 1; i < TYPE_NFIELDS (type); i++)
133 /* If the alignment changes, just assume it goes on the
135 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, i)) != alignment)
138 /* If the alignment is suitable for the d10v's 16 bit registers,
139 don't put it on the stack. */
140 if (alignment == 2 || alignment == 4)
146 static const unsigned char *
147 d10v_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
149 static unsigned char breakpoint[] =
150 {0x2f, 0x90, 0x5e, 0x00};
151 *lenptr = sizeof (breakpoint);
155 /* Map the REG_NR onto an ascii name. Return NULL or an empty string
156 when the reg_nr isn't valid. */
160 TS2_IMAP0_REGNUM = 32,
161 TS2_DMAP_REGNUM = 34,
162 TS2_NR_DMAP_REGS = 1,
167 d10v_ts2_register_name (int reg_nr)
169 static char *register_names[] =
171 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
172 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
173 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
174 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
175 "imap0", "imap1", "dmap", "a0", "a1"
179 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
181 return register_names[reg_nr];
186 TS3_IMAP0_REGNUM = 36,
187 TS3_DMAP0_REGNUM = 38,
188 TS3_NR_DMAP_REGS = 4,
193 d10v_ts3_register_name (int reg_nr)
195 static char *register_names[] =
197 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
198 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
199 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
200 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
204 "dmap0", "dmap1", "dmap2", "dmap3"
208 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
210 return register_names[reg_nr];
213 /* Access the DMAP/IMAP registers in a target independent way.
215 Divide the D10V's 64k data space into four 16k segments:
216 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and
219 On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 --
220 0x7fff) always map to the on-chip data RAM, and the fourth always
221 maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into
222 unified memory or instruction memory, under the control of the
223 single DMAP register.
225 On the TS3, there are four DMAP registers, each of which controls
226 one of the segments. */
229 d10v_ts2_dmap_register (int reg_nr)
237 return read_register (TS2_DMAP_REGNUM);
244 d10v_ts3_dmap_register (int reg_nr)
246 return read_register (TS3_DMAP0_REGNUM + reg_nr);
250 d10v_dmap_register (int reg_nr)
252 return gdbarch_tdep (current_gdbarch)->dmap_register (reg_nr);
256 d10v_ts2_imap_register (int reg_nr)
258 return read_register (TS2_IMAP0_REGNUM + reg_nr);
262 d10v_ts3_imap_register (int reg_nr)
264 return read_register (TS3_IMAP0_REGNUM + reg_nr);
268 d10v_imap_register (int reg_nr)
270 return gdbarch_tdep (current_gdbarch)->imap_register (reg_nr);
273 /* MAP GDB's internal register numbering (determined by the layout fo
274 the REGISTER_BYTE array) onto the simulator's register
278 d10v_ts2_register_sim_regno (int nr)
280 /* Only makes sense to supply raw registers. */
281 gdb_assert (nr >= 0 && nr < NUM_REGS);
282 if (nr >= TS2_IMAP0_REGNUM
283 && nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS)
284 return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM;
285 if (nr == TS2_DMAP_REGNUM)
286 return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM;
287 if (nr >= TS2_A0_REGNUM
288 && nr < TS2_A0_REGNUM + NR_A_REGS)
289 return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM;
294 d10v_ts3_register_sim_regno (int nr)
296 /* Only makes sense to supply raw registers. */
297 gdb_assert (nr >= 0 && nr < NUM_REGS);
298 if (nr >= TS3_IMAP0_REGNUM
299 && nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS)
300 return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM;
301 if (nr >= TS3_DMAP0_REGNUM
302 && nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS)
303 return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM;
304 if (nr >= TS3_A0_REGNUM
305 && nr < TS3_A0_REGNUM + NR_A_REGS)
306 return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM;
310 /* Index within `registers' of the first byte of the space for
314 d10v_register_byte (int reg_nr)
316 if (reg_nr < A0_REGNUM)
318 else if (reg_nr < (A0_REGNUM + NR_A_REGS))
319 return (A0_REGNUM * 2
320 + (reg_nr - A0_REGNUM) * 8);
322 return (A0_REGNUM * 2
324 + (reg_nr - A0_REGNUM - NR_A_REGS) * 2);
327 /* Number of bytes of storage in the actual machine representation for
331 d10v_register_raw_size (int reg_nr)
333 if (reg_nr < A0_REGNUM)
335 else if (reg_nr < (A0_REGNUM + NR_A_REGS))
341 /* Return the GDB type object for the "standard" data type
342 of data in register N. */
345 d10v_register_type (struct gdbarch *gdbarch, int reg_nr)
347 if (reg_nr == PC_REGNUM)
348 return builtin_type_void_func_ptr;
349 if (reg_nr == _SP_REGNUM || reg_nr == D10V_FP_REGNUM)
350 return builtin_type_void_data_ptr;
351 else if (reg_nr >= A0_REGNUM
352 && reg_nr < (A0_REGNUM + NR_A_REGS))
353 return builtin_type_int64;
355 return builtin_type_int16;
359 d10v_daddr_p (CORE_ADDR x)
361 return (((x) & 0x3000000) == DMEM_START);
365 d10v_iaddr_p (CORE_ADDR x)
367 return (((x) & 0x3000000) == IMEM_START);
371 d10v_make_daddr (CORE_ADDR x)
373 return ((x) | DMEM_START);
377 d10v_make_iaddr (CORE_ADDR x)
379 if (d10v_iaddr_p (x))
380 return x; /* Idempotency -- x is already in the IMEM space. */
382 return (((x) << 2) | IMEM_START);
386 d10v_convert_iaddr_to_raw (CORE_ADDR x)
388 return (((x) >> 2) & 0xffff);
392 d10v_convert_daddr_to_raw (CORE_ADDR x)
394 return ((x) & 0xffff);
398 d10v_address_to_pointer (struct type *type, void *buf, CORE_ADDR addr)
400 /* Is it a code address? */
401 if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC
402 || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD)
404 store_unsigned_integer (buf, TYPE_LENGTH (type),
405 d10v_convert_iaddr_to_raw (addr));
409 /* Strip off any upper segment bits. */
410 store_unsigned_integer (buf, TYPE_LENGTH (type),
411 d10v_convert_daddr_to_raw (addr));
416 d10v_pointer_to_address (struct type *type, const void *buf)
418 CORE_ADDR addr = extract_address (buf, TYPE_LENGTH (type));
420 /* Is it a code address? */
421 if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC
422 || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD
423 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type)))
424 return d10v_make_iaddr (addr);
426 return d10v_make_daddr (addr);
429 /* Don't do anything if we have an integer, this way users can type 'x
430 <addr>' w/o having gdb outsmart them. The internal gdb conversions
431 to the correct space are taken care of in the pointer_to_address
432 function. If we don't do this, 'x $fp' wouldn't work. */
434 d10v_integer_to_address (struct type *type, void *buf)
437 val = unpack_long (type, buf);
441 /* Write into appropriate registers a function return value
442 of type TYPE, given in virtual format.
444 Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */
447 d10v_store_return_value (struct type *type, struct regcache *regcache,
450 /* Only char return values need to be shifted right within the first
452 if (TYPE_LENGTH (type) == 1
453 && TYPE_CODE (type) == TYPE_CODE_INT)
456 tmp[1] = *(bfd_byte *)valbuf;
457 regcache_cooked_write (regcache, RET1_REGNUM, tmp);
462 /* A structure is never more than 8 bytes long. See
463 use_struct_convention(). */
464 gdb_assert (TYPE_LENGTH (type) <= 8);
465 /* Write out most registers, stop loop before trying to write
466 out any dangling byte at the end of the buffer. */
467 for (reg = 0; (reg * 2) + 1 < TYPE_LENGTH (type); reg++)
469 regcache_cooked_write (regcache, RET1_REGNUM + reg,
470 (bfd_byte *) valbuf + reg * 2);
472 /* Write out any dangling byte at the end of the buffer. */
473 if ((reg * 2) + 1 == TYPE_LENGTH (type))
474 regcache_cooked_write_part (regcache, reg, 0, 1,
475 (bfd_byte *) valbuf + reg * 2);
479 /* Extract from an array REGBUF containing the (raw) register state
480 the address in which a function should return its structure value,
481 as a CORE_ADDR (or an expression that can be used as one). */
484 d10v_extract_struct_value_address (struct regcache *regcache)
487 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &addr);
488 return (addr | DMEM_START);
491 /* Immediately after a function call, return the saved pc. We can't
492 use frame->return_pc beause that is determined by reading R13 off
493 the stack and that may not be written yet. */
496 d10v_saved_pc_after_call (struct frame_info *frame)
498 return ((read_register (LR_REGNUM) << 2)
503 check_prologue (unsigned short op)
506 if ((op & 0x7E1F) == 0x6C1F)
510 if ((op & 0x7E3F) == 0x6E1F)
514 if ((op & 0x7FE1) == 0x01E1)
526 if ((op & 0x7E1F) == 0x681E)
530 if ((op & 0x7E3F) == 0x3A1E)
537 d10v_skip_prologue (CORE_ADDR pc)
540 unsigned short op1, op2;
541 CORE_ADDR func_addr, func_end;
542 struct symtab_and_line sal;
544 /* If we have line debugging information, then the end of the */
545 /* prologue should the first assembly instruction of the first source line */
546 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
548 sal = find_pc_line (func_addr, 0);
549 if (sal.end && sal.end < func_end)
553 if (target_read_memory (pc, (char *) &op, 4))
554 return pc; /* Can't access it -- assume no prologue. */
558 op = (unsigned long) read_memory_integer (pc, 4);
559 if ((op & 0xC0000000) == 0xC0000000)
561 /* long instruction */
562 if (((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */
563 ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */
564 ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */
569 /* short instructions */
570 if ((op & 0xC0000000) == 0x80000000)
572 op2 = (op & 0x3FFF8000) >> 15;
577 op1 = (op & 0x3FFF8000) >> 15;
580 if (check_prologue (op1))
582 if (!check_prologue (op2))
584 /* if the previous opcode was really part of the prologue */
585 /* and not just a NOP, then we want to break after both instructions */
599 struct d10v_unwind_cache
602 /* The previous frame's inner most stack address. Used as this
603 frame ID's stack_addr. */
605 /* The frame's base, optionally used by the high-level debug info. */
608 CORE_ADDR *saved_regs;
609 /* How far the SP and r11 (FP) have been offset from the start of
610 the stack frame (as defined by the previous frame's stack
619 prologue_find_regs (struct d10v_unwind_cache *info, unsigned short op,
625 if ((op & 0x7E1F) == 0x6C1F)
627 n = (op & 0x1E0) >> 5;
628 info->sp_offset -= 2;
629 info->saved_regs[n] = info->sp_offset;
634 else if ((op & 0x7E3F) == 0x6E1F)
636 n = (op & 0x1E0) >> 5;
637 info->sp_offset -= 4;
638 info->saved_regs[n] = info->sp_offset;
639 info->saved_regs[n + 1] = info->sp_offset + 2;
644 if ((op & 0x7FE1) == 0x01E1)
646 n = (op & 0x1E) >> 1;
649 info->sp_offset -= n;
656 info->uses_frame = 1;
657 info->r11_offset = info->sp_offset;
662 if ((op & 0x7E1F) == 0x6816)
664 n = (op & 0x1E0) >> 5;
665 info->saved_regs[n] = info->r11_offset;
674 if ((op & 0x7E1F) == 0x681E)
676 n = (op & 0x1E0) >> 5;
677 info->saved_regs[n] = info->sp_offset;
682 if ((op & 0x7E3F) == 0x3A1E)
684 n = (op & 0x1E0) >> 5;
685 info->saved_regs[n] = info->sp_offset;
686 info->saved_regs[n + 1] = info->sp_offset + 2;
693 /* Put here the code to store, into fi->saved_regs, the addresses of
694 the saved registers of frame described by FRAME_INFO. This
695 includes special registers such as pc and fp saved in special ways
696 in the stack frame. sp is even more special: the address we return
697 for it IS the sp for the next frame. */
699 struct d10v_unwind_cache *
700 d10v_frame_unwind_cache (struct frame_info *next_frame,
701 void **this_prologue_cache)
707 unsigned short op1, op2;
709 struct d10v_unwind_cache *info;
711 if ((*this_prologue_cache))
712 return (*this_prologue_cache);
714 info = FRAME_OBSTACK_ZALLOC (struct d10v_unwind_cache);
715 (*this_prologue_cache) = info;
716 info->saved_regs = frame_obstack_zalloc (SIZEOF_FRAME_SAVED_REGS);
722 info->uses_frame = 0;
723 for (pc = get_pc_function_start (frame_pc_unwind (next_frame));
724 pc < frame_pc_unwind (next_frame);
727 op = (unsigned long) read_memory_integer (pc, 4);
728 if ((op & 0xC0000000) == 0xC0000000)
730 /* long instruction */
731 if ((op & 0x3FFF0000) == 0x01FF0000)
734 short n = op & 0xFFFF;
735 info->sp_offset += n;
737 else if ((op & 0x3F0F0000) == 0x340F0000)
739 /* st rn, @(offset,sp) */
740 short offset = op & 0xFFFF;
741 short n = (op >> 20) & 0xF;
742 info->saved_regs[n] = info->sp_offset + offset;
744 else if ((op & 0x3F1F0000) == 0x350F0000)
746 /* st2w rn, @(offset,sp) */
747 short offset = op & 0xFFFF;
748 short n = (op >> 20) & 0xF;
749 info->saved_regs[n] = info->sp_offset + offset;
750 info->saved_regs[n + 1] = info->sp_offset + offset + 2;
757 /* short instructions */
758 if ((op & 0xC0000000) == 0x80000000)
760 op2 = (op & 0x3FFF8000) >> 15;
765 op1 = (op & 0x3FFF8000) >> 15;
768 if (!prologue_find_regs (info, op1, pc)
769 || !prologue_find_regs (info, op2, pc))
774 info->size = -info->sp_offset;
776 /* Compute the frame's base, and the previous frame's SP. */
777 if (info->uses_frame)
779 /* The SP was moved to the FP. This indicates that a new frame
780 was created. Get THIS frame's FP value by unwinding it from
782 frame_unwind_unsigned_register (next_frame, D10V_FP_REGNUM, &this_base);
783 /* The FP points at the last saved register. Adjust the FP back
784 to before the first saved register giving the SP. */
785 prev_sp = this_base + info->size;
787 else if (info->saved_regs[SP_REGNUM])
789 /* The SP was saved (which is very unusual), the frame base is
790 just the PREV's frame's TOP-OF-STACK. */
791 this_base = read_memory_unsigned_integer (info->saved_regs[SP_REGNUM],
792 register_size (current_gdbarch,
798 /* Assume that the FP is this frame's SP but with that pushed
799 stack space added back. */
800 frame_unwind_unsigned_register (next_frame, SP_REGNUM, &this_base);
801 prev_sp = this_base + info->size;
804 info->base = d10v_make_daddr (this_base);
805 info->prev_sp = d10v_make_daddr (prev_sp);
807 /* Adjust all the saved registers so that they contain addresses and
809 for (i = 0; i < NUM_REGS - 1; i++)
810 if (info->saved_regs[i])
812 info->saved_regs[i] = (info->prev_sp + info->saved_regs[i]);
815 if (info->saved_regs[LR_REGNUM])
818 = read_memory_unsigned_integer (info->saved_regs[LR_REGNUM],
819 register_size (current_gdbarch, LR_REGNUM));
820 info->return_pc = d10v_make_iaddr (return_pc);
825 frame_unwind_unsigned_register (next_frame, LR_REGNUM, &return_pc);
826 info->return_pc = d10v_make_iaddr (return_pc);
829 /* The SP_REGNUM is special. Instead of the address of the SP, the
830 previous frame's SP value is saved. */
831 info->saved_regs[SP_REGNUM] = info->prev_sp;
837 d10v_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
838 struct frame_info *frame, int regnum, int all)
842 default_print_registers_info (gdbarch, file, frame, regnum, all);
847 ULONGEST pc, psw, rpt_s, rpt_e, rpt_c;
848 frame_read_unsigned_register (frame, PC_REGNUM, &pc);
849 frame_read_unsigned_register (frame, PSW_REGNUM, &psw);
850 frame_read_unsigned_register (frame, frame_map_name_to_regnum ("rpt_s", -1), &rpt_s);
851 frame_read_unsigned_register (frame, frame_map_name_to_regnum ("rpt_e", -1), &rpt_e);
852 frame_read_unsigned_register (frame, frame_map_name_to_regnum ("rpt_c", -1), &rpt_c);
853 fprintf_filtered (file, "PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n",
854 (long) pc, (long) d10v_make_iaddr (pc), (long) psw,
855 (long) rpt_s, (long) rpt_e, (long) rpt_c);
860 for (group = 0; group < 16; group += 8)
863 fprintf_filtered (file, "R%d-R%-2d", group, group + 7);
864 for (r = group; r < group + 8; r++)
867 frame_read_unsigned_register (frame, r, &tmp);
868 fprintf_filtered (file, " %04lx", (long) tmp);
870 fprintf_filtered (file, "\n");
874 /* Note: The IMAP/DMAP registers don't participate in function
875 calls. Don't bother trying to unwind them. */
879 for (a = 0; a < NR_IMAP_REGS; a++)
882 fprintf_filtered (file, " ");
883 fprintf_filtered (file, "IMAP%d %04lx", a, d10v_imap_register (a));
885 if (NR_DMAP_REGS == 1)
886 /* Registers DMAP0 and DMAP1 are constant. Just return dmap2. */
887 fprintf_filtered (file, " DMAP %04lx\n", d10v_dmap_register (2));
890 for (a = 0; a < NR_DMAP_REGS; a++)
892 fprintf_filtered (file, " DMAP%d %04lx", a, d10v_dmap_register (a));
894 fprintf_filtered (file, "\n");
899 char *num = alloca (max_register_size (gdbarch));
901 fprintf_filtered (file, "A0-A%d", NR_A_REGS - 1);
902 for (a = A0_REGNUM; a < A0_REGNUM + NR_A_REGS; a++)
905 fprintf_filtered (file, " ");
906 frame_register_read (frame, a, num);
907 for (i = 0; i < max_register_size (current_gdbarch); i++)
909 fprintf_filtered (file, "%02x", (num[i] & 0xff));
913 fprintf_filtered (file, "\n");
917 show_regs (char *args, int from_tty)
919 d10v_print_registers_info (current_gdbarch, gdb_stdout,
920 get_current_frame (), -1, 1);
924 d10v_read_pc (ptid_t ptid)
930 save_ptid = inferior_ptid;
931 inferior_ptid = ptid;
932 pc = (int) read_register (PC_REGNUM);
933 inferior_ptid = save_ptid;
934 retval = d10v_make_iaddr (pc);
939 d10v_write_pc (CORE_ADDR val, ptid_t ptid)
943 save_ptid = inferior_ptid;
944 inferior_ptid = ptid;
945 write_register (PC_REGNUM, d10v_convert_iaddr_to_raw (val));
946 inferior_ptid = save_ptid;
952 return (d10v_make_daddr (read_register (SP_REGNUM)));
958 return (d10v_make_daddr (read_register (D10V_FP_REGNUM)));
961 /* When arguments must be pushed onto the stack, they go on in reverse
962 order. The below implements a FILO (stack) to do this. */
967 struct stack_item *prev;
971 static struct stack_item *push_stack_item (struct stack_item *prev,
972 void *contents, int len);
973 static struct stack_item *
974 push_stack_item (struct stack_item *prev, void *contents, int len)
976 struct stack_item *si;
977 si = xmalloc (sizeof (struct stack_item));
978 si->data = xmalloc (len);
981 memcpy (si->data, contents, len);
985 static struct stack_item *pop_stack_item (struct stack_item *si);
986 static struct stack_item *
987 pop_stack_item (struct stack_item *si)
989 struct stack_item *dead = si;
998 d10v_push_dummy_call (struct gdbarch *gdbarch, struct regcache *regcache,
999 CORE_ADDR dummy_addr, int nargs, struct value **args,
1000 CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr)
1003 int regnum = ARG1_REGNUM;
1004 struct stack_item *si = NULL;
1007 /* Set the return address. For the d10v, the return breakpoint is
1008 always at DUMMY_ADDR. */
1009 regcache_cooked_write_unsigned (regcache, LR_REGNUM,
1010 d10v_convert_iaddr_to_raw (dummy_addr));
1012 /* If STRUCT_RETURN is true, then the struct return address (in
1013 STRUCT_ADDR) will consume the first argument-passing register.
1014 Both adjust the register count and store that value. */
1017 regcache_cooked_write_unsigned (regcache, regnum, struct_addr);
1021 /* Fill in registers and arg lists */
1022 for (i = 0; i < nargs; i++)
1024 struct value *arg = args[i];
1025 struct type *type = check_typedef (VALUE_TYPE (arg));
1026 char *contents = VALUE_CONTENTS (arg);
1027 int len = TYPE_LENGTH (type);
1028 int aligned_regnum = (regnum + 1) & ~1;
1030 /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */
1031 if (len <= 2 && regnum <= ARGN_REGNUM)
1032 /* fits in a single register, do not align */
1034 val = extract_unsigned_integer (contents, len);
1035 regcache_cooked_write_unsigned (regcache, regnum++, val);
1037 else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2)
1038 /* value fits in remaining registers, store keeping left
1042 regnum = aligned_regnum;
1043 for (b = 0; b < (len & ~1); b += 2)
1045 val = extract_unsigned_integer (&contents[b], 2);
1046 regcache_cooked_write_unsigned (regcache, regnum++, val);
1050 val = extract_unsigned_integer (&contents[b], 1);
1051 regcache_cooked_write_unsigned (regcache, regnum++, (val << 8));
1056 /* arg will go onto stack */
1057 regnum = ARGN_REGNUM + 1;
1058 si = push_stack_item (si, contents, len);
1064 sp = (sp - si->len) & ~1;
1065 write_memory (sp, si->data, si->len);
1066 si = pop_stack_item (si);
1069 /* Finally, update the SP register. */
1070 regcache_cooked_write_unsigned (regcache, SP_REGNUM,
1071 d10v_convert_daddr_to_raw (sp));
1077 /* Given a return value in `regbuf' with a type `valtype',
1078 extract and copy its value into `valbuf'. */
1081 d10v_extract_return_value (struct type *type, struct regcache *regcache,
1086 printf("RET: TYPE=%d len=%d r%d=0x%x\n", TYPE_CODE (type),
1087 TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM,
1088 (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM),
1089 register_size (current_gdbarch, RET1_REGNUM)));
1091 if (TYPE_LENGTH (type) == 1)
1094 regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &c);
1095 store_unsigned_integer (valbuf, 1, c);
1099 /* For return values of odd size, the first byte is in the
1100 least significant part of the first register. The
1101 remaining bytes in remaining registers. Interestingly, when
1102 such values are passed in, the last byte is in the most
1103 significant byte of that same register - wierd. */
1104 int reg = RET1_REGNUM;
1106 if (TYPE_LENGTH (type) & 1)
1108 regcache_cooked_read_part (regcache, RET1_REGNUM, 1, 1,
1109 (bfd_byte *)valbuf + off);
1113 /* Transfer the remaining registers. */
1114 for (; off < TYPE_LENGTH (type); reg++, off += 2)
1116 regcache_cooked_read (regcache, RET1_REGNUM + reg,
1117 (bfd_byte *) valbuf + off);
1122 /* Translate a GDB virtual ADDR/LEN into a format the remote target
1123 understands. Returns number of bytes that can be transfered
1124 starting at TARG_ADDR. Return ZERO if no bytes can be transfered
1125 (segmentation fault). Since the simulator knows all about how the
1126 VM system works, we just call that to do the translation. */
1129 remote_d10v_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes,
1130 CORE_ADDR *targ_addr, int *targ_len)
1134 out_len = sim_d10v_translate_addr (memaddr, nr_bytes,
1137 d10v_imap_register);
1138 *targ_addr = out_addr;
1139 *targ_len = out_len;
1143 /* The following code implements access to, and display of, the D10V's
1144 instruction trace buffer. The buffer consists of 64K or more
1145 4-byte words of data, of which each words includes an 8-bit count,
1146 an 8-bit segment number, and a 16-bit instruction address.
1148 In theory, the trace buffer is continuously capturing instruction
1149 data that the CPU presents on its "debug bus", but in practice, the
1150 ROMified GDB stub only enables tracing when it continues or steps
1151 the program, and stops tracing when the program stops; so it
1152 actually works for GDB to read the buffer counter out of memory and
1153 then read each trace word. The counter records where the tracing
1154 stops, but there is no record of where it started, so we remember
1155 the PC when we resumed and then search backwards in the trace
1156 buffer for a word that includes that address. This is not perfect,
1157 because you will miss trace data if the resumption PC is the target
1158 of a branch. (The value of the buffer counter is semi-random, any
1159 trace data from a previous program stop is gone.) */
1161 /* The address of the last word recorded in the trace buffer. */
1163 #define DBBC_ADDR (0xd80000)
1165 /* The base of the trace buffer, at least for the "Board_0". */
1167 #define TRACE_BUFFER_BASE (0xf40000)
1169 static void trace_command (char *, int);
1171 static void untrace_command (char *, int);
1173 static void trace_info (char *, int);
1175 static void tdisassemble_command (char *, int);
1177 static void display_trace (int, int);
1179 /* True when instruction traces are being collected. */
1183 /* Remembered PC. */
1185 static CORE_ADDR last_pc;
1187 /* True when trace output should be displayed whenever program stops. */
1189 static int trace_display;
1191 /* True when trace listing should include source lines. */
1193 static int default_trace_show_source = 1;
1204 trace_command (char *args, int from_tty)
1206 /* Clear the host-side trace buffer, allocating space if needed. */
1207 trace_data.size = 0;
1208 if (trace_data.counts == NULL)
1209 trace_data.counts = (short *) xmalloc (65536 * sizeof (short));
1210 if (trace_data.addrs == NULL)
1211 trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR));
1215 printf_filtered ("Tracing is now on.\n");
1219 untrace_command (char *args, int from_tty)
1223 printf_filtered ("Tracing is now off.\n");
1227 trace_info (char *args, int from_tty)
1231 if (trace_data.size)
1233 printf_filtered ("%d entries in trace buffer:\n", trace_data.size);
1235 for (i = 0; i < trace_data.size; ++i)
1237 printf_filtered ("%d: %d instruction%s at 0x%s\n",
1239 trace_data.counts[i],
1240 (trace_data.counts[i] == 1 ? "" : "s"),
1241 paddr_nz (trace_data.addrs[i]));
1245 printf_filtered ("No entries in trace buffer.\n");
1247 printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off"));
1250 /* Print the instruction at address MEMADDR in debugged memory,
1251 on STREAM. Returns length of the instruction, in bytes. */
1254 print_insn (CORE_ADDR memaddr, struct ui_file *stream)
1256 /* If there's no disassembler, something is very wrong. */
1257 if (tm_print_insn == NULL)
1258 internal_error (__FILE__, __LINE__,
1259 "print_insn: no disassembler");
1261 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1262 tm_print_insn_info.endian = BFD_ENDIAN_BIG;
1264 tm_print_insn_info.endian = BFD_ENDIAN_LITTLE;
1265 return TARGET_PRINT_INSN (memaddr, &tm_print_insn_info);
1269 d10v_eva_prepare_to_trace (void)
1274 last_pc = read_register (PC_REGNUM);
1277 /* Collect trace data from the target board and format it into a form
1278 more useful for display. */
1281 d10v_eva_get_trace_data (void)
1283 int count, i, j, oldsize;
1284 int trace_addr, trace_seg, trace_cnt, next_cnt;
1285 unsigned int last_trace, trace_word, next_word;
1286 unsigned int *tmpspace;
1291 tmpspace = xmalloc (65536 * sizeof (unsigned int));
1293 last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2;
1295 /* Collect buffer contents from the target, stopping when we reach
1296 the word recorded when execution resumed. */
1299 while (last_trace > 0)
1303 read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4);
1304 trace_addr = trace_word & 0xffff;
1306 /* Ignore an apparently nonsensical entry. */
1307 if (trace_addr == 0xffd5)
1309 tmpspace[count++] = trace_word;
1310 if (trace_addr == last_pc)
1316 /* Move the data to the host-side trace buffer, adjusting counts to
1317 include the last instruction executed and transforming the address
1318 into something that GDB likes. */
1320 for (i = 0; i < count; ++i)
1322 trace_word = tmpspace[i];
1323 next_word = ((i == 0) ? 0 : tmpspace[i - 1]);
1324 trace_addr = trace_word & 0xffff;
1325 next_cnt = (next_word >> 24) & 0xff;
1326 j = trace_data.size + count - i - 1;
1327 trace_data.addrs[j] = (trace_addr << 2) + 0x1000000;
1328 trace_data.counts[j] = next_cnt + 1;
1331 oldsize = trace_data.size;
1332 trace_data.size += count;
1337 display_trace (oldsize, trace_data.size);
1341 tdisassemble_command (char *arg, int from_tty)
1344 CORE_ADDR low, high;
1349 high = trace_data.size;
1353 char *space_index = strchr (arg, ' ');
1354 if (space_index == NULL)
1356 low = parse_and_eval_address (arg);
1361 /* Two arguments. */
1362 *space_index = '\0';
1363 low = parse_and_eval_address (arg);
1364 high = parse_and_eval_address (space_index + 1);
1370 printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high));
1372 display_trace (low, high);
1374 printf_filtered ("End of trace dump.\n");
1375 gdb_flush (gdb_stdout);
1379 display_trace (int low, int high)
1381 int i, count, trace_show_source, first, suppress;
1382 CORE_ADDR next_address;
1384 trace_show_source = default_trace_show_source;
1385 if (!have_full_symbols () && !have_partial_symbols ())
1387 trace_show_source = 0;
1388 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
1389 printf_filtered ("Trace will not display any source.\n");
1394 for (i = low; i < high; ++i)
1396 next_address = trace_data.addrs[i];
1397 count = trace_data.counts[i];
1401 if (trace_show_source)
1403 struct symtab_and_line sal, sal_prev;
1405 sal_prev = find_pc_line (next_address - 4, 0);
1406 sal = find_pc_line (next_address, 0);
1410 if (first || sal.line != sal_prev.line)
1411 print_source_lines (sal.symtab, sal.line, sal.line + 1, 0);
1417 /* FIXME-32x64--assumes sal.pc fits in long. */
1418 printf_filtered ("No source file for address %s.\n",
1419 local_hex_string ((unsigned long) sal.pc));
1424 print_address (next_address, gdb_stdout);
1425 printf_filtered (":");
1426 printf_filtered ("\t");
1428 next_address = next_address + print_insn (next_address, gdb_stdout);
1429 printf_filtered ("\n");
1430 gdb_flush (gdb_stdout);
1436 d10v_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1439 frame_unwind_unsigned_register (next_frame, PC_REGNUM, &pc);
1440 return d10v_make_iaddr (pc);
1443 /* Given a GDB frame, determine the address of the calling function's
1444 frame. This will be used to create a new GDB frame struct. */
1447 d10v_frame_this_id (struct frame_info *next_frame,
1448 void **this_prologue_cache,
1449 struct frame_id *this_id)
1451 struct d10v_unwind_cache *info
1452 = d10v_frame_unwind_cache (next_frame, this_prologue_cache);
1456 /* The PC is easy. */
1457 pc = frame_pc_unwind (next_frame);
1459 /* This is meant to halt the backtrace at "_start". Make sure we
1460 don't halt it at a generic dummy frame. */
1461 if (pc == IMEM_START || pc <= IMEM_START || inside_entry_file (pc))
1464 /* Hopefully the prologue analysis either correctly determined the
1465 frame's base (which is the SP from the previous frame), or set
1466 that base to "NULL". */
1467 base = info->prev_sp;
1468 if (base == STACK_START || base == 0)
1471 /* Check that we're not going round in circles with the same frame
1472 ID (but avoid applying the test to sentinel frames which do go
1473 round in circles). Can't use frame_id_eq() as that doesn't yet
1474 compare the frame's PC value. */
1475 if (frame_relative_level (next_frame) >= 0
1476 && get_frame_type (next_frame) != DUMMY_FRAME
1477 && get_frame_pc (next_frame) == pc
1478 && get_frame_base (next_frame) == base)
1481 (*this_id) = frame_id_build (base, pc);
1485 saved_regs_unwinder (struct frame_info *next_frame,
1486 CORE_ADDR *this_saved_regs,
1487 int regnum, int *optimizedp,
1488 enum lval_type *lvalp, CORE_ADDR *addrp,
1489 int *realnump, void *bufferp)
1491 if (this_saved_regs[regnum] != 0)
1493 if (regnum == SP_REGNUM)
1495 /* SP register treated specially. */
1500 if (bufferp != NULL)
1501 store_address (bufferp, register_size (current_gdbarch, regnum),
1502 this_saved_regs[regnum]);
1506 /* Any other register is saved in memory, fetch it but cache
1507 a local copy of its value. */
1509 *lvalp = lval_memory;
1510 *addrp = this_saved_regs[regnum];
1512 if (bufferp != NULL)
1514 /* Read the value in from memory. */
1515 read_memory (this_saved_regs[regnum], bufferp,
1516 register_size (current_gdbarch, regnum));
1522 /* No luck, assume this and the next frame have the same register
1523 value. If a value is needed, pass the request on down the chain;
1524 otherwise just return an indication that the value is in the same
1525 register as the next frame. */
1526 frame_register_unwind (next_frame, regnum, optimizedp, lvalp, addrp,
1532 d10v_frame_prev_register (struct frame_info *next_frame,
1533 void **this_prologue_cache,
1534 int regnum, int *optimizedp,
1535 enum lval_type *lvalp, CORE_ADDR *addrp,
1536 int *realnump, void *bufferp)
1538 struct d10v_unwind_cache *info
1539 = d10v_frame_unwind_cache (next_frame, this_prologue_cache);
1540 if (regnum == PC_REGNUM)
1542 /* The call instruction saves the caller's PC in LR. The
1543 function prologue of the callee may then save the LR on the
1544 stack. Find that possibly saved LR value and return it. */
1545 saved_regs_unwinder (next_frame, info->saved_regs, LR_REGNUM, optimizedp,
1546 lvalp, addrp, realnump, bufferp);
1550 saved_regs_unwinder (next_frame, info->saved_regs, regnum, optimizedp,
1551 lvalp, addrp, realnump, bufferp);
1555 static const struct frame_unwind d10v_frame_unwind = {
1558 d10v_frame_prev_register
1561 const struct frame_unwind *
1562 d10v_frame_p (CORE_ADDR pc)
1564 return &d10v_frame_unwind;
1568 d10v_frame_base_address (struct frame_info *next_frame, void **this_cache)
1570 struct d10v_unwind_cache *info
1571 = d10v_frame_unwind_cache (next_frame, this_cache);
1575 static const struct frame_base d10v_frame_base = {
1577 d10v_frame_base_address,
1578 d10v_frame_base_address,
1579 d10v_frame_base_address
1582 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1583 dummy frame. The frame ID's base needs to match the TOS value
1584 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1587 static struct frame_id
1588 d10v_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1591 frame_unwind_unsigned_register (next_frame, SP_REGNUM, &base);
1592 return frame_id_build (d10v_make_daddr (base), frame_pc_unwind (next_frame));
1595 static gdbarch_init_ftype d10v_gdbarch_init;
1597 static struct gdbarch *
1598 d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1600 struct gdbarch *gdbarch;
1602 struct gdbarch_tdep *tdep;
1603 gdbarch_register_name_ftype *d10v_register_name;
1604 gdbarch_register_sim_regno_ftype *d10v_register_sim_regno;
1606 /* Find a candidate among the list of pre-declared architectures. */
1607 arches = gdbarch_list_lookup_by_info (arches, &info);
1609 return arches->gdbarch;
1611 /* None found, create a new architecture from the information
1613 tdep = XMALLOC (struct gdbarch_tdep);
1614 gdbarch = gdbarch_alloc (&info, tdep);
1616 switch (info.bfd_arch_info->mach)
1618 case bfd_mach_d10v_ts2:
1620 d10v_register_name = d10v_ts2_register_name;
1621 d10v_register_sim_regno = d10v_ts2_register_sim_regno;
1622 tdep->a0_regnum = TS2_A0_REGNUM;
1623 tdep->nr_dmap_regs = TS2_NR_DMAP_REGS;
1624 tdep->dmap_register = d10v_ts2_dmap_register;
1625 tdep->imap_register = d10v_ts2_imap_register;
1628 case bfd_mach_d10v_ts3:
1630 d10v_register_name = d10v_ts3_register_name;
1631 d10v_register_sim_regno = d10v_ts3_register_sim_regno;
1632 tdep->a0_regnum = TS3_A0_REGNUM;
1633 tdep->nr_dmap_regs = TS3_NR_DMAP_REGS;
1634 tdep->dmap_register = d10v_ts3_dmap_register;
1635 tdep->imap_register = d10v_ts3_imap_register;
1639 set_gdbarch_read_pc (gdbarch, d10v_read_pc);
1640 set_gdbarch_write_pc (gdbarch, d10v_write_pc);
1641 set_gdbarch_read_fp (gdbarch, d10v_read_fp);
1642 set_gdbarch_read_sp (gdbarch, d10v_read_sp);
1644 set_gdbarch_num_regs (gdbarch, d10v_num_regs);
1645 set_gdbarch_sp_regnum (gdbarch, 15);
1646 set_gdbarch_pc_regnum (gdbarch, 18);
1647 set_gdbarch_register_name (gdbarch, d10v_register_name);
1648 set_gdbarch_register_size (gdbarch, 2);
1649 set_gdbarch_register_bytes (gdbarch, (d10v_num_regs - 2) * 2 + 16);
1650 set_gdbarch_register_byte (gdbarch, d10v_register_byte);
1651 set_gdbarch_register_raw_size (gdbarch, d10v_register_raw_size);
1652 set_gdbarch_register_virtual_size (gdbarch, generic_register_size);
1653 set_gdbarch_register_type (gdbarch, d10v_register_type);
1655 set_gdbarch_ptr_bit (gdbarch, 2 * TARGET_CHAR_BIT);
1656 set_gdbarch_addr_bit (gdbarch, 32);
1657 set_gdbarch_address_to_pointer (gdbarch, d10v_address_to_pointer);
1658 set_gdbarch_pointer_to_address (gdbarch, d10v_pointer_to_address);
1659 set_gdbarch_integer_to_address (gdbarch, d10v_integer_to_address);
1660 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
1661 set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT);
1662 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1663 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1664 /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long
1665 double'' is 64 bits. */
1666 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1667 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1668 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1669 switch (info.byte_order)
1671 case BFD_ENDIAN_BIG:
1672 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big);
1673 set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_big);
1674 set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big);
1676 case BFD_ENDIAN_LITTLE:
1677 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little);
1678 set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_little);
1679 set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_little);
1682 internal_error (__FILE__, __LINE__,
1683 "d10v_gdbarch_init: bad byte order for float format");
1686 set_gdbarch_extract_return_value (gdbarch, d10v_extract_return_value);
1687 set_gdbarch_push_dummy_call (gdbarch, d10v_push_dummy_call);
1688 set_gdbarch_store_return_value (gdbarch, d10v_store_return_value);
1689 set_gdbarch_extract_struct_value_address (gdbarch, d10v_extract_struct_value_address);
1690 set_gdbarch_use_struct_convention (gdbarch, d10v_use_struct_convention);
1692 set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue);
1693 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1694 set_gdbarch_decr_pc_after_break (gdbarch, 4);
1695 set_gdbarch_function_start_offset (gdbarch, 0);
1696 set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc);
1698 set_gdbarch_remote_translate_xfer_address (gdbarch, remote_d10v_translate_xfer_address);
1700 set_gdbarch_frame_args_skip (gdbarch, 0);
1701 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
1703 set_gdbarch_saved_pc_after_call (gdbarch, d10v_saved_pc_after_call);
1704 set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
1705 set_gdbarch_stack_align (gdbarch, d10v_stack_align);
1707 set_gdbarch_register_sim_regno (gdbarch, d10v_register_sim_regno);
1709 set_gdbarch_print_registers_info (gdbarch, d10v_print_registers_info);
1711 frame_unwind_append_predicate (gdbarch, d10v_frame_p);
1712 frame_base_set_default (gdbarch, &d10v_frame_base);
1714 /* Methods for saving / extracting a dummy frame's ID. */
1715 set_gdbarch_unwind_dummy_id (gdbarch, d10v_unwind_dummy_id);
1716 set_gdbarch_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos);
1718 /* Return the unwound PC value. */
1719 set_gdbarch_unwind_pc (gdbarch, d10v_unwind_pc);
1725 _initialize_d10v_tdep (void)
1727 register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init);
1729 tm_print_insn = print_insn_d10v;
1731 target_resume_hook = d10v_eva_prepare_to_trace;
1732 target_wait_loop_hook = d10v_eva_get_trace_data;
1734 deprecate_cmd (add_com ("regs", class_vars, show_regs, "Print all registers"),
1737 add_com ("itrace", class_support, trace_command,
1738 "Enable tracing of instruction execution.");
1740 add_com ("iuntrace", class_support, untrace_command,
1741 "Disable tracing of instruction execution.");
1743 add_com ("itdisassemble", class_vars, tdisassemble_command,
1744 "Disassemble the trace buffer.\n\
1745 Two optional arguments specify a range of trace buffer entries\n\
1746 as reported by info trace (NOT addresses!).");
1748 add_info ("itrace", trace_info,
1749 "Display info about the trace data buffer.");
1751 add_show_from_set (add_set_cmd ("itracedisplay", no_class,
1752 var_integer, (char *) &trace_display,
1753 "Set automatic display of trace.\n", &setlist),
1755 add_show_from_set (add_set_cmd ("itracesource", no_class,
1756 var_integer, (char *) &default_trace_show_source,
1757 "Set display of source code with trace.\n", &setlist),