1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
3 Copyright (C) 2001-2016 Free Software Foundation, Inc.
5 Contributed by Axis Communications AB.
6 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include "frame-unwind.h"
26 #include "frame-base.h"
27 #include "trad-frame.h"
28 #include "dwarf2-frame.h"
36 #include "opcode/cris.h"
38 #include "arch-utils.h"
43 #include "solib.h" /* Support for shared libraries. */
44 #include "solib-svr4.h"
47 #include "cris-tdep.h"
51 /* There are no floating point registers. Used in gdbserver low-linux.c. */
54 /* There are 16 general registers. */
57 /* There are 16 special registers. */
60 /* CRISv32 has a pseudo PC register, not noted here. */
62 /* CRISv32 has 16 support registers. */
66 /* Register numbers of various important registers.
67 CRIS_FP_REGNUM Contains address of executing stack frame.
68 STR_REGNUM Contains the address of structure return values.
69 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
70 ARG1_REGNUM Contains the first parameter to a function.
71 ARG2_REGNUM Contains the second parameter to a function.
72 ARG3_REGNUM Contains the third parameter to a function.
73 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
74 gdbarch_sp_regnum Contains address of top of stack.
75 gdbarch_pc_regnum Contains address of next instruction.
76 SRP_REGNUM Subroutine return pointer register.
77 BRP_REGNUM Breakpoint return pointer register. */
81 /* Enums with respect to the general registers, valid for all
82 CRIS versions. The frame pointer is always in R8. */
84 /* ABI related registers. */
92 /* Registers which happen to be common. */
97 /* CRISv10 et al. specific registers. */
109 /* CRISv32 specific registers. */
122 CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */
124 CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */
144 extern const struct cris_spec_reg cris_spec_regs[];
146 /* CRIS version, set via the user command 'set cris-version'. Affects
147 register names and sizes. */
148 static unsigned int usr_cmd_cris_version;
150 /* Indicates whether to trust the above variable. */
151 static int usr_cmd_cris_version_valid = 0;
153 static const char cris_mode_normal[] = "normal";
154 static const char cris_mode_guru[] = "guru";
155 static const char *const cris_modes[] = {
161 /* CRIS mode, set via the user command 'set cris-mode'. Affects
162 type of break instruction among other things. */
163 static const char *usr_cmd_cris_mode = cris_mode_normal;
165 /* Whether to make use of Dwarf-2 CFI (default on). */
166 static int usr_cmd_cris_dwarf2_cfi = 1;
168 /* Sigtramp identification code copied from i386-linux-tdep.c. */
170 #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
171 #define SIGTRAMP_OFFSET0 0
172 #define SIGTRAMP_INSN1 0xe93d /* break 13 */
173 #define SIGTRAMP_OFFSET1 4
175 static const unsigned short sigtramp_code[] =
177 SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */
178 SIGTRAMP_INSN1 /* break 13 */
181 #define SIGTRAMP_LEN (sizeof sigtramp_code)
183 /* Note: same length as normal sigtramp code. */
185 static const unsigned short rt_sigtramp_code[] =
187 SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */
188 SIGTRAMP_INSN1 /* break 13 */
191 /* If PC is in a sigtramp routine, return the address of the start of
192 the routine. Otherwise, return 0. */
195 cris_sigtramp_start (struct frame_info *this_frame)
197 CORE_ADDR pc = get_frame_pc (this_frame);
198 gdb_byte buf[SIGTRAMP_LEN];
200 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
203 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
205 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
208 pc -= SIGTRAMP_OFFSET1;
209 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
213 if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0)
219 /* If PC is in a RT sigtramp routine, return the address of the start of
220 the routine. Otherwise, return 0. */
223 cris_rt_sigtramp_start (struct frame_info *this_frame)
225 CORE_ADDR pc = get_frame_pc (this_frame);
226 gdb_byte buf[SIGTRAMP_LEN];
228 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
231 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
233 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
236 pc -= SIGTRAMP_OFFSET1;
237 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
241 if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0)
247 /* Assuming THIS_FRAME is a frame for a GNU/Linux sigtramp routine,
248 return the address of the associated sigcontext structure. */
251 cris_sigcontext_addr (struct frame_info *this_frame)
253 struct gdbarch *gdbarch = get_frame_arch (this_frame);
254 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
259 get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
260 sp = extract_unsigned_integer (buf, 4, byte_order);
262 /* Look for normal sigtramp frame first. */
263 pc = cris_sigtramp_start (this_frame);
266 /* struct signal_frame (arch/cris/kernel/signal.c) contains
267 struct sigcontext as its first member, meaning the SP points to
272 pc = cris_rt_sigtramp_start (this_frame);
275 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
276 a struct ucontext, which in turn contains a struct sigcontext.
278 4 + 4 + 128 to struct ucontext, then
279 4 + 4 + 12 to struct sigcontext. */
283 error (_("Couldn't recognize signal trampoline."));
287 struct cris_unwind_cache
289 /* The previous frame's inner most stack address. Used as this
290 frame ID's stack_addr. */
292 /* The frame's base, optionally used by the high-level debug info. */
295 /* How far the SP and r8 (FP) have been offset from the start of
296 the stack frame (as defined by the previous frame's stack
302 /* From old frame_extra_info struct. */
306 /* Table indicating the location of each and every register. */
307 struct trad_frame_saved_reg *saved_regs;
310 static struct cris_unwind_cache *
311 cris_sigtramp_frame_unwind_cache (struct frame_info *this_frame,
314 struct gdbarch *gdbarch = get_frame_arch (this_frame);
315 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
316 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
317 struct cris_unwind_cache *info;
323 return (struct cris_unwind_cache *) (*this_cache);
325 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
326 (*this_cache) = info;
327 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
329 /* Zero all fields. */
335 info->uses_frame = 0;
337 info->leaf_function = 0;
339 get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
340 info->base = extract_unsigned_integer (buf, 4, byte_order);
342 addr = cris_sigcontext_addr (this_frame);
344 /* Layout of the sigcontext struct:
347 unsigned long oldmask;
351 if (tdep->cris_version == 10)
353 /* R0 to R13 are stored in reverse order at offset (2 * 4) in
355 for (i = 0; i <= 13; i++)
356 info->saved_regs[i].addr = addr + ((15 - i) * 4);
358 info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4);
359 info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4);
360 info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4);
361 /* Note: IRP is off by 2 at this point. There's no point in correcting
362 it though since that will mean that the backtrace will show a PC
363 different from what is shown when stopped. */
364 info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4);
365 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
366 = info->saved_regs[IRP_REGNUM];
367 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr = addr + (24 * 4);
372 /* R0 to R13 are stored in order at offset (1 * 4) in
374 for (i = 0; i <= 13; i++)
375 info->saved_regs[i].addr = addr + ((i + 1) * 4);
377 info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4);
378 info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4);
379 info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4);
380 info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4);
381 info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4);
382 info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4);
383 info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4);
384 info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4);
385 info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4);
387 /* FIXME: If ERP is in a delay slot at this point then the PC will
388 be wrong at this point. This problem manifests itself in the
389 sigaltstack.exp test case, which occasionally generates FAILs when
390 the signal is received while in a delay slot.
392 This could be solved by a couple of read_memory_unsigned_integer and a
393 trad_frame_set_value. */
394 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
395 = info->saved_regs[ERP_REGNUM];
397 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr
405 cris_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
406 struct frame_id *this_id)
408 struct cris_unwind_cache *cache =
409 cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
410 (*this_id) = frame_id_build (cache->base, get_frame_pc (this_frame));
413 /* Forward declaration. */
415 static struct value *cris_frame_prev_register (struct frame_info *this_frame,
416 void **this_cache, int regnum);
417 static struct value *
418 cris_sigtramp_frame_prev_register (struct frame_info *this_frame,
419 void **this_cache, int regnum)
421 /* Make sure we've initialized the cache. */
422 cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
423 return cris_frame_prev_register (this_frame, this_cache, regnum);
427 cris_sigtramp_frame_sniffer (const struct frame_unwind *self,
428 struct frame_info *this_frame,
431 if (cris_sigtramp_start (this_frame)
432 || cris_rt_sigtramp_start (this_frame))
438 static const struct frame_unwind cris_sigtramp_frame_unwind =
441 default_frame_unwind_stop_reason,
442 cris_sigtramp_frame_this_id,
443 cris_sigtramp_frame_prev_register,
445 cris_sigtramp_frame_sniffer
449 crisv32_single_step_through_delay (struct gdbarch *gdbarch,
450 struct frame_info *this_frame)
452 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
456 if (tdep->cris_mode == cris_mode_guru)
457 erp = get_frame_register_unsigned (this_frame, NRP_REGNUM);
459 erp = get_frame_register_unsigned (this_frame, ERP_REGNUM);
463 /* In delay slot - check if there's a breakpoint at the preceding
465 if (breakpoint_here_p (get_frame_address_space (this_frame), erp & ~0x1))
471 /* The instruction environment needed to find single-step breakpoints. */
474 struct instruction_environment
476 unsigned long reg[NUM_GENREGS];
477 unsigned long preg[NUM_SPECREGS];
478 unsigned long branch_break_address;
479 unsigned long delay_slot_pc;
480 unsigned long prefix_value;
485 int delay_slot_pc_active;
487 int disable_interrupt;
488 enum bfd_endian byte_order;
491 /* Machine-dependencies in CRIS for opcodes. */
493 /* Instruction sizes. */
494 enum cris_instruction_sizes
501 /* Addressing modes. */
502 enum cris_addressing_modes
509 /* Prefix addressing modes. */
510 enum cris_prefix_addressing_modes
512 PREFIX_INDEX_MODE = 2,
513 PREFIX_ASSIGN_MODE = 3,
515 /* Handle immediate byte offset addressing mode prefix format. */
516 PREFIX_OFFSET_MODE = 2
519 /* Masks for opcodes. */
520 enum cris_opcode_masks
522 BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1,
523 SIGNED_EXTEND_BIT_MASK = 0x2,
524 SIGNED_BYTE_MASK = 0x80,
525 SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00,
526 SIGNED_WORD_MASK = 0x8000,
527 SIGNED_WORD_EXTEND_MASK = 0xFFFF0000,
528 SIGNED_DWORD_MASK = 0x80000000,
529 SIGNED_QUICK_VALUE_MASK = 0x20,
530 SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0
533 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
541 cris_get_operand2 (unsigned short insn)
543 return ((insn & 0xF000) >> 12);
547 cris_get_mode (unsigned short insn)
549 return ((insn & 0x0C00) >> 10);
553 cris_get_opcode (unsigned short insn)
555 return ((insn & 0x03C0) >> 6);
559 cris_get_size (unsigned short insn)
561 return ((insn & 0x0030) >> 4);
565 cris_get_operand1 (unsigned short insn)
567 return (insn & 0x000F);
570 /* Additional functions in order to handle opcodes. */
573 cris_get_quick_value (unsigned short insn)
575 return (insn & 0x003F);
579 cris_get_bdap_quick_offset (unsigned short insn)
581 return (insn & 0x00FF);
585 cris_get_branch_short_offset (unsigned short insn)
587 return (insn & 0x00FF);
591 cris_get_asr_shift_steps (unsigned long value)
593 return (value & 0x3F);
597 cris_get_clear_size (unsigned short insn)
599 return ((insn) & 0xC000);
603 cris_is_signed_extend_bit_on (unsigned short insn)
605 return (((insn) & 0x20) == 0x20);
609 cris_is_xflag_bit_on (unsigned short insn)
611 return (((insn) & 0x1000) == 0x1000);
615 cris_set_size_to_dword (unsigned short *insn)
622 cris_get_signed_offset (unsigned short insn)
624 return ((signed char) (insn & 0x00FF));
627 /* Calls an op function given the op-type, working on the insn and the
629 static void cris_gdb_func (struct gdbarch *, enum cris_op_type, unsigned short,
632 static struct gdbarch *cris_gdbarch_init (struct gdbarch_info,
633 struct gdbarch_list *);
635 static void cris_dump_tdep (struct gdbarch *, struct ui_file *);
637 static void set_cris_version (char *ignore_args, int from_tty,
638 struct cmd_list_element *c);
640 static void set_cris_mode (char *ignore_args, int from_tty,
641 struct cmd_list_element *c);
643 static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
644 struct cmd_list_element *c);
646 static CORE_ADDR cris_scan_prologue (CORE_ADDR pc,
647 struct frame_info *this_frame,
648 struct cris_unwind_cache *info);
650 static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc,
651 struct frame_info *this_frame,
652 struct cris_unwind_cache *info);
654 static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch,
655 struct frame_info *next_frame);
657 static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch,
658 struct frame_info *next_frame);
660 /* When arguments must be pushed onto the stack, they go on in reverse
661 order. The below implements a FILO (stack) to do this.
662 Copied from d10v-tdep.c. */
667 struct stack_item *prev;
671 static struct stack_item *
672 push_stack_item (struct stack_item *prev, const gdb_byte *contents, int len)
674 struct stack_item *si = XNEW (struct stack_item);
675 si->data = (gdb_byte *) xmalloc (len);
678 memcpy (si->data, contents, len);
682 static struct stack_item *
683 pop_stack_item (struct stack_item *si)
685 struct stack_item *dead = si;
692 /* Put here the code to store, into fi->saved_regs, the addresses of
693 the saved registers of frame described by FRAME_INFO. This
694 includes special registers such as pc and fp saved in special ways
695 in the stack frame. sp is even more special: the address we return
696 for it IS the sp for the next frame. */
698 static struct cris_unwind_cache *
699 cris_frame_unwind_cache (struct frame_info *this_frame,
700 void **this_prologue_cache)
702 struct gdbarch *gdbarch = get_frame_arch (this_frame);
703 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
704 struct cris_unwind_cache *info;
706 if ((*this_prologue_cache))
707 return (struct cris_unwind_cache *) (*this_prologue_cache);
709 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
710 (*this_prologue_cache) = info;
711 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
713 /* Zero all fields. */
719 info->uses_frame = 0;
721 info->leaf_function = 0;
723 /* Prologue analysis does the rest... */
724 if (tdep->cris_version == 32)
725 crisv32_scan_prologue (get_frame_func (this_frame), this_frame, info);
727 cris_scan_prologue (get_frame_func (this_frame), this_frame, info);
732 /* Given a GDB frame, determine the address of the calling function's
733 frame. This will be used to create a new GDB frame struct. */
736 cris_frame_this_id (struct frame_info *this_frame,
737 void **this_prologue_cache,
738 struct frame_id *this_id)
740 struct cris_unwind_cache *info
741 = cris_frame_unwind_cache (this_frame, this_prologue_cache);
746 /* The FUNC is easy. */
747 func = get_frame_func (this_frame);
749 /* Hopefully the prologue analysis either correctly determined the
750 frame's base (which is the SP from the previous frame), or set
751 that base to "NULL". */
752 base = info->prev_sp;
756 id = frame_id_build (base, func);
761 static struct value *
762 cris_frame_prev_register (struct frame_info *this_frame,
763 void **this_prologue_cache, int regnum)
765 struct cris_unwind_cache *info
766 = cris_frame_unwind_cache (this_frame, this_prologue_cache);
767 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
770 /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
771 frame. The frame ID's base needs to match the TOS value saved by
772 save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */
774 static struct frame_id
775 cris_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
778 sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
779 return frame_id_build (sp, get_frame_pc (this_frame));
783 cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
785 /* Align to the size of an instruction (so that they can safely be
786 pushed onto the stack). */
791 cris_push_dummy_code (struct gdbarch *gdbarch,
792 CORE_ADDR sp, CORE_ADDR funaddr,
793 struct value **args, int nargs,
794 struct type *value_type,
795 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
796 struct regcache *regcache)
798 /* Allocate space sufficient for a breakpoint. */
800 /* Store the address of that breakpoint */
802 /* CRIS always starts the call at the callee's entry point. */
808 cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
809 struct regcache *regcache, CORE_ADDR bp_addr,
810 int nargs, struct value **args, CORE_ADDR sp,
811 int struct_return, CORE_ADDR struct_addr)
813 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
817 struct stack_item *si = NULL;
819 /* Push the return address. */
820 regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr);
822 /* Are we returning a value using a structure return or a normal value
823 return? struct_addr is the address of the reserved space for the return
824 structure to be written on the stack. */
827 regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr);
830 /* Now load as many as possible of the first arguments into registers,
831 and push the rest onto the stack. */
832 argreg = ARG1_REGNUM;
834 for (argnum = 0; argnum < nargs; argnum++)
841 len = TYPE_LENGTH (value_type (args[argnum]));
842 val = value_contents (args[argnum]);
844 /* How may registers worth of storage do we need for this argument? */
845 reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0);
847 if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM))
849 /* Data passed by value. Fits in available register(s). */
850 for (i = 0; i < reg_demand; i++)
852 regcache_cooked_write (regcache, argreg, val);
857 else if (len <= (2 * 4) && argreg <= ARG4_REGNUM)
859 /* Data passed by value. Does not fit in available register(s).
860 Use the register(s) first, then the stack. */
861 for (i = 0; i < reg_demand; i++)
863 if (argreg <= ARG4_REGNUM)
865 regcache_cooked_write (regcache, argreg, val);
871 /* Push item for later so that pushed arguments
872 come in the right order. */
873 si = push_stack_item (si, val, 4);
878 else if (len > (2 * 4))
880 /* Data passed by reference. Push copy of data onto stack
881 and pass pointer to this copy as argument. */
882 sp = (sp - len) & ~3;
883 write_memory (sp, val, len);
885 if (argreg <= ARG4_REGNUM)
887 regcache_cooked_write_unsigned (regcache, argreg, sp);
893 store_unsigned_integer (buf, 4, byte_order, sp);
894 si = push_stack_item (si, buf, 4);
899 /* Data passed by value. No available registers. Put it on
901 si = push_stack_item (si, val, len);
907 /* fp_arg must be word-aligned (i.e., don't += len) to match
908 the function prologue. */
909 sp = (sp - si->len) & ~3;
910 write_memory (sp, si->data, si->len);
911 si = pop_stack_item (si);
914 /* Finally, update the SP register. */
915 regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp);
920 static const struct frame_unwind cris_frame_unwind =
923 default_frame_unwind_stop_reason,
925 cris_frame_prev_register,
927 default_frame_sniffer
931 cris_frame_base_address (struct frame_info *this_frame, void **this_cache)
933 struct cris_unwind_cache *info
934 = cris_frame_unwind_cache (this_frame, this_cache);
938 static const struct frame_base cris_frame_base =
941 cris_frame_base_address,
942 cris_frame_base_address,
943 cris_frame_base_address
946 /* Frames information. The definition of the struct frame_info is
950 enum frame_type type;
954 If the compilation option -fno-omit-frame-pointer is present the
955 variable frame will be set to the content of R8 which is the frame
958 The variable pc contains the address where execution is performed
959 in the present frame. The innermost frame contains the current content
960 of the register PC. All other frames contain the content of the
961 register PC in the next frame.
963 The variable `type' indicates the frame's type: normal, SIGTRAMP
964 (associated with a signal handler), dummy (associated with a dummy
967 The variable return_pc contains the address where execution should be
968 resumed when the present frame has finished, the return address.
970 The variable leaf_function is 1 if the return address is in the register
971 SRP, and 0 if it is on the stack.
973 Prologue instructions C-code.
974 The prologue may consist of (-fno-omit-frame-pointer)
978 move.d sp,r8 move.d sp,r8
980 movem rY,[sp] movem rY,[sp]
981 move.S rZ,[r8-U] move.S rZ,[r8-U]
983 where 1 is a non-terminal function, and 2 is a leaf-function.
985 Note that this assumption is extremely brittle, and will break at the
986 slightest change in GCC's prologue.
988 If local variables are declared or register contents are saved on stack
989 the subq-instruction will be present with X as the number of bytes
990 needed for storage. The reshuffle with respect to r8 may be performed
991 with any size S (b, w, d) and any of the general registers Z={0..13}.
992 The offset U should be representable by a signed 8-bit value in all cases.
993 Thus, the prefix word is assumed to be immediate byte offset mode followed
994 by another word containing the instruction.
1003 Prologue instructions C++-code.
1004 Case 1) and 2) in the C-code may be followed by
1006 move.d r10,rS ; this
1010 move.S [r8+U],rZ ; P4
1012 if any of the call parameters are stored. The host expects these
1013 instructions to be executed in order to get the call parameters right. */
1015 /* Examine the prologue of a function. The variable ip is the address of
1016 the first instruction of the prologue. The variable limit is the address
1017 of the first instruction after the prologue. The variable fi contains the
1018 information in struct frame_info. The variable frameless_p controls whether
1019 the entire prologue is examined (0) or just enough instructions to
1020 determine that it is a prologue (1). */
1023 cris_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
1024 struct cris_unwind_cache *info)
1026 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1027 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1029 /* Present instruction. */
1030 unsigned short insn;
1032 /* Next instruction, lookahead. */
1033 unsigned short insn_next;
1036 /* Number of byte on stack used for local variables and movem. */
1039 /* Highest register number in a movem. */
1042 /* move.d r<source_register>,rS */
1043 short source_register;
1048 /* This frame is with respect to a leaf until a push srp is found. */
1051 info->leaf_function = 1;
1054 /* Assume nothing on stack. */
1058 /* If we were called without a this_frame, that means we were called
1059 from cris_skip_prologue which already tried to find the end of the
1060 prologue through the symbol information. 64 instructions past current
1061 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
1062 limit = this_frame ? get_frame_pc (this_frame) : pc + 64;
1064 /* Find the prologue instructions. */
1065 while (pc > 0 && pc < limit)
1067 insn = read_memory_unsigned_integer (pc, 2, byte_order);
1071 /* push <reg> 32 bit instruction. */
1072 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1074 regno = cris_get_operand2 (insn_next);
1077 info->sp_offset += 4;
1079 /* This check, meant to recognize srp, used to be regno ==
1080 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
1081 if (insn_next == 0xBE7E)
1085 info->leaf_function = 0;
1088 else if (insn_next == 0x8FEE)
1093 info->r8_offset = info->sp_offset;
1097 else if (insn == 0x866E)
1102 info->uses_frame = 1;
1106 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1107 && cris_get_mode (insn) == 0x0000
1108 && cris_get_opcode (insn) == 0x000A)
1113 info->sp_offset += cris_get_quick_value (insn);
1116 else if (cris_get_mode (insn) == 0x0002
1117 && cris_get_opcode (insn) == 0x000F
1118 && cris_get_size (insn) == 0x0003
1119 && cris_get_operand1 (insn) == gdbarch_sp_regnum (gdbarch))
1121 /* movem r<regsave>,[sp] */
1122 regsave = cris_get_operand2 (insn);
1124 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1125 && ((insn & 0x0F00) >> 8) == 0x0001
1126 && (cris_get_signed_offset (insn) < 0))
1128 /* Immediate byte offset addressing prefix word with sp as base
1129 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1130 is between 64 and 128.
1131 movem r<regsave>,[sp=sp-<val>] */
1134 info->sp_offset += -cris_get_signed_offset (insn);
1136 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1138 if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE
1139 && cris_get_opcode (insn_next) == 0x000F
1140 && cris_get_size (insn_next) == 0x0003
1141 && cris_get_operand1 (insn_next) == gdbarch_sp_regnum
1144 regsave = cris_get_operand2 (insn_next);
1148 /* The prologue ended before the limit was reached. */
1153 else if (cris_get_mode (insn) == 0x0001
1154 && cris_get_opcode (insn) == 0x0009
1155 && cris_get_size (insn) == 0x0002)
1157 /* move.d r<10..13>,r<0..15> */
1158 source_register = cris_get_operand1 (insn);
1160 /* FIXME? In the glibc solibs, the prologue might contain something
1161 like (this example taken from relocate_doit):
1163 sub.d 0xfffef426,$r0
1164 which isn't covered by the source_register check below. Question
1165 is whether to add a check for this combo, or make better use of
1166 the limit variable instead. */
1167 if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM)
1169 /* The prologue ended before the limit was reached. */
1174 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1175 /* The size is a fixed-size. */
1176 && ((insn & 0x0F00) >> 8) == 0x0001
1177 /* A negative offset. */
1178 && (cris_get_signed_offset (insn) < 0))
1180 /* move.S rZ,[r8-U] (?) */
1181 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1183 regno = cris_get_operand2 (insn_next);
1184 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1185 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1186 && cris_get_opcode (insn_next) == 0x000F)
1188 /* move.S rZ,[r8-U] */
1193 /* The prologue ended before the limit was reached. */
1198 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1199 /* The size is a fixed-size. */
1200 && ((insn & 0x0F00) >> 8) == 0x0001
1201 /* A positive offset. */
1202 && (cris_get_signed_offset (insn) > 0))
1204 /* move.S [r8+U],rZ (?) */
1205 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1207 regno = cris_get_operand2 (insn_next);
1208 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1209 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1210 && cris_get_opcode (insn_next) == 0x0009
1211 && cris_get_operand1 (insn_next) == regno)
1213 /* move.S [r8+U],rZ */
1218 /* The prologue ended before the limit was reached. */
1225 /* The prologue ended before the limit was reached. */
1231 /* We only want to know the end of the prologue when this_frame and info
1232 are NULL (called from cris_skip_prologue i.e.). */
1233 if (this_frame == NULL && info == NULL)
1238 info->size = info->sp_offset;
1240 /* Compute the previous frame's stack pointer (which is also the
1241 frame's ID's stack address), and this frame's base pointer. */
1242 if (info->uses_frame)
1245 /* The SP was moved to the FP. This indicates that a new frame
1246 was created. Get THIS frame's FP value by unwinding it from
1248 this_base = get_frame_register_unsigned (this_frame, CRIS_FP_REGNUM);
1249 info->base = this_base;
1250 info->saved_regs[CRIS_FP_REGNUM].addr = info->base;
1252 /* The FP points at the last saved register. Adjust the FP back
1253 to before the first saved register giving the SP. */
1254 info->prev_sp = info->base + info->r8_offset;
1259 /* Assume that the FP is this frame's SP but with that pushed
1260 stack space added back. */
1261 this_base = get_frame_register_unsigned (this_frame,
1262 gdbarch_sp_regnum (gdbarch));
1263 info->base = this_base;
1264 info->prev_sp = info->base + info->size;
1267 /* Calculate the addresses for the saved registers on the stack. */
1268 /* FIXME: The address calculation should really be done on the fly while
1269 we're analyzing the prologue (we only hold one regsave value as it is
1271 val = info->sp_offset;
1273 for (regno = regsave; regno >= 0; regno--)
1275 info->saved_regs[regno].addr = info->base + info->r8_offset - val;
1279 /* The previous frame's SP needed to be computed. Save the computed
1281 trad_frame_set_value (info->saved_regs,
1282 gdbarch_sp_regnum (gdbarch), info->prev_sp);
1284 if (!info->leaf_function)
1286 /* SRP saved on the stack. But where? */
1287 if (info->r8_offset == 0)
1289 /* R8 not pushed yet. */
1290 info->saved_regs[SRP_REGNUM].addr = info->base;
1294 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1295 info->saved_regs[SRP_REGNUM].addr = info->base + 4;
1299 /* The PC is found in SRP (the actual register or located on the stack). */
1300 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1301 = info->saved_regs[SRP_REGNUM];
1307 crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
1308 struct cris_unwind_cache *info)
1310 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1313 /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not
1314 meant to be a full-fledged prologue scanner. It is only needed for
1315 the cases where we end up in code always lacking DWARF-2 CFI, notably:
1317 * PLT stubs (library calls)
1319 * signal trampolines
1321 For those cases, it is assumed that there is no actual prologue; that
1322 the stack pointer is not adjusted, and (as a consequence) the return
1323 address is not pushed onto the stack. */
1325 /* We only want to know the end of the prologue when this_frame and info
1326 are NULL (called from cris_skip_prologue i.e.). */
1327 if (this_frame == NULL && info == NULL)
1332 /* The SP is assumed to be unaltered. */
1333 this_base = get_frame_register_unsigned (this_frame,
1334 gdbarch_sp_regnum (gdbarch));
1335 info->base = this_base;
1336 info->prev_sp = this_base;
1338 /* The PC is assumed to be found in SRP. */
1339 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1340 = info->saved_regs[SRP_REGNUM];
1345 /* Advance pc beyond any function entry prologue instructions at pc
1346 to reach some "real" code. */
1348 /* Given a PC value corresponding to the start of a function, return the PC
1349 of the first instruction after the function prologue. */
1352 cris_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1354 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1355 CORE_ADDR func_addr, func_end;
1356 struct symtab_and_line sal;
1357 CORE_ADDR pc_after_prologue;
1359 /* If we have line debugging information, then the end of the prologue
1360 should the first assembly instruction of the first source line. */
1361 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1363 sal = find_pc_line (func_addr, 0);
1364 if (sal.end > 0 && sal.end < func_end)
1368 if (tdep->cris_version == 32)
1369 pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL);
1371 pc_after_prologue = cris_scan_prologue (pc, NULL, NULL);
1373 return pc_after_prologue;
1377 cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1380 pc = frame_unwind_register_unsigned (next_frame,
1381 gdbarch_pc_regnum (gdbarch));
1386 cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1389 sp = frame_unwind_register_unsigned (next_frame,
1390 gdbarch_sp_regnum (gdbarch));
1394 /* Implement the breakpoint_kind_from_pc gdbarch method. */
1397 cris_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
1402 /* Implement the sw_breakpoint_from_kind gdbarch method. */
1404 static const gdb_byte *
1405 cris_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
1407 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1408 static unsigned char break8_insn[] = {0x38, 0xe9};
1409 static unsigned char break15_insn[] = {0x3f, 0xe9};
1413 if (tdep->cris_mode == cris_mode_guru)
1414 return break15_insn;
1419 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1423 cris_spec_reg_applicable (struct gdbarch *gdbarch,
1424 struct cris_spec_reg spec_reg)
1426 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1427 unsigned int version = tdep->cris_version;
1429 switch (spec_reg.applicable_version)
1431 case cris_ver_version_all:
1433 case cris_ver_warning:
1434 /* Indeterminate/obsolete. */
1437 return (version >= 0 && version <= 3);
1439 return (version >= 3);
1441 return (version == 8 || version == 9);
1443 return (version >= 8);
1444 case cris_ver_v0_10:
1445 return (version >= 0 && version <= 10);
1446 case cris_ver_v3_10:
1447 return (version >= 3 && version <= 10);
1448 case cris_ver_v8_10:
1449 return (version >= 8 && version <= 10);
1451 return (version == 10);
1453 return (version >= 10);
1455 return (version >= 32);
1457 /* Invalid cris version. */
1462 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1463 register, -1 for an invalid register. */
1466 cris_register_size (struct gdbarch *gdbarch, int regno)
1471 if (regno >= 0 && regno < NUM_GENREGS)
1473 /* General registers (R0 - R15) are 32 bits. */
1476 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1478 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1479 Adjust regno accordingly. */
1480 spec_regno = regno - NUM_GENREGS;
1482 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1484 if (cris_spec_regs[i].number == spec_regno
1485 && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i]))
1486 /* Go with the first applicable register. */
1487 return cris_spec_regs[i].reg_size;
1489 /* Special register not applicable to this CRIS version. */
1492 else if (regno >= gdbarch_pc_regnum (gdbarch)
1493 && regno < gdbarch_num_regs (gdbarch))
1495 /* This will apply to CRISv32 only where there are additional registers
1496 after the special registers (pseudo PC and support registers). */
1504 /* Nonzero if regno should not be fetched from the target. This is the case
1505 for unimplemented (size 0) and non-existant registers. */
1508 cris_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1510 return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1511 || (cris_register_size (gdbarch, regno) == 0));
1514 /* Nonzero if regno should not be written to the target, for various
1518 cris_cannot_store_register (struct gdbarch *gdbarch, int regno)
1520 /* There are three kinds of registers we refuse to write to.
1521 1. Those that not implemented.
1522 2. Those that are read-only (depends on the processor mode).
1523 3. Those registers to which a write has no effect. */
1526 || regno >= gdbarch_num_regs (gdbarch)
1527 || cris_register_size (gdbarch, regno) == 0)
1528 /* Not implemented. */
1531 else if (regno == VR_REGNUM)
1535 else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM)
1536 /* Writing has no effect. */
1539 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
1540 agent decide whether they are writable. */
1545 /* Nonzero if regno should not be fetched from the target. This is the case
1546 for unimplemented (size 0) and non-existant registers. */
1549 crisv32_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1551 return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1552 || (cris_register_size (gdbarch, regno) == 0));
1555 /* Nonzero if regno should not be written to the target, for various
1559 crisv32_cannot_store_register (struct gdbarch *gdbarch, int regno)
1561 /* There are three kinds of registers we refuse to write to.
1562 1. Those that not implemented.
1563 2. Those that are read-only (depends on the processor mode).
1564 3. Those registers to which a write has no effect. */
1567 || regno >= gdbarch_num_regs (gdbarch)
1568 || cris_register_size (gdbarch, regno) == 0)
1569 /* Not implemented. */
1572 else if (regno == VR_REGNUM)
1576 else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM)
1577 /* Writing has no effect. */
1580 /* Many special registers are read-only in user mode. Let the debug
1581 agent decide whether they are writable. */
1586 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1587 of data in register regno. */
1589 static struct type *
1590 cris_register_type (struct gdbarch *gdbarch, int regno)
1592 if (regno == gdbarch_pc_regnum (gdbarch))
1593 return builtin_type (gdbarch)->builtin_func_ptr;
1594 else if (regno == gdbarch_sp_regnum (gdbarch)
1595 || regno == CRIS_FP_REGNUM)
1596 return builtin_type (gdbarch)->builtin_data_ptr;
1597 else if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1598 || (regno >= MOF_REGNUM && regno <= USP_REGNUM))
1599 /* Note: R8 taken care of previous clause. */
1600 return builtin_type (gdbarch)->builtin_uint32;
1601 else if (regno >= P4_REGNUM && regno <= CCR_REGNUM)
1602 return builtin_type (gdbarch)->builtin_uint16;
1603 else if (regno >= P0_REGNUM && regno <= VR_REGNUM)
1604 return builtin_type (gdbarch)->builtin_uint8;
1606 /* Invalid (unimplemented) register. */
1607 return builtin_type (gdbarch)->builtin_int0;
1610 static struct type *
1611 crisv32_register_type (struct gdbarch *gdbarch, int regno)
1613 if (regno == gdbarch_pc_regnum (gdbarch))
1614 return builtin_type (gdbarch)->builtin_func_ptr;
1615 else if (regno == gdbarch_sp_regnum (gdbarch)
1616 || regno == CRIS_FP_REGNUM)
1617 return builtin_type (gdbarch)->builtin_data_ptr;
1618 else if ((regno >= 0 && regno <= ACR_REGNUM)
1619 || (regno >= EXS_REGNUM && regno <= SPC_REGNUM)
1620 || (regno == PID_REGNUM)
1621 || (regno >= S0_REGNUM && regno <= S15_REGNUM))
1622 /* Note: R8 and SP taken care of by previous clause. */
1623 return builtin_type (gdbarch)->builtin_uint32;
1624 else if (regno == WZ_REGNUM)
1625 return builtin_type (gdbarch)->builtin_uint16;
1626 else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM)
1627 return builtin_type (gdbarch)->builtin_uint8;
1630 /* Invalid (unimplemented) register. Should not happen as there are
1631 no unimplemented CRISv32 registers. */
1632 warning (_("crisv32_register_type: unknown regno %d"), regno);
1633 return builtin_type (gdbarch)->builtin_int0;
1637 /* Stores a function return value of type type, where valbuf is the address
1638 of the value to be stored. */
1640 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1643 cris_store_return_value (struct type *type, struct regcache *regcache,
1644 const gdb_byte *valbuf)
1646 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1647 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1649 int len = TYPE_LENGTH (type);
1653 /* Put the return value in R10. */
1654 val = extract_unsigned_integer (valbuf, len, byte_order);
1655 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1659 /* Put the return value in R10 and R11. */
1660 val = extract_unsigned_integer (valbuf, 4, byte_order);
1661 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1662 val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order);
1663 regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val);
1666 error (_("cris_store_return_value: type length too large."));
1669 /* Return the name of register regno as a string. Return NULL for an
1670 invalid or unimplemented register. */
1673 cris_special_register_name (struct gdbarch *gdbarch, int regno)
1678 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1679 Adjust regno accordingly. */
1680 spec_regno = regno - NUM_GENREGS;
1682 /* Assume nothing about the layout of the cris_spec_regs struct
1684 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1686 if (cris_spec_regs[i].number == spec_regno
1687 && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i]))
1688 /* Go with the first applicable register. */
1689 return cris_spec_regs[i].name;
1691 /* Special register not applicable to this CRIS version. */
1696 cris_register_name (struct gdbarch *gdbarch, int regno)
1698 static char *cris_genreg_names[] =
1699 { "r0", "r1", "r2", "r3", \
1700 "r4", "r5", "r6", "r7", \
1701 "r8", "r9", "r10", "r11", \
1702 "r12", "r13", "sp", "pc" };
1704 if (regno >= 0 && regno < NUM_GENREGS)
1706 /* General register. */
1707 return cris_genreg_names[regno];
1709 else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (gdbarch))
1711 return cris_special_register_name (gdbarch, regno);
1715 /* Invalid register. */
1721 crisv32_register_name (struct gdbarch *gdbarch, int regno)
1723 static char *crisv32_genreg_names[] =
1724 { "r0", "r1", "r2", "r3", \
1725 "r4", "r5", "r6", "r7", \
1726 "r8", "r9", "r10", "r11", \
1727 "r12", "r13", "sp", "acr"
1730 static char *crisv32_sreg_names[] =
1731 { "s0", "s1", "s2", "s3", \
1732 "s4", "s5", "s6", "s7", \
1733 "s8", "s9", "s10", "s11", \
1734 "s12", "s13", "s14", "s15"
1737 if (regno >= 0 && regno < NUM_GENREGS)
1739 /* General register. */
1740 return crisv32_genreg_names[regno];
1742 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1744 return cris_special_register_name (gdbarch, regno);
1746 else if (regno == gdbarch_pc_regnum (gdbarch))
1750 else if (regno >= S0_REGNUM && regno <= S15_REGNUM)
1752 return crisv32_sreg_names[regno - S0_REGNUM];
1756 /* Invalid register. */
1761 /* Convert DWARF register number REG to the appropriate register
1762 number used by GDB. */
1765 cris_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1767 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1768 numbering, MOF is 18).
1769 Adapted from gcc/config/cris/cris.h. */
1770 static int cris_dwarf_regmap[] = {
1782 if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap))
1783 regnum = cris_dwarf_regmap[reg];
1788 /* DWARF-2 frame support. */
1791 cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1792 struct dwarf2_frame_state_reg *reg,
1793 struct frame_info *this_frame)
1795 /* The return address column. */
1796 if (regnum == gdbarch_pc_regnum (gdbarch))
1797 reg->how = DWARF2_FRAME_REG_RA;
1799 /* The call frame address. */
1800 else if (regnum == gdbarch_sp_regnum (gdbarch))
1801 reg->how = DWARF2_FRAME_REG_CFA;
1804 /* Extract from an array regbuf containing the raw register state a function
1805 return value of type type, and copy that, in virtual format, into
1808 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1811 cris_extract_return_value (struct type *type, struct regcache *regcache,
1814 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1815 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1817 int len = TYPE_LENGTH (type);
1821 /* Get the return value from R10. */
1822 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1823 store_unsigned_integer (valbuf, len, byte_order, val);
1827 /* Get the return value from R10 and R11. */
1828 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1829 store_unsigned_integer (valbuf, 4, byte_order, val);
1830 regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val);
1831 store_unsigned_integer (valbuf + 4, len - 4, byte_order, val);
1834 error (_("cris_extract_return_value: type length too large"));
1837 /* Handle the CRIS return value convention. */
1839 static enum return_value_convention
1840 cris_return_value (struct gdbarch *gdbarch, struct value *function,
1841 struct type *type, struct regcache *regcache,
1842 gdb_byte *readbuf, const gdb_byte *writebuf)
1844 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1845 || TYPE_CODE (type) == TYPE_CODE_UNION
1846 || TYPE_LENGTH (type) > 8)
1847 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1848 goes on the stack. */
1849 return RETURN_VALUE_STRUCT_CONVENTION;
1852 cris_extract_return_value (type, regcache, readbuf);
1854 cris_store_return_value (type, regcache, writebuf);
1856 return RETURN_VALUE_REGISTER_CONVENTION;
1859 /* Calculates a value that measures how good inst_args constraints an
1860 instruction. It stems from cris_constraint, found in cris-dis.c. */
1863 constraint (unsigned int insn, const char *inst_args,
1864 inst_env_type *inst_env)
1869 const gdb_byte *s = (const gdb_byte *) inst_args;
1875 if ((insn & 0x30) == 0x30)
1880 /* A prefix operand. */
1881 if (inst_env->prefix_found)
1887 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1888 valid "push" size. In case of special register, it may be != 4. */
1889 if (inst_env->prefix_found)
1895 retval = (((insn >> 0xC) & 0xF) == (insn & 0xF));
1903 tmp = (insn >> 0xC) & 0xF;
1905 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1907 /* Since we match four bits, we will give a value of
1908 4 - 1 = 3 in a match. If there is a corresponding
1909 exact match of a special register in another pattern, it
1910 will get a value of 4, which will be higher. This should
1911 be correct in that an exact pattern would match better that
1913 Note that there is a reason for not returning zero; the
1914 pattern for "clear" is partly matched in the bit-pattern
1915 (the two lower bits must be zero), while the bit-pattern
1916 for a move from a special register is matched in the
1917 register constraint.
1918 This also means we will will have a race condition if
1919 there is a partly match in three bits in the bit pattern. */
1920 if (tmp == cris_spec_regs[i].number)
1927 if (cris_spec_regs[i].name == NULL)
1934 /* Returns the number of bits set in the variable value. */
1937 number_of_bits (unsigned int value)
1939 int number_of_bits = 0;
1943 number_of_bits += 1;
1944 value &= (value - 1);
1946 return number_of_bits;
1949 /* Finds the address that should contain the single step breakpoint(s).
1950 It stems from code in cris-dis.c. */
1953 find_cris_op (unsigned short insn, inst_env_type *inst_env)
1956 int max_level_of_match = -1;
1957 int max_matched = -1;
1960 for (i = 0; cris_opcodes[i].name != NULL; i++)
1962 if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match)
1963 && ((cris_opcodes[i].lose & insn) == 0)
1964 /* Only CRISv10 instructions, please. */
1965 && (cris_opcodes[i].applicable_version != cris_ver_v32p))
1967 level_of_match = constraint (insn, cris_opcodes[i].args, inst_env);
1968 if (level_of_match >= 0)
1971 number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose);
1972 if (level_of_match > max_level_of_match)
1975 max_level_of_match = level_of_match;
1976 if (level_of_match == 16)
1978 /* All bits matched, cannot find better. */
1988 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
1989 actually an internal error. */
1992 find_step_target (struct regcache *regcache, inst_env_type *inst_env)
1996 unsigned short insn;
1997 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1998 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2000 /* Create a local register image and set the initial state. */
2001 for (i = 0; i < NUM_GENREGS; i++)
2004 (unsigned long) regcache_raw_get_unsigned (regcache, i);
2006 offset = NUM_GENREGS;
2007 for (i = 0; i < NUM_SPECREGS; i++)
2010 (unsigned long) regcache_raw_get_unsigned (regcache, offset + i);
2012 inst_env->branch_found = 0;
2013 inst_env->slot_needed = 0;
2014 inst_env->delay_slot_pc_active = 0;
2015 inst_env->prefix_found = 0;
2016 inst_env->invalid = 0;
2017 inst_env->xflag_found = 0;
2018 inst_env->disable_interrupt = 0;
2019 inst_env->byte_order = byte_order;
2021 /* Look for a step target. */
2024 /* Read an instruction from the client. */
2025 insn = read_memory_unsigned_integer
2026 (inst_env->reg[gdbarch_pc_regnum (gdbarch)], 2, byte_order);
2028 /* If the instruction is not in a delay slot the new content of the
2029 PC is [PC] + 2. If the instruction is in a delay slot it is not
2030 that simple. Since a instruction in a delay slot cannot change
2031 the content of the PC, it does not matter what value PC will have.
2032 Just make sure it is a valid instruction. */
2033 if (!inst_env->delay_slot_pc_active)
2035 inst_env->reg[gdbarch_pc_regnum (gdbarch)] += 2;
2039 inst_env->delay_slot_pc_active = 0;
2040 inst_env->reg[gdbarch_pc_regnum (gdbarch)]
2041 = inst_env->delay_slot_pc;
2043 /* Analyse the present instruction. */
2044 i = find_cris_op (insn, inst_env);
2047 inst_env->invalid = 1;
2051 cris_gdb_func (gdbarch, cris_opcodes[i].op, insn, inst_env);
2053 } while (!inst_env->invalid
2054 && (inst_env->prefix_found || inst_env->xflag_found
2055 || inst_env->slot_needed));
2059 /* There is no hardware single-step support. The function find_step_target
2060 digs through the opcodes in order to find all possible targets.
2061 Either one ordinary target or two targets for branches may be found. */
2063 static VEC (CORE_ADDR) *
2064 cris_software_single_step (struct regcache *regcache)
2066 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2067 inst_env_type inst_env;
2068 VEC (CORE_ADDR) *next_pcs = NULL;
2070 /* Analyse the present instruction environment and insert
2072 int status = find_step_target (regcache, &inst_env);
2075 /* Could not find a target. Things are likely to go downhill
2077 warning (_("CRIS software single step could not find a step target."));
2081 /* Insert at most two breakpoints. One for the next PC content
2082 and possibly another one for a branch, jump, etc. */
2084 = (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (gdbarch)];
2086 VEC_safe_push (CORE_ADDR, next_pcs, next_pc);
2087 if (inst_env.branch_found
2088 && (CORE_ADDR) inst_env.branch_break_address != next_pc)
2090 CORE_ADDR branch_target_address
2091 = (CORE_ADDR) inst_env.branch_break_address;
2093 VEC_safe_push (CORE_ADDR, next_pcs, branch_target_address);
2100 /* Calculates the prefix value for quick offset addressing mode. */
2103 quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2105 /* It's invalid to be in a delay slot. You can't have a prefix to this
2106 instruction (not 100% sure). */
2107 if (inst_env->slot_needed || inst_env->prefix_found)
2109 inst_env->invalid = 1;
2113 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2114 inst_env->prefix_value += cris_get_bdap_quick_offset (inst);
2116 /* A prefix doesn't change the xflag_found. But the rest of the flags
2118 inst_env->slot_needed = 0;
2119 inst_env->prefix_found = 1;
2122 /* Updates the autoincrement register. The size of the increment is derived
2123 from the size of the operation. The PC is always kept aligned on even
2127 process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env)
2129 if (size == INST_BYTE_SIZE)
2131 inst_env->reg[cris_get_operand1 (inst)] += 1;
2133 /* The PC must be word aligned, so increase the PC with one
2134 word even if the size is byte. */
2135 if (cris_get_operand1 (inst) == REG_PC)
2137 inst_env->reg[REG_PC] += 1;
2140 else if (size == INST_WORD_SIZE)
2142 inst_env->reg[cris_get_operand1 (inst)] += 2;
2144 else if (size == INST_DWORD_SIZE)
2146 inst_env->reg[cris_get_operand1 (inst)] += 4;
2151 inst_env->invalid = 1;
2155 /* Just a forward declaration. */
2157 static unsigned long get_data_from_address (unsigned short *inst,
2159 enum bfd_endian byte_order);
2161 /* Calculates the prefix value for the general case of offset addressing
2165 bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2167 /* It's invalid to be in a delay slot. */
2168 if (inst_env->slot_needed || inst_env->prefix_found)
2170 inst_env->invalid = 1;
2174 /* The calculation of prefix_value used to be after process_autoincrement,
2175 but that fails for an instruction such as jsr [$r0+12] which is encoded
2176 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
2177 mustn't be incremented until we have read it and what it points at. */
2178 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2180 /* The offset is an indirection of the contents of the operand1 register. */
2181 inst_env->prefix_value +=
2182 get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)],
2183 inst_env->byte_order);
2185 if (cris_get_mode (inst) == AUTOINC_MODE)
2187 process_autoincrement (cris_get_size (inst), inst, inst_env);
2190 /* A prefix doesn't change the xflag_found. But the rest of the flags
2192 inst_env->slot_needed = 0;
2193 inst_env->prefix_found = 1;
2196 /* Calculates the prefix value for the index addressing mode. */
2199 biap_prefix (unsigned short inst, inst_env_type *inst_env)
2201 /* It's invalid to be in a delay slot. I can't see that it's possible to
2202 have a prefix to this instruction. So I will treat this as invalid. */
2203 if (inst_env->slot_needed || inst_env->prefix_found)
2205 inst_env->invalid = 1;
2209 inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)];
2211 /* The offset is the operand2 value shifted the size of the instruction
2213 inst_env->prefix_value +=
2214 inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst);
2216 /* If the PC is operand1 (base) the address used is the address after
2217 the main instruction, i.e. address + 2 (the PC is already compensated
2218 for the prefix operation). */
2219 if (cris_get_operand1 (inst) == REG_PC)
2221 inst_env->prefix_value += 2;
2224 /* A prefix doesn't change the xflag_found. But the rest of the flags
2226 inst_env->slot_needed = 0;
2227 inst_env->xflag_found = 0;
2228 inst_env->prefix_found = 1;
2231 /* Calculates the prefix value for the double indirect addressing mode. */
2234 dip_prefix (unsigned short inst, inst_env_type *inst_env)
2239 /* It's invalid to be in a delay slot. */
2240 if (inst_env->slot_needed || inst_env->prefix_found)
2242 inst_env->invalid = 1;
2246 /* The prefix value is one dereference of the contents of the operand1
2248 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2249 inst_env->prefix_value
2250 = read_memory_unsigned_integer (address, 4, inst_env->byte_order);
2252 /* Check if the mode is autoincrement. */
2253 if (cris_get_mode (inst) == AUTOINC_MODE)
2255 inst_env->reg[cris_get_operand1 (inst)] += 4;
2258 /* A prefix doesn't change the xflag_found. But the rest of the flags
2260 inst_env->slot_needed = 0;
2261 inst_env->xflag_found = 0;
2262 inst_env->prefix_found = 1;
2265 /* Finds the destination for a branch with 8-bits offset. */
2268 eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2273 /* If we have a prefix or are in a delay slot it's bad. */
2274 if (inst_env->slot_needed || inst_env->prefix_found)
2276 inst_env->invalid = 1;
2280 /* We have a branch, find out where the branch will land. */
2281 offset = cris_get_branch_short_offset (inst);
2283 /* Check if the offset is signed. */
2284 if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK)
2289 /* The offset ends with the sign bit, set it to zero. The address
2290 should always be word aligned. */
2291 offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK;
2293 inst_env->branch_found = 1;
2294 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2296 inst_env->slot_needed = 1;
2297 inst_env->prefix_found = 0;
2298 inst_env->xflag_found = 0;
2299 inst_env->disable_interrupt = 1;
2302 /* Finds the destination for a branch with 16-bits offset. */
2305 sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2309 /* If we have a prefix or is in a delay slot it's bad. */
2310 if (inst_env->slot_needed || inst_env->prefix_found)
2312 inst_env->invalid = 1;
2316 /* We have a branch, find out the offset for the branch. */
2317 offset = read_memory_integer (inst_env->reg[REG_PC], 2,
2318 inst_env->byte_order);
2320 /* The instruction is one word longer than normal, so add one word
2322 inst_env->reg[REG_PC] += 2;
2324 inst_env->branch_found = 1;
2325 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2328 inst_env->slot_needed = 1;
2329 inst_env->prefix_found = 0;
2330 inst_env->xflag_found = 0;
2331 inst_env->disable_interrupt = 1;
2334 /* Handles the ABS instruction. */
2337 abs_op (unsigned short inst, inst_env_type *inst_env)
2342 /* ABS can't have a prefix, so it's bad if it does. */
2343 if (inst_env->prefix_found)
2345 inst_env->invalid = 1;
2349 /* Check if the operation affects the PC. */
2350 if (cris_get_operand2 (inst) == REG_PC)
2353 /* It's invalid to change to the PC if we are in a delay slot. */
2354 if (inst_env->slot_needed)
2356 inst_env->invalid = 1;
2360 value = (long) inst_env->reg[REG_PC];
2362 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
2363 if (value != SIGNED_DWORD_MASK)
2366 inst_env->reg[REG_PC] = (long) value;
2370 inst_env->slot_needed = 0;
2371 inst_env->prefix_found = 0;
2372 inst_env->xflag_found = 0;
2373 inst_env->disable_interrupt = 0;
2376 /* Handles the ADDI instruction. */
2379 addi_op (unsigned short inst, inst_env_type *inst_env)
2381 /* It's invalid to have the PC as base register. And ADDI can't have
2383 if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC))
2385 inst_env->invalid = 1;
2389 inst_env->slot_needed = 0;
2390 inst_env->prefix_found = 0;
2391 inst_env->xflag_found = 0;
2392 inst_env->disable_interrupt = 0;
2395 /* Handles the ASR instruction. */
2398 asr_op (unsigned short inst, inst_env_type *inst_env)
2401 unsigned long value;
2402 unsigned long signed_extend_mask = 0;
2404 /* ASR can't have a prefix, so check that it doesn't. */
2405 if (inst_env->prefix_found)
2407 inst_env->invalid = 1;
2411 /* Check if the PC is the target register. */
2412 if (cris_get_operand2 (inst) == REG_PC)
2414 /* It's invalid to change the PC in a delay slot. */
2415 if (inst_env->slot_needed)
2417 inst_env->invalid = 1;
2420 /* Get the number of bits to shift. */
2422 = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]);
2423 value = inst_env->reg[REG_PC];
2425 /* Find out how many bits the operation should apply to. */
2426 if (cris_get_size (inst) == INST_BYTE_SIZE)
2428 if (value & SIGNED_BYTE_MASK)
2430 signed_extend_mask = 0xFF;
2431 signed_extend_mask = signed_extend_mask >> shift_steps;
2432 signed_extend_mask = ~signed_extend_mask;
2434 value = value >> shift_steps;
2435 value |= signed_extend_mask;
2437 inst_env->reg[REG_PC] &= 0xFFFFFF00;
2438 inst_env->reg[REG_PC] |= value;
2440 else if (cris_get_size (inst) == INST_WORD_SIZE)
2442 if (value & SIGNED_WORD_MASK)
2444 signed_extend_mask = 0xFFFF;
2445 signed_extend_mask = signed_extend_mask >> shift_steps;
2446 signed_extend_mask = ~signed_extend_mask;
2448 value = value >> shift_steps;
2449 value |= signed_extend_mask;
2451 inst_env->reg[REG_PC] &= 0xFFFF0000;
2452 inst_env->reg[REG_PC] |= value;
2454 else if (cris_get_size (inst) == INST_DWORD_SIZE)
2456 if (value & SIGNED_DWORD_MASK)
2458 signed_extend_mask = 0xFFFFFFFF;
2459 signed_extend_mask = signed_extend_mask >> shift_steps;
2460 signed_extend_mask = ~signed_extend_mask;
2462 value = value >> shift_steps;
2463 value |= signed_extend_mask;
2464 inst_env->reg[REG_PC] = value;
2467 inst_env->slot_needed = 0;
2468 inst_env->prefix_found = 0;
2469 inst_env->xflag_found = 0;
2470 inst_env->disable_interrupt = 0;
2473 /* Handles the ASRQ instruction. */
2476 asrq_op (unsigned short inst, inst_env_type *inst_env)
2480 unsigned long value;
2481 unsigned long signed_extend_mask = 0;
2483 /* ASRQ can't have a prefix, so check that it doesn't. */
2484 if (inst_env->prefix_found)
2486 inst_env->invalid = 1;
2490 /* Check if the PC is the target register. */
2491 if (cris_get_operand2 (inst) == REG_PC)
2494 /* It's invalid to change the PC in a delay slot. */
2495 if (inst_env->slot_needed)
2497 inst_env->invalid = 1;
2500 /* The shift size is given as a 5 bit quick value, i.e. we don't
2501 want the sign bit of the quick value. */
2502 shift_steps = cris_get_asr_shift_steps (inst);
2503 value = inst_env->reg[REG_PC];
2504 if (value & SIGNED_DWORD_MASK)
2506 signed_extend_mask = 0xFFFFFFFF;
2507 signed_extend_mask = signed_extend_mask >> shift_steps;
2508 signed_extend_mask = ~signed_extend_mask;
2510 value = value >> shift_steps;
2511 value |= signed_extend_mask;
2512 inst_env->reg[REG_PC] = value;
2514 inst_env->slot_needed = 0;
2515 inst_env->prefix_found = 0;
2516 inst_env->xflag_found = 0;
2517 inst_env->disable_interrupt = 0;
2520 /* Handles the AX, EI and SETF instruction. */
2523 ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env)
2525 if (inst_env->prefix_found)
2527 inst_env->invalid = 1;
2530 /* Check if the instruction is setting the X flag. */
2531 if (cris_is_xflag_bit_on (inst))
2533 inst_env->xflag_found = 1;
2537 inst_env->xflag_found = 0;
2539 inst_env->slot_needed = 0;
2540 inst_env->prefix_found = 0;
2541 inst_env->disable_interrupt = 1;
2544 /* Checks if the instruction is in assign mode. If so, it updates the assign
2545 register. Note that check_assign assumes that the caller has checked that
2546 there is a prefix to this instruction. The mode check depends on this. */
2549 check_assign (unsigned short inst, inst_env_type *inst_env)
2551 /* Check if it's an assign addressing mode. */
2552 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2554 /* Assign the prefix value to operand 1. */
2555 inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value;
2559 /* Handles the 2-operand BOUND instruction. */
2562 two_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2564 /* It's invalid to have the PC as the index operand. */
2565 if (cris_get_operand2 (inst) == REG_PC)
2567 inst_env->invalid = 1;
2570 /* Check if we have a prefix. */
2571 if (inst_env->prefix_found)
2573 check_assign (inst, inst_env);
2575 /* Check if this is an autoincrement mode. */
2576 else if (cris_get_mode (inst) == AUTOINC_MODE)
2578 /* It's invalid to change the PC in a delay slot. */
2579 if (inst_env->slot_needed)
2581 inst_env->invalid = 1;
2584 process_autoincrement (cris_get_size (inst), inst, inst_env);
2586 inst_env->slot_needed = 0;
2587 inst_env->prefix_found = 0;
2588 inst_env->xflag_found = 0;
2589 inst_env->disable_interrupt = 0;
2592 /* Handles the 3-operand BOUND instruction. */
2595 three_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2597 /* It's an error if we haven't got a prefix. And it's also an error
2598 if the PC is the destination register. */
2599 if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC))
2601 inst_env->invalid = 1;
2604 inst_env->slot_needed = 0;
2605 inst_env->prefix_found = 0;
2606 inst_env->xflag_found = 0;
2607 inst_env->disable_interrupt = 0;
2610 /* Clears the status flags in inst_env. */
2613 btst_nop_op (unsigned short inst, inst_env_type *inst_env)
2615 /* It's an error if we have got a prefix. */
2616 if (inst_env->prefix_found)
2618 inst_env->invalid = 1;
2622 inst_env->slot_needed = 0;
2623 inst_env->prefix_found = 0;
2624 inst_env->xflag_found = 0;
2625 inst_env->disable_interrupt = 0;
2628 /* Clears the status flags in inst_env. */
2631 clearf_di_op (unsigned short inst, inst_env_type *inst_env)
2633 /* It's an error if we have got a prefix. */
2634 if (inst_env->prefix_found)
2636 inst_env->invalid = 1;
2640 inst_env->slot_needed = 0;
2641 inst_env->prefix_found = 0;
2642 inst_env->xflag_found = 0;
2643 inst_env->disable_interrupt = 1;
2646 /* Handles the CLEAR instruction if it's in register mode. */
2649 reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env)
2651 /* Check if the target is the PC. */
2652 if (cris_get_operand2 (inst) == REG_PC)
2654 /* The instruction will clear the instruction's size bits. */
2655 int clear_size = cris_get_clear_size (inst);
2656 if (clear_size == INST_BYTE_SIZE)
2658 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00;
2660 if (clear_size == INST_WORD_SIZE)
2662 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000;
2664 if (clear_size == INST_DWORD_SIZE)
2666 inst_env->delay_slot_pc = 0x0;
2668 /* The jump will be delayed with one delay slot. So we need a delay
2670 inst_env->slot_needed = 1;
2671 inst_env->delay_slot_pc_active = 1;
2675 /* The PC will not change => no delay slot. */
2676 inst_env->slot_needed = 0;
2678 inst_env->prefix_found = 0;
2679 inst_env->xflag_found = 0;
2680 inst_env->disable_interrupt = 0;
2683 /* Handles the TEST instruction if it's in register mode. */
2686 reg_mode_test_op (unsigned short inst, inst_env_type *inst_env)
2688 /* It's an error if we have got a prefix. */
2689 if (inst_env->prefix_found)
2691 inst_env->invalid = 1;
2694 inst_env->slot_needed = 0;
2695 inst_env->prefix_found = 0;
2696 inst_env->xflag_found = 0;
2697 inst_env->disable_interrupt = 0;
2701 /* Handles the CLEAR and TEST instruction if the instruction isn't
2702 in register mode. */
2705 none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env)
2707 /* Check if we are in a prefix mode. */
2708 if (inst_env->prefix_found)
2710 /* The only way the PC can change is if this instruction is in
2711 assign addressing mode. */
2712 check_assign (inst, inst_env);
2714 /* Indirect mode can't change the PC so just check if the mode is
2716 else if (cris_get_mode (inst) == AUTOINC_MODE)
2718 process_autoincrement (cris_get_size (inst), inst, inst_env);
2720 inst_env->slot_needed = 0;
2721 inst_env->prefix_found = 0;
2722 inst_env->xflag_found = 0;
2723 inst_env->disable_interrupt = 0;
2726 /* Checks that the PC isn't the destination register or the instructions has
2730 dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env)
2732 /* It's invalid to have the PC as the destination. The instruction can't
2734 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2736 inst_env->invalid = 1;
2740 inst_env->slot_needed = 0;
2741 inst_env->prefix_found = 0;
2742 inst_env->xflag_found = 0;
2743 inst_env->disable_interrupt = 0;
2746 /* Checks that the instruction doesn't have a prefix. */
2749 break_op (unsigned short inst, inst_env_type *inst_env)
2751 /* The instruction can't have a prefix. */
2752 if (inst_env->prefix_found)
2754 inst_env->invalid = 1;
2758 inst_env->slot_needed = 0;
2759 inst_env->prefix_found = 0;
2760 inst_env->xflag_found = 0;
2761 inst_env->disable_interrupt = 1;
2764 /* Checks that the PC isn't the destination register and that the instruction
2765 doesn't have a prefix. */
2768 scc_op (unsigned short inst, inst_env_type *inst_env)
2770 /* It's invalid to have the PC as the destination. The instruction can't
2772 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2774 inst_env->invalid = 1;
2778 inst_env->slot_needed = 0;
2779 inst_env->prefix_found = 0;
2780 inst_env->xflag_found = 0;
2781 inst_env->disable_interrupt = 1;
2784 /* Handles the register mode JUMP instruction. */
2787 reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2789 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2790 you can't have a prefix. */
2791 if ((inst_env->slot_needed) || (inst_env->prefix_found))
2793 inst_env->invalid = 1;
2797 /* Just change the PC. */
2798 inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)];
2799 inst_env->slot_needed = 0;
2800 inst_env->prefix_found = 0;
2801 inst_env->xflag_found = 0;
2802 inst_env->disable_interrupt = 1;
2805 /* Handles the JUMP instruction for all modes except register. */
2808 none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2810 unsigned long newpc;
2813 /* It's invalid to do a JUMP in a delay slot. */
2814 if (inst_env->slot_needed)
2816 inst_env->invalid = 1;
2820 /* Check if we have a prefix. */
2821 if (inst_env->prefix_found)
2823 check_assign (inst, inst_env);
2825 /* Get the new value for the PC. */
2827 read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value,
2828 4, inst_env->byte_order);
2832 /* Get the new value for the PC. */
2833 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2834 newpc = read_memory_unsigned_integer (address,
2835 4, inst_env->byte_order);
2837 /* Check if we should increment a register. */
2838 if (cris_get_mode (inst) == AUTOINC_MODE)
2840 inst_env->reg[cris_get_operand1 (inst)] += 4;
2843 inst_env->reg[REG_PC] = newpc;
2845 inst_env->slot_needed = 0;
2846 inst_env->prefix_found = 0;
2847 inst_env->xflag_found = 0;
2848 inst_env->disable_interrupt = 1;
2851 /* Handles moves to special registers (aka P-register) for all modes. */
2854 move_to_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2855 inst_env_type *inst_env)
2857 if (inst_env->prefix_found)
2859 /* The instruction has a prefix that means we are only interested if
2860 the instruction is in assign mode. */
2861 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2863 /* The prefix handles the problem if we are in a delay slot. */
2864 if (cris_get_operand1 (inst) == REG_PC)
2866 /* Just take care of the assign. */
2867 check_assign (inst, inst_env);
2871 else if (cris_get_mode (inst) == AUTOINC_MODE)
2873 /* The instruction doesn't have a prefix, the only case left that we
2874 are interested in is the autoincrement mode. */
2875 if (cris_get_operand1 (inst) == REG_PC)
2877 /* If the PC is to be incremented it's invalid to be in a
2879 if (inst_env->slot_needed)
2881 inst_env->invalid = 1;
2885 /* The increment depends on the size of the special register. */
2886 if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
2888 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2890 else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
2892 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2896 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2900 inst_env->slot_needed = 0;
2901 inst_env->prefix_found = 0;
2902 inst_env->xflag_found = 0;
2903 inst_env->disable_interrupt = 1;
2906 /* Handles moves from special registers (aka P-register) for all modes
2910 none_reg_mode_move_from_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2911 inst_env_type *inst_env)
2913 if (inst_env->prefix_found)
2915 /* The instruction has a prefix that means we are only interested if
2916 the instruction is in assign mode. */
2917 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2919 /* The prefix handles the problem if we are in a delay slot. */
2920 if (cris_get_operand1 (inst) == REG_PC)
2922 /* Just take care of the assign. */
2923 check_assign (inst, inst_env);
2927 /* The instruction doesn't have a prefix, the only case left that we
2928 are interested in is the autoincrement mode. */
2929 else if (cris_get_mode (inst) == AUTOINC_MODE)
2931 if (cris_get_operand1 (inst) == REG_PC)
2933 /* If the PC is to be incremented it's invalid to be in a
2935 if (inst_env->slot_needed)
2937 inst_env->invalid = 1;
2941 /* The increment depends on the size of the special register. */
2942 if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
2944 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2946 else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
2948 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2952 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2956 inst_env->slot_needed = 0;
2957 inst_env->prefix_found = 0;
2958 inst_env->xflag_found = 0;
2959 inst_env->disable_interrupt = 1;
2962 /* Handles moves from special registers (aka P-register) when the mode
2966 reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env)
2968 /* Register mode move from special register can't have a prefix. */
2969 if (inst_env->prefix_found)
2971 inst_env->invalid = 1;
2975 if (cris_get_operand1 (inst) == REG_PC)
2977 /* It's invalid to change the PC in a delay slot. */
2978 if (inst_env->slot_needed)
2980 inst_env->invalid = 1;
2983 /* The destination is the PC, the jump will have a delay slot. */
2984 inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)];
2985 inst_env->slot_needed = 1;
2986 inst_env->delay_slot_pc_active = 1;
2990 /* If the destination isn't PC, there will be no jump. */
2991 inst_env->slot_needed = 0;
2993 inst_env->prefix_found = 0;
2994 inst_env->xflag_found = 0;
2995 inst_env->disable_interrupt = 1;
2998 /* Handles the MOVEM from memory to general register instruction. */
3001 move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env)
3003 if (inst_env->prefix_found)
3005 /* The prefix handles the problem if we are in a delay slot. Is the
3006 MOVEM instruction going to change the PC? */
3007 if (cris_get_operand2 (inst) >= REG_PC)
3009 inst_env->reg[REG_PC] =
3010 read_memory_unsigned_integer (inst_env->prefix_value,
3011 4, inst_env->byte_order);
3013 /* The assign value is the value after the increment. Normally, the
3014 assign value is the value before the increment. */
3015 if ((cris_get_operand1 (inst) == REG_PC)
3016 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3018 inst_env->reg[REG_PC] = inst_env->prefix_value;
3019 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3024 /* Is the MOVEM instruction going to change the PC? */
3025 if (cris_get_operand2 (inst) == REG_PC)
3027 /* It's invalid to change the PC in a delay slot. */
3028 if (inst_env->slot_needed)
3030 inst_env->invalid = 1;
3033 inst_env->reg[REG_PC] =
3034 read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)],
3035 4, inst_env->byte_order);
3037 /* The increment is not depending on the size, instead it's depending
3038 on the number of registers loaded from memory. */
3039 if ((cris_get_operand1 (inst) == REG_PC)
3040 && (cris_get_mode (inst) == AUTOINC_MODE))
3042 /* It's invalid to change the PC in a delay slot. */
3043 if (inst_env->slot_needed)
3045 inst_env->invalid = 1;
3048 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3051 inst_env->slot_needed = 0;
3052 inst_env->prefix_found = 0;
3053 inst_env->xflag_found = 0;
3054 inst_env->disable_interrupt = 0;
3057 /* Handles the MOVEM to memory from general register instruction. */
3060 move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env)
3062 if (inst_env->prefix_found)
3064 /* The assign value is the value after the increment. Normally, the
3065 assign value is the value before the increment. */
3066 if ((cris_get_operand1 (inst) == REG_PC)
3067 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3069 /* The prefix handles the problem if we are in a delay slot. */
3070 inst_env->reg[REG_PC] = inst_env->prefix_value;
3071 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3076 /* The increment is not depending on the size, instead it's depending
3077 on the number of registers loaded to memory. */
3078 if ((cris_get_operand1 (inst) == REG_PC)
3079 && (cris_get_mode (inst) == AUTOINC_MODE))
3081 /* It's invalid to change the PC in a delay slot. */
3082 if (inst_env->slot_needed)
3084 inst_env->invalid = 1;
3087 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3090 inst_env->slot_needed = 0;
3091 inst_env->prefix_found = 0;
3092 inst_env->xflag_found = 0;
3093 inst_env->disable_interrupt = 0;
3096 /* Handles the intructions that's not yet implemented, by setting
3097 inst_env->invalid to true. */
3100 not_implemented_op (unsigned short inst, inst_env_type *inst_env)
3102 inst_env->invalid = 1;
3105 /* Handles the XOR instruction. */
3108 xor_op (unsigned short inst, inst_env_type *inst_env)
3110 /* XOR can't have a prefix. */
3111 if (inst_env->prefix_found)
3113 inst_env->invalid = 1;
3117 /* Check if the PC is the target. */
3118 if (cris_get_operand2 (inst) == REG_PC)
3120 /* It's invalid to change the PC in a delay slot. */
3121 if (inst_env->slot_needed)
3123 inst_env->invalid = 1;
3126 inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)];
3128 inst_env->slot_needed = 0;
3129 inst_env->prefix_found = 0;
3130 inst_env->xflag_found = 0;
3131 inst_env->disable_interrupt = 0;
3134 /* Handles the MULS instruction. */
3137 muls_op (unsigned short inst, inst_env_type *inst_env)
3139 /* MULS/U can't have a prefix. */
3140 if (inst_env->prefix_found)
3142 inst_env->invalid = 1;
3146 /* Consider it invalid if the PC is the target. */
3147 if (cris_get_operand2 (inst) == REG_PC)
3149 inst_env->invalid = 1;
3152 inst_env->slot_needed = 0;
3153 inst_env->prefix_found = 0;
3154 inst_env->xflag_found = 0;
3155 inst_env->disable_interrupt = 0;
3158 /* Handles the MULU instruction. */
3161 mulu_op (unsigned short inst, inst_env_type *inst_env)
3163 /* MULS/U can't have a prefix. */
3164 if (inst_env->prefix_found)
3166 inst_env->invalid = 1;
3170 /* Consider it invalid if the PC is the target. */
3171 if (cris_get_operand2 (inst) == REG_PC)
3173 inst_env->invalid = 1;
3176 inst_env->slot_needed = 0;
3177 inst_env->prefix_found = 0;
3178 inst_env->xflag_found = 0;
3179 inst_env->disable_interrupt = 0;
3182 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
3183 The MOVE instruction is the move from source to register. */
3186 add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env,
3187 unsigned long source1, unsigned long source2)
3189 unsigned long pc_mask;
3190 unsigned long operation_mask;
3192 /* Find out how many bits the operation should apply to. */
3193 if (cris_get_size (inst) == INST_BYTE_SIZE)
3195 pc_mask = 0xFFFFFF00;
3196 operation_mask = 0xFF;
3198 else if (cris_get_size (inst) == INST_WORD_SIZE)
3200 pc_mask = 0xFFFF0000;
3201 operation_mask = 0xFFFF;
3203 else if (cris_get_size (inst) == INST_DWORD_SIZE)
3206 operation_mask = 0xFFFFFFFF;
3210 /* The size is out of range. */
3211 inst_env->invalid = 1;
3215 /* The instruction just works on uw_operation_mask bits. */
3216 source2 &= operation_mask;
3217 source1 &= operation_mask;
3219 /* Now calculate the result. The opcode's 3 first bits separates
3220 the different actions. */
3221 switch (cris_get_opcode (inst) & 7)
3231 case 2: /* subtract */
3235 case 3: /* compare */
3247 inst_env->invalid = 1;
3253 /* Make sure that the result doesn't contain more than the instruction
3255 source2 &= operation_mask;
3257 /* Calculate the new breakpoint address. */
3258 inst_env->reg[REG_PC] &= pc_mask;
3259 inst_env->reg[REG_PC] |= source1;
3263 /* Extends the value from either byte or word size to a dword. If the mode
3264 is zero extend then the value is extended with zero. If instead the mode
3265 is signed extend the sign bit of the value is taken into consideration. */
3267 static unsigned long
3268 do_sign_or_zero_extend (unsigned long value, unsigned short *inst)
3270 /* The size can be either byte or word, check which one it is.
3271 Don't check the highest bit, it's indicating if it's a zero
3273 if (cris_get_size (*inst) & INST_WORD_SIZE)
3278 /* Check if the instruction is signed extend. If so, check if value has
3280 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK))
3282 value |= SIGNED_WORD_EXTEND_MASK;
3290 /* Check if the instruction is signed extend. If so, check if value has
3292 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK))
3294 value |= SIGNED_BYTE_EXTEND_MASK;
3297 /* The size should now be dword. */
3298 cris_set_size_to_dword (inst);
3302 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3303 instruction. The MOVE instruction is the move from source to register. */
3306 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3307 inst_env_type *inst_env)
3309 unsigned long operand1;
3310 unsigned long operand2;
3312 /* It's invalid to have a prefix to the instruction. This is a register
3313 mode instruction and can't have a prefix. */
3314 if (inst_env->prefix_found)
3316 inst_env->invalid = 1;
3319 /* Check if the instruction has PC as its target. */
3320 if (cris_get_operand2 (inst) == REG_PC)
3322 if (inst_env->slot_needed)
3324 inst_env->invalid = 1;
3327 /* The instruction has the PC as its target register. */
3328 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3329 operand2 = inst_env->reg[REG_PC];
3331 /* Check if it's a extend, signed or zero instruction. */
3332 if (cris_get_opcode (inst) < 4)
3334 operand1 = do_sign_or_zero_extend (operand1, &inst);
3336 /* Calculate the PC value after the instruction, i.e. where the
3337 breakpoint should be. The order of the udw_operands is vital. */
3338 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3340 inst_env->slot_needed = 0;
3341 inst_env->prefix_found = 0;
3342 inst_env->xflag_found = 0;
3343 inst_env->disable_interrupt = 0;
3346 /* Returns the data contained at address. The size of the data is derived from
3347 the size of the operation. If the instruction is a zero or signed
3348 extend instruction, the size field is changed in instruction. */
3350 static unsigned long
3351 get_data_from_address (unsigned short *inst, CORE_ADDR address,
3352 enum bfd_endian byte_order)
3354 int size = cris_get_size (*inst);
3355 unsigned long value;
3357 /* If it's an extend instruction we don't want the signed extend bit,
3358 because it influences the size. */
3359 if (cris_get_opcode (*inst) < 4)
3361 size &= ~SIGNED_EXTEND_BIT_MASK;
3363 /* Is there a need for checking the size? Size should contain the number of
3366 value = read_memory_unsigned_integer (address, size, byte_order);
3368 /* Check if it's an extend, signed or zero instruction. */
3369 if (cris_get_opcode (*inst) < 4)
3371 value = do_sign_or_zero_extend (value, inst);
3376 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3377 instructions. The MOVE instruction is the move from source to register. */
3380 handle_prefix_assign_mode_for_aritm_op (unsigned short inst,
3381 inst_env_type *inst_env)
3383 unsigned long operand2;
3384 unsigned long operand3;
3386 check_assign (inst, inst_env);
3387 if (cris_get_operand2 (inst) == REG_PC)
3389 operand2 = inst_env->reg[REG_PC];
3391 /* Get the value of the third operand. */
3392 operand3 = get_data_from_address (&inst, inst_env->prefix_value,
3393 inst_env->byte_order);
3395 /* Calculate the PC value after the instruction, i.e. where the
3396 breakpoint should be. The order of the udw_operands is vital. */
3397 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3399 inst_env->slot_needed = 0;
3400 inst_env->prefix_found = 0;
3401 inst_env->xflag_found = 0;
3402 inst_env->disable_interrupt = 0;
3405 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3406 OR instructions. Note that for this to work as expected, the calling
3407 function must have made sure that there is a prefix to this instruction. */
3410 three_operand_add_sub_cmp_and_or_op (unsigned short inst,
3411 inst_env_type *inst_env)
3413 unsigned long operand2;
3414 unsigned long operand3;
3416 if (cris_get_operand1 (inst) == REG_PC)
3418 /* The PC will be changed by the instruction. */
3419 operand2 = inst_env->reg[cris_get_operand2 (inst)];
3421 /* Get the value of the third operand. */
3422 operand3 = get_data_from_address (&inst, inst_env->prefix_value,
3423 inst_env->byte_order);
3425 /* Calculate the PC value after the instruction, i.e. where the
3426 breakpoint should be. */
3427 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3429 inst_env->slot_needed = 0;
3430 inst_env->prefix_found = 0;
3431 inst_env->xflag_found = 0;
3432 inst_env->disable_interrupt = 0;
3435 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3436 instructions. The MOVE instruction is the move from source to register. */
3439 handle_prefix_index_mode_for_aritm_op (unsigned short inst,
3440 inst_env_type *inst_env)
3442 if (cris_get_operand1 (inst) != cris_get_operand2 (inst))
3444 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
3445 SUB, AND or OR something weird is going on (if everything works these
3446 instructions should end up in the three operand version). */
3447 inst_env->invalid = 1;
3452 /* three_operand_add_sub_cmp_and_or does the same as we should do here
3454 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3456 inst_env->slot_needed = 0;
3457 inst_env->prefix_found = 0;
3458 inst_env->xflag_found = 0;
3459 inst_env->disable_interrupt = 0;
3462 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3463 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
3464 source to register. */
3467 handle_inc_and_index_mode_for_aritm_op (unsigned short inst,
3468 inst_env_type *inst_env)
3470 unsigned long operand1;
3471 unsigned long operand2;
3472 unsigned long operand3;
3475 /* The instruction is either an indirect or autoincrement addressing mode.
3476 Check if the destination register is the PC. */
3477 if (cris_get_operand2 (inst) == REG_PC)
3479 /* Must be done here, get_data_from_address may change the size
3481 size = cris_get_size (inst);
3482 operand2 = inst_env->reg[REG_PC];
3484 /* Get the value of the third operand, i.e. the indirect operand. */
3485 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3486 operand3 = get_data_from_address (&inst, operand1, inst_env->byte_order);
3488 /* Calculate the PC value after the instruction, i.e. where the
3489 breakpoint should be. The order of the udw_operands is vital. */
3490 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3492 /* If this is an autoincrement addressing mode, check if the increment
3494 if ((cris_get_operand1 (inst) == REG_PC)
3495 && (cris_get_mode (inst) == AUTOINC_MODE))
3497 /* Get the size field. */
3498 size = cris_get_size (inst);
3500 /* If it's an extend instruction we don't want the signed extend bit,
3501 because it influences the size. */
3502 if (cris_get_opcode (inst) < 4)
3504 size &= ~SIGNED_EXTEND_BIT_MASK;
3506 process_autoincrement (size, inst, inst_env);
3508 inst_env->slot_needed = 0;
3509 inst_env->prefix_found = 0;
3510 inst_env->xflag_found = 0;
3511 inst_env->disable_interrupt = 0;
3514 /* Handles the two-operand addressing mode, all modes except register, for
3515 the ADD, SUB CMP, AND and OR instruction. */
3518 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3519 inst_env_type *inst_env)
3521 if (inst_env->prefix_found)
3523 if (cris_get_mode (inst) == PREFIX_INDEX_MODE)
3525 handle_prefix_index_mode_for_aritm_op (inst, inst_env);
3527 else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
3529 handle_prefix_assign_mode_for_aritm_op (inst, inst_env);
3533 /* The mode is invalid for a prefixed base instruction. */
3534 inst_env->invalid = 1;
3540 handle_inc_and_index_mode_for_aritm_op (inst, inst_env);
3544 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3547 quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env)
3549 unsigned long operand1;
3550 unsigned long operand2;
3552 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3553 instruction and can't have a prefix. */
3554 if (inst_env->prefix_found)
3556 inst_env->invalid = 1;
3560 /* Check if the instruction has PC as its target. */
3561 if (cris_get_operand2 (inst) == REG_PC)
3563 if (inst_env->slot_needed)
3565 inst_env->invalid = 1;
3568 operand1 = cris_get_quick_value (inst);
3569 operand2 = inst_env->reg[REG_PC];
3571 /* The size should now be dword. */
3572 cris_set_size_to_dword (&inst);
3574 /* Calculate the PC value after the instruction, i.e. where the
3575 breakpoint should be. */
3576 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3578 inst_env->slot_needed = 0;
3579 inst_env->prefix_found = 0;
3580 inst_env->xflag_found = 0;
3581 inst_env->disable_interrupt = 0;
3584 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3587 quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env)
3589 unsigned long operand1;
3590 unsigned long operand2;
3592 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3593 instruction and can't have a prefix. */
3594 if (inst_env->prefix_found)
3596 inst_env->invalid = 1;
3599 /* Check if the instruction has PC as its target. */
3600 if (cris_get_operand2 (inst) == REG_PC)
3602 if (inst_env->slot_needed)
3604 inst_env->invalid = 1;
3607 /* The instruction has the PC as its target register. */
3608 operand1 = cris_get_quick_value (inst);
3609 operand2 = inst_env->reg[REG_PC];
3611 /* The quick value is signed, so check if we must do a signed extend. */
3612 if (operand1 & SIGNED_QUICK_VALUE_MASK)
3615 operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK;
3617 /* The size should now be dword. */
3618 cris_set_size_to_dword (&inst);
3620 /* Calculate the PC value after the instruction, i.e. where the
3621 breakpoint should be. */
3622 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3624 inst_env->slot_needed = 0;
3625 inst_env->prefix_found = 0;
3626 inst_env->xflag_found = 0;
3627 inst_env->disable_interrupt = 0;
3630 /* Translate op_type to a function and call it. */
3633 cris_gdb_func (struct gdbarch *gdbarch, enum cris_op_type op_type,
3634 unsigned short inst, inst_env_type *inst_env)
3638 case cris_not_implemented_op:
3639 not_implemented_op (inst, inst_env);
3643 abs_op (inst, inst_env);
3647 addi_op (inst, inst_env);
3651 asr_op (inst, inst_env);
3655 asrq_op (inst, inst_env);
3658 case cris_ax_ei_setf_op:
3659 ax_ei_setf_op (inst, inst_env);
3662 case cris_bdap_prefix:
3663 bdap_prefix (inst, inst_env);
3666 case cris_biap_prefix:
3667 biap_prefix (inst, inst_env);
3671 break_op (inst, inst_env);
3674 case cris_btst_nop_op:
3675 btst_nop_op (inst, inst_env);
3678 case cris_clearf_di_op:
3679 clearf_di_op (inst, inst_env);
3682 case cris_dip_prefix:
3683 dip_prefix (inst, inst_env);
3686 case cris_dstep_logshift_mstep_neg_not_op:
3687 dstep_logshift_mstep_neg_not_op (inst, inst_env);
3690 case cris_eight_bit_offset_branch_op:
3691 eight_bit_offset_branch_op (inst, inst_env);
3694 case cris_move_mem_to_reg_movem_op:
3695 move_mem_to_reg_movem_op (inst, inst_env);
3698 case cris_move_reg_to_mem_movem_op:
3699 move_reg_to_mem_movem_op (inst, inst_env);
3702 case cris_move_to_preg_op:
3703 move_to_preg_op (gdbarch, inst, inst_env);
3707 muls_op (inst, inst_env);
3711 mulu_op (inst, inst_env);
3714 case cris_none_reg_mode_add_sub_cmp_and_or_move_op:
3715 none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3718 case cris_none_reg_mode_clear_test_op:
3719 none_reg_mode_clear_test_op (inst, inst_env);
3722 case cris_none_reg_mode_jump_op:
3723 none_reg_mode_jump_op (inst, inst_env);
3726 case cris_none_reg_mode_move_from_preg_op:
3727 none_reg_mode_move_from_preg_op (gdbarch, inst, inst_env);
3730 case cris_quick_mode_add_sub_op:
3731 quick_mode_add_sub_op (inst, inst_env);
3734 case cris_quick_mode_and_cmp_move_or_op:
3735 quick_mode_and_cmp_move_or_op (inst, inst_env);
3738 case cris_quick_mode_bdap_prefix:
3739 quick_mode_bdap_prefix (inst, inst_env);
3742 case cris_reg_mode_add_sub_cmp_and_or_move_op:
3743 reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3746 case cris_reg_mode_clear_op:
3747 reg_mode_clear_op (inst, inst_env);
3750 case cris_reg_mode_jump_op:
3751 reg_mode_jump_op (inst, inst_env);
3754 case cris_reg_mode_move_from_preg_op:
3755 reg_mode_move_from_preg_op (inst, inst_env);
3758 case cris_reg_mode_test_op:
3759 reg_mode_test_op (inst, inst_env);
3763 scc_op (inst, inst_env);
3766 case cris_sixteen_bit_offset_branch_op:
3767 sixteen_bit_offset_branch_op (inst, inst_env);
3770 case cris_three_operand_add_sub_cmp_and_or_op:
3771 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3774 case cris_three_operand_bound_op:
3775 three_operand_bound_op (inst, inst_env);
3778 case cris_two_operand_bound_op:
3779 two_operand_bound_op (inst, inst_env);
3783 xor_op (inst, inst_env);
3788 /* This wrapper is to avoid cris_get_assembler being called before
3789 exec_bfd has been set. */
3792 cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info)
3794 int (*print_insn) (bfd_vma addr, struct disassemble_info *info);
3795 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3796 disassembler, even when there is no BFD. Does something like
3797 "gdb; target remote; disassmeble *0x123" work? */
3798 gdb_assert (exec_bfd != NULL);
3799 print_insn = cris_get_disassembler (exec_bfd);
3800 gdb_assert (print_insn != NULL);
3801 return print_insn (addr, info);
3804 /* Originally from <asm/elf.h>. */
3805 typedef unsigned char cris_elf_greg_t[4];
3807 /* Same as user_regs_struct struct in <asm/user.h>. */
3808 #define CRISV10_ELF_NGREG 35
3809 typedef cris_elf_greg_t cris_elf_gregset_t[CRISV10_ELF_NGREG];
3811 #define CRISV32_ELF_NGREG 32
3812 typedef cris_elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG];
3814 /* Unpack a cris_elf_gregset_t into GDB's register cache. */
3817 cris_supply_gregset (struct regcache *regcache, cris_elf_gregset_t *gregsetp)
3819 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3820 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3822 cris_elf_greg_t *regp = *gregsetp;
3824 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3825 knows about the actual size of each register so that's no problem. */
3826 for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++)
3828 regcache_raw_supply (regcache, i, (char *)®p[i]);
3831 if (tdep->cris_version == 32)
3833 /* Needed to set pseudo-register PC for CRISv32. */
3834 /* FIXME: If ERP is in a delay slot at this point then the PC will
3835 be wrong. Issue a warning to alert the user. */
3836 regcache_raw_supply (regcache, gdbarch_pc_regnum (gdbarch),
3837 (char *)®p[ERP_REGNUM]);
3839 if (*(char *)®p[ERP_REGNUM] & 0x1)
3840 fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n");
3844 /* Use a local version of this function to get the correct types for
3845 regsets, until multi-arch core support is ready. */
3848 fetch_core_registers (struct regcache *regcache,
3849 char *core_reg_sect, unsigned core_reg_size,
3850 int which, CORE_ADDR reg_addr)
3852 cris_elf_gregset_t gregset;
3857 if (core_reg_size != sizeof (cris_elf_gregset_t)
3858 && core_reg_size != sizeof (crisv32_elf_gregset_t))
3860 warning (_("wrong size gregset struct in core file"));
3864 memcpy (&gregset, core_reg_sect, sizeof (gregset));
3865 cris_supply_gregset (regcache, &gregset);
3869 /* We've covered all the kinds of registers we know about here,
3870 so this must be something we wouldn't know what to do with
3871 anyway. Just ignore it. */
3876 static struct core_fns cris_elf_core_fns =
3878 bfd_target_elf_flavour, /* core_flavour */
3879 default_check_format, /* check_format */
3880 default_core_sniffer, /* core_sniffer */
3881 fetch_core_registers, /* core_read_registers */
3885 extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */
3888 _initialize_cris_tdep (void)
3890 gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep);
3892 /* CRIS-specific user-commands. */
3893 add_setshow_zuinteger_cmd ("cris-version", class_support,
3894 &usr_cmd_cris_version,
3895 _("Set the current CRIS version."),
3896 _("Show the current CRIS version."),
3898 Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\
3901 NULL, /* FIXME: i18n: Current CRIS version
3903 &setlist, &showlist);
3905 add_setshow_enum_cmd ("cris-mode", class_support,
3906 cris_modes, &usr_cmd_cris_mode,
3907 _("Set the current CRIS mode."),
3908 _("Show the current CRIS mode."),
3910 Set to CRIS_MODE_GURU when debugging in guru mode.\n\
3911 Makes GDB use the NRP register instead of the ERP register in certain cases."),
3913 NULL, /* FIXME: i18n: Current CRIS version is %s. */
3914 &setlist, &showlist);
3916 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support,
3917 &usr_cmd_cris_dwarf2_cfi,
3918 _("Set the usage of Dwarf-2 CFI for CRIS."),
3919 _("Show the usage of Dwarf-2 CFI for CRIS."),
3920 _("Set this to \"off\" if using gcc-cris < R59."),
3921 set_cris_dwarf2_cfi,
3922 NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI
3924 &setlist, &showlist);
3926 deprecated_add_core_fns (&cris_elf_core_fns);
3929 /* Prints out all target specific values. */
3932 cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3934 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3937 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n",
3938 tdep->cris_version);
3939 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n",
3941 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
3942 tdep->cris_dwarf2_cfi);
3947 set_cris_version (char *ignore_args, int from_tty,
3948 struct cmd_list_element *c)
3950 struct gdbarch_info info;
3952 usr_cmd_cris_version_valid = 1;
3954 /* Update the current architecture, if needed. */
3955 gdbarch_info_init (&info);
3956 if (!gdbarch_update_p (info))
3957 internal_error (__FILE__, __LINE__,
3958 _("cris_gdbarch_update: failed to update architecture."));
3962 set_cris_mode (char *ignore_args, int from_tty,
3963 struct cmd_list_element *c)
3965 struct gdbarch_info info;
3967 /* Update the current architecture, if needed. */
3968 gdbarch_info_init (&info);
3969 if (!gdbarch_update_p (info))
3970 internal_error (__FILE__, __LINE__,
3971 "cris_gdbarch_update: failed to update architecture.");
3975 set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
3976 struct cmd_list_element *c)
3978 struct gdbarch_info info;
3980 /* Update the current architecture, if needed. */
3981 gdbarch_info_init (&info);
3982 if (!gdbarch_update_p (info))
3983 internal_error (__FILE__, __LINE__,
3984 _("cris_gdbarch_update: failed to update architecture."));
3987 static struct gdbarch *
3988 cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3990 struct gdbarch *gdbarch;
3991 struct gdbarch_tdep *tdep;
3992 unsigned int cris_version;
3994 if (usr_cmd_cris_version_valid)
3996 /* Trust the user's CRIS version setting. */
3997 cris_version = usr_cmd_cris_version;
3999 else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32)
4005 /* Assume it's CRIS version 10. */
4009 /* Make the current settings visible to the user. */
4010 usr_cmd_cris_version = cris_version;
4012 /* Find a candidate among the list of pre-declared architectures. */
4013 for (arches = gdbarch_list_lookup_by_info (arches, &info);
4015 arches = gdbarch_list_lookup_by_info (arches->next, &info))
4017 if ((gdbarch_tdep (arches->gdbarch)->cris_version
4018 == usr_cmd_cris_version)
4019 && (gdbarch_tdep (arches->gdbarch)->cris_mode
4020 == usr_cmd_cris_mode)
4021 && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi
4022 == usr_cmd_cris_dwarf2_cfi))
4023 return arches->gdbarch;
4026 /* No matching architecture was found. Create a new one. */
4027 tdep = XNEW (struct gdbarch_tdep);
4028 gdbarch = gdbarch_alloc (&info, tdep);
4030 tdep->cris_version = usr_cmd_cris_version;
4031 tdep->cris_mode = usr_cmd_cris_mode;
4032 tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi;
4034 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
4035 switch (info.byte_order)
4037 case BFD_ENDIAN_LITTLE:
4041 case BFD_ENDIAN_BIG:
4042 /* Cris is always little endian, but the user could have forced
4043 big endian with "set endian". */
4047 internal_error (__FILE__, __LINE__,
4048 _("cris_gdbarch_init: unknown byte order in info"));
4051 set_gdbarch_return_value (gdbarch, cris_return_value);
4053 set_gdbarch_sp_regnum (gdbarch, 14);
4055 /* Length of ordinary registers used in push_word and a few other
4056 places. register_size() is the real way to know how big a
4059 set_gdbarch_double_bit (gdbarch, 64);
4060 /* The default definition of a long double is 2 * gdbarch_double_bit,
4061 which means we have to set this explicitly. */
4062 set_gdbarch_long_double_bit (gdbarch, 64);
4064 /* The total amount of space needed to store (in an array called registers)
4065 GDB's copy of the machine's register state. Note: We can not use
4066 cris_register_size at this point, since it relies on gdbarch
4068 switch (tdep->cris_version)
4076 /* Old versions; not supported. */
4081 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
4082 P7 (32 bits), and P15 (32 bits) have been implemented. */
4083 set_gdbarch_pc_regnum (gdbarch, 15);
4084 set_gdbarch_register_type (gdbarch, cris_register_type);
4085 /* There are 32 registers (some of which may not be implemented). */
4086 set_gdbarch_num_regs (gdbarch, 32);
4087 set_gdbarch_register_name (gdbarch, cris_register_name);
4088 set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register);
4089 set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register);
4091 set_gdbarch_software_single_step (gdbarch, cris_software_single_step);
4095 /* CRIS v32. General registers R0 - R15 (32 bits), special registers
4096 P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
4097 and pseudo-register PC (32 bits). */
4098 set_gdbarch_pc_regnum (gdbarch, 32);
4099 set_gdbarch_register_type (gdbarch, crisv32_register_type);
4100 /* 32 registers + pseudo-register PC + 16 support registers. */
4101 set_gdbarch_num_regs (gdbarch, 32 + 1 + 16);
4102 set_gdbarch_register_name (gdbarch, crisv32_register_name);
4104 set_gdbarch_cannot_store_register
4105 (gdbarch, crisv32_cannot_store_register);
4106 set_gdbarch_cannot_fetch_register
4107 (gdbarch, crisv32_cannot_fetch_register);
4109 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
4111 set_gdbarch_single_step_through_delay
4112 (gdbarch, crisv32_single_step_through_delay);
4117 /* Unknown version. */
4121 /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
4122 have the same ABI). */
4123 set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code);
4124 set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call);
4125 set_gdbarch_frame_align (gdbarch, cris_frame_align);
4126 set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue);
4128 /* The stack grows downward. */
4129 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4131 set_gdbarch_breakpoint_kind_from_pc (gdbarch, cris_breakpoint_kind_from_pc);
4132 set_gdbarch_sw_breakpoint_from_kind (gdbarch, cris_sw_breakpoint_from_kind);
4134 set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc);
4135 set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp);
4136 set_gdbarch_dummy_id (gdbarch, cris_dummy_id);
4138 if (tdep->cris_dwarf2_cfi == 1)
4140 /* Hook in the Dwarf-2 frame sniffer. */
4141 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum);
4142 dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg);
4143 dwarf2_append_unwinders (gdbarch);
4146 if (tdep->cris_mode != cris_mode_guru)
4148 frame_unwind_append_unwinder (gdbarch, &cris_sigtramp_frame_unwind);
4151 frame_unwind_append_unwinder (gdbarch, &cris_frame_unwind);
4152 frame_base_set_default (gdbarch, &cris_frame_base);
4154 /* Hook in ABI-specific overrides, if they have been registered. */
4155 gdbarch_init_osabi (info, gdbarch);
4157 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
4158 disassembler, even when there is no BFD. Does something like
4159 "gdb; target remote; disassmeble *0x123" work? */
4160 set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler);