1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 Contributed by Axis Communications AB.
7 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "frame-unwind.h"
27 #include "frame-base.h"
28 #include "trad-frame.h"
29 #include "dwarf2-frame.h"
37 #include "opcode/cris.h"
38 #include "arch-utils.h"
40 #include "gdb_assert.h"
42 /* To get entry_point_address. */
45 #include "solib.h" /* Support for shared libraries. */
46 #include "solib-svr4.h"
47 #include "gdb_string.h"
52 /* There are no floating point registers. Used in gdbserver low-linux.c. */
55 /* There are 16 general registers. */
58 /* There are 16 special registers. */
61 /* CRISv32 has a pseudo PC register, not noted here. */
63 /* CRISv32 has 16 support registers. */
67 /* Register numbers of various important registers.
68 CRIS_FP_REGNUM Contains address of executing stack frame.
69 STR_REGNUM Contains the address of structure return values.
70 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
71 ARG1_REGNUM Contains the first parameter to a function.
72 ARG2_REGNUM Contains the second parameter to a function.
73 ARG3_REGNUM Contains the third parameter to a function.
74 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
75 gdbarch_sp_regnum Contains address of top of stack.
76 gdbarch_pc_regnum Contains address of next instruction.
77 SRP_REGNUM Subroutine return pointer register.
78 BRP_REGNUM Breakpoint return pointer register. */
82 /* Enums with respect to the general registers, valid for all
83 CRIS versions. The frame pointer is always in R8. */
85 /* ABI related registers. */
93 /* Registers which happen to be common. */
98 /* CRISv10 et. al. specific registers. */
110 /* CRISv32 specific registers. */
123 CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */
125 CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */
145 extern const struct cris_spec_reg cris_spec_regs[];
147 /* CRIS version, set via the user command 'set cris-version'. Affects
148 register names and sizes. */
149 static int usr_cmd_cris_version;
151 /* Indicates whether to trust the above variable. */
152 static int usr_cmd_cris_version_valid = 0;
154 static const char cris_mode_normal[] = "normal";
155 static const char cris_mode_guru[] = "guru";
156 static const char *cris_modes[] = {
162 /* CRIS mode, set via the user command 'set cris-mode'. Affects
163 type of break instruction among other things. */
164 static const char *usr_cmd_cris_mode = cris_mode_normal;
166 /* Whether to make use of Dwarf-2 CFI (default on). */
167 static int usr_cmd_cris_dwarf2_cfi = 1;
169 /* CRIS architecture specific information. */
173 const char *cris_mode;
177 /* Sigtramp identification code copied from i386-linux-tdep.c. */
179 #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
180 #define SIGTRAMP_OFFSET0 0
181 #define SIGTRAMP_INSN1 0xe93d /* break 13 */
182 #define SIGTRAMP_OFFSET1 4
184 static const unsigned short sigtramp_code[] =
186 SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */
187 SIGTRAMP_INSN1 /* break 13 */
190 #define SIGTRAMP_LEN (sizeof sigtramp_code)
192 /* Note: same length as normal sigtramp code. */
194 static const unsigned short rt_sigtramp_code[] =
196 SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */
197 SIGTRAMP_INSN1 /* break 13 */
200 /* If PC is in a sigtramp routine, return the address of the start of
201 the routine. Otherwise, return 0. */
204 cris_sigtramp_start (struct frame_info *this_frame)
206 CORE_ADDR pc = get_frame_pc (this_frame);
207 gdb_byte buf[SIGTRAMP_LEN];
209 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
212 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
214 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
217 pc -= SIGTRAMP_OFFSET1;
218 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
222 if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0)
228 /* If PC is in a RT sigtramp routine, return the address of the start of
229 the routine. Otherwise, return 0. */
232 cris_rt_sigtramp_start (struct frame_info *this_frame)
234 CORE_ADDR pc = get_frame_pc (this_frame);
235 gdb_byte buf[SIGTRAMP_LEN];
237 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
240 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
242 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
245 pc -= SIGTRAMP_OFFSET1;
246 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
250 if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0)
256 /* Assuming THIS_FRAME is a frame for a GNU/Linux sigtramp routine,
257 return the address of the associated sigcontext structure. */
260 cris_sigcontext_addr (struct frame_info *this_frame)
262 struct gdbarch *gdbarch = get_frame_arch (this_frame);
263 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
268 get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
269 sp = extract_unsigned_integer (buf, 4, byte_order);
271 /* Look for normal sigtramp frame first. */
272 pc = cris_sigtramp_start (this_frame);
275 /* struct signal_frame (arch/cris/kernel/signal.c) contains
276 struct sigcontext as its first member, meaning the SP points to
281 pc = cris_rt_sigtramp_start (this_frame);
284 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
285 a struct ucontext, which in turn contains a struct sigcontext.
287 4 + 4 + 128 to struct ucontext, then
288 4 + 4 + 12 to struct sigcontext. */
292 error (_("Couldn't recognize signal trampoline."));
296 struct cris_unwind_cache
298 /* The previous frame's inner most stack address. Used as this
299 frame ID's stack_addr. */
301 /* The frame's base, optionally used by the high-level debug info. */
304 /* How far the SP and r8 (FP) have been offset from the start of
305 the stack frame (as defined by the previous frame's stack
311 /* From old frame_extra_info struct. */
315 /* Table indicating the location of each and every register. */
316 struct trad_frame_saved_reg *saved_regs;
319 static struct cris_unwind_cache *
320 cris_sigtramp_frame_unwind_cache (struct frame_info *this_frame,
323 struct gdbarch *gdbarch = get_frame_arch (this_frame);
324 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
325 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
326 struct cris_unwind_cache *info;
334 return (*this_cache);
336 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
337 (*this_cache) = info;
338 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
340 /* Zero all fields. */
346 info->uses_frame = 0;
348 info->leaf_function = 0;
350 get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
351 info->base = extract_unsigned_integer (buf, 4, byte_order);
353 addr = cris_sigcontext_addr (this_frame);
355 /* Layout of the sigcontext struct:
358 unsigned long oldmask;
362 if (tdep->cris_version == 10)
364 /* R0 to R13 are stored in reverse order at offset (2 * 4) in
366 for (i = 0; i <= 13; i++)
367 info->saved_regs[i].addr = addr + ((15 - i) * 4);
369 info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4);
370 info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4);
371 info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4);
372 /* Note: IRP is off by 2 at this point. There's no point in correcting
373 it though since that will mean that the backtrace will show a PC
374 different from what is shown when stopped. */
375 info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4);
376 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
377 = info->saved_regs[IRP_REGNUM];
378 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr = addr + (24 * 4);
383 /* R0 to R13 are stored in order at offset (1 * 4) in
385 for (i = 0; i <= 13; i++)
386 info->saved_regs[i].addr = addr + ((i + 1) * 4);
388 info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4);
389 info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4);
390 info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4);
391 info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4);
392 info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4);
393 info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4);
394 info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4);
395 info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4);
396 info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4);
398 /* FIXME: If ERP is in a delay slot at this point then the PC will
399 be wrong at this point. This problem manifests itself in the
400 sigaltstack.exp test case, which occasionally generates FAILs when
401 the signal is received while in a delay slot.
403 This could be solved by a couple of read_memory_unsigned_integer and a
404 trad_frame_set_value. */
405 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
406 = info->saved_regs[ERP_REGNUM];
408 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr
416 cris_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
417 struct frame_id *this_id)
419 struct cris_unwind_cache *cache =
420 cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
421 (*this_id) = frame_id_build (cache->base, get_frame_pc (this_frame));
424 /* Forward declaration. */
426 static struct value *cris_frame_prev_register (struct frame_info *this_frame,
427 void **this_cache, int regnum);
428 static struct value *
429 cris_sigtramp_frame_prev_register (struct frame_info *this_frame,
430 void **this_cache, int regnum)
432 /* Make sure we've initialized the cache. */
433 cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
434 return cris_frame_prev_register (this_frame, this_cache, regnum);
438 cris_sigtramp_frame_sniffer (const struct frame_unwind *self,
439 struct frame_info *this_frame,
442 if (cris_sigtramp_start (this_frame)
443 || cris_rt_sigtramp_start (this_frame))
449 static const struct frame_unwind cris_sigtramp_frame_unwind =
452 cris_sigtramp_frame_this_id,
453 cris_sigtramp_frame_prev_register,
455 cris_sigtramp_frame_sniffer
459 crisv32_single_step_through_delay (struct gdbarch *gdbarch,
460 struct frame_info *this_frame)
462 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
466 if (tdep->cris_mode == cris_mode_guru)
467 erp = get_frame_register_unsigned (this_frame, NRP_REGNUM);
469 erp = get_frame_register_unsigned (this_frame, ERP_REGNUM);
473 /* In delay slot - check if there's a breakpoint at the preceding
475 if (breakpoint_here_p (erp & ~0x1))
481 /* Hardware watchpoint support. */
483 /* We support 6 hardware data watchpoints, but cannot trigger on execute
484 (any combination of read/write is fine). */
487 cris_can_use_hardware_watchpoint (int type, int count, int other)
489 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
491 /* No bookkeeping is done here; it is handled by the remote debug agent. */
493 if (tdep->cris_version != 32)
496 /* CRISv32: Six data watchpoints, one for instructions. */
497 return (((type == bp_read_watchpoint || type == bp_access_watchpoint
498 || type == bp_hardware_watchpoint) && count <= 6)
499 || (type == bp_hardware_breakpoint && count <= 1));
502 /* The CRISv32 hardware data watchpoints work by specifying ranges,
503 which have no alignment or length restrictions. */
506 cris_region_ok_for_watchpoint (CORE_ADDR addr, int len)
511 /* If the inferior has some watchpoint that triggered, return the
512 address associated with that watchpoint. Otherwise, return
516 cris_stopped_data_address (void)
519 eda = get_frame_register_unsigned (get_current_frame (), EDA_REGNUM);
523 /* The instruction environment needed to find single-step breakpoints. */
526 struct instruction_environment
528 unsigned long reg[NUM_GENREGS];
529 unsigned long preg[NUM_SPECREGS];
530 unsigned long branch_break_address;
531 unsigned long delay_slot_pc;
532 unsigned long prefix_value;
537 int delay_slot_pc_active;
539 int disable_interrupt;
543 /* Machine-dependencies in CRIS for opcodes. */
545 /* Instruction sizes. */
546 enum cris_instruction_sizes
553 /* Addressing modes. */
554 enum cris_addressing_modes
561 /* Prefix addressing modes. */
562 enum cris_prefix_addressing_modes
564 PREFIX_INDEX_MODE = 2,
565 PREFIX_ASSIGN_MODE = 3,
567 /* Handle immediate byte offset addressing mode prefix format. */
568 PREFIX_OFFSET_MODE = 2
571 /* Masks for opcodes. */
572 enum cris_opcode_masks
574 BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1,
575 SIGNED_EXTEND_BIT_MASK = 0x2,
576 SIGNED_BYTE_MASK = 0x80,
577 SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00,
578 SIGNED_WORD_MASK = 0x8000,
579 SIGNED_WORD_EXTEND_MASK = 0xFFFF0000,
580 SIGNED_DWORD_MASK = 0x80000000,
581 SIGNED_QUICK_VALUE_MASK = 0x20,
582 SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0
585 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
593 cris_get_operand2 (unsigned short insn)
595 return ((insn & 0xF000) >> 12);
599 cris_get_mode (unsigned short insn)
601 return ((insn & 0x0C00) >> 10);
605 cris_get_opcode (unsigned short insn)
607 return ((insn & 0x03C0) >> 6);
611 cris_get_size (unsigned short insn)
613 return ((insn & 0x0030) >> 4);
617 cris_get_operand1 (unsigned short insn)
619 return (insn & 0x000F);
622 /* Additional functions in order to handle opcodes. */
625 cris_get_quick_value (unsigned short insn)
627 return (insn & 0x003F);
631 cris_get_bdap_quick_offset (unsigned short insn)
633 return (insn & 0x00FF);
637 cris_get_branch_short_offset (unsigned short insn)
639 return (insn & 0x00FF);
643 cris_get_asr_shift_steps (unsigned long value)
645 return (value & 0x3F);
649 cris_get_clear_size (unsigned short insn)
651 return ((insn) & 0xC000);
655 cris_is_signed_extend_bit_on (unsigned short insn)
657 return (((insn) & 0x20) == 0x20);
661 cris_is_xflag_bit_on (unsigned short insn)
663 return (((insn) & 0x1000) == 0x1000);
667 cris_set_size_to_dword (unsigned short *insn)
674 cris_get_signed_offset (unsigned short insn)
676 return ((signed char) (insn & 0x00FF));
679 /* Calls an op function given the op-type, working on the insn and the
681 static void cris_gdb_func (struct gdbarch *, enum cris_op_type, unsigned short,
684 static struct gdbarch *cris_gdbarch_init (struct gdbarch_info,
685 struct gdbarch_list *);
687 static void cris_dump_tdep (struct gdbarch *, struct ui_file *);
689 static void set_cris_version (char *ignore_args, int from_tty,
690 struct cmd_list_element *c);
692 static void set_cris_mode (char *ignore_args, int from_tty,
693 struct cmd_list_element *c);
695 static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
696 struct cmd_list_element *c);
698 static CORE_ADDR cris_scan_prologue (CORE_ADDR pc,
699 struct frame_info *this_frame,
700 struct cris_unwind_cache *info);
702 static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc,
703 struct frame_info *this_frame,
704 struct cris_unwind_cache *info);
706 static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch,
707 struct frame_info *next_frame);
709 static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch,
710 struct frame_info *next_frame);
712 /* When arguments must be pushed onto the stack, they go on in reverse
713 order. The below implements a FILO (stack) to do this.
714 Copied from d10v-tdep.c. */
719 struct stack_item *prev;
723 static struct stack_item *
724 push_stack_item (struct stack_item *prev, void *contents, int len)
726 struct stack_item *si;
727 si = xmalloc (sizeof (struct stack_item));
728 si->data = xmalloc (len);
731 memcpy (si->data, contents, len);
735 static struct stack_item *
736 pop_stack_item (struct stack_item *si)
738 struct stack_item *dead = si;
745 /* Put here the code to store, into fi->saved_regs, the addresses of
746 the saved registers of frame described by FRAME_INFO. This
747 includes special registers such as pc and fp saved in special ways
748 in the stack frame. sp is even more special: the address we return
749 for it IS the sp for the next frame. */
751 static struct cris_unwind_cache *
752 cris_frame_unwind_cache (struct frame_info *this_frame,
753 void **this_prologue_cache)
755 struct gdbarch *gdbarch = get_frame_arch (this_frame);
756 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
758 struct cris_unwind_cache *info;
761 if ((*this_prologue_cache))
762 return (*this_prologue_cache);
764 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
765 (*this_prologue_cache) = info;
766 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
768 /* Zero all fields. */
774 info->uses_frame = 0;
776 info->leaf_function = 0;
778 /* Prologue analysis does the rest... */
779 if (tdep->cris_version == 32)
780 crisv32_scan_prologue (get_frame_func (this_frame), this_frame, info);
782 cris_scan_prologue (get_frame_func (this_frame), this_frame, info);
787 /* Given a GDB frame, determine the address of the calling function's
788 frame. This will be used to create a new GDB frame struct. */
791 cris_frame_this_id (struct frame_info *this_frame,
792 void **this_prologue_cache,
793 struct frame_id *this_id)
795 struct cris_unwind_cache *info
796 = cris_frame_unwind_cache (this_frame, this_prologue_cache);
801 /* The FUNC is easy. */
802 func = get_frame_func (this_frame);
804 /* Hopefully the prologue analysis either correctly determined the
805 frame's base (which is the SP from the previous frame), or set
806 that base to "NULL". */
807 base = info->prev_sp;
811 id = frame_id_build (base, func);
816 static struct value *
817 cris_frame_prev_register (struct frame_info *this_frame,
818 void **this_prologue_cache, int regnum)
820 struct cris_unwind_cache *info
821 = cris_frame_unwind_cache (this_frame, this_prologue_cache);
822 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
825 /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
826 frame. The frame ID's base needs to match the TOS value saved by
827 save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */
829 static struct frame_id
830 cris_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
833 sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
834 return frame_id_build (sp, get_frame_pc (this_frame));
838 cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
840 /* Align to the size of an instruction (so that they can safely be
841 pushed onto the stack). */
846 cris_push_dummy_code (struct gdbarch *gdbarch,
847 CORE_ADDR sp, CORE_ADDR funaddr,
848 struct value **args, int nargs,
849 struct type *value_type,
850 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
851 struct regcache *regcache)
853 /* Allocate space sufficient for a breakpoint. */
855 /* Store the address of that breakpoint */
857 /* CRIS always starts the call at the callee's entry point. */
863 cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
864 struct regcache *regcache, CORE_ADDR bp_addr,
865 int nargs, struct value **args, CORE_ADDR sp,
866 int struct_return, CORE_ADDR struct_addr)
868 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
876 /* The function's arguments and memory allocated by gdb for the arguments to
877 point at reside in separate areas on the stack.
878 Both frame pointers grow toward higher addresses. */
882 struct stack_item *si = NULL;
884 /* Push the return address. */
885 regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr);
887 /* Are we returning a value using a structure return or a normal value
888 return? struct_addr is the address of the reserved space for the return
889 structure to be written on the stack. */
892 regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr);
895 /* Now load as many as possible of the first arguments into registers,
896 and push the rest onto the stack. */
897 argreg = ARG1_REGNUM;
900 for (argnum = 0; argnum < nargs; argnum++)
907 len = TYPE_LENGTH (value_type (args[argnum]));
908 val = (char *) value_contents (args[argnum]);
910 /* How may registers worth of storage do we need for this argument? */
911 reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0);
913 if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM))
915 /* Data passed by value. Fits in available register(s). */
916 for (i = 0; i < reg_demand; i++)
918 regcache_cooked_write (regcache, argreg, val);
923 else if (len <= (2 * 4) && argreg <= ARG4_REGNUM)
925 /* Data passed by value. Does not fit in available register(s).
926 Use the register(s) first, then the stack. */
927 for (i = 0; i < reg_demand; i++)
929 if (argreg <= ARG4_REGNUM)
931 regcache_cooked_write (regcache, argreg, val);
937 /* Push item for later so that pushed arguments
938 come in the right order. */
939 si = push_stack_item (si, val, 4);
944 else if (len > (2 * 4))
946 /* Data passed by reference. Push copy of data onto stack
947 and pass pointer to this copy as argument. */
948 sp = (sp - len) & ~3;
949 write_memory (sp, val, len);
951 if (argreg <= ARG4_REGNUM)
953 regcache_cooked_write_unsigned (regcache, argreg, sp);
959 store_unsigned_integer (buf, 4, byte_order, sp);
960 si = push_stack_item (si, buf, 4);
965 /* Data passed by value. No available registers. Put it on
967 si = push_stack_item (si, val, len);
973 /* fp_arg must be word-aligned (i.e., don't += len) to match
974 the function prologue. */
975 sp = (sp - si->len) & ~3;
976 write_memory (sp, si->data, si->len);
977 si = pop_stack_item (si);
980 /* Finally, update the SP register. */
981 regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp);
986 static const struct frame_unwind cris_frame_unwind =
990 cris_frame_prev_register,
992 default_frame_sniffer
996 cris_frame_base_address (struct frame_info *this_frame, void **this_cache)
998 struct cris_unwind_cache *info
999 = cris_frame_unwind_cache (this_frame, this_cache);
1003 static const struct frame_base cris_frame_base =
1006 cris_frame_base_address,
1007 cris_frame_base_address,
1008 cris_frame_base_address
1011 /* Frames information. The definition of the struct frame_info is
1015 enum frame_type type;
1019 If the compilation option -fno-omit-frame-pointer is present the
1020 variable frame will be set to the content of R8 which is the frame
1023 The variable pc contains the address where execution is performed
1024 in the present frame. The innermost frame contains the current content
1025 of the register PC. All other frames contain the content of the
1026 register PC in the next frame.
1028 The variable `type' indicates the frame's type: normal, SIGTRAMP
1029 (associated with a signal handler), dummy (associated with a dummy
1032 The variable return_pc contains the address where execution should be
1033 resumed when the present frame has finished, the return address.
1035 The variable leaf_function is 1 if the return address is in the register
1036 SRP, and 0 if it is on the stack.
1038 Prologue instructions C-code.
1039 The prologue may consist of (-fno-omit-frame-pointer)
1043 move.d sp,r8 move.d sp,r8
1045 movem rY,[sp] movem rY,[sp]
1046 move.S rZ,[r8-U] move.S rZ,[r8-U]
1048 where 1 is a non-terminal function, and 2 is a leaf-function.
1050 Note that this assumption is extremely brittle, and will break at the
1051 slightest change in GCC's prologue.
1053 If local variables are declared or register contents are saved on stack
1054 the subq-instruction will be present with X as the number of bytes
1055 needed for storage. The reshuffle with respect to r8 may be performed
1056 with any size S (b, w, d) and any of the general registers Z={0..13}.
1057 The offset U should be representable by a signed 8-bit value in all cases.
1058 Thus, the prefix word is assumed to be immediate byte offset mode followed
1059 by another word containing the instruction.
1068 Prologue instructions C++-code.
1069 Case 1) and 2) in the C-code may be followed by
1071 move.d r10,rS ; this
1075 move.S [r8+U],rZ ; P4
1077 if any of the call parameters are stored. The host expects these
1078 instructions to be executed in order to get the call parameters right. */
1080 /* Examine the prologue of a function. The variable ip is the address of
1081 the first instruction of the prologue. The variable limit is the address
1082 of the first instruction after the prologue. The variable fi contains the
1083 information in struct frame_info. The variable frameless_p controls whether
1084 the entire prologue is examined (0) or just enough instructions to
1085 determine that it is a prologue (1). */
1088 cris_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
1089 struct cris_unwind_cache *info)
1091 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1092 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1094 /* Present instruction. */
1095 unsigned short insn;
1097 /* Next instruction, lookahead. */
1098 unsigned short insn_next;
1101 /* Is there a push fp? */
1104 /* Number of byte on stack used for local variables and movem. */
1107 /* Highest register number in a movem. */
1110 /* move.d r<source_register>,rS */
1111 short source_register;
1116 /* This frame is with respect to a leaf until a push srp is found. */
1119 info->leaf_function = 1;
1122 /* Assume nothing on stack. */
1126 /* If we were called without a this_frame, that means we were called
1127 from cris_skip_prologue which already tried to find the end of the
1128 prologue through the symbol information. 64 instructions past current
1129 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
1130 limit = this_frame ? get_frame_pc (this_frame) : pc + 64;
1132 /* Find the prologue instructions. */
1133 while (pc > 0 && pc < limit)
1135 insn = read_memory_unsigned_integer (pc, 2, byte_order);
1139 /* push <reg> 32 bit instruction */
1140 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1142 regno = cris_get_operand2 (insn_next);
1145 info->sp_offset += 4;
1147 /* This check, meant to recognize srp, used to be regno ==
1148 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
1149 if (insn_next == 0xBE7E)
1153 info->leaf_function = 0;
1156 else if (insn_next == 0x8FEE)
1161 info->r8_offset = info->sp_offset;
1165 else if (insn == 0x866E)
1170 info->uses_frame = 1;
1174 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1175 && cris_get_mode (insn) == 0x0000
1176 && cris_get_opcode (insn) == 0x000A)
1181 info->sp_offset += cris_get_quick_value (insn);
1184 else if (cris_get_mode (insn) == 0x0002
1185 && cris_get_opcode (insn) == 0x000F
1186 && cris_get_size (insn) == 0x0003
1187 && cris_get_operand1 (insn) == gdbarch_sp_regnum (gdbarch))
1189 /* movem r<regsave>,[sp] */
1190 regsave = cris_get_operand2 (insn);
1192 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1193 && ((insn & 0x0F00) >> 8) == 0x0001
1194 && (cris_get_signed_offset (insn) < 0))
1196 /* Immediate byte offset addressing prefix word with sp as base
1197 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1198 is between 64 and 128.
1199 movem r<regsave>,[sp=sp-<val>] */
1202 info->sp_offset += -cris_get_signed_offset (insn);
1204 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1206 if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE
1207 && cris_get_opcode (insn_next) == 0x000F
1208 && cris_get_size (insn_next) == 0x0003
1209 && cris_get_operand1 (insn_next) == gdbarch_sp_regnum
1212 regsave = cris_get_operand2 (insn_next);
1216 /* The prologue ended before the limit was reached. */
1221 else if (cris_get_mode (insn) == 0x0001
1222 && cris_get_opcode (insn) == 0x0009
1223 && cris_get_size (insn) == 0x0002)
1225 /* move.d r<10..13>,r<0..15> */
1226 source_register = cris_get_operand1 (insn);
1228 /* FIXME? In the glibc solibs, the prologue might contain something
1229 like (this example taken from relocate_doit):
1231 sub.d 0xfffef426,$r0
1232 which isn't covered by the source_register check below. Question
1233 is whether to add a check for this combo, or make better use of
1234 the limit variable instead. */
1235 if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM)
1237 /* The prologue ended before the limit was reached. */
1242 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1243 /* The size is a fixed-size. */
1244 && ((insn & 0x0F00) >> 8) == 0x0001
1245 /* A negative offset. */
1246 && (cris_get_signed_offset (insn) < 0))
1248 /* move.S rZ,[r8-U] (?) */
1249 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1251 regno = cris_get_operand2 (insn_next);
1252 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1253 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1254 && cris_get_opcode (insn_next) == 0x000F)
1256 /* move.S rZ,[r8-U] */
1261 /* The prologue ended before the limit was reached. */
1266 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1267 /* The size is a fixed-size. */
1268 && ((insn & 0x0F00) >> 8) == 0x0001
1269 /* A positive offset. */
1270 && (cris_get_signed_offset (insn) > 0))
1272 /* move.S [r8+U],rZ (?) */
1273 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1275 regno = cris_get_operand2 (insn_next);
1276 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1277 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1278 && cris_get_opcode (insn_next) == 0x0009
1279 && cris_get_operand1 (insn_next) == regno)
1281 /* move.S [r8+U],rZ */
1286 /* The prologue ended before the limit was reached. */
1293 /* The prologue ended before the limit was reached. */
1299 /* We only want to know the end of the prologue when this_frame and info
1300 are NULL (called from cris_skip_prologue i.e.). */
1301 if (this_frame == NULL && info == NULL)
1306 info->size = info->sp_offset;
1308 /* Compute the previous frame's stack pointer (which is also the
1309 frame's ID's stack address), and this frame's base pointer. */
1310 if (info->uses_frame)
1313 /* The SP was moved to the FP. This indicates that a new frame
1314 was created. Get THIS frame's FP value by unwinding it from
1316 this_base = get_frame_register_unsigned (this_frame, CRIS_FP_REGNUM);
1317 info->base = this_base;
1318 info->saved_regs[CRIS_FP_REGNUM].addr = info->base;
1320 /* The FP points at the last saved register. Adjust the FP back
1321 to before the first saved register giving the SP. */
1322 info->prev_sp = info->base + info->r8_offset;
1327 /* Assume that the FP is this frame's SP but with that pushed
1328 stack space added back. */
1329 this_base = get_frame_register_unsigned (this_frame,
1330 gdbarch_sp_regnum (gdbarch));
1331 info->base = this_base;
1332 info->prev_sp = info->base + info->size;
1335 /* Calculate the addresses for the saved registers on the stack. */
1336 /* FIXME: The address calculation should really be done on the fly while
1337 we're analyzing the prologue (we only hold one regsave value as it is
1339 val = info->sp_offset;
1341 for (regno = regsave; regno >= 0; regno--)
1343 info->saved_regs[regno].addr = info->base + info->r8_offset - val;
1347 /* The previous frame's SP needed to be computed. Save the computed
1349 trad_frame_set_value (info->saved_regs,
1350 gdbarch_sp_regnum (gdbarch), info->prev_sp);
1352 if (!info->leaf_function)
1354 /* SRP saved on the stack. But where? */
1355 if (info->r8_offset == 0)
1357 /* R8 not pushed yet. */
1358 info->saved_regs[SRP_REGNUM].addr = info->base;
1362 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1363 info->saved_regs[SRP_REGNUM].addr = info->base + 4;
1367 /* The PC is found in SRP (the actual register or located on the stack). */
1368 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1369 = info->saved_regs[SRP_REGNUM];
1375 crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
1376 struct cris_unwind_cache *info)
1378 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1381 /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not
1382 meant to be a full-fledged prologue scanner. It is only needed for
1383 the cases where we end up in code always lacking DWARF-2 CFI, notably:
1385 * PLT stubs (library calls)
1387 * signal trampolines
1389 For those cases, it is assumed that there is no actual prologue; that
1390 the stack pointer is not adjusted, and (as a consequence) the return
1391 address is not pushed onto the stack. */
1393 /* We only want to know the end of the prologue when this_frame and info
1394 are NULL (called from cris_skip_prologue i.e.). */
1395 if (this_frame == NULL && info == NULL)
1400 /* The SP is assumed to be unaltered. */
1401 this_base = get_frame_register_unsigned (this_frame,
1402 gdbarch_sp_regnum (gdbarch));
1403 info->base = this_base;
1404 info->prev_sp = this_base;
1406 /* The PC is assumed to be found in SRP. */
1407 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1408 = info->saved_regs[SRP_REGNUM];
1413 /* Advance pc beyond any function entry prologue instructions at pc
1414 to reach some "real" code. */
1416 /* Given a PC value corresponding to the start of a function, return the PC
1417 of the first instruction after the function prologue. */
1420 cris_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1422 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1423 CORE_ADDR func_addr, func_end;
1424 struct symtab_and_line sal;
1425 CORE_ADDR pc_after_prologue;
1427 /* If we have line debugging information, then the end of the prologue
1428 should the first assembly instruction of the first source line. */
1429 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1431 sal = find_pc_line (func_addr, 0);
1432 if (sal.end > 0 && sal.end < func_end)
1436 if (tdep->cris_version == 32)
1437 pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL);
1439 pc_after_prologue = cris_scan_prologue (pc, NULL, NULL);
1441 return pc_after_prologue;
1445 cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1448 pc = frame_unwind_register_unsigned (next_frame,
1449 gdbarch_pc_regnum (gdbarch));
1454 cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1457 sp = frame_unwind_register_unsigned (next_frame,
1458 gdbarch_sp_regnum (gdbarch));
1462 /* Use the program counter to determine the contents and size of a breakpoint
1463 instruction. It returns a pointer to a string of bytes that encode a
1464 breakpoint instruction, stores the length of the string to *lenptr, and
1465 adjusts pcptr (if necessary) to point to the actual memory location where
1466 the breakpoint should be inserted. */
1468 static const unsigned char *
1469 cris_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
1471 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1472 static unsigned char break8_insn[] = {0x38, 0xe9};
1473 static unsigned char break15_insn[] = {0x3f, 0xe9};
1476 if (tdep->cris_mode == cris_mode_guru)
1477 return break15_insn;
1482 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1486 cris_spec_reg_applicable (struct gdbarch *gdbarch,
1487 struct cris_spec_reg spec_reg)
1489 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1490 int version = tdep->cris_version;
1492 switch (spec_reg.applicable_version)
1494 case cris_ver_version_all:
1496 case cris_ver_warning:
1497 /* Indeterminate/obsolete. */
1500 return (version >= 0 && version <= 3);
1502 return (version >= 3);
1504 return (version == 8 || version == 9);
1506 return (version >= 8);
1507 case cris_ver_v0_10:
1508 return (version >= 0 && version <= 10);
1509 case cris_ver_v3_10:
1510 return (version >= 3 && version <= 10);
1511 case cris_ver_v8_10:
1512 return (version >= 8 && version <= 10);
1514 return (version == 10);
1516 return (version >= 10);
1518 return (version >= 32);
1520 /* Invalid cris version. */
1525 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1526 register, -1 for an invalid register. */
1529 cris_register_size (struct gdbarch *gdbarch, int regno)
1531 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1535 if (regno >= 0 && regno < NUM_GENREGS)
1537 /* General registers (R0 - R15) are 32 bits. */
1540 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1542 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1543 Adjust regno accordingly. */
1544 spec_regno = regno - NUM_GENREGS;
1546 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1548 if (cris_spec_regs[i].number == spec_regno
1549 && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i]))
1550 /* Go with the first applicable register. */
1551 return cris_spec_regs[i].reg_size;
1553 /* Special register not applicable to this CRIS version. */
1556 else if (regno >= gdbarch_pc_regnum (gdbarch)
1557 && regno < gdbarch_num_regs (gdbarch))
1559 /* This will apply to CRISv32 only where there are additional registers
1560 after the special registers (pseudo PC and support registers). */
1568 /* Nonzero if regno should not be fetched from the target. This is the case
1569 for unimplemented (size 0) and non-existant registers. */
1572 cris_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1574 return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1575 || (cris_register_size (gdbarch, regno) == 0));
1578 /* Nonzero if regno should not be written to the target, for various
1582 cris_cannot_store_register (struct gdbarch *gdbarch, int regno)
1584 /* There are three kinds of registers we refuse to write to.
1585 1. Those that not implemented.
1586 2. Those that are read-only (depends on the processor mode).
1587 3. Those registers to which a write has no effect.
1591 || regno >= gdbarch_num_regs (gdbarch)
1592 || cris_register_size (gdbarch, regno) == 0)
1593 /* Not implemented. */
1596 else if (regno == VR_REGNUM)
1600 else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM)
1601 /* Writing has no effect. */
1604 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
1605 agent decide whether they are writable. */
1610 /* Nonzero if regno should not be fetched from the target. This is the case
1611 for unimplemented (size 0) and non-existant registers. */
1614 crisv32_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1616 return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1617 || (cris_register_size (gdbarch, regno) == 0));
1620 /* Nonzero if regno should not be written to the target, for various
1624 crisv32_cannot_store_register (struct gdbarch *gdbarch, int regno)
1626 /* There are three kinds of registers we refuse to write to.
1627 1. Those that not implemented.
1628 2. Those that are read-only (depends on the processor mode).
1629 3. Those registers to which a write has no effect.
1633 || regno >= gdbarch_num_regs (gdbarch)
1634 || cris_register_size (gdbarch, regno) == 0)
1635 /* Not implemented. */
1638 else if (regno == VR_REGNUM)
1642 else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM)
1643 /* Writing has no effect. */
1646 /* Many special registers are read-only in user mode. Let the debug
1647 agent decide whether they are writable. */
1652 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1653 of data in register regno. */
1655 static struct type *
1656 cris_register_type (struct gdbarch *gdbarch, int regno)
1658 if (regno == gdbarch_pc_regnum (gdbarch))
1659 return builtin_type (gdbarch)->builtin_func_ptr;
1660 else if (regno == gdbarch_sp_regnum (gdbarch)
1661 || regno == CRIS_FP_REGNUM)
1662 return builtin_type (gdbarch)->builtin_data_ptr;
1663 else if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1664 || (regno >= MOF_REGNUM && regno <= USP_REGNUM))
1665 /* Note: R8 taken care of previous clause. */
1666 return builtin_type (gdbarch)->builtin_uint32;
1667 else if (regno >= P4_REGNUM && regno <= CCR_REGNUM)
1668 return builtin_type (gdbarch)->builtin_uint16;
1669 else if (regno >= P0_REGNUM && regno <= VR_REGNUM)
1670 return builtin_type (gdbarch)->builtin_uint8;
1672 /* Invalid (unimplemented) register. */
1673 return builtin_type (gdbarch)->builtin_int0;
1676 static struct type *
1677 crisv32_register_type (struct gdbarch *gdbarch, int regno)
1679 if (regno == gdbarch_pc_regnum (gdbarch))
1680 return builtin_type (gdbarch)->builtin_func_ptr;
1681 else if (regno == gdbarch_sp_regnum (gdbarch)
1682 || regno == CRIS_FP_REGNUM)
1683 return builtin_type (gdbarch)->builtin_data_ptr;
1684 else if ((regno >= 0 && regno <= ACR_REGNUM)
1685 || (regno >= EXS_REGNUM && regno <= SPC_REGNUM)
1686 || (regno == PID_REGNUM)
1687 || (regno >= S0_REGNUM && regno <= S15_REGNUM))
1688 /* Note: R8 and SP taken care of by previous clause. */
1689 return builtin_type (gdbarch)->builtin_uint32;
1690 else if (regno == WZ_REGNUM)
1691 return builtin_type (gdbarch)->builtin_uint16;
1692 else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM)
1693 return builtin_type (gdbarch)->builtin_uint8;
1696 /* Invalid (unimplemented) register. Should not happen as there are
1697 no unimplemented CRISv32 registers. */
1698 warning (_("crisv32_register_type: unknown regno %d"), regno);
1699 return builtin_type (gdbarch)->builtin_int0;
1703 /* Stores a function return value of type type, where valbuf is the address
1704 of the value to be stored. */
1706 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1709 cris_store_return_value (struct type *type, struct regcache *regcache,
1712 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1713 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1715 int len = TYPE_LENGTH (type);
1719 /* Put the return value in R10. */
1720 val = extract_unsigned_integer (valbuf, len, byte_order);
1721 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1725 /* Put the return value in R10 and R11. */
1726 val = extract_unsigned_integer (valbuf, 4, byte_order);
1727 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1728 val = extract_unsigned_integer ((char *)valbuf + 4, len - 4, byte_order);
1729 regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val);
1732 error (_("cris_store_return_value: type length too large."));
1735 /* Return the name of register regno as a string. Return NULL for an invalid or
1736 unimplemented register. */
1739 cris_special_register_name (struct gdbarch *gdbarch, int regno)
1744 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1745 Adjust regno accordingly. */
1746 spec_regno = regno - NUM_GENREGS;
1748 /* Assume nothing about the layout of the cris_spec_regs struct
1750 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1752 if (cris_spec_regs[i].number == spec_regno
1753 && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i]))
1754 /* Go with the first applicable register. */
1755 return cris_spec_regs[i].name;
1757 /* Special register not applicable to this CRIS version. */
1762 cris_register_name (struct gdbarch *gdbarch, int regno)
1764 static char *cris_genreg_names[] =
1765 { "r0", "r1", "r2", "r3", \
1766 "r4", "r5", "r6", "r7", \
1767 "r8", "r9", "r10", "r11", \
1768 "r12", "r13", "sp", "pc" };
1770 if (regno >= 0 && regno < NUM_GENREGS)
1772 /* General register. */
1773 return cris_genreg_names[regno];
1775 else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (gdbarch))
1777 return cris_special_register_name (gdbarch, regno);
1781 /* Invalid register. */
1787 crisv32_register_name (struct gdbarch *gdbarch, int regno)
1789 static char *crisv32_genreg_names[] =
1790 { "r0", "r1", "r2", "r3", \
1791 "r4", "r5", "r6", "r7", \
1792 "r8", "r9", "r10", "r11", \
1793 "r12", "r13", "sp", "acr"
1796 static char *crisv32_sreg_names[] =
1797 { "s0", "s1", "s2", "s3", \
1798 "s4", "s5", "s6", "s7", \
1799 "s8", "s9", "s10", "s11", \
1800 "s12", "s13", "s14", "s15"
1803 if (regno >= 0 && regno < NUM_GENREGS)
1805 /* General register. */
1806 return crisv32_genreg_names[regno];
1808 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1810 return cris_special_register_name (gdbarch, regno);
1812 else if (regno == gdbarch_pc_regnum (gdbarch))
1816 else if (regno >= S0_REGNUM && regno <= S15_REGNUM)
1818 return crisv32_sreg_names[regno - S0_REGNUM];
1822 /* Invalid register. */
1827 /* Convert DWARF register number REG to the appropriate register
1828 number used by GDB. */
1831 cris_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1833 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1834 numbering, MOF is 18).
1835 Adapted from gcc/config/cris/cris.h. */
1836 static int cris_dwarf_regmap[] = {
1848 if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap))
1849 regnum = cris_dwarf_regmap[reg];
1852 warning (_("Unmapped DWARF Register #%d encountered."), reg);
1857 /* DWARF-2 frame support. */
1860 cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1861 struct dwarf2_frame_state_reg *reg,
1862 struct frame_info *this_frame)
1864 /* The return address column. */
1865 if (regnum == gdbarch_pc_regnum (gdbarch))
1866 reg->how = DWARF2_FRAME_REG_RA;
1868 /* The call frame address. */
1869 else if (regnum == gdbarch_sp_regnum (gdbarch))
1870 reg->how = DWARF2_FRAME_REG_CFA;
1873 /* Extract from an array regbuf containing the raw register state a function
1874 return value of type type, and copy that, in virtual format, into
1877 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1880 cris_extract_return_value (struct type *type, struct regcache *regcache,
1883 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1884 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1886 int len = TYPE_LENGTH (type);
1890 /* Get the return value from R10. */
1891 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1892 store_unsigned_integer (valbuf, len, byte_order, val);
1896 /* Get the return value from R10 and R11. */
1897 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1898 store_unsigned_integer (valbuf, 4, byte_order, val);
1899 regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val);
1900 store_unsigned_integer ((char *)valbuf + 4, len - 4, byte_order, val);
1903 error (_("cris_extract_return_value: type length too large"));
1906 /* Handle the CRIS return value convention. */
1908 static enum return_value_convention
1909 cris_return_value (struct gdbarch *gdbarch, struct type *func_type,
1910 struct type *type, struct regcache *regcache,
1911 gdb_byte *readbuf, const gdb_byte *writebuf)
1913 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1914 || TYPE_CODE (type) == TYPE_CODE_UNION
1915 || TYPE_LENGTH (type) > 8)
1916 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1917 goes on the stack. */
1918 return RETURN_VALUE_STRUCT_CONVENTION;
1921 cris_extract_return_value (type, regcache, readbuf);
1923 cris_store_return_value (type, regcache, writebuf);
1925 return RETURN_VALUE_REGISTER_CONVENTION;
1928 /* Calculates a value that measures how good inst_args constraints an
1929 instruction. It stems from cris_constraint, found in cris-dis.c. */
1932 constraint (unsigned int insn, const signed char *inst_args,
1933 inst_env_type *inst_env)
1938 const char *s = inst_args;
1944 if ((insn & 0x30) == 0x30)
1949 /* A prefix operand. */
1950 if (inst_env->prefix_found)
1956 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1957 valid "push" size. In case of special register, it may be != 4. */
1958 if (inst_env->prefix_found)
1964 retval = (((insn >> 0xC) & 0xF) == (insn & 0xF));
1972 tmp = (insn >> 0xC) & 0xF;
1974 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1976 /* Since we match four bits, we will give a value of
1977 4 - 1 = 3 in a match. If there is a corresponding
1978 exact match of a special register in another pattern, it
1979 will get a value of 4, which will be higher. This should
1980 be correct in that an exact pattern would match better that
1982 Note that there is a reason for not returning zero; the
1983 pattern for "clear" is partly matched in the bit-pattern
1984 (the two lower bits must be zero), while the bit-pattern
1985 for a move from a special register is matched in the
1986 register constraint.
1987 This also means we will will have a race condition if
1988 there is a partly match in three bits in the bit pattern. */
1989 if (tmp == cris_spec_regs[i].number)
1996 if (cris_spec_regs[i].name == NULL)
2003 /* Returns the number of bits set in the variable value. */
2006 number_of_bits (unsigned int value)
2008 int number_of_bits = 0;
2012 number_of_bits += 1;
2013 value &= (value - 1);
2015 return number_of_bits;
2018 /* Finds the address that should contain the single step breakpoint(s).
2019 It stems from code in cris-dis.c. */
2022 find_cris_op (unsigned short insn, inst_env_type *inst_env)
2025 int max_level_of_match = -1;
2026 int max_matched = -1;
2029 for (i = 0; cris_opcodes[i].name != NULL; i++)
2031 if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match)
2032 && ((cris_opcodes[i].lose & insn) == 0)
2033 /* Only CRISv10 instructions, please. */
2034 && (cris_opcodes[i].applicable_version != cris_ver_v32p))
2036 level_of_match = constraint (insn, cris_opcodes[i].args, inst_env);
2037 if (level_of_match >= 0)
2040 number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose);
2041 if (level_of_match > max_level_of_match)
2044 max_level_of_match = level_of_match;
2045 if (level_of_match == 16)
2047 /* All bits matched, cannot find better. */
2057 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
2058 actually an internal error. */
2061 find_step_target (struct frame_info *frame, inst_env_type *inst_env)
2065 unsigned short insn;
2066 struct gdbarch *gdbarch = get_frame_arch (frame);
2067 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2069 /* Create a local register image and set the initial state. */
2070 for (i = 0; i < NUM_GENREGS; i++)
2073 (unsigned long) get_frame_register_unsigned (frame, i);
2075 offset = NUM_GENREGS;
2076 for (i = 0; i < NUM_SPECREGS; i++)
2079 (unsigned long) get_frame_register_unsigned (frame, offset + i);
2081 inst_env->branch_found = 0;
2082 inst_env->slot_needed = 0;
2083 inst_env->delay_slot_pc_active = 0;
2084 inst_env->prefix_found = 0;
2085 inst_env->invalid = 0;
2086 inst_env->xflag_found = 0;
2087 inst_env->disable_interrupt = 0;
2088 inst_env->byte_order = byte_order;
2090 /* Look for a step target. */
2093 /* Read an instruction from the client. */
2094 insn = read_memory_unsigned_integer
2095 (inst_env->reg[gdbarch_pc_regnum (gdbarch)], 2, byte_order);
2097 /* If the instruction is not in a delay slot the new content of the
2098 PC is [PC] + 2. If the instruction is in a delay slot it is not
2099 that simple. Since a instruction in a delay slot cannot change
2100 the content of the PC, it does not matter what value PC will have.
2101 Just make sure it is a valid instruction. */
2102 if (!inst_env->delay_slot_pc_active)
2104 inst_env->reg[gdbarch_pc_regnum (gdbarch)] += 2;
2108 inst_env->delay_slot_pc_active = 0;
2109 inst_env->reg[gdbarch_pc_regnum (gdbarch)]
2110 = inst_env->delay_slot_pc;
2112 /* Analyse the present instruction. */
2113 i = find_cris_op (insn, inst_env);
2116 inst_env->invalid = 1;
2120 cris_gdb_func (gdbarch, cris_opcodes[i].op, insn, inst_env);
2122 } while (!inst_env->invalid
2123 && (inst_env->prefix_found || inst_env->xflag_found
2124 || inst_env->slot_needed));
2128 /* There is no hardware single-step support. The function find_step_target
2129 digs through the opcodes in order to find all possible targets.
2130 Either one ordinary target or two targets for branches may be found. */
2133 cris_software_single_step (struct frame_info *frame)
2135 struct gdbarch *gdbarch = get_frame_arch (frame);
2136 inst_env_type inst_env;
2138 /* Analyse the present instruction environment and insert
2140 int status = find_step_target (frame, &inst_env);
2143 /* Could not find a target. Things are likely to go downhill
2145 warning (_("CRIS software single step could not find a step target."));
2149 /* Insert at most two breakpoints. One for the next PC content
2150 and possibly another one for a branch, jump, etc. */
2152 = (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (gdbarch)];
2153 insert_single_step_breakpoint (gdbarch, next_pc);
2154 if (inst_env.branch_found
2155 && (CORE_ADDR) inst_env.branch_break_address != next_pc)
2157 CORE_ADDR branch_target_address
2158 = (CORE_ADDR) inst_env.branch_break_address;
2159 insert_single_step_breakpoint (gdbarch, branch_target_address);
2166 /* Calculates the prefix value for quick offset addressing mode. */
2169 quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2171 /* It's invalid to be in a delay slot. You can't have a prefix to this
2172 instruction (not 100% sure). */
2173 if (inst_env->slot_needed || inst_env->prefix_found)
2175 inst_env->invalid = 1;
2179 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2180 inst_env->prefix_value += cris_get_bdap_quick_offset (inst);
2182 /* A prefix doesn't change the xflag_found. But the rest of the flags
2184 inst_env->slot_needed = 0;
2185 inst_env->prefix_found = 1;
2188 /* Updates the autoincrement register. The size of the increment is derived
2189 from the size of the operation. The PC is always kept aligned on even
2193 process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env)
2195 if (size == INST_BYTE_SIZE)
2197 inst_env->reg[cris_get_operand1 (inst)] += 1;
2199 /* The PC must be word aligned, so increase the PC with one
2200 word even if the size is byte. */
2201 if (cris_get_operand1 (inst) == REG_PC)
2203 inst_env->reg[REG_PC] += 1;
2206 else if (size == INST_WORD_SIZE)
2208 inst_env->reg[cris_get_operand1 (inst)] += 2;
2210 else if (size == INST_DWORD_SIZE)
2212 inst_env->reg[cris_get_operand1 (inst)] += 4;
2217 inst_env->invalid = 1;
2221 /* Just a forward declaration. */
2223 static unsigned long get_data_from_address (unsigned short *inst,
2225 enum bfd_endian byte_order);
2227 /* Calculates the prefix value for the general case of offset addressing
2231 bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2236 /* It's invalid to be in a delay slot. */
2237 if (inst_env->slot_needed || inst_env->prefix_found)
2239 inst_env->invalid = 1;
2243 /* The calculation of prefix_value used to be after process_autoincrement,
2244 but that fails for an instruction such as jsr [$r0+12] which is encoded
2245 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
2246 mustn't be incremented until we have read it and what it points at. */
2247 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2249 /* The offset is an indirection of the contents of the operand1 register. */
2250 inst_env->prefix_value +=
2251 get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)],
2252 inst_env->byte_order);
2254 if (cris_get_mode (inst) == AUTOINC_MODE)
2256 process_autoincrement (cris_get_size (inst), inst, inst_env);
2259 /* A prefix doesn't change the xflag_found. But the rest of the flags
2261 inst_env->slot_needed = 0;
2262 inst_env->prefix_found = 1;
2265 /* Calculates the prefix value for the index addressing mode. */
2268 biap_prefix (unsigned short inst, inst_env_type *inst_env)
2270 /* It's invalid to be in a delay slot. I can't see that it's possible to
2271 have a prefix to this instruction. So I will treat this as invalid. */
2272 if (inst_env->slot_needed || inst_env->prefix_found)
2274 inst_env->invalid = 1;
2278 inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)];
2280 /* The offset is the operand2 value shifted the size of the instruction
2282 inst_env->prefix_value +=
2283 inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst);
2285 /* If the PC is operand1 (base) the address used is the address after
2286 the main instruction, i.e. address + 2 (the PC is already compensated
2287 for the prefix operation). */
2288 if (cris_get_operand1 (inst) == REG_PC)
2290 inst_env->prefix_value += 2;
2293 /* A prefix doesn't change the xflag_found. But the rest of the flags
2295 inst_env->slot_needed = 0;
2296 inst_env->xflag_found = 0;
2297 inst_env->prefix_found = 1;
2300 /* Calculates the prefix value for the double indirect addressing mode. */
2303 dip_prefix (unsigned short inst, inst_env_type *inst_env)
2308 /* It's invalid to be in a delay slot. */
2309 if (inst_env->slot_needed || inst_env->prefix_found)
2311 inst_env->invalid = 1;
2315 /* The prefix value is one dereference of the contents of the operand1
2317 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2318 inst_env->prefix_value
2319 = read_memory_unsigned_integer (address, 4, inst_env->byte_order);
2321 /* Check if the mode is autoincrement. */
2322 if (cris_get_mode (inst) == AUTOINC_MODE)
2324 inst_env->reg[cris_get_operand1 (inst)] += 4;
2327 /* A prefix doesn't change the xflag_found. But the rest of the flags
2329 inst_env->slot_needed = 0;
2330 inst_env->xflag_found = 0;
2331 inst_env->prefix_found = 1;
2334 /* Finds the destination for a branch with 8-bits offset. */
2337 eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2342 /* If we have a prefix or are in a delay slot it's bad. */
2343 if (inst_env->slot_needed || inst_env->prefix_found)
2345 inst_env->invalid = 1;
2349 /* We have a branch, find out where the branch will land. */
2350 offset = cris_get_branch_short_offset (inst);
2352 /* Check if the offset is signed. */
2353 if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK)
2358 /* The offset ends with the sign bit, set it to zero. The address
2359 should always be word aligned. */
2360 offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK;
2362 inst_env->branch_found = 1;
2363 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2365 inst_env->slot_needed = 1;
2366 inst_env->prefix_found = 0;
2367 inst_env->xflag_found = 0;
2368 inst_env->disable_interrupt = 1;
2371 /* Finds the destination for a branch with 16-bits offset. */
2374 sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2378 /* If we have a prefix or is in a delay slot it's bad. */
2379 if (inst_env->slot_needed || inst_env->prefix_found)
2381 inst_env->invalid = 1;
2385 /* We have a branch, find out the offset for the branch. */
2386 offset = read_memory_integer (inst_env->reg[REG_PC], 2, inst_env->byte_order);
2388 /* The instruction is one word longer than normal, so add one word
2390 inst_env->reg[REG_PC] += 2;
2392 inst_env->branch_found = 1;
2393 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2396 inst_env->slot_needed = 1;
2397 inst_env->prefix_found = 0;
2398 inst_env->xflag_found = 0;
2399 inst_env->disable_interrupt = 1;
2402 /* Handles the ABS instruction. */
2405 abs_op (unsigned short inst, inst_env_type *inst_env)
2410 /* ABS can't have a prefix, so it's bad if it does. */
2411 if (inst_env->prefix_found)
2413 inst_env->invalid = 1;
2417 /* Check if the operation affects the PC. */
2418 if (cris_get_operand2 (inst) == REG_PC)
2421 /* It's invalid to change to the PC if we are in a delay slot. */
2422 if (inst_env->slot_needed)
2424 inst_env->invalid = 1;
2428 value = (long) inst_env->reg[REG_PC];
2430 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
2431 if (value != SIGNED_DWORD_MASK)
2434 inst_env->reg[REG_PC] = (long) value;
2438 inst_env->slot_needed = 0;
2439 inst_env->prefix_found = 0;
2440 inst_env->xflag_found = 0;
2441 inst_env->disable_interrupt = 0;
2444 /* Handles the ADDI instruction. */
2447 addi_op (unsigned short inst, inst_env_type *inst_env)
2449 /* It's invalid to have the PC as base register. And ADDI can't have
2451 if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC))
2453 inst_env->invalid = 1;
2457 inst_env->slot_needed = 0;
2458 inst_env->prefix_found = 0;
2459 inst_env->xflag_found = 0;
2460 inst_env->disable_interrupt = 0;
2463 /* Handles the ASR instruction. */
2466 asr_op (unsigned short inst, inst_env_type *inst_env)
2469 unsigned long value;
2470 unsigned long signed_extend_mask = 0;
2472 /* ASR can't have a prefix, so check that it doesn't. */
2473 if (inst_env->prefix_found)
2475 inst_env->invalid = 1;
2479 /* Check if the PC is the target register. */
2480 if (cris_get_operand2 (inst) == REG_PC)
2482 /* It's invalid to change the PC in a delay slot. */
2483 if (inst_env->slot_needed)
2485 inst_env->invalid = 1;
2488 /* Get the number of bits to shift. */
2489 shift_steps = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]);
2490 value = inst_env->reg[REG_PC];
2492 /* Find out how many bits the operation should apply to. */
2493 if (cris_get_size (inst) == INST_BYTE_SIZE)
2495 if (value & SIGNED_BYTE_MASK)
2497 signed_extend_mask = 0xFF;
2498 signed_extend_mask = signed_extend_mask >> shift_steps;
2499 signed_extend_mask = ~signed_extend_mask;
2501 value = value >> shift_steps;
2502 value |= signed_extend_mask;
2504 inst_env->reg[REG_PC] &= 0xFFFFFF00;
2505 inst_env->reg[REG_PC] |= value;
2507 else if (cris_get_size (inst) == INST_WORD_SIZE)
2509 if (value & SIGNED_WORD_MASK)
2511 signed_extend_mask = 0xFFFF;
2512 signed_extend_mask = signed_extend_mask >> shift_steps;
2513 signed_extend_mask = ~signed_extend_mask;
2515 value = value >> shift_steps;
2516 value |= signed_extend_mask;
2518 inst_env->reg[REG_PC] &= 0xFFFF0000;
2519 inst_env->reg[REG_PC] |= value;
2521 else if (cris_get_size (inst) == INST_DWORD_SIZE)
2523 if (value & SIGNED_DWORD_MASK)
2525 signed_extend_mask = 0xFFFFFFFF;
2526 signed_extend_mask = signed_extend_mask >> shift_steps;
2527 signed_extend_mask = ~signed_extend_mask;
2529 value = value >> shift_steps;
2530 value |= signed_extend_mask;
2531 inst_env->reg[REG_PC] = value;
2534 inst_env->slot_needed = 0;
2535 inst_env->prefix_found = 0;
2536 inst_env->xflag_found = 0;
2537 inst_env->disable_interrupt = 0;
2540 /* Handles the ASRQ instruction. */
2543 asrq_op (unsigned short inst, inst_env_type *inst_env)
2547 unsigned long value;
2548 unsigned long signed_extend_mask = 0;
2550 /* ASRQ can't have a prefix, so check that it doesn't. */
2551 if (inst_env->prefix_found)
2553 inst_env->invalid = 1;
2557 /* Check if the PC is the target register. */
2558 if (cris_get_operand2 (inst) == REG_PC)
2561 /* It's invalid to change the PC in a delay slot. */
2562 if (inst_env->slot_needed)
2564 inst_env->invalid = 1;
2567 /* The shift size is given as a 5 bit quick value, i.e. we don't
2568 want the the sign bit of the quick value. */
2569 shift_steps = cris_get_asr_shift_steps (inst);
2570 value = inst_env->reg[REG_PC];
2571 if (value & SIGNED_DWORD_MASK)
2573 signed_extend_mask = 0xFFFFFFFF;
2574 signed_extend_mask = signed_extend_mask >> shift_steps;
2575 signed_extend_mask = ~signed_extend_mask;
2577 value = value >> shift_steps;
2578 value |= signed_extend_mask;
2579 inst_env->reg[REG_PC] = value;
2581 inst_env->slot_needed = 0;
2582 inst_env->prefix_found = 0;
2583 inst_env->xflag_found = 0;
2584 inst_env->disable_interrupt = 0;
2587 /* Handles the AX, EI and SETF instruction. */
2590 ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env)
2592 if (inst_env->prefix_found)
2594 inst_env->invalid = 1;
2597 /* Check if the instruction is setting the X flag. */
2598 if (cris_is_xflag_bit_on (inst))
2600 inst_env->xflag_found = 1;
2604 inst_env->xflag_found = 0;
2606 inst_env->slot_needed = 0;
2607 inst_env->prefix_found = 0;
2608 inst_env->disable_interrupt = 1;
2611 /* Checks if the instruction is in assign mode. If so, it updates the assign
2612 register. Note that check_assign assumes that the caller has checked that
2613 there is a prefix to this instruction. The mode check depends on this. */
2616 check_assign (unsigned short inst, inst_env_type *inst_env)
2618 /* Check if it's an assign addressing mode. */
2619 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2621 /* Assign the prefix value to operand 1. */
2622 inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value;
2626 /* Handles the 2-operand BOUND instruction. */
2629 two_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2631 /* It's invalid to have the PC as the index operand. */
2632 if (cris_get_operand2 (inst) == REG_PC)
2634 inst_env->invalid = 1;
2637 /* Check if we have a prefix. */
2638 if (inst_env->prefix_found)
2640 check_assign (inst, inst_env);
2642 /* Check if this is an autoincrement mode. */
2643 else if (cris_get_mode (inst) == AUTOINC_MODE)
2645 /* It's invalid to change the PC in a delay slot. */
2646 if (inst_env->slot_needed)
2648 inst_env->invalid = 1;
2651 process_autoincrement (cris_get_size (inst), inst, inst_env);
2653 inst_env->slot_needed = 0;
2654 inst_env->prefix_found = 0;
2655 inst_env->xflag_found = 0;
2656 inst_env->disable_interrupt = 0;
2659 /* Handles the 3-operand BOUND instruction. */
2662 three_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2664 /* It's an error if we haven't got a prefix. And it's also an error
2665 if the PC is the destination register. */
2666 if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC))
2668 inst_env->invalid = 1;
2671 inst_env->slot_needed = 0;
2672 inst_env->prefix_found = 0;
2673 inst_env->xflag_found = 0;
2674 inst_env->disable_interrupt = 0;
2677 /* Clears the status flags in inst_env. */
2680 btst_nop_op (unsigned short inst, inst_env_type *inst_env)
2682 /* It's an error if we have got a prefix. */
2683 if (inst_env->prefix_found)
2685 inst_env->invalid = 1;
2689 inst_env->slot_needed = 0;
2690 inst_env->prefix_found = 0;
2691 inst_env->xflag_found = 0;
2692 inst_env->disable_interrupt = 0;
2695 /* Clears the status flags in inst_env. */
2698 clearf_di_op (unsigned short inst, inst_env_type *inst_env)
2700 /* It's an error if we have got a prefix. */
2701 if (inst_env->prefix_found)
2703 inst_env->invalid = 1;
2707 inst_env->slot_needed = 0;
2708 inst_env->prefix_found = 0;
2709 inst_env->xflag_found = 0;
2710 inst_env->disable_interrupt = 1;
2713 /* Handles the CLEAR instruction if it's in register mode. */
2716 reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env)
2718 /* Check if the target is the PC. */
2719 if (cris_get_operand2 (inst) == REG_PC)
2721 /* The instruction will clear the instruction's size bits. */
2722 int clear_size = cris_get_clear_size (inst);
2723 if (clear_size == INST_BYTE_SIZE)
2725 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00;
2727 if (clear_size == INST_WORD_SIZE)
2729 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000;
2731 if (clear_size == INST_DWORD_SIZE)
2733 inst_env->delay_slot_pc = 0x0;
2735 /* The jump will be delayed with one delay slot. So we need a delay
2737 inst_env->slot_needed = 1;
2738 inst_env->delay_slot_pc_active = 1;
2742 /* The PC will not change => no delay slot. */
2743 inst_env->slot_needed = 0;
2745 inst_env->prefix_found = 0;
2746 inst_env->xflag_found = 0;
2747 inst_env->disable_interrupt = 0;
2750 /* Handles the TEST instruction if it's in register mode. */
2753 reg_mode_test_op (unsigned short inst, inst_env_type *inst_env)
2755 /* It's an error if we have got a prefix. */
2756 if (inst_env->prefix_found)
2758 inst_env->invalid = 1;
2761 inst_env->slot_needed = 0;
2762 inst_env->prefix_found = 0;
2763 inst_env->xflag_found = 0;
2764 inst_env->disable_interrupt = 0;
2768 /* Handles the CLEAR and TEST instruction if the instruction isn't
2769 in register mode. */
2772 none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env)
2774 /* Check if we are in a prefix mode. */
2775 if (inst_env->prefix_found)
2777 /* The only way the PC can change is if this instruction is in
2778 assign addressing mode. */
2779 check_assign (inst, inst_env);
2781 /* Indirect mode can't change the PC so just check if the mode is
2783 else if (cris_get_mode (inst) == AUTOINC_MODE)
2785 process_autoincrement (cris_get_size (inst), inst, inst_env);
2787 inst_env->slot_needed = 0;
2788 inst_env->prefix_found = 0;
2789 inst_env->xflag_found = 0;
2790 inst_env->disable_interrupt = 0;
2793 /* Checks that the PC isn't the destination register or the instructions has
2797 dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env)
2799 /* It's invalid to have the PC as the destination. The instruction can't
2801 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2803 inst_env->invalid = 1;
2807 inst_env->slot_needed = 0;
2808 inst_env->prefix_found = 0;
2809 inst_env->xflag_found = 0;
2810 inst_env->disable_interrupt = 0;
2813 /* Checks that the instruction doesn't have a prefix. */
2816 break_op (unsigned short inst, inst_env_type *inst_env)
2818 /* The instruction can't have a prefix. */
2819 if (inst_env->prefix_found)
2821 inst_env->invalid = 1;
2825 inst_env->slot_needed = 0;
2826 inst_env->prefix_found = 0;
2827 inst_env->xflag_found = 0;
2828 inst_env->disable_interrupt = 1;
2831 /* Checks that the PC isn't the destination register and that the instruction
2832 doesn't have a prefix. */
2835 scc_op (unsigned short inst, inst_env_type *inst_env)
2837 /* It's invalid to have the PC as the destination. The instruction can't
2839 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2841 inst_env->invalid = 1;
2845 inst_env->slot_needed = 0;
2846 inst_env->prefix_found = 0;
2847 inst_env->xflag_found = 0;
2848 inst_env->disable_interrupt = 1;
2851 /* Handles the register mode JUMP instruction. */
2854 reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2856 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2857 you can't have a prefix. */
2858 if ((inst_env->slot_needed) || (inst_env->prefix_found))
2860 inst_env->invalid = 1;
2864 /* Just change the PC. */
2865 inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)];
2866 inst_env->slot_needed = 0;
2867 inst_env->prefix_found = 0;
2868 inst_env->xflag_found = 0;
2869 inst_env->disable_interrupt = 1;
2872 /* Handles the JUMP instruction for all modes except register. */
2875 none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2877 unsigned long newpc;
2880 /* It's invalid to do a JUMP in a delay slot. */
2881 if (inst_env->slot_needed)
2883 inst_env->invalid = 1;
2887 /* Check if we have a prefix. */
2888 if (inst_env->prefix_found)
2890 check_assign (inst, inst_env);
2892 /* Get the new value for the the PC. */
2894 read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value,
2895 4, inst_env->byte_order);
2899 /* Get the new value for the PC. */
2900 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2901 newpc = read_memory_unsigned_integer (address,
2902 4, inst_env->byte_order);
2904 /* Check if we should increment a register. */
2905 if (cris_get_mode (inst) == AUTOINC_MODE)
2907 inst_env->reg[cris_get_operand1 (inst)] += 4;
2910 inst_env->reg[REG_PC] = newpc;
2912 inst_env->slot_needed = 0;
2913 inst_env->prefix_found = 0;
2914 inst_env->xflag_found = 0;
2915 inst_env->disable_interrupt = 1;
2918 /* Handles moves to special registers (aka P-register) for all modes. */
2921 move_to_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2922 inst_env_type *inst_env)
2924 if (inst_env->prefix_found)
2926 /* The instruction has a prefix that means we are only interested if
2927 the instruction is in assign mode. */
2928 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2930 /* The prefix handles the problem if we are in a delay slot. */
2931 if (cris_get_operand1 (inst) == REG_PC)
2933 /* Just take care of the assign. */
2934 check_assign (inst, inst_env);
2938 else if (cris_get_mode (inst) == AUTOINC_MODE)
2940 /* The instruction doesn't have a prefix, the only case left that we
2941 are interested in is the autoincrement mode. */
2942 if (cris_get_operand1 (inst) == REG_PC)
2944 /* If the PC is to be incremented it's invalid to be in a
2946 if (inst_env->slot_needed)
2948 inst_env->invalid = 1;
2952 /* The increment depends on the size of the special register. */
2953 if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
2955 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2957 else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
2959 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2963 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2967 inst_env->slot_needed = 0;
2968 inst_env->prefix_found = 0;
2969 inst_env->xflag_found = 0;
2970 inst_env->disable_interrupt = 1;
2973 /* Handles moves from special registers (aka P-register) for all modes
2977 none_reg_mode_move_from_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2978 inst_env_type *inst_env)
2980 if (inst_env->prefix_found)
2982 /* The instruction has a prefix that means we are only interested if
2983 the instruction is in assign mode. */
2984 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2986 /* The prefix handles the problem if we are in a delay slot. */
2987 if (cris_get_operand1 (inst) == REG_PC)
2989 /* Just take care of the assign. */
2990 check_assign (inst, inst_env);
2994 /* The instruction doesn't have a prefix, the only case left that we
2995 are interested in is the autoincrement mode. */
2996 else if (cris_get_mode (inst) == AUTOINC_MODE)
2998 if (cris_get_operand1 (inst) == REG_PC)
3000 /* If the PC is to be incremented it's invalid to be in a
3002 if (inst_env->slot_needed)
3004 inst_env->invalid = 1;
3008 /* The increment depends on the size of the special register. */
3009 if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
3011 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
3013 else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
3015 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
3019 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
3023 inst_env->slot_needed = 0;
3024 inst_env->prefix_found = 0;
3025 inst_env->xflag_found = 0;
3026 inst_env->disable_interrupt = 1;
3029 /* Handles moves from special registers (aka P-register) when the mode
3033 reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env)
3035 /* Register mode move from special register can't have a prefix. */
3036 if (inst_env->prefix_found)
3038 inst_env->invalid = 1;
3042 if (cris_get_operand1 (inst) == REG_PC)
3044 /* It's invalid to change the PC in a delay slot. */
3045 if (inst_env->slot_needed)
3047 inst_env->invalid = 1;
3050 /* The destination is the PC, the jump will have a delay slot. */
3051 inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)];
3052 inst_env->slot_needed = 1;
3053 inst_env->delay_slot_pc_active = 1;
3057 /* If the destination isn't PC, there will be no jump. */
3058 inst_env->slot_needed = 0;
3060 inst_env->prefix_found = 0;
3061 inst_env->xflag_found = 0;
3062 inst_env->disable_interrupt = 1;
3065 /* Handles the MOVEM from memory to general register instruction. */
3068 move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env)
3070 if (inst_env->prefix_found)
3072 /* The prefix handles the problem if we are in a delay slot. Is the
3073 MOVEM instruction going to change the PC? */
3074 if (cris_get_operand2 (inst) >= REG_PC)
3076 inst_env->reg[REG_PC] =
3077 read_memory_unsigned_integer (inst_env->prefix_value,
3078 4, inst_env->byte_order);
3080 /* The assign value is the value after the increment. Normally, the
3081 assign value is the value before the increment. */
3082 if ((cris_get_operand1 (inst) == REG_PC)
3083 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3085 inst_env->reg[REG_PC] = inst_env->prefix_value;
3086 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3091 /* Is the MOVEM instruction going to change the PC? */
3092 if (cris_get_operand2 (inst) == REG_PC)
3094 /* It's invalid to change the PC in a delay slot. */
3095 if (inst_env->slot_needed)
3097 inst_env->invalid = 1;
3100 inst_env->reg[REG_PC] =
3101 read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)],
3102 4, inst_env->byte_order);
3104 /* The increment is not depending on the size, instead it's depending
3105 on the number of registers loaded from memory. */
3106 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3108 /* It's invalid to change the PC in a delay slot. */
3109 if (inst_env->slot_needed)
3111 inst_env->invalid = 1;
3114 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3117 inst_env->slot_needed = 0;
3118 inst_env->prefix_found = 0;
3119 inst_env->xflag_found = 0;
3120 inst_env->disable_interrupt = 0;
3123 /* Handles the MOVEM to memory from general register instruction. */
3126 move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env)
3128 if (inst_env->prefix_found)
3130 /* The assign value is the value after the increment. Normally, the
3131 assign value is the value before the increment. */
3132 if ((cris_get_operand1 (inst) == REG_PC) &&
3133 (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3135 /* The prefix handles the problem if we are in a delay slot. */
3136 inst_env->reg[REG_PC] = inst_env->prefix_value;
3137 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3142 /* The increment is not depending on the size, instead it's depending
3143 on the number of registers loaded to memory. */
3144 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3146 /* It's invalid to change the PC in a delay slot. */
3147 if (inst_env->slot_needed)
3149 inst_env->invalid = 1;
3152 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3155 inst_env->slot_needed = 0;
3156 inst_env->prefix_found = 0;
3157 inst_env->xflag_found = 0;
3158 inst_env->disable_interrupt = 0;
3161 /* Handles the intructions that's not yet implemented, by setting
3162 inst_env->invalid to true. */
3165 not_implemented_op (unsigned short inst, inst_env_type *inst_env)
3167 inst_env->invalid = 1;
3170 /* Handles the XOR instruction. */
3173 xor_op (unsigned short inst, inst_env_type *inst_env)
3175 /* XOR can't have a prefix. */
3176 if (inst_env->prefix_found)
3178 inst_env->invalid = 1;
3182 /* Check if the PC is the target. */
3183 if (cris_get_operand2 (inst) == REG_PC)
3185 /* It's invalid to change the PC in a delay slot. */
3186 if (inst_env->slot_needed)
3188 inst_env->invalid = 1;
3191 inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)];
3193 inst_env->slot_needed = 0;
3194 inst_env->prefix_found = 0;
3195 inst_env->xflag_found = 0;
3196 inst_env->disable_interrupt = 0;
3199 /* Handles the MULS instruction. */
3202 muls_op (unsigned short inst, inst_env_type *inst_env)
3204 /* MULS/U can't have a prefix. */
3205 if (inst_env->prefix_found)
3207 inst_env->invalid = 1;
3211 /* Consider it invalid if the PC is the target. */
3212 if (cris_get_operand2 (inst) == REG_PC)
3214 inst_env->invalid = 1;
3217 inst_env->slot_needed = 0;
3218 inst_env->prefix_found = 0;
3219 inst_env->xflag_found = 0;
3220 inst_env->disable_interrupt = 0;
3223 /* Handles the MULU instruction. */
3226 mulu_op (unsigned short inst, inst_env_type *inst_env)
3228 /* MULS/U can't have a prefix. */
3229 if (inst_env->prefix_found)
3231 inst_env->invalid = 1;
3235 /* Consider it invalid if the PC is the target. */
3236 if (cris_get_operand2 (inst) == REG_PC)
3238 inst_env->invalid = 1;
3241 inst_env->slot_needed = 0;
3242 inst_env->prefix_found = 0;
3243 inst_env->xflag_found = 0;
3244 inst_env->disable_interrupt = 0;
3247 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
3248 The MOVE instruction is the move from source to register. */
3251 add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env,
3252 unsigned long source1, unsigned long source2)
3254 unsigned long pc_mask;
3255 unsigned long operation_mask;
3257 /* Find out how many bits the operation should apply to. */
3258 if (cris_get_size (inst) == INST_BYTE_SIZE)
3260 pc_mask = 0xFFFFFF00;
3261 operation_mask = 0xFF;
3263 else if (cris_get_size (inst) == INST_WORD_SIZE)
3265 pc_mask = 0xFFFF0000;
3266 operation_mask = 0xFFFF;
3268 else if (cris_get_size (inst) == INST_DWORD_SIZE)
3271 operation_mask = 0xFFFFFFFF;
3275 /* The size is out of range. */
3276 inst_env->invalid = 1;
3280 /* The instruction just works on uw_operation_mask bits. */
3281 source2 &= operation_mask;
3282 source1 &= operation_mask;
3284 /* Now calculate the result. The opcode's 3 first bits separates
3285 the different actions. */
3286 switch (cris_get_opcode (inst) & 7)
3296 case 2: /* subtract */
3300 case 3: /* compare */
3312 inst_env->invalid = 1;
3318 /* Make sure that the result doesn't contain more than the instruction
3320 source2 &= operation_mask;
3322 /* Calculate the new breakpoint address. */
3323 inst_env->reg[REG_PC] &= pc_mask;
3324 inst_env->reg[REG_PC] |= source1;
3328 /* Extends the value from either byte or word size to a dword. If the mode
3329 is zero extend then the value is extended with zero. If instead the mode
3330 is signed extend the sign bit of the value is taken into consideration. */
3332 static unsigned long
3333 do_sign_or_zero_extend (unsigned long value, unsigned short *inst)
3335 /* The size can be either byte or word, check which one it is.
3336 Don't check the highest bit, it's indicating if it's a zero
3338 if (cris_get_size (*inst) & INST_WORD_SIZE)
3343 /* Check if the instruction is signed extend. If so, check if value has
3345 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK))
3347 value |= SIGNED_WORD_EXTEND_MASK;
3355 /* Check if the instruction is signed extend. If so, check if value has
3357 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK))
3359 value |= SIGNED_BYTE_EXTEND_MASK;
3362 /* The size should now be dword. */
3363 cris_set_size_to_dword (inst);
3367 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3368 instruction. The MOVE instruction is the move from source to register. */
3371 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3372 inst_env_type *inst_env)
3374 unsigned long operand1;
3375 unsigned long operand2;
3377 /* It's invalid to have a prefix to the instruction. This is a register
3378 mode instruction and can't have a prefix. */
3379 if (inst_env->prefix_found)
3381 inst_env->invalid = 1;
3384 /* Check if the instruction has PC as its target. */
3385 if (cris_get_operand2 (inst) == REG_PC)
3387 if (inst_env->slot_needed)
3389 inst_env->invalid = 1;
3392 /* The instruction has the PC as its target register. */
3393 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3394 operand2 = inst_env->reg[REG_PC];
3396 /* Check if it's a extend, signed or zero instruction. */
3397 if (cris_get_opcode (inst) < 4)
3399 operand1 = do_sign_or_zero_extend (operand1, &inst);
3401 /* Calculate the PC value after the instruction, i.e. where the
3402 breakpoint should be. The order of the udw_operands is vital. */
3403 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3405 inst_env->slot_needed = 0;
3406 inst_env->prefix_found = 0;
3407 inst_env->xflag_found = 0;
3408 inst_env->disable_interrupt = 0;
3411 /* Returns the data contained at address. The size of the data is derived from
3412 the size of the operation. If the instruction is a zero or signed
3413 extend instruction, the size field is changed in instruction. */
3415 static unsigned long
3416 get_data_from_address (unsigned short *inst, CORE_ADDR address, enum bfd_endian byte_order)
3418 int size = cris_get_size (*inst);
3419 unsigned long value;
3421 /* If it's an extend instruction we don't want the signed extend bit,
3422 because it influences the size. */
3423 if (cris_get_opcode (*inst) < 4)
3425 size &= ~SIGNED_EXTEND_BIT_MASK;
3427 /* Is there a need for checking the size? Size should contain the number of
3430 value = read_memory_unsigned_integer (address, size, byte_order);
3432 /* Check if it's an extend, signed or zero instruction. */
3433 if (cris_get_opcode (*inst) < 4)
3435 value = do_sign_or_zero_extend (value, inst);
3440 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3441 instructions. The MOVE instruction is the move from source to register. */
3444 handle_prefix_assign_mode_for_aritm_op (unsigned short inst,
3445 inst_env_type *inst_env)
3447 unsigned long operand2;
3448 unsigned long operand3;
3450 check_assign (inst, inst_env);
3451 if (cris_get_operand2 (inst) == REG_PC)
3453 operand2 = inst_env->reg[REG_PC];
3455 /* Get the value of the third operand. */
3456 operand3 = get_data_from_address (&inst, inst_env->prefix_value,
3457 inst_env->byte_order);
3459 /* Calculate the PC value after the instruction, i.e. where the
3460 breakpoint should be. The order of the udw_operands is vital. */
3461 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3463 inst_env->slot_needed = 0;
3464 inst_env->prefix_found = 0;
3465 inst_env->xflag_found = 0;
3466 inst_env->disable_interrupt = 0;
3469 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3470 OR instructions. Note that for this to work as expected, the calling
3471 function must have made sure that there is a prefix to this instruction. */
3474 three_operand_add_sub_cmp_and_or_op (unsigned short inst,
3475 inst_env_type *inst_env)
3477 unsigned long operand2;
3478 unsigned long operand3;
3480 if (cris_get_operand1 (inst) == REG_PC)
3482 /* The PC will be changed by the instruction. */
3483 operand2 = inst_env->reg[cris_get_operand2 (inst)];
3485 /* Get the value of the third operand. */
3486 operand3 = get_data_from_address (&inst, inst_env->prefix_value,
3487 inst_env->byte_order);
3489 /* Calculate the PC value after the instruction, i.e. where the
3490 breakpoint should be. */
3491 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3493 inst_env->slot_needed = 0;
3494 inst_env->prefix_found = 0;
3495 inst_env->xflag_found = 0;
3496 inst_env->disable_interrupt = 0;
3499 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3500 instructions. The MOVE instruction is the move from source to register. */
3503 handle_prefix_index_mode_for_aritm_op (unsigned short inst,
3504 inst_env_type *inst_env)
3506 if (cris_get_operand1 (inst) != cris_get_operand2 (inst))
3508 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
3509 SUB, AND or OR something weird is going on (if everything works these
3510 instructions should end up in the three operand version). */
3511 inst_env->invalid = 1;
3516 /* three_operand_add_sub_cmp_and_or does the same as we should do here
3518 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3520 inst_env->slot_needed = 0;
3521 inst_env->prefix_found = 0;
3522 inst_env->xflag_found = 0;
3523 inst_env->disable_interrupt = 0;
3526 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3527 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
3528 source to register. */
3531 handle_inc_and_index_mode_for_aritm_op (unsigned short inst,
3532 inst_env_type *inst_env)
3534 unsigned long operand1;
3535 unsigned long operand2;
3536 unsigned long operand3;
3539 /* The instruction is either an indirect or autoincrement addressing mode.
3540 Check if the destination register is the PC. */
3541 if (cris_get_operand2 (inst) == REG_PC)
3543 /* Must be done here, get_data_from_address may change the size
3545 size = cris_get_size (inst);
3546 operand2 = inst_env->reg[REG_PC];
3548 /* Get the value of the third operand, i.e. the indirect operand. */
3549 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3550 operand3 = get_data_from_address (&inst, operand1, inst_env->byte_order);
3552 /* Calculate the PC value after the instruction, i.e. where the
3553 breakpoint should be. The order of the udw_operands is vital. */
3554 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3556 /* If this is an autoincrement addressing mode, check if the increment
3558 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3560 /* Get the size field. */
3561 size = cris_get_size (inst);
3563 /* If it's an extend instruction we don't want the signed extend bit,
3564 because it influences the size. */
3565 if (cris_get_opcode (inst) < 4)
3567 size &= ~SIGNED_EXTEND_BIT_MASK;
3569 process_autoincrement (size, inst, inst_env);
3571 inst_env->slot_needed = 0;
3572 inst_env->prefix_found = 0;
3573 inst_env->xflag_found = 0;
3574 inst_env->disable_interrupt = 0;
3577 /* Handles the two-operand addressing mode, all modes except register, for
3578 the ADD, SUB CMP, AND and OR instruction. */
3581 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3582 inst_env_type *inst_env)
3584 if (inst_env->prefix_found)
3586 if (cris_get_mode (inst) == PREFIX_INDEX_MODE)
3588 handle_prefix_index_mode_for_aritm_op (inst, inst_env);
3590 else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
3592 handle_prefix_assign_mode_for_aritm_op (inst, inst_env);
3596 /* The mode is invalid for a prefixed base instruction. */
3597 inst_env->invalid = 1;
3603 handle_inc_and_index_mode_for_aritm_op (inst, inst_env);
3607 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3610 quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env)
3612 unsigned long operand1;
3613 unsigned long operand2;
3615 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3616 instruction and can't have a prefix. */
3617 if (inst_env->prefix_found)
3619 inst_env->invalid = 1;
3623 /* Check if the instruction has PC as its target. */
3624 if (cris_get_operand2 (inst) == REG_PC)
3626 if (inst_env->slot_needed)
3628 inst_env->invalid = 1;
3631 operand1 = cris_get_quick_value (inst);
3632 operand2 = inst_env->reg[REG_PC];
3634 /* The size should now be dword. */
3635 cris_set_size_to_dword (&inst);
3637 /* Calculate the PC value after the instruction, i.e. where the
3638 breakpoint should be. */
3639 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3641 inst_env->slot_needed = 0;
3642 inst_env->prefix_found = 0;
3643 inst_env->xflag_found = 0;
3644 inst_env->disable_interrupt = 0;
3647 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3650 quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env)
3652 unsigned long operand1;
3653 unsigned long operand2;
3655 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3656 instruction and can't have a prefix. */
3657 if (inst_env->prefix_found)
3659 inst_env->invalid = 1;
3662 /* Check if the instruction has PC as its target. */
3663 if (cris_get_operand2 (inst) == REG_PC)
3665 if (inst_env->slot_needed)
3667 inst_env->invalid = 1;
3670 /* The instruction has the PC as its target register. */
3671 operand1 = cris_get_quick_value (inst);
3672 operand2 = inst_env->reg[REG_PC];
3674 /* The quick value is signed, so check if we must do a signed extend. */
3675 if (operand1 & SIGNED_QUICK_VALUE_MASK)
3678 operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK;
3680 /* The size should now be dword. */
3681 cris_set_size_to_dword (&inst);
3683 /* Calculate the PC value after the instruction, i.e. where the
3684 breakpoint should be. */
3685 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3687 inst_env->slot_needed = 0;
3688 inst_env->prefix_found = 0;
3689 inst_env->xflag_found = 0;
3690 inst_env->disable_interrupt = 0;
3693 /* Translate op_type to a function and call it. */
3696 cris_gdb_func (struct gdbarch *gdbarch, enum cris_op_type op_type,
3697 unsigned short inst, inst_env_type *inst_env)
3701 case cris_not_implemented_op:
3702 not_implemented_op (inst, inst_env);
3706 abs_op (inst, inst_env);
3710 addi_op (inst, inst_env);
3714 asr_op (inst, inst_env);
3718 asrq_op (inst, inst_env);
3721 case cris_ax_ei_setf_op:
3722 ax_ei_setf_op (inst, inst_env);
3725 case cris_bdap_prefix:
3726 bdap_prefix (inst, inst_env);
3729 case cris_biap_prefix:
3730 biap_prefix (inst, inst_env);
3734 break_op (inst, inst_env);
3737 case cris_btst_nop_op:
3738 btst_nop_op (inst, inst_env);
3741 case cris_clearf_di_op:
3742 clearf_di_op (inst, inst_env);
3745 case cris_dip_prefix:
3746 dip_prefix (inst, inst_env);
3749 case cris_dstep_logshift_mstep_neg_not_op:
3750 dstep_logshift_mstep_neg_not_op (inst, inst_env);
3753 case cris_eight_bit_offset_branch_op:
3754 eight_bit_offset_branch_op (inst, inst_env);
3757 case cris_move_mem_to_reg_movem_op:
3758 move_mem_to_reg_movem_op (inst, inst_env);
3761 case cris_move_reg_to_mem_movem_op:
3762 move_reg_to_mem_movem_op (inst, inst_env);
3765 case cris_move_to_preg_op:
3766 move_to_preg_op (gdbarch, inst, inst_env);
3770 muls_op (inst, inst_env);
3774 mulu_op (inst, inst_env);
3777 case cris_none_reg_mode_add_sub_cmp_and_or_move_op:
3778 none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3781 case cris_none_reg_mode_clear_test_op:
3782 none_reg_mode_clear_test_op (inst, inst_env);
3785 case cris_none_reg_mode_jump_op:
3786 none_reg_mode_jump_op (inst, inst_env);
3789 case cris_none_reg_mode_move_from_preg_op:
3790 none_reg_mode_move_from_preg_op (gdbarch, inst, inst_env);
3793 case cris_quick_mode_add_sub_op:
3794 quick_mode_add_sub_op (inst, inst_env);
3797 case cris_quick_mode_and_cmp_move_or_op:
3798 quick_mode_and_cmp_move_or_op (inst, inst_env);
3801 case cris_quick_mode_bdap_prefix:
3802 quick_mode_bdap_prefix (inst, inst_env);
3805 case cris_reg_mode_add_sub_cmp_and_or_move_op:
3806 reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3809 case cris_reg_mode_clear_op:
3810 reg_mode_clear_op (inst, inst_env);
3813 case cris_reg_mode_jump_op:
3814 reg_mode_jump_op (inst, inst_env);
3817 case cris_reg_mode_move_from_preg_op:
3818 reg_mode_move_from_preg_op (inst, inst_env);
3821 case cris_reg_mode_test_op:
3822 reg_mode_test_op (inst, inst_env);
3826 scc_op (inst, inst_env);
3829 case cris_sixteen_bit_offset_branch_op:
3830 sixteen_bit_offset_branch_op (inst, inst_env);
3833 case cris_three_operand_add_sub_cmp_and_or_op:
3834 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3837 case cris_three_operand_bound_op:
3838 three_operand_bound_op (inst, inst_env);
3841 case cris_two_operand_bound_op:
3842 two_operand_bound_op (inst, inst_env);
3846 xor_op (inst, inst_env);
3851 /* This wrapper is to avoid cris_get_assembler being called before
3852 exec_bfd has been set. */
3855 cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info)
3857 int (*print_insn) (bfd_vma addr, struct disassemble_info *info);
3858 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3859 disassembler, even when there is no BFD. Does something like
3860 "gdb; target remote; disassmeble *0x123" work? */
3861 gdb_assert (exec_bfd != NULL);
3862 print_insn = cris_get_disassembler (exec_bfd);
3863 gdb_assert (print_insn != NULL);
3864 return print_insn (addr, info);
3867 /* Copied from <asm/elf.h>. */
3868 typedef unsigned long elf_greg_t;
3870 /* Same as user_regs_struct struct in <asm/user.h>. */
3871 #define CRISV10_ELF_NGREG 35
3872 typedef elf_greg_t elf_gregset_t[CRISV10_ELF_NGREG];
3874 #define CRISV32_ELF_NGREG 32
3875 typedef elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG];
3877 /* Unpack an elf_gregset_t into GDB's register cache. */
3880 cris_supply_gregset (struct regcache *regcache, elf_gregset_t *gregsetp)
3882 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3883 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3885 elf_greg_t *regp = *gregsetp;
3886 static char zerobuf[4] = {0};
3888 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3889 knows about the actual size of each register so that's no problem. */
3890 for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++)
3892 regcache_raw_supply (regcache, i, (char *)®p[i]);
3895 if (tdep->cris_version == 32)
3897 /* Needed to set pseudo-register PC for CRISv32. */
3898 /* FIXME: If ERP is in a delay slot at this point then the PC will
3899 be wrong. Issue a warning to alert the user. */
3900 regcache_raw_supply (regcache, gdbarch_pc_regnum (gdbarch),
3901 (char *)®p[ERP_REGNUM]);
3903 if (*(char *)®p[ERP_REGNUM] & 0x1)
3904 fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n");
3908 /* Use a local version of this function to get the correct types for
3909 regsets, until multi-arch core support is ready. */
3912 fetch_core_registers (struct regcache *regcache,
3913 char *core_reg_sect, unsigned core_reg_size,
3914 int which, CORE_ADDR reg_addr)
3916 elf_gregset_t gregset;
3921 if (core_reg_size != sizeof (elf_gregset_t)
3922 && core_reg_size != sizeof (crisv32_elf_gregset_t))
3924 warning (_("wrong size gregset struct in core file"));
3928 memcpy (&gregset, core_reg_sect, sizeof (gregset));
3929 cris_supply_gregset (regcache, &gregset);
3933 /* We've covered all the kinds of registers we know about here,
3934 so this must be something we wouldn't know what to do with
3935 anyway. Just ignore it. */
3940 static struct core_fns cris_elf_core_fns =
3942 bfd_target_elf_flavour, /* core_flavour */
3943 default_check_format, /* check_format */
3944 default_core_sniffer, /* core_sniffer */
3945 fetch_core_registers, /* core_read_registers */
3949 extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */
3952 _initialize_cris_tdep (void)
3954 static struct cmd_list_element *cris_set_cmdlist;
3955 static struct cmd_list_element *cris_show_cmdlist;
3957 struct cmd_list_element *c;
3959 gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep);
3961 /* CRIS-specific user-commands. */
3962 add_setshow_uinteger_cmd ("cris-version", class_support,
3963 &usr_cmd_cris_version,
3964 _("Set the current CRIS version."),
3965 _("Show the current CRIS version."),
3967 Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\
3970 NULL, /* FIXME: i18n: Current CRIS version is %s. */
3971 &setlist, &showlist);
3973 add_setshow_enum_cmd ("cris-mode", class_support,
3974 cris_modes, &usr_cmd_cris_mode,
3975 _("Set the current CRIS mode."),
3976 _("Show the current CRIS mode."),
3978 Set to CRIS_MODE_GURU when debugging in guru mode.\n\
3979 Makes GDB use the NRP register instead of the ERP register in certain cases."),
3981 NULL, /* FIXME: i18n: Current CRIS version is %s. */
3982 &setlist, &showlist);
3984 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support,
3985 &usr_cmd_cris_dwarf2_cfi,
3986 _("Set the usage of Dwarf-2 CFI for CRIS."),
3987 _("Show the usage of Dwarf-2 CFI for CRIS."),
3988 _("Set this to \"off\" if using gcc-cris < R59."),
3989 set_cris_dwarf2_cfi,
3990 NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI for CRIS is %d. */
3991 &setlist, &showlist);
3993 deprecated_add_core_fns (&cris_elf_core_fns);
3996 /* Prints out all target specific values. */
3999 cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
4001 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4004 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n",
4005 tdep->cris_version);
4006 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n",
4008 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
4009 tdep->cris_dwarf2_cfi);
4014 set_cris_version (char *ignore_args, int from_tty,
4015 struct cmd_list_element *c)
4017 struct gdbarch_info info;
4019 usr_cmd_cris_version_valid = 1;
4021 /* Update the current architecture, if needed. */
4022 gdbarch_info_init (&info);
4023 if (!gdbarch_update_p (info))
4024 internal_error (__FILE__, __LINE__,
4025 _("cris_gdbarch_update: failed to update architecture."));
4029 set_cris_mode (char *ignore_args, int from_tty,
4030 struct cmd_list_element *c)
4032 struct gdbarch_info info;
4034 /* Update the current architecture, if needed. */
4035 gdbarch_info_init (&info);
4036 if (!gdbarch_update_p (info))
4037 internal_error (__FILE__, __LINE__,
4038 "cris_gdbarch_update: failed to update architecture.");
4042 set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
4043 struct cmd_list_element *c)
4045 struct gdbarch_info info;
4047 /* Update the current architecture, if needed. */
4048 gdbarch_info_init (&info);
4049 if (!gdbarch_update_p (info))
4050 internal_error (__FILE__, __LINE__,
4051 _("cris_gdbarch_update: failed to update architecture."));
4054 static struct gdbarch *
4055 cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
4057 struct gdbarch *gdbarch;
4058 struct gdbarch_tdep *tdep;
4061 if (usr_cmd_cris_version_valid)
4063 /* Trust the user's CRIS version setting. */
4064 cris_version = usr_cmd_cris_version;
4066 else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32)
4072 /* Assume it's CRIS version 10. */
4076 /* Make the current settings visible to the user. */
4077 usr_cmd_cris_version = cris_version;
4079 /* Find a candidate among the list of pre-declared architectures. */
4080 for (arches = gdbarch_list_lookup_by_info (arches, &info);
4082 arches = gdbarch_list_lookup_by_info (arches->next, &info))
4084 if ((gdbarch_tdep (arches->gdbarch)->cris_version
4085 == usr_cmd_cris_version)
4086 && (gdbarch_tdep (arches->gdbarch)->cris_mode
4087 == usr_cmd_cris_mode)
4088 && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi
4089 == usr_cmd_cris_dwarf2_cfi))
4090 return arches->gdbarch;
4093 /* No matching architecture was found. Create a new one. */
4094 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
4095 gdbarch = gdbarch_alloc (&info, tdep);
4097 tdep->cris_version = usr_cmd_cris_version;
4098 tdep->cris_mode = usr_cmd_cris_mode;
4099 tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi;
4101 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
4102 switch (info.byte_order)
4104 case BFD_ENDIAN_LITTLE:
4108 case BFD_ENDIAN_BIG:
4109 internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: big endian byte order in info"));
4113 internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: unknown byte order in info"));
4116 set_gdbarch_return_value (gdbarch, cris_return_value);
4118 set_gdbarch_sp_regnum (gdbarch, 14);
4120 /* Length of ordinary registers used in push_word and a few other
4121 places. register_size() is the real way to know how big a
4124 set_gdbarch_double_bit (gdbarch, 64);
4125 /* The default definition of a long double is 2 * gdbarch_double_bit,
4126 which means we have to set this explicitly. */
4127 set_gdbarch_long_double_bit (gdbarch, 64);
4129 /* The total amount of space needed to store (in an array called registers)
4130 GDB's copy of the machine's register state. Note: We can not use
4131 cris_register_size at this point, since it relies on gdbarch
4133 switch (tdep->cris_version)
4141 /* Old versions; not supported. */
4142 internal_error (__FILE__, __LINE__,
4143 _("cris_gdbarch_init: unsupported CRIS version"));
4148 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
4149 P7 (32 bits), and P15 (32 bits) have been implemented. */
4150 set_gdbarch_pc_regnum (gdbarch, 15);
4151 set_gdbarch_register_type (gdbarch, cris_register_type);
4152 /* There are 32 registers (some of which may not be implemented). */
4153 set_gdbarch_num_regs (gdbarch, 32);
4154 set_gdbarch_register_name (gdbarch, cris_register_name);
4155 set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register);
4156 set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register);
4158 set_gdbarch_software_single_step (gdbarch, cris_software_single_step);
4162 /* CRIS v32. General registers R0 - R15 (32 bits), special registers
4163 P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
4164 and pseudo-register PC (32 bits). */
4165 set_gdbarch_pc_regnum (gdbarch, 32);
4166 set_gdbarch_register_type (gdbarch, crisv32_register_type);
4167 /* 32 registers + pseudo-register PC + 16 support registers. */
4168 set_gdbarch_num_regs (gdbarch, 32 + 1 + 16);
4169 set_gdbarch_register_name (gdbarch, crisv32_register_name);
4171 set_gdbarch_cannot_store_register
4172 (gdbarch, crisv32_cannot_store_register);
4173 set_gdbarch_cannot_fetch_register
4174 (gdbarch, crisv32_cannot_fetch_register);
4176 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
4178 set_gdbarch_single_step_through_delay
4179 (gdbarch, crisv32_single_step_through_delay);
4184 internal_error (__FILE__, __LINE__,
4185 _("cris_gdbarch_init: unknown CRIS version"));
4188 /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
4189 have the same ABI). */
4190 set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code);
4191 set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call);
4192 set_gdbarch_frame_align (gdbarch, cris_frame_align);
4193 set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue);
4195 /* The stack grows downward. */
4196 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4198 set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc);
4200 set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc);
4201 set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp);
4202 set_gdbarch_dummy_id (gdbarch, cris_dummy_id);
4204 if (tdep->cris_dwarf2_cfi == 1)
4206 /* Hook in the Dwarf-2 frame sniffer. */
4207 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum);
4208 dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg);
4209 dwarf2_append_unwinders (gdbarch);
4212 if (tdep->cris_mode != cris_mode_guru)
4214 frame_unwind_append_unwinder (gdbarch, &cris_sigtramp_frame_unwind);
4217 frame_unwind_append_unwinder (gdbarch, &cris_frame_unwind);
4218 frame_base_set_default (gdbarch, &cris_frame_base);
4220 set_solib_svr4_fetch_link_map_offsets
4221 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
4223 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
4224 disassembler, even when there is no BFD. Does something like
4225 "gdb; target remote; disassmeble *0x123" work? */
4226 set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler);