1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
3 Copyright (C) 2001-2014 Free Software Foundation, Inc.
5 Contributed by Axis Communications AB.
6 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include "frame-unwind.h"
26 #include "frame-base.h"
27 #include "trad-frame.h"
28 #include "dwarf2-frame.h"
36 #include "opcode/cris.h"
38 #include "arch-utils.h"
43 #include "solib.h" /* Support for shared libraries. */
44 #include "solib-svr4.h"
48 #include "cris-tdep.h"
52 /* There are no floating point registers. Used in gdbserver low-linux.c. */
55 /* There are 16 general registers. */
58 /* There are 16 special registers. */
61 /* CRISv32 has a pseudo PC register, not noted here. */
63 /* CRISv32 has 16 support registers. */
67 /* Register numbers of various important registers.
68 CRIS_FP_REGNUM Contains address of executing stack frame.
69 STR_REGNUM Contains the address of structure return values.
70 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
71 ARG1_REGNUM Contains the first parameter to a function.
72 ARG2_REGNUM Contains the second parameter to a function.
73 ARG3_REGNUM Contains the third parameter to a function.
74 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
75 gdbarch_sp_regnum Contains address of top of stack.
76 gdbarch_pc_regnum Contains address of next instruction.
77 SRP_REGNUM Subroutine return pointer register.
78 BRP_REGNUM Breakpoint return pointer register. */
82 /* Enums with respect to the general registers, valid for all
83 CRIS versions. The frame pointer is always in R8. */
85 /* ABI related registers. */
93 /* Registers which happen to be common. */
98 /* CRISv10 et al. specific registers. */
110 /* CRISv32 specific registers. */
123 CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */
125 CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */
145 extern const struct cris_spec_reg cris_spec_regs[];
147 /* CRIS version, set via the user command 'set cris-version'. Affects
148 register names and sizes. */
149 static unsigned int usr_cmd_cris_version;
151 /* Indicates whether to trust the above variable. */
152 static int usr_cmd_cris_version_valid = 0;
154 static const char cris_mode_normal[] = "normal";
155 static const char cris_mode_guru[] = "guru";
156 static const char *const cris_modes[] = {
162 /* CRIS mode, set via the user command 'set cris-mode'. Affects
163 type of break instruction among other things. */
164 static const char *usr_cmd_cris_mode = cris_mode_normal;
166 /* Whether to make use of Dwarf-2 CFI (default on). */
167 static int usr_cmd_cris_dwarf2_cfi = 1;
169 /* Sigtramp identification code copied from i386-linux-tdep.c. */
171 #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
172 #define SIGTRAMP_OFFSET0 0
173 #define SIGTRAMP_INSN1 0xe93d /* break 13 */
174 #define SIGTRAMP_OFFSET1 4
176 static const unsigned short sigtramp_code[] =
178 SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */
179 SIGTRAMP_INSN1 /* break 13 */
182 #define SIGTRAMP_LEN (sizeof sigtramp_code)
184 /* Note: same length as normal sigtramp code. */
186 static const unsigned short rt_sigtramp_code[] =
188 SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */
189 SIGTRAMP_INSN1 /* break 13 */
192 /* If PC is in a sigtramp routine, return the address of the start of
193 the routine. Otherwise, return 0. */
196 cris_sigtramp_start (struct frame_info *this_frame)
198 CORE_ADDR pc = get_frame_pc (this_frame);
199 gdb_byte buf[SIGTRAMP_LEN];
201 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
204 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
206 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
209 pc -= SIGTRAMP_OFFSET1;
210 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
214 if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0)
220 /* If PC is in a RT sigtramp routine, return the address of the start of
221 the routine. Otherwise, return 0. */
224 cris_rt_sigtramp_start (struct frame_info *this_frame)
226 CORE_ADDR pc = get_frame_pc (this_frame);
227 gdb_byte buf[SIGTRAMP_LEN];
229 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
232 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
234 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
237 pc -= SIGTRAMP_OFFSET1;
238 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
242 if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0)
248 /* Assuming THIS_FRAME is a frame for a GNU/Linux sigtramp routine,
249 return the address of the associated sigcontext structure. */
252 cris_sigcontext_addr (struct frame_info *this_frame)
254 struct gdbarch *gdbarch = get_frame_arch (this_frame);
255 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
260 get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
261 sp = extract_unsigned_integer (buf, 4, byte_order);
263 /* Look for normal sigtramp frame first. */
264 pc = cris_sigtramp_start (this_frame);
267 /* struct signal_frame (arch/cris/kernel/signal.c) contains
268 struct sigcontext as its first member, meaning the SP points to
273 pc = cris_rt_sigtramp_start (this_frame);
276 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
277 a struct ucontext, which in turn contains a struct sigcontext.
279 4 + 4 + 128 to struct ucontext, then
280 4 + 4 + 12 to struct sigcontext. */
284 error (_("Couldn't recognize signal trampoline."));
288 struct cris_unwind_cache
290 /* The previous frame's inner most stack address. Used as this
291 frame ID's stack_addr. */
293 /* The frame's base, optionally used by the high-level debug info. */
296 /* How far the SP and r8 (FP) have been offset from the start of
297 the stack frame (as defined by the previous frame's stack
303 /* From old frame_extra_info struct. */
307 /* Table indicating the location of each and every register. */
308 struct trad_frame_saved_reg *saved_regs;
311 static struct cris_unwind_cache *
312 cris_sigtramp_frame_unwind_cache (struct frame_info *this_frame,
315 struct gdbarch *gdbarch = get_frame_arch (this_frame);
316 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
317 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
318 struct cris_unwind_cache *info;
324 return (*this_cache);
326 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
327 (*this_cache) = info;
328 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
330 /* Zero all fields. */
336 info->uses_frame = 0;
338 info->leaf_function = 0;
340 get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
341 info->base = extract_unsigned_integer (buf, 4, byte_order);
343 addr = cris_sigcontext_addr (this_frame);
345 /* Layout of the sigcontext struct:
348 unsigned long oldmask;
352 if (tdep->cris_version == 10)
354 /* R0 to R13 are stored in reverse order at offset (2 * 4) in
356 for (i = 0; i <= 13; i++)
357 info->saved_regs[i].addr = addr + ((15 - i) * 4);
359 info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4);
360 info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4);
361 info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4);
362 /* Note: IRP is off by 2 at this point. There's no point in correcting
363 it though since that will mean that the backtrace will show a PC
364 different from what is shown when stopped. */
365 info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4);
366 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
367 = info->saved_regs[IRP_REGNUM];
368 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr = addr + (24 * 4);
373 /* R0 to R13 are stored in order at offset (1 * 4) in
375 for (i = 0; i <= 13; i++)
376 info->saved_regs[i].addr = addr + ((i + 1) * 4);
378 info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4);
379 info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4);
380 info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4);
381 info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4);
382 info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4);
383 info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4);
384 info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4);
385 info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4);
386 info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4);
388 /* FIXME: If ERP is in a delay slot at this point then the PC will
389 be wrong at this point. This problem manifests itself in the
390 sigaltstack.exp test case, which occasionally generates FAILs when
391 the signal is received while in a delay slot.
393 This could be solved by a couple of read_memory_unsigned_integer and a
394 trad_frame_set_value. */
395 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
396 = info->saved_regs[ERP_REGNUM];
398 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr
406 cris_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
407 struct frame_id *this_id)
409 struct cris_unwind_cache *cache =
410 cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
411 (*this_id) = frame_id_build (cache->base, get_frame_pc (this_frame));
414 /* Forward declaration. */
416 static struct value *cris_frame_prev_register (struct frame_info *this_frame,
417 void **this_cache, int regnum);
418 static struct value *
419 cris_sigtramp_frame_prev_register (struct frame_info *this_frame,
420 void **this_cache, int regnum)
422 /* Make sure we've initialized the cache. */
423 cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
424 return cris_frame_prev_register (this_frame, this_cache, regnum);
428 cris_sigtramp_frame_sniffer (const struct frame_unwind *self,
429 struct frame_info *this_frame,
432 if (cris_sigtramp_start (this_frame)
433 || cris_rt_sigtramp_start (this_frame))
439 static const struct frame_unwind cris_sigtramp_frame_unwind =
442 default_frame_unwind_stop_reason,
443 cris_sigtramp_frame_this_id,
444 cris_sigtramp_frame_prev_register,
446 cris_sigtramp_frame_sniffer
450 crisv32_single_step_through_delay (struct gdbarch *gdbarch,
451 struct frame_info *this_frame)
453 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
457 if (tdep->cris_mode == cris_mode_guru)
458 erp = get_frame_register_unsigned (this_frame, NRP_REGNUM);
460 erp = get_frame_register_unsigned (this_frame, ERP_REGNUM);
464 /* In delay slot - check if there's a breakpoint at the preceding
466 if (breakpoint_here_p (get_frame_address_space (this_frame), erp & ~0x1))
472 /* The instruction environment needed to find single-step breakpoints. */
475 struct instruction_environment
477 unsigned long reg[NUM_GENREGS];
478 unsigned long preg[NUM_SPECREGS];
479 unsigned long branch_break_address;
480 unsigned long delay_slot_pc;
481 unsigned long prefix_value;
486 int delay_slot_pc_active;
488 int disable_interrupt;
492 /* Machine-dependencies in CRIS for opcodes. */
494 /* Instruction sizes. */
495 enum cris_instruction_sizes
502 /* Addressing modes. */
503 enum cris_addressing_modes
510 /* Prefix addressing modes. */
511 enum cris_prefix_addressing_modes
513 PREFIX_INDEX_MODE = 2,
514 PREFIX_ASSIGN_MODE = 3,
516 /* Handle immediate byte offset addressing mode prefix format. */
517 PREFIX_OFFSET_MODE = 2
520 /* Masks for opcodes. */
521 enum cris_opcode_masks
523 BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1,
524 SIGNED_EXTEND_BIT_MASK = 0x2,
525 SIGNED_BYTE_MASK = 0x80,
526 SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00,
527 SIGNED_WORD_MASK = 0x8000,
528 SIGNED_WORD_EXTEND_MASK = 0xFFFF0000,
529 SIGNED_DWORD_MASK = 0x80000000,
530 SIGNED_QUICK_VALUE_MASK = 0x20,
531 SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0
534 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
542 cris_get_operand2 (unsigned short insn)
544 return ((insn & 0xF000) >> 12);
548 cris_get_mode (unsigned short insn)
550 return ((insn & 0x0C00) >> 10);
554 cris_get_opcode (unsigned short insn)
556 return ((insn & 0x03C0) >> 6);
560 cris_get_size (unsigned short insn)
562 return ((insn & 0x0030) >> 4);
566 cris_get_operand1 (unsigned short insn)
568 return (insn & 0x000F);
571 /* Additional functions in order to handle opcodes. */
574 cris_get_quick_value (unsigned short insn)
576 return (insn & 0x003F);
580 cris_get_bdap_quick_offset (unsigned short insn)
582 return (insn & 0x00FF);
586 cris_get_branch_short_offset (unsigned short insn)
588 return (insn & 0x00FF);
592 cris_get_asr_shift_steps (unsigned long value)
594 return (value & 0x3F);
598 cris_get_clear_size (unsigned short insn)
600 return ((insn) & 0xC000);
604 cris_is_signed_extend_bit_on (unsigned short insn)
606 return (((insn) & 0x20) == 0x20);
610 cris_is_xflag_bit_on (unsigned short insn)
612 return (((insn) & 0x1000) == 0x1000);
616 cris_set_size_to_dword (unsigned short *insn)
623 cris_get_signed_offset (unsigned short insn)
625 return ((signed char) (insn & 0x00FF));
628 /* Calls an op function given the op-type, working on the insn and the
630 static void cris_gdb_func (struct gdbarch *, enum cris_op_type, unsigned short,
633 static struct gdbarch *cris_gdbarch_init (struct gdbarch_info,
634 struct gdbarch_list *);
636 static void cris_dump_tdep (struct gdbarch *, struct ui_file *);
638 static void set_cris_version (char *ignore_args, int from_tty,
639 struct cmd_list_element *c);
641 static void set_cris_mode (char *ignore_args, int from_tty,
642 struct cmd_list_element *c);
644 static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
645 struct cmd_list_element *c);
647 static CORE_ADDR cris_scan_prologue (CORE_ADDR pc,
648 struct frame_info *this_frame,
649 struct cris_unwind_cache *info);
651 static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc,
652 struct frame_info *this_frame,
653 struct cris_unwind_cache *info);
655 static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch,
656 struct frame_info *next_frame);
658 static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch,
659 struct frame_info *next_frame);
661 /* When arguments must be pushed onto the stack, they go on in reverse
662 order. The below implements a FILO (stack) to do this.
663 Copied from d10v-tdep.c. */
668 struct stack_item *prev;
672 static struct stack_item *
673 push_stack_item (struct stack_item *prev, const gdb_byte *contents, int len)
675 struct stack_item *si;
676 si = xmalloc (sizeof (struct stack_item));
677 si->data = xmalloc (len);
680 memcpy (si->data, contents, len);
684 static struct stack_item *
685 pop_stack_item (struct stack_item *si)
687 struct stack_item *dead = si;
694 /* Put here the code to store, into fi->saved_regs, the addresses of
695 the saved registers of frame described by FRAME_INFO. This
696 includes special registers such as pc and fp saved in special ways
697 in the stack frame. sp is even more special: the address we return
698 for it IS the sp for the next frame. */
700 static struct cris_unwind_cache *
701 cris_frame_unwind_cache (struct frame_info *this_frame,
702 void **this_prologue_cache)
704 struct gdbarch *gdbarch = get_frame_arch (this_frame);
705 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
706 struct cris_unwind_cache *info;
708 if ((*this_prologue_cache))
709 return (*this_prologue_cache);
711 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
712 (*this_prologue_cache) = info;
713 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
715 /* Zero all fields. */
721 info->uses_frame = 0;
723 info->leaf_function = 0;
725 /* Prologue analysis does the rest... */
726 if (tdep->cris_version == 32)
727 crisv32_scan_prologue (get_frame_func (this_frame), this_frame, info);
729 cris_scan_prologue (get_frame_func (this_frame), this_frame, info);
734 /* Given a GDB frame, determine the address of the calling function's
735 frame. This will be used to create a new GDB frame struct. */
738 cris_frame_this_id (struct frame_info *this_frame,
739 void **this_prologue_cache,
740 struct frame_id *this_id)
742 struct cris_unwind_cache *info
743 = cris_frame_unwind_cache (this_frame, this_prologue_cache);
748 /* The FUNC is easy. */
749 func = get_frame_func (this_frame);
751 /* Hopefully the prologue analysis either correctly determined the
752 frame's base (which is the SP from the previous frame), or set
753 that base to "NULL". */
754 base = info->prev_sp;
758 id = frame_id_build (base, func);
763 static struct value *
764 cris_frame_prev_register (struct frame_info *this_frame,
765 void **this_prologue_cache, int regnum)
767 struct cris_unwind_cache *info
768 = cris_frame_unwind_cache (this_frame, this_prologue_cache);
769 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
772 /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
773 frame. The frame ID's base needs to match the TOS value saved by
774 save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */
776 static struct frame_id
777 cris_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
780 sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
781 return frame_id_build (sp, get_frame_pc (this_frame));
785 cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
787 /* Align to the size of an instruction (so that they can safely be
788 pushed onto the stack). */
793 cris_push_dummy_code (struct gdbarch *gdbarch,
794 CORE_ADDR sp, CORE_ADDR funaddr,
795 struct value **args, int nargs,
796 struct type *value_type,
797 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
798 struct regcache *regcache)
800 /* Allocate space sufficient for a breakpoint. */
802 /* Store the address of that breakpoint */
804 /* CRIS always starts the call at the callee's entry point. */
810 cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
811 struct regcache *regcache, CORE_ADDR bp_addr,
812 int nargs, struct value **args, CORE_ADDR sp,
813 int struct_return, CORE_ADDR struct_addr)
815 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
820 /* The function's arguments and memory allocated by gdb for the arguments to
821 point at reside in separate areas on the stack.
822 Both frame pointers grow toward higher addresses. */
826 struct stack_item *si = NULL;
828 /* Push the return address. */
829 regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr);
831 /* Are we returning a value using a structure return or a normal value
832 return? struct_addr is the address of the reserved space for the return
833 structure to be written on the stack. */
836 regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr);
839 /* Now load as many as possible of the first arguments into registers,
840 and push the rest onto the stack. */
841 argreg = ARG1_REGNUM;
844 for (argnum = 0; argnum < nargs; argnum++)
851 len = TYPE_LENGTH (value_type (args[argnum]));
852 val = value_contents (args[argnum]);
854 /* How may registers worth of storage do we need for this argument? */
855 reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0);
857 if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM))
859 /* Data passed by value. Fits in available register(s). */
860 for (i = 0; i < reg_demand; i++)
862 regcache_cooked_write (regcache, argreg, val);
867 else if (len <= (2 * 4) && argreg <= ARG4_REGNUM)
869 /* Data passed by value. Does not fit in available register(s).
870 Use the register(s) first, then the stack. */
871 for (i = 0; i < reg_demand; i++)
873 if (argreg <= ARG4_REGNUM)
875 regcache_cooked_write (regcache, argreg, val);
881 /* Push item for later so that pushed arguments
882 come in the right order. */
883 si = push_stack_item (si, val, 4);
888 else if (len > (2 * 4))
890 /* Data passed by reference. Push copy of data onto stack
891 and pass pointer to this copy as argument. */
892 sp = (sp - len) & ~3;
893 write_memory (sp, val, len);
895 if (argreg <= ARG4_REGNUM)
897 regcache_cooked_write_unsigned (regcache, argreg, sp);
903 store_unsigned_integer (buf, 4, byte_order, sp);
904 si = push_stack_item (si, buf, 4);
909 /* Data passed by value. No available registers. Put it on
911 si = push_stack_item (si, val, len);
917 /* fp_arg must be word-aligned (i.e., don't += len) to match
918 the function prologue. */
919 sp = (sp - si->len) & ~3;
920 write_memory (sp, si->data, si->len);
921 si = pop_stack_item (si);
924 /* Finally, update the SP register. */
925 regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp);
930 static const struct frame_unwind cris_frame_unwind =
933 default_frame_unwind_stop_reason,
935 cris_frame_prev_register,
937 default_frame_sniffer
941 cris_frame_base_address (struct frame_info *this_frame, void **this_cache)
943 struct cris_unwind_cache *info
944 = cris_frame_unwind_cache (this_frame, this_cache);
948 static const struct frame_base cris_frame_base =
951 cris_frame_base_address,
952 cris_frame_base_address,
953 cris_frame_base_address
956 /* Frames information. The definition of the struct frame_info is
960 enum frame_type type;
964 If the compilation option -fno-omit-frame-pointer is present the
965 variable frame will be set to the content of R8 which is the frame
968 The variable pc contains the address where execution is performed
969 in the present frame. The innermost frame contains the current content
970 of the register PC. All other frames contain the content of the
971 register PC in the next frame.
973 The variable `type' indicates the frame's type: normal, SIGTRAMP
974 (associated with a signal handler), dummy (associated with a dummy
977 The variable return_pc contains the address where execution should be
978 resumed when the present frame has finished, the return address.
980 The variable leaf_function is 1 if the return address is in the register
981 SRP, and 0 if it is on the stack.
983 Prologue instructions C-code.
984 The prologue may consist of (-fno-omit-frame-pointer)
988 move.d sp,r8 move.d sp,r8
990 movem rY,[sp] movem rY,[sp]
991 move.S rZ,[r8-U] move.S rZ,[r8-U]
993 where 1 is a non-terminal function, and 2 is a leaf-function.
995 Note that this assumption is extremely brittle, and will break at the
996 slightest change in GCC's prologue.
998 If local variables are declared or register contents are saved on stack
999 the subq-instruction will be present with X as the number of bytes
1000 needed for storage. The reshuffle with respect to r8 may be performed
1001 with any size S (b, w, d) and any of the general registers Z={0..13}.
1002 The offset U should be representable by a signed 8-bit value in all cases.
1003 Thus, the prefix word is assumed to be immediate byte offset mode followed
1004 by another word containing the instruction.
1013 Prologue instructions C++-code.
1014 Case 1) and 2) in the C-code may be followed by
1016 move.d r10,rS ; this
1020 move.S [r8+U],rZ ; P4
1022 if any of the call parameters are stored. The host expects these
1023 instructions to be executed in order to get the call parameters right. */
1025 /* Examine the prologue of a function. The variable ip is the address of
1026 the first instruction of the prologue. The variable limit is the address
1027 of the first instruction after the prologue. The variable fi contains the
1028 information in struct frame_info. The variable frameless_p controls whether
1029 the entire prologue is examined (0) or just enough instructions to
1030 determine that it is a prologue (1). */
1033 cris_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
1034 struct cris_unwind_cache *info)
1036 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1037 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1039 /* Present instruction. */
1040 unsigned short insn;
1042 /* Next instruction, lookahead. */
1043 unsigned short insn_next;
1046 /* Is there a push fp? */
1049 /* Number of byte on stack used for local variables and movem. */
1052 /* Highest register number in a movem. */
1055 /* move.d r<source_register>,rS */
1056 short source_register;
1061 /* This frame is with respect to a leaf until a push srp is found. */
1064 info->leaf_function = 1;
1067 /* Assume nothing on stack. */
1071 /* If we were called without a this_frame, that means we were called
1072 from cris_skip_prologue which already tried to find the end of the
1073 prologue through the symbol information. 64 instructions past current
1074 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
1075 limit = this_frame ? get_frame_pc (this_frame) : pc + 64;
1077 /* Find the prologue instructions. */
1078 while (pc > 0 && pc < limit)
1080 insn = read_memory_unsigned_integer (pc, 2, byte_order);
1084 /* push <reg> 32 bit instruction. */
1085 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1087 regno = cris_get_operand2 (insn_next);
1090 info->sp_offset += 4;
1092 /* This check, meant to recognize srp, used to be regno ==
1093 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
1094 if (insn_next == 0xBE7E)
1098 info->leaf_function = 0;
1101 else if (insn_next == 0x8FEE)
1106 info->r8_offset = info->sp_offset;
1110 else if (insn == 0x866E)
1115 info->uses_frame = 1;
1119 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1120 && cris_get_mode (insn) == 0x0000
1121 && cris_get_opcode (insn) == 0x000A)
1126 info->sp_offset += cris_get_quick_value (insn);
1129 else if (cris_get_mode (insn) == 0x0002
1130 && cris_get_opcode (insn) == 0x000F
1131 && cris_get_size (insn) == 0x0003
1132 && cris_get_operand1 (insn) == gdbarch_sp_regnum (gdbarch))
1134 /* movem r<regsave>,[sp] */
1135 regsave = cris_get_operand2 (insn);
1137 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1138 && ((insn & 0x0F00) >> 8) == 0x0001
1139 && (cris_get_signed_offset (insn) < 0))
1141 /* Immediate byte offset addressing prefix word with sp as base
1142 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1143 is between 64 and 128.
1144 movem r<regsave>,[sp=sp-<val>] */
1147 info->sp_offset += -cris_get_signed_offset (insn);
1149 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1151 if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE
1152 && cris_get_opcode (insn_next) == 0x000F
1153 && cris_get_size (insn_next) == 0x0003
1154 && cris_get_operand1 (insn_next) == gdbarch_sp_regnum
1157 regsave = cris_get_operand2 (insn_next);
1161 /* The prologue ended before the limit was reached. */
1166 else if (cris_get_mode (insn) == 0x0001
1167 && cris_get_opcode (insn) == 0x0009
1168 && cris_get_size (insn) == 0x0002)
1170 /* move.d r<10..13>,r<0..15> */
1171 source_register = cris_get_operand1 (insn);
1173 /* FIXME? In the glibc solibs, the prologue might contain something
1174 like (this example taken from relocate_doit):
1176 sub.d 0xfffef426,$r0
1177 which isn't covered by the source_register check below. Question
1178 is whether to add a check for this combo, or make better use of
1179 the limit variable instead. */
1180 if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM)
1182 /* The prologue ended before the limit was reached. */
1187 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1188 /* The size is a fixed-size. */
1189 && ((insn & 0x0F00) >> 8) == 0x0001
1190 /* A negative offset. */
1191 && (cris_get_signed_offset (insn) < 0))
1193 /* move.S rZ,[r8-U] (?) */
1194 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1196 regno = cris_get_operand2 (insn_next);
1197 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1198 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1199 && cris_get_opcode (insn_next) == 0x000F)
1201 /* move.S rZ,[r8-U] */
1206 /* The prologue ended before the limit was reached. */
1211 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1212 /* The size is a fixed-size. */
1213 && ((insn & 0x0F00) >> 8) == 0x0001
1214 /* A positive offset. */
1215 && (cris_get_signed_offset (insn) > 0))
1217 /* move.S [r8+U],rZ (?) */
1218 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1220 regno = cris_get_operand2 (insn_next);
1221 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1222 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1223 && cris_get_opcode (insn_next) == 0x0009
1224 && cris_get_operand1 (insn_next) == regno)
1226 /* move.S [r8+U],rZ */
1231 /* The prologue ended before the limit was reached. */
1238 /* The prologue ended before the limit was reached. */
1244 /* We only want to know the end of the prologue when this_frame and info
1245 are NULL (called from cris_skip_prologue i.e.). */
1246 if (this_frame == NULL && info == NULL)
1251 info->size = info->sp_offset;
1253 /* Compute the previous frame's stack pointer (which is also the
1254 frame's ID's stack address), and this frame's base pointer. */
1255 if (info->uses_frame)
1258 /* The SP was moved to the FP. This indicates that a new frame
1259 was created. Get THIS frame's FP value by unwinding it from
1261 this_base = get_frame_register_unsigned (this_frame, CRIS_FP_REGNUM);
1262 info->base = this_base;
1263 info->saved_regs[CRIS_FP_REGNUM].addr = info->base;
1265 /* The FP points at the last saved register. Adjust the FP back
1266 to before the first saved register giving the SP. */
1267 info->prev_sp = info->base + info->r8_offset;
1272 /* Assume that the FP is this frame's SP but with that pushed
1273 stack space added back. */
1274 this_base = get_frame_register_unsigned (this_frame,
1275 gdbarch_sp_regnum (gdbarch));
1276 info->base = this_base;
1277 info->prev_sp = info->base + info->size;
1280 /* Calculate the addresses for the saved registers on the stack. */
1281 /* FIXME: The address calculation should really be done on the fly while
1282 we're analyzing the prologue (we only hold one regsave value as it is
1284 val = info->sp_offset;
1286 for (regno = regsave; regno >= 0; regno--)
1288 info->saved_regs[regno].addr = info->base + info->r8_offset - val;
1292 /* The previous frame's SP needed to be computed. Save the computed
1294 trad_frame_set_value (info->saved_regs,
1295 gdbarch_sp_regnum (gdbarch), info->prev_sp);
1297 if (!info->leaf_function)
1299 /* SRP saved on the stack. But where? */
1300 if (info->r8_offset == 0)
1302 /* R8 not pushed yet. */
1303 info->saved_regs[SRP_REGNUM].addr = info->base;
1307 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1308 info->saved_regs[SRP_REGNUM].addr = info->base + 4;
1312 /* The PC is found in SRP (the actual register or located on the stack). */
1313 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1314 = info->saved_regs[SRP_REGNUM];
1320 crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
1321 struct cris_unwind_cache *info)
1323 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1326 /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not
1327 meant to be a full-fledged prologue scanner. It is only needed for
1328 the cases where we end up in code always lacking DWARF-2 CFI, notably:
1330 * PLT stubs (library calls)
1332 * signal trampolines
1334 For those cases, it is assumed that there is no actual prologue; that
1335 the stack pointer is not adjusted, and (as a consequence) the return
1336 address is not pushed onto the stack. */
1338 /* We only want to know the end of the prologue when this_frame and info
1339 are NULL (called from cris_skip_prologue i.e.). */
1340 if (this_frame == NULL && info == NULL)
1345 /* The SP is assumed to be unaltered. */
1346 this_base = get_frame_register_unsigned (this_frame,
1347 gdbarch_sp_regnum (gdbarch));
1348 info->base = this_base;
1349 info->prev_sp = this_base;
1351 /* The PC is assumed to be found in SRP. */
1352 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1353 = info->saved_regs[SRP_REGNUM];
1358 /* Advance pc beyond any function entry prologue instructions at pc
1359 to reach some "real" code. */
1361 /* Given a PC value corresponding to the start of a function, return the PC
1362 of the first instruction after the function prologue. */
1365 cris_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1367 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1368 CORE_ADDR func_addr, func_end;
1369 struct symtab_and_line sal;
1370 CORE_ADDR pc_after_prologue;
1372 /* If we have line debugging information, then the end of the prologue
1373 should the first assembly instruction of the first source line. */
1374 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1376 sal = find_pc_line (func_addr, 0);
1377 if (sal.end > 0 && sal.end < func_end)
1381 if (tdep->cris_version == 32)
1382 pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL);
1384 pc_after_prologue = cris_scan_prologue (pc, NULL, NULL);
1386 return pc_after_prologue;
1390 cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1393 pc = frame_unwind_register_unsigned (next_frame,
1394 gdbarch_pc_regnum (gdbarch));
1399 cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1402 sp = frame_unwind_register_unsigned (next_frame,
1403 gdbarch_sp_regnum (gdbarch));
1407 /* Use the program counter to determine the contents and size of a breakpoint
1408 instruction. It returns a pointer to a string of bytes that encode a
1409 breakpoint instruction, stores the length of the string to *lenptr, and
1410 adjusts pcptr (if necessary) to point to the actual memory location where
1411 the breakpoint should be inserted. */
1413 static const unsigned char *
1414 cris_breakpoint_from_pc (struct gdbarch *gdbarch,
1415 CORE_ADDR *pcptr, int *lenptr)
1417 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1418 static unsigned char break8_insn[] = {0x38, 0xe9};
1419 static unsigned char break15_insn[] = {0x3f, 0xe9};
1422 if (tdep->cris_mode == cris_mode_guru)
1423 return break15_insn;
1428 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1432 cris_spec_reg_applicable (struct gdbarch *gdbarch,
1433 struct cris_spec_reg spec_reg)
1435 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1436 unsigned int version = tdep->cris_version;
1438 switch (spec_reg.applicable_version)
1440 case cris_ver_version_all:
1442 case cris_ver_warning:
1443 /* Indeterminate/obsolete. */
1446 return (version >= 0 && version <= 3);
1448 return (version >= 3);
1450 return (version == 8 || version == 9);
1452 return (version >= 8);
1453 case cris_ver_v0_10:
1454 return (version >= 0 && version <= 10);
1455 case cris_ver_v3_10:
1456 return (version >= 3 && version <= 10);
1457 case cris_ver_v8_10:
1458 return (version >= 8 && version <= 10);
1460 return (version == 10);
1462 return (version >= 10);
1464 return (version >= 32);
1466 /* Invalid cris version. */
1471 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1472 register, -1 for an invalid register. */
1475 cris_register_size (struct gdbarch *gdbarch, int regno)
1477 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1481 if (regno >= 0 && regno < NUM_GENREGS)
1483 /* General registers (R0 - R15) are 32 bits. */
1486 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1488 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1489 Adjust regno accordingly. */
1490 spec_regno = regno - NUM_GENREGS;
1492 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1494 if (cris_spec_regs[i].number == spec_regno
1495 && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i]))
1496 /* Go with the first applicable register. */
1497 return cris_spec_regs[i].reg_size;
1499 /* Special register not applicable to this CRIS version. */
1502 else if (regno >= gdbarch_pc_regnum (gdbarch)
1503 && regno < gdbarch_num_regs (gdbarch))
1505 /* This will apply to CRISv32 only where there are additional registers
1506 after the special registers (pseudo PC and support registers). */
1514 /* Nonzero if regno should not be fetched from the target. This is the case
1515 for unimplemented (size 0) and non-existant registers. */
1518 cris_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1520 return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1521 || (cris_register_size (gdbarch, regno) == 0));
1524 /* Nonzero if regno should not be written to the target, for various
1528 cris_cannot_store_register (struct gdbarch *gdbarch, int regno)
1530 /* There are three kinds of registers we refuse to write to.
1531 1. Those that not implemented.
1532 2. Those that are read-only (depends on the processor mode).
1533 3. Those registers to which a write has no effect. */
1536 || regno >= gdbarch_num_regs (gdbarch)
1537 || cris_register_size (gdbarch, regno) == 0)
1538 /* Not implemented. */
1541 else if (regno == VR_REGNUM)
1545 else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM)
1546 /* Writing has no effect. */
1549 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
1550 agent decide whether they are writable. */
1555 /* Nonzero if regno should not be fetched from the target. This is the case
1556 for unimplemented (size 0) and non-existant registers. */
1559 crisv32_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1561 return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1562 || (cris_register_size (gdbarch, regno) == 0));
1565 /* Nonzero if regno should not be written to the target, for various
1569 crisv32_cannot_store_register (struct gdbarch *gdbarch, int regno)
1571 /* There are three kinds of registers we refuse to write to.
1572 1. Those that not implemented.
1573 2. Those that are read-only (depends on the processor mode).
1574 3. Those registers to which a write has no effect. */
1577 || regno >= gdbarch_num_regs (gdbarch)
1578 || cris_register_size (gdbarch, regno) == 0)
1579 /* Not implemented. */
1582 else if (regno == VR_REGNUM)
1586 else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM)
1587 /* Writing has no effect. */
1590 /* Many special registers are read-only in user mode. Let the debug
1591 agent decide whether they are writable. */
1596 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1597 of data in register regno. */
1599 static struct type *
1600 cris_register_type (struct gdbarch *gdbarch, int regno)
1602 if (regno == gdbarch_pc_regnum (gdbarch))
1603 return builtin_type (gdbarch)->builtin_func_ptr;
1604 else if (regno == gdbarch_sp_regnum (gdbarch)
1605 || regno == CRIS_FP_REGNUM)
1606 return builtin_type (gdbarch)->builtin_data_ptr;
1607 else if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1608 || (regno >= MOF_REGNUM && regno <= USP_REGNUM))
1609 /* Note: R8 taken care of previous clause. */
1610 return builtin_type (gdbarch)->builtin_uint32;
1611 else if (regno >= P4_REGNUM && regno <= CCR_REGNUM)
1612 return builtin_type (gdbarch)->builtin_uint16;
1613 else if (regno >= P0_REGNUM && regno <= VR_REGNUM)
1614 return builtin_type (gdbarch)->builtin_uint8;
1616 /* Invalid (unimplemented) register. */
1617 return builtin_type (gdbarch)->builtin_int0;
1620 static struct type *
1621 crisv32_register_type (struct gdbarch *gdbarch, int regno)
1623 if (regno == gdbarch_pc_regnum (gdbarch))
1624 return builtin_type (gdbarch)->builtin_func_ptr;
1625 else if (regno == gdbarch_sp_regnum (gdbarch)
1626 || regno == CRIS_FP_REGNUM)
1627 return builtin_type (gdbarch)->builtin_data_ptr;
1628 else if ((regno >= 0 && regno <= ACR_REGNUM)
1629 || (regno >= EXS_REGNUM && regno <= SPC_REGNUM)
1630 || (regno == PID_REGNUM)
1631 || (regno >= S0_REGNUM && regno <= S15_REGNUM))
1632 /* Note: R8 and SP taken care of by previous clause. */
1633 return builtin_type (gdbarch)->builtin_uint32;
1634 else if (regno == WZ_REGNUM)
1635 return builtin_type (gdbarch)->builtin_uint16;
1636 else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM)
1637 return builtin_type (gdbarch)->builtin_uint8;
1640 /* Invalid (unimplemented) register. Should not happen as there are
1641 no unimplemented CRISv32 registers. */
1642 warning (_("crisv32_register_type: unknown regno %d"), regno);
1643 return builtin_type (gdbarch)->builtin_int0;
1647 /* Stores a function return value of type type, where valbuf is the address
1648 of the value to be stored. */
1650 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1653 cris_store_return_value (struct type *type, struct regcache *regcache,
1654 const gdb_byte *valbuf)
1656 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1657 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1659 int len = TYPE_LENGTH (type);
1663 /* Put the return value in R10. */
1664 val = extract_unsigned_integer (valbuf, len, byte_order);
1665 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1669 /* Put the return value in R10 and R11. */
1670 val = extract_unsigned_integer (valbuf, 4, byte_order);
1671 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1672 val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order);
1673 regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val);
1676 error (_("cris_store_return_value: type length too large."));
1679 /* Return the name of register regno as a string. Return NULL for an
1680 invalid or unimplemented register. */
1683 cris_special_register_name (struct gdbarch *gdbarch, int regno)
1688 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1689 Adjust regno accordingly. */
1690 spec_regno = regno - NUM_GENREGS;
1692 /* Assume nothing about the layout of the cris_spec_regs struct
1694 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1696 if (cris_spec_regs[i].number == spec_regno
1697 && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i]))
1698 /* Go with the first applicable register. */
1699 return cris_spec_regs[i].name;
1701 /* Special register not applicable to this CRIS version. */
1706 cris_register_name (struct gdbarch *gdbarch, int regno)
1708 static char *cris_genreg_names[] =
1709 { "r0", "r1", "r2", "r3", \
1710 "r4", "r5", "r6", "r7", \
1711 "r8", "r9", "r10", "r11", \
1712 "r12", "r13", "sp", "pc" };
1714 if (regno >= 0 && regno < NUM_GENREGS)
1716 /* General register. */
1717 return cris_genreg_names[regno];
1719 else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (gdbarch))
1721 return cris_special_register_name (gdbarch, regno);
1725 /* Invalid register. */
1731 crisv32_register_name (struct gdbarch *gdbarch, int regno)
1733 static char *crisv32_genreg_names[] =
1734 { "r0", "r1", "r2", "r3", \
1735 "r4", "r5", "r6", "r7", \
1736 "r8", "r9", "r10", "r11", \
1737 "r12", "r13", "sp", "acr"
1740 static char *crisv32_sreg_names[] =
1741 { "s0", "s1", "s2", "s3", \
1742 "s4", "s5", "s6", "s7", \
1743 "s8", "s9", "s10", "s11", \
1744 "s12", "s13", "s14", "s15"
1747 if (regno >= 0 && regno < NUM_GENREGS)
1749 /* General register. */
1750 return crisv32_genreg_names[regno];
1752 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1754 return cris_special_register_name (gdbarch, regno);
1756 else if (regno == gdbarch_pc_regnum (gdbarch))
1760 else if (regno >= S0_REGNUM && regno <= S15_REGNUM)
1762 return crisv32_sreg_names[regno - S0_REGNUM];
1766 /* Invalid register. */
1771 /* Convert DWARF register number REG to the appropriate register
1772 number used by GDB. */
1775 cris_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1777 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1778 numbering, MOF is 18).
1779 Adapted from gcc/config/cris/cris.h. */
1780 static int cris_dwarf_regmap[] = {
1792 if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap))
1793 regnum = cris_dwarf_regmap[reg];
1796 warning (_("Unmapped DWARF Register #%d encountered."), reg);
1801 /* DWARF-2 frame support. */
1804 cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1805 struct dwarf2_frame_state_reg *reg,
1806 struct frame_info *this_frame)
1808 /* The return address column. */
1809 if (regnum == gdbarch_pc_regnum (gdbarch))
1810 reg->how = DWARF2_FRAME_REG_RA;
1812 /* The call frame address. */
1813 else if (regnum == gdbarch_sp_regnum (gdbarch))
1814 reg->how = DWARF2_FRAME_REG_CFA;
1817 /* Extract from an array regbuf containing the raw register state a function
1818 return value of type type, and copy that, in virtual format, into
1821 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1824 cris_extract_return_value (struct type *type, struct regcache *regcache,
1827 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1828 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1830 int len = TYPE_LENGTH (type);
1834 /* Get the return value from R10. */
1835 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1836 store_unsigned_integer (valbuf, len, byte_order, val);
1840 /* Get the return value from R10 and R11. */
1841 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1842 store_unsigned_integer (valbuf, 4, byte_order, val);
1843 regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val);
1844 store_unsigned_integer (valbuf + 4, len - 4, byte_order, val);
1847 error (_("cris_extract_return_value: type length too large"));
1850 /* Handle the CRIS return value convention. */
1852 static enum return_value_convention
1853 cris_return_value (struct gdbarch *gdbarch, struct value *function,
1854 struct type *type, struct regcache *regcache,
1855 gdb_byte *readbuf, const gdb_byte *writebuf)
1857 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1858 || TYPE_CODE (type) == TYPE_CODE_UNION
1859 || TYPE_LENGTH (type) > 8)
1860 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1861 goes on the stack. */
1862 return RETURN_VALUE_STRUCT_CONVENTION;
1865 cris_extract_return_value (type, regcache, readbuf);
1867 cris_store_return_value (type, regcache, writebuf);
1869 return RETURN_VALUE_REGISTER_CONVENTION;
1872 /* Calculates a value that measures how good inst_args constraints an
1873 instruction. It stems from cris_constraint, found in cris-dis.c. */
1876 constraint (unsigned int insn, const char *inst_args,
1877 inst_env_type *inst_env)
1882 const gdb_byte *s = (const gdb_byte *) inst_args;
1888 if ((insn & 0x30) == 0x30)
1893 /* A prefix operand. */
1894 if (inst_env->prefix_found)
1900 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1901 valid "push" size. In case of special register, it may be != 4. */
1902 if (inst_env->prefix_found)
1908 retval = (((insn >> 0xC) & 0xF) == (insn & 0xF));
1916 tmp = (insn >> 0xC) & 0xF;
1918 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1920 /* Since we match four bits, we will give a value of
1921 4 - 1 = 3 in a match. If there is a corresponding
1922 exact match of a special register in another pattern, it
1923 will get a value of 4, which will be higher. This should
1924 be correct in that an exact pattern would match better that
1926 Note that there is a reason for not returning zero; the
1927 pattern for "clear" is partly matched in the bit-pattern
1928 (the two lower bits must be zero), while the bit-pattern
1929 for a move from a special register is matched in the
1930 register constraint.
1931 This also means we will will have a race condition if
1932 there is a partly match in three bits in the bit pattern. */
1933 if (tmp == cris_spec_regs[i].number)
1940 if (cris_spec_regs[i].name == NULL)
1947 /* Returns the number of bits set in the variable value. */
1950 number_of_bits (unsigned int value)
1952 int number_of_bits = 0;
1956 number_of_bits += 1;
1957 value &= (value - 1);
1959 return number_of_bits;
1962 /* Finds the address that should contain the single step breakpoint(s).
1963 It stems from code in cris-dis.c. */
1966 find_cris_op (unsigned short insn, inst_env_type *inst_env)
1969 int max_level_of_match = -1;
1970 int max_matched = -1;
1973 for (i = 0; cris_opcodes[i].name != NULL; i++)
1975 if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match)
1976 && ((cris_opcodes[i].lose & insn) == 0)
1977 /* Only CRISv10 instructions, please. */
1978 && (cris_opcodes[i].applicable_version != cris_ver_v32p))
1980 level_of_match = constraint (insn, cris_opcodes[i].args, inst_env);
1981 if (level_of_match >= 0)
1984 number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose);
1985 if (level_of_match > max_level_of_match)
1988 max_level_of_match = level_of_match;
1989 if (level_of_match == 16)
1991 /* All bits matched, cannot find better. */
2001 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
2002 actually an internal error. */
2005 find_step_target (struct frame_info *frame, inst_env_type *inst_env)
2009 unsigned short insn;
2010 struct gdbarch *gdbarch = get_frame_arch (frame);
2011 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2013 /* Create a local register image and set the initial state. */
2014 for (i = 0; i < NUM_GENREGS; i++)
2017 (unsigned long) get_frame_register_unsigned (frame, i);
2019 offset = NUM_GENREGS;
2020 for (i = 0; i < NUM_SPECREGS; i++)
2023 (unsigned long) get_frame_register_unsigned (frame, offset + i);
2025 inst_env->branch_found = 0;
2026 inst_env->slot_needed = 0;
2027 inst_env->delay_slot_pc_active = 0;
2028 inst_env->prefix_found = 0;
2029 inst_env->invalid = 0;
2030 inst_env->xflag_found = 0;
2031 inst_env->disable_interrupt = 0;
2032 inst_env->byte_order = byte_order;
2034 /* Look for a step target. */
2037 /* Read an instruction from the client. */
2038 insn = read_memory_unsigned_integer
2039 (inst_env->reg[gdbarch_pc_regnum (gdbarch)], 2, byte_order);
2041 /* If the instruction is not in a delay slot the new content of the
2042 PC is [PC] + 2. If the instruction is in a delay slot it is not
2043 that simple. Since a instruction in a delay slot cannot change
2044 the content of the PC, it does not matter what value PC will have.
2045 Just make sure it is a valid instruction. */
2046 if (!inst_env->delay_slot_pc_active)
2048 inst_env->reg[gdbarch_pc_regnum (gdbarch)] += 2;
2052 inst_env->delay_slot_pc_active = 0;
2053 inst_env->reg[gdbarch_pc_regnum (gdbarch)]
2054 = inst_env->delay_slot_pc;
2056 /* Analyse the present instruction. */
2057 i = find_cris_op (insn, inst_env);
2060 inst_env->invalid = 1;
2064 cris_gdb_func (gdbarch, cris_opcodes[i].op, insn, inst_env);
2066 } while (!inst_env->invalid
2067 && (inst_env->prefix_found || inst_env->xflag_found
2068 || inst_env->slot_needed));
2072 /* There is no hardware single-step support. The function find_step_target
2073 digs through the opcodes in order to find all possible targets.
2074 Either one ordinary target or two targets for branches may be found. */
2077 cris_software_single_step (struct frame_info *frame)
2079 struct gdbarch *gdbarch = get_frame_arch (frame);
2080 struct address_space *aspace = get_frame_address_space (frame);
2081 inst_env_type inst_env;
2083 /* Analyse the present instruction environment and insert
2085 int status = find_step_target (frame, &inst_env);
2088 /* Could not find a target. Things are likely to go downhill
2090 warning (_("CRIS software single step could not find a step target."));
2094 /* Insert at most two breakpoints. One for the next PC content
2095 and possibly another one for a branch, jump, etc. */
2097 = (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (gdbarch)];
2098 insert_single_step_breakpoint (gdbarch, aspace, next_pc);
2099 if (inst_env.branch_found
2100 && (CORE_ADDR) inst_env.branch_break_address != next_pc)
2102 CORE_ADDR branch_target_address
2103 = (CORE_ADDR) inst_env.branch_break_address;
2104 insert_single_step_breakpoint (gdbarch,
2105 aspace, branch_target_address);
2112 /* Calculates the prefix value for quick offset addressing mode. */
2115 quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2117 /* It's invalid to be in a delay slot. You can't have a prefix to this
2118 instruction (not 100% sure). */
2119 if (inst_env->slot_needed || inst_env->prefix_found)
2121 inst_env->invalid = 1;
2125 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2126 inst_env->prefix_value += cris_get_bdap_quick_offset (inst);
2128 /* A prefix doesn't change the xflag_found. But the rest of the flags
2130 inst_env->slot_needed = 0;
2131 inst_env->prefix_found = 1;
2134 /* Updates the autoincrement register. The size of the increment is derived
2135 from the size of the operation. The PC is always kept aligned on even
2139 process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env)
2141 if (size == INST_BYTE_SIZE)
2143 inst_env->reg[cris_get_operand1 (inst)] += 1;
2145 /* The PC must be word aligned, so increase the PC with one
2146 word even if the size is byte. */
2147 if (cris_get_operand1 (inst) == REG_PC)
2149 inst_env->reg[REG_PC] += 1;
2152 else if (size == INST_WORD_SIZE)
2154 inst_env->reg[cris_get_operand1 (inst)] += 2;
2156 else if (size == INST_DWORD_SIZE)
2158 inst_env->reg[cris_get_operand1 (inst)] += 4;
2163 inst_env->invalid = 1;
2167 /* Just a forward declaration. */
2169 static unsigned long get_data_from_address (unsigned short *inst,
2171 enum bfd_endian byte_order);
2173 /* Calculates the prefix value for the general case of offset addressing
2177 bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2179 /* It's invalid to be in a delay slot. */
2180 if (inst_env->slot_needed || inst_env->prefix_found)
2182 inst_env->invalid = 1;
2186 /* The calculation of prefix_value used to be after process_autoincrement,
2187 but that fails for an instruction such as jsr [$r0+12] which is encoded
2188 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
2189 mustn't be incremented until we have read it and what it points at. */
2190 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2192 /* The offset is an indirection of the contents of the operand1 register. */
2193 inst_env->prefix_value +=
2194 get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)],
2195 inst_env->byte_order);
2197 if (cris_get_mode (inst) == AUTOINC_MODE)
2199 process_autoincrement (cris_get_size (inst), inst, inst_env);
2202 /* A prefix doesn't change the xflag_found. But the rest of the flags
2204 inst_env->slot_needed = 0;
2205 inst_env->prefix_found = 1;
2208 /* Calculates the prefix value for the index addressing mode. */
2211 biap_prefix (unsigned short inst, inst_env_type *inst_env)
2213 /* It's invalid to be in a delay slot. I can't see that it's possible to
2214 have a prefix to this instruction. So I will treat this as invalid. */
2215 if (inst_env->slot_needed || inst_env->prefix_found)
2217 inst_env->invalid = 1;
2221 inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)];
2223 /* The offset is the operand2 value shifted the size of the instruction
2225 inst_env->prefix_value +=
2226 inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst);
2228 /* If the PC is operand1 (base) the address used is the address after
2229 the main instruction, i.e. address + 2 (the PC is already compensated
2230 for the prefix operation). */
2231 if (cris_get_operand1 (inst) == REG_PC)
2233 inst_env->prefix_value += 2;
2236 /* A prefix doesn't change the xflag_found. But the rest of the flags
2238 inst_env->slot_needed = 0;
2239 inst_env->xflag_found = 0;
2240 inst_env->prefix_found = 1;
2243 /* Calculates the prefix value for the double indirect addressing mode. */
2246 dip_prefix (unsigned short inst, inst_env_type *inst_env)
2251 /* It's invalid to be in a delay slot. */
2252 if (inst_env->slot_needed || inst_env->prefix_found)
2254 inst_env->invalid = 1;
2258 /* The prefix value is one dereference of the contents of the operand1
2260 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2261 inst_env->prefix_value
2262 = read_memory_unsigned_integer (address, 4, inst_env->byte_order);
2264 /* Check if the mode is autoincrement. */
2265 if (cris_get_mode (inst) == AUTOINC_MODE)
2267 inst_env->reg[cris_get_operand1 (inst)] += 4;
2270 /* A prefix doesn't change the xflag_found. But the rest of the flags
2272 inst_env->slot_needed = 0;
2273 inst_env->xflag_found = 0;
2274 inst_env->prefix_found = 1;
2277 /* Finds the destination for a branch with 8-bits offset. */
2280 eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2285 /* If we have a prefix or are in a delay slot it's bad. */
2286 if (inst_env->slot_needed || inst_env->prefix_found)
2288 inst_env->invalid = 1;
2292 /* We have a branch, find out where the branch will land. */
2293 offset = cris_get_branch_short_offset (inst);
2295 /* Check if the offset is signed. */
2296 if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK)
2301 /* The offset ends with the sign bit, set it to zero. The address
2302 should always be word aligned. */
2303 offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK;
2305 inst_env->branch_found = 1;
2306 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2308 inst_env->slot_needed = 1;
2309 inst_env->prefix_found = 0;
2310 inst_env->xflag_found = 0;
2311 inst_env->disable_interrupt = 1;
2314 /* Finds the destination for a branch with 16-bits offset. */
2317 sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2321 /* If we have a prefix or is in a delay slot it's bad. */
2322 if (inst_env->slot_needed || inst_env->prefix_found)
2324 inst_env->invalid = 1;
2328 /* We have a branch, find out the offset for the branch. */
2329 offset = read_memory_integer (inst_env->reg[REG_PC], 2,
2330 inst_env->byte_order);
2332 /* The instruction is one word longer than normal, so add one word
2334 inst_env->reg[REG_PC] += 2;
2336 inst_env->branch_found = 1;
2337 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2340 inst_env->slot_needed = 1;
2341 inst_env->prefix_found = 0;
2342 inst_env->xflag_found = 0;
2343 inst_env->disable_interrupt = 1;
2346 /* Handles the ABS instruction. */
2349 abs_op (unsigned short inst, inst_env_type *inst_env)
2354 /* ABS can't have a prefix, so it's bad if it does. */
2355 if (inst_env->prefix_found)
2357 inst_env->invalid = 1;
2361 /* Check if the operation affects the PC. */
2362 if (cris_get_operand2 (inst) == REG_PC)
2365 /* It's invalid to change to the PC if we are in a delay slot. */
2366 if (inst_env->slot_needed)
2368 inst_env->invalid = 1;
2372 value = (long) inst_env->reg[REG_PC];
2374 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
2375 if (value != SIGNED_DWORD_MASK)
2378 inst_env->reg[REG_PC] = (long) value;
2382 inst_env->slot_needed = 0;
2383 inst_env->prefix_found = 0;
2384 inst_env->xflag_found = 0;
2385 inst_env->disable_interrupt = 0;
2388 /* Handles the ADDI instruction. */
2391 addi_op (unsigned short inst, inst_env_type *inst_env)
2393 /* It's invalid to have the PC as base register. And ADDI can't have
2395 if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC))
2397 inst_env->invalid = 1;
2401 inst_env->slot_needed = 0;
2402 inst_env->prefix_found = 0;
2403 inst_env->xflag_found = 0;
2404 inst_env->disable_interrupt = 0;
2407 /* Handles the ASR instruction. */
2410 asr_op (unsigned short inst, inst_env_type *inst_env)
2413 unsigned long value;
2414 unsigned long signed_extend_mask = 0;
2416 /* ASR can't have a prefix, so check that it doesn't. */
2417 if (inst_env->prefix_found)
2419 inst_env->invalid = 1;
2423 /* Check if the PC is the target register. */
2424 if (cris_get_operand2 (inst) == REG_PC)
2426 /* It's invalid to change the PC in a delay slot. */
2427 if (inst_env->slot_needed)
2429 inst_env->invalid = 1;
2432 /* Get the number of bits to shift. */
2434 = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]);
2435 value = inst_env->reg[REG_PC];
2437 /* Find out how many bits the operation should apply to. */
2438 if (cris_get_size (inst) == INST_BYTE_SIZE)
2440 if (value & SIGNED_BYTE_MASK)
2442 signed_extend_mask = 0xFF;
2443 signed_extend_mask = signed_extend_mask >> shift_steps;
2444 signed_extend_mask = ~signed_extend_mask;
2446 value = value >> shift_steps;
2447 value |= signed_extend_mask;
2449 inst_env->reg[REG_PC] &= 0xFFFFFF00;
2450 inst_env->reg[REG_PC] |= value;
2452 else if (cris_get_size (inst) == INST_WORD_SIZE)
2454 if (value & SIGNED_WORD_MASK)
2456 signed_extend_mask = 0xFFFF;
2457 signed_extend_mask = signed_extend_mask >> shift_steps;
2458 signed_extend_mask = ~signed_extend_mask;
2460 value = value >> shift_steps;
2461 value |= signed_extend_mask;
2463 inst_env->reg[REG_PC] &= 0xFFFF0000;
2464 inst_env->reg[REG_PC] |= value;
2466 else if (cris_get_size (inst) == INST_DWORD_SIZE)
2468 if (value & SIGNED_DWORD_MASK)
2470 signed_extend_mask = 0xFFFFFFFF;
2471 signed_extend_mask = signed_extend_mask >> shift_steps;
2472 signed_extend_mask = ~signed_extend_mask;
2474 value = value >> shift_steps;
2475 value |= signed_extend_mask;
2476 inst_env->reg[REG_PC] = value;
2479 inst_env->slot_needed = 0;
2480 inst_env->prefix_found = 0;
2481 inst_env->xflag_found = 0;
2482 inst_env->disable_interrupt = 0;
2485 /* Handles the ASRQ instruction. */
2488 asrq_op (unsigned short inst, inst_env_type *inst_env)
2492 unsigned long value;
2493 unsigned long signed_extend_mask = 0;
2495 /* ASRQ can't have a prefix, so check that it doesn't. */
2496 if (inst_env->prefix_found)
2498 inst_env->invalid = 1;
2502 /* Check if the PC is the target register. */
2503 if (cris_get_operand2 (inst) == REG_PC)
2506 /* It's invalid to change the PC in a delay slot. */
2507 if (inst_env->slot_needed)
2509 inst_env->invalid = 1;
2512 /* The shift size is given as a 5 bit quick value, i.e. we don't
2513 want the sign bit of the quick value. */
2514 shift_steps = cris_get_asr_shift_steps (inst);
2515 value = inst_env->reg[REG_PC];
2516 if (value & SIGNED_DWORD_MASK)
2518 signed_extend_mask = 0xFFFFFFFF;
2519 signed_extend_mask = signed_extend_mask >> shift_steps;
2520 signed_extend_mask = ~signed_extend_mask;
2522 value = value >> shift_steps;
2523 value |= signed_extend_mask;
2524 inst_env->reg[REG_PC] = value;
2526 inst_env->slot_needed = 0;
2527 inst_env->prefix_found = 0;
2528 inst_env->xflag_found = 0;
2529 inst_env->disable_interrupt = 0;
2532 /* Handles the AX, EI and SETF instruction. */
2535 ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env)
2537 if (inst_env->prefix_found)
2539 inst_env->invalid = 1;
2542 /* Check if the instruction is setting the X flag. */
2543 if (cris_is_xflag_bit_on (inst))
2545 inst_env->xflag_found = 1;
2549 inst_env->xflag_found = 0;
2551 inst_env->slot_needed = 0;
2552 inst_env->prefix_found = 0;
2553 inst_env->disable_interrupt = 1;
2556 /* Checks if the instruction is in assign mode. If so, it updates the assign
2557 register. Note that check_assign assumes that the caller has checked that
2558 there is a prefix to this instruction. The mode check depends on this. */
2561 check_assign (unsigned short inst, inst_env_type *inst_env)
2563 /* Check if it's an assign addressing mode. */
2564 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2566 /* Assign the prefix value to operand 1. */
2567 inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value;
2571 /* Handles the 2-operand BOUND instruction. */
2574 two_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2576 /* It's invalid to have the PC as the index operand. */
2577 if (cris_get_operand2 (inst) == REG_PC)
2579 inst_env->invalid = 1;
2582 /* Check if we have a prefix. */
2583 if (inst_env->prefix_found)
2585 check_assign (inst, inst_env);
2587 /* Check if this is an autoincrement mode. */
2588 else if (cris_get_mode (inst) == AUTOINC_MODE)
2590 /* It's invalid to change the PC in a delay slot. */
2591 if (inst_env->slot_needed)
2593 inst_env->invalid = 1;
2596 process_autoincrement (cris_get_size (inst), inst, inst_env);
2598 inst_env->slot_needed = 0;
2599 inst_env->prefix_found = 0;
2600 inst_env->xflag_found = 0;
2601 inst_env->disable_interrupt = 0;
2604 /* Handles the 3-operand BOUND instruction. */
2607 three_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2609 /* It's an error if we haven't got a prefix. And it's also an error
2610 if the PC is the destination register. */
2611 if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC))
2613 inst_env->invalid = 1;
2616 inst_env->slot_needed = 0;
2617 inst_env->prefix_found = 0;
2618 inst_env->xflag_found = 0;
2619 inst_env->disable_interrupt = 0;
2622 /* Clears the status flags in inst_env. */
2625 btst_nop_op (unsigned short inst, inst_env_type *inst_env)
2627 /* It's an error if we have got a prefix. */
2628 if (inst_env->prefix_found)
2630 inst_env->invalid = 1;
2634 inst_env->slot_needed = 0;
2635 inst_env->prefix_found = 0;
2636 inst_env->xflag_found = 0;
2637 inst_env->disable_interrupt = 0;
2640 /* Clears the status flags in inst_env. */
2643 clearf_di_op (unsigned short inst, inst_env_type *inst_env)
2645 /* It's an error if we have got a prefix. */
2646 if (inst_env->prefix_found)
2648 inst_env->invalid = 1;
2652 inst_env->slot_needed = 0;
2653 inst_env->prefix_found = 0;
2654 inst_env->xflag_found = 0;
2655 inst_env->disable_interrupt = 1;
2658 /* Handles the CLEAR instruction if it's in register mode. */
2661 reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env)
2663 /* Check if the target is the PC. */
2664 if (cris_get_operand2 (inst) == REG_PC)
2666 /* The instruction will clear the instruction's size bits. */
2667 int clear_size = cris_get_clear_size (inst);
2668 if (clear_size == INST_BYTE_SIZE)
2670 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00;
2672 if (clear_size == INST_WORD_SIZE)
2674 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000;
2676 if (clear_size == INST_DWORD_SIZE)
2678 inst_env->delay_slot_pc = 0x0;
2680 /* The jump will be delayed with one delay slot. So we need a delay
2682 inst_env->slot_needed = 1;
2683 inst_env->delay_slot_pc_active = 1;
2687 /* The PC will not change => no delay slot. */
2688 inst_env->slot_needed = 0;
2690 inst_env->prefix_found = 0;
2691 inst_env->xflag_found = 0;
2692 inst_env->disable_interrupt = 0;
2695 /* Handles the TEST instruction if it's in register mode. */
2698 reg_mode_test_op (unsigned short inst, inst_env_type *inst_env)
2700 /* It's an error if we have got a prefix. */
2701 if (inst_env->prefix_found)
2703 inst_env->invalid = 1;
2706 inst_env->slot_needed = 0;
2707 inst_env->prefix_found = 0;
2708 inst_env->xflag_found = 0;
2709 inst_env->disable_interrupt = 0;
2713 /* Handles the CLEAR and TEST instruction if the instruction isn't
2714 in register mode. */
2717 none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env)
2719 /* Check if we are in a prefix mode. */
2720 if (inst_env->prefix_found)
2722 /* The only way the PC can change is if this instruction is in
2723 assign addressing mode. */
2724 check_assign (inst, inst_env);
2726 /* Indirect mode can't change the PC so just check if the mode is
2728 else if (cris_get_mode (inst) == AUTOINC_MODE)
2730 process_autoincrement (cris_get_size (inst), inst, inst_env);
2732 inst_env->slot_needed = 0;
2733 inst_env->prefix_found = 0;
2734 inst_env->xflag_found = 0;
2735 inst_env->disable_interrupt = 0;
2738 /* Checks that the PC isn't the destination register or the instructions has
2742 dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env)
2744 /* It's invalid to have the PC as the destination. The instruction can't
2746 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2748 inst_env->invalid = 1;
2752 inst_env->slot_needed = 0;
2753 inst_env->prefix_found = 0;
2754 inst_env->xflag_found = 0;
2755 inst_env->disable_interrupt = 0;
2758 /* Checks that the instruction doesn't have a prefix. */
2761 break_op (unsigned short inst, inst_env_type *inst_env)
2763 /* The instruction can't have a prefix. */
2764 if (inst_env->prefix_found)
2766 inst_env->invalid = 1;
2770 inst_env->slot_needed = 0;
2771 inst_env->prefix_found = 0;
2772 inst_env->xflag_found = 0;
2773 inst_env->disable_interrupt = 1;
2776 /* Checks that the PC isn't the destination register and that the instruction
2777 doesn't have a prefix. */
2780 scc_op (unsigned short inst, inst_env_type *inst_env)
2782 /* It's invalid to have the PC as the destination. The instruction can't
2784 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2786 inst_env->invalid = 1;
2790 inst_env->slot_needed = 0;
2791 inst_env->prefix_found = 0;
2792 inst_env->xflag_found = 0;
2793 inst_env->disable_interrupt = 1;
2796 /* Handles the register mode JUMP instruction. */
2799 reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2801 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2802 you can't have a prefix. */
2803 if ((inst_env->slot_needed) || (inst_env->prefix_found))
2805 inst_env->invalid = 1;
2809 /* Just change the PC. */
2810 inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)];
2811 inst_env->slot_needed = 0;
2812 inst_env->prefix_found = 0;
2813 inst_env->xflag_found = 0;
2814 inst_env->disable_interrupt = 1;
2817 /* Handles the JUMP instruction for all modes except register. */
2820 none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2822 unsigned long newpc;
2825 /* It's invalid to do a JUMP in a delay slot. */
2826 if (inst_env->slot_needed)
2828 inst_env->invalid = 1;
2832 /* Check if we have a prefix. */
2833 if (inst_env->prefix_found)
2835 check_assign (inst, inst_env);
2837 /* Get the new value for the PC. */
2839 read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value,
2840 4, inst_env->byte_order);
2844 /* Get the new value for the PC. */
2845 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2846 newpc = read_memory_unsigned_integer (address,
2847 4, inst_env->byte_order);
2849 /* Check if we should increment a register. */
2850 if (cris_get_mode (inst) == AUTOINC_MODE)
2852 inst_env->reg[cris_get_operand1 (inst)] += 4;
2855 inst_env->reg[REG_PC] = newpc;
2857 inst_env->slot_needed = 0;
2858 inst_env->prefix_found = 0;
2859 inst_env->xflag_found = 0;
2860 inst_env->disable_interrupt = 1;
2863 /* Handles moves to special registers (aka P-register) for all modes. */
2866 move_to_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2867 inst_env_type *inst_env)
2869 if (inst_env->prefix_found)
2871 /* The instruction has a prefix that means we are only interested if
2872 the instruction is in assign mode. */
2873 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2875 /* The prefix handles the problem if we are in a delay slot. */
2876 if (cris_get_operand1 (inst) == REG_PC)
2878 /* Just take care of the assign. */
2879 check_assign (inst, inst_env);
2883 else if (cris_get_mode (inst) == AUTOINC_MODE)
2885 /* The instruction doesn't have a prefix, the only case left that we
2886 are interested in is the autoincrement mode. */
2887 if (cris_get_operand1 (inst) == REG_PC)
2889 /* If the PC is to be incremented it's invalid to be in a
2891 if (inst_env->slot_needed)
2893 inst_env->invalid = 1;
2897 /* The increment depends on the size of the special register. */
2898 if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
2900 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2902 else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
2904 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2908 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2912 inst_env->slot_needed = 0;
2913 inst_env->prefix_found = 0;
2914 inst_env->xflag_found = 0;
2915 inst_env->disable_interrupt = 1;
2918 /* Handles moves from special registers (aka P-register) for all modes
2922 none_reg_mode_move_from_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2923 inst_env_type *inst_env)
2925 if (inst_env->prefix_found)
2927 /* The instruction has a prefix that means we are only interested if
2928 the instruction is in assign mode. */
2929 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2931 /* The prefix handles the problem if we are in a delay slot. */
2932 if (cris_get_operand1 (inst) == REG_PC)
2934 /* Just take care of the assign. */
2935 check_assign (inst, inst_env);
2939 /* The instruction doesn't have a prefix, the only case left that we
2940 are interested in is the autoincrement mode. */
2941 else if (cris_get_mode (inst) == AUTOINC_MODE)
2943 if (cris_get_operand1 (inst) == REG_PC)
2945 /* If the PC is to be incremented it's invalid to be in a
2947 if (inst_env->slot_needed)
2949 inst_env->invalid = 1;
2953 /* The increment depends on the size of the special register. */
2954 if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
2956 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2958 else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
2960 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2964 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2968 inst_env->slot_needed = 0;
2969 inst_env->prefix_found = 0;
2970 inst_env->xflag_found = 0;
2971 inst_env->disable_interrupt = 1;
2974 /* Handles moves from special registers (aka P-register) when the mode
2978 reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env)
2980 /* Register mode move from special register can't have a prefix. */
2981 if (inst_env->prefix_found)
2983 inst_env->invalid = 1;
2987 if (cris_get_operand1 (inst) == REG_PC)
2989 /* It's invalid to change the PC in a delay slot. */
2990 if (inst_env->slot_needed)
2992 inst_env->invalid = 1;
2995 /* The destination is the PC, the jump will have a delay slot. */
2996 inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)];
2997 inst_env->slot_needed = 1;
2998 inst_env->delay_slot_pc_active = 1;
3002 /* If the destination isn't PC, there will be no jump. */
3003 inst_env->slot_needed = 0;
3005 inst_env->prefix_found = 0;
3006 inst_env->xflag_found = 0;
3007 inst_env->disable_interrupt = 1;
3010 /* Handles the MOVEM from memory to general register instruction. */
3013 move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env)
3015 if (inst_env->prefix_found)
3017 /* The prefix handles the problem if we are in a delay slot. Is the
3018 MOVEM instruction going to change the PC? */
3019 if (cris_get_operand2 (inst) >= REG_PC)
3021 inst_env->reg[REG_PC] =
3022 read_memory_unsigned_integer (inst_env->prefix_value,
3023 4, inst_env->byte_order);
3025 /* The assign value is the value after the increment. Normally, the
3026 assign value is the value before the increment. */
3027 if ((cris_get_operand1 (inst) == REG_PC)
3028 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3030 inst_env->reg[REG_PC] = inst_env->prefix_value;
3031 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3036 /* Is the MOVEM instruction going to change the PC? */
3037 if (cris_get_operand2 (inst) == REG_PC)
3039 /* It's invalid to change the PC in a delay slot. */
3040 if (inst_env->slot_needed)
3042 inst_env->invalid = 1;
3045 inst_env->reg[REG_PC] =
3046 read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)],
3047 4, inst_env->byte_order);
3049 /* The increment is not depending on the size, instead it's depending
3050 on the number of registers loaded from memory. */
3051 if ((cris_get_operand1 (inst) == REG_PC)
3052 && (cris_get_mode (inst) == AUTOINC_MODE))
3054 /* It's invalid to change the PC in a delay slot. */
3055 if (inst_env->slot_needed)
3057 inst_env->invalid = 1;
3060 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3063 inst_env->slot_needed = 0;
3064 inst_env->prefix_found = 0;
3065 inst_env->xflag_found = 0;
3066 inst_env->disable_interrupt = 0;
3069 /* Handles the MOVEM to memory from general register instruction. */
3072 move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env)
3074 if (inst_env->prefix_found)
3076 /* The assign value is the value after the increment. Normally, the
3077 assign value is the value before the increment. */
3078 if ((cris_get_operand1 (inst) == REG_PC)
3079 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3081 /* The prefix handles the problem if we are in a delay slot. */
3082 inst_env->reg[REG_PC] = inst_env->prefix_value;
3083 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3088 /* The increment is not depending on the size, instead it's depending
3089 on the number of registers loaded to memory. */
3090 if ((cris_get_operand1 (inst) == REG_PC)
3091 && (cris_get_mode (inst) == AUTOINC_MODE))
3093 /* It's invalid to change the PC in a delay slot. */
3094 if (inst_env->slot_needed)
3096 inst_env->invalid = 1;
3099 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3102 inst_env->slot_needed = 0;
3103 inst_env->prefix_found = 0;
3104 inst_env->xflag_found = 0;
3105 inst_env->disable_interrupt = 0;
3108 /* Handles the intructions that's not yet implemented, by setting
3109 inst_env->invalid to true. */
3112 not_implemented_op (unsigned short inst, inst_env_type *inst_env)
3114 inst_env->invalid = 1;
3117 /* Handles the XOR instruction. */
3120 xor_op (unsigned short inst, inst_env_type *inst_env)
3122 /* XOR can't have a prefix. */
3123 if (inst_env->prefix_found)
3125 inst_env->invalid = 1;
3129 /* Check if the PC is the target. */
3130 if (cris_get_operand2 (inst) == REG_PC)
3132 /* It's invalid to change the PC in a delay slot. */
3133 if (inst_env->slot_needed)
3135 inst_env->invalid = 1;
3138 inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)];
3140 inst_env->slot_needed = 0;
3141 inst_env->prefix_found = 0;
3142 inst_env->xflag_found = 0;
3143 inst_env->disable_interrupt = 0;
3146 /* Handles the MULS instruction. */
3149 muls_op (unsigned short inst, inst_env_type *inst_env)
3151 /* MULS/U can't have a prefix. */
3152 if (inst_env->prefix_found)
3154 inst_env->invalid = 1;
3158 /* Consider it invalid if the PC is the target. */
3159 if (cris_get_operand2 (inst) == REG_PC)
3161 inst_env->invalid = 1;
3164 inst_env->slot_needed = 0;
3165 inst_env->prefix_found = 0;
3166 inst_env->xflag_found = 0;
3167 inst_env->disable_interrupt = 0;
3170 /* Handles the MULU instruction. */
3173 mulu_op (unsigned short inst, inst_env_type *inst_env)
3175 /* MULS/U can't have a prefix. */
3176 if (inst_env->prefix_found)
3178 inst_env->invalid = 1;
3182 /* Consider it invalid if the PC is the target. */
3183 if (cris_get_operand2 (inst) == REG_PC)
3185 inst_env->invalid = 1;
3188 inst_env->slot_needed = 0;
3189 inst_env->prefix_found = 0;
3190 inst_env->xflag_found = 0;
3191 inst_env->disable_interrupt = 0;
3194 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
3195 The MOVE instruction is the move from source to register. */
3198 add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env,
3199 unsigned long source1, unsigned long source2)
3201 unsigned long pc_mask;
3202 unsigned long operation_mask;
3204 /* Find out how many bits the operation should apply to. */
3205 if (cris_get_size (inst) == INST_BYTE_SIZE)
3207 pc_mask = 0xFFFFFF00;
3208 operation_mask = 0xFF;
3210 else if (cris_get_size (inst) == INST_WORD_SIZE)
3212 pc_mask = 0xFFFF0000;
3213 operation_mask = 0xFFFF;
3215 else if (cris_get_size (inst) == INST_DWORD_SIZE)
3218 operation_mask = 0xFFFFFFFF;
3222 /* The size is out of range. */
3223 inst_env->invalid = 1;
3227 /* The instruction just works on uw_operation_mask bits. */
3228 source2 &= operation_mask;
3229 source1 &= operation_mask;
3231 /* Now calculate the result. The opcode's 3 first bits separates
3232 the different actions. */
3233 switch (cris_get_opcode (inst) & 7)
3243 case 2: /* subtract */
3247 case 3: /* compare */
3259 inst_env->invalid = 1;
3265 /* Make sure that the result doesn't contain more than the instruction
3267 source2 &= operation_mask;
3269 /* Calculate the new breakpoint address. */
3270 inst_env->reg[REG_PC] &= pc_mask;
3271 inst_env->reg[REG_PC] |= source1;
3275 /* Extends the value from either byte or word size to a dword. If the mode
3276 is zero extend then the value is extended with zero. If instead the mode
3277 is signed extend the sign bit of the value is taken into consideration. */
3279 static unsigned long
3280 do_sign_or_zero_extend (unsigned long value, unsigned short *inst)
3282 /* The size can be either byte or word, check which one it is.
3283 Don't check the highest bit, it's indicating if it's a zero
3285 if (cris_get_size (*inst) & INST_WORD_SIZE)
3290 /* Check if the instruction is signed extend. If so, check if value has
3292 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK))
3294 value |= SIGNED_WORD_EXTEND_MASK;
3302 /* Check if the instruction is signed extend. If so, check if value has
3304 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK))
3306 value |= SIGNED_BYTE_EXTEND_MASK;
3309 /* The size should now be dword. */
3310 cris_set_size_to_dword (inst);
3314 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3315 instruction. The MOVE instruction is the move from source to register. */
3318 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3319 inst_env_type *inst_env)
3321 unsigned long operand1;
3322 unsigned long operand2;
3324 /* It's invalid to have a prefix to the instruction. This is a register
3325 mode instruction and can't have a prefix. */
3326 if (inst_env->prefix_found)
3328 inst_env->invalid = 1;
3331 /* Check if the instruction has PC as its target. */
3332 if (cris_get_operand2 (inst) == REG_PC)
3334 if (inst_env->slot_needed)
3336 inst_env->invalid = 1;
3339 /* The instruction has the PC as its target register. */
3340 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3341 operand2 = inst_env->reg[REG_PC];
3343 /* Check if it's a extend, signed or zero instruction. */
3344 if (cris_get_opcode (inst) < 4)
3346 operand1 = do_sign_or_zero_extend (operand1, &inst);
3348 /* Calculate the PC value after the instruction, i.e. where the
3349 breakpoint should be. The order of the udw_operands is vital. */
3350 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3352 inst_env->slot_needed = 0;
3353 inst_env->prefix_found = 0;
3354 inst_env->xflag_found = 0;
3355 inst_env->disable_interrupt = 0;
3358 /* Returns the data contained at address. The size of the data is derived from
3359 the size of the operation. If the instruction is a zero or signed
3360 extend instruction, the size field is changed in instruction. */
3362 static unsigned long
3363 get_data_from_address (unsigned short *inst, CORE_ADDR address,
3364 enum bfd_endian byte_order)
3366 int size = cris_get_size (*inst);
3367 unsigned long value;
3369 /* If it's an extend instruction we don't want the signed extend bit,
3370 because it influences the size. */
3371 if (cris_get_opcode (*inst) < 4)
3373 size &= ~SIGNED_EXTEND_BIT_MASK;
3375 /* Is there a need for checking the size? Size should contain the number of
3378 value = read_memory_unsigned_integer (address, size, byte_order);
3380 /* Check if it's an extend, signed or zero instruction. */
3381 if (cris_get_opcode (*inst) < 4)
3383 value = do_sign_or_zero_extend (value, inst);
3388 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3389 instructions. The MOVE instruction is the move from source to register. */
3392 handle_prefix_assign_mode_for_aritm_op (unsigned short inst,
3393 inst_env_type *inst_env)
3395 unsigned long operand2;
3396 unsigned long operand3;
3398 check_assign (inst, inst_env);
3399 if (cris_get_operand2 (inst) == REG_PC)
3401 operand2 = inst_env->reg[REG_PC];
3403 /* Get the value of the third operand. */
3404 operand3 = get_data_from_address (&inst, inst_env->prefix_value,
3405 inst_env->byte_order);
3407 /* Calculate the PC value after the instruction, i.e. where the
3408 breakpoint should be. The order of the udw_operands is vital. */
3409 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3411 inst_env->slot_needed = 0;
3412 inst_env->prefix_found = 0;
3413 inst_env->xflag_found = 0;
3414 inst_env->disable_interrupt = 0;
3417 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3418 OR instructions. Note that for this to work as expected, the calling
3419 function must have made sure that there is a prefix to this instruction. */
3422 three_operand_add_sub_cmp_and_or_op (unsigned short inst,
3423 inst_env_type *inst_env)
3425 unsigned long operand2;
3426 unsigned long operand3;
3428 if (cris_get_operand1 (inst) == REG_PC)
3430 /* The PC will be changed by the instruction. */
3431 operand2 = inst_env->reg[cris_get_operand2 (inst)];
3433 /* Get the value of the third operand. */
3434 operand3 = get_data_from_address (&inst, inst_env->prefix_value,
3435 inst_env->byte_order);
3437 /* Calculate the PC value after the instruction, i.e. where the
3438 breakpoint should be. */
3439 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3441 inst_env->slot_needed = 0;
3442 inst_env->prefix_found = 0;
3443 inst_env->xflag_found = 0;
3444 inst_env->disable_interrupt = 0;
3447 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3448 instructions. The MOVE instruction is the move from source to register. */
3451 handle_prefix_index_mode_for_aritm_op (unsigned short inst,
3452 inst_env_type *inst_env)
3454 if (cris_get_operand1 (inst) != cris_get_operand2 (inst))
3456 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
3457 SUB, AND or OR something weird is going on (if everything works these
3458 instructions should end up in the three operand version). */
3459 inst_env->invalid = 1;
3464 /* three_operand_add_sub_cmp_and_or does the same as we should do here
3466 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3468 inst_env->slot_needed = 0;
3469 inst_env->prefix_found = 0;
3470 inst_env->xflag_found = 0;
3471 inst_env->disable_interrupt = 0;
3474 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3475 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
3476 source to register. */
3479 handle_inc_and_index_mode_for_aritm_op (unsigned short inst,
3480 inst_env_type *inst_env)
3482 unsigned long operand1;
3483 unsigned long operand2;
3484 unsigned long operand3;
3487 /* The instruction is either an indirect or autoincrement addressing mode.
3488 Check if the destination register is the PC. */
3489 if (cris_get_operand2 (inst) == REG_PC)
3491 /* Must be done here, get_data_from_address may change the size
3493 size = cris_get_size (inst);
3494 operand2 = inst_env->reg[REG_PC];
3496 /* Get the value of the third operand, i.e. the indirect operand. */
3497 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3498 operand3 = get_data_from_address (&inst, operand1, inst_env->byte_order);
3500 /* Calculate the PC value after the instruction, i.e. where the
3501 breakpoint should be. The order of the udw_operands is vital. */
3502 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3504 /* If this is an autoincrement addressing mode, check if the increment
3506 if ((cris_get_operand1 (inst) == REG_PC)
3507 && (cris_get_mode (inst) == AUTOINC_MODE))
3509 /* Get the size field. */
3510 size = cris_get_size (inst);
3512 /* If it's an extend instruction we don't want the signed extend bit,
3513 because it influences the size. */
3514 if (cris_get_opcode (inst) < 4)
3516 size &= ~SIGNED_EXTEND_BIT_MASK;
3518 process_autoincrement (size, inst, inst_env);
3520 inst_env->slot_needed = 0;
3521 inst_env->prefix_found = 0;
3522 inst_env->xflag_found = 0;
3523 inst_env->disable_interrupt = 0;
3526 /* Handles the two-operand addressing mode, all modes except register, for
3527 the ADD, SUB CMP, AND and OR instruction. */
3530 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3531 inst_env_type *inst_env)
3533 if (inst_env->prefix_found)
3535 if (cris_get_mode (inst) == PREFIX_INDEX_MODE)
3537 handle_prefix_index_mode_for_aritm_op (inst, inst_env);
3539 else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
3541 handle_prefix_assign_mode_for_aritm_op (inst, inst_env);
3545 /* The mode is invalid for a prefixed base instruction. */
3546 inst_env->invalid = 1;
3552 handle_inc_and_index_mode_for_aritm_op (inst, inst_env);
3556 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3559 quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env)
3561 unsigned long operand1;
3562 unsigned long operand2;
3564 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3565 instruction and can't have a prefix. */
3566 if (inst_env->prefix_found)
3568 inst_env->invalid = 1;
3572 /* Check if the instruction has PC as its target. */
3573 if (cris_get_operand2 (inst) == REG_PC)
3575 if (inst_env->slot_needed)
3577 inst_env->invalid = 1;
3580 operand1 = cris_get_quick_value (inst);
3581 operand2 = inst_env->reg[REG_PC];
3583 /* The size should now be dword. */
3584 cris_set_size_to_dword (&inst);
3586 /* Calculate the PC value after the instruction, i.e. where the
3587 breakpoint should be. */
3588 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3590 inst_env->slot_needed = 0;
3591 inst_env->prefix_found = 0;
3592 inst_env->xflag_found = 0;
3593 inst_env->disable_interrupt = 0;
3596 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3599 quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env)
3601 unsigned long operand1;
3602 unsigned long operand2;
3604 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3605 instruction and can't have a prefix. */
3606 if (inst_env->prefix_found)
3608 inst_env->invalid = 1;
3611 /* Check if the instruction has PC as its target. */
3612 if (cris_get_operand2 (inst) == REG_PC)
3614 if (inst_env->slot_needed)
3616 inst_env->invalid = 1;
3619 /* The instruction has the PC as its target register. */
3620 operand1 = cris_get_quick_value (inst);
3621 operand2 = inst_env->reg[REG_PC];
3623 /* The quick value is signed, so check if we must do a signed extend. */
3624 if (operand1 & SIGNED_QUICK_VALUE_MASK)
3627 operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK;
3629 /* The size should now be dword. */
3630 cris_set_size_to_dword (&inst);
3632 /* Calculate the PC value after the instruction, i.e. where the
3633 breakpoint should be. */
3634 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3636 inst_env->slot_needed = 0;
3637 inst_env->prefix_found = 0;
3638 inst_env->xflag_found = 0;
3639 inst_env->disable_interrupt = 0;
3642 /* Translate op_type to a function and call it. */
3645 cris_gdb_func (struct gdbarch *gdbarch, enum cris_op_type op_type,
3646 unsigned short inst, inst_env_type *inst_env)
3650 case cris_not_implemented_op:
3651 not_implemented_op (inst, inst_env);
3655 abs_op (inst, inst_env);
3659 addi_op (inst, inst_env);
3663 asr_op (inst, inst_env);
3667 asrq_op (inst, inst_env);
3670 case cris_ax_ei_setf_op:
3671 ax_ei_setf_op (inst, inst_env);
3674 case cris_bdap_prefix:
3675 bdap_prefix (inst, inst_env);
3678 case cris_biap_prefix:
3679 biap_prefix (inst, inst_env);
3683 break_op (inst, inst_env);
3686 case cris_btst_nop_op:
3687 btst_nop_op (inst, inst_env);
3690 case cris_clearf_di_op:
3691 clearf_di_op (inst, inst_env);
3694 case cris_dip_prefix:
3695 dip_prefix (inst, inst_env);
3698 case cris_dstep_logshift_mstep_neg_not_op:
3699 dstep_logshift_mstep_neg_not_op (inst, inst_env);
3702 case cris_eight_bit_offset_branch_op:
3703 eight_bit_offset_branch_op (inst, inst_env);
3706 case cris_move_mem_to_reg_movem_op:
3707 move_mem_to_reg_movem_op (inst, inst_env);
3710 case cris_move_reg_to_mem_movem_op:
3711 move_reg_to_mem_movem_op (inst, inst_env);
3714 case cris_move_to_preg_op:
3715 move_to_preg_op (gdbarch, inst, inst_env);
3719 muls_op (inst, inst_env);
3723 mulu_op (inst, inst_env);
3726 case cris_none_reg_mode_add_sub_cmp_and_or_move_op:
3727 none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3730 case cris_none_reg_mode_clear_test_op:
3731 none_reg_mode_clear_test_op (inst, inst_env);
3734 case cris_none_reg_mode_jump_op:
3735 none_reg_mode_jump_op (inst, inst_env);
3738 case cris_none_reg_mode_move_from_preg_op:
3739 none_reg_mode_move_from_preg_op (gdbarch, inst, inst_env);
3742 case cris_quick_mode_add_sub_op:
3743 quick_mode_add_sub_op (inst, inst_env);
3746 case cris_quick_mode_and_cmp_move_or_op:
3747 quick_mode_and_cmp_move_or_op (inst, inst_env);
3750 case cris_quick_mode_bdap_prefix:
3751 quick_mode_bdap_prefix (inst, inst_env);
3754 case cris_reg_mode_add_sub_cmp_and_or_move_op:
3755 reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3758 case cris_reg_mode_clear_op:
3759 reg_mode_clear_op (inst, inst_env);
3762 case cris_reg_mode_jump_op:
3763 reg_mode_jump_op (inst, inst_env);
3766 case cris_reg_mode_move_from_preg_op:
3767 reg_mode_move_from_preg_op (inst, inst_env);
3770 case cris_reg_mode_test_op:
3771 reg_mode_test_op (inst, inst_env);
3775 scc_op (inst, inst_env);
3778 case cris_sixteen_bit_offset_branch_op:
3779 sixteen_bit_offset_branch_op (inst, inst_env);
3782 case cris_three_operand_add_sub_cmp_and_or_op:
3783 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3786 case cris_three_operand_bound_op:
3787 three_operand_bound_op (inst, inst_env);
3790 case cris_two_operand_bound_op:
3791 two_operand_bound_op (inst, inst_env);
3795 xor_op (inst, inst_env);
3800 /* This wrapper is to avoid cris_get_assembler being called before
3801 exec_bfd has been set. */
3804 cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info)
3806 int (*print_insn) (bfd_vma addr, struct disassemble_info *info);
3807 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3808 disassembler, even when there is no BFD. Does something like
3809 "gdb; target remote; disassmeble *0x123" work? */
3810 gdb_assert (exec_bfd != NULL);
3811 print_insn = cris_get_disassembler (exec_bfd);
3812 gdb_assert (print_insn != NULL);
3813 return print_insn (addr, info);
3816 /* Originally from <asm/elf.h>. */
3817 typedef unsigned char cris_elf_greg_t[4];
3819 /* Same as user_regs_struct struct in <asm/user.h>. */
3820 #define CRISV10_ELF_NGREG 35
3821 typedef cris_elf_greg_t cris_elf_gregset_t[CRISV10_ELF_NGREG];
3823 #define CRISV32_ELF_NGREG 32
3824 typedef cris_elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG];
3826 /* Unpack a cris_elf_gregset_t into GDB's register cache. */
3829 cris_supply_gregset (struct regcache *regcache, cris_elf_gregset_t *gregsetp)
3831 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3832 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3834 cris_elf_greg_t *regp = *gregsetp;
3836 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3837 knows about the actual size of each register so that's no problem. */
3838 for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++)
3840 regcache_raw_supply (regcache, i, (char *)®p[i]);
3843 if (tdep->cris_version == 32)
3845 /* Needed to set pseudo-register PC for CRISv32. */
3846 /* FIXME: If ERP is in a delay slot at this point then the PC will
3847 be wrong. Issue a warning to alert the user. */
3848 regcache_raw_supply (regcache, gdbarch_pc_regnum (gdbarch),
3849 (char *)®p[ERP_REGNUM]);
3851 if (*(char *)®p[ERP_REGNUM] & 0x1)
3852 fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n");
3856 /* Use a local version of this function to get the correct types for
3857 regsets, until multi-arch core support is ready. */
3860 fetch_core_registers (struct regcache *regcache,
3861 char *core_reg_sect, unsigned core_reg_size,
3862 int which, CORE_ADDR reg_addr)
3864 cris_elf_gregset_t gregset;
3869 if (core_reg_size != sizeof (cris_elf_gregset_t)
3870 && core_reg_size != sizeof (crisv32_elf_gregset_t))
3872 warning (_("wrong size gregset struct in core file"));
3876 memcpy (&gregset, core_reg_sect, sizeof (gregset));
3877 cris_supply_gregset (regcache, &gregset);
3881 /* We've covered all the kinds of registers we know about here,
3882 so this must be something we wouldn't know what to do with
3883 anyway. Just ignore it. */
3888 static struct core_fns cris_elf_core_fns =
3890 bfd_target_elf_flavour, /* core_flavour */
3891 default_check_format, /* check_format */
3892 default_core_sniffer, /* core_sniffer */
3893 fetch_core_registers, /* core_read_registers */
3897 extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */
3900 _initialize_cris_tdep (void)
3902 struct cmd_list_element *c;
3904 gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep);
3906 /* CRIS-specific user-commands. */
3907 add_setshow_zuinteger_cmd ("cris-version", class_support,
3908 &usr_cmd_cris_version,
3909 _("Set the current CRIS version."),
3910 _("Show the current CRIS version."),
3912 Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\
3915 NULL, /* FIXME: i18n: Current CRIS version
3917 &setlist, &showlist);
3919 add_setshow_enum_cmd ("cris-mode", class_support,
3920 cris_modes, &usr_cmd_cris_mode,
3921 _("Set the current CRIS mode."),
3922 _("Show the current CRIS mode."),
3924 Set to CRIS_MODE_GURU when debugging in guru mode.\n\
3925 Makes GDB use the NRP register instead of the ERP register in certain cases."),
3927 NULL, /* FIXME: i18n: Current CRIS version is %s. */
3928 &setlist, &showlist);
3930 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support,
3931 &usr_cmd_cris_dwarf2_cfi,
3932 _("Set the usage of Dwarf-2 CFI for CRIS."),
3933 _("Show the usage of Dwarf-2 CFI for CRIS."),
3934 _("Set this to \"off\" if using gcc-cris < R59."),
3935 set_cris_dwarf2_cfi,
3936 NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI
3938 &setlist, &showlist);
3940 deprecated_add_core_fns (&cris_elf_core_fns);
3943 /* Prints out all target specific values. */
3946 cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3948 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3951 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n",
3952 tdep->cris_version);
3953 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n",
3955 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
3956 tdep->cris_dwarf2_cfi);
3961 set_cris_version (char *ignore_args, int from_tty,
3962 struct cmd_list_element *c)
3964 struct gdbarch_info info;
3966 usr_cmd_cris_version_valid = 1;
3968 /* Update the current architecture, if needed. */
3969 gdbarch_info_init (&info);
3970 if (!gdbarch_update_p (info))
3971 internal_error (__FILE__, __LINE__,
3972 _("cris_gdbarch_update: failed to update architecture."));
3976 set_cris_mode (char *ignore_args, int from_tty,
3977 struct cmd_list_element *c)
3979 struct gdbarch_info info;
3981 /* Update the current architecture, if needed. */
3982 gdbarch_info_init (&info);
3983 if (!gdbarch_update_p (info))
3984 internal_error (__FILE__, __LINE__,
3985 "cris_gdbarch_update: failed to update architecture.");
3989 set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
3990 struct cmd_list_element *c)
3992 struct gdbarch_info info;
3994 /* Update the current architecture, if needed. */
3995 gdbarch_info_init (&info);
3996 if (!gdbarch_update_p (info))
3997 internal_error (__FILE__, __LINE__,
3998 _("cris_gdbarch_update: failed to update architecture."));
4001 static struct gdbarch *
4002 cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
4004 struct gdbarch *gdbarch;
4005 struct gdbarch_tdep *tdep;
4006 unsigned int cris_version;
4008 if (usr_cmd_cris_version_valid)
4010 /* Trust the user's CRIS version setting. */
4011 cris_version = usr_cmd_cris_version;
4013 else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32)
4019 /* Assume it's CRIS version 10. */
4023 /* Make the current settings visible to the user. */
4024 usr_cmd_cris_version = cris_version;
4026 /* Find a candidate among the list of pre-declared architectures. */
4027 for (arches = gdbarch_list_lookup_by_info (arches, &info);
4029 arches = gdbarch_list_lookup_by_info (arches->next, &info))
4031 if ((gdbarch_tdep (arches->gdbarch)->cris_version
4032 == usr_cmd_cris_version)
4033 && (gdbarch_tdep (arches->gdbarch)->cris_mode
4034 == usr_cmd_cris_mode)
4035 && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi
4036 == usr_cmd_cris_dwarf2_cfi))
4037 return arches->gdbarch;
4040 /* No matching architecture was found. Create a new one. */
4041 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
4042 gdbarch = gdbarch_alloc (&info, tdep);
4044 tdep->cris_version = usr_cmd_cris_version;
4045 tdep->cris_mode = usr_cmd_cris_mode;
4046 tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi;
4048 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
4049 switch (info.byte_order)
4051 case BFD_ENDIAN_LITTLE:
4055 case BFD_ENDIAN_BIG:
4056 internal_error (__FILE__, __LINE__,
4057 _("cris_gdbarch_init: big endian byte order in info"));
4061 internal_error (__FILE__, __LINE__,
4062 _("cris_gdbarch_init: unknown byte order in info"));
4065 set_gdbarch_return_value (gdbarch, cris_return_value);
4067 set_gdbarch_sp_regnum (gdbarch, 14);
4069 /* Length of ordinary registers used in push_word and a few other
4070 places. register_size() is the real way to know how big a
4073 set_gdbarch_double_bit (gdbarch, 64);
4074 /* The default definition of a long double is 2 * gdbarch_double_bit,
4075 which means we have to set this explicitly. */
4076 set_gdbarch_long_double_bit (gdbarch, 64);
4078 /* The total amount of space needed to store (in an array called registers)
4079 GDB's copy of the machine's register state. Note: We can not use
4080 cris_register_size at this point, since it relies on gdbarch
4082 switch (tdep->cris_version)
4090 /* Old versions; not supported. */
4091 internal_error (__FILE__, __LINE__,
4092 _("cris_gdbarch_init: unsupported CRIS version"));
4097 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
4098 P7 (32 bits), and P15 (32 bits) have been implemented. */
4099 set_gdbarch_pc_regnum (gdbarch, 15);
4100 set_gdbarch_register_type (gdbarch, cris_register_type);
4101 /* There are 32 registers (some of which may not be implemented). */
4102 set_gdbarch_num_regs (gdbarch, 32);
4103 set_gdbarch_register_name (gdbarch, cris_register_name);
4104 set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register);
4105 set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register);
4107 set_gdbarch_software_single_step (gdbarch, cris_software_single_step);
4111 /* CRIS v32. General registers R0 - R15 (32 bits), special registers
4112 P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
4113 and pseudo-register PC (32 bits). */
4114 set_gdbarch_pc_regnum (gdbarch, 32);
4115 set_gdbarch_register_type (gdbarch, crisv32_register_type);
4116 /* 32 registers + pseudo-register PC + 16 support registers. */
4117 set_gdbarch_num_regs (gdbarch, 32 + 1 + 16);
4118 set_gdbarch_register_name (gdbarch, crisv32_register_name);
4120 set_gdbarch_cannot_store_register
4121 (gdbarch, crisv32_cannot_store_register);
4122 set_gdbarch_cannot_fetch_register
4123 (gdbarch, crisv32_cannot_fetch_register);
4125 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
4127 set_gdbarch_single_step_through_delay
4128 (gdbarch, crisv32_single_step_through_delay);
4133 internal_error (__FILE__, __LINE__,
4134 _("cris_gdbarch_init: unknown CRIS version"));
4137 /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
4138 have the same ABI). */
4139 set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code);
4140 set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call);
4141 set_gdbarch_frame_align (gdbarch, cris_frame_align);
4142 set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue);
4144 /* The stack grows downward. */
4145 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4147 set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc);
4149 set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc);
4150 set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp);
4151 set_gdbarch_dummy_id (gdbarch, cris_dummy_id);
4153 if (tdep->cris_dwarf2_cfi == 1)
4155 /* Hook in the Dwarf-2 frame sniffer. */
4156 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum);
4157 dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg);
4158 dwarf2_append_unwinders (gdbarch);
4161 if (tdep->cris_mode != cris_mode_guru)
4163 frame_unwind_append_unwinder (gdbarch, &cris_sigtramp_frame_unwind);
4166 frame_unwind_append_unwinder (gdbarch, &cris_frame_unwind);
4167 frame_base_set_default (gdbarch, &cris_frame_base);
4169 /* Hook in ABI-specific overrides, if they have been registered. */
4170 gdbarch_init_osabi (info, gdbarch);
4172 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
4173 disassembler, even when there is no BFD. Does something like
4174 "gdb; target remote; disassmeble *0x123" work? */
4175 set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler);