1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 Contributed by Axis Communications AB.
7 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "frame-unwind.h"
27 #include "frame-base.h"
28 #include "trad-frame.h"
29 #include "dwarf2-frame.h"
37 #include "opcode/cris.h"
38 #include "arch-utils.h"
40 #include "gdb_assert.h"
42 /* To get entry_point_address. */
45 #include "solib.h" /* Support for shared libraries. */
46 #include "solib-svr4.h"
47 #include "gdb_string.h"
52 /* There are no floating point registers. Used in gdbserver low-linux.c. */
55 /* There are 16 general registers. */
58 /* There are 16 special registers. */
61 /* CRISv32 has a pseudo PC register, not noted here. */
63 /* CRISv32 has 16 support registers. */
67 /* Register numbers of various important registers.
68 CRIS_FP_REGNUM Contains address of executing stack frame.
69 STR_REGNUM Contains the address of structure return values.
70 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
71 ARG1_REGNUM Contains the first parameter to a function.
72 ARG2_REGNUM Contains the second parameter to a function.
73 ARG3_REGNUM Contains the third parameter to a function.
74 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
75 gdbarch_sp_regnum Contains address of top of stack.
76 gdbarch_pc_regnum Contains address of next instruction.
77 SRP_REGNUM Subroutine return pointer register.
78 BRP_REGNUM Breakpoint return pointer register. */
82 /* Enums with respect to the general registers, valid for all
83 CRIS versions. The frame pointer is always in R8. */
85 /* ABI related registers. */
93 /* Registers which happen to be common. */
98 /* CRISv10 et. al. specific registers. */
110 /* CRISv32 specific registers. */
123 CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */
125 CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */
145 extern const struct cris_spec_reg cris_spec_regs[];
147 /* CRIS version, set via the user command 'set cris-version'. Affects
148 register names and sizes. */
149 static int usr_cmd_cris_version;
151 /* Indicates whether to trust the above variable. */
152 static int usr_cmd_cris_version_valid = 0;
154 static const char cris_mode_normal[] = "normal";
155 static const char cris_mode_guru[] = "guru";
156 static const char *cris_modes[] = {
162 /* CRIS mode, set via the user command 'set cris-mode'. Affects
163 type of break instruction among other things. */
164 static const char *usr_cmd_cris_mode = cris_mode_normal;
166 /* Whether to make use of Dwarf-2 CFI (default on). */
167 static int usr_cmd_cris_dwarf2_cfi = 1;
169 /* CRIS architecture specific information. */
173 const char *cris_mode;
177 /* Functions for accessing target dependent data. */
182 return (gdbarch_tdep (current_gdbarch)->cris_version);
188 return (gdbarch_tdep (current_gdbarch)->cris_mode);
191 /* Sigtramp identification code copied from i386-linux-tdep.c. */
193 #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
194 #define SIGTRAMP_OFFSET0 0
195 #define SIGTRAMP_INSN1 0xe93d /* break 13 */
196 #define SIGTRAMP_OFFSET1 4
198 static const unsigned short sigtramp_code[] =
200 SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */
201 SIGTRAMP_INSN1 /* break 13 */
204 #define SIGTRAMP_LEN (sizeof sigtramp_code)
206 /* Note: same length as normal sigtramp code. */
208 static const unsigned short rt_sigtramp_code[] =
210 SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */
211 SIGTRAMP_INSN1 /* break 13 */
214 /* If PC is in a sigtramp routine, return the address of the start of
215 the routine. Otherwise, return 0. */
218 cris_sigtramp_start (struct frame_info *next_frame)
220 CORE_ADDR pc = frame_pc_unwind (next_frame);
221 gdb_byte buf[SIGTRAMP_LEN];
223 if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN))
226 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
228 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
231 pc -= SIGTRAMP_OFFSET1;
232 if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN))
236 if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0)
242 /* If PC is in a RT sigtramp routine, return the address of the start of
243 the routine. Otherwise, return 0. */
246 cris_rt_sigtramp_start (struct frame_info *next_frame)
248 CORE_ADDR pc = frame_pc_unwind (next_frame);
249 gdb_byte buf[SIGTRAMP_LEN];
251 if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN))
254 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
256 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
259 pc -= SIGTRAMP_OFFSET1;
260 if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN))
264 if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0)
270 /* Assuming NEXT_FRAME is a frame following a GNU/Linux sigtramp
271 routine, return the address of the associated sigcontext structure. */
274 cris_sigcontext_addr (struct frame_info *next_frame)
280 frame_unwind_register (next_frame,
281 gdbarch_sp_regnum (get_frame_arch (next_frame)), buf);
282 sp = extract_unsigned_integer (buf, 4);
284 /* Look for normal sigtramp frame first. */
285 pc = cris_sigtramp_start (next_frame);
288 /* struct signal_frame (arch/cris/kernel/signal.c) contains
289 struct sigcontext as its first member, meaning the SP points to
294 pc = cris_rt_sigtramp_start (next_frame);
297 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
298 a struct ucontext, which in turn contains a struct sigcontext.
300 4 + 4 + 128 to struct ucontext, then
301 4 + 4 + 12 to struct sigcontext. */
305 error (_("Couldn't recognize signal trampoline."));
309 struct cris_unwind_cache
311 /* The previous frame's inner most stack address. Used as this
312 frame ID's stack_addr. */
314 /* The frame's base, optionally used by the high-level debug info. */
317 /* How far the SP and r8 (FP) have been offset from the start of
318 the stack frame (as defined by the previous frame's stack
324 /* From old frame_extra_info struct. */
328 /* Table indicating the location of each and every register. */
329 struct trad_frame_saved_reg *saved_regs;
332 static struct cris_unwind_cache *
333 cris_sigtramp_frame_unwind_cache (struct frame_info *next_frame,
336 struct gdbarch *gdbarch = get_frame_arch (next_frame);
337 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
338 struct cris_unwind_cache *info;
346 return (*this_cache);
348 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
349 (*this_cache) = info;
350 info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
352 /* Zero all fields. */
358 info->uses_frame = 0;
360 info->leaf_function = 0;
362 frame_unwind_register (next_frame, gdbarch_sp_regnum (gdbarch), buf);
363 info->base = extract_unsigned_integer (buf, 4);
365 addr = cris_sigcontext_addr (next_frame);
367 /* Layout of the sigcontext struct:
370 unsigned long oldmask;
374 if (tdep->cris_version == 10)
376 /* R0 to R13 are stored in reverse order at offset (2 * 4) in
378 for (i = 0; i <= 13; i++)
379 info->saved_regs[i].addr = addr + ((15 - i) * 4);
381 info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4);
382 info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4);
383 info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4);
384 /* Note: IRP is off by 2 at this point. There's no point in correcting
385 it though since that will mean that the backtrace will show a PC
386 different from what is shown when stopped. */
387 info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4);
388 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
389 = info->saved_regs[IRP_REGNUM];
390 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr = addr + (24 * 4);
395 /* R0 to R13 are stored in order at offset (1 * 4) in
397 for (i = 0; i <= 13; i++)
398 info->saved_regs[i].addr = addr + ((i + 1) * 4);
400 info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4);
401 info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4);
402 info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4);
403 info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4);
404 info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4);
405 info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4);
406 info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4);
407 info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4);
408 info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4);
410 /* FIXME: If ERP is in a delay slot at this point then the PC will
411 be wrong at this point. This problem manifests itself in the
412 sigaltstack.exp test case, which occasionally generates FAILs when
413 the signal is received while in a delay slot.
415 This could be solved by a couple of read_memory_unsigned_integer and a
416 trad_frame_set_value. */
417 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
418 = info->saved_regs[ERP_REGNUM];
420 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr
428 cris_sigtramp_frame_this_id (struct frame_info *next_frame, void **this_cache,
429 struct frame_id *this_id)
431 struct cris_unwind_cache *cache =
432 cris_sigtramp_frame_unwind_cache (next_frame, this_cache);
433 (*this_id) = frame_id_build (cache->base, frame_pc_unwind (next_frame));
436 /* Forward declaration. */
438 static void cris_frame_prev_register (struct frame_info *next_frame,
439 void **this_prologue_cache,
440 int regnum, int *optimizedp,
441 enum lval_type *lvalp, CORE_ADDR *addrp,
442 int *realnump, gdb_byte *bufferp);
444 cris_sigtramp_frame_prev_register (struct frame_info *next_frame,
446 int regnum, int *optimizedp,
447 enum lval_type *lvalp, CORE_ADDR *addrp,
448 int *realnump, gdb_byte *valuep)
450 /* Make sure we've initialized the cache. */
451 cris_sigtramp_frame_unwind_cache (next_frame, this_cache);
452 cris_frame_prev_register (next_frame, this_cache, regnum,
453 optimizedp, lvalp, addrp, realnump, valuep);
456 static const struct frame_unwind cris_sigtramp_frame_unwind =
459 cris_sigtramp_frame_this_id,
460 cris_sigtramp_frame_prev_register
463 static const struct frame_unwind *
464 cris_sigtramp_frame_sniffer (struct frame_info *next_frame)
466 if (cris_sigtramp_start (next_frame)
467 || cris_rt_sigtramp_start (next_frame))
468 return &cris_sigtramp_frame_unwind;
474 crisv32_single_step_through_delay (struct gdbarch *gdbarch,
475 struct frame_info *this_frame)
477 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
482 if (cris_mode () == cris_mode_guru)
484 frame_unwind_register (this_frame, NRP_REGNUM, buf);
488 frame_unwind_register (this_frame, ERP_REGNUM, buf);
491 erp = extract_unsigned_integer (buf, 4);
495 /* In delay slot - check if there's a breakpoint at the preceding
497 if (breakpoint_here_p (erp & ~0x1))
503 /* Hardware watchpoint support. */
505 /* We support 6 hardware data watchpoints, but cannot trigger on execute
506 (any combination of read/write is fine). */
509 cris_can_use_hardware_watchpoint (int type, int count, int other)
511 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
513 /* No bookkeeping is done here; it is handled by the remote debug agent. */
515 if (tdep->cris_version != 32)
518 /* CRISv32: Six data watchpoints, one for instructions. */
519 return (((type == bp_read_watchpoint || type == bp_access_watchpoint
520 || type == bp_hardware_watchpoint) && count <= 6)
521 || (type == bp_hardware_breakpoint && count <= 1));
524 /* The CRISv32 hardware data watchpoints work by specifying ranges,
525 which have no alignment or length restrictions. */
528 cris_region_ok_for_watchpoint (CORE_ADDR addr, int len)
533 /* If the inferior has some watchpoint that triggered, return the
534 address associated with that watchpoint. Otherwise, return
538 cris_stopped_data_address (void)
541 eda = get_frame_register_unsigned (get_current_frame (), EDA_REGNUM);
545 /* The instruction environment needed to find single-step breakpoints. */
548 struct instruction_environment
550 unsigned long reg[NUM_GENREGS];
551 unsigned long preg[NUM_SPECREGS];
552 unsigned long branch_break_address;
553 unsigned long delay_slot_pc;
554 unsigned long prefix_value;
559 int delay_slot_pc_active;
561 int disable_interrupt;
564 /* Machine-dependencies in CRIS for opcodes. */
566 /* Instruction sizes. */
567 enum cris_instruction_sizes
574 /* Addressing modes. */
575 enum cris_addressing_modes
582 /* Prefix addressing modes. */
583 enum cris_prefix_addressing_modes
585 PREFIX_INDEX_MODE = 2,
586 PREFIX_ASSIGN_MODE = 3,
588 /* Handle immediate byte offset addressing mode prefix format. */
589 PREFIX_OFFSET_MODE = 2
592 /* Masks for opcodes. */
593 enum cris_opcode_masks
595 BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1,
596 SIGNED_EXTEND_BIT_MASK = 0x2,
597 SIGNED_BYTE_MASK = 0x80,
598 SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00,
599 SIGNED_WORD_MASK = 0x8000,
600 SIGNED_WORD_EXTEND_MASK = 0xFFFF0000,
601 SIGNED_DWORD_MASK = 0x80000000,
602 SIGNED_QUICK_VALUE_MASK = 0x20,
603 SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0
606 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
614 cris_get_operand2 (unsigned short insn)
616 return ((insn & 0xF000) >> 12);
620 cris_get_mode (unsigned short insn)
622 return ((insn & 0x0C00) >> 10);
626 cris_get_opcode (unsigned short insn)
628 return ((insn & 0x03C0) >> 6);
632 cris_get_size (unsigned short insn)
634 return ((insn & 0x0030) >> 4);
638 cris_get_operand1 (unsigned short insn)
640 return (insn & 0x000F);
643 /* Additional functions in order to handle opcodes. */
646 cris_get_quick_value (unsigned short insn)
648 return (insn & 0x003F);
652 cris_get_bdap_quick_offset (unsigned short insn)
654 return (insn & 0x00FF);
658 cris_get_branch_short_offset (unsigned short insn)
660 return (insn & 0x00FF);
664 cris_get_asr_shift_steps (unsigned long value)
666 return (value & 0x3F);
670 cris_get_clear_size (unsigned short insn)
672 return ((insn) & 0xC000);
676 cris_is_signed_extend_bit_on (unsigned short insn)
678 return (((insn) & 0x20) == 0x20);
682 cris_is_xflag_bit_on (unsigned short insn)
684 return (((insn) & 0x1000) == 0x1000);
688 cris_set_size_to_dword (unsigned short *insn)
695 cris_get_signed_offset (unsigned short insn)
697 return ((signed char) (insn & 0x00FF));
700 /* Calls an op function given the op-type, working on the insn and the
702 static void cris_gdb_func (enum cris_op_type, unsigned short, inst_env_type *);
704 static struct gdbarch *cris_gdbarch_init (struct gdbarch_info,
705 struct gdbarch_list *);
707 static void cris_dump_tdep (struct gdbarch *, struct ui_file *);
709 static void set_cris_version (char *ignore_args, int from_tty,
710 struct cmd_list_element *c);
712 static void set_cris_mode (char *ignore_args, int from_tty,
713 struct cmd_list_element *c);
715 static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
716 struct cmd_list_element *c);
718 static CORE_ADDR cris_scan_prologue (CORE_ADDR pc,
719 struct frame_info *next_frame,
720 struct cris_unwind_cache *info);
722 static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc,
723 struct frame_info *next_frame,
724 struct cris_unwind_cache *info);
726 static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch,
727 struct frame_info *next_frame);
729 static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch,
730 struct frame_info *next_frame);
732 /* When arguments must be pushed onto the stack, they go on in reverse
733 order. The below implements a FILO (stack) to do this.
734 Copied from d10v-tdep.c. */
739 struct stack_item *prev;
743 static struct stack_item *
744 push_stack_item (struct stack_item *prev, void *contents, int len)
746 struct stack_item *si;
747 si = xmalloc (sizeof (struct stack_item));
748 si->data = xmalloc (len);
751 memcpy (si->data, contents, len);
755 static struct stack_item *
756 pop_stack_item (struct stack_item *si)
758 struct stack_item *dead = si;
765 /* Put here the code to store, into fi->saved_regs, the addresses of
766 the saved registers of frame described by FRAME_INFO. This
767 includes special registers such as pc and fp saved in special ways
768 in the stack frame. sp is even more special: the address we return
769 for it IS the sp for the next frame. */
771 struct cris_unwind_cache *
772 cris_frame_unwind_cache (struct frame_info *next_frame,
773 void **this_prologue_cache)
776 struct cris_unwind_cache *info;
779 if ((*this_prologue_cache))
780 return (*this_prologue_cache);
782 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
783 (*this_prologue_cache) = info;
784 info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
786 /* Zero all fields. */
792 info->uses_frame = 0;
794 info->leaf_function = 0;
796 /* Prologue analysis does the rest... */
797 if (cris_version () == 32)
798 crisv32_scan_prologue (frame_func_unwind (next_frame, NORMAL_FRAME),
801 cris_scan_prologue (frame_func_unwind (next_frame, NORMAL_FRAME),
807 /* Given a GDB frame, determine the address of the calling function's
808 frame. This will be used to create a new GDB frame struct. */
811 cris_frame_this_id (struct frame_info *next_frame,
812 void **this_prologue_cache,
813 struct frame_id *this_id)
815 struct cris_unwind_cache *info
816 = cris_frame_unwind_cache (next_frame, this_prologue_cache);
821 /* The FUNC is easy. */
822 func = frame_func_unwind (next_frame, NORMAL_FRAME);
824 /* Hopefully the prologue analysis either correctly determined the
825 frame's base (which is the SP from the previous frame), or set
826 that base to "NULL". */
827 base = info->prev_sp;
831 id = frame_id_build (base, func);
837 cris_frame_prev_register (struct frame_info *next_frame,
838 void **this_prologue_cache,
839 int regnum, int *optimizedp,
840 enum lval_type *lvalp, CORE_ADDR *addrp,
841 int *realnump, gdb_byte *bufferp)
843 struct cris_unwind_cache *info
844 = cris_frame_unwind_cache (next_frame, this_prologue_cache);
845 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
846 optimizedp, lvalp, addrp, realnump, bufferp);
849 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
850 dummy frame. The frame ID's base needs to match the TOS value
851 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
854 static struct frame_id
855 cris_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
857 return frame_id_build (cris_unwind_sp (gdbarch, next_frame),
858 frame_pc_unwind (next_frame));
862 cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
864 /* Align to the size of an instruction (so that they can safely be
865 pushed onto the stack). */
870 cris_push_dummy_code (struct gdbarch *gdbarch,
871 CORE_ADDR sp, CORE_ADDR funaddr,
872 struct value **args, int nargs,
873 struct type *value_type,
874 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
875 struct regcache *regcache)
877 /* Allocate space sufficient for a breakpoint. */
879 /* Store the address of that breakpoint */
881 /* CRIS always starts the call at the callee's entry point. */
887 cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
888 struct regcache *regcache, CORE_ADDR bp_addr,
889 int nargs, struct value **args, CORE_ADDR sp,
890 int struct_return, CORE_ADDR struct_addr)
899 /* The function's arguments and memory allocated by gdb for the arguments to
900 point at reside in separate areas on the stack.
901 Both frame pointers grow toward higher addresses. */
905 struct stack_item *si = NULL;
907 /* Push the return address. */
908 regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr);
910 /* Are we returning a value using a structure return or a normal value
911 return? struct_addr is the address of the reserved space for the return
912 structure to be written on the stack. */
915 regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr);
918 /* Now load as many as possible of the first arguments into registers,
919 and push the rest onto the stack. */
920 argreg = ARG1_REGNUM;
923 for (argnum = 0; argnum < nargs; argnum++)
930 len = TYPE_LENGTH (value_type (args[argnum]));
931 val = (char *) value_contents (args[argnum]);
933 /* How may registers worth of storage do we need for this argument? */
934 reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0);
936 if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM))
938 /* Data passed by value. Fits in available register(s). */
939 for (i = 0; i < reg_demand; i++)
941 regcache_cooked_write (regcache, argreg, val);
946 else if (len <= (2 * 4) && argreg <= ARG4_REGNUM)
948 /* Data passed by value. Does not fit in available register(s).
949 Use the register(s) first, then the stack. */
950 for (i = 0; i < reg_demand; i++)
952 if (argreg <= ARG4_REGNUM)
954 regcache_cooked_write (regcache, argreg, val);
960 /* Push item for later so that pushed arguments
961 come in the right order. */
962 si = push_stack_item (si, val, 4);
967 else if (len > (2 * 4))
969 /* Data passed by reference. Push copy of data onto stack
970 and pass pointer to this copy as argument. */
971 sp = (sp - len) & ~3;
972 write_memory (sp, val, len);
974 if (argreg <= ARG4_REGNUM)
976 regcache_cooked_write_unsigned (regcache, argreg, sp);
982 store_unsigned_integer (buf, 4, sp);
983 si = push_stack_item (si, buf, 4);
988 /* Data passed by value. No available registers. Put it on
990 si = push_stack_item (si, val, len);
996 /* fp_arg must be word-aligned (i.e., don't += len) to match
997 the function prologue. */
998 sp = (sp - si->len) & ~3;
999 write_memory (sp, si->data, si->len);
1000 si = pop_stack_item (si);
1003 /* Finally, update the SP register. */
1004 regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp);
1009 static const struct frame_unwind cris_frame_unwind =
1013 cris_frame_prev_register
1016 const struct frame_unwind *
1017 cris_frame_sniffer (struct frame_info *next_frame)
1019 return &cris_frame_unwind;
1023 cris_frame_base_address (struct frame_info *next_frame, void **this_cache)
1025 struct cris_unwind_cache *info
1026 = cris_frame_unwind_cache (next_frame, this_cache);
1030 static const struct frame_base cris_frame_base =
1033 cris_frame_base_address,
1034 cris_frame_base_address,
1035 cris_frame_base_address
1038 /* Frames information. The definition of the struct frame_info is
1042 enum frame_type type;
1046 If the compilation option -fno-omit-frame-pointer is present the
1047 variable frame will be set to the content of R8 which is the frame
1050 The variable pc contains the address where execution is performed
1051 in the present frame. The innermost frame contains the current content
1052 of the register PC. All other frames contain the content of the
1053 register PC in the next frame.
1055 The variable `type' indicates the frame's type: normal, SIGTRAMP
1056 (associated with a signal handler), dummy (associated with a dummy
1059 The variable return_pc contains the address where execution should be
1060 resumed when the present frame has finished, the return address.
1062 The variable leaf_function is 1 if the return address is in the register
1063 SRP, and 0 if it is on the stack.
1065 Prologue instructions C-code.
1066 The prologue may consist of (-fno-omit-frame-pointer)
1070 move.d sp,r8 move.d sp,r8
1072 movem rY,[sp] movem rY,[sp]
1073 move.S rZ,[r8-U] move.S rZ,[r8-U]
1075 where 1 is a non-terminal function, and 2 is a leaf-function.
1077 Note that this assumption is extremely brittle, and will break at the
1078 slightest change in GCC's prologue.
1080 If local variables are declared or register contents are saved on stack
1081 the subq-instruction will be present with X as the number of bytes
1082 needed for storage. The reshuffle with respect to r8 may be performed
1083 with any size S (b, w, d) and any of the general registers Z={0..13}.
1084 The offset U should be representable by a signed 8-bit value in all cases.
1085 Thus, the prefix word is assumed to be immediate byte offset mode followed
1086 by another word containing the instruction.
1095 Prologue instructions C++-code.
1096 Case 1) and 2) in the C-code may be followed by
1098 move.d r10,rS ; this
1102 move.S [r8+U],rZ ; P4
1104 if any of the call parameters are stored. The host expects these
1105 instructions to be executed in order to get the call parameters right. */
1107 /* Examine the prologue of a function. The variable ip is the address of
1108 the first instruction of the prologue. The variable limit is the address
1109 of the first instruction after the prologue. The variable fi contains the
1110 information in struct frame_info. The variable frameless_p controls whether
1111 the entire prologue is examined (0) or just enough instructions to
1112 determine that it is a prologue (1). */
1115 cris_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame,
1116 struct cris_unwind_cache *info)
1118 struct gdbarch *gdbarch = get_frame_arch (next_frame);
1119 /* Present instruction. */
1120 unsigned short insn;
1122 /* Next instruction, lookahead. */
1123 unsigned short insn_next;
1126 /* Is there a push fp? */
1129 /* Number of byte on stack used for local variables and movem. */
1132 /* Highest register number in a movem. */
1135 /* move.d r<source_register>,rS */
1136 short source_register;
1141 /* This frame is with respect to a leaf until a push srp is found. */
1144 info->leaf_function = 1;
1147 /* Assume nothing on stack. */
1151 /* If we were called without a next_frame, that means we were called
1152 from cris_skip_prologue which already tried to find the end of the
1153 prologue through the symbol information. 64 instructions past current
1154 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
1155 limit = next_frame ? frame_pc_unwind (next_frame) : pc + 64;
1157 /* Find the prologue instructions. */
1158 while (pc > 0 && pc < limit)
1160 insn = read_memory_unsigned_integer (pc, 2);
1164 /* push <reg> 32 bit instruction */
1165 insn_next = read_memory_unsigned_integer (pc, 2);
1167 regno = cris_get_operand2 (insn_next);
1170 info->sp_offset += 4;
1172 /* This check, meant to recognize srp, used to be regno ==
1173 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
1174 if (insn_next == 0xBE7E)
1178 info->leaf_function = 0;
1181 else if (insn_next == 0x8FEE)
1186 info->r8_offset = info->sp_offset;
1190 else if (insn == 0x866E)
1195 info->uses_frame = 1;
1199 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1200 && cris_get_mode (insn) == 0x0000
1201 && cris_get_opcode (insn) == 0x000A)
1206 info->sp_offset += cris_get_quick_value (insn);
1209 else if (cris_get_mode (insn) == 0x0002
1210 && cris_get_opcode (insn) == 0x000F
1211 && cris_get_size (insn) == 0x0003
1212 && cris_get_operand1 (insn) == gdbarch_sp_regnum (gdbarch))
1214 /* movem r<regsave>,[sp] */
1215 regsave = cris_get_operand2 (insn);
1217 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1218 && ((insn & 0x0F00) >> 8) == 0x0001
1219 && (cris_get_signed_offset (insn) < 0))
1221 /* Immediate byte offset addressing prefix word with sp as base
1222 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1223 is between 64 and 128.
1224 movem r<regsave>,[sp=sp-<val>] */
1227 info->sp_offset += -cris_get_signed_offset (insn);
1229 insn_next = read_memory_unsigned_integer (pc, 2);
1231 if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE
1232 && cris_get_opcode (insn_next) == 0x000F
1233 && cris_get_size (insn_next) == 0x0003
1234 && cris_get_operand1 (insn_next) == gdbarch_sp_regnum
1237 regsave = cris_get_operand2 (insn_next);
1241 /* The prologue ended before the limit was reached. */
1246 else if (cris_get_mode (insn) == 0x0001
1247 && cris_get_opcode (insn) == 0x0009
1248 && cris_get_size (insn) == 0x0002)
1250 /* move.d r<10..13>,r<0..15> */
1251 source_register = cris_get_operand1 (insn);
1253 /* FIXME? In the glibc solibs, the prologue might contain something
1254 like (this example taken from relocate_doit):
1256 sub.d 0xfffef426,$r0
1257 which isn't covered by the source_register check below. Question
1258 is whether to add a check for this combo, or make better use of
1259 the limit variable instead. */
1260 if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM)
1262 /* The prologue ended before the limit was reached. */
1267 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1268 /* The size is a fixed-size. */
1269 && ((insn & 0x0F00) >> 8) == 0x0001
1270 /* A negative offset. */
1271 && (cris_get_signed_offset (insn) < 0))
1273 /* move.S rZ,[r8-U] (?) */
1274 insn_next = read_memory_unsigned_integer (pc, 2);
1276 regno = cris_get_operand2 (insn_next);
1277 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1278 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1279 && cris_get_opcode (insn_next) == 0x000F)
1281 /* move.S rZ,[r8-U] */
1286 /* The prologue ended before the limit was reached. */
1291 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1292 /* The size is a fixed-size. */
1293 && ((insn & 0x0F00) >> 8) == 0x0001
1294 /* A positive offset. */
1295 && (cris_get_signed_offset (insn) > 0))
1297 /* move.S [r8+U],rZ (?) */
1298 insn_next = read_memory_unsigned_integer (pc, 2);
1300 regno = cris_get_operand2 (insn_next);
1301 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1302 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1303 && cris_get_opcode (insn_next) == 0x0009
1304 && cris_get_operand1 (insn_next) == regno)
1306 /* move.S [r8+U],rZ */
1311 /* The prologue ended before the limit was reached. */
1318 /* The prologue ended before the limit was reached. */
1324 /* We only want to know the end of the prologue when next_frame and info
1325 are NULL (called from cris_skip_prologue i.e.). */
1326 if (next_frame == NULL && info == NULL)
1331 info->size = info->sp_offset;
1333 /* Compute the previous frame's stack pointer (which is also the
1334 frame's ID's stack address), and this frame's base pointer. */
1335 if (info->uses_frame)
1338 /* The SP was moved to the FP. This indicates that a new frame
1339 was created. Get THIS frame's FP value by unwinding it from
1341 this_base = frame_unwind_register_unsigned (next_frame, CRIS_FP_REGNUM);
1342 info->base = this_base;
1343 info->saved_regs[CRIS_FP_REGNUM].addr = info->base;
1345 /* The FP points at the last saved register. Adjust the FP back
1346 to before the first saved register giving the SP. */
1347 info->prev_sp = info->base + info->r8_offset;
1352 /* Assume that the FP is this frame's SP but with that pushed
1353 stack space added back. */
1354 this_base = frame_unwind_register_unsigned (next_frame,
1355 gdbarch_sp_regnum (gdbarch));
1356 info->base = this_base;
1357 info->prev_sp = info->base + info->size;
1360 /* Calculate the addresses for the saved registers on the stack. */
1361 /* FIXME: The address calculation should really be done on the fly while
1362 we're analyzing the prologue (we only hold one regsave value as it is
1364 val = info->sp_offset;
1366 for (regno = regsave; regno >= 0; regno--)
1368 info->saved_regs[regno].addr = info->base + info->r8_offset - val;
1372 /* The previous frame's SP needed to be computed. Save the computed
1374 trad_frame_set_value (info->saved_regs,
1375 gdbarch_sp_regnum (gdbarch), info->prev_sp);
1377 if (!info->leaf_function)
1379 /* SRP saved on the stack. But where? */
1380 if (info->r8_offset == 0)
1382 /* R8 not pushed yet. */
1383 info->saved_regs[SRP_REGNUM].addr = info->base;
1387 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1388 info->saved_regs[SRP_REGNUM].addr = info->base + 4;
1392 /* The PC is found in SRP (the actual register or located on the stack). */
1393 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1394 = info->saved_regs[SRP_REGNUM];
1400 crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame,
1401 struct cris_unwind_cache *info)
1403 struct gdbarch *gdbarch = get_frame_arch (next_frame);
1406 /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not
1407 meant to be a full-fledged prologue scanner. It is only needed for
1408 the cases where we end up in code always lacking DWARF-2 CFI, notably:
1410 * PLT stubs (library calls)
1412 * signal trampolines
1414 For those cases, it is assumed that there is no actual prologue; that
1415 the stack pointer is not adjusted, and (as a consequence) the return
1416 address is not pushed onto the stack. */
1418 /* We only want to know the end of the prologue when next_frame and info
1419 are NULL (called from cris_skip_prologue i.e.). */
1420 if (next_frame == NULL && info == NULL)
1425 /* The SP is assumed to be unaltered. */
1426 this_base = frame_unwind_register_unsigned (next_frame,
1427 gdbarch_sp_regnum (gdbarch));
1428 info->base = this_base;
1429 info->prev_sp = this_base;
1431 /* The PC is assumed to be found in SRP. */
1432 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1433 = info->saved_regs[SRP_REGNUM];
1438 /* Advance pc beyond any function entry prologue instructions at pc
1439 to reach some "real" code. */
1441 /* Given a PC value corresponding to the start of a function, return the PC
1442 of the first instruction after the function prologue. */
1445 cris_skip_prologue (CORE_ADDR pc)
1447 CORE_ADDR func_addr, func_end;
1448 struct symtab_and_line sal;
1449 CORE_ADDR pc_after_prologue;
1451 /* If we have line debugging information, then the end of the prologue
1452 should the first assembly instruction of the first source line. */
1453 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1455 sal = find_pc_line (func_addr, 0);
1456 if (sal.end > 0 && sal.end < func_end)
1460 if (cris_version () == 32)
1461 pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL);
1463 pc_after_prologue = cris_scan_prologue (pc, NULL, NULL);
1465 return pc_after_prologue;
1469 cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1472 pc = frame_unwind_register_unsigned (next_frame,
1473 gdbarch_pc_regnum (gdbarch));
1478 cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1481 sp = frame_unwind_register_unsigned (next_frame,
1482 gdbarch_sp_regnum (gdbarch));
1486 /* Use the program counter to determine the contents and size of a breakpoint
1487 instruction. It returns a pointer to a string of bytes that encode a
1488 breakpoint instruction, stores the length of the string to *lenptr, and
1489 adjusts pcptr (if necessary) to point to the actual memory location where
1490 the breakpoint should be inserted. */
1492 static const unsigned char *
1493 cris_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
1495 static unsigned char break8_insn[] = {0x38, 0xe9};
1496 static unsigned char break15_insn[] = {0x3f, 0xe9};
1499 if (cris_mode () == cris_mode_guru)
1500 return break15_insn;
1505 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1509 cris_spec_reg_applicable (struct cris_spec_reg spec_reg)
1511 int version = cris_version ();
1513 switch (spec_reg.applicable_version)
1515 case cris_ver_version_all:
1517 case cris_ver_warning:
1518 /* Indeterminate/obsolete. */
1521 return (version >= 0 && version <= 3);
1523 return (version >= 3);
1525 return (version == 8 || version == 9);
1527 return (version >= 8);
1528 case cris_ver_v0_10:
1529 return (version >= 0 && version <= 10);
1530 case cris_ver_v3_10:
1531 return (version >= 3 && version <= 10);
1532 case cris_ver_v8_10:
1533 return (version >= 8 && version <= 10);
1535 return (version == 10);
1537 return (version >= 10);
1539 return (version >= 32);
1541 /* Invalid cris version. */
1546 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1547 register, -1 for an invalid register. */
1550 cris_register_size (int regno)
1552 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1556 if (regno >= 0 && regno < NUM_GENREGS)
1558 /* General registers (R0 - R15) are 32 bits. */
1561 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1563 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1564 Adjust regno accordingly. */
1565 spec_regno = regno - NUM_GENREGS;
1567 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1569 if (cris_spec_regs[i].number == spec_regno
1570 && cris_spec_reg_applicable (cris_spec_regs[i]))
1571 /* Go with the first applicable register. */
1572 return cris_spec_regs[i].reg_size;
1574 /* Special register not applicable to this CRIS version. */
1577 else if (regno >= gdbarch_pc_regnum (current_gdbarch)
1578 && regno < gdbarch_num_regs (current_gdbarch))
1580 /* This will apply to CRISv32 only where there are additional registers
1581 after the special registers (pseudo PC and support registers). */
1589 /* Nonzero if regno should not be fetched from the target. This is the case
1590 for unimplemented (size 0) and non-existant registers. */
1593 cris_cannot_fetch_register (int regno)
1595 return ((regno < 0 || regno >= gdbarch_num_regs (current_gdbarch))
1596 || (cris_register_size (regno) == 0));
1599 /* Nonzero if regno should not be written to the target, for various
1603 cris_cannot_store_register (int regno)
1605 /* There are three kinds of registers we refuse to write to.
1606 1. Those that not implemented.
1607 2. Those that are read-only (depends on the processor mode).
1608 3. Those registers to which a write has no effect.
1612 || regno >= gdbarch_num_regs (current_gdbarch)
1613 || cris_register_size (regno) == 0)
1614 /* Not implemented. */
1617 else if (regno == VR_REGNUM)
1621 else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM)
1622 /* Writing has no effect. */
1625 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
1626 agent decide whether they are writable. */
1631 /* Nonzero if regno should not be fetched from the target. This is the case
1632 for unimplemented (size 0) and non-existant registers. */
1635 crisv32_cannot_fetch_register (int regno)
1637 return ((regno < 0 || regno >= gdbarch_num_regs (current_gdbarch))
1638 || (cris_register_size (regno) == 0));
1641 /* Nonzero if regno should not be written to the target, for various
1645 crisv32_cannot_store_register (int regno)
1647 /* There are three kinds of registers we refuse to write to.
1648 1. Those that not implemented.
1649 2. Those that are read-only (depends on the processor mode).
1650 3. Those registers to which a write has no effect.
1654 || regno >= gdbarch_num_regs (current_gdbarch)
1655 || cris_register_size (regno) == 0)
1656 /* Not implemented. */
1659 else if (regno == VR_REGNUM)
1663 else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM)
1664 /* Writing has no effect. */
1667 /* Many special registers are read-only in user mode. Let the debug
1668 agent decide whether they are writable. */
1673 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1674 of data in register regno. */
1676 static struct type *
1677 cris_register_type (struct gdbarch *gdbarch, int regno)
1679 if (regno == gdbarch_pc_regnum (gdbarch))
1680 return builtin_type_void_func_ptr;
1681 else if (regno == gdbarch_sp_regnum (gdbarch)
1682 || regno == CRIS_FP_REGNUM)
1683 return builtin_type_void_data_ptr;
1684 else if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1685 || (regno >= MOF_REGNUM && regno <= USP_REGNUM))
1686 /* Note: R8 taken care of previous clause. */
1687 return builtin_type_uint32;
1688 else if (regno >= P4_REGNUM && regno <= CCR_REGNUM)
1689 return builtin_type_uint16;
1690 else if (regno >= P0_REGNUM && regno <= VR_REGNUM)
1691 return builtin_type_uint8;
1693 /* Invalid (unimplemented) register. */
1694 return builtin_type_int0;
1697 static struct type *
1698 crisv32_register_type (struct gdbarch *gdbarch, int regno)
1700 if (regno == gdbarch_pc_regnum (gdbarch))
1701 return builtin_type_void_func_ptr;
1702 else if (regno == gdbarch_sp_regnum (gdbarch)
1703 || regno == CRIS_FP_REGNUM)
1704 return builtin_type_void_data_ptr;
1705 else if ((regno >= 0 && regno <= ACR_REGNUM)
1706 || (regno >= EXS_REGNUM && regno <= SPC_REGNUM)
1707 || (regno == PID_REGNUM)
1708 || (regno >= S0_REGNUM && regno <= S15_REGNUM))
1709 /* Note: R8 and SP taken care of by previous clause. */
1710 return builtin_type_uint32;
1711 else if (regno == WZ_REGNUM)
1712 return builtin_type_uint16;
1713 else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM)
1714 return builtin_type_uint8;
1717 /* Invalid (unimplemented) register. Should not happen as there are
1718 no unimplemented CRISv32 registers. */
1719 warning (_("crisv32_register_type: unknown regno %d"), regno);
1720 return builtin_type_int0;
1724 /* Stores a function return value of type type, where valbuf is the address
1725 of the value to be stored. */
1727 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1730 cris_store_return_value (struct type *type, struct regcache *regcache,
1734 int len = TYPE_LENGTH (type);
1738 /* Put the return value in R10. */
1739 val = extract_unsigned_integer (valbuf, len);
1740 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1744 /* Put the return value in R10 and R11. */
1745 val = extract_unsigned_integer (valbuf, 4);
1746 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1747 val = extract_unsigned_integer ((char *)valbuf + 4, len - 4);
1748 regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val);
1751 error (_("cris_store_return_value: type length too large."));
1754 /* Return the name of register regno as a string. Return NULL for an invalid or
1755 unimplemented register. */
1758 cris_special_register_name (int regno)
1763 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1764 Adjust regno accordingly. */
1765 spec_regno = regno - NUM_GENREGS;
1767 /* Assume nothing about the layout of the cris_spec_regs struct
1769 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1771 if (cris_spec_regs[i].number == spec_regno
1772 && cris_spec_reg_applicable (cris_spec_regs[i]))
1773 /* Go with the first applicable register. */
1774 return cris_spec_regs[i].name;
1776 /* Special register not applicable to this CRIS version. */
1781 cris_register_name (struct gdbarch *gdbarch, int regno)
1783 static char *cris_genreg_names[] =
1784 { "r0", "r1", "r2", "r3", \
1785 "r4", "r5", "r6", "r7", \
1786 "r8", "r9", "r10", "r11", \
1787 "r12", "r13", "sp", "pc" };
1789 if (regno >= 0 && regno < NUM_GENREGS)
1791 /* General register. */
1792 return cris_genreg_names[regno];
1794 else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (gdbarch))
1796 return cris_special_register_name (regno);
1800 /* Invalid register. */
1806 crisv32_register_name (struct gdbarch *gdbarch, int regno)
1808 static char *crisv32_genreg_names[] =
1809 { "r0", "r1", "r2", "r3", \
1810 "r4", "r5", "r6", "r7", \
1811 "r8", "r9", "r10", "r11", \
1812 "r12", "r13", "sp", "acr"
1815 static char *crisv32_sreg_names[] =
1816 { "s0", "s1", "s2", "s3", \
1817 "s4", "s5", "s6", "s7", \
1818 "s8", "s9", "s10", "s11", \
1819 "s12", "s13", "s14", "s15"
1822 if (regno >= 0 && regno < NUM_GENREGS)
1824 /* General register. */
1825 return crisv32_genreg_names[regno];
1827 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1829 return cris_special_register_name (regno);
1831 else if (regno == gdbarch_pc_regnum (gdbarch))
1835 else if (regno >= S0_REGNUM && regno <= S15_REGNUM)
1837 return crisv32_sreg_names[regno - S0_REGNUM];
1841 /* Invalid register. */
1846 /* Convert DWARF register number REG to the appropriate register
1847 number used by GDB. */
1850 cris_dwarf2_reg_to_regnum (int reg)
1852 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1853 numbering, MOF is 18).
1854 Adapted from gcc/config/cris/cris.h. */
1855 static int cris_dwarf_regmap[] = {
1867 if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap))
1868 regnum = cris_dwarf_regmap[reg];
1871 warning (_("Unmapped DWARF Register #%d encountered."), reg);
1876 /* DWARF-2 frame support. */
1879 cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1880 struct dwarf2_frame_state_reg *reg,
1881 struct frame_info *next_frame)
1883 /* The return address column. */
1884 if (regnum == gdbarch_pc_regnum (gdbarch))
1885 reg->how = DWARF2_FRAME_REG_RA;
1887 /* The call frame address. */
1888 else if (regnum == gdbarch_sp_regnum (gdbarch))
1889 reg->how = DWARF2_FRAME_REG_CFA;
1892 /* Extract from an array regbuf containing the raw register state a function
1893 return value of type type, and copy that, in virtual format, into
1896 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1899 cris_extract_return_value (struct type *type, struct regcache *regcache,
1903 int len = TYPE_LENGTH (type);
1907 /* Get the return value from R10. */
1908 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1909 store_unsigned_integer (valbuf, len, val);
1913 /* Get the return value from R10 and R11. */
1914 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1915 store_unsigned_integer (valbuf, 4, val);
1916 regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val);
1917 store_unsigned_integer ((char *)valbuf + 4, len - 4, val);
1920 error (_("cris_extract_return_value: type length too large"));
1923 /* Handle the CRIS return value convention. */
1925 static enum return_value_convention
1926 cris_return_value (struct gdbarch *gdbarch, struct type *type,
1927 struct regcache *regcache, gdb_byte *readbuf,
1928 const gdb_byte *writebuf)
1930 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1931 || TYPE_CODE (type) == TYPE_CODE_UNION
1932 || TYPE_LENGTH (type) > 8)
1933 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1934 goes on the stack. */
1935 return RETURN_VALUE_STRUCT_CONVENTION;
1938 cris_extract_return_value (type, regcache, readbuf);
1940 cris_store_return_value (type, regcache, writebuf);
1942 return RETURN_VALUE_REGISTER_CONVENTION;
1945 /* Calculates a value that measures how good inst_args constraints an
1946 instruction. It stems from cris_constraint, found in cris-dis.c. */
1949 constraint (unsigned int insn, const signed char *inst_args,
1950 inst_env_type *inst_env)
1955 const char *s = inst_args;
1961 if ((insn & 0x30) == 0x30)
1966 /* A prefix operand. */
1967 if (inst_env->prefix_found)
1973 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1974 valid "push" size. In case of special register, it may be != 4. */
1975 if (inst_env->prefix_found)
1981 retval = (((insn >> 0xC) & 0xF) == (insn & 0xF));
1989 tmp = (insn >> 0xC) & 0xF;
1991 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1993 /* Since we match four bits, we will give a value of
1994 4 - 1 = 3 in a match. If there is a corresponding
1995 exact match of a special register in another pattern, it
1996 will get a value of 4, which will be higher. This should
1997 be correct in that an exact pattern would match better that
1999 Note that there is a reason for not returning zero; the
2000 pattern for "clear" is partly matched in the bit-pattern
2001 (the two lower bits must be zero), while the bit-pattern
2002 for a move from a special register is matched in the
2003 register constraint.
2004 This also means we will will have a race condition if
2005 there is a partly match in three bits in the bit pattern. */
2006 if (tmp == cris_spec_regs[i].number)
2013 if (cris_spec_regs[i].name == NULL)
2020 /* Returns the number of bits set in the variable value. */
2023 number_of_bits (unsigned int value)
2025 int number_of_bits = 0;
2029 number_of_bits += 1;
2030 value &= (value - 1);
2032 return number_of_bits;
2035 /* Finds the address that should contain the single step breakpoint(s).
2036 It stems from code in cris-dis.c. */
2039 find_cris_op (unsigned short insn, inst_env_type *inst_env)
2042 int max_level_of_match = -1;
2043 int max_matched = -1;
2046 for (i = 0; cris_opcodes[i].name != NULL; i++)
2048 if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match)
2049 && ((cris_opcodes[i].lose & insn) == 0)
2050 /* Only CRISv10 instructions, please. */
2051 && (cris_opcodes[i].applicable_version != cris_ver_v32p))
2053 level_of_match = constraint (insn, cris_opcodes[i].args, inst_env);
2054 if (level_of_match >= 0)
2057 number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose);
2058 if (level_of_match > max_level_of_match)
2061 max_level_of_match = level_of_match;
2062 if (level_of_match == 16)
2064 /* All bits matched, cannot find better. */
2074 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
2075 actually an internal error. */
2078 find_step_target (struct frame_info *frame, inst_env_type *inst_env)
2082 unsigned short insn;
2083 struct gdbarch *gdbarch = get_frame_arch (frame);
2085 /* Create a local register image and set the initial state. */
2086 for (i = 0; i < NUM_GENREGS; i++)
2089 (unsigned long) get_frame_register_unsigned (frame, i);
2091 offset = NUM_GENREGS;
2092 for (i = 0; i < NUM_SPECREGS; i++)
2095 (unsigned long) get_frame_register_unsigned (frame, offset + i);
2097 inst_env->branch_found = 0;
2098 inst_env->slot_needed = 0;
2099 inst_env->delay_slot_pc_active = 0;
2100 inst_env->prefix_found = 0;
2101 inst_env->invalid = 0;
2102 inst_env->xflag_found = 0;
2103 inst_env->disable_interrupt = 0;
2105 /* Look for a step target. */
2108 /* Read an instruction from the client. */
2109 insn = read_memory_unsigned_integer
2110 (inst_env->reg[gdbarch_pc_regnum (gdbarch)], 2);
2112 /* If the instruction is not in a delay slot the new content of the
2113 PC is [PC] + 2. If the instruction is in a delay slot it is not
2114 that simple. Since a instruction in a delay slot cannot change
2115 the content of the PC, it does not matter what value PC will have.
2116 Just make sure it is a valid instruction. */
2117 if (!inst_env->delay_slot_pc_active)
2119 inst_env->reg[gdbarch_pc_regnum (gdbarch)] += 2;
2123 inst_env->delay_slot_pc_active = 0;
2124 inst_env->reg[gdbarch_pc_regnum (gdbarch)]
2125 = inst_env->delay_slot_pc;
2127 /* Analyse the present instruction. */
2128 i = find_cris_op (insn, inst_env);
2131 inst_env->invalid = 1;
2135 cris_gdb_func (cris_opcodes[i].op, insn, inst_env);
2137 } while (!inst_env->invalid
2138 && (inst_env->prefix_found || inst_env->xflag_found
2139 || inst_env->slot_needed));
2143 /* There is no hardware single-step support. The function find_step_target
2144 digs through the opcodes in order to find all possible targets.
2145 Either one ordinary target or two targets for branches may be found. */
2148 cris_software_single_step (struct frame_info *frame)
2150 inst_env_type inst_env;
2152 /* Analyse the present instruction environment and insert
2154 int status = find_step_target (frame, &inst_env);
2157 /* Could not find a target. Things are likely to go downhill
2159 warning (_("CRIS software single step could not find a step target."));
2163 /* Insert at most two breakpoints. One for the next PC content
2164 and possibly another one for a branch, jump, etc. */
2166 (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (get_frame_arch (frame))];
2167 insert_single_step_breakpoint (next_pc);
2168 if (inst_env.branch_found
2169 && (CORE_ADDR) inst_env.branch_break_address != next_pc)
2171 CORE_ADDR branch_target_address
2172 = (CORE_ADDR) inst_env.branch_break_address;
2173 insert_single_step_breakpoint (branch_target_address);
2180 /* Calculates the prefix value for quick offset addressing mode. */
2183 quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2185 /* It's invalid to be in a delay slot. You can't have a prefix to this
2186 instruction (not 100% sure). */
2187 if (inst_env->slot_needed || inst_env->prefix_found)
2189 inst_env->invalid = 1;
2193 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2194 inst_env->prefix_value += cris_get_bdap_quick_offset (inst);
2196 /* A prefix doesn't change the xflag_found. But the rest of the flags
2198 inst_env->slot_needed = 0;
2199 inst_env->prefix_found = 1;
2202 /* Updates the autoincrement register. The size of the increment is derived
2203 from the size of the operation. The PC is always kept aligned on even
2207 process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env)
2209 if (size == INST_BYTE_SIZE)
2211 inst_env->reg[cris_get_operand1 (inst)] += 1;
2213 /* The PC must be word aligned, so increase the PC with one
2214 word even if the size is byte. */
2215 if (cris_get_operand1 (inst) == REG_PC)
2217 inst_env->reg[REG_PC] += 1;
2220 else if (size == INST_WORD_SIZE)
2222 inst_env->reg[cris_get_operand1 (inst)] += 2;
2224 else if (size == INST_DWORD_SIZE)
2226 inst_env->reg[cris_get_operand1 (inst)] += 4;
2231 inst_env->invalid = 1;
2235 /* Just a forward declaration. */
2237 static unsigned long get_data_from_address (unsigned short *inst,
2240 /* Calculates the prefix value for the general case of offset addressing
2244 bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2249 /* It's invalid to be in a delay slot. */
2250 if (inst_env->slot_needed || inst_env->prefix_found)
2252 inst_env->invalid = 1;
2256 /* The calculation of prefix_value used to be after process_autoincrement,
2257 but that fails for an instruction such as jsr [$r0+12] which is encoded
2258 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
2259 mustn't be incremented until we have read it and what it points at. */
2260 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2262 /* The offset is an indirection of the contents of the operand1 register. */
2263 inst_env->prefix_value +=
2264 get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)]);
2266 if (cris_get_mode (inst) == AUTOINC_MODE)
2268 process_autoincrement (cris_get_size (inst), inst, inst_env);
2271 /* A prefix doesn't change the xflag_found. But the rest of the flags
2273 inst_env->slot_needed = 0;
2274 inst_env->prefix_found = 1;
2277 /* Calculates the prefix value for the index addressing mode. */
2280 biap_prefix (unsigned short inst, inst_env_type *inst_env)
2282 /* It's invalid to be in a delay slot. I can't see that it's possible to
2283 have a prefix to this instruction. So I will treat this as invalid. */
2284 if (inst_env->slot_needed || inst_env->prefix_found)
2286 inst_env->invalid = 1;
2290 inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)];
2292 /* The offset is the operand2 value shifted the size of the instruction
2294 inst_env->prefix_value +=
2295 inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst);
2297 /* If the PC is operand1 (base) the address used is the address after
2298 the main instruction, i.e. address + 2 (the PC is already compensated
2299 for the prefix operation). */
2300 if (cris_get_operand1 (inst) == REG_PC)
2302 inst_env->prefix_value += 2;
2305 /* A prefix doesn't change the xflag_found. But the rest of the flags
2307 inst_env->slot_needed = 0;
2308 inst_env->xflag_found = 0;
2309 inst_env->prefix_found = 1;
2312 /* Calculates the prefix value for the double indirect addressing mode. */
2315 dip_prefix (unsigned short inst, inst_env_type *inst_env)
2320 /* It's invalid to be in a delay slot. */
2321 if (inst_env->slot_needed || inst_env->prefix_found)
2323 inst_env->invalid = 1;
2327 /* The prefix value is one dereference of the contents of the operand1
2329 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2330 inst_env->prefix_value = read_memory_unsigned_integer (address, 4);
2332 /* Check if the mode is autoincrement. */
2333 if (cris_get_mode (inst) == AUTOINC_MODE)
2335 inst_env->reg[cris_get_operand1 (inst)] += 4;
2338 /* A prefix doesn't change the xflag_found. But the rest of the flags
2340 inst_env->slot_needed = 0;
2341 inst_env->xflag_found = 0;
2342 inst_env->prefix_found = 1;
2345 /* Finds the destination for a branch with 8-bits offset. */
2348 eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2353 /* If we have a prefix or are in a delay slot it's bad. */
2354 if (inst_env->slot_needed || inst_env->prefix_found)
2356 inst_env->invalid = 1;
2360 /* We have a branch, find out where the branch will land. */
2361 offset = cris_get_branch_short_offset (inst);
2363 /* Check if the offset is signed. */
2364 if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK)
2369 /* The offset ends with the sign bit, set it to zero. The address
2370 should always be word aligned. */
2371 offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK;
2373 inst_env->branch_found = 1;
2374 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2376 inst_env->slot_needed = 1;
2377 inst_env->prefix_found = 0;
2378 inst_env->xflag_found = 0;
2379 inst_env->disable_interrupt = 1;
2382 /* Finds the destination for a branch with 16-bits offset. */
2385 sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2389 /* If we have a prefix or is in a delay slot it's bad. */
2390 if (inst_env->slot_needed || inst_env->prefix_found)
2392 inst_env->invalid = 1;
2396 /* We have a branch, find out the offset for the branch. */
2397 offset = read_memory_integer (inst_env->reg[REG_PC], 2);
2399 /* The instruction is one word longer than normal, so add one word
2401 inst_env->reg[REG_PC] += 2;
2403 inst_env->branch_found = 1;
2404 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2407 inst_env->slot_needed = 1;
2408 inst_env->prefix_found = 0;
2409 inst_env->xflag_found = 0;
2410 inst_env->disable_interrupt = 1;
2413 /* Handles the ABS instruction. */
2416 abs_op (unsigned short inst, inst_env_type *inst_env)
2421 /* ABS can't have a prefix, so it's bad if it does. */
2422 if (inst_env->prefix_found)
2424 inst_env->invalid = 1;
2428 /* Check if the operation affects the PC. */
2429 if (cris_get_operand2 (inst) == REG_PC)
2432 /* It's invalid to change to the PC if we are in a delay slot. */
2433 if (inst_env->slot_needed)
2435 inst_env->invalid = 1;
2439 value = (long) inst_env->reg[REG_PC];
2441 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
2442 if (value != SIGNED_DWORD_MASK)
2445 inst_env->reg[REG_PC] = (long) value;
2449 inst_env->slot_needed = 0;
2450 inst_env->prefix_found = 0;
2451 inst_env->xflag_found = 0;
2452 inst_env->disable_interrupt = 0;
2455 /* Handles the ADDI instruction. */
2458 addi_op (unsigned short inst, inst_env_type *inst_env)
2460 /* It's invalid to have the PC as base register. And ADDI can't have
2462 if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC))
2464 inst_env->invalid = 1;
2468 inst_env->slot_needed = 0;
2469 inst_env->prefix_found = 0;
2470 inst_env->xflag_found = 0;
2471 inst_env->disable_interrupt = 0;
2474 /* Handles the ASR instruction. */
2477 asr_op (unsigned short inst, inst_env_type *inst_env)
2480 unsigned long value;
2481 unsigned long signed_extend_mask = 0;
2483 /* ASR can't have a prefix, so check that it doesn't. */
2484 if (inst_env->prefix_found)
2486 inst_env->invalid = 1;
2490 /* Check if the PC is the target register. */
2491 if (cris_get_operand2 (inst) == REG_PC)
2493 /* It's invalid to change the PC in a delay slot. */
2494 if (inst_env->slot_needed)
2496 inst_env->invalid = 1;
2499 /* Get the number of bits to shift. */
2500 shift_steps = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]);
2501 value = inst_env->reg[REG_PC];
2503 /* Find out how many bits the operation should apply to. */
2504 if (cris_get_size (inst) == INST_BYTE_SIZE)
2506 if (value & SIGNED_BYTE_MASK)
2508 signed_extend_mask = 0xFF;
2509 signed_extend_mask = signed_extend_mask >> shift_steps;
2510 signed_extend_mask = ~signed_extend_mask;
2512 value = value >> shift_steps;
2513 value |= signed_extend_mask;
2515 inst_env->reg[REG_PC] &= 0xFFFFFF00;
2516 inst_env->reg[REG_PC] |= value;
2518 else if (cris_get_size (inst) == INST_WORD_SIZE)
2520 if (value & SIGNED_WORD_MASK)
2522 signed_extend_mask = 0xFFFF;
2523 signed_extend_mask = signed_extend_mask >> shift_steps;
2524 signed_extend_mask = ~signed_extend_mask;
2526 value = value >> shift_steps;
2527 value |= signed_extend_mask;
2529 inst_env->reg[REG_PC] &= 0xFFFF0000;
2530 inst_env->reg[REG_PC] |= value;
2532 else if (cris_get_size (inst) == INST_DWORD_SIZE)
2534 if (value & SIGNED_DWORD_MASK)
2536 signed_extend_mask = 0xFFFFFFFF;
2537 signed_extend_mask = signed_extend_mask >> shift_steps;
2538 signed_extend_mask = ~signed_extend_mask;
2540 value = value >> shift_steps;
2541 value |= signed_extend_mask;
2542 inst_env->reg[REG_PC] = value;
2545 inst_env->slot_needed = 0;
2546 inst_env->prefix_found = 0;
2547 inst_env->xflag_found = 0;
2548 inst_env->disable_interrupt = 0;
2551 /* Handles the ASRQ instruction. */
2554 asrq_op (unsigned short inst, inst_env_type *inst_env)
2558 unsigned long value;
2559 unsigned long signed_extend_mask = 0;
2561 /* ASRQ can't have a prefix, so check that it doesn't. */
2562 if (inst_env->prefix_found)
2564 inst_env->invalid = 1;
2568 /* Check if the PC is the target register. */
2569 if (cris_get_operand2 (inst) == REG_PC)
2572 /* It's invalid to change the PC in a delay slot. */
2573 if (inst_env->slot_needed)
2575 inst_env->invalid = 1;
2578 /* The shift size is given as a 5 bit quick value, i.e. we don't
2579 want the the sign bit of the quick value. */
2580 shift_steps = cris_get_asr_shift_steps (inst);
2581 value = inst_env->reg[REG_PC];
2582 if (value & SIGNED_DWORD_MASK)
2584 signed_extend_mask = 0xFFFFFFFF;
2585 signed_extend_mask = signed_extend_mask >> shift_steps;
2586 signed_extend_mask = ~signed_extend_mask;
2588 value = value >> shift_steps;
2589 value |= signed_extend_mask;
2590 inst_env->reg[REG_PC] = value;
2592 inst_env->slot_needed = 0;
2593 inst_env->prefix_found = 0;
2594 inst_env->xflag_found = 0;
2595 inst_env->disable_interrupt = 0;
2598 /* Handles the AX, EI and SETF instruction. */
2601 ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env)
2603 if (inst_env->prefix_found)
2605 inst_env->invalid = 1;
2608 /* Check if the instruction is setting the X flag. */
2609 if (cris_is_xflag_bit_on (inst))
2611 inst_env->xflag_found = 1;
2615 inst_env->xflag_found = 0;
2617 inst_env->slot_needed = 0;
2618 inst_env->prefix_found = 0;
2619 inst_env->disable_interrupt = 1;
2622 /* Checks if the instruction is in assign mode. If so, it updates the assign
2623 register. Note that check_assign assumes that the caller has checked that
2624 there is a prefix to this instruction. The mode check depends on this. */
2627 check_assign (unsigned short inst, inst_env_type *inst_env)
2629 /* Check if it's an assign addressing mode. */
2630 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2632 /* Assign the prefix value to operand 1. */
2633 inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value;
2637 /* Handles the 2-operand BOUND instruction. */
2640 two_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2642 /* It's invalid to have the PC as the index operand. */
2643 if (cris_get_operand2 (inst) == REG_PC)
2645 inst_env->invalid = 1;
2648 /* Check if we have a prefix. */
2649 if (inst_env->prefix_found)
2651 check_assign (inst, inst_env);
2653 /* Check if this is an autoincrement mode. */
2654 else if (cris_get_mode (inst) == AUTOINC_MODE)
2656 /* It's invalid to change the PC in a delay slot. */
2657 if (inst_env->slot_needed)
2659 inst_env->invalid = 1;
2662 process_autoincrement (cris_get_size (inst), inst, inst_env);
2664 inst_env->slot_needed = 0;
2665 inst_env->prefix_found = 0;
2666 inst_env->xflag_found = 0;
2667 inst_env->disable_interrupt = 0;
2670 /* Handles the 3-operand BOUND instruction. */
2673 three_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2675 /* It's an error if we haven't got a prefix. And it's also an error
2676 if the PC is the destination register. */
2677 if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC))
2679 inst_env->invalid = 1;
2682 inst_env->slot_needed = 0;
2683 inst_env->prefix_found = 0;
2684 inst_env->xflag_found = 0;
2685 inst_env->disable_interrupt = 0;
2688 /* Clears the status flags in inst_env. */
2691 btst_nop_op (unsigned short inst, inst_env_type *inst_env)
2693 /* It's an error if we have got a prefix. */
2694 if (inst_env->prefix_found)
2696 inst_env->invalid = 1;
2700 inst_env->slot_needed = 0;
2701 inst_env->prefix_found = 0;
2702 inst_env->xflag_found = 0;
2703 inst_env->disable_interrupt = 0;
2706 /* Clears the status flags in inst_env. */
2709 clearf_di_op (unsigned short inst, inst_env_type *inst_env)
2711 /* It's an error if we have got a prefix. */
2712 if (inst_env->prefix_found)
2714 inst_env->invalid = 1;
2718 inst_env->slot_needed = 0;
2719 inst_env->prefix_found = 0;
2720 inst_env->xflag_found = 0;
2721 inst_env->disable_interrupt = 1;
2724 /* Handles the CLEAR instruction if it's in register mode. */
2727 reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env)
2729 /* Check if the target is the PC. */
2730 if (cris_get_operand2 (inst) == REG_PC)
2732 /* The instruction will clear the instruction's size bits. */
2733 int clear_size = cris_get_clear_size (inst);
2734 if (clear_size == INST_BYTE_SIZE)
2736 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00;
2738 if (clear_size == INST_WORD_SIZE)
2740 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000;
2742 if (clear_size == INST_DWORD_SIZE)
2744 inst_env->delay_slot_pc = 0x0;
2746 /* The jump will be delayed with one delay slot. So we need a delay
2748 inst_env->slot_needed = 1;
2749 inst_env->delay_slot_pc_active = 1;
2753 /* The PC will not change => no delay slot. */
2754 inst_env->slot_needed = 0;
2756 inst_env->prefix_found = 0;
2757 inst_env->xflag_found = 0;
2758 inst_env->disable_interrupt = 0;
2761 /* Handles the TEST instruction if it's in register mode. */
2764 reg_mode_test_op (unsigned short inst, inst_env_type *inst_env)
2766 /* It's an error if we have got a prefix. */
2767 if (inst_env->prefix_found)
2769 inst_env->invalid = 1;
2772 inst_env->slot_needed = 0;
2773 inst_env->prefix_found = 0;
2774 inst_env->xflag_found = 0;
2775 inst_env->disable_interrupt = 0;
2779 /* Handles the CLEAR and TEST instruction if the instruction isn't
2780 in register mode. */
2783 none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env)
2785 /* Check if we are in a prefix mode. */
2786 if (inst_env->prefix_found)
2788 /* The only way the PC can change is if this instruction is in
2789 assign addressing mode. */
2790 check_assign (inst, inst_env);
2792 /* Indirect mode can't change the PC so just check if the mode is
2794 else if (cris_get_mode (inst) == AUTOINC_MODE)
2796 process_autoincrement (cris_get_size (inst), inst, inst_env);
2798 inst_env->slot_needed = 0;
2799 inst_env->prefix_found = 0;
2800 inst_env->xflag_found = 0;
2801 inst_env->disable_interrupt = 0;
2804 /* Checks that the PC isn't the destination register or the instructions has
2808 dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env)
2810 /* It's invalid to have the PC as the destination. The instruction can't
2812 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2814 inst_env->invalid = 1;
2818 inst_env->slot_needed = 0;
2819 inst_env->prefix_found = 0;
2820 inst_env->xflag_found = 0;
2821 inst_env->disable_interrupt = 0;
2824 /* Checks that the instruction doesn't have a prefix. */
2827 break_op (unsigned short inst, inst_env_type *inst_env)
2829 /* The instruction can't have a prefix. */
2830 if (inst_env->prefix_found)
2832 inst_env->invalid = 1;
2836 inst_env->slot_needed = 0;
2837 inst_env->prefix_found = 0;
2838 inst_env->xflag_found = 0;
2839 inst_env->disable_interrupt = 1;
2842 /* Checks that the PC isn't the destination register and that the instruction
2843 doesn't have a prefix. */
2846 scc_op (unsigned short inst, inst_env_type *inst_env)
2848 /* It's invalid to have the PC as the destination. The instruction can't
2850 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2852 inst_env->invalid = 1;
2856 inst_env->slot_needed = 0;
2857 inst_env->prefix_found = 0;
2858 inst_env->xflag_found = 0;
2859 inst_env->disable_interrupt = 1;
2862 /* Handles the register mode JUMP instruction. */
2865 reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2867 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2868 you can't have a prefix. */
2869 if ((inst_env->slot_needed) || (inst_env->prefix_found))
2871 inst_env->invalid = 1;
2875 /* Just change the PC. */
2876 inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)];
2877 inst_env->slot_needed = 0;
2878 inst_env->prefix_found = 0;
2879 inst_env->xflag_found = 0;
2880 inst_env->disable_interrupt = 1;
2883 /* Handles the JUMP instruction for all modes except register. */
2886 none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2888 unsigned long newpc;
2891 /* It's invalid to do a JUMP in a delay slot. */
2892 if (inst_env->slot_needed)
2894 inst_env->invalid = 1;
2898 /* Check if we have a prefix. */
2899 if (inst_env->prefix_found)
2901 check_assign (inst, inst_env);
2903 /* Get the new value for the the PC. */
2905 read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value,
2910 /* Get the new value for the PC. */
2911 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2912 newpc = read_memory_unsigned_integer (address, 4);
2914 /* Check if we should increment a register. */
2915 if (cris_get_mode (inst) == AUTOINC_MODE)
2917 inst_env->reg[cris_get_operand1 (inst)] += 4;
2920 inst_env->reg[REG_PC] = newpc;
2922 inst_env->slot_needed = 0;
2923 inst_env->prefix_found = 0;
2924 inst_env->xflag_found = 0;
2925 inst_env->disable_interrupt = 1;
2928 /* Handles moves to special registers (aka P-register) for all modes. */
2931 move_to_preg_op (unsigned short inst, inst_env_type *inst_env)
2933 if (inst_env->prefix_found)
2935 /* The instruction has a prefix that means we are only interested if
2936 the instruction is in assign mode. */
2937 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2939 /* The prefix handles the problem if we are in a delay slot. */
2940 if (cris_get_operand1 (inst) == REG_PC)
2942 /* Just take care of the assign. */
2943 check_assign (inst, inst_env);
2947 else if (cris_get_mode (inst) == AUTOINC_MODE)
2949 /* The instruction doesn't have a prefix, the only case left that we
2950 are interested in is the autoincrement mode. */
2951 if (cris_get_operand1 (inst) == REG_PC)
2953 /* If the PC is to be incremented it's invalid to be in a
2955 if (inst_env->slot_needed)
2957 inst_env->invalid = 1;
2961 /* The increment depends on the size of the special register. */
2962 if (cris_register_size (cris_get_operand2 (inst)) == 1)
2964 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2966 else if (cris_register_size (cris_get_operand2 (inst)) == 2)
2968 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2972 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2976 inst_env->slot_needed = 0;
2977 inst_env->prefix_found = 0;
2978 inst_env->xflag_found = 0;
2979 inst_env->disable_interrupt = 1;
2982 /* Handles moves from special registers (aka P-register) for all modes
2986 none_reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env)
2988 if (inst_env->prefix_found)
2990 /* The instruction has a prefix that means we are only interested if
2991 the instruction is in assign mode. */
2992 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2994 /* The prefix handles the problem if we are in a delay slot. */
2995 if (cris_get_operand1 (inst) == REG_PC)
2997 /* Just take care of the assign. */
2998 check_assign (inst, inst_env);
3002 /* The instruction doesn't have a prefix, the only case left that we
3003 are interested in is the autoincrement mode. */
3004 else if (cris_get_mode (inst) == AUTOINC_MODE)
3006 if (cris_get_operand1 (inst) == REG_PC)
3008 /* If the PC is to be incremented it's invalid to be in a
3010 if (inst_env->slot_needed)
3012 inst_env->invalid = 1;
3016 /* The increment depends on the size of the special register. */
3017 if (cris_register_size (cris_get_operand2 (inst)) == 1)
3019 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
3021 else if (cris_register_size (cris_get_operand2 (inst)) == 2)
3023 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
3027 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
3031 inst_env->slot_needed = 0;
3032 inst_env->prefix_found = 0;
3033 inst_env->xflag_found = 0;
3034 inst_env->disable_interrupt = 1;
3037 /* Handles moves from special registers (aka P-register) when the mode
3041 reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env)
3043 /* Register mode move from special register can't have a prefix. */
3044 if (inst_env->prefix_found)
3046 inst_env->invalid = 1;
3050 if (cris_get_operand1 (inst) == REG_PC)
3052 /* It's invalid to change the PC in a delay slot. */
3053 if (inst_env->slot_needed)
3055 inst_env->invalid = 1;
3058 /* The destination is the PC, the jump will have a delay slot. */
3059 inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)];
3060 inst_env->slot_needed = 1;
3061 inst_env->delay_slot_pc_active = 1;
3065 /* If the destination isn't PC, there will be no jump. */
3066 inst_env->slot_needed = 0;
3068 inst_env->prefix_found = 0;
3069 inst_env->xflag_found = 0;
3070 inst_env->disable_interrupt = 1;
3073 /* Handles the MOVEM from memory to general register instruction. */
3076 move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env)
3078 if (inst_env->prefix_found)
3080 /* The prefix handles the problem if we are in a delay slot. Is the
3081 MOVEM instruction going to change the PC? */
3082 if (cris_get_operand2 (inst) >= REG_PC)
3084 inst_env->reg[REG_PC] =
3085 read_memory_unsigned_integer (inst_env->prefix_value, 4);
3087 /* The assign value is the value after the increment. Normally, the
3088 assign value is the value before the increment. */
3089 if ((cris_get_operand1 (inst) == REG_PC)
3090 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3092 inst_env->reg[REG_PC] = inst_env->prefix_value;
3093 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3098 /* Is the MOVEM instruction going to change the PC? */
3099 if (cris_get_operand2 (inst) == REG_PC)
3101 /* It's invalid to change the PC in a delay slot. */
3102 if (inst_env->slot_needed)
3104 inst_env->invalid = 1;
3107 inst_env->reg[REG_PC] =
3108 read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)],
3111 /* The increment is not depending on the size, instead it's depending
3112 on the number of registers loaded from memory. */
3113 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3115 /* It's invalid to change the PC in a delay slot. */
3116 if (inst_env->slot_needed)
3118 inst_env->invalid = 1;
3121 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3124 inst_env->slot_needed = 0;
3125 inst_env->prefix_found = 0;
3126 inst_env->xflag_found = 0;
3127 inst_env->disable_interrupt = 0;
3130 /* Handles the MOVEM to memory from general register instruction. */
3133 move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env)
3135 if (inst_env->prefix_found)
3137 /* The assign value is the value after the increment. Normally, the
3138 assign value is the value before the increment. */
3139 if ((cris_get_operand1 (inst) == REG_PC) &&
3140 (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3142 /* The prefix handles the problem if we are in a delay slot. */
3143 inst_env->reg[REG_PC] = inst_env->prefix_value;
3144 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3149 /* The increment is not depending on the size, instead it's depending
3150 on the number of registers loaded to memory. */
3151 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3153 /* It's invalid to change the PC in a delay slot. */
3154 if (inst_env->slot_needed)
3156 inst_env->invalid = 1;
3159 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3162 inst_env->slot_needed = 0;
3163 inst_env->prefix_found = 0;
3164 inst_env->xflag_found = 0;
3165 inst_env->disable_interrupt = 0;
3168 /* Handles the intructions that's not yet implemented, by setting
3169 inst_env->invalid to true. */
3172 not_implemented_op (unsigned short inst, inst_env_type *inst_env)
3174 inst_env->invalid = 1;
3177 /* Handles the XOR instruction. */
3180 xor_op (unsigned short inst, inst_env_type *inst_env)
3182 /* XOR can't have a prefix. */
3183 if (inst_env->prefix_found)
3185 inst_env->invalid = 1;
3189 /* Check if the PC is the target. */
3190 if (cris_get_operand2 (inst) == REG_PC)
3192 /* It's invalid to change the PC in a delay slot. */
3193 if (inst_env->slot_needed)
3195 inst_env->invalid = 1;
3198 inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)];
3200 inst_env->slot_needed = 0;
3201 inst_env->prefix_found = 0;
3202 inst_env->xflag_found = 0;
3203 inst_env->disable_interrupt = 0;
3206 /* Handles the MULS instruction. */
3209 muls_op (unsigned short inst, inst_env_type *inst_env)
3211 /* MULS/U can't have a prefix. */
3212 if (inst_env->prefix_found)
3214 inst_env->invalid = 1;
3218 /* Consider it invalid if the PC is the target. */
3219 if (cris_get_operand2 (inst) == REG_PC)
3221 inst_env->invalid = 1;
3224 inst_env->slot_needed = 0;
3225 inst_env->prefix_found = 0;
3226 inst_env->xflag_found = 0;
3227 inst_env->disable_interrupt = 0;
3230 /* Handles the MULU instruction. */
3233 mulu_op (unsigned short inst, inst_env_type *inst_env)
3235 /* MULS/U can't have a prefix. */
3236 if (inst_env->prefix_found)
3238 inst_env->invalid = 1;
3242 /* Consider it invalid if the PC is the target. */
3243 if (cris_get_operand2 (inst) == REG_PC)
3245 inst_env->invalid = 1;
3248 inst_env->slot_needed = 0;
3249 inst_env->prefix_found = 0;
3250 inst_env->xflag_found = 0;
3251 inst_env->disable_interrupt = 0;
3254 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
3255 The MOVE instruction is the move from source to register. */
3258 add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env,
3259 unsigned long source1, unsigned long source2)
3261 unsigned long pc_mask;
3262 unsigned long operation_mask;
3264 /* Find out how many bits the operation should apply to. */
3265 if (cris_get_size (inst) == INST_BYTE_SIZE)
3267 pc_mask = 0xFFFFFF00;
3268 operation_mask = 0xFF;
3270 else if (cris_get_size (inst) == INST_WORD_SIZE)
3272 pc_mask = 0xFFFF0000;
3273 operation_mask = 0xFFFF;
3275 else if (cris_get_size (inst) == INST_DWORD_SIZE)
3278 operation_mask = 0xFFFFFFFF;
3282 /* The size is out of range. */
3283 inst_env->invalid = 1;
3287 /* The instruction just works on uw_operation_mask bits. */
3288 source2 &= operation_mask;
3289 source1 &= operation_mask;
3291 /* Now calculate the result. The opcode's 3 first bits separates
3292 the different actions. */
3293 switch (cris_get_opcode (inst) & 7)
3303 case 2: /* subtract */
3307 case 3: /* compare */
3319 inst_env->invalid = 1;
3325 /* Make sure that the result doesn't contain more than the instruction
3327 source2 &= operation_mask;
3329 /* Calculate the new breakpoint address. */
3330 inst_env->reg[REG_PC] &= pc_mask;
3331 inst_env->reg[REG_PC] |= source1;
3335 /* Extends the value from either byte or word size to a dword. If the mode
3336 is zero extend then the value is extended with zero. If instead the mode
3337 is signed extend the sign bit of the value is taken into consideration. */
3339 static unsigned long
3340 do_sign_or_zero_extend (unsigned long value, unsigned short *inst)
3342 /* The size can be either byte or word, check which one it is.
3343 Don't check the highest bit, it's indicating if it's a zero
3345 if (cris_get_size (*inst) & INST_WORD_SIZE)
3350 /* Check if the instruction is signed extend. If so, check if value has
3352 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK))
3354 value |= SIGNED_WORD_EXTEND_MASK;
3362 /* Check if the instruction is signed extend. If so, check if value has
3364 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK))
3366 value |= SIGNED_BYTE_EXTEND_MASK;
3369 /* The size should now be dword. */
3370 cris_set_size_to_dword (inst);
3374 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3375 instruction. The MOVE instruction is the move from source to register. */
3378 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3379 inst_env_type *inst_env)
3381 unsigned long operand1;
3382 unsigned long operand2;
3384 /* It's invalid to have a prefix to the instruction. This is a register
3385 mode instruction and can't have a prefix. */
3386 if (inst_env->prefix_found)
3388 inst_env->invalid = 1;
3391 /* Check if the instruction has PC as its target. */
3392 if (cris_get_operand2 (inst) == REG_PC)
3394 if (inst_env->slot_needed)
3396 inst_env->invalid = 1;
3399 /* The instruction has the PC as its target register. */
3400 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3401 operand2 = inst_env->reg[REG_PC];
3403 /* Check if it's a extend, signed or zero instruction. */
3404 if (cris_get_opcode (inst) < 4)
3406 operand1 = do_sign_or_zero_extend (operand1, &inst);
3408 /* Calculate the PC value after the instruction, i.e. where the
3409 breakpoint should be. The order of the udw_operands is vital. */
3410 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3412 inst_env->slot_needed = 0;
3413 inst_env->prefix_found = 0;
3414 inst_env->xflag_found = 0;
3415 inst_env->disable_interrupt = 0;
3418 /* Returns the data contained at address. The size of the data is derived from
3419 the size of the operation. If the instruction is a zero or signed
3420 extend instruction, the size field is changed in instruction. */
3422 static unsigned long
3423 get_data_from_address (unsigned short *inst, CORE_ADDR address)
3425 int size = cris_get_size (*inst);
3426 unsigned long value;
3428 /* If it's an extend instruction we don't want the signed extend bit,
3429 because it influences the size. */
3430 if (cris_get_opcode (*inst) < 4)
3432 size &= ~SIGNED_EXTEND_BIT_MASK;
3434 /* Is there a need for checking the size? Size should contain the number of
3437 value = read_memory_unsigned_integer (address, size);
3439 /* Check if it's an extend, signed or zero instruction. */
3440 if (cris_get_opcode (*inst) < 4)
3442 value = do_sign_or_zero_extend (value, inst);
3447 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3448 instructions. The MOVE instruction is the move from source to register. */
3451 handle_prefix_assign_mode_for_aritm_op (unsigned short inst,
3452 inst_env_type *inst_env)
3454 unsigned long operand2;
3455 unsigned long operand3;
3457 check_assign (inst, inst_env);
3458 if (cris_get_operand2 (inst) == REG_PC)
3460 operand2 = inst_env->reg[REG_PC];
3462 /* Get the value of the third operand. */
3463 operand3 = get_data_from_address (&inst, inst_env->prefix_value);
3465 /* Calculate the PC value after the instruction, i.e. where the
3466 breakpoint should be. The order of the udw_operands is vital. */
3467 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3469 inst_env->slot_needed = 0;
3470 inst_env->prefix_found = 0;
3471 inst_env->xflag_found = 0;
3472 inst_env->disable_interrupt = 0;
3475 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3476 OR instructions. Note that for this to work as expected, the calling
3477 function must have made sure that there is a prefix to this instruction. */
3480 three_operand_add_sub_cmp_and_or_op (unsigned short inst,
3481 inst_env_type *inst_env)
3483 unsigned long operand2;
3484 unsigned long operand3;
3486 if (cris_get_operand1 (inst) == REG_PC)
3488 /* The PC will be changed by the instruction. */
3489 operand2 = inst_env->reg[cris_get_operand2 (inst)];
3491 /* Get the value of the third operand. */
3492 operand3 = get_data_from_address (&inst, inst_env->prefix_value);
3494 /* Calculate the PC value after the instruction, i.e. where the
3495 breakpoint should be. */
3496 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3498 inst_env->slot_needed = 0;
3499 inst_env->prefix_found = 0;
3500 inst_env->xflag_found = 0;
3501 inst_env->disable_interrupt = 0;
3504 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3505 instructions. The MOVE instruction is the move from source to register. */
3508 handle_prefix_index_mode_for_aritm_op (unsigned short inst,
3509 inst_env_type *inst_env)
3511 if (cris_get_operand1 (inst) != cris_get_operand2 (inst))
3513 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
3514 SUB, AND or OR something weird is going on (if everything works these
3515 instructions should end up in the three operand version). */
3516 inst_env->invalid = 1;
3521 /* three_operand_add_sub_cmp_and_or does the same as we should do here
3523 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3525 inst_env->slot_needed = 0;
3526 inst_env->prefix_found = 0;
3527 inst_env->xflag_found = 0;
3528 inst_env->disable_interrupt = 0;
3531 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3532 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
3533 source to register. */
3536 handle_inc_and_index_mode_for_aritm_op (unsigned short inst,
3537 inst_env_type *inst_env)
3539 unsigned long operand1;
3540 unsigned long operand2;
3541 unsigned long operand3;
3544 /* The instruction is either an indirect or autoincrement addressing mode.
3545 Check if the destination register is the PC. */
3546 if (cris_get_operand2 (inst) == REG_PC)
3548 /* Must be done here, get_data_from_address may change the size
3550 size = cris_get_size (inst);
3551 operand2 = inst_env->reg[REG_PC];
3553 /* Get the value of the third operand, i.e. the indirect operand. */
3554 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3555 operand3 = get_data_from_address (&inst, operand1);
3557 /* Calculate the PC value after the instruction, i.e. where the
3558 breakpoint should be. The order of the udw_operands is vital. */
3559 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3561 /* If this is an autoincrement addressing mode, check if the increment
3563 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3565 /* Get the size field. */
3566 size = cris_get_size (inst);
3568 /* If it's an extend instruction we don't want the signed extend bit,
3569 because it influences the size. */
3570 if (cris_get_opcode (inst) < 4)
3572 size &= ~SIGNED_EXTEND_BIT_MASK;
3574 process_autoincrement (size, inst, inst_env);
3576 inst_env->slot_needed = 0;
3577 inst_env->prefix_found = 0;
3578 inst_env->xflag_found = 0;
3579 inst_env->disable_interrupt = 0;
3582 /* Handles the two-operand addressing mode, all modes except register, for
3583 the ADD, SUB CMP, AND and OR instruction. */
3586 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3587 inst_env_type *inst_env)
3589 if (inst_env->prefix_found)
3591 if (cris_get_mode (inst) == PREFIX_INDEX_MODE)
3593 handle_prefix_index_mode_for_aritm_op (inst, inst_env);
3595 else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
3597 handle_prefix_assign_mode_for_aritm_op (inst, inst_env);
3601 /* The mode is invalid for a prefixed base instruction. */
3602 inst_env->invalid = 1;
3608 handle_inc_and_index_mode_for_aritm_op (inst, inst_env);
3612 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3615 quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env)
3617 unsigned long operand1;
3618 unsigned long operand2;
3620 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3621 instruction and can't have a prefix. */
3622 if (inst_env->prefix_found)
3624 inst_env->invalid = 1;
3628 /* Check if the instruction has PC as its target. */
3629 if (cris_get_operand2 (inst) == REG_PC)
3631 if (inst_env->slot_needed)
3633 inst_env->invalid = 1;
3636 operand1 = cris_get_quick_value (inst);
3637 operand2 = inst_env->reg[REG_PC];
3639 /* The size should now be dword. */
3640 cris_set_size_to_dword (&inst);
3642 /* Calculate the PC value after the instruction, i.e. where the
3643 breakpoint should be. */
3644 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3646 inst_env->slot_needed = 0;
3647 inst_env->prefix_found = 0;
3648 inst_env->xflag_found = 0;
3649 inst_env->disable_interrupt = 0;
3652 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3655 quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env)
3657 unsigned long operand1;
3658 unsigned long operand2;
3660 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3661 instruction and can't have a prefix. */
3662 if (inst_env->prefix_found)
3664 inst_env->invalid = 1;
3667 /* Check if the instruction has PC as its target. */
3668 if (cris_get_operand2 (inst) == REG_PC)
3670 if (inst_env->slot_needed)
3672 inst_env->invalid = 1;
3675 /* The instruction has the PC as its target register. */
3676 operand1 = cris_get_quick_value (inst);
3677 operand2 = inst_env->reg[REG_PC];
3679 /* The quick value is signed, so check if we must do a signed extend. */
3680 if (operand1 & SIGNED_QUICK_VALUE_MASK)
3683 operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK;
3685 /* The size should now be dword. */
3686 cris_set_size_to_dword (&inst);
3688 /* Calculate the PC value after the instruction, i.e. where the
3689 breakpoint should be. */
3690 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3692 inst_env->slot_needed = 0;
3693 inst_env->prefix_found = 0;
3694 inst_env->xflag_found = 0;
3695 inst_env->disable_interrupt = 0;
3698 /* Translate op_type to a function and call it. */
3701 cris_gdb_func (enum cris_op_type op_type, unsigned short inst,
3702 inst_env_type *inst_env)
3706 case cris_not_implemented_op:
3707 not_implemented_op (inst, inst_env);
3711 abs_op (inst, inst_env);
3715 addi_op (inst, inst_env);
3719 asr_op (inst, inst_env);
3723 asrq_op (inst, inst_env);
3726 case cris_ax_ei_setf_op:
3727 ax_ei_setf_op (inst, inst_env);
3730 case cris_bdap_prefix:
3731 bdap_prefix (inst, inst_env);
3734 case cris_biap_prefix:
3735 biap_prefix (inst, inst_env);
3739 break_op (inst, inst_env);
3742 case cris_btst_nop_op:
3743 btst_nop_op (inst, inst_env);
3746 case cris_clearf_di_op:
3747 clearf_di_op (inst, inst_env);
3750 case cris_dip_prefix:
3751 dip_prefix (inst, inst_env);
3754 case cris_dstep_logshift_mstep_neg_not_op:
3755 dstep_logshift_mstep_neg_not_op (inst, inst_env);
3758 case cris_eight_bit_offset_branch_op:
3759 eight_bit_offset_branch_op (inst, inst_env);
3762 case cris_move_mem_to_reg_movem_op:
3763 move_mem_to_reg_movem_op (inst, inst_env);
3766 case cris_move_reg_to_mem_movem_op:
3767 move_reg_to_mem_movem_op (inst, inst_env);
3770 case cris_move_to_preg_op:
3771 move_to_preg_op (inst, inst_env);
3775 muls_op (inst, inst_env);
3779 mulu_op (inst, inst_env);
3782 case cris_none_reg_mode_add_sub_cmp_and_or_move_op:
3783 none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3786 case cris_none_reg_mode_clear_test_op:
3787 none_reg_mode_clear_test_op (inst, inst_env);
3790 case cris_none_reg_mode_jump_op:
3791 none_reg_mode_jump_op (inst, inst_env);
3794 case cris_none_reg_mode_move_from_preg_op:
3795 none_reg_mode_move_from_preg_op (inst, inst_env);
3798 case cris_quick_mode_add_sub_op:
3799 quick_mode_add_sub_op (inst, inst_env);
3802 case cris_quick_mode_and_cmp_move_or_op:
3803 quick_mode_and_cmp_move_or_op (inst, inst_env);
3806 case cris_quick_mode_bdap_prefix:
3807 quick_mode_bdap_prefix (inst, inst_env);
3810 case cris_reg_mode_add_sub_cmp_and_or_move_op:
3811 reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3814 case cris_reg_mode_clear_op:
3815 reg_mode_clear_op (inst, inst_env);
3818 case cris_reg_mode_jump_op:
3819 reg_mode_jump_op (inst, inst_env);
3822 case cris_reg_mode_move_from_preg_op:
3823 reg_mode_move_from_preg_op (inst, inst_env);
3826 case cris_reg_mode_test_op:
3827 reg_mode_test_op (inst, inst_env);
3831 scc_op (inst, inst_env);
3834 case cris_sixteen_bit_offset_branch_op:
3835 sixteen_bit_offset_branch_op (inst, inst_env);
3838 case cris_three_operand_add_sub_cmp_and_or_op:
3839 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3842 case cris_three_operand_bound_op:
3843 three_operand_bound_op (inst, inst_env);
3846 case cris_two_operand_bound_op:
3847 two_operand_bound_op (inst, inst_env);
3851 xor_op (inst, inst_env);
3856 /* This wrapper is to avoid cris_get_assembler being called before
3857 exec_bfd has been set. */
3860 cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info)
3862 int (*print_insn) (bfd_vma addr, struct disassemble_info *info);
3863 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3864 disassembler, even when there is no BFD. Does something like
3865 "gdb; target remote; disassmeble *0x123" work? */
3866 gdb_assert (exec_bfd != NULL);
3867 print_insn = cris_get_disassembler (exec_bfd);
3868 gdb_assert (print_insn != NULL);
3869 return print_insn (addr, info);
3872 /* Copied from <asm/elf.h>. */
3873 typedef unsigned long elf_greg_t;
3875 /* Same as user_regs_struct struct in <asm/user.h>. */
3876 #define CRISV10_ELF_NGREG 35
3877 typedef elf_greg_t elf_gregset_t[CRISV10_ELF_NGREG];
3879 #define CRISV32_ELF_NGREG 32
3880 typedef elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG];
3882 /* Unpack an elf_gregset_t into GDB's register cache. */
3885 cris_supply_gregset (struct regcache *regcache, elf_gregset_t *gregsetp)
3887 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3888 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3890 elf_greg_t *regp = *gregsetp;
3891 static char zerobuf[4] = {0};
3893 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3894 knows about the actual size of each register so that's no problem. */
3895 for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++)
3897 regcache_raw_supply (regcache, i, (char *)®p[i]);
3900 if (tdep->cris_version == 32)
3902 /* Needed to set pseudo-register PC for CRISv32. */
3903 /* FIXME: If ERP is in a delay slot at this point then the PC will
3904 be wrong. Issue a warning to alert the user. */
3905 regcache_raw_supply (regcache, gdbarch_pc_regnum (gdbarch),
3906 (char *)®p[ERP_REGNUM]);
3908 if (*(char *)®p[ERP_REGNUM] & 0x1)
3909 fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n");
3913 /* Use a local version of this function to get the correct types for
3914 regsets, until multi-arch core support is ready. */
3917 fetch_core_registers (struct regcache *regcache,
3918 char *core_reg_sect, unsigned core_reg_size,
3919 int which, CORE_ADDR reg_addr)
3921 elf_gregset_t gregset;
3926 if (core_reg_size != sizeof (elf_gregset_t)
3927 && core_reg_size != sizeof (crisv32_elf_gregset_t))
3929 warning (_("wrong size gregset struct in core file"));
3933 memcpy (&gregset, core_reg_sect, sizeof (gregset));
3934 cris_supply_gregset (regcache, &gregset);
3938 /* We've covered all the kinds of registers we know about here,
3939 so this must be something we wouldn't know what to do with
3940 anyway. Just ignore it. */
3945 static struct core_fns cris_elf_core_fns =
3947 bfd_target_elf_flavour, /* core_flavour */
3948 default_check_format, /* check_format */
3949 default_core_sniffer, /* core_sniffer */
3950 fetch_core_registers, /* core_read_registers */
3954 extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */
3957 _initialize_cris_tdep (void)
3959 static struct cmd_list_element *cris_set_cmdlist;
3960 static struct cmd_list_element *cris_show_cmdlist;
3962 struct cmd_list_element *c;
3964 gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep);
3966 /* CRIS-specific user-commands. */
3967 add_setshow_uinteger_cmd ("cris-version", class_support,
3968 &usr_cmd_cris_version,
3969 _("Set the current CRIS version."),
3970 _("Show the current CRIS version."),
3972 Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\
3975 NULL, /* FIXME: i18n: Current CRIS version is %s. */
3976 &setlist, &showlist);
3978 add_setshow_enum_cmd ("cris-mode", class_support,
3979 cris_modes, &usr_cmd_cris_mode,
3980 _("Set the current CRIS mode."),
3981 _("Show the current CRIS mode."),
3983 Set to CRIS_MODE_GURU when debugging in guru mode.\n\
3984 Makes GDB use the NRP register instead of the ERP register in certain cases."),
3986 NULL, /* FIXME: i18n: Current CRIS version is %s. */
3987 &setlist, &showlist);
3989 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support,
3990 &usr_cmd_cris_dwarf2_cfi,
3991 _("Set the usage of Dwarf-2 CFI for CRIS."),
3992 _("Show the usage of Dwarf-2 CFI for CRIS."),
3993 _("Set this to \"off\" if using gcc-cris < R59."),
3994 set_cris_dwarf2_cfi,
3995 NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI for CRIS is %d. */
3996 &setlist, &showlist);
3998 deprecated_add_core_fns (&cris_elf_core_fns);
4001 /* Prints out all target specific values. */
4004 cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
4006 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4009 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n",
4010 tdep->cris_version);
4011 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n",
4013 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
4014 tdep->cris_dwarf2_cfi);
4019 set_cris_version (char *ignore_args, int from_tty,
4020 struct cmd_list_element *c)
4022 struct gdbarch_info info;
4024 usr_cmd_cris_version_valid = 1;
4026 /* Update the current architecture, if needed. */
4027 gdbarch_info_init (&info);
4028 if (!gdbarch_update_p (info))
4029 internal_error (__FILE__, __LINE__,
4030 _("cris_gdbarch_update: failed to update architecture."));
4034 set_cris_mode (char *ignore_args, int from_tty,
4035 struct cmd_list_element *c)
4037 struct gdbarch_info info;
4039 /* Update the current architecture, if needed. */
4040 gdbarch_info_init (&info);
4041 if (!gdbarch_update_p (info))
4042 internal_error (__FILE__, __LINE__,
4043 "cris_gdbarch_update: failed to update architecture.");
4047 set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
4048 struct cmd_list_element *c)
4050 struct gdbarch_info info;
4052 /* Update the current architecture, if needed. */
4053 gdbarch_info_init (&info);
4054 if (!gdbarch_update_p (info))
4055 internal_error (__FILE__, __LINE__,
4056 _("cris_gdbarch_update: failed to update architecture."));
4059 static struct gdbarch *
4060 cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
4062 struct gdbarch *gdbarch;
4063 struct gdbarch_tdep *tdep;
4066 if (usr_cmd_cris_version_valid)
4068 /* Trust the user's CRIS version setting. */
4069 cris_version = usr_cmd_cris_version;
4071 else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32)
4077 /* Assume it's CRIS version 10. */
4081 /* Make the current settings visible to the user. */
4082 usr_cmd_cris_version = cris_version;
4084 /* Find a candidate among the list of pre-declared architectures. */
4085 for (arches = gdbarch_list_lookup_by_info (arches, &info);
4087 arches = gdbarch_list_lookup_by_info (arches->next, &info))
4089 if ((gdbarch_tdep (arches->gdbarch)->cris_version
4090 == usr_cmd_cris_version)
4091 && (gdbarch_tdep (arches->gdbarch)->cris_mode
4092 == usr_cmd_cris_mode)
4093 && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi
4094 == usr_cmd_cris_dwarf2_cfi))
4095 return arches->gdbarch;
4098 /* No matching architecture was found. Create a new one. */
4099 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
4100 gdbarch = gdbarch_alloc (&info, tdep);
4102 tdep->cris_version = usr_cmd_cris_version;
4103 tdep->cris_mode = usr_cmd_cris_mode;
4104 tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi;
4106 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
4107 switch (info.byte_order)
4109 case BFD_ENDIAN_LITTLE:
4113 case BFD_ENDIAN_BIG:
4114 internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: big endian byte order in info"));
4118 internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: unknown byte order in info"));
4121 set_gdbarch_return_value (gdbarch, cris_return_value);
4123 set_gdbarch_sp_regnum (gdbarch, 14);
4125 /* Length of ordinary registers used in push_word and a few other
4126 places. register_size() is the real way to know how big a
4129 set_gdbarch_double_bit (gdbarch, 64);
4130 /* The default definition of a long double is 2 * gdbarch_double_bit,
4131 which means we have to set this explicitly. */
4132 set_gdbarch_long_double_bit (gdbarch, 64);
4134 /* The total amount of space needed to store (in an array called registers)
4135 GDB's copy of the machine's register state. Note: We can not use
4136 cris_register_size at this point, since it relies on gdbarch
4138 switch (tdep->cris_version)
4146 /* Old versions; not supported. */
4147 internal_error (__FILE__, __LINE__,
4148 _("cris_gdbarch_init: unsupported CRIS version"));
4153 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
4154 P7 (32 bits), and P15 (32 bits) have been implemented. */
4155 set_gdbarch_pc_regnum (gdbarch, 15);
4156 set_gdbarch_register_type (gdbarch, cris_register_type);
4157 /* There are 32 registers (some of which may not be implemented). */
4158 set_gdbarch_num_regs (gdbarch, 32);
4159 set_gdbarch_register_name (gdbarch, cris_register_name);
4160 set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register);
4161 set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register);
4163 set_gdbarch_software_single_step (gdbarch, cris_software_single_step);
4167 /* CRIS v32. General registers R0 - R15 (32 bits), special registers
4168 P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
4169 and pseudo-register PC (32 bits). */
4170 set_gdbarch_pc_regnum (gdbarch, 32);
4171 set_gdbarch_register_type (gdbarch, crisv32_register_type);
4172 /* 32 registers + pseudo-register PC + 16 support registers. */
4173 set_gdbarch_num_regs (gdbarch, 32 + 1 + 16);
4174 set_gdbarch_register_name (gdbarch, crisv32_register_name);
4176 set_gdbarch_cannot_store_register
4177 (gdbarch, crisv32_cannot_store_register);
4178 set_gdbarch_cannot_fetch_register
4179 (gdbarch, crisv32_cannot_fetch_register);
4181 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
4183 set_gdbarch_single_step_through_delay
4184 (gdbarch, crisv32_single_step_through_delay);
4189 internal_error (__FILE__, __LINE__,
4190 _("cris_gdbarch_init: unknown CRIS version"));
4193 /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
4194 have the same ABI). */
4195 set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code);
4196 set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call);
4197 set_gdbarch_frame_align (gdbarch, cris_frame_align);
4198 set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue);
4200 /* The stack grows downward. */
4201 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4203 set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc);
4205 set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc);
4206 set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp);
4207 set_gdbarch_unwind_dummy_id (gdbarch, cris_unwind_dummy_id);
4209 if (tdep->cris_dwarf2_cfi == 1)
4211 /* Hook in the Dwarf-2 frame sniffer. */
4212 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum);
4213 dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg);
4214 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
4217 if (tdep->cris_mode != cris_mode_guru)
4219 frame_unwind_append_sniffer (gdbarch, cris_sigtramp_frame_sniffer);
4222 frame_unwind_append_sniffer (gdbarch, cris_frame_sniffer);
4223 frame_base_set_default (gdbarch, &cris_frame_base);
4225 set_solib_svr4_fetch_link_map_offsets
4226 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
4228 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
4229 disassembler, even when there is no BFD. Does something like
4230 "gdb; target remote; disassmeble *0x123" work? */
4231 set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler);