1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
3 Copyright (C) 2001-2015 Free Software Foundation, Inc.
5 Contributed by Axis Communications AB.
6 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include "frame-unwind.h"
26 #include "frame-base.h"
27 #include "trad-frame.h"
28 #include "dwarf2-frame.h"
36 #include "opcode/cris.h"
38 #include "arch-utils.h"
43 #include "solib.h" /* Support for shared libraries. */
44 #include "solib-svr4.h"
47 #include "cris-tdep.h"
51 /* There are no floating point registers. Used in gdbserver low-linux.c. */
54 /* There are 16 general registers. */
57 /* There are 16 special registers. */
60 /* CRISv32 has a pseudo PC register, not noted here. */
62 /* CRISv32 has 16 support registers. */
66 /* Register numbers of various important registers.
67 CRIS_FP_REGNUM Contains address of executing stack frame.
68 STR_REGNUM Contains the address of structure return values.
69 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
70 ARG1_REGNUM Contains the first parameter to a function.
71 ARG2_REGNUM Contains the second parameter to a function.
72 ARG3_REGNUM Contains the third parameter to a function.
73 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
74 gdbarch_sp_regnum Contains address of top of stack.
75 gdbarch_pc_regnum Contains address of next instruction.
76 SRP_REGNUM Subroutine return pointer register.
77 BRP_REGNUM Breakpoint return pointer register. */
81 /* Enums with respect to the general registers, valid for all
82 CRIS versions. The frame pointer is always in R8. */
84 /* ABI related registers. */
92 /* Registers which happen to be common. */
97 /* CRISv10 et al. specific registers. */
109 /* CRISv32 specific registers. */
122 CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */
124 CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */
144 extern const struct cris_spec_reg cris_spec_regs[];
146 /* CRIS version, set via the user command 'set cris-version'. Affects
147 register names and sizes. */
148 static unsigned int usr_cmd_cris_version;
150 /* Indicates whether to trust the above variable. */
151 static int usr_cmd_cris_version_valid = 0;
153 static const char cris_mode_normal[] = "normal";
154 static const char cris_mode_guru[] = "guru";
155 static const char *const cris_modes[] = {
161 /* CRIS mode, set via the user command 'set cris-mode'. Affects
162 type of break instruction among other things. */
163 static const char *usr_cmd_cris_mode = cris_mode_normal;
165 /* Whether to make use of Dwarf-2 CFI (default on). */
166 static int usr_cmd_cris_dwarf2_cfi = 1;
168 /* Sigtramp identification code copied from i386-linux-tdep.c. */
170 #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
171 #define SIGTRAMP_OFFSET0 0
172 #define SIGTRAMP_INSN1 0xe93d /* break 13 */
173 #define SIGTRAMP_OFFSET1 4
175 static const unsigned short sigtramp_code[] =
177 SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */
178 SIGTRAMP_INSN1 /* break 13 */
181 #define SIGTRAMP_LEN (sizeof sigtramp_code)
183 /* Note: same length as normal sigtramp code. */
185 static const unsigned short rt_sigtramp_code[] =
187 SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */
188 SIGTRAMP_INSN1 /* break 13 */
191 /* If PC is in a sigtramp routine, return the address of the start of
192 the routine. Otherwise, return 0. */
195 cris_sigtramp_start (struct frame_info *this_frame)
197 CORE_ADDR pc = get_frame_pc (this_frame);
198 gdb_byte buf[SIGTRAMP_LEN];
200 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
203 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
205 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
208 pc -= SIGTRAMP_OFFSET1;
209 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
213 if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0)
219 /* If PC is in a RT sigtramp routine, return the address of the start of
220 the routine. Otherwise, return 0. */
223 cris_rt_sigtramp_start (struct frame_info *this_frame)
225 CORE_ADDR pc = get_frame_pc (this_frame);
226 gdb_byte buf[SIGTRAMP_LEN];
228 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
231 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
233 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
236 pc -= SIGTRAMP_OFFSET1;
237 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
241 if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0)
247 /* Assuming THIS_FRAME is a frame for a GNU/Linux sigtramp routine,
248 return the address of the associated sigcontext structure. */
251 cris_sigcontext_addr (struct frame_info *this_frame)
253 struct gdbarch *gdbarch = get_frame_arch (this_frame);
254 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
259 get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
260 sp = extract_unsigned_integer (buf, 4, byte_order);
262 /* Look for normal sigtramp frame first. */
263 pc = cris_sigtramp_start (this_frame);
266 /* struct signal_frame (arch/cris/kernel/signal.c) contains
267 struct sigcontext as its first member, meaning the SP points to
272 pc = cris_rt_sigtramp_start (this_frame);
275 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
276 a struct ucontext, which in turn contains a struct sigcontext.
278 4 + 4 + 128 to struct ucontext, then
279 4 + 4 + 12 to struct sigcontext. */
283 error (_("Couldn't recognize signal trampoline."));
287 struct cris_unwind_cache
289 /* The previous frame's inner most stack address. Used as this
290 frame ID's stack_addr. */
292 /* The frame's base, optionally used by the high-level debug info. */
295 /* How far the SP and r8 (FP) have been offset from the start of
296 the stack frame (as defined by the previous frame's stack
302 /* From old frame_extra_info struct. */
306 /* Table indicating the location of each and every register. */
307 struct trad_frame_saved_reg *saved_regs;
310 static struct cris_unwind_cache *
311 cris_sigtramp_frame_unwind_cache (struct frame_info *this_frame,
314 struct gdbarch *gdbarch = get_frame_arch (this_frame);
315 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
316 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
317 struct cris_unwind_cache *info;
323 return (struct cris_unwind_cache *) (*this_cache);
325 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
326 (*this_cache) = info;
327 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
329 /* Zero all fields. */
335 info->uses_frame = 0;
337 info->leaf_function = 0;
339 get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
340 info->base = extract_unsigned_integer (buf, 4, byte_order);
342 addr = cris_sigcontext_addr (this_frame);
344 /* Layout of the sigcontext struct:
347 unsigned long oldmask;
351 if (tdep->cris_version == 10)
353 /* R0 to R13 are stored in reverse order at offset (2 * 4) in
355 for (i = 0; i <= 13; i++)
356 info->saved_regs[i].addr = addr + ((15 - i) * 4);
358 info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4);
359 info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4);
360 info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4);
361 /* Note: IRP is off by 2 at this point. There's no point in correcting
362 it though since that will mean that the backtrace will show a PC
363 different from what is shown when stopped. */
364 info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4);
365 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
366 = info->saved_regs[IRP_REGNUM];
367 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr = addr + (24 * 4);
372 /* R0 to R13 are stored in order at offset (1 * 4) in
374 for (i = 0; i <= 13; i++)
375 info->saved_regs[i].addr = addr + ((i + 1) * 4);
377 info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4);
378 info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4);
379 info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4);
380 info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4);
381 info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4);
382 info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4);
383 info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4);
384 info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4);
385 info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4);
387 /* FIXME: If ERP is in a delay slot at this point then the PC will
388 be wrong at this point. This problem manifests itself in the
389 sigaltstack.exp test case, which occasionally generates FAILs when
390 the signal is received while in a delay slot.
392 This could be solved by a couple of read_memory_unsigned_integer and a
393 trad_frame_set_value. */
394 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
395 = info->saved_regs[ERP_REGNUM];
397 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr
405 cris_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
406 struct frame_id *this_id)
408 struct cris_unwind_cache *cache =
409 cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
410 (*this_id) = frame_id_build (cache->base, get_frame_pc (this_frame));
413 /* Forward declaration. */
415 static struct value *cris_frame_prev_register (struct frame_info *this_frame,
416 void **this_cache, int regnum);
417 static struct value *
418 cris_sigtramp_frame_prev_register (struct frame_info *this_frame,
419 void **this_cache, int regnum)
421 /* Make sure we've initialized the cache. */
422 cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
423 return cris_frame_prev_register (this_frame, this_cache, regnum);
427 cris_sigtramp_frame_sniffer (const struct frame_unwind *self,
428 struct frame_info *this_frame,
431 if (cris_sigtramp_start (this_frame)
432 || cris_rt_sigtramp_start (this_frame))
438 static const struct frame_unwind cris_sigtramp_frame_unwind =
441 default_frame_unwind_stop_reason,
442 cris_sigtramp_frame_this_id,
443 cris_sigtramp_frame_prev_register,
445 cris_sigtramp_frame_sniffer
449 crisv32_single_step_through_delay (struct gdbarch *gdbarch,
450 struct frame_info *this_frame)
452 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
456 if (tdep->cris_mode == cris_mode_guru)
457 erp = get_frame_register_unsigned (this_frame, NRP_REGNUM);
459 erp = get_frame_register_unsigned (this_frame, ERP_REGNUM);
463 /* In delay slot - check if there's a breakpoint at the preceding
465 if (breakpoint_here_p (get_frame_address_space (this_frame), erp & ~0x1))
471 /* The instruction environment needed to find single-step breakpoints. */
474 struct instruction_environment
476 unsigned long reg[NUM_GENREGS];
477 unsigned long preg[NUM_SPECREGS];
478 unsigned long branch_break_address;
479 unsigned long delay_slot_pc;
480 unsigned long prefix_value;
485 int delay_slot_pc_active;
487 int disable_interrupt;
491 /* Machine-dependencies in CRIS for opcodes. */
493 /* Instruction sizes. */
494 enum cris_instruction_sizes
501 /* Addressing modes. */
502 enum cris_addressing_modes
509 /* Prefix addressing modes. */
510 enum cris_prefix_addressing_modes
512 PREFIX_INDEX_MODE = 2,
513 PREFIX_ASSIGN_MODE = 3,
515 /* Handle immediate byte offset addressing mode prefix format. */
516 PREFIX_OFFSET_MODE = 2
519 /* Masks for opcodes. */
520 enum cris_opcode_masks
522 BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1,
523 SIGNED_EXTEND_BIT_MASK = 0x2,
524 SIGNED_BYTE_MASK = 0x80,
525 SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00,
526 SIGNED_WORD_MASK = 0x8000,
527 SIGNED_WORD_EXTEND_MASK = 0xFFFF0000,
528 SIGNED_DWORD_MASK = 0x80000000,
529 SIGNED_QUICK_VALUE_MASK = 0x20,
530 SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0
533 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
541 cris_get_operand2 (unsigned short insn)
543 return ((insn & 0xF000) >> 12);
547 cris_get_mode (unsigned short insn)
549 return ((insn & 0x0C00) >> 10);
553 cris_get_opcode (unsigned short insn)
555 return ((insn & 0x03C0) >> 6);
559 cris_get_size (unsigned short insn)
561 return ((insn & 0x0030) >> 4);
565 cris_get_operand1 (unsigned short insn)
567 return (insn & 0x000F);
570 /* Additional functions in order to handle opcodes. */
573 cris_get_quick_value (unsigned short insn)
575 return (insn & 0x003F);
579 cris_get_bdap_quick_offset (unsigned short insn)
581 return (insn & 0x00FF);
585 cris_get_branch_short_offset (unsigned short insn)
587 return (insn & 0x00FF);
591 cris_get_asr_shift_steps (unsigned long value)
593 return (value & 0x3F);
597 cris_get_clear_size (unsigned short insn)
599 return ((insn) & 0xC000);
603 cris_is_signed_extend_bit_on (unsigned short insn)
605 return (((insn) & 0x20) == 0x20);
609 cris_is_xflag_bit_on (unsigned short insn)
611 return (((insn) & 0x1000) == 0x1000);
615 cris_set_size_to_dword (unsigned short *insn)
622 cris_get_signed_offset (unsigned short insn)
624 return ((signed char) (insn & 0x00FF));
627 /* Calls an op function given the op-type, working on the insn and the
629 static void cris_gdb_func (struct gdbarch *, enum cris_op_type, unsigned short,
632 static struct gdbarch *cris_gdbarch_init (struct gdbarch_info,
633 struct gdbarch_list *);
635 static void cris_dump_tdep (struct gdbarch *, struct ui_file *);
637 static void set_cris_version (char *ignore_args, int from_tty,
638 struct cmd_list_element *c);
640 static void set_cris_mode (char *ignore_args, int from_tty,
641 struct cmd_list_element *c);
643 static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
644 struct cmd_list_element *c);
646 static CORE_ADDR cris_scan_prologue (CORE_ADDR pc,
647 struct frame_info *this_frame,
648 struct cris_unwind_cache *info);
650 static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc,
651 struct frame_info *this_frame,
652 struct cris_unwind_cache *info);
654 static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch,
655 struct frame_info *next_frame);
657 static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch,
658 struct frame_info *next_frame);
660 /* When arguments must be pushed onto the stack, they go on in reverse
661 order. The below implements a FILO (stack) to do this.
662 Copied from d10v-tdep.c. */
667 struct stack_item *prev;
671 static struct stack_item *
672 push_stack_item (struct stack_item *prev, const gdb_byte *contents, int len)
674 struct stack_item *si = XNEW (struct stack_item);
675 si->data = xmalloc (len);
678 memcpy (si->data, contents, len);
682 static struct stack_item *
683 pop_stack_item (struct stack_item *si)
685 struct stack_item *dead = si;
692 /* Put here the code to store, into fi->saved_regs, the addresses of
693 the saved registers of frame described by FRAME_INFO. This
694 includes special registers such as pc and fp saved in special ways
695 in the stack frame. sp is even more special: the address we return
696 for it IS the sp for the next frame. */
698 static struct cris_unwind_cache *
699 cris_frame_unwind_cache (struct frame_info *this_frame,
700 void **this_prologue_cache)
702 struct gdbarch *gdbarch = get_frame_arch (this_frame);
703 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
704 struct cris_unwind_cache *info;
706 if ((*this_prologue_cache))
707 return (struct cris_unwind_cache *) (*this_prologue_cache);
709 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
710 (*this_prologue_cache) = info;
711 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
713 /* Zero all fields. */
719 info->uses_frame = 0;
721 info->leaf_function = 0;
723 /* Prologue analysis does the rest... */
724 if (tdep->cris_version == 32)
725 crisv32_scan_prologue (get_frame_func (this_frame), this_frame, info);
727 cris_scan_prologue (get_frame_func (this_frame), this_frame, info);
732 /* Given a GDB frame, determine the address of the calling function's
733 frame. This will be used to create a new GDB frame struct. */
736 cris_frame_this_id (struct frame_info *this_frame,
737 void **this_prologue_cache,
738 struct frame_id *this_id)
740 struct cris_unwind_cache *info
741 = cris_frame_unwind_cache (this_frame, this_prologue_cache);
746 /* The FUNC is easy. */
747 func = get_frame_func (this_frame);
749 /* Hopefully the prologue analysis either correctly determined the
750 frame's base (which is the SP from the previous frame), or set
751 that base to "NULL". */
752 base = info->prev_sp;
756 id = frame_id_build (base, func);
761 static struct value *
762 cris_frame_prev_register (struct frame_info *this_frame,
763 void **this_prologue_cache, int regnum)
765 struct cris_unwind_cache *info
766 = cris_frame_unwind_cache (this_frame, this_prologue_cache);
767 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
770 /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
771 frame. The frame ID's base needs to match the TOS value saved by
772 save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */
774 static struct frame_id
775 cris_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
778 sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
779 return frame_id_build (sp, get_frame_pc (this_frame));
783 cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
785 /* Align to the size of an instruction (so that they can safely be
786 pushed onto the stack). */
791 cris_push_dummy_code (struct gdbarch *gdbarch,
792 CORE_ADDR sp, CORE_ADDR funaddr,
793 struct value **args, int nargs,
794 struct type *value_type,
795 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
796 struct regcache *regcache)
798 /* Allocate space sufficient for a breakpoint. */
800 /* Store the address of that breakpoint */
802 /* CRIS always starts the call at the callee's entry point. */
808 cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
809 struct regcache *regcache, CORE_ADDR bp_addr,
810 int nargs, struct value **args, CORE_ADDR sp,
811 int struct_return, CORE_ADDR struct_addr)
813 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
818 /* The function's arguments and memory allocated by gdb for the arguments to
819 point at reside in separate areas on the stack.
820 Both frame pointers grow toward higher addresses. */
824 struct stack_item *si = NULL;
826 /* Push the return address. */
827 regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr);
829 /* Are we returning a value using a structure return or a normal value
830 return? struct_addr is the address of the reserved space for the return
831 structure to be written on the stack. */
834 regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr);
837 /* Now load as many as possible of the first arguments into registers,
838 and push the rest onto the stack. */
839 argreg = ARG1_REGNUM;
842 for (argnum = 0; argnum < nargs; argnum++)
849 len = TYPE_LENGTH (value_type (args[argnum]));
850 val = value_contents (args[argnum]);
852 /* How may registers worth of storage do we need for this argument? */
853 reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0);
855 if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM))
857 /* Data passed by value. Fits in available register(s). */
858 for (i = 0; i < reg_demand; i++)
860 regcache_cooked_write (regcache, argreg, val);
865 else if (len <= (2 * 4) && argreg <= ARG4_REGNUM)
867 /* Data passed by value. Does not fit in available register(s).
868 Use the register(s) first, then the stack. */
869 for (i = 0; i < reg_demand; i++)
871 if (argreg <= ARG4_REGNUM)
873 regcache_cooked_write (regcache, argreg, val);
879 /* Push item for later so that pushed arguments
880 come in the right order. */
881 si = push_stack_item (si, val, 4);
886 else if (len > (2 * 4))
888 /* Data passed by reference. Push copy of data onto stack
889 and pass pointer to this copy as argument. */
890 sp = (sp - len) & ~3;
891 write_memory (sp, val, len);
893 if (argreg <= ARG4_REGNUM)
895 regcache_cooked_write_unsigned (regcache, argreg, sp);
901 store_unsigned_integer (buf, 4, byte_order, sp);
902 si = push_stack_item (si, buf, 4);
907 /* Data passed by value. No available registers. Put it on
909 si = push_stack_item (si, val, len);
915 /* fp_arg must be word-aligned (i.e., don't += len) to match
916 the function prologue. */
917 sp = (sp - si->len) & ~3;
918 write_memory (sp, si->data, si->len);
919 si = pop_stack_item (si);
922 /* Finally, update the SP register. */
923 regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp);
928 static const struct frame_unwind cris_frame_unwind =
931 default_frame_unwind_stop_reason,
933 cris_frame_prev_register,
935 default_frame_sniffer
939 cris_frame_base_address (struct frame_info *this_frame, void **this_cache)
941 struct cris_unwind_cache *info
942 = cris_frame_unwind_cache (this_frame, this_cache);
946 static const struct frame_base cris_frame_base =
949 cris_frame_base_address,
950 cris_frame_base_address,
951 cris_frame_base_address
954 /* Frames information. The definition of the struct frame_info is
958 enum frame_type type;
962 If the compilation option -fno-omit-frame-pointer is present the
963 variable frame will be set to the content of R8 which is the frame
966 The variable pc contains the address where execution is performed
967 in the present frame. The innermost frame contains the current content
968 of the register PC. All other frames contain the content of the
969 register PC in the next frame.
971 The variable `type' indicates the frame's type: normal, SIGTRAMP
972 (associated with a signal handler), dummy (associated with a dummy
975 The variable return_pc contains the address where execution should be
976 resumed when the present frame has finished, the return address.
978 The variable leaf_function is 1 if the return address is in the register
979 SRP, and 0 if it is on the stack.
981 Prologue instructions C-code.
982 The prologue may consist of (-fno-omit-frame-pointer)
986 move.d sp,r8 move.d sp,r8
988 movem rY,[sp] movem rY,[sp]
989 move.S rZ,[r8-U] move.S rZ,[r8-U]
991 where 1 is a non-terminal function, and 2 is a leaf-function.
993 Note that this assumption is extremely brittle, and will break at the
994 slightest change in GCC's prologue.
996 If local variables are declared or register contents are saved on stack
997 the subq-instruction will be present with X as the number of bytes
998 needed for storage. The reshuffle with respect to r8 may be performed
999 with any size S (b, w, d) and any of the general registers Z={0..13}.
1000 The offset U should be representable by a signed 8-bit value in all cases.
1001 Thus, the prefix word is assumed to be immediate byte offset mode followed
1002 by another word containing the instruction.
1011 Prologue instructions C++-code.
1012 Case 1) and 2) in the C-code may be followed by
1014 move.d r10,rS ; this
1018 move.S [r8+U],rZ ; P4
1020 if any of the call parameters are stored. The host expects these
1021 instructions to be executed in order to get the call parameters right. */
1023 /* Examine the prologue of a function. The variable ip is the address of
1024 the first instruction of the prologue. The variable limit is the address
1025 of the first instruction after the prologue. The variable fi contains the
1026 information in struct frame_info. The variable frameless_p controls whether
1027 the entire prologue is examined (0) or just enough instructions to
1028 determine that it is a prologue (1). */
1031 cris_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
1032 struct cris_unwind_cache *info)
1034 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1035 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1037 /* Present instruction. */
1038 unsigned short insn;
1040 /* Next instruction, lookahead. */
1041 unsigned short insn_next;
1044 /* Is there a push fp? */
1047 /* Number of byte on stack used for local variables and movem. */
1050 /* Highest register number in a movem. */
1053 /* move.d r<source_register>,rS */
1054 short source_register;
1059 /* This frame is with respect to a leaf until a push srp is found. */
1062 info->leaf_function = 1;
1065 /* Assume nothing on stack. */
1069 /* If we were called without a this_frame, that means we were called
1070 from cris_skip_prologue which already tried to find the end of the
1071 prologue through the symbol information. 64 instructions past current
1072 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
1073 limit = this_frame ? get_frame_pc (this_frame) : pc + 64;
1075 /* Find the prologue instructions. */
1076 while (pc > 0 && pc < limit)
1078 insn = read_memory_unsigned_integer (pc, 2, byte_order);
1082 /* push <reg> 32 bit instruction. */
1083 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1085 regno = cris_get_operand2 (insn_next);
1088 info->sp_offset += 4;
1090 /* This check, meant to recognize srp, used to be regno ==
1091 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
1092 if (insn_next == 0xBE7E)
1096 info->leaf_function = 0;
1099 else if (insn_next == 0x8FEE)
1104 info->r8_offset = info->sp_offset;
1108 else if (insn == 0x866E)
1113 info->uses_frame = 1;
1117 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1118 && cris_get_mode (insn) == 0x0000
1119 && cris_get_opcode (insn) == 0x000A)
1124 info->sp_offset += cris_get_quick_value (insn);
1127 else if (cris_get_mode (insn) == 0x0002
1128 && cris_get_opcode (insn) == 0x000F
1129 && cris_get_size (insn) == 0x0003
1130 && cris_get_operand1 (insn) == gdbarch_sp_regnum (gdbarch))
1132 /* movem r<regsave>,[sp] */
1133 regsave = cris_get_operand2 (insn);
1135 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1136 && ((insn & 0x0F00) >> 8) == 0x0001
1137 && (cris_get_signed_offset (insn) < 0))
1139 /* Immediate byte offset addressing prefix word with sp as base
1140 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1141 is between 64 and 128.
1142 movem r<regsave>,[sp=sp-<val>] */
1145 info->sp_offset += -cris_get_signed_offset (insn);
1147 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1149 if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE
1150 && cris_get_opcode (insn_next) == 0x000F
1151 && cris_get_size (insn_next) == 0x0003
1152 && cris_get_operand1 (insn_next) == gdbarch_sp_regnum
1155 regsave = cris_get_operand2 (insn_next);
1159 /* The prologue ended before the limit was reached. */
1164 else if (cris_get_mode (insn) == 0x0001
1165 && cris_get_opcode (insn) == 0x0009
1166 && cris_get_size (insn) == 0x0002)
1168 /* move.d r<10..13>,r<0..15> */
1169 source_register = cris_get_operand1 (insn);
1171 /* FIXME? In the glibc solibs, the prologue might contain something
1172 like (this example taken from relocate_doit):
1174 sub.d 0xfffef426,$r0
1175 which isn't covered by the source_register check below. Question
1176 is whether to add a check for this combo, or make better use of
1177 the limit variable instead. */
1178 if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM)
1180 /* The prologue ended before the limit was reached. */
1185 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1186 /* The size is a fixed-size. */
1187 && ((insn & 0x0F00) >> 8) == 0x0001
1188 /* A negative offset. */
1189 && (cris_get_signed_offset (insn) < 0))
1191 /* move.S rZ,[r8-U] (?) */
1192 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1194 regno = cris_get_operand2 (insn_next);
1195 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1196 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1197 && cris_get_opcode (insn_next) == 0x000F)
1199 /* move.S rZ,[r8-U] */
1204 /* The prologue ended before the limit was reached. */
1209 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1210 /* The size is a fixed-size. */
1211 && ((insn & 0x0F00) >> 8) == 0x0001
1212 /* A positive offset. */
1213 && (cris_get_signed_offset (insn) > 0))
1215 /* move.S [r8+U],rZ (?) */
1216 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1218 regno = cris_get_operand2 (insn_next);
1219 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1220 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1221 && cris_get_opcode (insn_next) == 0x0009
1222 && cris_get_operand1 (insn_next) == regno)
1224 /* move.S [r8+U],rZ */
1229 /* The prologue ended before the limit was reached. */
1236 /* The prologue ended before the limit was reached. */
1242 /* We only want to know the end of the prologue when this_frame and info
1243 are NULL (called from cris_skip_prologue i.e.). */
1244 if (this_frame == NULL && info == NULL)
1249 info->size = info->sp_offset;
1251 /* Compute the previous frame's stack pointer (which is also the
1252 frame's ID's stack address), and this frame's base pointer. */
1253 if (info->uses_frame)
1256 /* The SP was moved to the FP. This indicates that a new frame
1257 was created. Get THIS frame's FP value by unwinding it from
1259 this_base = get_frame_register_unsigned (this_frame, CRIS_FP_REGNUM);
1260 info->base = this_base;
1261 info->saved_regs[CRIS_FP_REGNUM].addr = info->base;
1263 /* The FP points at the last saved register. Adjust the FP back
1264 to before the first saved register giving the SP. */
1265 info->prev_sp = info->base + info->r8_offset;
1270 /* Assume that the FP is this frame's SP but with that pushed
1271 stack space added back. */
1272 this_base = get_frame_register_unsigned (this_frame,
1273 gdbarch_sp_regnum (gdbarch));
1274 info->base = this_base;
1275 info->prev_sp = info->base + info->size;
1278 /* Calculate the addresses for the saved registers on the stack. */
1279 /* FIXME: The address calculation should really be done on the fly while
1280 we're analyzing the prologue (we only hold one regsave value as it is
1282 val = info->sp_offset;
1284 for (regno = regsave; regno >= 0; regno--)
1286 info->saved_regs[regno].addr = info->base + info->r8_offset - val;
1290 /* The previous frame's SP needed to be computed. Save the computed
1292 trad_frame_set_value (info->saved_regs,
1293 gdbarch_sp_regnum (gdbarch), info->prev_sp);
1295 if (!info->leaf_function)
1297 /* SRP saved on the stack. But where? */
1298 if (info->r8_offset == 0)
1300 /* R8 not pushed yet. */
1301 info->saved_regs[SRP_REGNUM].addr = info->base;
1305 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1306 info->saved_regs[SRP_REGNUM].addr = info->base + 4;
1310 /* The PC is found in SRP (the actual register or located on the stack). */
1311 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1312 = info->saved_regs[SRP_REGNUM];
1318 crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
1319 struct cris_unwind_cache *info)
1321 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1324 /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not
1325 meant to be a full-fledged prologue scanner. It is only needed for
1326 the cases where we end up in code always lacking DWARF-2 CFI, notably:
1328 * PLT stubs (library calls)
1330 * signal trampolines
1332 For those cases, it is assumed that there is no actual prologue; that
1333 the stack pointer is not adjusted, and (as a consequence) the return
1334 address is not pushed onto the stack. */
1336 /* We only want to know the end of the prologue when this_frame and info
1337 are NULL (called from cris_skip_prologue i.e.). */
1338 if (this_frame == NULL && info == NULL)
1343 /* The SP is assumed to be unaltered. */
1344 this_base = get_frame_register_unsigned (this_frame,
1345 gdbarch_sp_regnum (gdbarch));
1346 info->base = this_base;
1347 info->prev_sp = this_base;
1349 /* The PC is assumed to be found in SRP. */
1350 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1351 = info->saved_regs[SRP_REGNUM];
1356 /* Advance pc beyond any function entry prologue instructions at pc
1357 to reach some "real" code. */
1359 /* Given a PC value corresponding to the start of a function, return the PC
1360 of the first instruction after the function prologue. */
1363 cris_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1365 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1366 CORE_ADDR func_addr, func_end;
1367 struct symtab_and_line sal;
1368 CORE_ADDR pc_after_prologue;
1370 /* If we have line debugging information, then the end of the prologue
1371 should the first assembly instruction of the first source line. */
1372 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1374 sal = find_pc_line (func_addr, 0);
1375 if (sal.end > 0 && sal.end < func_end)
1379 if (tdep->cris_version == 32)
1380 pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL);
1382 pc_after_prologue = cris_scan_prologue (pc, NULL, NULL);
1384 return pc_after_prologue;
1388 cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1391 pc = frame_unwind_register_unsigned (next_frame,
1392 gdbarch_pc_regnum (gdbarch));
1397 cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1400 sp = frame_unwind_register_unsigned (next_frame,
1401 gdbarch_sp_regnum (gdbarch));
1405 /* Use the program counter to determine the contents and size of a breakpoint
1406 instruction. It returns a pointer to a string of bytes that encode a
1407 breakpoint instruction, stores the length of the string to *lenptr, and
1408 adjusts pcptr (if necessary) to point to the actual memory location where
1409 the breakpoint should be inserted. */
1411 static const unsigned char *
1412 cris_breakpoint_from_pc (struct gdbarch *gdbarch,
1413 CORE_ADDR *pcptr, int *lenptr)
1415 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1416 static unsigned char break8_insn[] = {0x38, 0xe9};
1417 static unsigned char break15_insn[] = {0x3f, 0xe9};
1420 if (tdep->cris_mode == cris_mode_guru)
1421 return break15_insn;
1426 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1430 cris_spec_reg_applicable (struct gdbarch *gdbarch,
1431 struct cris_spec_reg spec_reg)
1433 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1434 unsigned int version = tdep->cris_version;
1436 switch (spec_reg.applicable_version)
1438 case cris_ver_version_all:
1440 case cris_ver_warning:
1441 /* Indeterminate/obsolete. */
1444 return (version >= 0 && version <= 3);
1446 return (version >= 3);
1448 return (version == 8 || version == 9);
1450 return (version >= 8);
1451 case cris_ver_v0_10:
1452 return (version >= 0 && version <= 10);
1453 case cris_ver_v3_10:
1454 return (version >= 3 && version <= 10);
1455 case cris_ver_v8_10:
1456 return (version >= 8 && version <= 10);
1458 return (version == 10);
1460 return (version >= 10);
1462 return (version >= 32);
1464 /* Invalid cris version. */
1469 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1470 register, -1 for an invalid register. */
1473 cris_register_size (struct gdbarch *gdbarch, int regno)
1475 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1479 if (regno >= 0 && regno < NUM_GENREGS)
1481 /* General registers (R0 - R15) are 32 bits. */
1484 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1486 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1487 Adjust regno accordingly. */
1488 spec_regno = regno - NUM_GENREGS;
1490 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1492 if (cris_spec_regs[i].number == spec_regno
1493 && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i]))
1494 /* Go with the first applicable register. */
1495 return cris_spec_regs[i].reg_size;
1497 /* Special register not applicable to this CRIS version. */
1500 else if (regno >= gdbarch_pc_regnum (gdbarch)
1501 && regno < gdbarch_num_regs (gdbarch))
1503 /* This will apply to CRISv32 only where there are additional registers
1504 after the special registers (pseudo PC and support registers). */
1512 /* Nonzero if regno should not be fetched from the target. This is the case
1513 for unimplemented (size 0) and non-existant registers. */
1516 cris_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1518 return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1519 || (cris_register_size (gdbarch, regno) == 0));
1522 /* Nonzero if regno should not be written to the target, for various
1526 cris_cannot_store_register (struct gdbarch *gdbarch, int regno)
1528 /* There are three kinds of registers we refuse to write to.
1529 1. Those that not implemented.
1530 2. Those that are read-only (depends on the processor mode).
1531 3. Those registers to which a write has no effect. */
1534 || regno >= gdbarch_num_regs (gdbarch)
1535 || cris_register_size (gdbarch, regno) == 0)
1536 /* Not implemented. */
1539 else if (regno == VR_REGNUM)
1543 else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM)
1544 /* Writing has no effect. */
1547 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
1548 agent decide whether they are writable. */
1553 /* Nonzero if regno should not be fetched from the target. This is the case
1554 for unimplemented (size 0) and non-existant registers. */
1557 crisv32_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1559 return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1560 || (cris_register_size (gdbarch, regno) == 0));
1563 /* Nonzero if regno should not be written to the target, for various
1567 crisv32_cannot_store_register (struct gdbarch *gdbarch, int regno)
1569 /* There are three kinds of registers we refuse to write to.
1570 1. Those that not implemented.
1571 2. Those that are read-only (depends on the processor mode).
1572 3. Those registers to which a write has no effect. */
1575 || regno >= gdbarch_num_regs (gdbarch)
1576 || cris_register_size (gdbarch, regno) == 0)
1577 /* Not implemented. */
1580 else if (regno == VR_REGNUM)
1584 else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM)
1585 /* Writing has no effect. */
1588 /* Many special registers are read-only in user mode. Let the debug
1589 agent decide whether they are writable. */
1594 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1595 of data in register regno. */
1597 static struct type *
1598 cris_register_type (struct gdbarch *gdbarch, int regno)
1600 if (regno == gdbarch_pc_regnum (gdbarch))
1601 return builtin_type (gdbarch)->builtin_func_ptr;
1602 else if (regno == gdbarch_sp_regnum (gdbarch)
1603 || regno == CRIS_FP_REGNUM)
1604 return builtin_type (gdbarch)->builtin_data_ptr;
1605 else if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1606 || (regno >= MOF_REGNUM && regno <= USP_REGNUM))
1607 /* Note: R8 taken care of previous clause. */
1608 return builtin_type (gdbarch)->builtin_uint32;
1609 else if (regno >= P4_REGNUM && regno <= CCR_REGNUM)
1610 return builtin_type (gdbarch)->builtin_uint16;
1611 else if (regno >= P0_REGNUM && regno <= VR_REGNUM)
1612 return builtin_type (gdbarch)->builtin_uint8;
1614 /* Invalid (unimplemented) register. */
1615 return builtin_type (gdbarch)->builtin_int0;
1618 static struct type *
1619 crisv32_register_type (struct gdbarch *gdbarch, int regno)
1621 if (regno == gdbarch_pc_regnum (gdbarch))
1622 return builtin_type (gdbarch)->builtin_func_ptr;
1623 else if (regno == gdbarch_sp_regnum (gdbarch)
1624 || regno == CRIS_FP_REGNUM)
1625 return builtin_type (gdbarch)->builtin_data_ptr;
1626 else if ((regno >= 0 && regno <= ACR_REGNUM)
1627 || (regno >= EXS_REGNUM && regno <= SPC_REGNUM)
1628 || (regno == PID_REGNUM)
1629 || (regno >= S0_REGNUM && regno <= S15_REGNUM))
1630 /* Note: R8 and SP taken care of by previous clause. */
1631 return builtin_type (gdbarch)->builtin_uint32;
1632 else if (regno == WZ_REGNUM)
1633 return builtin_type (gdbarch)->builtin_uint16;
1634 else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM)
1635 return builtin_type (gdbarch)->builtin_uint8;
1638 /* Invalid (unimplemented) register. Should not happen as there are
1639 no unimplemented CRISv32 registers. */
1640 warning (_("crisv32_register_type: unknown regno %d"), regno);
1641 return builtin_type (gdbarch)->builtin_int0;
1645 /* Stores a function return value of type type, where valbuf is the address
1646 of the value to be stored. */
1648 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1651 cris_store_return_value (struct type *type, struct regcache *regcache,
1652 const gdb_byte *valbuf)
1654 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1655 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1657 int len = TYPE_LENGTH (type);
1661 /* Put the return value in R10. */
1662 val = extract_unsigned_integer (valbuf, len, byte_order);
1663 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1667 /* Put the return value in R10 and R11. */
1668 val = extract_unsigned_integer (valbuf, 4, byte_order);
1669 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1670 val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order);
1671 regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val);
1674 error (_("cris_store_return_value: type length too large."));
1677 /* Return the name of register regno as a string. Return NULL for an
1678 invalid or unimplemented register. */
1681 cris_special_register_name (struct gdbarch *gdbarch, int regno)
1686 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1687 Adjust regno accordingly. */
1688 spec_regno = regno - NUM_GENREGS;
1690 /* Assume nothing about the layout of the cris_spec_regs struct
1692 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1694 if (cris_spec_regs[i].number == spec_regno
1695 && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i]))
1696 /* Go with the first applicable register. */
1697 return cris_spec_regs[i].name;
1699 /* Special register not applicable to this CRIS version. */
1704 cris_register_name (struct gdbarch *gdbarch, int regno)
1706 static char *cris_genreg_names[] =
1707 { "r0", "r1", "r2", "r3", \
1708 "r4", "r5", "r6", "r7", \
1709 "r8", "r9", "r10", "r11", \
1710 "r12", "r13", "sp", "pc" };
1712 if (regno >= 0 && regno < NUM_GENREGS)
1714 /* General register. */
1715 return cris_genreg_names[regno];
1717 else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (gdbarch))
1719 return cris_special_register_name (gdbarch, regno);
1723 /* Invalid register. */
1729 crisv32_register_name (struct gdbarch *gdbarch, int regno)
1731 static char *crisv32_genreg_names[] =
1732 { "r0", "r1", "r2", "r3", \
1733 "r4", "r5", "r6", "r7", \
1734 "r8", "r9", "r10", "r11", \
1735 "r12", "r13", "sp", "acr"
1738 static char *crisv32_sreg_names[] =
1739 { "s0", "s1", "s2", "s3", \
1740 "s4", "s5", "s6", "s7", \
1741 "s8", "s9", "s10", "s11", \
1742 "s12", "s13", "s14", "s15"
1745 if (regno >= 0 && regno < NUM_GENREGS)
1747 /* General register. */
1748 return crisv32_genreg_names[regno];
1750 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1752 return cris_special_register_name (gdbarch, regno);
1754 else if (regno == gdbarch_pc_regnum (gdbarch))
1758 else if (regno >= S0_REGNUM && regno <= S15_REGNUM)
1760 return crisv32_sreg_names[regno - S0_REGNUM];
1764 /* Invalid register. */
1769 /* Convert DWARF register number REG to the appropriate register
1770 number used by GDB. */
1773 cris_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1775 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1776 numbering, MOF is 18).
1777 Adapted from gcc/config/cris/cris.h. */
1778 static int cris_dwarf_regmap[] = {
1790 if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap))
1791 regnum = cris_dwarf_regmap[reg];
1794 warning (_("Unmapped DWARF Register #%d encountered."), reg);
1799 /* DWARF-2 frame support. */
1802 cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1803 struct dwarf2_frame_state_reg *reg,
1804 struct frame_info *this_frame)
1806 /* The return address column. */
1807 if (regnum == gdbarch_pc_regnum (gdbarch))
1808 reg->how = DWARF2_FRAME_REG_RA;
1810 /* The call frame address. */
1811 else if (regnum == gdbarch_sp_regnum (gdbarch))
1812 reg->how = DWARF2_FRAME_REG_CFA;
1815 /* Extract from an array regbuf containing the raw register state a function
1816 return value of type type, and copy that, in virtual format, into
1819 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1822 cris_extract_return_value (struct type *type, struct regcache *regcache,
1825 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1826 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1828 int len = TYPE_LENGTH (type);
1832 /* Get the return value from R10. */
1833 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1834 store_unsigned_integer (valbuf, len, byte_order, val);
1838 /* Get the return value from R10 and R11. */
1839 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1840 store_unsigned_integer (valbuf, 4, byte_order, val);
1841 regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val);
1842 store_unsigned_integer (valbuf + 4, len - 4, byte_order, val);
1845 error (_("cris_extract_return_value: type length too large"));
1848 /* Handle the CRIS return value convention. */
1850 static enum return_value_convention
1851 cris_return_value (struct gdbarch *gdbarch, struct value *function,
1852 struct type *type, struct regcache *regcache,
1853 gdb_byte *readbuf, const gdb_byte *writebuf)
1855 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1856 || TYPE_CODE (type) == TYPE_CODE_UNION
1857 || TYPE_LENGTH (type) > 8)
1858 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1859 goes on the stack. */
1860 return RETURN_VALUE_STRUCT_CONVENTION;
1863 cris_extract_return_value (type, regcache, readbuf);
1865 cris_store_return_value (type, regcache, writebuf);
1867 return RETURN_VALUE_REGISTER_CONVENTION;
1870 /* Calculates a value that measures how good inst_args constraints an
1871 instruction. It stems from cris_constraint, found in cris-dis.c. */
1874 constraint (unsigned int insn, const char *inst_args,
1875 inst_env_type *inst_env)
1880 const gdb_byte *s = (const gdb_byte *) inst_args;
1886 if ((insn & 0x30) == 0x30)
1891 /* A prefix operand. */
1892 if (inst_env->prefix_found)
1898 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1899 valid "push" size. In case of special register, it may be != 4. */
1900 if (inst_env->prefix_found)
1906 retval = (((insn >> 0xC) & 0xF) == (insn & 0xF));
1914 tmp = (insn >> 0xC) & 0xF;
1916 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1918 /* Since we match four bits, we will give a value of
1919 4 - 1 = 3 in a match. If there is a corresponding
1920 exact match of a special register in another pattern, it
1921 will get a value of 4, which will be higher. This should
1922 be correct in that an exact pattern would match better that
1924 Note that there is a reason for not returning zero; the
1925 pattern for "clear" is partly matched in the bit-pattern
1926 (the two lower bits must be zero), while the bit-pattern
1927 for a move from a special register is matched in the
1928 register constraint.
1929 This also means we will will have a race condition if
1930 there is a partly match in three bits in the bit pattern. */
1931 if (tmp == cris_spec_regs[i].number)
1938 if (cris_spec_regs[i].name == NULL)
1945 /* Returns the number of bits set in the variable value. */
1948 number_of_bits (unsigned int value)
1950 int number_of_bits = 0;
1954 number_of_bits += 1;
1955 value &= (value - 1);
1957 return number_of_bits;
1960 /* Finds the address that should contain the single step breakpoint(s).
1961 It stems from code in cris-dis.c. */
1964 find_cris_op (unsigned short insn, inst_env_type *inst_env)
1967 int max_level_of_match = -1;
1968 int max_matched = -1;
1971 for (i = 0; cris_opcodes[i].name != NULL; i++)
1973 if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match)
1974 && ((cris_opcodes[i].lose & insn) == 0)
1975 /* Only CRISv10 instructions, please. */
1976 && (cris_opcodes[i].applicable_version != cris_ver_v32p))
1978 level_of_match = constraint (insn, cris_opcodes[i].args, inst_env);
1979 if (level_of_match >= 0)
1982 number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose);
1983 if (level_of_match > max_level_of_match)
1986 max_level_of_match = level_of_match;
1987 if (level_of_match == 16)
1989 /* All bits matched, cannot find better. */
1999 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
2000 actually an internal error. */
2003 find_step_target (struct frame_info *frame, inst_env_type *inst_env)
2007 unsigned short insn;
2008 struct gdbarch *gdbarch = get_frame_arch (frame);
2009 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2011 /* Create a local register image and set the initial state. */
2012 for (i = 0; i < NUM_GENREGS; i++)
2015 (unsigned long) get_frame_register_unsigned (frame, i);
2017 offset = NUM_GENREGS;
2018 for (i = 0; i < NUM_SPECREGS; i++)
2021 (unsigned long) get_frame_register_unsigned (frame, offset + i);
2023 inst_env->branch_found = 0;
2024 inst_env->slot_needed = 0;
2025 inst_env->delay_slot_pc_active = 0;
2026 inst_env->prefix_found = 0;
2027 inst_env->invalid = 0;
2028 inst_env->xflag_found = 0;
2029 inst_env->disable_interrupt = 0;
2030 inst_env->byte_order = byte_order;
2032 /* Look for a step target. */
2035 /* Read an instruction from the client. */
2036 insn = read_memory_unsigned_integer
2037 (inst_env->reg[gdbarch_pc_regnum (gdbarch)], 2, byte_order);
2039 /* If the instruction is not in a delay slot the new content of the
2040 PC is [PC] + 2. If the instruction is in a delay slot it is not
2041 that simple. Since a instruction in a delay slot cannot change
2042 the content of the PC, it does not matter what value PC will have.
2043 Just make sure it is a valid instruction. */
2044 if (!inst_env->delay_slot_pc_active)
2046 inst_env->reg[gdbarch_pc_regnum (gdbarch)] += 2;
2050 inst_env->delay_slot_pc_active = 0;
2051 inst_env->reg[gdbarch_pc_regnum (gdbarch)]
2052 = inst_env->delay_slot_pc;
2054 /* Analyse the present instruction. */
2055 i = find_cris_op (insn, inst_env);
2058 inst_env->invalid = 1;
2062 cris_gdb_func (gdbarch, cris_opcodes[i].op, insn, inst_env);
2064 } while (!inst_env->invalid
2065 && (inst_env->prefix_found || inst_env->xflag_found
2066 || inst_env->slot_needed));
2070 /* There is no hardware single-step support. The function find_step_target
2071 digs through the opcodes in order to find all possible targets.
2072 Either one ordinary target or two targets for branches may be found. */
2075 cris_software_single_step (struct frame_info *frame)
2077 struct gdbarch *gdbarch = get_frame_arch (frame);
2078 struct address_space *aspace = get_frame_address_space (frame);
2079 inst_env_type inst_env;
2081 /* Analyse the present instruction environment and insert
2083 int status = find_step_target (frame, &inst_env);
2086 /* Could not find a target. Things are likely to go downhill
2088 warning (_("CRIS software single step could not find a step target."));
2092 /* Insert at most two breakpoints. One for the next PC content
2093 and possibly another one for a branch, jump, etc. */
2095 = (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (gdbarch)];
2096 insert_single_step_breakpoint (gdbarch, aspace, next_pc);
2097 if (inst_env.branch_found
2098 && (CORE_ADDR) inst_env.branch_break_address != next_pc)
2100 CORE_ADDR branch_target_address
2101 = (CORE_ADDR) inst_env.branch_break_address;
2102 insert_single_step_breakpoint (gdbarch,
2103 aspace, branch_target_address);
2110 /* Calculates the prefix value for quick offset addressing mode. */
2113 quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2115 /* It's invalid to be in a delay slot. You can't have a prefix to this
2116 instruction (not 100% sure). */
2117 if (inst_env->slot_needed || inst_env->prefix_found)
2119 inst_env->invalid = 1;
2123 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2124 inst_env->prefix_value += cris_get_bdap_quick_offset (inst);
2126 /* A prefix doesn't change the xflag_found. But the rest of the flags
2128 inst_env->slot_needed = 0;
2129 inst_env->prefix_found = 1;
2132 /* Updates the autoincrement register. The size of the increment is derived
2133 from the size of the operation. The PC is always kept aligned on even
2137 process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env)
2139 if (size == INST_BYTE_SIZE)
2141 inst_env->reg[cris_get_operand1 (inst)] += 1;
2143 /* The PC must be word aligned, so increase the PC with one
2144 word even if the size is byte. */
2145 if (cris_get_operand1 (inst) == REG_PC)
2147 inst_env->reg[REG_PC] += 1;
2150 else if (size == INST_WORD_SIZE)
2152 inst_env->reg[cris_get_operand1 (inst)] += 2;
2154 else if (size == INST_DWORD_SIZE)
2156 inst_env->reg[cris_get_operand1 (inst)] += 4;
2161 inst_env->invalid = 1;
2165 /* Just a forward declaration. */
2167 static unsigned long get_data_from_address (unsigned short *inst,
2169 enum bfd_endian byte_order);
2171 /* Calculates the prefix value for the general case of offset addressing
2175 bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2177 /* It's invalid to be in a delay slot. */
2178 if (inst_env->slot_needed || inst_env->prefix_found)
2180 inst_env->invalid = 1;
2184 /* The calculation of prefix_value used to be after process_autoincrement,
2185 but that fails for an instruction such as jsr [$r0+12] which is encoded
2186 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
2187 mustn't be incremented until we have read it and what it points at. */
2188 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2190 /* The offset is an indirection of the contents of the operand1 register. */
2191 inst_env->prefix_value +=
2192 get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)],
2193 inst_env->byte_order);
2195 if (cris_get_mode (inst) == AUTOINC_MODE)
2197 process_autoincrement (cris_get_size (inst), inst, inst_env);
2200 /* A prefix doesn't change the xflag_found. But the rest of the flags
2202 inst_env->slot_needed = 0;
2203 inst_env->prefix_found = 1;
2206 /* Calculates the prefix value for the index addressing mode. */
2209 biap_prefix (unsigned short inst, inst_env_type *inst_env)
2211 /* It's invalid to be in a delay slot. I can't see that it's possible to
2212 have a prefix to this instruction. So I will treat this as invalid. */
2213 if (inst_env->slot_needed || inst_env->prefix_found)
2215 inst_env->invalid = 1;
2219 inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)];
2221 /* The offset is the operand2 value shifted the size of the instruction
2223 inst_env->prefix_value +=
2224 inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst);
2226 /* If the PC is operand1 (base) the address used is the address after
2227 the main instruction, i.e. address + 2 (the PC is already compensated
2228 for the prefix operation). */
2229 if (cris_get_operand1 (inst) == REG_PC)
2231 inst_env->prefix_value += 2;
2234 /* A prefix doesn't change the xflag_found. But the rest of the flags
2236 inst_env->slot_needed = 0;
2237 inst_env->xflag_found = 0;
2238 inst_env->prefix_found = 1;
2241 /* Calculates the prefix value for the double indirect addressing mode. */
2244 dip_prefix (unsigned short inst, inst_env_type *inst_env)
2249 /* It's invalid to be in a delay slot. */
2250 if (inst_env->slot_needed || inst_env->prefix_found)
2252 inst_env->invalid = 1;
2256 /* The prefix value is one dereference of the contents of the operand1
2258 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2259 inst_env->prefix_value
2260 = read_memory_unsigned_integer (address, 4, inst_env->byte_order);
2262 /* Check if the mode is autoincrement. */
2263 if (cris_get_mode (inst) == AUTOINC_MODE)
2265 inst_env->reg[cris_get_operand1 (inst)] += 4;
2268 /* A prefix doesn't change the xflag_found. But the rest of the flags
2270 inst_env->slot_needed = 0;
2271 inst_env->xflag_found = 0;
2272 inst_env->prefix_found = 1;
2275 /* Finds the destination for a branch with 8-bits offset. */
2278 eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2283 /* If we have a prefix or are in a delay slot it's bad. */
2284 if (inst_env->slot_needed || inst_env->prefix_found)
2286 inst_env->invalid = 1;
2290 /* We have a branch, find out where the branch will land. */
2291 offset = cris_get_branch_short_offset (inst);
2293 /* Check if the offset is signed. */
2294 if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK)
2299 /* The offset ends with the sign bit, set it to zero. The address
2300 should always be word aligned. */
2301 offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK;
2303 inst_env->branch_found = 1;
2304 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2306 inst_env->slot_needed = 1;
2307 inst_env->prefix_found = 0;
2308 inst_env->xflag_found = 0;
2309 inst_env->disable_interrupt = 1;
2312 /* Finds the destination for a branch with 16-bits offset. */
2315 sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2319 /* If we have a prefix or is in a delay slot it's bad. */
2320 if (inst_env->slot_needed || inst_env->prefix_found)
2322 inst_env->invalid = 1;
2326 /* We have a branch, find out the offset for the branch. */
2327 offset = read_memory_integer (inst_env->reg[REG_PC], 2,
2328 inst_env->byte_order);
2330 /* The instruction is one word longer than normal, so add one word
2332 inst_env->reg[REG_PC] += 2;
2334 inst_env->branch_found = 1;
2335 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2338 inst_env->slot_needed = 1;
2339 inst_env->prefix_found = 0;
2340 inst_env->xflag_found = 0;
2341 inst_env->disable_interrupt = 1;
2344 /* Handles the ABS instruction. */
2347 abs_op (unsigned short inst, inst_env_type *inst_env)
2352 /* ABS can't have a prefix, so it's bad if it does. */
2353 if (inst_env->prefix_found)
2355 inst_env->invalid = 1;
2359 /* Check if the operation affects the PC. */
2360 if (cris_get_operand2 (inst) == REG_PC)
2363 /* It's invalid to change to the PC if we are in a delay slot. */
2364 if (inst_env->slot_needed)
2366 inst_env->invalid = 1;
2370 value = (long) inst_env->reg[REG_PC];
2372 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
2373 if (value != SIGNED_DWORD_MASK)
2376 inst_env->reg[REG_PC] = (long) value;
2380 inst_env->slot_needed = 0;
2381 inst_env->prefix_found = 0;
2382 inst_env->xflag_found = 0;
2383 inst_env->disable_interrupt = 0;
2386 /* Handles the ADDI instruction. */
2389 addi_op (unsigned short inst, inst_env_type *inst_env)
2391 /* It's invalid to have the PC as base register. And ADDI can't have
2393 if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC))
2395 inst_env->invalid = 1;
2399 inst_env->slot_needed = 0;
2400 inst_env->prefix_found = 0;
2401 inst_env->xflag_found = 0;
2402 inst_env->disable_interrupt = 0;
2405 /* Handles the ASR instruction. */
2408 asr_op (unsigned short inst, inst_env_type *inst_env)
2411 unsigned long value;
2412 unsigned long signed_extend_mask = 0;
2414 /* ASR can't have a prefix, so check that it doesn't. */
2415 if (inst_env->prefix_found)
2417 inst_env->invalid = 1;
2421 /* Check if the PC is the target register. */
2422 if (cris_get_operand2 (inst) == REG_PC)
2424 /* It's invalid to change the PC in a delay slot. */
2425 if (inst_env->slot_needed)
2427 inst_env->invalid = 1;
2430 /* Get the number of bits to shift. */
2432 = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]);
2433 value = inst_env->reg[REG_PC];
2435 /* Find out how many bits the operation should apply to. */
2436 if (cris_get_size (inst) == INST_BYTE_SIZE)
2438 if (value & SIGNED_BYTE_MASK)
2440 signed_extend_mask = 0xFF;
2441 signed_extend_mask = signed_extend_mask >> shift_steps;
2442 signed_extend_mask = ~signed_extend_mask;
2444 value = value >> shift_steps;
2445 value |= signed_extend_mask;
2447 inst_env->reg[REG_PC] &= 0xFFFFFF00;
2448 inst_env->reg[REG_PC] |= value;
2450 else if (cris_get_size (inst) == INST_WORD_SIZE)
2452 if (value & SIGNED_WORD_MASK)
2454 signed_extend_mask = 0xFFFF;
2455 signed_extend_mask = signed_extend_mask >> shift_steps;
2456 signed_extend_mask = ~signed_extend_mask;
2458 value = value >> shift_steps;
2459 value |= signed_extend_mask;
2461 inst_env->reg[REG_PC] &= 0xFFFF0000;
2462 inst_env->reg[REG_PC] |= value;
2464 else if (cris_get_size (inst) == INST_DWORD_SIZE)
2466 if (value & SIGNED_DWORD_MASK)
2468 signed_extend_mask = 0xFFFFFFFF;
2469 signed_extend_mask = signed_extend_mask >> shift_steps;
2470 signed_extend_mask = ~signed_extend_mask;
2472 value = value >> shift_steps;
2473 value |= signed_extend_mask;
2474 inst_env->reg[REG_PC] = value;
2477 inst_env->slot_needed = 0;
2478 inst_env->prefix_found = 0;
2479 inst_env->xflag_found = 0;
2480 inst_env->disable_interrupt = 0;
2483 /* Handles the ASRQ instruction. */
2486 asrq_op (unsigned short inst, inst_env_type *inst_env)
2490 unsigned long value;
2491 unsigned long signed_extend_mask = 0;
2493 /* ASRQ can't have a prefix, so check that it doesn't. */
2494 if (inst_env->prefix_found)
2496 inst_env->invalid = 1;
2500 /* Check if the PC is the target register. */
2501 if (cris_get_operand2 (inst) == REG_PC)
2504 /* It's invalid to change the PC in a delay slot. */
2505 if (inst_env->slot_needed)
2507 inst_env->invalid = 1;
2510 /* The shift size is given as a 5 bit quick value, i.e. we don't
2511 want the sign bit of the quick value. */
2512 shift_steps = cris_get_asr_shift_steps (inst);
2513 value = inst_env->reg[REG_PC];
2514 if (value & SIGNED_DWORD_MASK)
2516 signed_extend_mask = 0xFFFFFFFF;
2517 signed_extend_mask = signed_extend_mask >> shift_steps;
2518 signed_extend_mask = ~signed_extend_mask;
2520 value = value >> shift_steps;
2521 value |= signed_extend_mask;
2522 inst_env->reg[REG_PC] = value;
2524 inst_env->slot_needed = 0;
2525 inst_env->prefix_found = 0;
2526 inst_env->xflag_found = 0;
2527 inst_env->disable_interrupt = 0;
2530 /* Handles the AX, EI and SETF instruction. */
2533 ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env)
2535 if (inst_env->prefix_found)
2537 inst_env->invalid = 1;
2540 /* Check if the instruction is setting the X flag. */
2541 if (cris_is_xflag_bit_on (inst))
2543 inst_env->xflag_found = 1;
2547 inst_env->xflag_found = 0;
2549 inst_env->slot_needed = 0;
2550 inst_env->prefix_found = 0;
2551 inst_env->disable_interrupt = 1;
2554 /* Checks if the instruction is in assign mode. If so, it updates the assign
2555 register. Note that check_assign assumes that the caller has checked that
2556 there is a prefix to this instruction. The mode check depends on this. */
2559 check_assign (unsigned short inst, inst_env_type *inst_env)
2561 /* Check if it's an assign addressing mode. */
2562 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2564 /* Assign the prefix value to operand 1. */
2565 inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value;
2569 /* Handles the 2-operand BOUND instruction. */
2572 two_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2574 /* It's invalid to have the PC as the index operand. */
2575 if (cris_get_operand2 (inst) == REG_PC)
2577 inst_env->invalid = 1;
2580 /* Check if we have a prefix. */
2581 if (inst_env->prefix_found)
2583 check_assign (inst, inst_env);
2585 /* Check if this is an autoincrement mode. */
2586 else if (cris_get_mode (inst) == AUTOINC_MODE)
2588 /* It's invalid to change the PC in a delay slot. */
2589 if (inst_env->slot_needed)
2591 inst_env->invalid = 1;
2594 process_autoincrement (cris_get_size (inst), inst, inst_env);
2596 inst_env->slot_needed = 0;
2597 inst_env->prefix_found = 0;
2598 inst_env->xflag_found = 0;
2599 inst_env->disable_interrupt = 0;
2602 /* Handles the 3-operand BOUND instruction. */
2605 three_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2607 /* It's an error if we haven't got a prefix. And it's also an error
2608 if the PC is the destination register. */
2609 if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC))
2611 inst_env->invalid = 1;
2614 inst_env->slot_needed = 0;
2615 inst_env->prefix_found = 0;
2616 inst_env->xflag_found = 0;
2617 inst_env->disable_interrupt = 0;
2620 /* Clears the status flags in inst_env. */
2623 btst_nop_op (unsigned short inst, inst_env_type *inst_env)
2625 /* It's an error if we have got a prefix. */
2626 if (inst_env->prefix_found)
2628 inst_env->invalid = 1;
2632 inst_env->slot_needed = 0;
2633 inst_env->prefix_found = 0;
2634 inst_env->xflag_found = 0;
2635 inst_env->disable_interrupt = 0;
2638 /* Clears the status flags in inst_env. */
2641 clearf_di_op (unsigned short inst, inst_env_type *inst_env)
2643 /* It's an error if we have got a prefix. */
2644 if (inst_env->prefix_found)
2646 inst_env->invalid = 1;
2650 inst_env->slot_needed = 0;
2651 inst_env->prefix_found = 0;
2652 inst_env->xflag_found = 0;
2653 inst_env->disable_interrupt = 1;
2656 /* Handles the CLEAR instruction if it's in register mode. */
2659 reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env)
2661 /* Check if the target is the PC. */
2662 if (cris_get_operand2 (inst) == REG_PC)
2664 /* The instruction will clear the instruction's size bits. */
2665 int clear_size = cris_get_clear_size (inst);
2666 if (clear_size == INST_BYTE_SIZE)
2668 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00;
2670 if (clear_size == INST_WORD_SIZE)
2672 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000;
2674 if (clear_size == INST_DWORD_SIZE)
2676 inst_env->delay_slot_pc = 0x0;
2678 /* The jump will be delayed with one delay slot. So we need a delay
2680 inst_env->slot_needed = 1;
2681 inst_env->delay_slot_pc_active = 1;
2685 /* The PC will not change => no delay slot. */
2686 inst_env->slot_needed = 0;
2688 inst_env->prefix_found = 0;
2689 inst_env->xflag_found = 0;
2690 inst_env->disable_interrupt = 0;
2693 /* Handles the TEST instruction if it's in register mode. */
2696 reg_mode_test_op (unsigned short inst, inst_env_type *inst_env)
2698 /* It's an error if we have got a prefix. */
2699 if (inst_env->prefix_found)
2701 inst_env->invalid = 1;
2704 inst_env->slot_needed = 0;
2705 inst_env->prefix_found = 0;
2706 inst_env->xflag_found = 0;
2707 inst_env->disable_interrupt = 0;
2711 /* Handles the CLEAR and TEST instruction if the instruction isn't
2712 in register mode. */
2715 none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env)
2717 /* Check if we are in a prefix mode. */
2718 if (inst_env->prefix_found)
2720 /* The only way the PC can change is if this instruction is in
2721 assign addressing mode. */
2722 check_assign (inst, inst_env);
2724 /* Indirect mode can't change the PC so just check if the mode is
2726 else if (cris_get_mode (inst) == AUTOINC_MODE)
2728 process_autoincrement (cris_get_size (inst), inst, inst_env);
2730 inst_env->slot_needed = 0;
2731 inst_env->prefix_found = 0;
2732 inst_env->xflag_found = 0;
2733 inst_env->disable_interrupt = 0;
2736 /* Checks that the PC isn't the destination register or the instructions has
2740 dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env)
2742 /* It's invalid to have the PC as the destination. The instruction can't
2744 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2746 inst_env->invalid = 1;
2750 inst_env->slot_needed = 0;
2751 inst_env->prefix_found = 0;
2752 inst_env->xflag_found = 0;
2753 inst_env->disable_interrupt = 0;
2756 /* Checks that the instruction doesn't have a prefix. */
2759 break_op (unsigned short inst, inst_env_type *inst_env)
2761 /* The instruction can't have a prefix. */
2762 if (inst_env->prefix_found)
2764 inst_env->invalid = 1;
2768 inst_env->slot_needed = 0;
2769 inst_env->prefix_found = 0;
2770 inst_env->xflag_found = 0;
2771 inst_env->disable_interrupt = 1;
2774 /* Checks that the PC isn't the destination register and that the instruction
2775 doesn't have a prefix. */
2778 scc_op (unsigned short inst, inst_env_type *inst_env)
2780 /* It's invalid to have the PC as the destination. The instruction can't
2782 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2784 inst_env->invalid = 1;
2788 inst_env->slot_needed = 0;
2789 inst_env->prefix_found = 0;
2790 inst_env->xflag_found = 0;
2791 inst_env->disable_interrupt = 1;
2794 /* Handles the register mode JUMP instruction. */
2797 reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2799 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2800 you can't have a prefix. */
2801 if ((inst_env->slot_needed) || (inst_env->prefix_found))
2803 inst_env->invalid = 1;
2807 /* Just change the PC. */
2808 inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)];
2809 inst_env->slot_needed = 0;
2810 inst_env->prefix_found = 0;
2811 inst_env->xflag_found = 0;
2812 inst_env->disable_interrupt = 1;
2815 /* Handles the JUMP instruction for all modes except register. */
2818 none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2820 unsigned long newpc;
2823 /* It's invalid to do a JUMP in a delay slot. */
2824 if (inst_env->slot_needed)
2826 inst_env->invalid = 1;
2830 /* Check if we have a prefix. */
2831 if (inst_env->prefix_found)
2833 check_assign (inst, inst_env);
2835 /* Get the new value for the PC. */
2837 read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value,
2838 4, inst_env->byte_order);
2842 /* Get the new value for the PC. */
2843 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2844 newpc = read_memory_unsigned_integer (address,
2845 4, inst_env->byte_order);
2847 /* Check if we should increment a register. */
2848 if (cris_get_mode (inst) == AUTOINC_MODE)
2850 inst_env->reg[cris_get_operand1 (inst)] += 4;
2853 inst_env->reg[REG_PC] = newpc;
2855 inst_env->slot_needed = 0;
2856 inst_env->prefix_found = 0;
2857 inst_env->xflag_found = 0;
2858 inst_env->disable_interrupt = 1;
2861 /* Handles moves to special registers (aka P-register) for all modes. */
2864 move_to_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2865 inst_env_type *inst_env)
2867 if (inst_env->prefix_found)
2869 /* The instruction has a prefix that means we are only interested if
2870 the instruction is in assign mode. */
2871 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2873 /* The prefix handles the problem if we are in a delay slot. */
2874 if (cris_get_operand1 (inst) == REG_PC)
2876 /* Just take care of the assign. */
2877 check_assign (inst, inst_env);
2881 else if (cris_get_mode (inst) == AUTOINC_MODE)
2883 /* The instruction doesn't have a prefix, the only case left that we
2884 are interested in is the autoincrement mode. */
2885 if (cris_get_operand1 (inst) == REG_PC)
2887 /* If the PC is to be incremented it's invalid to be in a
2889 if (inst_env->slot_needed)
2891 inst_env->invalid = 1;
2895 /* The increment depends on the size of the special register. */
2896 if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
2898 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2900 else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
2902 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2906 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2910 inst_env->slot_needed = 0;
2911 inst_env->prefix_found = 0;
2912 inst_env->xflag_found = 0;
2913 inst_env->disable_interrupt = 1;
2916 /* Handles moves from special registers (aka P-register) for all modes
2920 none_reg_mode_move_from_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2921 inst_env_type *inst_env)
2923 if (inst_env->prefix_found)
2925 /* The instruction has a prefix that means we are only interested if
2926 the instruction is in assign mode. */
2927 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2929 /* The prefix handles the problem if we are in a delay slot. */
2930 if (cris_get_operand1 (inst) == REG_PC)
2932 /* Just take care of the assign. */
2933 check_assign (inst, inst_env);
2937 /* The instruction doesn't have a prefix, the only case left that we
2938 are interested in is the autoincrement mode. */
2939 else if (cris_get_mode (inst) == AUTOINC_MODE)
2941 if (cris_get_operand1 (inst) == REG_PC)
2943 /* If the PC is to be incremented it's invalid to be in a
2945 if (inst_env->slot_needed)
2947 inst_env->invalid = 1;
2951 /* The increment depends on the size of the special register. */
2952 if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
2954 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2956 else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
2958 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2962 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2966 inst_env->slot_needed = 0;
2967 inst_env->prefix_found = 0;
2968 inst_env->xflag_found = 0;
2969 inst_env->disable_interrupt = 1;
2972 /* Handles moves from special registers (aka P-register) when the mode
2976 reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env)
2978 /* Register mode move from special register can't have a prefix. */
2979 if (inst_env->prefix_found)
2981 inst_env->invalid = 1;
2985 if (cris_get_operand1 (inst) == REG_PC)
2987 /* It's invalid to change the PC in a delay slot. */
2988 if (inst_env->slot_needed)
2990 inst_env->invalid = 1;
2993 /* The destination is the PC, the jump will have a delay slot. */
2994 inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)];
2995 inst_env->slot_needed = 1;
2996 inst_env->delay_slot_pc_active = 1;
3000 /* If the destination isn't PC, there will be no jump. */
3001 inst_env->slot_needed = 0;
3003 inst_env->prefix_found = 0;
3004 inst_env->xflag_found = 0;
3005 inst_env->disable_interrupt = 1;
3008 /* Handles the MOVEM from memory to general register instruction. */
3011 move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env)
3013 if (inst_env->prefix_found)
3015 /* The prefix handles the problem if we are in a delay slot. Is the
3016 MOVEM instruction going to change the PC? */
3017 if (cris_get_operand2 (inst) >= REG_PC)
3019 inst_env->reg[REG_PC] =
3020 read_memory_unsigned_integer (inst_env->prefix_value,
3021 4, inst_env->byte_order);
3023 /* The assign value is the value after the increment. Normally, the
3024 assign value is the value before the increment. */
3025 if ((cris_get_operand1 (inst) == REG_PC)
3026 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3028 inst_env->reg[REG_PC] = inst_env->prefix_value;
3029 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3034 /* Is the MOVEM instruction going to change the PC? */
3035 if (cris_get_operand2 (inst) == REG_PC)
3037 /* It's invalid to change the PC in a delay slot. */
3038 if (inst_env->slot_needed)
3040 inst_env->invalid = 1;
3043 inst_env->reg[REG_PC] =
3044 read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)],
3045 4, inst_env->byte_order);
3047 /* The increment is not depending on the size, instead it's depending
3048 on the number of registers loaded from memory. */
3049 if ((cris_get_operand1 (inst) == REG_PC)
3050 && (cris_get_mode (inst) == AUTOINC_MODE))
3052 /* It's invalid to change the PC in a delay slot. */
3053 if (inst_env->slot_needed)
3055 inst_env->invalid = 1;
3058 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3061 inst_env->slot_needed = 0;
3062 inst_env->prefix_found = 0;
3063 inst_env->xflag_found = 0;
3064 inst_env->disable_interrupt = 0;
3067 /* Handles the MOVEM to memory from general register instruction. */
3070 move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env)
3072 if (inst_env->prefix_found)
3074 /* The assign value is the value after the increment. Normally, the
3075 assign value is the value before the increment. */
3076 if ((cris_get_operand1 (inst) == REG_PC)
3077 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3079 /* The prefix handles the problem if we are in a delay slot. */
3080 inst_env->reg[REG_PC] = inst_env->prefix_value;
3081 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3086 /* The increment is not depending on the size, instead it's depending
3087 on the number of registers loaded to memory. */
3088 if ((cris_get_operand1 (inst) == REG_PC)
3089 && (cris_get_mode (inst) == AUTOINC_MODE))
3091 /* It's invalid to change the PC in a delay slot. */
3092 if (inst_env->slot_needed)
3094 inst_env->invalid = 1;
3097 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3100 inst_env->slot_needed = 0;
3101 inst_env->prefix_found = 0;
3102 inst_env->xflag_found = 0;
3103 inst_env->disable_interrupt = 0;
3106 /* Handles the intructions that's not yet implemented, by setting
3107 inst_env->invalid to true. */
3110 not_implemented_op (unsigned short inst, inst_env_type *inst_env)
3112 inst_env->invalid = 1;
3115 /* Handles the XOR instruction. */
3118 xor_op (unsigned short inst, inst_env_type *inst_env)
3120 /* XOR can't have a prefix. */
3121 if (inst_env->prefix_found)
3123 inst_env->invalid = 1;
3127 /* Check if the PC is the target. */
3128 if (cris_get_operand2 (inst) == REG_PC)
3130 /* It's invalid to change the PC in a delay slot. */
3131 if (inst_env->slot_needed)
3133 inst_env->invalid = 1;
3136 inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)];
3138 inst_env->slot_needed = 0;
3139 inst_env->prefix_found = 0;
3140 inst_env->xflag_found = 0;
3141 inst_env->disable_interrupt = 0;
3144 /* Handles the MULS instruction. */
3147 muls_op (unsigned short inst, inst_env_type *inst_env)
3149 /* MULS/U can't have a prefix. */
3150 if (inst_env->prefix_found)
3152 inst_env->invalid = 1;
3156 /* Consider it invalid if the PC is the target. */
3157 if (cris_get_operand2 (inst) == REG_PC)
3159 inst_env->invalid = 1;
3162 inst_env->slot_needed = 0;
3163 inst_env->prefix_found = 0;
3164 inst_env->xflag_found = 0;
3165 inst_env->disable_interrupt = 0;
3168 /* Handles the MULU instruction. */
3171 mulu_op (unsigned short inst, inst_env_type *inst_env)
3173 /* MULS/U can't have a prefix. */
3174 if (inst_env->prefix_found)
3176 inst_env->invalid = 1;
3180 /* Consider it invalid if the PC is the target. */
3181 if (cris_get_operand2 (inst) == REG_PC)
3183 inst_env->invalid = 1;
3186 inst_env->slot_needed = 0;
3187 inst_env->prefix_found = 0;
3188 inst_env->xflag_found = 0;
3189 inst_env->disable_interrupt = 0;
3192 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
3193 The MOVE instruction is the move from source to register. */
3196 add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env,
3197 unsigned long source1, unsigned long source2)
3199 unsigned long pc_mask;
3200 unsigned long operation_mask;
3202 /* Find out how many bits the operation should apply to. */
3203 if (cris_get_size (inst) == INST_BYTE_SIZE)
3205 pc_mask = 0xFFFFFF00;
3206 operation_mask = 0xFF;
3208 else if (cris_get_size (inst) == INST_WORD_SIZE)
3210 pc_mask = 0xFFFF0000;
3211 operation_mask = 0xFFFF;
3213 else if (cris_get_size (inst) == INST_DWORD_SIZE)
3216 operation_mask = 0xFFFFFFFF;
3220 /* The size is out of range. */
3221 inst_env->invalid = 1;
3225 /* The instruction just works on uw_operation_mask bits. */
3226 source2 &= operation_mask;
3227 source1 &= operation_mask;
3229 /* Now calculate the result. The opcode's 3 first bits separates
3230 the different actions. */
3231 switch (cris_get_opcode (inst) & 7)
3241 case 2: /* subtract */
3245 case 3: /* compare */
3257 inst_env->invalid = 1;
3263 /* Make sure that the result doesn't contain more than the instruction
3265 source2 &= operation_mask;
3267 /* Calculate the new breakpoint address. */
3268 inst_env->reg[REG_PC] &= pc_mask;
3269 inst_env->reg[REG_PC] |= source1;
3273 /* Extends the value from either byte or word size to a dword. If the mode
3274 is zero extend then the value is extended with zero. If instead the mode
3275 is signed extend the sign bit of the value is taken into consideration. */
3277 static unsigned long
3278 do_sign_or_zero_extend (unsigned long value, unsigned short *inst)
3280 /* The size can be either byte or word, check which one it is.
3281 Don't check the highest bit, it's indicating if it's a zero
3283 if (cris_get_size (*inst) & INST_WORD_SIZE)
3288 /* Check if the instruction is signed extend. If so, check if value has
3290 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK))
3292 value |= SIGNED_WORD_EXTEND_MASK;
3300 /* Check if the instruction is signed extend. If so, check if value has
3302 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK))
3304 value |= SIGNED_BYTE_EXTEND_MASK;
3307 /* The size should now be dword. */
3308 cris_set_size_to_dword (inst);
3312 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3313 instruction. The MOVE instruction is the move from source to register. */
3316 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3317 inst_env_type *inst_env)
3319 unsigned long operand1;
3320 unsigned long operand2;
3322 /* It's invalid to have a prefix to the instruction. This is a register
3323 mode instruction and can't have a prefix. */
3324 if (inst_env->prefix_found)
3326 inst_env->invalid = 1;
3329 /* Check if the instruction has PC as its target. */
3330 if (cris_get_operand2 (inst) == REG_PC)
3332 if (inst_env->slot_needed)
3334 inst_env->invalid = 1;
3337 /* The instruction has the PC as its target register. */
3338 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3339 operand2 = inst_env->reg[REG_PC];
3341 /* Check if it's a extend, signed or zero instruction. */
3342 if (cris_get_opcode (inst) < 4)
3344 operand1 = do_sign_or_zero_extend (operand1, &inst);
3346 /* Calculate the PC value after the instruction, i.e. where the
3347 breakpoint should be. The order of the udw_operands is vital. */
3348 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3350 inst_env->slot_needed = 0;
3351 inst_env->prefix_found = 0;
3352 inst_env->xflag_found = 0;
3353 inst_env->disable_interrupt = 0;
3356 /* Returns the data contained at address. The size of the data is derived from
3357 the size of the operation. If the instruction is a zero or signed
3358 extend instruction, the size field is changed in instruction. */
3360 static unsigned long
3361 get_data_from_address (unsigned short *inst, CORE_ADDR address,
3362 enum bfd_endian byte_order)
3364 int size = cris_get_size (*inst);
3365 unsigned long value;
3367 /* If it's an extend instruction we don't want the signed extend bit,
3368 because it influences the size. */
3369 if (cris_get_opcode (*inst) < 4)
3371 size &= ~SIGNED_EXTEND_BIT_MASK;
3373 /* Is there a need for checking the size? Size should contain the number of
3376 value = read_memory_unsigned_integer (address, size, byte_order);
3378 /* Check if it's an extend, signed or zero instruction. */
3379 if (cris_get_opcode (*inst) < 4)
3381 value = do_sign_or_zero_extend (value, inst);
3386 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3387 instructions. The MOVE instruction is the move from source to register. */
3390 handle_prefix_assign_mode_for_aritm_op (unsigned short inst,
3391 inst_env_type *inst_env)
3393 unsigned long operand2;
3394 unsigned long operand3;
3396 check_assign (inst, inst_env);
3397 if (cris_get_operand2 (inst) == REG_PC)
3399 operand2 = inst_env->reg[REG_PC];
3401 /* Get the value of the third operand. */
3402 operand3 = get_data_from_address (&inst, inst_env->prefix_value,
3403 inst_env->byte_order);
3405 /* Calculate the PC value after the instruction, i.e. where the
3406 breakpoint should be. The order of the udw_operands is vital. */
3407 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3409 inst_env->slot_needed = 0;
3410 inst_env->prefix_found = 0;
3411 inst_env->xflag_found = 0;
3412 inst_env->disable_interrupt = 0;
3415 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3416 OR instructions. Note that for this to work as expected, the calling
3417 function must have made sure that there is a prefix to this instruction. */
3420 three_operand_add_sub_cmp_and_or_op (unsigned short inst,
3421 inst_env_type *inst_env)
3423 unsigned long operand2;
3424 unsigned long operand3;
3426 if (cris_get_operand1 (inst) == REG_PC)
3428 /* The PC will be changed by the instruction. */
3429 operand2 = inst_env->reg[cris_get_operand2 (inst)];
3431 /* Get the value of the third operand. */
3432 operand3 = get_data_from_address (&inst, inst_env->prefix_value,
3433 inst_env->byte_order);
3435 /* Calculate the PC value after the instruction, i.e. where the
3436 breakpoint should be. */
3437 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3439 inst_env->slot_needed = 0;
3440 inst_env->prefix_found = 0;
3441 inst_env->xflag_found = 0;
3442 inst_env->disable_interrupt = 0;
3445 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3446 instructions. The MOVE instruction is the move from source to register. */
3449 handle_prefix_index_mode_for_aritm_op (unsigned short inst,
3450 inst_env_type *inst_env)
3452 if (cris_get_operand1 (inst) != cris_get_operand2 (inst))
3454 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
3455 SUB, AND or OR something weird is going on (if everything works these
3456 instructions should end up in the three operand version). */
3457 inst_env->invalid = 1;
3462 /* three_operand_add_sub_cmp_and_or does the same as we should do here
3464 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3466 inst_env->slot_needed = 0;
3467 inst_env->prefix_found = 0;
3468 inst_env->xflag_found = 0;
3469 inst_env->disable_interrupt = 0;
3472 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3473 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
3474 source to register. */
3477 handle_inc_and_index_mode_for_aritm_op (unsigned short inst,
3478 inst_env_type *inst_env)
3480 unsigned long operand1;
3481 unsigned long operand2;
3482 unsigned long operand3;
3485 /* The instruction is either an indirect or autoincrement addressing mode.
3486 Check if the destination register is the PC. */
3487 if (cris_get_operand2 (inst) == REG_PC)
3489 /* Must be done here, get_data_from_address may change the size
3491 size = cris_get_size (inst);
3492 operand2 = inst_env->reg[REG_PC];
3494 /* Get the value of the third operand, i.e. the indirect operand. */
3495 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3496 operand3 = get_data_from_address (&inst, operand1, inst_env->byte_order);
3498 /* Calculate the PC value after the instruction, i.e. where the
3499 breakpoint should be. The order of the udw_operands is vital. */
3500 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3502 /* If this is an autoincrement addressing mode, check if the increment
3504 if ((cris_get_operand1 (inst) == REG_PC)
3505 && (cris_get_mode (inst) == AUTOINC_MODE))
3507 /* Get the size field. */
3508 size = cris_get_size (inst);
3510 /* If it's an extend instruction we don't want the signed extend bit,
3511 because it influences the size. */
3512 if (cris_get_opcode (inst) < 4)
3514 size &= ~SIGNED_EXTEND_BIT_MASK;
3516 process_autoincrement (size, inst, inst_env);
3518 inst_env->slot_needed = 0;
3519 inst_env->prefix_found = 0;
3520 inst_env->xflag_found = 0;
3521 inst_env->disable_interrupt = 0;
3524 /* Handles the two-operand addressing mode, all modes except register, for
3525 the ADD, SUB CMP, AND and OR instruction. */
3528 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3529 inst_env_type *inst_env)
3531 if (inst_env->prefix_found)
3533 if (cris_get_mode (inst) == PREFIX_INDEX_MODE)
3535 handle_prefix_index_mode_for_aritm_op (inst, inst_env);
3537 else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
3539 handle_prefix_assign_mode_for_aritm_op (inst, inst_env);
3543 /* The mode is invalid for a prefixed base instruction. */
3544 inst_env->invalid = 1;
3550 handle_inc_and_index_mode_for_aritm_op (inst, inst_env);
3554 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3557 quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env)
3559 unsigned long operand1;
3560 unsigned long operand2;
3562 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3563 instruction and can't have a prefix. */
3564 if (inst_env->prefix_found)
3566 inst_env->invalid = 1;
3570 /* Check if the instruction has PC as its target. */
3571 if (cris_get_operand2 (inst) == REG_PC)
3573 if (inst_env->slot_needed)
3575 inst_env->invalid = 1;
3578 operand1 = cris_get_quick_value (inst);
3579 operand2 = inst_env->reg[REG_PC];
3581 /* The size should now be dword. */
3582 cris_set_size_to_dword (&inst);
3584 /* Calculate the PC value after the instruction, i.e. where the
3585 breakpoint should be. */
3586 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3588 inst_env->slot_needed = 0;
3589 inst_env->prefix_found = 0;
3590 inst_env->xflag_found = 0;
3591 inst_env->disable_interrupt = 0;
3594 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3597 quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env)
3599 unsigned long operand1;
3600 unsigned long operand2;
3602 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3603 instruction and can't have a prefix. */
3604 if (inst_env->prefix_found)
3606 inst_env->invalid = 1;
3609 /* Check if the instruction has PC as its target. */
3610 if (cris_get_operand2 (inst) == REG_PC)
3612 if (inst_env->slot_needed)
3614 inst_env->invalid = 1;
3617 /* The instruction has the PC as its target register. */
3618 operand1 = cris_get_quick_value (inst);
3619 operand2 = inst_env->reg[REG_PC];
3621 /* The quick value is signed, so check if we must do a signed extend. */
3622 if (operand1 & SIGNED_QUICK_VALUE_MASK)
3625 operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK;
3627 /* The size should now be dword. */
3628 cris_set_size_to_dword (&inst);
3630 /* Calculate the PC value after the instruction, i.e. where the
3631 breakpoint should be. */
3632 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3634 inst_env->slot_needed = 0;
3635 inst_env->prefix_found = 0;
3636 inst_env->xflag_found = 0;
3637 inst_env->disable_interrupt = 0;
3640 /* Translate op_type to a function and call it. */
3643 cris_gdb_func (struct gdbarch *gdbarch, enum cris_op_type op_type,
3644 unsigned short inst, inst_env_type *inst_env)
3648 case cris_not_implemented_op:
3649 not_implemented_op (inst, inst_env);
3653 abs_op (inst, inst_env);
3657 addi_op (inst, inst_env);
3661 asr_op (inst, inst_env);
3665 asrq_op (inst, inst_env);
3668 case cris_ax_ei_setf_op:
3669 ax_ei_setf_op (inst, inst_env);
3672 case cris_bdap_prefix:
3673 bdap_prefix (inst, inst_env);
3676 case cris_biap_prefix:
3677 biap_prefix (inst, inst_env);
3681 break_op (inst, inst_env);
3684 case cris_btst_nop_op:
3685 btst_nop_op (inst, inst_env);
3688 case cris_clearf_di_op:
3689 clearf_di_op (inst, inst_env);
3692 case cris_dip_prefix:
3693 dip_prefix (inst, inst_env);
3696 case cris_dstep_logshift_mstep_neg_not_op:
3697 dstep_logshift_mstep_neg_not_op (inst, inst_env);
3700 case cris_eight_bit_offset_branch_op:
3701 eight_bit_offset_branch_op (inst, inst_env);
3704 case cris_move_mem_to_reg_movem_op:
3705 move_mem_to_reg_movem_op (inst, inst_env);
3708 case cris_move_reg_to_mem_movem_op:
3709 move_reg_to_mem_movem_op (inst, inst_env);
3712 case cris_move_to_preg_op:
3713 move_to_preg_op (gdbarch, inst, inst_env);
3717 muls_op (inst, inst_env);
3721 mulu_op (inst, inst_env);
3724 case cris_none_reg_mode_add_sub_cmp_and_or_move_op:
3725 none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3728 case cris_none_reg_mode_clear_test_op:
3729 none_reg_mode_clear_test_op (inst, inst_env);
3732 case cris_none_reg_mode_jump_op:
3733 none_reg_mode_jump_op (inst, inst_env);
3736 case cris_none_reg_mode_move_from_preg_op:
3737 none_reg_mode_move_from_preg_op (gdbarch, inst, inst_env);
3740 case cris_quick_mode_add_sub_op:
3741 quick_mode_add_sub_op (inst, inst_env);
3744 case cris_quick_mode_and_cmp_move_or_op:
3745 quick_mode_and_cmp_move_or_op (inst, inst_env);
3748 case cris_quick_mode_bdap_prefix:
3749 quick_mode_bdap_prefix (inst, inst_env);
3752 case cris_reg_mode_add_sub_cmp_and_or_move_op:
3753 reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3756 case cris_reg_mode_clear_op:
3757 reg_mode_clear_op (inst, inst_env);
3760 case cris_reg_mode_jump_op:
3761 reg_mode_jump_op (inst, inst_env);
3764 case cris_reg_mode_move_from_preg_op:
3765 reg_mode_move_from_preg_op (inst, inst_env);
3768 case cris_reg_mode_test_op:
3769 reg_mode_test_op (inst, inst_env);
3773 scc_op (inst, inst_env);
3776 case cris_sixteen_bit_offset_branch_op:
3777 sixteen_bit_offset_branch_op (inst, inst_env);
3780 case cris_three_operand_add_sub_cmp_and_or_op:
3781 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3784 case cris_three_operand_bound_op:
3785 three_operand_bound_op (inst, inst_env);
3788 case cris_two_operand_bound_op:
3789 two_operand_bound_op (inst, inst_env);
3793 xor_op (inst, inst_env);
3798 /* This wrapper is to avoid cris_get_assembler being called before
3799 exec_bfd has been set. */
3802 cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info)
3804 int (*print_insn) (bfd_vma addr, struct disassemble_info *info);
3805 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3806 disassembler, even when there is no BFD. Does something like
3807 "gdb; target remote; disassmeble *0x123" work? */
3808 gdb_assert (exec_bfd != NULL);
3809 print_insn = cris_get_disassembler (exec_bfd);
3810 gdb_assert (print_insn != NULL);
3811 return print_insn (addr, info);
3814 /* Originally from <asm/elf.h>. */
3815 typedef unsigned char cris_elf_greg_t[4];
3817 /* Same as user_regs_struct struct in <asm/user.h>. */
3818 #define CRISV10_ELF_NGREG 35
3819 typedef cris_elf_greg_t cris_elf_gregset_t[CRISV10_ELF_NGREG];
3821 #define CRISV32_ELF_NGREG 32
3822 typedef cris_elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG];
3824 /* Unpack a cris_elf_gregset_t into GDB's register cache. */
3827 cris_supply_gregset (struct regcache *regcache, cris_elf_gregset_t *gregsetp)
3829 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3830 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3832 cris_elf_greg_t *regp = *gregsetp;
3834 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3835 knows about the actual size of each register so that's no problem. */
3836 for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++)
3838 regcache_raw_supply (regcache, i, (char *)®p[i]);
3841 if (tdep->cris_version == 32)
3843 /* Needed to set pseudo-register PC for CRISv32. */
3844 /* FIXME: If ERP is in a delay slot at this point then the PC will
3845 be wrong. Issue a warning to alert the user. */
3846 regcache_raw_supply (regcache, gdbarch_pc_regnum (gdbarch),
3847 (char *)®p[ERP_REGNUM]);
3849 if (*(char *)®p[ERP_REGNUM] & 0x1)
3850 fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n");
3854 /* Use a local version of this function to get the correct types for
3855 regsets, until multi-arch core support is ready. */
3858 fetch_core_registers (struct regcache *regcache,
3859 char *core_reg_sect, unsigned core_reg_size,
3860 int which, CORE_ADDR reg_addr)
3862 cris_elf_gregset_t gregset;
3867 if (core_reg_size != sizeof (cris_elf_gregset_t)
3868 && core_reg_size != sizeof (crisv32_elf_gregset_t))
3870 warning (_("wrong size gregset struct in core file"));
3874 memcpy (&gregset, core_reg_sect, sizeof (gregset));
3875 cris_supply_gregset (regcache, &gregset);
3879 /* We've covered all the kinds of registers we know about here,
3880 so this must be something we wouldn't know what to do with
3881 anyway. Just ignore it. */
3886 static struct core_fns cris_elf_core_fns =
3888 bfd_target_elf_flavour, /* core_flavour */
3889 default_check_format, /* check_format */
3890 default_core_sniffer, /* core_sniffer */
3891 fetch_core_registers, /* core_read_registers */
3895 extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */
3898 _initialize_cris_tdep (void)
3900 struct cmd_list_element *c;
3902 gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep);
3904 /* CRIS-specific user-commands. */
3905 add_setshow_zuinteger_cmd ("cris-version", class_support,
3906 &usr_cmd_cris_version,
3907 _("Set the current CRIS version."),
3908 _("Show the current CRIS version."),
3910 Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\
3913 NULL, /* FIXME: i18n: Current CRIS version
3915 &setlist, &showlist);
3917 add_setshow_enum_cmd ("cris-mode", class_support,
3918 cris_modes, &usr_cmd_cris_mode,
3919 _("Set the current CRIS mode."),
3920 _("Show the current CRIS mode."),
3922 Set to CRIS_MODE_GURU when debugging in guru mode.\n\
3923 Makes GDB use the NRP register instead of the ERP register in certain cases."),
3925 NULL, /* FIXME: i18n: Current CRIS version is %s. */
3926 &setlist, &showlist);
3928 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support,
3929 &usr_cmd_cris_dwarf2_cfi,
3930 _("Set the usage of Dwarf-2 CFI for CRIS."),
3931 _("Show the usage of Dwarf-2 CFI for CRIS."),
3932 _("Set this to \"off\" if using gcc-cris < R59."),
3933 set_cris_dwarf2_cfi,
3934 NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI
3936 &setlist, &showlist);
3938 deprecated_add_core_fns (&cris_elf_core_fns);
3941 /* Prints out all target specific values. */
3944 cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3946 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3949 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n",
3950 tdep->cris_version);
3951 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n",
3953 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
3954 tdep->cris_dwarf2_cfi);
3959 set_cris_version (char *ignore_args, int from_tty,
3960 struct cmd_list_element *c)
3962 struct gdbarch_info info;
3964 usr_cmd_cris_version_valid = 1;
3966 /* Update the current architecture, if needed. */
3967 gdbarch_info_init (&info);
3968 if (!gdbarch_update_p (info))
3969 internal_error (__FILE__, __LINE__,
3970 _("cris_gdbarch_update: failed to update architecture."));
3974 set_cris_mode (char *ignore_args, int from_tty,
3975 struct cmd_list_element *c)
3977 struct gdbarch_info info;
3979 /* Update the current architecture, if needed. */
3980 gdbarch_info_init (&info);
3981 if (!gdbarch_update_p (info))
3982 internal_error (__FILE__, __LINE__,
3983 "cris_gdbarch_update: failed to update architecture.");
3987 set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
3988 struct cmd_list_element *c)
3990 struct gdbarch_info info;
3992 /* Update the current architecture, if needed. */
3993 gdbarch_info_init (&info);
3994 if (!gdbarch_update_p (info))
3995 internal_error (__FILE__, __LINE__,
3996 _("cris_gdbarch_update: failed to update architecture."));
3999 static struct gdbarch *
4000 cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
4002 struct gdbarch *gdbarch;
4003 struct gdbarch_tdep *tdep;
4004 unsigned int cris_version;
4006 if (usr_cmd_cris_version_valid)
4008 /* Trust the user's CRIS version setting. */
4009 cris_version = usr_cmd_cris_version;
4011 else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32)
4017 /* Assume it's CRIS version 10. */
4021 /* Make the current settings visible to the user. */
4022 usr_cmd_cris_version = cris_version;
4024 /* Find a candidate among the list of pre-declared architectures. */
4025 for (arches = gdbarch_list_lookup_by_info (arches, &info);
4027 arches = gdbarch_list_lookup_by_info (arches->next, &info))
4029 if ((gdbarch_tdep (arches->gdbarch)->cris_version
4030 == usr_cmd_cris_version)
4031 && (gdbarch_tdep (arches->gdbarch)->cris_mode
4032 == usr_cmd_cris_mode)
4033 && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi
4034 == usr_cmd_cris_dwarf2_cfi))
4035 return arches->gdbarch;
4038 /* No matching architecture was found. Create a new one. */
4039 tdep = XNEW (struct gdbarch_tdep);
4040 gdbarch = gdbarch_alloc (&info, tdep);
4042 tdep->cris_version = usr_cmd_cris_version;
4043 tdep->cris_mode = usr_cmd_cris_mode;
4044 tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi;
4046 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
4047 switch (info.byte_order)
4049 case BFD_ENDIAN_LITTLE:
4053 case BFD_ENDIAN_BIG:
4054 internal_error (__FILE__, __LINE__,
4055 _("cris_gdbarch_init: big endian byte order in info"));
4059 internal_error (__FILE__, __LINE__,
4060 _("cris_gdbarch_init: unknown byte order in info"));
4063 set_gdbarch_return_value (gdbarch, cris_return_value);
4065 set_gdbarch_sp_regnum (gdbarch, 14);
4067 /* Length of ordinary registers used in push_word and a few other
4068 places. register_size() is the real way to know how big a
4071 set_gdbarch_double_bit (gdbarch, 64);
4072 /* The default definition of a long double is 2 * gdbarch_double_bit,
4073 which means we have to set this explicitly. */
4074 set_gdbarch_long_double_bit (gdbarch, 64);
4076 /* The total amount of space needed to store (in an array called registers)
4077 GDB's copy of the machine's register state. Note: We can not use
4078 cris_register_size at this point, since it relies on gdbarch
4080 switch (tdep->cris_version)
4088 /* Old versions; not supported. */
4089 internal_error (__FILE__, __LINE__,
4090 _("cris_gdbarch_init: unsupported CRIS version"));
4095 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
4096 P7 (32 bits), and P15 (32 bits) have been implemented. */
4097 set_gdbarch_pc_regnum (gdbarch, 15);
4098 set_gdbarch_register_type (gdbarch, cris_register_type);
4099 /* There are 32 registers (some of which may not be implemented). */
4100 set_gdbarch_num_regs (gdbarch, 32);
4101 set_gdbarch_register_name (gdbarch, cris_register_name);
4102 set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register);
4103 set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register);
4105 set_gdbarch_software_single_step (gdbarch, cris_software_single_step);
4109 /* CRIS v32. General registers R0 - R15 (32 bits), special registers
4110 P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
4111 and pseudo-register PC (32 bits). */
4112 set_gdbarch_pc_regnum (gdbarch, 32);
4113 set_gdbarch_register_type (gdbarch, crisv32_register_type);
4114 /* 32 registers + pseudo-register PC + 16 support registers. */
4115 set_gdbarch_num_regs (gdbarch, 32 + 1 + 16);
4116 set_gdbarch_register_name (gdbarch, crisv32_register_name);
4118 set_gdbarch_cannot_store_register
4119 (gdbarch, crisv32_cannot_store_register);
4120 set_gdbarch_cannot_fetch_register
4121 (gdbarch, crisv32_cannot_fetch_register);
4123 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
4125 set_gdbarch_single_step_through_delay
4126 (gdbarch, crisv32_single_step_through_delay);
4131 internal_error (__FILE__, __LINE__,
4132 _("cris_gdbarch_init: unknown CRIS version"));
4135 /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
4136 have the same ABI). */
4137 set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code);
4138 set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call);
4139 set_gdbarch_frame_align (gdbarch, cris_frame_align);
4140 set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue);
4142 /* The stack grows downward. */
4143 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4145 set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc);
4147 set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc);
4148 set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp);
4149 set_gdbarch_dummy_id (gdbarch, cris_dummy_id);
4151 if (tdep->cris_dwarf2_cfi == 1)
4153 /* Hook in the Dwarf-2 frame sniffer. */
4154 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum);
4155 dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg);
4156 dwarf2_append_unwinders (gdbarch);
4159 if (tdep->cris_mode != cris_mode_guru)
4161 frame_unwind_append_unwinder (gdbarch, &cris_sigtramp_frame_unwind);
4164 frame_unwind_append_unwinder (gdbarch, &cris_frame_unwind);
4165 frame_base_set_default (gdbarch, &cris_frame_base);
4167 /* Hook in ABI-specific overrides, if they have been registered. */
4168 gdbarch_init_osabi (info, gdbarch);
4170 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
4171 disassembler, even when there is no BFD. Does something like
4172 "gdb; target remote; disassmeble *0x123" work? */
4173 set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler);