1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 Contributed by Axis Communications AB.
7 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "frame-unwind.h"
27 #include "frame-base.h"
28 #include "trad-frame.h"
29 #include "dwarf2-frame.h"
37 #include "opcode/cris.h"
38 #include "arch-utils.h"
40 #include "gdb_assert.h"
42 /* To get entry_point_address. */
45 #include "solib.h" /* Support for shared libraries. */
46 #include "solib-svr4.h"
47 #include "gdb_string.h"
52 /* There are no floating point registers. Used in gdbserver low-linux.c. */
55 /* There are 16 general registers. */
58 /* There are 16 special registers. */
61 /* CRISv32 has a pseudo PC register, not noted here. */
63 /* CRISv32 has 16 support registers. */
67 /* Register numbers of various important registers.
68 CRIS_FP_REGNUM Contains address of executing stack frame.
69 STR_REGNUM Contains the address of structure return values.
70 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
71 ARG1_REGNUM Contains the first parameter to a function.
72 ARG2_REGNUM Contains the second parameter to a function.
73 ARG3_REGNUM Contains the third parameter to a function.
74 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
75 gdbarch_sp_regnum Contains address of top of stack.
76 gdbarch_pc_regnum Contains address of next instruction.
77 SRP_REGNUM Subroutine return pointer register.
78 BRP_REGNUM Breakpoint return pointer register. */
82 /* Enums with respect to the general registers, valid for all
83 CRIS versions. The frame pointer is always in R8. */
85 /* ABI related registers. */
93 /* Registers which happen to be common. */
98 /* CRISv10 et. al. specific registers. */
110 /* CRISv32 specific registers. */
123 CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */
125 CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */
145 extern const struct cris_spec_reg cris_spec_regs[];
147 /* CRIS version, set via the user command 'set cris-version'. Affects
148 register names and sizes. */
149 static int usr_cmd_cris_version;
151 /* Indicates whether to trust the above variable. */
152 static int usr_cmd_cris_version_valid = 0;
154 static const char cris_mode_normal[] = "normal";
155 static const char cris_mode_guru[] = "guru";
156 static const char *cris_modes[] = {
162 /* CRIS mode, set via the user command 'set cris-mode'. Affects
163 type of break instruction among other things. */
164 static const char *usr_cmd_cris_mode = cris_mode_normal;
166 /* Whether to make use of Dwarf-2 CFI (default on). */
167 static int usr_cmd_cris_dwarf2_cfi = 1;
169 /* CRIS architecture specific information. */
173 const char *cris_mode;
177 /* Functions for accessing target dependent data. */
182 return (gdbarch_tdep (current_gdbarch)->cris_version);
188 return (gdbarch_tdep (current_gdbarch)->cris_mode);
191 /* Sigtramp identification code copied from i386-linux-tdep.c. */
193 #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
194 #define SIGTRAMP_OFFSET0 0
195 #define SIGTRAMP_INSN1 0xe93d /* break 13 */
196 #define SIGTRAMP_OFFSET1 4
198 static const unsigned short sigtramp_code[] =
200 SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */
201 SIGTRAMP_INSN1 /* break 13 */
204 #define SIGTRAMP_LEN (sizeof sigtramp_code)
206 /* Note: same length as normal sigtramp code. */
208 static const unsigned short rt_sigtramp_code[] =
210 SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */
211 SIGTRAMP_INSN1 /* break 13 */
214 /* If PC is in a sigtramp routine, return the address of the start of
215 the routine. Otherwise, return 0. */
218 cris_sigtramp_start (struct frame_info *this_frame)
220 CORE_ADDR pc = get_frame_pc (this_frame);
221 gdb_byte buf[SIGTRAMP_LEN];
223 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
226 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
228 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
231 pc -= SIGTRAMP_OFFSET1;
232 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
236 if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0)
242 /* If PC is in a RT sigtramp routine, return the address of the start of
243 the routine. Otherwise, return 0. */
246 cris_rt_sigtramp_start (struct frame_info *this_frame)
248 CORE_ADDR pc = get_frame_pc (this_frame);
249 gdb_byte buf[SIGTRAMP_LEN];
251 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
254 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
256 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
259 pc -= SIGTRAMP_OFFSET1;
260 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
264 if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0)
270 /* Assuming THIS_FRAME is a frame for a GNU/Linux sigtramp routine,
271 return the address of the associated sigcontext structure. */
274 cris_sigcontext_addr (struct frame_info *this_frame)
280 get_frame_register (this_frame,
281 gdbarch_sp_regnum (get_frame_arch (this_frame)), buf);
282 sp = extract_unsigned_integer (buf, 4);
284 /* Look for normal sigtramp frame first. */
285 pc = cris_sigtramp_start (this_frame);
288 /* struct signal_frame (arch/cris/kernel/signal.c) contains
289 struct sigcontext as its first member, meaning the SP points to
294 pc = cris_rt_sigtramp_start (this_frame);
297 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
298 a struct ucontext, which in turn contains a struct sigcontext.
300 4 + 4 + 128 to struct ucontext, then
301 4 + 4 + 12 to struct sigcontext. */
305 error (_("Couldn't recognize signal trampoline."));
309 struct cris_unwind_cache
311 /* The previous frame's inner most stack address. Used as this
312 frame ID's stack_addr. */
314 /* The frame's base, optionally used by the high-level debug info. */
317 /* How far the SP and r8 (FP) have been offset from the start of
318 the stack frame (as defined by the previous frame's stack
324 /* From old frame_extra_info struct. */
328 /* Table indicating the location of each and every register. */
329 struct trad_frame_saved_reg *saved_regs;
332 static struct cris_unwind_cache *
333 cris_sigtramp_frame_unwind_cache (struct frame_info *this_frame,
336 struct gdbarch *gdbarch = get_frame_arch (this_frame);
337 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
338 struct cris_unwind_cache *info;
346 return (*this_cache);
348 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
349 (*this_cache) = info;
350 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
352 /* Zero all fields. */
358 info->uses_frame = 0;
360 info->leaf_function = 0;
362 get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
363 info->base = extract_unsigned_integer (buf, 4);
365 addr = cris_sigcontext_addr (this_frame);
367 /* Layout of the sigcontext struct:
370 unsigned long oldmask;
374 if (tdep->cris_version == 10)
376 /* R0 to R13 are stored in reverse order at offset (2 * 4) in
378 for (i = 0; i <= 13; i++)
379 info->saved_regs[i].addr = addr + ((15 - i) * 4);
381 info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4);
382 info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4);
383 info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4);
384 /* Note: IRP is off by 2 at this point. There's no point in correcting
385 it though since that will mean that the backtrace will show a PC
386 different from what is shown when stopped. */
387 info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4);
388 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
389 = info->saved_regs[IRP_REGNUM];
390 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr = addr + (24 * 4);
395 /* R0 to R13 are stored in order at offset (1 * 4) in
397 for (i = 0; i <= 13; i++)
398 info->saved_regs[i].addr = addr + ((i + 1) * 4);
400 info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4);
401 info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4);
402 info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4);
403 info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4);
404 info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4);
405 info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4);
406 info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4);
407 info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4);
408 info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4);
410 /* FIXME: If ERP is in a delay slot at this point then the PC will
411 be wrong at this point. This problem manifests itself in the
412 sigaltstack.exp test case, which occasionally generates FAILs when
413 the signal is received while in a delay slot.
415 This could be solved by a couple of read_memory_unsigned_integer and a
416 trad_frame_set_value. */
417 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
418 = info->saved_regs[ERP_REGNUM];
420 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr
428 cris_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
429 struct frame_id *this_id)
431 struct cris_unwind_cache *cache =
432 cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
433 (*this_id) = frame_id_build (cache->base, get_frame_pc (this_frame));
436 /* Forward declaration. */
438 static struct value *cris_frame_prev_register (struct frame_info *this_frame,
439 void **this_cache, int regnum);
440 static struct value *
441 cris_sigtramp_frame_prev_register (struct frame_info *this_frame,
442 void **this_cache, int regnum)
444 /* Make sure we've initialized the cache. */
445 cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
446 return cris_frame_prev_register (this_frame, this_cache, regnum);
450 cris_sigtramp_frame_sniffer (const struct frame_unwind *self,
451 struct frame_info *this_frame,
454 if (cris_sigtramp_start (this_frame)
455 || cris_rt_sigtramp_start (this_frame))
461 static const struct frame_unwind cris_sigtramp_frame_unwind =
464 cris_sigtramp_frame_this_id,
465 cris_sigtramp_frame_prev_register,
467 cris_sigtramp_frame_sniffer
471 crisv32_single_step_through_delay (struct gdbarch *gdbarch,
472 struct frame_info *this_frame)
474 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
479 if (cris_mode () == cris_mode_guru)
481 frame_unwind_register (this_frame, NRP_REGNUM, buf);
485 frame_unwind_register (this_frame, ERP_REGNUM, buf);
488 erp = extract_unsigned_integer (buf, 4);
492 /* In delay slot - check if there's a breakpoint at the preceding
494 if (breakpoint_here_p (erp & ~0x1))
500 /* Hardware watchpoint support. */
502 /* We support 6 hardware data watchpoints, but cannot trigger on execute
503 (any combination of read/write is fine). */
506 cris_can_use_hardware_watchpoint (int type, int count, int other)
508 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
510 /* No bookkeeping is done here; it is handled by the remote debug agent. */
512 if (tdep->cris_version != 32)
515 /* CRISv32: Six data watchpoints, one for instructions. */
516 return (((type == bp_read_watchpoint || type == bp_access_watchpoint
517 || type == bp_hardware_watchpoint) && count <= 6)
518 || (type == bp_hardware_breakpoint && count <= 1));
521 /* The CRISv32 hardware data watchpoints work by specifying ranges,
522 which have no alignment or length restrictions. */
525 cris_region_ok_for_watchpoint (CORE_ADDR addr, int len)
530 /* If the inferior has some watchpoint that triggered, return the
531 address associated with that watchpoint. Otherwise, return
535 cris_stopped_data_address (void)
538 eda = get_frame_register_unsigned (get_current_frame (), EDA_REGNUM);
542 /* The instruction environment needed to find single-step breakpoints. */
545 struct instruction_environment
547 unsigned long reg[NUM_GENREGS];
548 unsigned long preg[NUM_SPECREGS];
549 unsigned long branch_break_address;
550 unsigned long delay_slot_pc;
551 unsigned long prefix_value;
556 int delay_slot_pc_active;
558 int disable_interrupt;
561 /* Machine-dependencies in CRIS for opcodes. */
563 /* Instruction sizes. */
564 enum cris_instruction_sizes
571 /* Addressing modes. */
572 enum cris_addressing_modes
579 /* Prefix addressing modes. */
580 enum cris_prefix_addressing_modes
582 PREFIX_INDEX_MODE = 2,
583 PREFIX_ASSIGN_MODE = 3,
585 /* Handle immediate byte offset addressing mode prefix format. */
586 PREFIX_OFFSET_MODE = 2
589 /* Masks for opcodes. */
590 enum cris_opcode_masks
592 BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1,
593 SIGNED_EXTEND_BIT_MASK = 0x2,
594 SIGNED_BYTE_MASK = 0x80,
595 SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00,
596 SIGNED_WORD_MASK = 0x8000,
597 SIGNED_WORD_EXTEND_MASK = 0xFFFF0000,
598 SIGNED_DWORD_MASK = 0x80000000,
599 SIGNED_QUICK_VALUE_MASK = 0x20,
600 SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0
603 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
611 cris_get_operand2 (unsigned short insn)
613 return ((insn & 0xF000) >> 12);
617 cris_get_mode (unsigned short insn)
619 return ((insn & 0x0C00) >> 10);
623 cris_get_opcode (unsigned short insn)
625 return ((insn & 0x03C0) >> 6);
629 cris_get_size (unsigned short insn)
631 return ((insn & 0x0030) >> 4);
635 cris_get_operand1 (unsigned short insn)
637 return (insn & 0x000F);
640 /* Additional functions in order to handle opcodes. */
643 cris_get_quick_value (unsigned short insn)
645 return (insn & 0x003F);
649 cris_get_bdap_quick_offset (unsigned short insn)
651 return (insn & 0x00FF);
655 cris_get_branch_short_offset (unsigned short insn)
657 return (insn & 0x00FF);
661 cris_get_asr_shift_steps (unsigned long value)
663 return (value & 0x3F);
667 cris_get_clear_size (unsigned short insn)
669 return ((insn) & 0xC000);
673 cris_is_signed_extend_bit_on (unsigned short insn)
675 return (((insn) & 0x20) == 0x20);
679 cris_is_xflag_bit_on (unsigned short insn)
681 return (((insn) & 0x1000) == 0x1000);
685 cris_set_size_to_dword (unsigned short *insn)
692 cris_get_signed_offset (unsigned short insn)
694 return ((signed char) (insn & 0x00FF));
697 /* Calls an op function given the op-type, working on the insn and the
699 static void cris_gdb_func (struct gdbarch *, enum cris_op_type, unsigned short,
702 static struct gdbarch *cris_gdbarch_init (struct gdbarch_info,
703 struct gdbarch_list *);
705 static void cris_dump_tdep (struct gdbarch *, struct ui_file *);
707 static void set_cris_version (char *ignore_args, int from_tty,
708 struct cmd_list_element *c);
710 static void set_cris_mode (char *ignore_args, int from_tty,
711 struct cmd_list_element *c);
713 static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
714 struct cmd_list_element *c);
716 static CORE_ADDR cris_scan_prologue (CORE_ADDR pc,
717 struct frame_info *this_frame,
718 struct cris_unwind_cache *info);
720 static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc,
721 struct frame_info *this_frame,
722 struct cris_unwind_cache *info);
724 static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch,
725 struct frame_info *next_frame);
727 static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch,
728 struct frame_info *next_frame);
730 /* When arguments must be pushed onto the stack, they go on in reverse
731 order. The below implements a FILO (stack) to do this.
732 Copied from d10v-tdep.c. */
737 struct stack_item *prev;
741 static struct stack_item *
742 push_stack_item (struct stack_item *prev, void *contents, int len)
744 struct stack_item *si;
745 si = xmalloc (sizeof (struct stack_item));
746 si->data = xmalloc (len);
749 memcpy (si->data, contents, len);
753 static struct stack_item *
754 pop_stack_item (struct stack_item *si)
756 struct stack_item *dead = si;
763 /* Put here the code to store, into fi->saved_regs, the addresses of
764 the saved registers of frame described by FRAME_INFO. This
765 includes special registers such as pc and fp saved in special ways
766 in the stack frame. sp is even more special: the address we return
767 for it IS the sp for the next frame. */
769 struct cris_unwind_cache *
770 cris_frame_unwind_cache (struct frame_info *this_frame,
771 void **this_prologue_cache)
774 struct cris_unwind_cache *info;
777 if ((*this_prologue_cache))
778 return (*this_prologue_cache);
780 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
781 (*this_prologue_cache) = info;
782 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
784 /* Zero all fields. */
790 info->uses_frame = 0;
792 info->leaf_function = 0;
794 /* Prologue analysis does the rest... */
795 if (cris_version () == 32)
796 crisv32_scan_prologue (get_frame_func (this_frame), this_frame, info);
798 cris_scan_prologue (get_frame_func (this_frame), this_frame, info);
803 /* Given a GDB frame, determine the address of the calling function's
804 frame. This will be used to create a new GDB frame struct. */
807 cris_frame_this_id (struct frame_info *this_frame,
808 void **this_prologue_cache,
809 struct frame_id *this_id)
811 struct cris_unwind_cache *info
812 = cris_frame_unwind_cache (this_frame, this_prologue_cache);
817 /* The FUNC is easy. */
818 func = get_frame_func (this_frame);
820 /* Hopefully the prologue analysis either correctly determined the
821 frame's base (which is the SP from the previous frame), or set
822 that base to "NULL". */
823 base = info->prev_sp;
827 id = frame_id_build (base, func);
832 static struct value *
833 cris_frame_prev_register (struct frame_info *this_frame,
834 void **this_prologue_cache, int regnum)
836 struct cris_unwind_cache *info
837 = cris_frame_unwind_cache (this_frame, this_prologue_cache);
838 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
841 /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
842 frame. The frame ID's base needs to match the TOS value saved by
843 save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */
845 static struct frame_id
846 cris_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
849 sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
850 return frame_id_build (sp, get_frame_pc (this_frame));
854 cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
856 /* Align to the size of an instruction (so that they can safely be
857 pushed onto the stack). */
862 cris_push_dummy_code (struct gdbarch *gdbarch,
863 CORE_ADDR sp, CORE_ADDR funaddr,
864 struct value **args, int nargs,
865 struct type *value_type,
866 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
867 struct regcache *regcache)
869 /* Allocate space sufficient for a breakpoint. */
871 /* Store the address of that breakpoint */
873 /* CRIS always starts the call at the callee's entry point. */
879 cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
880 struct regcache *regcache, CORE_ADDR bp_addr,
881 int nargs, struct value **args, CORE_ADDR sp,
882 int struct_return, CORE_ADDR struct_addr)
891 /* The function's arguments and memory allocated by gdb for the arguments to
892 point at reside in separate areas on the stack.
893 Both frame pointers grow toward higher addresses. */
897 struct stack_item *si = NULL;
899 /* Push the return address. */
900 regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr);
902 /* Are we returning a value using a structure return or a normal value
903 return? struct_addr is the address of the reserved space for the return
904 structure to be written on the stack. */
907 regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr);
910 /* Now load as many as possible of the first arguments into registers,
911 and push the rest onto the stack. */
912 argreg = ARG1_REGNUM;
915 for (argnum = 0; argnum < nargs; argnum++)
922 len = TYPE_LENGTH (value_type (args[argnum]));
923 val = (char *) value_contents (args[argnum]);
925 /* How may registers worth of storage do we need for this argument? */
926 reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0);
928 if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM))
930 /* Data passed by value. Fits in available register(s). */
931 for (i = 0; i < reg_demand; i++)
933 regcache_cooked_write (regcache, argreg, val);
938 else if (len <= (2 * 4) && argreg <= ARG4_REGNUM)
940 /* Data passed by value. Does not fit in available register(s).
941 Use the register(s) first, then the stack. */
942 for (i = 0; i < reg_demand; i++)
944 if (argreg <= ARG4_REGNUM)
946 regcache_cooked_write (regcache, argreg, val);
952 /* Push item for later so that pushed arguments
953 come in the right order. */
954 si = push_stack_item (si, val, 4);
959 else if (len > (2 * 4))
961 /* Data passed by reference. Push copy of data onto stack
962 and pass pointer to this copy as argument. */
963 sp = (sp - len) & ~3;
964 write_memory (sp, val, len);
966 if (argreg <= ARG4_REGNUM)
968 regcache_cooked_write_unsigned (regcache, argreg, sp);
974 store_unsigned_integer (buf, 4, sp);
975 si = push_stack_item (si, buf, 4);
980 /* Data passed by value. No available registers. Put it on
982 si = push_stack_item (si, val, len);
988 /* fp_arg must be word-aligned (i.e., don't += len) to match
989 the function prologue. */
990 sp = (sp - si->len) & ~3;
991 write_memory (sp, si->data, si->len);
992 si = pop_stack_item (si);
995 /* Finally, update the SP register. */
996 regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp);
1001 static const struct frame_unwind cris_frame_unwind =
1005 cris_frame_prev_register,
1007 default_frame_sniffer
1011 cris_frame_base_address (struct frame_info *this_frame, void **this_cache)
1013 struct cris_unwind_cache *info
1014 = cris_frame_unwind_cache (this_frame, this_cache);
1018 static const struct frame_base cris_frame_base =
1021 cris_frame_base_address,
1022 cris_frame_base_address,
1023 cris_frame_base_address
1026 /* Frames information. The definition of the struct frame_info is
1030 enum frame_type type;
1034 If the compilation option -fno-omit-frame-pointer is present the
1035 variable frame will be set to the content of R8 which is the frame
1038 The variable pc contains the address where execution is performed
1039 in the present frame. The innermost frame contains the current content
1040 of the register PC. All other frames contain the content of the
1041 register PC in the next frame.
1043 The variable `type' indicates the frame's type: normal, SIGTRAMP
1044 (associated with a signal handler), dummy (associated with a dummy
1047 The variable return_pc contains the address where execution should be
1048 resumed when the present frame has finished, the return address.
1050 The variable leaf_function is 1 if the return address is in the register
1051 SRP, and 0 if it is on the stack.
1053 Prologue instructions C-code.
1054 The prologue may consist of (-fno-omit-frame-pointer)
1058 move.d sp,r8 move.d sp,r8
1060 movem rY,[sp] movem rY,[sp]
1061 move.S rZ,[r8-U] move.S rZ,[r8-U]
1063 where 1 is a non-terminal function, and 2 is a leaf-function.
1065 Note that this assumption is extremely brittle, and will break at the
1066 slightest change in GCC's prologue.
1068 If local variables are declared or register contents are saved on stack
1069 the subq-instruction will be present with X as the number of bytes
1070 needed for storage. The reshuffle with respect to r8 may be performed
1071 with any size S (b, w, d) and any of the general registers Z={0..13}.
1072 The offset U should be representable by a signed 8-bit value in all cases.
1073 Thus, the prefix word is assumed to be immediate byte offset mode followed
1074 by another word containing the instruction.
1083 Prologue instructions C++-code.
1084 Case 1) and 2) in the C-code may be followed by
1086 move.d r10,rS ; this
1090 move.S [r8+U],rZ ; P4
1092 if any of the call parameters are stored. The host expects these
1093 instructions to be executed in order to get the call parameters right. */
1095 /* Examine the prologue of a function. The variable ip is the address of
1096 the first instruction of the prologue. The variable limit is the address
1097 of the first instruction after the prologue. The variable fi contains the
1098 information in struct frame_info. The variable frameless_p controls whether
1099 the entire prologue is examined (0) or just enough instructions to
1100 determine that it is a prologue (1). */
1103 cris_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
1104 struct cris_unwind_cache *info)
1106 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1107 /* Present instruction. */
1108 unsigned short insn;
1110 /* Next instruction, lookahead. */
1111 unsigned short insn_next;
1114 /* Is there a push fp? */
1117 /* Number of byte on stack used for local variables and movem. */
1120 /* Highest register number in a movem. */
1123 /* move.d r<source_register>,rS */
1124 short source_register;
1129 /* This frame is with respect to a leaf until a push srp is found. */
1132 info->leaf_function = 1;
1135 /* Assume nothing on stack. */
1139 /* If we were called without a this_frame, that means we were called
1140 from cris_skip_prologue which already tried to find the end of the
1141 prologue through the symbol information. 64 instructions past current
1142 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
1143 limit = this_frame ? get_frame_pc (this_frame) : pc + 64;
1145 /* Find the prologue instructions. */
1146 while (pc > 0 && pc < limit)
1148 insn = read_memory_unsigned_integer (pc, 2);
1152 /* push <reg> 32 bit instruction */
1153 insn_next = read_memory_unsigned_integer (pc, 2);
1155 regno = cris_get_operand2 (insn_next);
1158 info->sp_offset += 4;
1160 /* This check, meant to recognize srp, used to be regno ==
1161 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
1162 if (insn_next == 0xBE7E)
1166 info->leaf_function = 0;
1169 else if (insn_next == 0x8FEE)
1174 info->r8_offset = info->sp_offset;
1178 else if (insn == 0x866E)
1183 info->uses_frame = 1;
1187 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1188 && cris_get_mode (insn) == 0x0000
1189 && cris_get_opcode (insn) == 0x000A)
1194 info->sp_offset += cris_get_quick_value (insn);
1197 else if (cris_get_mode (insn) == 0x0002
1198 && cris_get_opcode (insn) == 0x000F
1199 && cris_get_size (insn) == 0x0003
1200 && cris_get_operand1 (insn) == gdbarch_sp_regnum (gdbarch))
1202 /* movem r<regsave>,[sp] */
1203 regsave = cris_get_operand2 (insn);
1205 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1206 && ((insn & 0x0F00) >> 8) == 0x0001
1207 && (cris_get_signed_offset (insn) < 0))
1209 /* Immediate byte offset addressing prefix word with sp as base
1210 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1211 is between 64 and 128.
1212 movem r<regsave>,[sp=sp-<val>] */
1215 info->sp_offset += -cris_get_signed_offset (insn);
1217 insn_next = read_memory_unsigned_integer (pc, 2);
1219 if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE
1220 && cris_get_opcode (insn_next) == 0x000F
1221 && cris_get_size (insn_next) == 0x0003
1222 && cris_get_operand1 (insn_next) == gdbarch_sp_regnum
1225 regsave = cris_get_operand2 (insn_next);
1229 /* The prologue ended before the limit was reached. */
1234 else if (cris_get_mode (insn) == 0x0001
1235 && cris_get_opcode (insn) == 0x0009
1236 && cris_get_size (insn) == 0x0002)
1238 /* move.d r<10..13>,r<0..15> */
1239 source_register = cris_get_operand1 (insn);
1241 /* FIXME? In the glibc solibs, the prologue might contain something
1242 like (this example taken from relocate_doit):
1244 sub.d 0xfffef426,$r0
1245 which isn't covered by the source_register check below. Question
1246 is whether to add a check for this combo, or make better use of
1247 the limit variable instead. */
1248 if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM)
1250 /* The prologue ended before the limit was reached. */
1255 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1256 /* The size is a fixed-size. */
1257 && ((insn & 0x0F00) >> 8) == 0x0001
1258 /* A negative offset. */
1259 && (cris_get_signed_offset (insn) < 0))
1261 /* move.S rZ,[r8-U] (?) */
1262 insn_next = read_memory_unsigned_integer (pc, 2);
1264 regno = cris_get_operand2 (insn_next);
1265 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1266 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1267 && cris_get_opcode (insn_next) == 0x000F)
1269 /* move.S rZ,[r8-U] */
1274 /* The prologue ended before the limit was reached. */
1279 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1280 /* The size is a fixed-size. */
1281 && ((insn & 0x0F00) >> 8) == 0x0001
1282 /* A positive offset. */
1283 && (cris_get_signed_offset (insn) > 0))
1285 /* move.S [r8+U],rZ (?) */
1286 insn_next = read_memory_unsigned_integer (pc, 2);
1288 regno = cris_get_operand2 (insn_next);
1289 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1290 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1291 && cris_get_opcode (insn_next) == 0x0009
1292 && cris_get_operand1 (insn_next) == regno)
1294 /* move.S [r8+U],rZ */
1299 /* The prologue ended before the limit was reached. */
1306 /* The prologue ended before the limit was reached. */
1312 /* We only want to know the end of the prologue when this_frame and info
1313 are NULL (called from cris_skip_prologue i.e.). */
1314 if (this_frame == NULL && info == NULL)
1319 info->size = info->sp_offset;
1321 /* Compute the previous frame's stack pointer (which is also the
1322 frame's ID's stack address), and this frame's base pointer. */
1323 if (info->uses_frame)
1326 /* The SP was moved to the FP. This indicates that a new frame
1327 was created. Get THIS frame's FP value by unwinding it from
1329 this_base = get_frame_register_unsigned (this_frame, CRIS_FP_REGNUM);
1330 info->base = this_base;
1331 info->saved_regs[CRIS_FP_REGNUM].addr = info->base;
1333 /* The FP points at the last saved register. Adjust the FP back
1334 to before the first saved register giving the SP. */
1335 info->prev_sp = info->base + info->r8_offset;
1340 /* Assume that the FP is this frame's SP but with that pushed
1341 stack space added back. */
1342 this_base = get_frame_register_unsigned (this_frame,
1343 gdbarch_sp_regnum (gdbarch));
1344 info->base = this_base;
1345 info->prev_sp = info->base + info->size;
1348 /* Calculate the addresses for the saved registers on the stack. */
1349 /* FIXME: The address calculation should really be done on the fly while
1350 we're analyzing the prologue (we only hold one regsave value as it is
1352 val = info->sp_offset;
1354 for (regno = regsave; regno >= 0; regno--)
1356 info->saved_regs[regno].addr = info->base + info->r8_offset - val;
1360 /* The previous frame's SP needed to be computed. Save the computed
1362 trad_frame_set_value (info->saved_regs,
1363 gdbarch_sp_regnum (gdbarch), info->prev_sp);
1365 if (!info->leaf_function)
1367 /* SRP saved on the stack. But where? */
1368 if (info->r8_offset == 0)
1370 /* R8 not pushed yet. */
1371 info->saved_regs[SRP_REGNUM].addr = info->base;
1375 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1376 info->saved_regs[SRP_REGNUM].addr = info->base + 4;
1380 /* The PC is found in SRP (the actual register or located on the stack). */
1381 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1382 = info->saved_regs[SRP_REGNUM];
1388 crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
1389 struct cris_unwind_cache *info)
1391 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1394 /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not
1395 meant to be a full-fledged prologue scanner. It is only needed for
1396 the cases where we end up in code always lacking DWARF-2 CFI, notably:
1398 * PLT stubs (library calls)
1400 * signal trampolines
1402 For those cases, it is assumed that there is no actual prologue; that
1403 the stack pointer is not adjusted, and (as a consequence) the return
1404 address is not pushed onto the stack. */
1406 /* We only want to know the end of the prologue when this_frame and info
1407 are NULL (called from cris_skip_prologue i.e.). */
1408 if (this_frame == NULL && info == NULL)
1413 /* The SP is assumed to be unaltered. */
1414 this_base = get_frame_register_unsigned (this_frame,
1415 gdbarch_sp_regnum (gdbarch));
1416 info->base = this_base;
1417 info->prev_sp = this_base;
1419 /* The PC is assumed to be found in SRP. */
1420 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1421 = info->saved_regs[SRP_REGNUM];
1426 /* Advance pc beyond any function entry prologue instructions at pc
1427 to reach some "real" code. */
1429 /* Given a PC value corresponding to the start of a function, return the PC
1430 of the first instruction after the function prologue. */
1433 cris_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1435 CORE_ADDR func_addr, func_end;
1436 struct symtab_and_line sal;
1437 CORE_ADDR pc_after_prologue;
1439 /* If we have line debugging information, then the end of the prologue
1440 should the first assembly instruction of the first source line. */
1441 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1443 sal = find_pc_line (func_addr, 0);
1444 if (sal.end > 0 && sal.end < func_end)
1448 if (cris_version () == 32)
1449 pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL);
1451 pc_after_prologue = cris_scan_prologue (pc, NULL, NULL);
1453 return pc_after_prologue;
1457 cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1460 pc = frame_unwind_register_unsigned (next_frame,
1461 gdbarch_pc_regnum (gdbarch));
1466 cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1469 sp = frame_unwind_register_unsigned (next_frame,
1470 gdbarch_sp_regnum (gdbarch));
1474 /* Use the program counter to determine the contents and size of a breakpoint
1475 instruction. It returns a pointer to a string of bytes that encode a
1476 breakpoint instruction, stores the length of the string to *lenptr, and
1477 adjusts pcptr (if necessary) to point to the actual memory location where
1478 the breakpoint should be inserted. */
1480 static const unsigned char *
1481 cris_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
1483 static unsigned char break8_insn[] = {0x38, 0xe9};
1484 static unsigned char break15_insn[] = {0x3f, 0xe9};
1487 if (cris_mode () == cris_mode_guru)
1488 return break15_insn;
1493 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1497 cris_spec_reg_applicable (struct cris_spec_reg spec_reg)
1499 int version = cris_version ();
1501 switch (spec_reg.applicable_version)
1503 case cris_ver_version_all:
1505 case cris_ver_warning:
1506 /* Indeterminate/obsolete. */
1509 return (version >= 0 && version <= 3);
1511 return (version >= 3);
1513 return (version == 8 || version == 9);
1515 return (version >= 8);
1516 case cris_ver_v0_10:
1517 return (version >= 0 && version <= 10);
1518 case cris_ver_v3_10:
1519 return (version >= 3 && version <= 10);
1520 case cris_ver_v8_10:
1521 return (version >= 8 && version <= 10);
1523 return (version == 10);
1525 return (version >= 10);
1527 return (version >= 32);
1529 /* Invalid cris version. */
1534 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1535 register, -1 for an invalid register. */
1538 cris_register_size (struct gdbarch *gdbarch, int regno)
1540 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1544 if (regno >= 0 && regno < NUM_GENREGS)
1546 /* General registers (R0 - R15) are 32 bits. */
1549 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1551 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1552 Adjust regno accordingly. */
1553 spec_regno = regno - NUM_GENREGS;
1555 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1557 if (cris_spec_regs[i].number == spec_regno
1558 && cris_spec_reg_applicable (cris_spec_regs[i]))
1559 /* Go with the first applicable register. */
1560 return cris_spec_regs[i].reg_size;
1562 /* Special register not applicable to this CRIS version. */
1565 else if (regno >= gdbarch_pc_regnum (gdbarch)
1566 && regno < gdbarch_num_regs (gdbarch))
1568 /* This will apply to CRISv32 only where there are additional registers
1569 after the special registers (pseudo PC and support registers). */
1577 /* Nonzero if regno should not be fetched from the target. This is the case
1578 for unimplemented (size 0) and non-existant registers. */
1581 cris_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1583 return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1584 || (cris_register_size (gdbarch, regno) == 0));
1587 /* Nonzero if regno should not be written to the target, for various
1591 cris_cannot_store_register (struct gdbarch *gdbarch, int regno)
1593 /* There are three kinds of registers we refuse to write to.
1594 1. Those that not implemented.
1595 2. Those that are read-only (depends on the processor mode).
1596 3. Those registers to which a write has no effect.
1600 || regno >= gdbarch_num_regs (gdbarch)
1601 || cris_register_size (gdbarch, regno) == 0)
1602 /* Not implemented. */
1605 else if (regno == VR_REGNUM)
1609 else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM)
1610 /* Writing has no effect. */
1613 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
1614 agent decide whether they are writable. */
1619 /* Nonzero if regno should not be fetched from the target. This is the case
1620 for unimplemented (size 0) and non-existant registers. */
1623 crisv32_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1625 return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1626 || (cris_register_size (gdbarch, regno) == 0));
1629 /* Nonzero if regno should not be written to the target, for various
1633 crisv32_cannot_store_register (struct gdbarch *gdbarch, int regno)
1635 /* There are three kinds of registers we refuse to write to.
1636 1. Those that not implemented.
1637 2. Those that are read-only (depends on the processor mode).
1638 3. Those registers to which a write has no effect.
1642 || regno >= gdbarch_num_regs (gdbarch)
1643 || cris_register_size (gdbarch, regno) == 0)
1644 /* Not implemented. */
1647 else if (regno == VR_REGNUM)
1651 else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM)
1652 /* Writing has no effect. */
1655 /* Many special registers are read-only in user mode. Let the debug
1656 agent decide whether they are writable. */
1661 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1662 of data in register regno. */
1664 static struct type *
1665 cris_register_type (struct gdbarch *gdbarch, int regno)
1667 if (regno == gdbarch_pc_regnum (gdbarch))
1668 return builtin_type_void_func_ptr;
1669 else if (regno == gdbarch_sp_regnum (gdbarch)
1670 || regno == CRIS_FP_REGNUM)
1671 return builtin_type_void_data_ptr;
1672 else if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1673 || (regno >= MOF_REGNUM && regno <= USP_REGNUM))
1674 /* Note: R8 taken care of previous clause. */
1675 return builtin_type_uint32;
1676 else if (regno >= P4_REGNUM && regno <= CCR_REGNUM)
1677 return builtin_type_uint16;
1678 else if (regno >= P0_REGNUM && regno <= VR_REGNUM)
1679 return builtin_type_uint8;
1681 /* Invalid (unimplemented) register. */
1682 return builtin_type_int0;
1685 static struct type *
1686 crisv32_register_type (struct gdbarch *gdbarch, int regno)
1688 if (regno == gdbarch_pc_regnum (gdbarch))
1689 return builtin_type_void_func_ptr;
1690 else if (regno == gdbarch_sp_regnum (gdbarch)
1691 || regno == CRIS_FP_REGNUM)
1692 return builtin_type_void_data_ptr;
1693 else if ((regno >= 0 && regno <= ACR_REGNUM)
1694 || (regno >= EXS_REGNUM && regno <= SPC_REGNUM)
1695 || (regno == PID_REGNUM)
1696 || (regno >= S0_REGNUM && regno <= S15_REGNUM))
1697 /* Note: R8 and SP taken care of by previous clause. */
1698 return builtin_type_uint32;
1699 else if (regno == WZ_REGNUM)
1700 return builtin_type_uint16;
1701 else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM)
1702 return builtin_type_uint8;
1705 /* Invalid (unimplemented) register. Should not happen as there are
1706 no unimplemented CRISv32 registers. */
1707 warning (_("crisv32_register_type: unknown regno %d"), regno);
1708 return builtin_type_int0;
1712 /* Stores a function return value of type type, where valbuf is the address
1713 of the value to be stored. */
1715 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1718 cris_store_return_value (struct type *type, struct regcache *regcache,
1722 int len = TYPE_LENGTH (type);
1726 /* Put the return value in R10. */
1727 val = extract_unsigned_integer (valbuf, len);
1728 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1732 /* Put the return value in R10 and R11. */
1733 val = extract_unsigned_integer (valbuf, 4);
1734 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1735 val = extract_unsigned_integer ((char *)valbuf + 4, len - 4);
1736 regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val);
1739 error (_("cris_store_return_value: type length too large."));
1742 /* Return the name of register regno as a string. Return NULL for an invalid or
1743 unimplemented register. */
1746 cris_special_register_name (int regno)
1751 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1752 Adjust regno accordingly. */
1753 spec_regno = regno - NUM_GENREGS;
1755 /* Assume nothing about the layout of the cris_spec_regs struct
1757 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1759 if (cris_spec_regs[i].number == spec_regno
1760 && cris_spec_reg_applicable (cris_spec_regs[i]))
1761 /* Go with the first applicable register. */
1762 return cris_spec_regs[i].name;
1764 /* Special register not applicable to this CRIS version. */
1769 cris_register_name (struct gdbarch *gdbarch, int regno)
1771 static char *cris_genreg_names[] =
1772 { "r0", "r1", "r2", "r3", \
1773 "r4", "r5", "r6", "r7", \
1774 "r8", "r9", "r10", "r11", \
1775 "r12", "r13", "sp", "pc" };
1777 if (regno >= 0 && regno < NUM_GENREGS)
1779 /* General register. */
1780 return cris_genreg_names[regno];
1782 else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (gdbarch))
1784 return cris_special_register_name (regno);
1788 /* Invalid register. */
1794 crisv32_register_name (struct gdbarch *gdbarch, int regno)
1796 static char *crisv32_genreg_names[] =
1797 { "r0", "r1", "r2", "r3", \
1798 "r4", "r5", "r6", "r7", \
1799 "r8", "r9", "r10", "r11", \
1800 "r12", "r13", "sp", "acr"
1803 static char *crisv32_sreg_names[] =
1804 { "s0", "s1", "s2", "s3", \
1805 "s4", "s5", "s6", "s7", \
1806 "s8", "s9", "s10", "s11", \
1807 "s12", "s13", "s14", "s15"
1810 if (regno >= 0 && regno < NUM_GENREGS)
1812 /* General register. */
1813 return crisv32_genreg_names[regno];
1815 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1817 return cris_special_register_name (regno);
1819 else if (regno == gdbarch_pc_regnum (gdbarch))
1823 else if (regno >= S0_REGNUM && regno <= S15_REGNUM)
1825 return crisv32_sreg_names[regno - S0_REGNUM];
1829 /* Invalid register. */
1834 /* Convert DWARF register number REG to the appropriate register
1835 number used by GDB. */
1838 cris_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1840 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1841 numbering, MOF is 18).
1842 Adapted from gcc/config/cris/cris.h. */
1843 static int cris_dwarf_regmap[] = {
1855 if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap))
1856 regnum = cris_dwarf_regmap[reg];
1859 warning (_("Unmapped DWARF Register #%d encountered."), reg);
1864 /* DWARF-2 frame support. */
1867 cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1868 struct dwarf2_frame_state_reg *reg,
1869 struct frame_info *this_frame)
1871 /* The return address column. */
1872 if (regnum == gdbarch_pc_regnum (gdbarch))
1873 reg->how = DWARF2_FRAME_REG_RA;
1875 /* The call frame address. */
1876 else if (regnum == gdbarch_sp_regnum (gdbarch))
1877 reg->how = DWARF2_FRAME_REG_CFA;
1880 /* Extract from an array regbuf containing the raw register state a function
1881 return value of type type, and copy that, in virtual format, into
1884 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1887 cris_extract_return_value (struct type *type, struct regcache *regcache,
1891 int len = TYPE_LENGTH (type);
1895 /* Get the return value from R10. */
1896 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1897 store_unsigned_integer (valbuf, len, val);
1901 /* Get the return value from R10 and R11. */
1902 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1903 store_unsigned_integer (valbuf, 4, val);
1904 regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val);
1905 store_unsigned_integer ((char *)valbuf + 4, len - 4, val);
1908 error (_("cris_extract_return_value: type length too large"));
1911 /* Handle the CRIS return value convention. */
1913 static enum return_value_convention
1914 cris_return_value (struct gdbarch *gdbarch, struct type *func_type,
1915 struct type *type, struct regcache *regcache,
1916 gdb_byte *readbuf, const gdb_byte *writebuf)
1918 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1919 || TYPE_CODE (type) == TYPE_CODE_UNION
1920 || TYPE_LENGTH (type) > 8)
1921 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1922 goes on the stack. */
1923 return RETURN_VALUE_STRUCT_CONVENTION;
1926 cris_extract_return_value (type, regcache, readbuf);
1928 cris_store_return_value (type, regcache, writebuf);
1930 return RETURN_VALUE_REGISTER_CONVENTION;
1933 /* Calculates a value that measures how good inst_args constraints an
1934 instruction. It stems from cris_constraint, found in cris-dis.c. */
1937 constraint (unsigned int insn, const signed char *inst_args,
1938 inst_env_type *inst_env)
1943 const char *s = inst_args;
1949 if ((insn & 0x30) == 0x30)
1954 /* A prefix operand. */
1955 if (inst_env->prefix_found)
1961 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1962 valid "push" size. In case of special register, it may be != 4. */
1963 if (inst_env->prefix_found)
1969 retval = (((insn >> 0xC) & 0xF) == (insn & 0xF));
1977 tmp = (insn >> 0xC) & 0xF;
1979 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1981 /* Since we match four bits, we will give a value of
1982 4 - 1 = 3 in a match. If there is a corresponding
1983 exact match of a special register in another pattern, it
1984 will get a value of 4, which will be higher. This should
1985 be correct in that an exact pattern would match better that
1987 Note that there is a reason for not returning zero; the
1988 pattern for "clear" is partly matched in the bit-pattern
1989 (the two lower bits must be zero), while the bit-pattern
1990 for a move from a special register is matched in the
1991 register constraint.
1992 This also means we will will have a race condition if
1993 there is a partly match in three bits in the bit pattern. */
1994 if (tmp == cris_spec_regs[i].number)
2001 if (cris_spec_regs[i].name == NULL)
2008 /* Returns the number of bits set in the variable value. */
2011 number_of_bits (unsigned int value)
2013 int number_of_bits = 0;
2017 number_of_bits += 1;
2018 value &= (value - 1);
2020 return number_of_bits;
2023 /* Finds the address that should contain the single step breakpoint(s).
2024 It stems from code in cris-dis.c. */
2027 find_cris_op (unsigned short insn, inst_env_type *inst_env)
2030 int max_level_of_match = -1;
2031 int max_matched = -1;
2034 for (i = 0; cris_opcodes[i].name != NULL; i++)
2036 if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match)
2037 && ((cris_opcodes[i].lose & insn) == 0)
2038 /* Only CRISv10 instructions, please. */
2039 && (cris_opcodes[i].applicable_version != cris_ver_v32p))
2041 level_of_match = constraint (insn, cris_opcodes[i].args, inst_env);
2042 if (level_of_match >= 0)
2045 number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose);
2046 if (level_of_match > max_level_of_match)
2049 max_level_of_match = level_of_match;
2050 if (level_of_match == 16)
2052 /* All bits matched, cannot find better. */
2062 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
2063 actually an internal error. */
2066 find_step_target (struct frame_info *frame, inst_env_type *inst_env)
2070 unsigned short insn;
2071 struct gdbarch *gdbarch = get_frame_arch (frame);
2073 /* Create a local register image and set the initial state. */
2074 for (i = 0; i < NUM_GENREGS; i++)
2077 (unsigned long) get_frame_register_unsigned (frame, i);
2079 offset = NUM_GENREGS;
2080 for (i = 0; i < NUM_SPECREGS; i++)
2083 (unsigned long) get_frame_register_unsigned (frame, offset + i);
2085 inst_env->branch_found = 0;
2086 inst_env->slot_needed = 0;
2087 inst_env->delay_slot_pc_active = 0;
2088 inst_env->prefix_found = 0;
2089 inst_env->invalid = 0;
2090 inst_env->xflag_found = 0;
2091 inst_env->disable_interrupt = 0;
2093 /* Look for a step target. */
2096 /* Read an instruction from the client. */
2097 insn = read_memory_unsigned_integer
2098 (inst_env->reg[gdbarch_pc_regnum (gdbarch)], 2);
2100 /* If the instruction is not in a delay slot the new content of the
2101 PC is [PC] + 2. If the instruction is in a delay slot it is not
2102 that simple. Since a instruction in a delay slot cannot change
2103 the content of the PC, it does not matter what value PC will have.
2104 Just make sure it is a valid instruction. */
2105 if (!inst_env->delay_slot_pc_active)
2107 inst_env->reg[gdbarch_pc_regnum (gdbarch)] += 2;
2111 inst_env->delay_slot_pc_active = 0;
2112 inst_env->reg[gdbarch_pc_regnum (gdbarch)]
2113 = inst_env->delay_slot_pc;
2115 /* Analyse the present instruction. */
2116 i = find_cris_op (insn, inst_env);
2119 inst_env->invalid = 1;
2123 cris_gdb_func (gdbarch, cris_opcodes[i].op, insn, inst_env);
2125 } while (!inst_env->invalid
2126 && (inst_env->prefix_found || inst_env->xflag_found
2127 || inst_env->slot_needed));
2131 /* There is no hardware single-step support. The function find_step_target
2132 digs through the opcodes in order to find all possible targets.
2133 Either one ordinary target or two targets for branches may be found. */
2136 cris_software_single_step (struct frame_info *frame)
2138 inst_env_type inst_env;
2140 /* Analyse the present instruction environment and insert
2142 int status = find_step_target (frame, &inst_env);
2145 /* Could not find a target. Things are likely to go downhill
2147 warning (_("CRIS software single step could not find a step target."));
2151 /* Insert at most two breakpoints. One for the next PC content
2152 and possibly another one for a branch, jump, etc. */
2154 (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (get_frame_arch (frame))];
2155 insert_single_step_breakpoint (next_pc);
2156 if (inst_env.branch_found
2157 && (CORE_ADDR) inst_env.branch_break_address != next_pc)
2159 CORE_ADDR branch_target_address
2160 = (CORE_ADDR) inst_env.branch_break_address;
2161 insert_single_step_breakpoint (branch_target_address);
2168 /* Calculates the prefix value for quick offset addressing mode. */
2171 quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2173 /* It's invalid to be in a delay slot. You can't have a prefix to this
2174 instruction (not 100% sure). */
2175 if (inst_env->slot_needed || inst_env->prefix_found)
2177 inst_env->invalid = 1;
2181 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2182 inst_env->prefix_value += cris_get_bdap_quick_offset (inst);
2184 /* A prefix doesn't change the xflag_found. But the rest of the flags
2186 inst_env->slot_needed = 0;
2187 inst_env->prefix_found = 1;
2190 /* Updates the autoincrement register. The size of the increment is derived
2191 from the size of the operation. The PC is always kept aligned on even
2195 process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env)
2197 if (size == INST_BYTE_SIZE)
2199 inst_env->reg[cris_get_operand1 (inst)] += 1;
2201 /* The PC must be word aligned, so increase the PC with one
2202 word even if the size is byte. */
2203 if (cris_get_operand1 (inst) == REG_PC)
2205 inst_env->reg[REG_PC] += 1;
2208 else if (size == INST_WORD_SIZE)
2210 inst_env->reg[cris_get_operand1 (inst)] += 2;
2212 else if (size == INST_DWORD_SIZE)
2214 inst_env->reg[cris_get_operand1 (inst)] += 4;
2219 inst_env->invalid = 1;
2223 /* Just a forward declaration. */
2225 static unsigned long get_data_from_address (unsigned short *inst,
2228 /* Calculates the prefix value for the general case of offset addressing
2232 bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2237 /* It's invalid to be in a delay slot. */
2238 if (inst_env->slot_needed || inst_env->prefix_found)
2240 inst_env->invalid = 1;
2244 /* The calculation of prefix_value used to be after process_autoincrement,
2245 but that fails for an instruction such as jsr [$r0+12] which is encoded
2246 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
2247 mustn't be incremented until we have read it and what it points at. */
2248 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2250 /* The offset is an indirection of the contents of the operand1 register. */
2251 inst_env->prefix_value +=
2252 get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)]);
2254 if (cris_get_mode (inst) == AUTOINC_MODE)
2256 process_autoincrement (cris_get_size (inst), inst, inst_env);
2259 /* A prefix doesn't change the xflag_found. But the rest of the flags
2261 inst_env->slot_needed = 0;
2262 inst_env->prefix_found = 1;
2265 /* Calculates the prefix value for the index addressing mode. */
2268 biap_prefix (unsigned short inst, inst_env_type *inst_env)
2270 /* It's invalid to be in a delay slot. I can't see that it's possible to
2271 have a prefix to this instruction. So I will treat this as invalid. */
2272 if (inst_env->slot_needed || inst_env->prefix_found)
2274 inst_env->invalid = 1;
2278 inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)];
2280 /* The offset is the operand2 value shifted the size of the instruction
2282 inst_env->prefix_value +=
2283 inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst);
2285 /* If the PC is operand1 (base) the address used is the address after
2286 the main instruction, i.e. address + 2 (the PC is already compensated
2287 for the prefix operation). */
2288 if (cris_get_operand1 (inst) == REG_PC)
2290 inst_env->prefix_value += 2;
2293 /* A prefix doesn't change the xflag_found. But the rest of the flags
2295 inst_env->slot_needed = 0;
2296 inst_env->xflag_found = 0;
2297 inst_env->prefix_found = 1;
2300 /* Calculates the prefix value for the double indirect addressing mode. */
2303 dip_prefix (unsigned short inst, inst_env_type *inst_env)
2308 /* It's invalid to be in a delay slot. */
2309 if (inst_env->slot_needed || inst_env->prefix_found)
2311 inst_env->invalid = 1;
2315 /* The prefix value is one dereference of the contents of the operand1
2317 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2318 inst_env->prefix_value = read_memory_unsigned_integer (address, 4);
2320 /* Check if the mode is autoincrement. */
2321 if (cris_get_mode (inst) == AUTOINC_MODE)
2323 inst_env->reg[cris_get_operand1 (inst)] += 4;
2326 /* A prefix doesn't change the xflag_found. But the rest of the flags
2328 inst_env->slot_needed = 0;
2329 inst_env->xflag_found = 0;
2330 inst_env->prefix_found = 1;
2333 /* Finds the destination for a branch with 8-bits offset. */
2336 eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2341 /* If we have a prefix or are in a delay slot it's bad. */
2342 if (inst_env->slot_needed || inst_env->prefix_found)
2344 inst_env->invalid = 1;
2348 /* We have a branch, find out where the branch will land. */
2349 offset = cris_get_branch_short_offset (inst);
2351 /* Check if the offset is signed. */
2352 if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK)
2357 /* The offset ends with the sign bit, set it to zero. The address
2358 should always be word aligned. */
2359 offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK;
2361 inst_env->branch_found = 1;
2362 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2364 inst_env->slot_needed = 1;
2365 inst_env->prefix_found = 0;
2366 inst_env->xflag_found = 0;
2367 inst_env->disable_interrupt = 1;
2370 /* Finds the destination for a branch with 16-bits offset. */
2373 sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2377 /* If we have a prefix or is in a delay slot it's bad. */
2378 if (inst_env->slot_needed || inst_env->prefix_found)
2380 inst_env->invalid = 1;
2384 /* We have a branch, find out the offset for the branch. */
2385 offset = read_memory_integer (inst_env->reg[REG_PC], 2);
2387 /* The instruction is one word longer than normal, so add one word
2389 inst_env->reg[REG_PC] += 2;
2391 inst_env->branch_found = 1;
2392 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2395 inst_env->slot_needed = 1;
2396 inst_env->prefix_found = 0;
2397 inst_env->xflag_found = 0;
2398 inst_env->disable_interrupt = 1;
2401 /* Handles the ABS instruction. */
2404 abs_op (unsigned short inst, inst_env_type *inst_env)
2409 /* ABS can't have a prefix, so it's bad if it does. */
2410 if (inst_env->prefix_found)
2412 inst_env->invalid = 1;
2416 /* Check if the operation affects the PC. */
2417 if (cris_get_operand2 (inst) == REG_PC)
2420 /* It's invalid to change to the PC if we are in a delay slot. */
2421 if (inst_env->slot_needed)
2423 inst_env->invalid = 1;
2427 value = (long) inst_env->reg[REG_PC];
2429 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
2430 if (value != SIGNED_DWORD_MASK)
2433 inst_env->reg[REG_PC] = (long) value;
2437 inst_env->slot_needed = 0;
2438 inst_env->prefix_found = 0;
2439 inst_env->xflag_found = 0;
2440 inst_env->disable_interrupt = 0;
2443 /* Handles the ADDI instruction. */
2446 addi_op (unsigned short inst, inst_env_type *inst_env)
2448 /* It's invalid to have the PC as base register. And ADDI can't have
2450 if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC))
2452 inst_env->invalid = 1;
2456 inst_env->slot_needed = 0;
2457 inst_env->prefix_found = 0;
2458 inst_env->xflag_found = 0;
2459 inst_env->disable_interrupt = 0;
2462 /* Handles the ASR instruction. */
2465 asr_op (unsigned short inst, inst_env_type *inst_env)
2468 unsigned long value;
2469 unsigned long signed_extend_mask = 0;
2471 /* ASR can't have a prefix, so check that it doesn't. */
2472 if (inst_env->prefix_found)
2474 inst_env->invalid = 1;
2478 /* Check if the PC is the target register. */
2479 if (cris_get_operand2 (inst) == REG_PC)
2481 /* It's invalid to change the PC in a delay slot. */
2482 if (inst_env->slot_needed)
2484 inst_env->invalid = 1;
2487 /* Get the number of bits to shift. */
2488 shift_steps = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]);
2489 value = inst_env->reg[REG_PC];
2491 /* Find out how many bits the operation should apply to. */
2492 if (cris_get_size (inst) == INST_BYTE_SIZE)
2494 if (value & SIGNED_BYTE_MASK)
2496 signed_extend_mask = 0xFF;
2497 signed_extend_mask = signed_extend_mask >> shift_steps;
2498 signed_extend_mask = ~signed_extend_mask;
2500 value = value >> shift_steps;
2501 value |= signed_extend_mask;
2503 inst_env->reg[REG_PC] &= 0xFFFFFF00;
2504 inst_env->reg[REG_PC] |= value;
2506 else if (cris_get_size (inst) == INST_WORD_SIZE)
2508 if (value & SIGNED_WORD_MASK)
2510 signed_extend_mask = 0xFFFF;
2511 signed_extend_mask = signed_extend_mask >> shift_steps;
2512 signed_extend_mask = ~signed_extend_mask;
2514 value = value >> shift_steps;
2515 value |= signed_extend_mask;
2517 inst_env->reg[REG_PC] &= 0xFFFF0000;
2518 inst_env->reg[REG_PC] |= value;
2520 else if (cris_get_size (inst) == INST_DWORD_SIZE)
2522 if (value & SIGNED_DWORD_MASK)
2524 signed_extend_mask = 0xFFFFFFFF;
2525 signed_extend_mask = signed_extend_mask >> shift_steps;
2526 signed_extend_mask = ~signed_extend_mask;
2528 value = value >> shift_steps;
2529 value |= signed_extend_mask;
2530 inst_env->reg[REG_PC] = value;
2533 inst_env->slot_needed = 0;
2534 inst_env->prefix_found = 0;
2535 inst_env->xflag_found = 0;
2536 inst_env->disable_interrupt = 0;
2539 /* Handles the ASRQ instruction. */
2542 asrq_op (unsigned short inst, inst_env_type *inst_env)
2546 unsigned long value;
2547 unsigned long signed_extend_mask = 0;
2549 /* ASRQ can't have a prefix, so check that it doesn't. */
2550 if (inst_env->prefix_found)
2552 inst_env->invalid = 1;
2556 /* Check if the PC is the target register. */
2557 if (cris_get_operand2 (inst) == REG_PC)
2560 /* It's invalid to change the PC in a delay slot. */
2561 if (inst_env->slot_needed)
2563 inst_env->invalid = 1;
2566 /* The shift size is given as a 5 bit quick value, i.e. we don't
2567 want the the sign bit of the quick value. */
2568 shift_steps = cris_get_asr_shift_steps (inst);
2569 value = inst_env->reg[REG_PC];
2570 if (value & SIGNED_DWORD_MASK)
2572 signed_extend_mask = 0xFFFFFFFF;
2573 signed_extend_mask = signed_extend_mask >> shift_steps;
2574 signed_extend_mask = ~signed_extend_mask;
2576 value = value >> shift_steps;
2577 value |= signed_extend_mask;
2578 inst_env->reg[REG_PC] = value;
2580 inst_env->slot_needed = 0;
2581 inst_env->prefix_found = 0;
2582 inst_env->xflag_found = 0;
2583 inst_env->disable_interrupt = 0;
2586 /* Handles the AX, EI and SETF instruction. */
2589 ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env)
2591 if (inst_env->prefix_found)
2593 inst_env->invalid = 1;
2596 /* Check if the instruction is setting the X flag. */
2597 if (cris_is_xflag_bit_on (inst))
2599 inst_env->xflag_found = 1;
2603 inst_env->xflag_found = 0;
2605 inst_env->slot_needed = 0;
2606 inst_env->prefix_found = 0;
2607 inst_env->disable_interrupt = 1;
2610 /* Checks if the instruction is in assign mode. If so, it updates the assign
2611 register. Note that check_assign assumes that the caller has checked that
2612 there is a prefix to this instruction. The mode check depends on this. */
2615 check_assign (unsigned short inst, inst_env_type *inst_env)
2617 /* Check if it's an assign addressing mode. */
2618 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2620 /* Assign the prefix value to operand 1. */
2621 inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value;
2625 /* Handles the 2-operand BOUND instruction. */
2628 two_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2630 /* It's invalid to have the PC as the index operand. */
2631 if (cris_get_operand2 (inst) == REG_PC)
2633 inst_env->invalid = 1;
2636 /* Check if we have a prefix. */
2637 if (inst_env->prefix_found)
2639 check_assign (inst, inst_env);
2641 /* Check if this is an autoincrement mode. */
2642 else if (cris_get_mode (inst) == AUTOINC_MODE)
2644 /* It's invalid to change the PC in a delay slot. */
2645 if (inst_env->slot_needed)
2647 inst_env->invalid = 1;
2650 process_autoincrement (cris_get_size (inst), inst, inst_env);
2652 inst_env->slot_needed = 0;
2653 inst_env->prefix_found = 0;
2654 inst_env->xflag_found = 0;
2655 inst_env->disable_interrupt = 0;
2658 /* Handles the 3-operand BOUND instruction. */
2661 three_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2663 /* It's an error if we haven't got a prefix. And it's also an error
2664 if the PC is the destination register. */
2665 if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC))
2667 inst_env->invalid = 1;
2670 inst_env->slot_needed = 0;
2671 inst_env->prefix_found = 0;
2672 inst_env->xflag_found = 0;
2673 inst_env->disable_interrupt = 0;
2676 /* Clears the status flags in inst_env. */
2679 btst_nop_op (unsigned short inst, inst_env_type *inst_env)
2681 /* It's an error if we have got a prefix. */
2682 if (inst_env->prefix_found)
2684 inst_env->invalid = 1;
2688 inst_env->slot_needed = 0;
2689 inst_env->prefix_found = 0;
2690 inst_env->xflag_found = 0;
2691 inst_env->disable_interrupt = 0;
2694 /* Clears the status flags in inst_env. */
2697 clearf_di_op (unsigned short inst, inst_env_type *inst_env)
2699 /* It's an error if we have got a prefix. */
2700 if (inst_env->prefix_found)
2702 inst_env->invalid = 1;
2706 inst_env->slot_needed = 0;
2707 inst_env->prefix_found = 0;
2708 inst_env->xflag_found = 0;
2709 inst_env->disable_interrupt = 1;
2712 /* Handles the CLEAR instruction if it's in register mode. */
2715 reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env)
2717 /* Check if the target is the PC. */
2718 if (cris_get_operand2 (inst) == REG_PC)
2720 /* The instruction will clear the instruction's size bits. */
2721 int clear_size = cris_get_clear_size (inst);
2722 if (clear_size == INST_BYTE_SIZE)
2724 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00;
2726 if (clear_size == INST_WORD_SIZE)
2728 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000;
2730 if (clear_size == INST_DWORD_SIZE)
2732 inst_env->delay_slot_pc = 0x0;
2734 /* The jump will be delayed with one delay slot. So we need a delay
2736 inst_env->slot_needed = 1;
2737 inst_env->delay_slot_pc_active = 1;
2741 /* The PC will not change => no delay slot. */
2742 inst_env->slot_needed = 0;
2744 inst_env->prefix_found = 0;
2745 inst_env->xflag_found = 0;
2746 inst_env->disable_interrupt = 0;
2749 /* Handles the TEST instruction if it's in register mode. */
2752 reg_mode_test_op (unsigned short inst, inst_env_type *inst_env)
2754 /* It's an error if we have got a prefix. */
2755 if (inst_env->prefix_found)
2757 inst_env->invalid = 1;
2760 inst_env->slot_needed = 0;
2761 inst_env->prefix_found = 0;
2762 inst_env->xflag_found = 0;
2763 inst_env->disable_interrupt = 0;
2767 /* Handles the CLEAR and TEST instruction if the instruction isn't
2768 in register mode. */
2771 none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env)
2773 /* Check if we are in a prefix mode. */
2774 if (inst_env->prefix_found)
2776 /* The only way the PC can change is if this instruction is in
2777 assign addressing mode. */
2778 check_assign (inst, inst_env);
2780 /* Indirect mode can't change the PC so just check if the mode is
2782 else if (cris_get_mode (inst) == AUTOINC_MODE)
2784 process_autoincrement (cris_get_size (inst), inst, inst_env);
2786 inst_env->slot_needed = 0;
2787 inst_env->prefix_found = 0;
2788 inst_env->xflag_found = 0;
2789 inst_env->disable_interrupt = 0;
2792 /* Checks that the PC isn't the destination register or the instructions has
2796 dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env)
2798 /* It's invalid to have the PC as the destination. The instruction can't
2800 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2802 inst_env->invalid = 1;
2806 inst_env->slot_needed = 0;
2807 inst_env->prefix_found = 0;
2808 inst_env->xflag_found = 0;
2809 inst_env->disable_interrupt = 0;
2812 /* Checks that the instruction doesn't have a prefix. */
2815 break_op (unsigned short inst, inst_env_type *inst_env)
2817 /* The instruction can't have a prefix. */
2818 if (inst_env->prefix_found)
2820 inst_env->invalid = 1;
2824 inst_env->slot_needed = 0;
2825 inst_env->prefix_found = 0;
2826 inst_env->xflag_found = 0;
2827 inst_env->disable_interrupt = 1;
2830 /* Checks that the PC isn't the destination register and that the instruction
2831 doesn't have a prefix. */
2834 scc_op (unsigned short inst, inst_env_type *inst_env)
2836 /* It's invalid to have the PC as the destination. The instruction can't
2838 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2840 inst_env->invalid = 1;
2844 inst_env->slot_needed = 0;
2845 inst_env->prefix_found = 0;
2846 inst_env->xflag_found = 0;
2847 inst_env->disable_interrupt = 1;
2850 /* Handles the register mode JUMP instruction. */
2853 reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2855 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2856 you can't have a prefix. */
2857 if ((inst_env->slot_needed) || (inst_env->prefix_found))
2859 inst_env->invalid = 1;
2863 /* Just change the PC. */
2864 inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)];
2865 inst_env->slot_needed = 0;
2866 inst_env->prefix_found = 0;
2867 inst_env->xflag_found = 0;
2868 inst_env->disable_interrupt = 1;
2871 /* Handles the JUMP instruction for all modes except register. */
2874 none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2876 unsigned long newpc;
2879 /* It's invalid to do a JUMP in a delay slot. */
2880 if (inst_env->slot_needed)
2882 inst_env->invalid = 1;
2886 /* Check if we have a prefix. */
2887 if (inst_env->prefix_found)
2889 check_assign (inst, inst_env);
2891 /* Get the new value for the the PC. */
2893 read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value,
2898 /* Get the new value for the PC. */
2899 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2900 newpc = read_memory_unsigned_integer (address, 4);
2902 /* Check if we should increment a register. */
2903 if (cris_get_mode (inst) == AUTOINC_MODE)
2905 inst_env->reg[cris_get_operand1 (inst)] += 4;
2908 inst_env->reg[REG_PC] = newpc;
2910 inst_env->slot_needed = 0;
2911 inst_env->prefix_found = 0;
2912 inst_env->xflag_found = 0;
2913 inst_env->disable_interrupt = 1;
2916 /* Handles moves to special registers (aka P-register) for all modes. */
2919 move_to_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2920 inst_env_type *inst_env)
2922 if (inst_env->prefix_found)
2924 /* The instruction has a prefix that means we are only interested if
2925 the instruction is in assign mode. */
2926 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2928 /* The prefix handles the problem if we are in a delay slot. */
2929 if (cris_get_operand1 (inst) == REG_PC)
2931 /* Just take care of the assign. */
2932 check_assign (inst, inst_env);
2936 else if (cris_get_mode (inst) == AUTOINC_MODE)
2938 /* The instruction doesn't have a prefix, the only case left that we
2939 are interested in is the autoincrement mode. */
2940 if (cris_get_operand1 (inst) == REG_PC)
2942 /* If the PC is to be incremented it's invalid to be in a
2944 if (inst_env->slot_needed)
2946 inst_env->invalid = 1;
2950 /* The increment depends on the size of the special register. */
2951 if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
2953 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2955 else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
2957 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2961 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2965 inst_env->slot_needed = 0;
2966 inst_env->prefix_found = 0;
2967 inst_env->xflag_found = 0;
2968 inst_env->disable_interrupt = 1;
2971 /* Handles moves from special registers (aka P-register) for all modes
2975 none_reg_mode_move_from_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2976 inst_env_type *inst_env)
2978 if (inst_env->prefix_found)
2980 /* The instruction has a prefix that means we are only interested if
2981 the instruction is in assign mode. */
2982 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2984 /* The prefix handles the problem if we are in a delay slot. */
2985 if (cris_get_operand1 (inst) == REG_PC)
2987 /* Just take care of the assign. */
2988 check_assign (inst, inst_env);
2992 /* The instruction doesn't have a prefix, the only case left that we
2993 are interested in is the autoincrement mode. */
2994 else if (cris_get_mode (inst) == AUTOINC_MODE)
2996 if (cris_get_operand1 (inst) == REG_PC)
2998 /* If the PC is to be incremented it's invalid to be in a
3000 if (inst_env->slot_needed)
3002 inst_env->invalid = 1;
3006 /* The increment depends on the size of the special register. */
3007 if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
3009 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
3011 else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
3013 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
3017 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
3021 inst_env->slot_needed = 0;
3022 inst_env->prefix_found = 0;
3023 inst_env->xflag_found = 0;
3024 inst_env->disable_interrupt = 1;
3027 /* Handles moves from special registers (aka P-register) when the mode
3031 reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env)
3033 /* Register mode move from special register can't have a prefix. */
3034 if (inst_env->prefix_found)
3036 inst_env->invalid = 1;
3040 if (cris_get_operand1 (inst) == REG_PC)
3042 /* It's invalid to change the PC in a delay slot. */
3043 if (inst_env->slot_needed)
3045 inst_env->invalid = 1;
3048 /* The destination is the PC, the jump will have a delay slot. */
3049 inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)];
3050 inst_env->slot_needed = 1;
3051 inst_env->delay_slot_pc_active = 1;
3055 /* If the destination isn't PC, there will be no jump. */
3056 inst_env->slot_needed = 0;
3058 inst_env->prefix_found = 0;
3059 inst_env->xflag_found = 0;
3060 inst_env->disable_interrupt = 1;
3063 /* Handles the MOVEM from memory to general register instruction. */
3066 move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env)
3068 if (inst_env->prefix_found)
3070 /* The prefix handles the problem if we are in a delay slot. Is the
3071 MOVEM instruction going to change the PC? */
3072 if (cris_get_operand2 (inst) >= REG_PC)
3074 inst_env->reg[REG_PC] =
3075 read_memory_unsigned_integer (inst_env->prefix_value, 4);
3077 /* The assign value is the value after the increment. Normally, the
3078 assign value is the value before the increment. */
3079 if ((cris_get_operand1 (inst) == REG_PC)
3080 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3082 inst_env->reg[REG_PC] = inst_env->prefix_value;
3083 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3088 /* Is the MOVEM instruction going to change the PC? */
3089 if (cris_get_operand2 (inst) == REG_PC)
3091 /* It's invalid to change the PC in a delay slot. */
3092 if (inst_env->slot_needed)
3094 inst_env->invalid = 1;
3097 inst_env->reg[REG_PC] =
3098 read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)],
3101 /* The increment is not depending on the size, instead it's depending
3102 on the number of registers loaded from memory. */
3103 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3105 /* It's invalid to change the PC in a delay slot. */
3106 if (inst_env->slot_needed)
3108 inst_env->invalid = 1;
3111 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3114 inst_env->slot_needed = 0;
3115 inst_env->prefix_found = 0;
3116 inst_env->xflag_found = 0;
3117 inst_env->disable_interrupt = 0;
3120 /* Handles the MOVEM to memory from general register instruction. */
3123 move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env)
3125 if (inst_env->prefix_found)
3127 /* The assign value is the value after the increment. Normally, the
3128 assign value is the value before the increment. */
3129 if ((cris_get_operand1 (inst) == REG_PC) &&
3130 (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3132 /* The prefix handles the problem if we are in a delay slot. */
3133 inst_env->reg[REG_PC] = inst_env->prefix_value;
3134 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3139 /* The increment is not depending on the size, instead it's depending
3140 on the number of registers loaded to memory. */
3141 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3143 /* It's invalid to change the PC in a delay slot. */
3144 if (inst_env->slot_needed)
3146 inst_env->invalid = 1;
3149 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3152 inst_env->slot_needed = 0;
3153 inst_env->prefix_found = 0;
3154 inst_env->xflag_found = 0;
3155 inst_env->disable_interrupt = 0;
3158 /* Handles the intructions that's not yet implemented, by setting
3159 inst_env->invalid to true. */
3162 not_implemented_op (unsigned short inst, inst_env_type *inst_env)
3164 inst_env->invalid = 1;
3167 /* Handles the XOR instruction. */
3170 xor_op (unsigned short inst, inst_env_type *inst_env)
3172 /* XOR can't have a prefix. */
3173 if (inst_env->prefix_found)
3175 inst_env->invalid = 1;
3179 /* Check if the PC is the target. */
3180 if (cris_get_operand2 (inst) == REG_PC)
3182 /* It's invalid to change the PC in a delay slot. */
3183 if (inst_env->slot_needed)
3185 inst_env->invalid = 1;
3188 inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)];
3190 inst_env->slot_needed = 0;
3191 inst_env->prefix_found = 0;
3192 inst_env->xflag_found = 0;
3193 inst_env->disable_interrupt = 0;
3196 /* Handles the MULS instruction. */
3199 muls_op (unsigned short inst, inst_env_type *inst_env)
3201 /* MULS/U can't have a prefix. */
3202 if (inst_env->prefix_found)
3204 inst_env->invalid = 1;
3208 /* Consider it invalid if the PC is the target. */
3209 if (cris_get_operand2 (inst) == REG_PC)
3211 inst_env->invalid = 1;
3214 inst_env->slot_needed = 0;
3215 inst_env->prefix_found = 0;
3216 inst_env->xflag_found = 0;
3217 inst_env->disable_interrupt = 0;
3220 /* Handles the MULU instruction. */
3223 mulu_op (unsigned short inst, inst_env_type *inst_env)
3225 /* MULS/U can't have a prefix. */
3226 if (inst_env->prefix_found)
3228 inst_env->invalid = 1;
3232 /* Consider it invalid if the PC is the target. */
3233 if (cris_get_operand2 (inst) == REG_PC)
3235 inst_env->invalid = 1;
3238 inst_env->slot_needed = 0;
3239 inst_env->prefix_found = 0;
3240 inst_env->xflag_found = 0;
3241 inst_env->disable_interrupt = 0;
3244 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
3245 The MOVE instruction is the move from source to register. */
3248 add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env,
3249 unsigned long source1, unsigned long source2)
3251 unsigned long pc_mask;
3252 unsigned long operation_mask;
3254 /* Find out how many bits the operation should apply to. */
3255 if (cris_get_size (inst) == INST_BYTE_SIZE)
3257 pc_mask = 0xFFFFFF00;
3258 operation_mask = 0xFF;
3260 else if (cris_get_size (inst) == INST_WORD_SIZE)
3262 pc_mask = 0xFFFF0000;
3263 operation_mask = 0xFFFF;
3265 else if (cris_get_size (inst) == INST_DWORD_SIZE)
3268 operation_mask = 0xFFFFFFFF;
3272 /* The size is out of range. */
3273 inst_env->invalid = 1;
3277 /* The instruction just works on uw_operation_mask bits. */
3278 source2 &= operation_mask;
3279 source1 &= operation_mask;
3281 /* Now calculate the result. The opcode's 3 first bits separates
3282 the different actions. */
3283 switch (cris_get_opcode (inst) & 7)
3293 case 2: /* subtract */
3297 case 3: /* compare */
3309 inst_env->invalid = 1;
3315 /* Make sure that the result doesn't contain more than the instruction
3317 source2 &= operation_mask;
3319 /* Calculate the new breakpoint address. */
3320 inst_env->reg[REG_PC] &= pc_mask;
3321 inst_env->reg[REG_PC] |= source1;
3325 /* Extends the value from either byte or word size to a dword. If the mode
3326 is zero extend then the value is extended with zero. If instead the mode
3327 is signed extend the sign bit of the value is taken into consideration. */
3329 static unsigned long
3330 do_sign_or_zero_extend (unsigned long value, unsigned short *inst)
3332 /* The size can be either byte or word, check which one it is.
3333 Don't check the highest bit, it's indicating if it's a zero
3335 if (cris_get_size (*inst) & INST_WORD_SIZE)
3340 /* Check if the instruction is signed extend. If so, check if value has
3342 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK))
3344 value |= SIGNED_WORD_EXTEND_MASK;
3352 /* Check if the instruction is signed extend. If so, check if value has
3354 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK))
3356 value |= SIGNED_BYTE_EXTEND_MASK;
3359 /* The size should now be dword. */
3360 cris_set_size_to_dword (inst);
3364 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3365 instruction. The MOVE instruction is the move from source to register. */
3368 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3369 inst_env_type *inst_env)
3371 unsigned long operand1;
3372 unsigned long operand2;
3374 /* It's invalid to have a prefix to the instruction. This is a register
3375 mode instruction and can't have a prefix. */
3376 if (inst_env->prefix_found)
3378 inst_env->invalid = 1;
3381 /* Check if the instruction has PC as its target. */
3382 if (cris_get_operand2 (inst) == REG_PC)
3384 if (inst_env->slot_needed)
3386 inst_env->invalid = 1;
3389 /* The instruction has the PC as its target register. */
3390 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3391 operand2 = inst_env->reg[REG_PC];
3393 /* Check if it's a extend, signed or zero instruction. */
3394 if (cris_get_opcode (inst) < 4)
3396 operand1 = do_sign_or_zero_extend (operand1, &inst);
3398 /* Calculate the PC value after the instruction, i.e. where the
3399 breakpoint should be. The order of the udw_operands is vital. */
3400 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3402 inst_env->slot_needed = 0;
3403 inst_env->prefix_found = 0;
3404 inst_env->xflag_found = 0;
3405 inst_env->disable_interrupt = 0;
3408 /* Returns the data contained at address. The size of the data is derived from
3409 the size of the operation. If the instruction is a zero or signed
3410 extend instruction, the size field is changed in instruction. */
3412 static unsigned long
3413 get_data_from_address (unsigned short *inst, CORE_ADDR address)
3415 int size = cris_get_size (*inst);
3416 unsigned long value;
3418 /* If it's an extend instruction we don't want the signed extend bit,
3419 because it influences the size. */
3420 if (cris_get_opcode (*inst) < 4)
3422 size &= ~SIGNED_EXTEND_BIT_MASK;
3424 /* Is there a need for checking the size? Size should contain the number of
3427 value = read_memory_unsigned_integer (address, size);
3429 /* Check if it's an extend, signed or zero instruction. */
3430 if (cris_get_opcode (*inst) < 4)
3432 value = do_sign_or_zero_extend (value, inst);
3437 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3438 instructions. The MOVE instruction is the move from source to register. */
3441 handle_prefix_assign_mode_for_aritm_op (unsigned short inst,
3442 inst_env_type *inst_env)
3444 unsigned long operand2;
3445 unsigned long operand3;
3447 check_assign (inst, inst_env);
3448 if (cris_get_operand2 (inst) == REG_PC)
3450 operand2 = inst_env->reg[REG_PC];
3452 /* Get the value of the third operand. */
3453 operand3 = get_data_from_address (&inst, inst_env->prefix_value);
3455 /* Calculate the PC value after the instruction, i.e. where the
3456 breakpoint should be. The order of the udw_operands is vital. */
3457 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3459 inst_env->slot_needed = 0;
3460 inst_env->prefix_found = 0;
3461 inst_env->xflag_found = 0;
3462 inst_env->disable_interrupt = 0;
3465 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3466 OR instructions. Note that for this to work as expected, the calling
3467 function must have made sure that there is a prefix to this instruction. */
3470 three_operand_add_sub_cmp_and_or_op (unsigned short inst,
3471 inst_env_type *inst_env)
3473 unsigned long operand2;
3474 unsigned long operand3;
3476 if (cris_get_operand1 (inst) == REG_PC)
3478 /* The PC will be changed by the instruction. */
3479 operand2 = inst_env->reg[cris_get_operand2 (inst)];
3481 /* Get the value of the third operand. */
3482 operand3 = get_data_from_address (&inst, inst_env->prefix_value);
3484 /* Calculate the PC value after the instruction, i.e. where the
3485 breakpoint should be. */
3486 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3488 inst_env->slot_needed = 0;
3489 inst_env->prefix_found = 0;
3490 inst_env->xflag_found = 0;
3491 inst_env->disable_interrupt = 0;
3494 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3495 instructions. The MOVE instruction is the move from source to register. */
3498 handle_prefix_index_mode_for_aritm_op (unsigned short inst,
3499 inst_env_type *inst_env)
3501 if (cris_get_operand1 (inst) != cris_get_operand2 (inst))
3503 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
3504 SUB, AND or OR something weird is going on (if everything works these
3505 instructions should end up in the three operand version). */
3506 inst_env->invalid = 1;
3511 /* three_operand_add_sub_cmp_and_or does the same as we should do here
3513 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3515 inst_env->slot_needed = 0;
3516 inst_env->prefix_found = 0;
3517 inst_env->xflag_found = 0;
3518 inst_env->disable_interrupt = 0;
3521 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3522 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
3523 source to register. */
3526 handle_inc_and_index_mode_for_aritm_op (unsigned short inst,
3527 inst_env_type *inst_env)
3529 unsigned long operand1;
3530 unsigned long operand2;
3531 unsigned long operand3;
3534 /* The instruction is either an indirect or autoincrement addressing mode.
3535 Check if the destination register is the PC. */
3536 if (cris_get_operand2 (inst) == REG_PC)
3538 /* Must be done here, get_data_from_address may change the size
3540 size = cris_get_size (inst);
3541 operand2 = inst_env->reg[REG_PC];
3543 /* Get the value of the third operand, i.e. the indirect operand. */
3544 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3545 operand3 = get_data_from_address (&inst, operand1);
3547 /* Calculate the PC value after the instruction, i.e. where the
3548 breakpoint should be. The order of the udw_operands is vital. */
3549 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3551 /* If this is an autoincrement addressing mode, check if the increment
3553 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3555 /* Get the size field. */
3556 size = cris_get_size (inst);
3558 /* If it's an extend instruction we don't want the signed extend bit,
3559 because it influences the size. */
3560 if (cris_get_opcode (inst) < 4)
3562 size &= ~SIGNED_EXTEND_BIT_MASK;
3564 process_autoincrement (size, inst, inst_env);
3566 inst_env->slot_needed = 0;
3567 inst_env->prefix_found = 0;
3568 inst_env->xflag_found = 0;
3569 inst_env->disable_interrupt = 0;
3572 /* Handles the two-operand addressing mode, all modes except register, for
3573 the ADD, SUB CMP, AND and OR instruction. */
3576 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3577 inst_env_type *inst_env)
3579 if (inst_env->prefix_found)
3581 if (cris_get_mode (inst) == PREFIX_INDEX_MODE)
3583 handle_prefix_index_mode_for_aritm_op (inst, inst_env);
3585 else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
3587 handle_prefix_assign_mode_for_aritm_op (inst, inst_env);
3591 /* The mode is invalid for a prefixed base instruction. */
3592 inst_env->invalid = 1;
3598 handle_inc_and_index_mode_for_aritm_op (inst, inst_env);
3602 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3605 quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env)
3607 unsigned long operand1;
3608 unsigned long operand2;
3610 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3611 instruction and can't have a prefix. */
3612 if (inst_env->prefix_found)
3614 inst_env->invalid = 1;
3618 /* Check if the instruction has PC as its target. */
3619 if (cris_get_operand2 (inst) == REG_PC)
3621 if (inst_env->slot_needed)
3623 inst_env->invalid = 1;
3626 operand1 = cris_get_quick_value (inst);
3627 operand2 = inst_env->reg[REG_PC];
3629 /* The size should now be dword. */
3630 cris_set_size_to_dword (&inst);
3632 /* Calculate the PC value after the instruction, i.e. where the
3633 breakpoint should be. */
3634 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3636 inst_env->slot_needed = 0;
3637 inst_env->prefix_found = 0;
3638 inst_env->xflag_found = 0;
3639 inst_env->disable_interrupt = 0;
3642 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3645 quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env)
3647 unsigned long operand1;
3648 unsigned long operand2;
3650 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3651 instruction and can't have a prefix. */
3652 if (inst_env->prefix_found)
3654 inst_env->invalid = 1;
3657 /* Check if the instruction has PC as its target. */
3658 if (cris_get_operand2 (inst) == REG_PC)
3660 if (inst_env->slot_needed)
3662 inst_env->invalid = 1;
3665 /* The instruction has the PC as its target register. */
3666 operand1 = cris_get_quick_value (inst);
3667 operand2 = inst_env->reg[REG_PC];
3669 /* The quick value is signed, so check if we must do a signed extend. */
3670 if (operand1 & SIGNED_QUICK_VALUE_MASK)
3673 operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK;
3675 /* The size should now be dword. */
3676 cris_set_size_to_dword (&inst);
3678 /* Calculate the PC value after the instruction, i.e. where the
3679 breakpoint should be. */
3680 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3682 inst_env->slot_needed = 0;
3683 inst_env->prefix_found = 0;
3684 inst_env->xflag_found = 0;
3685 inst_env->disable_interrupt = 0;
3688 /* Translate op_type to a function and call it. */
3691 cris_gdb_func (struct gdbarch *gdbarch, enum cris_op_type op_type,
3692 unsigned short inst, inst_env_type *inst_env)
3696 case cris_not_implemented_op:
3697 not_implemented_op (inst, inst_env);
3701 abs_op (inst, inst_env);
3705 addi_op (inst, inst_env);
3709 asr_op (inst, inst_env);
3713 asrq_op (inst, inst_env);
3716 case cris_ax_ei_setf_op:
3717 ax_ei_setf_op (inst, inst_env);
3720 case cris_bdap_prefix:
3721 bdap_prefix (inst, inst_env);
3724 case cris_biap_prefix:
3725 biap_prefix (inst, inst_env);
3729 break_op (inst, inst_env);
3732 case cris_btst_nop_op:
3733 btst_nop_op (inst, inst_env);
3736 case cris_clearf_di_op:
3737 clearf_di_op (inst, inst_env);
3740 case cris_dip_prefix:
3741 dip_prefix (inst, inst_env);
3744 case cris_dstep_logshift_mstep_neg_not_op:
3745 dstep_logshift_mstep_neg_not_op (inst, inst_env);
3748 case cris_eight_bit_offset_branch_op:
3749 eight_bit_offset_branch_op (inst, inst_env);
3752 case cris_move_mem_to_reg_movem_op:
3753 move_mem_to_reg_movem_op (inst, inst_env);
3756 case cris_move_reg_to_mem_movem_op:
3757 move_reg_to_mem_movem_op (inst, inst_env);
3760 case cris_move_to_preg_op:
3761 move_to_preg_op (gdbarch, inst, inst_env);
3765 muls_op (inst, inst_env);
3769 mulu_op (inst, inst_env);
3772 case cris_none_reg_mode_add_sub_cmp_and_or_move_op:
3773 none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3776 case cris_none_reg_mode_clear_test_op:
3777 none_reg_mode_clear_test_op (inst, inst_env);
3780 case cris_none_reg_mode_jump_op:
3781 none_reg_mode_jump_op (inst, inst_env);
3784 case cris_none_reg_mode_move_from_preg_op:
3785 none_reg_mode_move_from_preg_op (gdbarch, inst, inst_env);
3788 case cris_quick_mode_add_sub_op:
3789 quick_mode_add_sub_op (inst, inst_env);
3792 case cris_quick_mode_and_cmp_move_or_op:
3793 quick_mode_and_cmp_move_or_op (inst, inst_env);
3796 case cris_quick_mode_bdap_prefix:
3797 quick_mode_bdap_prefix (inst, inst_env);
3800 case cris_reg_mode_add_sub_cmp_and_or_move_op:
3801 reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3804 case cris_reg_mode_clear_op:
3805 reg_mode_clear_op (inst, inst_env);
3808 case cris_reg_mode_jump_op:
3809 reg_mode_jump_op (inst, inst_env);
3812 case cris_reg_mode_move_from_preg_op:
3813 reg_mode_move_from_preg_op (inst, inst_env);
3816 case cris_reg_mode_test_op:
3817 reg_mode_test_op (inst, inst_env);
3821 scc_op (inst, inst_env);
3824 case cris_sixteen_bit_offset_branch_op:
3825 sixteen_bit_offset_branch_op (inst, inst_env);
3828 case cris_three_operand_add_sub_cmp_and_or_op:
3829 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3832 case cris_three_operand_bound_op:
3833 three_operand_bound_op (inst, inst_env);
3836 case cris_two_operand_bound_op:
3837 two_operand_bound_op (inst, inst_env);
3841 xor_op (inst, inst_env);
3846 /* This wrapper is to avoid cris_get_assembler being called before
3847 exec_bfd has been set. */
3850 cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info)
3852 int (*print_insn) (bfd_vma addr, struct disassemble_info *info);
3853 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3854 disassembler, even when there is no BFD. Does something like
3855 "gdb; target remote; disassmeble *0x123" work? */
3856 gdb_assert (exec_bfd != NULL);
3857 print_insn = cris_get_disassembler (exec_bfd);
3858 gdb_assert (print_insn != NULL);
3859 return print_insn (addr, info);
3862 /* Copied from <asm/elf.h>. */
3863 typedef unsigned long elf_greg_t;
3865 /* Same as user_regs_struct struct in <asm/user.h>. */
3866 #define CRISV10_ELF_NGREG 35
3867 typedef elf_greg_t elf_gregset_t[CRISV10_ELF_NGREG];
3869 #define CRISV32_ELF_NGREG 32
3870 typedef elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG];
3872 /* Unpack an elf_gregset_t into GDB's register cache. */
3875 cris_supply_gregset (struct regcache *regcache, elf_gregset_t *gregsetp)
3877 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3878 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3880 elf_greg_t *regp = *gregsetp;
3881 static char zerobuf[4] = {0};
3883 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3884 knows about the actual size of each register so that's no problem. */
3885 for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++)
3887 regcache_raw_supply (regcache, i, (char *)®p[i]);
3890 if (tdep->cris_version == 32)
3892 /* Needed to set pseudo-register PC for CRISv32. */
3893 /* FIXME: If ERP is in a delay slot at this point then the PC will
3894 be wrong. Issue a warning to alert the user. */
3895 regcache_raw_supply (regcache, gdbarch_pc_regnum (gdbarch),
3896 (char *)®p[ERP_REGNUM]);
3898 if (*(char *)®p[ERP_REGNUM] & 0x1)
3899 fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n");
3903 /* Use a local version of this function to get the correct types for
3904 regsets, until multi-arch core support is ready. */
3907 fetch_core_registers (struct regcache *regcache,
3908 char *core_reg_sect, unsigned core_reg_size,
3909 int which, CORE_ADDR reg_addr)
3911 elf_gregset_t gregset;
3916 if (core_reg_size != sizeof (elf_gregset_t)
3917 && core_reg_size != sizeof (crisv32_elf_gregset_t))
3919 warning (_("wrong size gregset struct in core file"));
3923 memcpy (&gregset, core_reg_sect, sizeof (gregset));
3924 cris_supply_gregset (regcache, &gregset);
3928 /* We've covered all the kinds of registers we know about here,
3929 so this must be something we wouldn't know what to do with
3930 anyway. Just ignore it. */
3935 static struct core_fns cris_elf_core_fns =
3937 bfd_target_elf_flavour, /* core_flavour */
3938 default_check_format, /* check_format */
3939 default_core_sniffer, /* core_sniffer */
3940 fetch_core_registers, /* core_read_registers */
3944 extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */
3947 _initialize_cris_tdep (void)
3949 static struct cmd_list_element *cris_set_cmdlist;
3950 static struct cmd_list_element *cris_show_cmdlist;
3952 struct cmd_list_element *c;
3954 gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep);
3956 /* CRIS-specific user-commands. */
3957 add_setshow_uinteger_cmd ("cris-version", class_support,
3958 &usr_cmd_cris_version,
3959 _("Set the current CRIS version."),
3960 _("Show the current CRIS version."),
3962 Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\
3965 NULL, /* FIXME: i18n: Current CRIS version is %s. */
3966 &setlist, &showlist);
3968 add_setshow_enum_cmd ("cris-mode", class_support,
3969 cris_modes, &usr_cmd_cris_mode,
3970 _("Set the current CRIS mode."),
3971 _("Show the current CRIS mode."),
3973 Set to CRIS_MODE_GURU when debugging in guru mode.\n\
3974 Makes GDB use the NRP register instead of the ERP register in certain cases."),
3976 NULL, /* FIXME: i18n: Current CRIS version is %s. */
3977 &setlist, &showlist);
3979 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support,
3980 &usr_cmd_cris_dwarf2_cfi,
3981 _("Set the usage of Dwarf-2 CFI for CRIS."),
3982 _("Show the usage of Dwarf-2 CFI for CRIS."),
3983 _("Set this to \"off\" if using gcc-cris < R59."),
3984 set_cris_dwarf2_cfi,
3985 NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI for CRIS is %d. */
3986 &setlist, &showlist);
3988 deprecated_add_core_fns (&cris_elf_core_fns);
3991 /* Prints out all target specific values. */
3994 cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3996 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3999 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n",
4000 tdep->cris_version);
4001 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n",
4003 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
4004 tdep->cris_dwarf2_cfi);
4009 set_cris_version (char *ignore_args, int from_tty,
4010 struct cmd_list_element *c)
4012 struct gdbarch_info info;
4014 usr_cmd_cris_version_valid = 1;
4016 /* Update the current architecture, if needed. */
4017 gdbarch_info_init (&info);
4018 if (!gdbarch_update_p (info))
4019 internal_error (__FILE__, __LINE__,
4020 _("cris_gdbarch_update: failed to update architecture."));
4024 set_cris_mode (char *ignore_args, int from_tty,
4025 struct cmd_list_element *c)
4027 struct gdbarch_info info;
4029 /* Update the current architecture, if needed. */
4030 gdbarch_info_init (&info);
4031 if (!gdbarch_update_p (info))
4032 internal_error (__FILE__, __LINE__,
4033 "cris_gdbarch_update: failed to update architecture.");
4037 set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
4038 struct cmd_list_element *c)
4040 struct gdbarch_info info;
4042 /* Update the current architecture, if needed. */
4043 gdbarch_info_init (&info);
4044 if (!gdbarch_update_p (info))
4045 internal_error (__FILE__, __LINE__,
4046 _("cris_gdbarch_update: failed to update architecture."));
4049 static struct gdbarch *
4050 cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
4052 struct gdbarch *gdbarch;
4053 struct gdbarch_tdep *tdep;
4056 if (usr_cmd_cris_version_valid)
4058 /* Trust the user's CRIS version setting. */
4059 cris_version = usr_cmd_cris_version;
4061 else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32)
4067 /* Assume it's CRIS version 10. */
4071 /* Make the current settings visible to the user. */
4072 usr_cmd_cris_version = cris_version;
4074 /* Find a candidate among the list of pre-declared architectures. */
4075 for (arches = gdbarch_list_lookup_by_info (arches, &info);
4077 arches = gdbarch_list_lookup_by_info (arches->next, &info))
4079 if ((gdbarch_tdep (arches->gdbarch)->cris_version
4080 == usr_cmd_cris_version)
4081 && (gdbarch_tdep (arches->gdbarch)->cris_mode
4082 == usr_cmd_cris_mode)
4083 && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi
4084 == usr_cmd_cris_dwarf2_cfi))
4085 return arches->gdbarch;
4088 /* No matching architecture was found. Create a new one. */
4089 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
4090 gdbarch = gdbarch_alloc (&info, tdep);
4092 tdep->cris_version = usr_cmd_cris_version;
4093 tdep->cris_mode = usr_cmd_cris_mode;
4094 tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi;
4096 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
4097 switch (info.byte_order)
4099 case BFD_ENDIAN_LITTLE:
4103 case BFD_ENDIAN_BIG:
4104 internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: big endian byte order in info"));
4108 internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: unknown byte order in info"));
4111 set_gdbarch_return_value (gdbarch, cris_return_value);
4113 set_gdbarch_sp_regnum (gdbarch, 14);
4115 /* Length of ordinary registers used in push_word and a few other
4116 places. register_size() is the real way to know how big a
4119 set_gdbarch_double_bit (gdbarch, 64);
4120 /* The default definition of a long double is 2 * gdbarch_double_bit,
4121 which means we have to set this explicitly. */
4122 set_gdbarch_long_double_bit (gdbarch, 64);
4124 /* The total amount of space needed to store (in an array called registers)
4125 GDB's copy of the machine's register state. Note: We can not use
4126 cris_register_size at this point, since it relies on gdbarch
4128 switch (tdep->cris_version)
4136 /* Old versions; not supported. */
4137 internal_error (__FILE__, __LINE__,
4138 _("cris_gdbarch_init: unsupported CRIS version"));
4143 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
4144 P7 (32 bits), and P15 (32 bits) have been implemented. */
4145 set_gdbarch_pc_regnum (gdbarch, 15);
4146 set_gdbarch_register_type (gdbarch, cris_register_type);
4147 /* There are 32 registers (some of which may not be implemented). */
4148 set_gdbarch_num_regs (gdbarch, 32);
4149 set_gdbarch_register_name (gdbarch, cris_register_name);
4150 set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register);
4151 set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register);
4153 set_gdbarch_software_single_step (gdbarch, cris_software_single_step);
4157 /* CRIS v32. General registers R0 - R15 (32 bits), special registers
4158 P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
4159 and pseudo-register PC (32 bits). */
4160 set_gdbarch_pc_regnum (gdbarch, 32);
4161 set_gdbarch_register_type (gdbarch, crisv32_register_type);
4162 /* 32 registers + pseudo-register PC + 16 support registers. */
4163 set_gdbarch_num_regs (gdbarch, 32 + 1 + 16);
4164 set_gdbarch_register_name (gdbarch, crisv32_register_name);
4166 set_gdbarch_cannot_store_register
4167 (gdbarch, crisv32_cannot_store_register);
4168 set_gdbarch_cannot_fetch_register
4169 (gdbarch, crisv32_cannot_fetch_register);
4171 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
4173 set_gdbarch_single_step_through_delay
4174 (gdbarch, crisv32_single_step_through_delay);
4179 internal_error (__FILE__, __LINE__,
4180 _("cris_gdbarch_init: unknown CRIS version"));
4183 /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
4184 have the same ABI). */
4185 set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code);
4186 set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call);
4187 set_gdbarch_frame_align (gdbarch, cris_frame_align);
4188 set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue);
4190 /* The stack grows downward. */
4191 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4193 set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc);
4195 set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc);
4196 set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp);
4197 set_gdbarch_dummy_id (gdbarch, cris_dummy_id);
4199 if (tdep->cris_dwarf2_cfi == 1)
4201 /* Hook in the Dwarf-2 frame sniffer. */
4202 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum);
4203 dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg);
4204 dwarf2_append_unwinders (gdbarch);
4207 if (tdep->cris_mode != cris_mode_guru)
4209 frame_unwind_append_unwinder (gdbarch, &cris_sigtramp_frame_unwind);
4212 frame_unwind_append_unwinder (gdbarch, &cris_frame_unwind);
4213 frame_base_set_default (gdbarch, &cris_frame_base);
4215 set_solib_svr4_fetch_link_map_offsets
4216 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
4218 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
4219 disassembler, even when there is no BFD. Does something like
4220 "gdb; target remote; disassmeble *0x123" work? */
4221 set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler);