1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
3 Copyright (C) 2001-2012 Free Software Foundation, Inc.
5 Contributed by Axis Communications AB.
6 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include "frame-unwind.h"
26 #include "frame-base.h"
27 #include "trad-frame.h"
28 #include "dwarf2-frame.h"
36 #include "opcode/cris.h"
37 #include "arch-utils.h"
39 #include "gdb_assert.h"
43 #include "solib.h" /* Support for shared libraries. */
44 #include "solib-svr4.h"
45 #include "gdb_string.h"
50 /* There are no floating point registers. Used in gdbserver low-linux.c. */
53 /* There are 16 general registers. */
56 /* There are 16 special registers. */
59 /* CRISv32 has a pseudo PC register, not noted here. */
61 /* CRISv32 has 16 support registers. */
65 /* Register numbers of various important registers.
66 CRIS_FP_REGNUM Contains address of executing stack frame.
67 STR_REGNUM Contains the address of structure return values.
68 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
69 ARG1_REGNUM Contains the first parameter to a function.
70 ARG2_REGNUM Contains the second parameter to a function.
71 ARG3_REGNUM Contains the third parameter to a function.
72 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
73 gdbarch_sp_regnum Contains address of top of stack.
74 gdbarch_pc_regnum Contains address of next instruction.
75 SRP_REGNUM Subroutine return pointer register.
76 BRP_REGNUM Breakpoint return pointer register. */
80 /* Enums with respect to the general registers, valid for all
81 CRIS versions. The frame pointer is always in R8. */
83 /* ABI related registers. */
91 /* Registers which happen to be common. */
96 /* CRISv10 et al. specific registers. */
108 /* CRISv32 specific registers. */
121 CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */
123 CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */
143 extern const struct cris_spec_reg cris_spec_regs[];
145 /* CRIS version, set via the user command 'set cris-version'. Affects
146 register names and sizes. */
147 static int usr_cmd_cris_version;
149 /* Indicates whether to trust the above variable. */
150 static int usr_cmd_cris_version_valid = 0;
152 static const char cris_mode_normal[] = "normal";
153 static const char cris_mode_guru[] = "guru";
154 static const char *const cris_modes[] = {
160 /* CRIS mode, set via the user command 'set cris-mode'. Affects
161 type of break instruction among other things. */
162 static const char *usr_cmd_cris_mode = cris_mode_normal;
164 /* Whether to make use of Dwarf-2 CFI (default on). */
165 static int usr_cmd_cris_dwarf2_cfi = 1;
167 /* CRIS architecture specific information. */
171 const char *cris_mode;
175 /* Sigtramp identification code copied from i386-linux-tdep.c. */
177 #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
178 #define SIGTRAMP_OFFSET0 0
179 #define SIGTRAMP_INSN1 0xe93d /* break 13 */
180 #define SIGTRAMP_OFFSET1 4
182 static const unsigned short sigtramp_code[] =
184 SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */
185 SIGTRAMP_INSN1 /* break 13 */
188 #define SIGTRAMP_LEN (sizeof sigtramp_code)
190 /* Note: same length as normal sigtramp code. */
192 static const unsigned short rt_sigtramp_code[] =
194 SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */
195 SIGTRAMP_INSN1 /* break 13 */
198 /* If PC is in a sigtramp routine, return the address of the start of
199 the routine. Otherwise, return 0. */
202 cris_sigtramp_start (struct frame_info *this_frame)
204 CORE_ADDR pc = get_frame_pc (this_frame);
205 gdb_byte buf[SIGTRAMP_LEN];
207 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
210 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
212 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
215 pc -= SIGTRAMP_OFFSET1;
216 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
220 if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0)
226 /* If PC is in a RT sigtramp routine, return the address of the start of
227 the routine. Otherwise, return 0. */
230 cris_rt_sigtramp_start (struct frame_info *this_frame)
232 CORE_ADDR pc = get_frame_pc (this_frame);
233 gdb_byte buf[SIGTRAMP_LEN];
235 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
238 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
240 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
243 pc -= SIGTRAMP_OFFSET1;
244 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
248 if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0)
254 /* Assuming THIS_FRAME is a frame for a GNU/Linux sigtramp routine,
255 return the address of the associated sigcontext structure. */
258 cris_sigcontext_addr (struct frame_info *this_frame)
260 struct gdbarch *gdbarch = get_frame_arch (this_frame);
261 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
266 get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
267 sp = extract_unsigned_integer (buf, 4, byte_order);
269 /* Look for normal sigtramp frame first. */
270 pc = cris_sigtramp_start (this_frame);
273 /* struct signal_frame (arch/cris/kernel/signal.c) contains
274 struct sigcontext as its first member, meaning the SP points to
279 pc = cris_rt_sigtramp_start (this_frame);
282 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
283 a struct ucontext, which in turn contains a struct sigcontext.
285 4 + 4 + 128 to struct ucontext, then
286 4 + 4 + 12 to struct sigcontext. */
290 error (_("Couldn't recognize signal trampoline."));
294 struct cris_unwind_cache
296 /* The previous frame's inner most stack address. Used as this
297 frame ID's stack_addr. */
299 /* The frame's base, optionally used by the high-level debug info. */
302 /* How far the SP and r8 (FP) have been offset from the start of
303 the stack frame (as defined by the previous frame's stack
309 /* From old frame_extra_info struct. */
313 /* Table indicating the location of each and every register. */
314 struct trad_frame_saved_reg *saved_regs;
317 static struct cris_unwind_cache *
318 cris_sigtramp_frame_unwind_cache (struct frame_info *this_frame,
321 struct gdbarch *gdbarch = get_frame_arch (this_frame);
322 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
323 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
324 struct cris_unwind_cache *info;
330 return (*this_cache);
332 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
333 (*this_cache) = info;
334 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
336 /* Zero all fields. */
342 info->uses_frame = 0;
344 info->leaf_function = 0;
346 get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
347 info->base = extract_unsigned_integer (buf, 4, byte_order);
349 addr = cris_sigcontext_addr (this_frame);
351 /* Layout of the sigcontext struct:
354 unsigned long oldmask;
358 if (tdep->cris_version == 10)
360 /* R0 to R13 are stored in reverse order at offset (2 * 4) in
362 for (i = 0; i <= 13; i++)
363 info->saved_regs[i].addr = addr + ((15 - i) * 4);
365 info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4);
366 info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4);
367 info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4);
368 /* Note: IRP is off by 2 at this point. There's no point in correcting
369 it though since that will mean that the backtrace will show a PC
370 different from what is shown when stopped. */
371 info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4);
372 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
373 = info->saved_regs[IRP_REGNUM];
374 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr = addr + (24 * 4);
379 /* R0 to R13 are stored in order at offset (1 * 4) in
381 for (i = 0; i <= 13; i++)
382 info->saved_regs[i].addr = addr + ((i + 1) * 4);
384 info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4);
385 info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4);
386 info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4);
387 info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4);
388 info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4);
389 info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4);
390 info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4);
391 info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4);
392 info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4);
394 /* FIXME: If ERP is in a delay slot at this point then the PC will
395 be wrong at this point. This problem manifests itself in the
396 sigaltstack.exp test case, which occasionally generates FAILs when
397 the signal is received while in a delay slot.
399 This could be solved by a couple of read_memory_unsigned_integer and a
400 trad_frame_set_value. */
401 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
402 = info->saved_regs[ERP_REGNUM];
404 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr
412 cris_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
413 struct frame_id *this_id)
415 struct cris_unwind_cache *cache =
416 cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
417 (*this_id) = frame_id_build (cache->base, get_frame_pc (this_frame));
420 /* Forward declaration. */
422 static struct value *cris_frame_prev_register (struct frame_info *this_frame,
423 void **this_cache, int regnum);
424 static struct value *
425 cris_sigtramp_frame_prev_register (struct frame_info *this_frame,
426 void **this_cache, int regnum)
428 /* Make sure we've initialized the cache. */
429 cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
430 return cris_frame_prev_register (this_frame, this_cache, regnum);
434 cris_sigtramp_frame_sniffer (const struct frame_unwind *self,
435 struct frame_info *this_frame,
438 if (cris_sigtramp_start (this_frame)
439 || cris_rt_sigtramp_start (this_frame))
445 static const struct frame_unwind cris_sigtramp_frame_unwind =
448 default_frame_unwind_stop_reason,
449 cris_sigtramp_frame_this_id,
450 cris_sigtramp_frame_prev_register,
452 cris_sigtramp_frame_sniffer
456 crisv32_single_step_through_delay (struct gdbarch *gdbarch,
457 struct frame_info *this_frame)
459 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
463 if (tdep->cris_mode == cris_mode_guru)
464 erp = get_frame_register_unsigned (this_frame, NRP_REGNUM);
466 erp = get_frame_register_unsigned (this_frame, ERP_REGNUM);
470 /* In delay slot - check if there's a breakpoint at the preceding
472 if (breakpoint_here_p (get_frame_address_space (this_frame), erp & ~0x1))
478 /* The instruction environment needed to find single-step breakpoints. */
481 struct instruction_environment
483 unsigned long reg[NUM_GENREGS];
484 unsigned long preg[NUM_SPECREGS];
485 unsigned long branch_break_address;
486 unsigned long delay_slot_pc;
487 unsigned long prefix_value;
492 int delay_slot_pc_active;
494 int disable_interrupt;
498 /* Machine-dependencies in CRIS for opcodes. */
500 /* Instruction sizes. */
501 enum cris_instruction_sizes
508 /* Addressing modes. */
509 enum cris_addressing_modes
516 /* Prefix addressing modes. */
517 enum cris_prefix_addressing_modes
519 PREFIX_INDEX_MODE = 2,
520 PREFIX_ASSIGN_MODE = 3,
522 /* Handle immediate byte offset addressing mode prefix format. */
523 PREFIX_OFFSET_MODE = 2
526 /* Masks for opcodes. */
527 enum cris_opcode_masks
529 BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1,
530 SIGNED_EXTEND_BIT_MASK = 0x2,
531 SIGNED_BYTE_MASK = 0x80,
532 SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00,
533 SIGNED_WORD_MASK = 0x8000,
534 SIGNED_WORD_EXTEND_MASK = 0xFFFF0000,
535 SIGNED_DWORD_MASK = 0x80000000,
536 SIGNED_QUICK_VALUE_MASK = 0x20,
537 SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0
540 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
548 cris_get_operand2 (unsigned short insn)
550 return ((insn & 0xF000) >> 12);
554 cris_get_mode (unsigned short insn)
556 return ((insn & 0x0C00) >> 10);
560 cris_get_opcode (unsigned short insn)
562 return ((insn & 0x03C0) >> 6);
566 cris_get_size (unsigned short insn)
568 return ((insn & 0x0030) >> 4);
572 cris_get_operand1 (unsigned short insn)
574 return (insn & 0x000F);
577 /* Additional functions in order to handle opcodes. */
580 cris_get_quick_value (unsigned short insn)
582 return (insn & 0x003F);
586 cris_get_bdap_quick_offset (unsigned short insn)
588 return (insn & 0x00FF);
592 cris_get_branch_short_offset (unsigned short insn)
594 return (insn & 0x00FF);
598 cris_get_asr_shift_steps (unsigned long value)
600 return (value & 0x3F);
604 cris_get_clear_size (unsigned short insn)
606 return ((insn) & 0xC000);
610 cris_is_signed_extend_bit_on (unsigned short insn)
612 return (((insn) & 0x20) == 0x20);
616 cris_is_xflag_bit_on (unsigned short insn)
618 return (((insn) & 0x1000) == 0x1000);
622 cris_set_size_to_dword (unsigned short *insn)
629 cris_get_signed_offset (unsigned short insn)
631 return ((signed char) (insn & 0x00FF));
634 /* Calls an op function given the op-type, working on the insn and the
636 static void cris_gdb_func (struct gdbarch *, enum cris_op_type, unsigned short,
639 static struct gdbarch *cris_gdbarch_init (struct gdbarch_info,
640 struct gdbarch_list *);
642 static void cris_dump_tdep (struct gdbarch *, struct ui_file *);
644 static void set_cris_version (char *ignore_args, int from_tty,
645 struct cmd_list_element *c);
647 static void set_cris_mode (char *ignore_args, int from_tty,
648 struct cmd_list_element *c);
650 static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
651 struct cmd_list_element *c);
653 static CORE_ADDR cris_scan_prologue (CORE_ADDR pc,
654 struct frame_info *this_frame,
655 struct cris_unwind_cache *info);
657 static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc,
658 struct frame_info *this_frame,
659 struct cris_unwind_cache *info);
661 static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch,
662 struct frame_info *next_frame);
664 static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch,
665 struct frame_info *next_frame);
667 /* When arguments must be pushed onto the stack, they go on in reverse
668 order. The below implements a FILO (stack) to do this.
669 Copied from d10v-tdep.c. */
674 struct stack_item *prev;
678 static struct stack_item *
679 push_stack_item (struct stack_item *prev, void *contents, int len)
681 struct stack_item *si;
682 si = xmalloc (sizeof (struct stack_item));
683 si->data = xmalloc (len);
686 memcpy (si->data, contents, len);
690 static struct stack_item *
691 pop_stack_item (struct stack_item *si)
693 struct stack_item *dead = si;
700 /* Put here the code to store, into fi->saved_regs, the addresses of
701 the saved registers of frame described by FRAME_INFO. This
702 includes special registers such as pc and fp saved in special ways
703 in the stack frame. sp is even more special: the address we return
704 for it IS the sp for the next frame. */
706 static struct cris_unwind_cache *
707 cris_frame_unwind_cache (struct frame_info *this_frame,
708 void **this_prologue_cache)
710 struct gdbarch *gdbarch = get_frame_arch (this_frame);
711 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
712 struct cris_unwind_cache *info;
714 if ((*this_prologue_cache))
715 return (*this_prologue_cache);
717 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
718 (*this_prologue_cache) = info;
719 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
721 /* Zero all fields. */
727 info->uses_frame = 0;
729 info->leaf_function = 0;
731 /* Prologue analysis does the rest... */
732 if (tdep->cris_version == 32)
733 crisv32_scan_prologue (get_frame_func (this_frame), this_frame, info);
735 cris_scan_prologue (get_frame_func (this_frame), this_frame, info);
740 /* Given a GDB frame, determine the address of the calling function's
741 frame. This will be used to create a new GDB frame struct. */
744 cris_frame_this_id (struct frame_info *this_frame,
745 void **this_prologue_cache,
746 struct frame_id *this_id)
748 struct cris_unwind_cache *info
749 = cris_frame_unwind_cache (this_frame, this_prologue_cache);
754 /* The FUNC is easy. */
755 func = get_frame_func (this_frame);
757 /* Hopefully the prologue analysis either correctly determined the
758 frame's base (which is the SP from the previous frame), or set
759 that base to "NULL". */
760 base = info->prev_sp;
764 id = frame_id_build (base, func);
769 static struct value *
770 cris_frame_prev_register (struct frame_info *this_frame,
771 void **this_prologue_cache, int regnum)
773 struct cris_unwind_cache *info
774 = cris_frame_unwind_cache (this_frame, this_prologue_cache);
775 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
778 /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
779 frame. The frame ID's base needs to match the TOS value saved by
780 save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */
782 static struct frame_id
783 cris_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
786 sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
787 return frame_id_build (sp, get_frame_pc (this_frame));
791 cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
793 /* Align to the size of an instruction (so that they can safely be
794 pushed onto the stack). */
799 cris_push_dummy_code (struct gdbarch *gdbarch,
800 CORE_ADDR sp, CORE_ADDR funaddr,
801 struct value **args, int nargs,
802 struct type *value_type,
803 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
804 struct regcache *regcache)
806 /* Allocate space sufficient for a breakpoint. */
808 /* Store the address of that breakpoint */
810 /* CRIS always starts the call at the callee's entry point. */
816 cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
817 struct regcache *regcache, CORE_ADDR bp_addr,
818 int nargs, struct value **args, CORE_ADDR sp,
819 int struct_return, CORE_ADDR struct_addr)
821 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
826 /* The function's arguments and memory allocated by gdb for the arguments to
827 point at reside in separate areas on the stack.
828 Both frame pointers grow toward higher addresses. */
832 struct stack_item *si = NULL;
834 /* Push the return address. */
835 regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr);
837 /* Are we returning a value using a structure return or a normal value
838 return? struct_addr is the address of the reserved space for the return
839 structure to be written on the stack. */
842 regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr);
845 /* Now load as many as possible of the first arguments into registers,
846 and push the rest onto the stack. */
847 argreg = ARG1_REGNUM;
850 for (argnum = 0; argnum < nargs; argnum++)
857 len = TYPE_LENGTH (value_type (args[argnum]));
858 val = (char *) value_contents (args[argnum]);
860 /* How may registers worth of storage do we need for this argument? */
861 reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0);
863 if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM))
865 /* Data passed by value. Fits in available register(s). */
866 for (i = 0; i < reg_demand; i++)
868 regcache_cooked_write (regcache, argreg, val);
873 else if (len <= (2 * 4) && argreg <= ARG4_REGNUM)
875 /* Data passed by value. Does not fit in available register(s).
876 Use the register(s) first, then the stack. */
877 for (i = 0; i < reg_demand; i++)
879 if (argreg <= ARG4_REGNUM)
881 regcache_cooked_write (regcache, argreg, val);
887 /* Push item for later so that pushed arguments
888 come in the right order. */
889 si = push_stack_item (si, val, 4);
894 else if (len > (2 * 4))
896 /* Data passed by reference. Push copy of data onto stack
897 and pass pointer to this copy as argument. */
898 sp = (sp - len) & ~3;
899 write_memory (sp, val, len);
901 if (argreg <= ARG4_REGNUM)
903 regcache_cooked_write_unsigned (regcache, argreg, sp);
909 store_unsigned_integer (buf, 4, byte_order, sp);
910 si = push_stack_item (si, buf, 4);
915 /* Data passed by value. No available registers. Put it on
917 si = push_stack_item (si, val, len);
923 /* fp_arg must be word-aligned (i.e., don't += len) to match
924 the function prologue. */
925 sp = (sp - si->len) & ~3;
926 write_memory (sp, si->data, si->len);
927 si = pop_stack_item (si);
930 /* Finally, update the SP register. */
931 regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp);
936 static const struct frame_unwind cris_frame_unwind =
939 default_frame_unwind_stop_reason,
941 cris_frame_prev_register,
943 default_frame_sniffer
947 cris_frame_base_address (struct frame_info *this_frame, void **this_cache)
949 struct cris_unwind_cache *info
950 = cris_frame_unwind_cache (this_frame, this_cache);
954 static const struct frame_base cris_frame_base =
957 cris_frame_base_address,
958 cris_frame_base_address,
959 cris_frame_base_address
962 /* Frames information. The definition of the struct frame_info is
966 enum frame_type type;
970 If the compilation option -fno-omit-frame-pointer is present the
971 variable frame will be set to the content of R8 which is the frame
974 The variable pc contains the address where execution is performed
975 in the present frame. The innermost frame contains the current content
976 of the register PC. All other frames contain the content of the
977 register PC in the next frame.
979 The variable `type' indicates the frame's type: normal, SIGTRAMP
980 (associated with a signal handler), dummy (associated with a dummy
983 The variable return_pc contains the address where execution should be
984 resumed when the present frame has finished, the return address.
986 The variable leaf_function is 1 if the return address is in the register
987 SRP, and 0 if it is on the stack.
989 Prologue instructions C-code.
990 The prologue may consist of (-fno-omit-frame-pointer)
994 move.d sp,r8 move.d sp,r8
996 movem rY,[sp] movem rY,[sp]
997 move.S rZ,[r8-U] move.S rZ,[r8-U]
999 where 1 is a non-terminal function, and 2 is a leaf-function.
1001 Note that this assumption is extremely brittle, and will break at the
1002 slightest change in GCC's prologue.
1004 If local variables are declared or register contents are saved on stack
1005 the subq-instruction will be present with X as the number of bytes
1006 needed for storage. The reshuffle with respect to r8 may be performed
1007 with any size S (b, w, d) and any of the general registers Z={0..13}.
1008 The offset U should be representable by a signed 8-bit value in all cases.
1009 Thus, the prefix word is assumed to be immediate byte offset mode followed
1010 by another word containing the instruction.
1019 Prologue instructions C++-code.
1020 Case 1) and 2) in the C-code may be followed by
1022 move.d r10,rS ; this
1026 move.S [r8+U],rZ ; P4
1028 if any of the call parameters are stored. The host expects these
1029 instructions to be executed in order to get the call parameters right. */
1031 /* Examine the prologue of a function. The variable ip is the address of
1032 the first instruction of the prologue. The variable limit is the address
1033 of the first instruction after the prologue. The variable fi contains the
1034 information in struct frame_info. The variable frameless_p controls whether
1035 the entire prologue is examined (0) or just enough instructions to
1036 determine that it is a prologue (1). */
1039 cris_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
1040 struct cris_unwind_cache *info)
1042 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1043 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1045 /* Present instruction. */
1046 unsigned short insn;
1048 /* Next instruction, lookahead. */
1049 unsigned short insn_next;
1052 /* Is there a push fp? */
1055 /* Number of byte on stack used for local variables and movem. */
1058 /* Highest register number in a movem. */
1061 /* move.d r<source_register>,rS */
1062 short source_register;
1067 /* This frame is with respect to a leaf until a push srp is found. */
1070 info->leaf_function = 1;
1073 /* Assume nothing on stack. */
1077 /* If we were called without a this_frame, that means we were called
1078 from cris_skip_prologue which already tried to find the end of the
1079 prologue through the symbol information. 64 instructions past current
1080 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
1081 limit = this_frame ? get_frame_pc (this_frame) : pc + 64;
1083 /* Find the prologue instructions. */
1084 while (pc > 0 && pc < limit)
1086 insn = read_memory_unsigned_integer (pc, 2, byte_order);
1090 /* push <reg> 32 bit instruction. */
1091 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1093 regno = cris_get_operand2 (insn_next);
1096 info->sp_offset += 4;
1098 /* This check, meant to recognize srp, used to be regno ==
1099 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
1100 if (insn_next == 0xBE7E)
1104 info->leaf_function = 0;
1107 else if (insn_next == 0x8FEE)
1112 info->r8_offset = info->sp_offset;
1116 else if (insn == 0x866E)
1121 info->uses_frame = 1;
1125 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1126 && cris_get_mode (insn) == 0x0000
1127 && cris_get_opcode (insn) == 0x000A)
1132 info->sp_offset += cris_get_quick_value (insn);
1135 else if (cris_get_mode (insn) == 0x0002
1136 && cris_get_opcode (insn) == 0x000F
1137 && cris_get_size (insn) == 0x0003
1138 && cris_get_operand1 (insn) == gdbarch_sp_regnum (gdbarch))
1140 /* movem r<regsave>,[sp] */
1141 regsave = cris_get_operand2 (insn);
1143 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1144 && ((insn & 0x0F00) >> 8) == 0x0001
1145 && (cris_get_signed_offset (insn) < 0))
1147 /* Immediate byte offset addressing prefix word with sp as base
1148 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1149 is between 64 and 128.
1150 movem r<regsave>,[sp=sp-<val>] */
1153 info->sp_offset += -cris_get_signed_offset (insn);
1155 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1157 if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE
1158 && cris_get_opcode (insn_next) == 0x000F
1159 && cris_get_size (insn_next) == 0x0003
1160 && cris_get_operand1 (insn_next) == gdbarch_sp_regnum
1163 regsave = cris_get_operand2 (insn_next);
1167 /* The prologue ended before the limit was reached. */
1172 else if (cris_get_mode (insn) == 0x0001
1173 && cris_get_opcode (insn) == 0x0009
1174 && cris_get_size (insn) == 0x0002)
1176 /* move.d r<10..13>,r<0..15> */
1177 source_register = cris_get_operand1 (insn);
1179 /* FIXME? In the glibc solibs, the prologue might contain something
1180 like (this example taken from relocate_doit):
1182 sub.d 0xfffef426,$r0
1183 which isn't covered by the source_register check below. Question
1184 is whether to add a check for this combo, or make better use of
1185 the limit variable instead. */
1186 if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM)
1188 /* The prologue ended before the limit was reached. */
1193 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1194 /* The size is a fixed-size. */
1195 && ((insn & 0x0F00) >> 8) == 0x0001
1196 /* A negative offset. */
1197 && (cris_get_signed_offset (insn) < 0))
1199 /* move.S rZ,[r8-U] (?) */
1200 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1202 regno = cris_get_operand2 (insn_next);
1203 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1204 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1205 && cris_get_opcode (insn_next) == 0x000F)
1207 /* move.S rZ,[r8-U] */
1212 /* The prologue ended before the limit was reached. */
1217 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1218 /* The size is a fixed-size. */
1219 && ((insn & 0x0F00) >> 8) == 0x0001
1220 /* A positive offset. */
1221 && (cris_get_signed_offset (insn) > 0))
1223 /* move.S [r8+U],rZ (?) */
1224 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1226 regno = cris_get_operand2 (insn_next);
1227 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1228 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1229 && cris_get_opcode (insn_next) == 0x0009
1230 && cris_get_operand1 (insn_next) == regno)
1232 /* move.S [r8+U],rZ */
1237 /* The prologue ended before the limit was reached. */
1244 /* The prologue ended before the limit was reached. */
1250 /* We only want to know the end of the prologue when this_frame and info
1251 are NULL (called from cris_skip_prologue i.e.). */
1252 if (this_frame == NULL && info == NULL)
1257 info->size = info->sp_offset;
1259 /* Compute the previous frame's stack pointer (which is also the
1260 frame's ID's stack address), and this frame's base pointer. */
1261 if (info->uses_frame)
1264 /* The SP was moved to the FP. This indicates that a new frame
1265 was created. Get THIS frame's FP value by unwinding it from
1267 this_base = get_frame_register_unsigned (this_frame, CRIS_FP_REGNUM);
1268 info->base = this_base;
1269 info->saved_regs[CRIS_FP_REGNUM].addr = info->base;
1271 /* The FP points at the last saved register. Adjust the FP back
1272 to before the first saved register giving the SP. */
1273 info->prev_sp = info->base + info->r8_offset;
1278 /* Assume that the FP is this frame's SP but with that pushed
1279 stack space added back. */
1280 this_base = get_frame_register_unsigned (this_frame,
1281 gdbarch_sp_regnum (gdbarch));
1282 info->base = this_base;
1283 info->prev_sp = info->base + info->size;
1286 /* Calculate the addresses for the saved registers on the stack. */
1287 /* FIXME: The address calculation should really be done on the fly while
1288 we're analyzing the prologue (we only hold one regsave value as it is
1290 val = info->sp_offset;
1292 for (regno = regsave; regno >= 0; regno--)
1294 info->saved_regs[regno].addr = info->base + info->r8_offset - val;
1298 /* The previous frame's SP needed to be computed. Save the computed
1300 trad_frame_set_value (info->saved_regs,
1301 gdbarch_sp_regnum (gdbarch), info->prev_sp);
1303 if (!info->leaf_function)
1305 /* SRP saved on the stack. But where? */
1306 if (info->r8_offset == 0)
1308 /* R8 not pushed yet. */
1309 info->saved_regs[SRP_REGNUM].addr = info->base;
1313 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1314 info->saved_regs[SRP_REGNUM].addr = info->base + 4;
1318 /* The PC is found in SRP (the actual register or located on the stack). */
1319 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1320 = info->saved_regs[SRP_REGNUM];
1326 crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
1327 struct cris_unwind_cache *info)
1329 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1332 /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not
1333 meant to be a full-fledged prologue scanner. It is only needed for
1334 the cases where we end up in code always lacking DWARF-2 CFI, notably:
1336 * PLT stubs (library calls)
1338 * signal trampolines
1340 For those cases, it is assumed that there is no actual prologue; that
1341 the stack pointer is not adjusted, and (as a consequence) the return
1342 address is not pushed onto the stack. */
1344 /* We only want to know the end of the prologue when this_frame and info
1345 are NULL (called from cris_skip_prologue i.e.). */
1346 if (this_frame == NULL && info == NULL)
1351 /* The SP is assumed to be unaltered. */
1352 this_base = get_frame_register_unsigned (this_frame,
1353 gdbarch_sp_regnum (gdbarch));
1354 info->base = this_base;
1355 info->prev_sp = this_base;
1357 /* The PC is assumed to be found in SRP. */
1358 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1359 = info->saved_regs[SRP_REGNUM];
1364 /* Advance pc beyond any function entry prologue instructions at pc
1365 to reach some "real" code. */
1367 /* Given a PC value corresponding to the start of a function, return the PC
1368 of the first instruction after the function prologue. */
1371 cris_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1373 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1374 CORE_ADDR func_addr, func_end;
1375 struct symtab_and_line sal;
1376 CORE_ADDR pc_after_prologue;
1378 /* If we have line debugging information, then the end of the prologue
1379 should the first assembly instruction of the first source line. */
1380 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1382 sal = find_pc_line (func_addr, 0);
1383 if (sal.end > 0 && sal.end < func_end)
1387 if (tdep->cris_version == 32)
1388 pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL);
1390 pc_after_prologue = cris_scan_prologue (pc, NULL, NULL);
1392 return pc_after_prologue;
1396 cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1399 pc = frame_unwind_register_unsigned (next_frame,
1400 gdbarch_pc_regnum (gdbarch));
1405 cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1408 sp = frame_unwind_register_unsigned (next_frame,
1409 gdbarch_sp_regnum (gdbarch));
1413 /* Use the program counter to determine the contents and size of a breakpoint
1414 instruction. It returns a pointer to a string of bytes that encode a
1415 breakpoint instruction, stores the length of the string to *lenptr, and
1416 adjusts pcptr (if necessary) to point to the actual memory location where
1417 the breakpoint should be inserted. */
1419 static const unsigned char *
1420 cris_breakpoint_from_pc (struct gdbarch *gdbarch,
1421 CORE_ADDR *pcptr, int *lenptr)
1423 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1424 static unsigned char break8_insn[] = {0x38, 0xe9};
1425 static unsigned char break15_insn[] = {0x3f, 0xe9};
1428 if (tdep->cris_mode == cris_mode_guru)
1429 return break15_insn;
1434 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1438 cris_spec_reg_applicable (struct gdbarch *gdbarch,
1439 struct cris_spec_reg spec_reg)
1441 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1442 int version = tdep->cris_version;
1444 switch (spec_reg.applicable_version)
1446 case cris_ver_version_all:
1448 case cris_ver_warning:
1449 /* Indeterminate/obsolete. */
1452 return (version >= 0 && version <= 3);
1454 return (version >= 3);
1456 return (version == 8 || version == 9);
1458 return (version >= 8);
1459 case cris_ver_v0_10:
1460 return (version >= 0 && version <= 10);
1461 case cris_ver_v3_10:
1462 return (version >= 3 && version <= 10);
1463 case cris_ver_v8_10:
1464 return (version >= 8 && version <= 10);
1466 return (version == 10);
1468 return (version >= 10);
1470 return (version >= 32);
1472 /* Invalid cris version. */
1477 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1478 register, -1 for an invalid register. */
1481 cris_register_size (struct gdbarch *gdbarch, int regno)
1483 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1487 if (regno >= 0 && regno < NUM_GENREGS)
1489 /* General registers (R0 - R15) are 32 bits. */
1492 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1494 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1495 Adjust regno accordingly. */
1496 spec_regno = regno - NUM_GENREGS;
1498 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1500 if (cris_spec_regs[i].number == spec_regno
1501 && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i]))
1502 /* Go with the first applicable register. */
1503 return cris_spec_regs[i].reg_size;
1505 /* Special register not applicable to this CRIS version. */
1508 else if (regno >= gdbarch_pc_regnum (gdbarch)
1509 && regno < gdbarch_num_regs (gdbarch))
1511 /* This will apply to CRISv32 only where there are additional registers
1512 after the special registers (pseudo PC and support registers). */
1520 /* Nonzero if regno should not be fetched from the target. This is the case
1521 for unimplemented (size 0) and non-existant registers. */
1524 cris_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1526 return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1527 || (cris_register_size (gdbarch, regno) == 0));
1530 /* Nonzero if regno should not be written to the target, for various
1534 cris_cannot_store_register (struct gdbarch *gdbarch, int regno)
1536 /* There are three kinds of registers we refuse to write to.
1537 1. Those that not implemented.
1538 2. Those that are read-only (depends on the processor mode).
1539 3. Those registers to which a write has no effect. */
1542 || regno >= gdbarch_num_regs (gdbarch)
1543 || cris_register_size (gdbarch, regno) == 0)
1544 /* Not implemented. */
1547 else if (regno == VR_REGNUM)
1551 else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM)
1552 /* Writing has no effect. */
1555 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
1556 agent decide whether they are writable. */
1561 /* Nonzero if regno should not be fetched from the target. This is the case
1562 for unimplemented (size 0) and non-existant registers. */
1565 crisv32_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1567 return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1568 || (cris_register_size (gdbarch, regno) == 0));
1571 /* Nonzero if regno should not be written to the target, for various
1575 crisv32_cannot_store_register (struct gdbarch *gdbarch, int regno)
1577 /* There are three kinds of registers we refuse to write to.
1578 1. Those that not implemented.
1579 2. Those that are read-only (depends on the processor mode).
1580 3. Those registers to which a write has no effect. */
1583 || regno >= gdbarch_num_regs (gdbarch)
1584 || cris_register_size (gdbarch, regno) == 0)
1585 /* Not implemented. */
1588 else if (regno == VR_REGNUM)
1592 else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM)
1593 /* Writing has no effect. */
1596 /* Many special registers are read-only in user mode. Let the debug
1597 agent decide whether they are writable. */
1602 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1603 of data in register regno. */
1605 static struct type *
1606 cris_register_type (struct gdbarch *gdbarch, int regno)
1608 if (regno == gdbarch_pc_regnum (gdbarch))
1609 return builtin_type (gdbarch)->builtin_func_ptr;
1610 else if (regno == gdbarch_sp_regnum (gdbarch)
1611 || regno == CRIS_FP_REGNUM)
1612 return builtin_type (gdbarch)->builtin_data_ptr;
1613 else if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1614 || (regno >= MOF_REGNUM && regno <= USP_REGNUM))
1615 /* Note: R8 taken care of previous clause. */
1616 return builtin_type (gdbarch)->builtin_uint32;
1617 else if (regno >= P4_REGNUM && regno <= CCR_REGNUM)
1618 return builtin_type (gdbarch)->builtin_uint16;
1619 else if (regno >= P0_REGNUM && regno <= VR_REGNUM)
1620 return builtin_type (gdbarch)->builtin_uint8;
1622 /* Invalid (unimplemented) register. */
1623 return builtin_type (gdbarch)->builtin_int0;
1626 static struct type *
1627 crisv32_register_type (struct gdbarch *gdbarch, int regno)
1629 if (regno == gdbarch_pc_regnum (gdbarch))
1630 return builtin_type (gdbarch)->builtin_func_ptr;
1631 else if (regno == gdbarch_sp_regnum (gdbarch)
1632 || regno == CRIS_FP_REGNUM)
1633 return builtin_type (gdbarch)->builtin_data_ptr;
1634 else if ((regno >= 0 && regno <= ACR_REGNUM)
1635 || (regno >= EXS_REGNUM && regno <= SPC_REGNUM)
1636 || (regno == PID_REGNUM)
1637 || (regno >= S0_REGNUM && regno <= S15_REGNUM))
1638 /* Note: R8 and SP taken care of by previous clause. */
1639 return builtin_type (gdbarch)->builtin_uint32;
1640 else if (regno == WZ_REGNUM)
1641 return builtin_type (gdbarch)->builtin_uint16;
1642 else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM)
1643 return builtin_type (gdbarch)->builtin_uint8;
1646 /* Invalid (unimplemented) register. Should not happen as there are
1647 no unimplemented CRISv32 registers. */
1648 warning (_("crisv32_register_type: unknown regno %d"), regno);
1649 return builtin_type (gdbarch)->builtin_int0;
1653 /* Stores a function return value of type type, where valbuf is the address
1654 of the value to be stored. */
1656 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1659 cris_store_return_value (struct type *type, struct regcache *regcache,
1662 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1663 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1666 if (TYPE_LENGTH (type) <= 4)
1668 /* Put the return value in R10. */
1669 val = extract_unsigned_integer (valbuf, TYPE_LENGTH (type), byte_order);
1670 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1672 else if (TYPE_LENGTH (type) <= 8)
1674 /* Put the return value in R10 and R11. */
1675 val = extract_unsigned_integer (valbuf, 4, byte_order);
1676 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1677 val = extract_unsigned_integer ((char *)valbuf + 4,
1678 TYPE_LENGTH (type) - 4, byte_order);
1679 regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val);
1682 error (_("cris_store_return_value: type length too large."));
1685 /* Return the name of register regno as a string. Return NULL for an
1686 invalid or unimplemented register. */
1689 cris_special_register_name (struct gdbarch *gdbarch, int regno)
1694 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1695 Adjust regno accordingly. */
1696 spec_regno = regno - NUM_GENREGS;
1698 /* Assume nothing about the layout of the cris_spec_regs struct
1700 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1702 if (cris_spec_regs[i].number == spec_regno
1703 && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i]))
1704 /* Go with the first applicable register. */
1705 return cris_spec_regs[i].name;
1707 /* Special register not applicable to this CRIS version. */
1712 cris_register_name (struct gdbarch *gdbarch, int regno)
1714 static char *cris_genreg_names[] =
1715 { "r0", "r1", "r2", "r3", \
1716 "r4", "r5", "r6", "r7", \
1717 "r8", "r9", "r10", "r11", \
1718 "r12", "r13", "sp", "pc" };
1720 if (regno >= 0 && regno < NUM_GENREGS)
1722 /* General register. */
1723 return cris_genreg_names[regno];
1725 else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (gdbarch))
1727 return cris_special_register_name (gdbarch, regno);
1731 /* Invalid register. */
1737 crisv32_register_name (struct gdbarch *gdbarch, int regno)
1739 static char *crisv32_genreg_names[] =
1740 { "r0", "r1", "r2", "r3", \
1741 "r4", "r5", "r6", "r7", \
1742 "r8", "r9", "r10", "r11", \
1743 "r12", "r13", "sp", "acr"
1746 static char *crisv32_sreg_names[] =
1747 { "s0", "s1", "s2", "s3", \
1748 "s4", "s5", "s6", "s7", \
1749 "s8", "s9", "s10", "s11", \
1750 "s12", "s13", "s14", "s15"
1753 if (regno >= 0 && regno < NUM_GENREGS)
1755 /* General register. */
1756 return crisv32_genreg_names[regno];
1758 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1760 return cris_special_register_name (gdbarch, regno);
1762 else if (regno == gdbarch_pc_regnum (gdbarch))
1766 else if (regno >= S0_REGNUM && regno <= S15_REGNUM)
1768 return crisv32_sreg_names[regno - S0_REGNUM];
1772 /* Invalid register. */
1777 /* Convert DWARF register number REG to the appropriate register
1778 number used by GDB. */
1781 cris_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1783 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1784 numbering, MOF is 18).
1785 Adapted from gcc/config/cris/cris.h. */
1786 static int cris_dwarf_regmap[] = {
1798 if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap))
1799 regnum = cris_dwarf_regmap[reg];
1802 warning (_("Unmapped DWARF Register #%d encountered."), reg);
1807 /* DWARF-2 frame support. */
1810 cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1811 struct dwarf2_frame_state_reg *reg,
1812 struct frame_info *this_frame)
1814 /* The return address column. */
1815 if (regnum == gdbarch_pc_regnum (gdbarch))
1816 reg->how = DWARF2_FRAME_REG_RA;
1818 /* The call frame address. */
1819 else if (regnum == gdbarch_sp_regnum (gdbarch))
1820 reg->how = DWARF2_FRAME_REG_CFA;
1823 /* Extract from an array regbuf containing the raw register state a function
1824 return value of type type, and copy that, in virtual format, into
1827 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1830 cris_extract_return_value (struct type *type, struct regcache *regcache,
1833 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1834 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1837 if (TYPE_LENGTH (type) <= 4)
1839 /* Get the return value from R10. */
1840 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1841 store_unsigned_integer (valbuf, TYPE_LENGTH (type), byte_order, val);
1843 else if (TYPE_LENGTH (type) <= 8)
1845 /* Get the return value from R10 and R11. */
1846 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1847 store_unsigned_integer (valbuf, 4, byte_order, val);
1848 regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val);
1849 store_unsigned_integer ((char *)valbuf + 4, TYPE_LENGTH (type) - 4,
1853 error (_("cris_extract_return_value: type length too large"));
1856 /* Handle the CRIS return value convention. */
1858 static enum return_value_convention
1859 cris_return_value (struct gdbarch *gdbarch, struct value *function,
1860 struct type *type, struct regcache *regcache,
1861 gdb_byte *readbuf, const gdb_byte *writebuf)
1863 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1864 || TYPE_CODE (type) == TYPE_CODE_UNION
1865 || TYPE_LENGTH (type) > 8)
1866 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1867 goes on the stack. */
1868 return RETURN_VALUE_STRUCT_CONVENTION;
1871 cris_extract_return_value (type, regcache, readbuf);
1873 cris_store_return_value (type, regcache, writebuf);
1875 return RETURN_VALUE_REGISTER_CONVENTION;
1878 /* Calculates a value that measures how good inst_args constraints an
1879 instruction. It stems from cris_constraint, found in cris-dis.c. */
1882 constraint (unsigned int insn, const signed char *inst_args,
1883 inst_env_type *inst_env)
1888 const char *s = inst_args;
1894 if ((insn & 0x30) == 0x30)
1899 /* A prefix operand. */
1900 if (inst_env->prefix_found)
1906 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1907 valid "push" size. In case of special register, it may be != 4. */
1908 if (inst_env->prefix_found)
1914 retval = (((insn >> 0xC) & 0xF) == (insn & 0xF));
1922 tmp = (insn >> 0xC) & 0xF;
1924 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1926 /* Since we match four bits, we will give a value of
1927 4 - 1 = 3 in a match. If there is a corresponding
1928 exact match of a special register in another pattern, it
1929 will get a value of 4, which will be higher. This should
1930 be correct in that an exact pattern would match better that
1932 Note that there is a reason for not returning zero; the
1933 pattern for "clear" is partly matched in the bit-pattern
1934 (the two lower bits must be zero), while the bit-pattern
1935 for a move from a special register is matched in the
1936 register constraint.
1937 This also means we will will have a race condition if
1938 there is a partly match in three bits in the bit pattern. */
1939 if (tmp == cris_spec_regs[i].number)
1946 if (cris_spec_regs[i].name == NULL)
1953 /* Returns the number of bits set in the variable value. */
1956 number_of_bits (unsigned int value)
1958 int number_of_bits = 0;
1962 number_of_bits += 1;
1963 value &= (value - 1);
1965 return number_of_bits;
1968 /* Finds the address that should contain the single step breakpoint(s).
1969 It stems from code in cris-dis.c. */
1972 find_cris_op (unsigned short insn, inst_env_type *inst_env)
1975 int max_level_of_match = -1;
1976 int max_matched = -1;
1979 for (i = 0; cris_opcodes[i].name != NULL; i++)
1981 if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match)
1982 && ((cris_opcodes[i].lose & insn) == 0)
1983 /* Only CRISv10 instructions, please. */
1984 && (cris_opcodes[i].applicable_version != cris_ver_v32p))
1986 level_of_match = constraint (insn, cris_opcodes[i].args, inst_env);
1987 if (level_of_match >= 0)
1990 number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose);
1991 if (level_of_match > max_level_of_match)
1994 max_level_of_match = level_of_match;
1995 if (level_of_match == 16)
1997 /* All bits matched, cannot find better. */
2007 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
2008 actually an internal error. */
2011 find_step_target (struct frame_info *frame, inst_env_type *inst_env)
2015 unsigned short insn;
2016 struct gdbarch *gdbarch = get_frame_arch (frame);
2017 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2019 /* Create a local register image and set the initial state. */
2020 for (i = 0; i < NUM_GENREGS; i++)
2023 (unsigned long) get_frame_register_unsigned (frame, i);
2025 offset = NUM_GENREGS;
2026 for (i = 0; i < NUM_SPECREGS; i++)
2029 (unsigned long) get_frame_register_unsigned (frame, offset + i);
2031 inst_env->branch_found = 0;
2032 inst_env->slot_needed = 0;
2033 inst_env->delay_slot_pc_active = 0;
2034 inst_env->prefix_found = 0;
2035 inst_env->invalid = 0;
2036 inst_env->xflag_found = 0;
2037 inst_env->disable_interrupt = 0;
2038 inst_env->byte_order = byte_order;
2040 /* Look for a step target. */
2043 /* Read an instruction from the client. */
2044 insn = read_memory_unsigned_integer
2045 (inst_env->reg[gdbarch_pc_regnum (gdbarch)], 2, byte_order);
2047 /* If the instruction is not in a delay slot the new content of the
2048 PC is [PC] + 2. If the instruction is in a delay slot it is not
2049 that simple. Since a instruction in a delay slot cannot change
2050 the content of the PC, it does not matter what value PC will have.
2051 Just make sure it is a valid instruction. */
2052 if (!inst_env->delay_slot_pc_active)
2054 inst_env->reg[gdbarch_pc_regnum (gdbarch)] += 2;
2058 inst_env->delay_slot_pc_active = 0;
2059 inst_env->reg[gdbarch_pc_regnum (gdbarch)]
2060 = inst_env->delay_slot_pc;
2062 /* Analyse the present instruction. */
2063 i = find_cris_op (insn, inst_env);
2066 inst_env->invalid = 1;
2070 cris_gdb_func (gdbarch, cris_opcodes[i].op, insn, inst_env);
2072 } while (!inst_env->invalid
2073 && (inst_env->prefix_found || inst_env->xflag_found
2074 || inst_env->slot_needed));
2078 /* There is no hardware single-step support. The function find_step_target
2079 digs through the opcodes in order to find all possible targets.
2080 Either one ordinary target or two targets for branches may be found. */
2083 cris_software_single_step (struct frame_info *frame)
2085 struct gdbarch *gdbarch = get_frame_arch (frame);
2086 struct address_space *aspace = get_frame_address_space (frame);
2087 inst_env_type inst_env;
2089 /* Analyse the present instruction environment and insert
2091 int status = find_step_target (frame, &inst_env);
2094 /* Could not find a target. Things are likely to go downhill
2096 warning (_("CRIS software single step could not find a step target."));
2100 /* Insert at most two breakpoints. One for the next PC content
2101 and possibly another one for a branch, jump, etc. */
2103 = (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (gdbarch)];
2104 insert_single_step_breakpoint (gdbarch, aspace, next_pc);
2105 if (inst_env.branch_found
2106 && (CORE_ADDR) inst_env.branch_break_address != next_pc)
2108 CORE_ADDR branch_target_address
2109 = (CORE_ADDR) inst_env.branch_break_address;
2110 insert_single_step_breakpoint (gdbarch,
2111 aspace, branch_target_address);
2118 /* Calculates the prefix value for quick offset addressing mode. */
2121 quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2123 /* It's invalid to be in a delay slot. You can't have a prefix to this
2124 instruction (not 100% sure). */
2125 if (inst_env->slot_needed || inst_env->prefix_found)
2127 inst_env->invalid = 1;
2131 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2132 inst_env->prefix_value += cris_get_bdap_quick_offset (inst);
2134 /* A prefix doesn't change the xflag_found. But the rest of the flags
2136 inst_env->slot_needed = 0;
2137 inst_env->prefix_found = 1;
2140 /* Updates the autoincrement register. The size of the increment is derived
2141 from the size of the operation. The PC is always kept aligned on even
2145 process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env)
2147 if (size == INST_BYTE_SIZE)
2149 inst_env->reg[cris_get_operand1 (inst)] += 1;
2151 /* The PC must be word aligned, so increase the PC with one
2152 word even if the size is byte. */
2153 if (cris_get_operand1 (inst) == REG_PC)
2155 inst_env->reg[REG_PC] += 1;
2158 else if (size == INST_WORD_SIZE)
2160 inst_env->reg[cris_get_operand1 (inst)] += 2;
2162 else if (size == INST_DWORD_SIZE)
2164 inst_env->reg[cris_get_operand1 (inst)] += 4;
2169 inst_env->invalid = 1;
2173 /* Just a forward declaration. */
2175 static unsigned long get_data_from_address (unsigned short *inst,
2177 enum bfd_endian byte_order);
2179 /* Calculates the prefix value for the general case of offset addressing
2183 bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2185 /* It's invalid to be in a delay slot. */
2186 if (inst_env->slot_needed || inst_env->prefix_found)
2188 inst_env->invalid = 1;
2192 /* The calculation of prefix_value used to be after process_autoincrement,
2193 but that fails for an instruction such as jsr [$r0+12] which is encoded
2194 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
2195 mustn't be incremented until we have read it and what it points at. */
2196 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2198 /* The offset is an indirection of the contents of the operand1 register. */
2199 inst_env->prefix_value +=
2200 get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)],
2201 inst_env->byte_order);
2203 if (cris_get_mode (inst) == AUTOINC_MODE)
2205 process_autoincrement (cris_get_size (inst), inst, inst_env);
2208 /* A prefix doesn't change the xflag_found. But the rest of the flags
2210 inst_env->slot_needed = 0;
2211 inst_env->prefix_found = 1;
2214 /* Calculates the prefix value for the index addressing mode. */
2217 biap_prefix (unsigned short inst, inst_env_type *inst_env)
2219 /* It's invalid to be in a delay slot. I can't see that it's possible to
2220 have a prefix to this instruction. So I will treat this as invalid. */
2221 if (inst_env->slot_needed || inst_env->prefix_found)
2223 inst_env->invalid = 1;
2227 inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)];
2229 /* The offset is the operand2 value shifted the size of the instruction
2231 inst_env->prefix_value +=
2232 inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst);
2234 /* If the PC is operand1 (base) the address used is the address after
2235 the main instruction, i.e. address + 2 (the PC is already compensated
2236 for the prefix operation). */
2237 if (cris_get_operand1 (inst) == REG_PC)
2239 inst_env->prefix_value += 2;
2242 /* A prefix doesn't change the xflag_found. But the rest of the flags
2244 inst_env->slot_needed = 0;
2245 inst_env->xflag_found = 0;
2246 inst_env->prefix_found = 1;
2249 /* Calculates the prefix value for the double indirect addressing mode. */
2252 dip_prefix (unsigned short inst, inst_env_type *inst_env)
2257 /* It's invalid to be in a delay slot. */
2258 if (inst_env->slot_needed || inst_env->prefix_found)
2260 inst_env->invalid = 1;
2264 /* The prefix value is one dereference of the contents of the operand1
2266 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2267 inst_env->prefix_value
2268 = read_memory_unsigned_integer (address, 4, inst_env->byte_order);
2270 /* Check if the mode is autoincrement. */
2271 if (cris_get_mode (inst) == AUTOINC_MODE)
2273 inst_env->reg[cris_get_operand1 (inst)] += 4;
2276 /* A prefix doesn't change the xflag_found. But the rest of the flags
2278 inst_env->slot_needed = 0;
2279 inst_env->xflag_found = 0;
2280 inst_env->prefix_found = 1;
2283 /* Finds the destination for a branch with 8-bits offset. */
2286 eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2291 /* If we have a prefix or are in a delay slot it's bad. */
2292 if (inst_env->slot_needed || inst_env->prefix_found)
2294 inst_env->invalid = 1;
2298 /* We have a branch, find out where the branch will land. */
2299 offset = cris_get_branch_short_offset (inst);
2301 /* Check if the offset is signed. */
2302 if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK)
2307 /* The offset ends with the sign bit, set it to zero. The address
2308 should always be word aligned. */
2309 offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK;
2311 inst_env->branch_found = 1;
2312 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2314 inst_env->slot_needed = 1;
2315 inst_env->prefix_found = 0;
2316 inst_env->xflag_found = 0;
2317 inst_env->disable_interrupt = 1;
2320 /* Finds the destination for a branch with 16-bits offset. */
2323 sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2327 /* If we have a prefix or is in a delay slot it's bad. */
2328 if (inst_env->slot_needed || inst_env->prefix_found)
2330 inst_env->invalid = 1;
2334 /* We have a branch, find out the offset for the branch. */
2335 offset = read_memory_integer (inst_env->reg[REG_PC], 2,
2336 inst_env->byte_order);
2338 /* The instruction is one word longer than normal, so add one word
2340 inst_env->reg[REG_PC] += 2;
2342 inst_env->branch_found = 1;
2343 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2346 inst_env->slot_needed = 1;
2347 inst_env->prefix_found = 0;
2348 inst_env->xflag_found = 0;
2349 inst_env->disable_interrupt = 1;
2352 /* Handles the ABS instruction. */
2355 abs_op (unsigned short inst, inst_env_type *inst_env)
2360 /* ABS can't have a prefix, so it's bad if it does. */
2361 if (inst_env->prefix_found)
2363 inst_env->invalid = 1;
2367 /* Check if the operation affects the PC. */
2368 if (cris_get_operand2 (inst) == REG_PC)
2371 /* It's invalid to change to the PC if we are in a delay slot. */
2372 if (inst_env->slot_needed)
2374 inst_env->invalid = 1;
2378 value = (long) inst_env->reg[REG_PC];
2380 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
2381 if (value != SIGNED_DWORD_MASK)
2384 inst_env->reg[REG_PC] = (long) value;
2388 inst_env->slot_needed = 0;
2389 inst_env->prefix_found = 0;
2390 inst_env->xflag_found = 0;
2391 inst_env->disable_interrupt = 0;
2394 /* Handles the ADDI instruction. */
2397 addi_op (unsigned short inst, inst_env_type *inst_env)
2399 /* It's invalid to have the PC as base register. And ADDI can't have
2401 if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC))
2403 inst_env->invalid = 1;
2407 inst_env->slot_needed = 0;
2408 inst_env->prefix_found = 0;
2409 inst_env->xflag_found = 0;
2410 inst_env->disable_interrupt = 0;
2413 /* Handles the ASR instruction. */
2416 asr_op (unsigned short inst, inst_env_type *inst_env)
2419 unsigned long value;
2420 unsigned long signed_extend_mask = 0;
2422 /* ASR can't have a prefix, so check that it doesn't. */
2423 if (inst_env->prefix_found)
2425 inst_env->invalid = 1;
2429 /* Check if the PC is the target register. */
2430 if (cris_get_operand2 (inst) == REG_PC)
2432 /* It's invalid to change the PC in a delay slot. */
2433 if (inst_env->slot_needed)
2435 inst_env->invalid = 1;
2438 /* Get the number of bits to shift. */
2440 = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]);
2441 value = inst_env->reg[REG_PC];
2443 /* Find out how many bits the operation should apply to. */
2444 if (cris_get_size (inst) == INST_BYTE_SIZE)
2446 if (value & SIGNED_BYTE_MASK)
2448 signed_extend_mask = 0xFF;
2449 signed_extend_mask = signed_extend_mask >> shift_steps;
2450 signed_extend_mask = ~signed_extend_mask;
2452 value = value >> shift_steps;
2453 value |= signed_extend_mask;
2455 inst_env->reg[REG_PC] &= 0xFFFFFF00;
2456 inst_env->reg[REG_PC] |= value;
2458 else if (cris_get_size (inst) == INST_WORD_SIZE)
2460 if (value & SIGNED_WORD_MASK)
2462 signed_extend_mask = 0xFFFF;
2463 signed_extend_mask = signed_extend_mask >> shift_steps;
2464 signed_extend_mask = ~signed_extend_mask;
2466 value = value >> shift_steps;
2467 value |= signed_extend_mask;
2469 inst_env->reg[REG_PC] &= 0xFFFF0000;
2470 inst_env->reg[REG_PC] |= value;
2472 else if (cris_get_size (inst) == INST_DWORD_SIZE)
2474 if (value & SIGNED_DWORD_MASK)
2476 signed_extend_mask = 0xFFFFFFFF;
2477 signed_extend_mask = signed_extend_mask >> shift_steps;
2478 signed_extend_mask = ~signed_extend_mask;
2480 value = value >> shift_steps;
2481 value |= signed_extend_mask;
2482 inst_env->reg[REG_PC] = value;
2485 inst_env->slot_needed = 0;
2486 inst_env->prefix_found = 0;
2487 inst_env->xflag_found = 0;
2488 inst_env->disable_interrupt = 0;
2491 /* Handles the ASRQ instruction. */
2494 asrq_op (unsigned short inst, inst_env_type *inst_env)
2498 unsigned long value;
2499 unsigned long signed_extend_mask = 0;
2501 /* ASRQ can't have a prefix, so check that it doesn't. */
2502 if (inst_env->prefix_found)
2504 inst_env->invalid = 1;
2508 /* Check if the PC is the target register. */
2509 if (cris_get_operand2 (inst) == REG_PC)
2512 /* It's invalid to change the PC in a delay slot. */
2513 if (inst_env->slot_needed)
2515 inst_env->invalid = 1;
2518 /* The shift size is given as a 5 bit quick value, i.e. we don't
2519 want the sign bit of the quick value. */
2520 shift_steps = cris_get_asr_shift_steps (inst);
2521 value = inst_env->reg[REG_PC];
2522 if (value & SIGNED_DWORD_MASK)
2524 signed_extend_mask = 0xFFFFFFFF;
2525 signed_extend_mask = signed_extend_mask >> shift_steps;
2526 signed_extend_mask = ~signed_extend_mask;
2528 value = value >> shift_steps;
2529 value |= signed_extend_mask;
2530 inst_env->reg[REG_PC] = value;
2532 inst_env->slot_needed = 0;
2533 inst_env->prefix_found = 0;
2534 inst_env->xflag_found = 0;
2535 inst_env->disable_interrupt = 0;
2538 /* Handles the AX, EI and SETF instruction. */
2541 ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env)
2543 if (inst_env->prefix_found)
2545 inst_env->invalid = 1;
2548 /* Check if the instruction is setting the X flag. */
2549 if (cris_is_xflag_bit_on (inst))
2551 inst_env->xflag_found = 1;
2555 inst_env->xflag_found = 0;
2557 inst_env->slot_needed = 0;
2558 inst_env->prefix_found = 0;
2559 inst_env->disable_interrupt = 1;
2562 /* Checks if the instruction is in assign mode. If so, it updates the assign
2563 register. Note that check_assign assumes that the caller has checked that
2564 there is a prefix to this instruction. The mode check depends on this. */
2567 check_assign (unsigned short inst, inst_env_type *inst_env)
2569 /* Check if it's an assign addressing mode. */
2570 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2572 /* Assign the prefix value to operand 1. */
2573 inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value;
2577 /* Handles the 2-operand BOUND instruction. */
2580 two_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2582 /* It's invalid to have the PC as the index operand. */
2583 if (cris_get_operand2 (inst) == REG_PC)
2585 inst_env->invalid = 1;
2588 /* Check if we have a prefix. */
2589 if (inst_env->prefix_found)
2591 check_assign (inst, inst_env);
2593 /* Check if this is an autoincrement mode. */
2594 else if (cris_get_mode (inst) == AUTOINC_MODE)
2596 /* It's invalid to change the PC in a delay slot. */
2597 if (inst_env->slot_needed)
2599 inst_env->invalid = 1;
2602 process_autoincrement (cris_get_size (inst), inst, inst_env);
2604 inst_env->slot_needed = 0;
2605 inst_env->prefix_found = 0;
2606 inst_env->xflag_found = 0;
2607 inst_env->disable_interrupt = 0;
2610 /* Handles the 3-operand BOUND instruction. */
2613 three_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2615 /* It's an error if we haven't got a prefix. And it's also an error
2616 if the PC is the destination register. */
2617 if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC))
2619 inst_env->invalid = 1;
2622 inst_env->slot_needed = 0;
2623 inst_env->prefix_found = 0;
2624 inst_env->xflag_found = 0;
2625 inst_env->disable_interrupt = 0;
2628 /* Clears the status flags in inst_env. */
2631 btst_nop_op (unsigned short inst, inst_env_type *inst_env)
2633 /* It's an error if we have got a prefix. */
2634 if (inst_env->prefix_found)
2636 inst_env->invalid = 1;
2640 inst_env->slot_needed = 0;
2641 inst_env->prefix_found = 0;
2642 inst_env->xflag_found = 0;
2643 inst_env->disable_interrupt = 0;
2646 /* Clears the status flags in inst_env. */
2649 clearf_di_op (unsigned short inst, inst_env_type *inst_env)
2651 /* It's an error if we have got a prefix. */
2652 if (inst_env->prefix_found)
2654 inst_env->invalid = 1;
2658 inst_env->slot_needed = 0;
2659 inst_env->prefix_found = 0;
2660 inst_env->xflag_found = 0;
2661 inst_env->disable_interrupt = 1;
2664 /* Handles the CLEAR instruction if it's in register mode. */
2667 reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env)
2669 /* Check if the target is the PC. */
2670 if (cris_get_operand2 (inst) == REG_PC)
2672 /* The instruction will clear the instruction's size bits. */
2673 int clear_size = cris_get_clear_size (inst);
2674 if (clear_size == INST_BYTE_SIZE)
2676 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00;
2678 if (clear_size == INST_WORD_SIZE)
2680 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000;
2682 if (clear_size == INST_DWORD_SIZE)
2684 inst_env->delay_slot_pc = 0x0;
2686 /* The jump will be delayed with one delay slot. So we need a delay
2688 inst_env->slot_needed = 1;
2689 inst_env->delay_slot_pc_active = 1;
2693 /* The PC will not change => no delay slot. */
2694 inst_env->slot_needed = 0;
2696 inst_env->prefix_found = 0;
2697 inst_env->xflag_found = 0;
2698 inst_env->disable_interrupt = 0;
2701 /* Handles the TEST instruction if it's in register mode. */
2704 reg_mode_test_op (unsigned short inst, inst_env_type *inst_env)
2706 /* It's an error if we have got a prefix. */
2707 if (inst_env->prefix_found)
2709 inst_env->invalid = 1;
2712 inst_env->slot_needed = 0;
2713 inst_env->prefix_found = 0;
2714 inst_env->xflag_found = 0;
2715 inst_env->disable_interrupt = 0;
2719 /* Handles the CLEAR and TEST instruction if the instruction isn't
2720 in register mode. */
2723 none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env)
2725 /* Check if we are in a prefix mode. */
2726 if (inst_env->prefix_found)
2728 /* The only way the PC can change is if this instruction is in
2729 assign addressing mode. */
2730 check_assign (inst, inst_env);
2732 /* Indirect mode can't change the PC so just check if the mode is
2734 else if (cris_get_mode (inst) == AUTOINC_MODE)
2736 process_autoincrement (cris_get_size (inst), inst, inst_env);
2738 inst_env->slot_needed = 0;
2739 inst_env->prefix_found = 0;
2740 inst_env->xflag_found = 0;
2741 inst_env->disable_interrupt = 0;
2744 /* Checks that the PC isn't the destination register or the instructions has
2748 dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env)
2750 /* It's invalid to have the PC as the destination. The instruction can't
2752 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2754 inst_env->invalid = 1;
2758 inst_env->slot_needed = 0;
2759 inst_env->prefix_found = 0;
2760 inst_env->xflag_found = 0;
2761 inst_env->disable_interrupt = 0;
2764 /* Checks that the instruction doesn't have a prefix. */
2767 break_op (unsigned short inst, inst_env_type *inst_env)
2769 /* The instruction can't have a prefix. */
2770 if (inst_env->prefix_found)
2772 inst_env->invalid = 1;
2776 inst_env->slot_needed = 0;
2777 inst_env->prefix_found = 0;
2778 inst_env->xflag_found = 0;
2779 inst_env->disable_interrupt = 1;
2782 /* Checks that the PC isn't the destination register and that the instruction
2783 doesn't have a prefix. */
2786 scc_op (unsigned short inst, inst_env_type *inst_env)
2788 /* It's invalid to have the PC as the destination. The instruction can't
2790 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2792 inst_env->invalid = 1;
2796 inst_env->slot_needed = 0;
2797 inst_env->prefix_found = 0;
2798 inst_env->xflag_found = 0;
2799 inst_env->disable_interrupt = 1;
2802 /* Handles the register mode JUMP instruction. */
2805 reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2807 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2808 you can't have a prefix. */
2809 if ((inst_env->slot_needed) || (inst_env->prefix_found))
2811 inst_env->invalid = 1;
2815 /* Just change the PC. */
2816 inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)];
2817 inst_env->slot_needed = 0;
2818 inst_env->prefix_found = 0;
2819 inst_env->xflag_found = 0;
2820 inst_env->disable_interrupt = 1;
2823 /* Handles the JUMP instruction for all modes except register. */
2826 none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2828 unsigned long newpc;
2831 /* It's invalid to do a JUMP in a delay slot. */
2832 if (inst_env->slot_needed)
2834 inst_env->invalid = 1;
2838 /* Check if we have a prefix. */
2839 if (inst_env->prefix_found)
2841 check_assign (inst, inst_env);
2843 /* Get the new value for the PC. */
2845 read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value,
2846 4, inst_env->byte_order);
2850 /* Get the new value for the PC. */
2851 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2852 newpc = read_memory_unsigned_integer (address,
2853 4, inst_env->byte_order);
2855 /* Check if we should increment a register. */
2856 if (cris_get_mode (inst) == AUTOINC_MODE)
2858 inst_env->reg[cris_get_operand1 (inst)] += 4;
2861 inst_env->reg[REG_PC] = newpc;
2863 inst_env->slot_needed = 0;
2864 inst_env->prefix_found = 0;
2865 inst_env->xflag_found = 0;
2866 inst_env->disable_interrupt = 1;
2869 /* Handles moves to special registers (aka P-register) for all modes. */
2872 move_to_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2873 inst_env_type *inst_env)
2875 if (inst_env->prefix_found)
2877 /* The instruction has a prefix that means we are only interested if
2878 the instruction is in assign mode. */
2879 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2881 /* The prefix handles the problem if we are in a delay slot. */
2882 if (cris_get_operand1 (inst) == REG_PC)
2884 /* Just take care of the assign. */
2885 check_assign (inst, inst_env);
2889 else if (cris_get_mode (inst) == AUTOINC_MODE)
2891 /* The instruction doesn't have a prefix, the only case left that we
2892 are interested in is the autoincrement mode. */
2893 if (cris_get_operand1 (inst) == REG_PC)
2895 /* If the PC is to be incremented it's invalid to be in a
2897 if (inst_env->slot_needed)
2899 inst_env->invalid = 1;
2903 /* The increment depends on the size of the special register. */
2904 if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
2906 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2908 else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
2910 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2914 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2918 inst_env->slot_needed = 0;
2919 inst_env->prefix_found = 0;
2920 inst_env->xflag_found = 0;
2921 inst_env->disable_interrupt = 1;
2924 /* Handles moves from special registers (aka P-register) for all modes
2928 none_reg_mode_move_from_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2929 inst_env_type *inst_env)
2931 if (inst_env->prefix_found)
2933 /* The instruction has a prefix that means we are only interested if
2934 the instruction is in assign mode. */
2935 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2937 /* The prefix handles the problem if we are in a delay slot. */
2938 if (cris_get_operand1 (inst) == REG_PC)
2940 /* Just take care of the assign. */
2941 check_assign (inst, inst_env);
2945 /* The instruction doesn't have a prefix, the only case left that we
2946 are interested in is the autoincrement mode. */
2947 else if (cris_get_mode (inst) == AUTOINC_MODE)
2949 if (cris_get_operand1 (inst) == REG_PC)
2951 /* If the PC is to be incremented it's invalid to be in a
2953 if (inst_env->slot_needed)
2955 inst_env->invalid = 1;
2959 /* The increment depends on the size of the special register. */
2960 if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
2962 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2964 else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
2966 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2970 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2974 inst_env->slot_needed = 0;
2975 inst_env->prefix_found = 0;
2976 inst_env->xflag_found = 0;
2977 inst_env->disable_interrupt = 1;
2980 /* Handles moves from special registers (aka P-register) when the mode
2984 reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env)
2986 /* Register mode move from special register can't have a prefix. */
2987 if (inst_env->prefix_found)
2989 inst_env->invalid = 1;
2993 if (cris_get_operand1 (inst) == REG_PC)
2995 /* It's invalid to change the PC in a delay slot. */
2996 if (inst_env->slot_needed)
2998 inst_env->invalid = 1;
3001 /* The destination is the PC, the jump will have a delay slot. */
3002 inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)];
3003 inst_env->slot_needed = 1;
3004 inst_env->delay_slot_pc_active = 1;
3008 /* If the destination isn't PC, there will be no jump. */
3009 inst_env->slot_needed = 0;
3011 inst_env->prefix_found = 0;
3012 inst_env->xflag_found = 0;
3013 inst_env->disable_interrupt = 1;
3016 /* Handles the MOVEM from memory to general register instruction. */
3019 move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env)
3021 if (inst_env->prefix_found)
3023 /* The prefix handles the problem if we are in a delay slot. Is the
3024 MOVEM instruction going to change the PC? */
3025 if (cris_get_operand2 (inst) >= REG_PC)
3027 inst_env->reg[REG_PC] =
3028 read_memory_unsigned_integer (inst_env->prefix_value,
3029 4, inst_env->byte_order);
3031 /* The assign value is the value after the increment. Normally, the
3032 assign value is the value before the increment. */
3033 if ((cris_get_operand1 (inst) == REG_PC)
3034 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3036 inst_env->reg[REG_PC] = inst_env->prefix_value;
3037 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3042 /* Is the MOVEM instruction going to change the PC? */
3043 if (cris_get_operand2 (inst) == REG_PC)
3045 /* It's invalid to change the PC in a delay slot. */
3046 if (inst_env->slot_needed)
3048 inst_env->invalid = 1;
3051 inst_env->reg[REG_PC] =
3052 read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)],
3053 4, inst_env->byte_order);
3055 /* The increment is not depending on the size, instead it's depending
3056 on the number of registers loaded from memory. */
3057 if ((cris_get_operand1 (inst) == REG_PC)
3058 && (cris_get_mode (inst) == AUTOINC_MODE))
3060 /* It's invalid to change the PC in a delay slot. */
3061 if (inst_env->slot_needed)
3063 inst_env->invalid = 1;
3066 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3069 inst_env->slot_needed = 0;
3070 inst_env->prefix_found = 0;
3071 inst_env->xflag_found = 0;
3072 inst_env->disable_interrupt = 0;
3075 /* Handles the MOVEM to memory from general register instruction. */
3078 move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env)
3080 if (inst_env->prefix_found)
3082 /* The assign value is the value after the increment. Normally, the
3083 assign value is the value before the increment. */
3084 if ((cris_get_operand1 (inst) == REG_PC)
3085 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3087 /* The prefix handles the problem if we are in a delay slot. */
3088 inst_env->reg[REG_PC] = inst_env->prefix_value;
3089 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3094 /* The increment is not depending on the size, instead it's depending
3095 on the number of registers loaded to memory. */
3096 if ((cris_get_operand1 (inst) == REG_PC)
3097 && (cris_get_mode (inst) == AUTOINC_MODE))
3099 /* It's invalid to change the PC in a delay slot. */
3100 if (inst_env->slot_needed)
3102 inst_env->invalid = 1;
3105 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3108 inst_env->slot_needed = 0;
3109 inst_env->prefix_found = 0;
3110 inst_env->xflag_found = 0;
3111 inst_env->disable_interrupt = 0;
3114 /* Handles the intructions that's not yet implemented, by setting
3115 inst_env->invalid to true. */
3118 not_implemented_op (unsigned short inst, inst_env_type *inst_env)
3120 inst_env->invalid = 1;
3123 /* Handles the XOR instruction. */
3126 xor_op (unsigned short inst, inst_env_type *inst_env)
3128 /* XOR can't have a prefix. */
3129 if (inst_env->prefix_found)
3131 inst_env->invalid = 1;
3135 /* Check if the PC is the target. */
3136 if (cris_get_operand2 (inst) == REG_PC)
3138 /* It's invalid to change the PC in a delay slot. */
3139 if (inst_env->slot_needed)
3141 inst_env->invalid = 1;
3144 inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)];
3146 inst_env->slot_needed = 0;
3147 inst_env->prefix_found = 0;
3148 inst_env->xflag_found = 0;
3149 inst_env->disable_interrupt = 0;
3152 /* Handles the MULS instruction. */
3155 muls_op (unsigned short inst, inst_env_type *inst_env)
3157 /* MULS/U can't have a prefix. */
3158 if (inst_env->prefix_found)
3160 inst_env->invalid = 1;
3164 /* Consider it invalid if the PC is the target. */
3165 if (cris_get_operand2 (inst) == REG_PC)
3167 inst_env->invalid = 1;
3170 inst_env->slot_needed = 0;
3171 inst_env->prefix_found = 0;
3172 inst_env->xflag_found = 0;
3173 inst_env->disable_interrupt = 0;
3176 /* Handles the MULU instruction. */
3179 mulu_op (unsigned short inst, inst_env_type *inst_env)
3181 /* MULS/U can't have a prefix. */
3182 if (inst_env->prefix_found)
3184 inst_env->invalid = 1;
3188 /* Consider it invalid if the PC is the target. */
3189 if (cris_get_operand2 (inst) == REG_PC)
3191 inst_env->invalid = 1;
3194 inst_env->slot_needed = 0;
3195 inst_env->prefix_found = 0;
3196 inst_env->xflag_found = 0;
3197 inst_env->disable_interrupt = 0;
3200 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
3201 The MOVE instruction is the move from source to register. */
3204 add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env,
3205 unsigned long source1, unsigned long source2)
3207 unsigned long pc_mask;
3208 unsigned long operation_mask;
3210 /* Find out how many bits the operation should apply to. */
3211 if (cris_get_size (inst) == INST_BYTE_SIZE)
3213 pc_mask = 0xFFFFFF00;
3214 operation_mask = 0xFF;
3216 else if (cris_get_size (inst) == INST_WORD_SIZE)
3218 pc_mask = 0xFFFF0000;
3219 operation_mask = 0xFFFF;
3221 else if (cris_get_size (inst) == INST_DWORD_SIZE)
3224 operation_mask = 0xFFFFFFFF;
3228 /* The size is out of range. */
3229 inst_env->invalid = 1;
3233 /* The instruction just works on uw_operation_mask bits. */
3234 source2 &= operation_mask;
3235 source1 &= operation_mask;
3237 /* Now calculate the result. The opcode's 3 first bits separates
3238 the different actions. */
3239 switch (cris_get_opcode (inst) & 7)
3249 case 2: /* subtract */
3253 case 3: /* compare */
3265 inst_env->invalid = 1;
3271 /* Make sure that the result doesn't contain more than the instruction
3273 source2 &= operation_mask;
3275 /* Calculate the new breakpoint address. */
3276 inst_env->reg[REG_PC] &= pc_mask;
3277 inst_env->reg[REG_PC] |= source1;
3281 /* Extends the value from either byte or word size to a dword. If the mode
3282 is zero extend then the value is extended with zero. If instead the mode
3283 is signed extend the sign bit of the value is taken into consideration. */
3285 static unsigned long
3286 do_sign_or_zero_extend (unsigned long value, unsigned short *inst)
3288 /* The size can be either byte or word, check which one it is.
3289 Don't check the highest bit, it's indicating if it's a zero
3291 if (cris_get_size (*inst) & INST_WORD_SIZE)
3296 /* Check if the instruction is signed extend. If so, check if value has
3298 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK))
3300 value |= SIGNED_WORD_EXTEND_MASK;
3308 /* Check if the instruction is signed extend. If so, check if value has
3310 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK))
3312 value |= SIGNED_BYTE_EXTEND_MASK;
3315 /* The size should now be dword. */
3316 cris_set_size_to_dword (inst);
3320 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3321 instruction. The MOVE instruction is the move from source to register. */
3324 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3325 inst_env_type *inst_env)
3327 unsigned long operand1;
3328 unsigned long operand2;
3330 /* It's invalid to have a prefix to the instruction. This is a register
3331 mode instruction and can't have a prefix. */
3332 if (inst_env->prefix_found)
3334 inst_env->invalid = 1;
3337 /* Check if the instruction has PC as its target. */
3338 if (cris_get_operand2 (inst) == REG_PC)
3340 if (inst_env->slot_needed)
3342 inst_env->invalid = 1;
3345 /* The instruction has the PC as its target register. */
3346 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3347 operand2 = inst_env->reg[REG_PC];
3349 /* Check if it's a extend, signed or zero instruction. */
3350 if (cris_get_opcode (inst) < 4)
3352 operand1 = do_sign_or_zero_extend (operand1, &inst);
3354 /* Calculate the PC value after the instruction, i.e. where the
3355 breakpoint should be. The order of the udw_operands is vital. */
3356 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3358 inst_env->slot_needed = 0;
3359 inst_env->prefix_found = 0;
3360 inst_env->xflag_found = 0;
3361 inst_env->disable_interrupt = 0;
3364 /* Returns the data contained at address. The size of the data is derived from
3365 the size of the operation. If the instruction is a zero or signed
3366 extend instruction, the size field is changed in instruction. */
3368 static unsigned long
3369 get_data_from_address (unsigned short *inst, CORE_ADDR address,
3370 enum bfd_endian byte_order)
3372 int size = cris_get_size (*inst);
3373 unsigned long value;
3375 /* If it's an extend instruction we don't want the signed extend bit,
3376 because it influences the size. */
3377 if (cris_get_opcode (*inst) < 4)
3379 size &= ~SIGNED_EXTEND_BIT_MASK;
3381 /* Is there a need for checking the size? Size should contain the number of
3384 value = read_memory_unsigned_integer (address, size, byte_order);
3386 /* Check if it's an extend, signed or zero instruction. */
3387 if (cris_get_opcode (*inst) < 4)
3389 value = do_sign_or_zero_extend (value, inst);
3394 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3395 instructions. The MOVE instruction is the move from source to register. */
3398 handle_prefix_assign_mode_for_aritm_op (unsigned short inst,
3399 inst_env_type *inst_env)
3401 unsigned long operand2;
3402 unsigned long operand3;
3404 check_assign (inst, inst_env);
3405 if (cris_get_operand2 (inst) == REG_PC)
3407 operand2 = inst_env->reg[REG_PC];
3409 /* Get the value of the third operand. */
3410 operand3 = get_data_from_address (&inst, inst_env->prefix_value,
3411 inst_env->byte_order);
3413 /* Calculate the PC value after the instruction, i.e. where the
3414 breakpoint should be. The order of the udw_operands is vital. */
3415 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3417 inst_env->slot_needed = 0;
3418 inst_env->prefix_found = 0;
3419 inst_env->xflag_found = 0;
3420 inst_env->disable_interrupt = 0;
3423 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3424 OR instructions. Note that for this to work as expected, the calling
3425 function must have made sure that there is a prefix to this instruction. */
3428 three_operand_add_sub_cmp_and_or_op (unsigned short inst,
3429 inst_env_type *inst_env)
3431 unsigned long operand2;
3432 unsigned long operand3;
3434 if (cris_get_operand1 (inst) == REG_PC)
3436 /* The PC will be changed by the instruction. */
3437 operand2 = inst_env->reg[cris_get_operand2 (inst)];
3439 /* Get the value of the third operand. */
3440 operand3 = get_data_from_address (&inst, inst_env->prefix_value,
3441 inst_env->byte_order);
3443 /* Calculate the PC value after the instruction, i.e. where the
3444 breakpoint should be. */
3445 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3447 inst_env->slot_needed = 0;
3448 inst_env->prefix_found = 0;
3449 inst_env->xflag_found = 0;
3450 inst_env->disable_interrupt = 0;
3453 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3454 instructions. The MOVE instruction is the move from source to register. */
3457 handle_prefix_index_mode_for_aritm_op (unsigned short inst,
3458 inst_env_type *inst_env)
3460 if (cris_get_operand1 (inst) != cris_get_operand2 (inst))
3462 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
3463 SUB, AND or OR something weird is going on (if everything works these
3464 instructions should end up in the three operand version). */
3465 inst_env->invalid = 1;
3470 /* three_operand_add_sub_cmp_and_or does the same as we should do here
3472 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3474 inst_env->slot_needed = 0;
3475 inst_env->prefix_found = 0;
3476 inst_env->xflag_found = 0;
3477 inst_env->disable_interrupt = 0;
3480 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3481 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
3482 source to register. */
3485 handle_inc_and_index_mode_for_aritm_op (unsigned short inst,
3486 inst_env_type *inst_env)
3488 unsigned long operand1;
3489 unsigned long operand2;
3490 unsigned long operand3;
3493 /* The instruction is either an indirect or autoincrement addressing mode.
3494 Check if the destination register is the PC. */
3495 if (cris_get_operand2 (inst) == REG_PC)
3497 /* Must be done here, get_data_from_address may change the size
3499 size = cris_get_size (inst);
3500 operand2 = inst_env->reg[REG_PC];
3502 /* Get the value of the third operand, i.e. the indirect operand. */
3503 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3504 operand3 = get_data_from_address (&inst, operand1, inst_env->byte_order);
3506 /* Calculate the PC value after the instruction, i.e. where the
3507 breakpoint should be. The order of the udw_operands is vital. */
3508 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3510 /* If this is an autoincrement addressing mode, check if the increment
3512 if ((cris_get_operand1 (inst) == REG_PC)
3513 && (cris_get_mode (inst) == AUTOINC_MODE))
3515 /* Get the size field. */
3516 size = cris_get_size (inst);
3518 /* If it's an extend instruction we don't want the signed extend bit,
3519 because it influences the size. */
3520 if (cris_get_opcode (inst) < 4)
3522 size &= ~SIGNED_EXTEND_BIT_MASK;
3524 process_autoincrement (size, inst, inst_env);
3526 inst_env->slot_needed = 0;
3527 inst_env->prefix_found = 0;
3528 inst_env->xflag_found = 0;
3529 inst_env->disable_interrupt = 0;
3532 /* Handles the two-operand addressing mode, all modes except register, for
3533 the ADD, SUB CMP, AND and OR instruction. */
3536 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3537 inst_env_type *inst_env)
3539 if (inst_env->prefix_found)
3541 if (cris_get_mode (inst) == PREFIX_INDEX_MODE)
3543 handle_prefix_index_mode_for_aritm_op (inst, inst_env);
3545 else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
3547 handle_prefix_assign_mode_for_aritm_op (inst, inst_env);
3551 /* The mode is invalid for a prefixed base instruction. */
3552 inst_env->invalid = 1;
3558 handle_inc_and_index_mode_for_aritm_op (inst, inst_env);
3562 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3565 quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env)
3567 unsigned long operand1;
3568 unsigned long operand2;
3570 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3571 instruction and can't have a prefix. */
3572 if (inst_env->prefix_found)
3574 inst_env->invalid = 1;
3578 /* Check if the instruction has PC as its target. */
3579 if (cris_get_operand2 (inst) == REG_PC)
3581 if (inst_env->slot_needed)
3583 inst_env->invalid = 1;
3586 operand1 = cris_get_quick_value (inst);
3587 operand2 = inst_env->reg[REG_PC];
3589 /* The size should now be dword. */
3590 cris_set_size_to_dword (&inst);
3592 /* Calculate the PC value after the instruction, i.e. where the
3593 breakpoint should be. */
3594 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3596 inst_env->slot_needed = 0;
3597 inst_env->prefix_found = 0;
3598 inst_env->xflag_found = 0;
3599 inst_env->disable_interrupt = 0;
3602 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3605 quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env)
3607 unsigned long operand1;
3608 unsigned long operand2;
3610 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3611 instruction and can't have a prefix. */
3612 if (inst_env->prefix_found)
3614 inst_env->invalid = 1;
3617 /* Check if the instruction has PC as its target. */
3618 if (cris_get_operand2 (inst) == REG_PC)
3620 if (inst_env->slot_needed)
3622 inst_env->invalid = 1;
3625 /* The instruction has the PC as its target register. */
3626 operand1 = cris_get_quick_value (inst);
3627 operand2 = inst_env->reg[REG_PC];
3629 /* The quick value is signed, so check if we must do a signed extend. */
3630 if (operand1 & SIGNED_QUICK_VALUE_MASK)
3633 operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK;
3635 /* The size should now be dword. */
3636 cris_set_size_to_dword (&inst);
3638 /* Calculate the PC value after the instruction, i.e. where the
3639 breakpoint should be. */
3640 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3642 inst_env->slot_needed = 0;
3643 inst_env->prefix_found = 0;
3644 inst_env->xflag_found = 0;
3645 inst_env->disable_interrupt = 0;
3648 /* Translate op_type to a function and call it. */
3651 cris_gdb_func (struct gdbarch *gdbarch, enum cris_op_type op_type,
3652 unsigned short inst, inst_env_type *inst_env)
3656 case cris_not_implemented_op:
3657 not_implemented_op (inst, inst_env);
3661 abs_op (inst, inst_env);
3665 addi_op (inst, inst_env);
3669 asr_op (inst, inst_env);
3673 asrq_op (inst, inst_env);
3676 case cris_ax_ei_setf_op:
3677 ax_ei_setf_op (inst, inst_env);
3680 case cris_bdap_prefix:
3681 bdap_prefix (inst, inst_env);
3684 case cris_biap_prefix:
3685 biap_prefix (inst, inst_env);
3689 break_op (inst, inst_env);
3692 case cris_btst_nop_op:
3693 btst_nop_op (inst, inst_env);
3696 case cris_clearf_di_op:
3697 clearf_di_op (inst, inst_env);
3700 case cris_dip_prefix:
3701 dip_prefix (inst, inst_env);
3704 case cris_dstep_logshift_mstep_neg_not_op:
3705 dstep_logshift_mstep_neg_not_op (inst, inst_env);
3708 case cris_eight_bit_offset_branch_op:
3709 eight_bit_offset_branch_op (inst, inst_env);
3712 case cris_move_mem_to_reg_movem_op:
3713 move_mem_to_reg_movem_op (inst, inst_env);
3716 case cris_move_reg_to_mem_movem_op:
3717 move_reg_to_mem_movem_op (inst, inst_env);
3720 case cris_move_to_preg_op:
3721 move_to_preg_op (gdbarch, inst, inst_env);
3725 muls_op (inst, inst_env);
3729 mulu_op (inst, inst_env);
3732 case cris_none_reg_mode_add_sub_cmp_and_or_move_op:
3733 none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3736 case cris_none_reg_mode_clear_test_op:
3737 none_reg_mode_clear_test_op (inst, inst_env);
3740 case cris_none_reg_mode_jump_op:
3741 none_reg_mode_jump_op (inst, inst_env);
3744 case cris_none_reg_mode_move_from_preg_op:
3745 none_reg_mode_move_from_preg_op (gdbarch, inst, inst_env);
3748 case cris_quick_mode_add_sub_op:
3749 quick_mode_add_sub_op (inst, inst_env);
3752 case cris_quick_mode_and_cmp_move_or_op:
3753 quick_mode_and_cmp_move_or_op (inst, inst_env);
3756 case cris_quick_mode_bdap_prefix:
3757 quick_mode_bdap_prefix (inst, inst_env);
3760 case cris_reg_mode_add_sub_cmp_and_or_move_op:
3761 reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3764 case cris_reg_mode_clear_op:
3765 reg_mode_clear_op (inst, inst_env);
3768 case cris_reg_mode_jump_op:
3769 reg_mode_jump_op (inst, inst_env);
3772 case cris_reg_mode_move_from_preg_op:
3773 reg_mode_move_from_preg_op (inst, inst_env);
3776 case cris_reg_mode_test_op:
3777 reg_mode_test_op (inst, inst_env);
3781 scc_op (inst, inst_env);
3784 case cris_sixteen_bit_offset_branch_op:
3785 sixteen_bit_offset_branch_op (inst, inst_env);
3788 case cris_three_operand_add_sub_cmp_and_or_op:
3789 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3792 case cris_three_operand_bound_op:
3793 three_operand_bound_op (inst, inst_env);
3796 case cris_two_operand_bound_op:
3797 two_operand_bound_op (inst, inst_env);
3801 xor_op (inst, inst_env);
3806 /* This wrapper is to avoid cris_get_assembler being called before
3807 exec_bfd has been set. */
3810 cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info)
3812 int (*print_insn) (bfd_vma addr, struct disassemble_info *info);
3813 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3814 disassembler, even when there is no BFD. Does something like
3815 "gdb; target remote; disassmeble *0x123" work? */
3816 gdb_assert (exec_bfd != NULL);
3817 print_insn = cris_get_disassembler (exec_bfd);
3818 gdb_assert (print_insn != NULL);
3819 return print_insn (addr, info);
3822 /* Copied from <asm/elf.h>. */
3823 typedef unsigned long elf_greg_t;
3825 /* Same as user_regs_struct struct in <asm/user.h>. */
3826 #define CRISV10_ELF_NGREG 35
3827 typedef elf_greg_t elf_gregset_t[CRISV10_ELF_NGREG];
3829 #define CRISV32_ELF_NGREG 32
3830 typedef elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG];
3832 /* Unpack an elf_gregset_t into GDB's register cache. */
3835 cris_supply_gregset (struct regcache *regcache, elf_gregset_t *gregsetp)
3837 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3838 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3840 elf_greg_t *regp = *gregsetp;
3841 static char zerobuf[4] = {0};
3843 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3844 knows about the actual size of each register so that's no problem. */
3845 for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++)
3847 regcache_raw_supply (regcache, i, (char *)®p[i]);
3850 if (tdep->cris_version == 32)
3852 /* Needed to set pseudo-register PC for CRISv32. */
3853 /* FIXME: If ERP is in a delay slot at this point then the PC will
3854 be wrong. Issue a warning to alert the user. */
3855 regcache_raw_supply (regcache, gdbarch_pc_regnum (gdbarch),
3856 (char *)®p[ERP_REGNUM]);
3858 if (*(char *)®p[ERP_REGNUM] & 0x1)
3859 fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n");
3863 /* Use a local version of this function to get the correct types for
3864 regsets, until multi-arch core support is ready. */
3867 fetch_core_registers (struct regcache *regcache,
3868 char *core_reg_sect, unsigned core_reg_size,
3869 int which, CORE_ADDR reg_addr)
3871 elf_gregset_t gregset;
3876 if (core_reg_size != sizeof (elf_gregset_t)
3877 && core_reg_size != sizeof (crisv32_elf_gregset_t))
3879 warning (_("wrong size gregset struct in core file"));
3883 memcpy (&gregset, core_reg_sect, sizeof (gregset));
3884 cris_supply_gregset (regcache, &gregset);
3888 /* We've covered all the kinds of registers we know about here,
3889 so this must be something we wouldn't know what to do with
3890 anyway. Just ignore it. */
3895 static struct core_fns cris_elf_core_fns =
3897 bfd_target_elf_flavour, /* core_flavour */
3898 default_check_format, /* check_format */
3899 default_core_sniffer, /* core_sniffer */
3900 fetch_core_registers, /* core_read_registers */
3904 extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */
3907 _initialize_cris_tdep (void)
3909 static struct cmd_list_element *cris_set_cmdlist;
3910 static struct cmd_list_element *cris_show_cmdlist;
3912 struct cmd_list_element *c;
3914 gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep);
3916 /* CRIS-specific user-commands. */
3917 add_setshow_uinteger_cmd ("cris-version", class_support,
3918 &usr_cmd_cris_version,
3919 _("Set the current CRIS version."),
3920 _("Show the current CRIS version."),
3922 Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\
3925 NULL, /* FIXME: i18n: Current CRIS version
3927 &setlist, &showlist);
3929 add_setshow_enum_cmd ("cris-mode", class_support,
3930 cris_modes, &usr_cmd_cris_mode,
3931 _("Set the current CRIS mode."),
3932 _("Show the current CRIS mode."),
3934 Set to CRIS_MODE_GURU when debugging in guru mode.\n\
3935 Makes GDB use the NRP register instead of the ERP register in certain cases."),
3937 NULL, /* FIXME: i18n: Current CRIS version is %s. */
3938 &setlist, &showlist);
3940 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support,
3941 &usr_cmd_cris_dwarf2_cfi,
3942 _("Set the usage of Dwarf-2 CFI for CRIS."),
3943 _("Show the usage of Dwarf-2 CFI for CRIS."),
3944 _("Set this to \"off\" if using gcc-cris < R59."),
3945 set_cris_dwarf2_cfi,
3946 NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI
3948 &setlist, &showlist);
3950 deprecated_add_core_fns (&cris_elf_core_fns);
3953 /* Prints out all target specific values. */
3956 cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3958 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3961 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n",
3962 tdep->cris_version);
3963 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n",
3965 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
3966 tdep->cris_dwarf2_cfi);
3971 set_cris_version (char *ignore_args, int from_tty,
3972 struct cmd_list_element *c)
3974 struct gdbarch_info info;
3976 usr_cmd_cris_version_valid = 1;
3978 /* Update the current architecture, if needed. */
3979 gdbarch_info_init (&info);
3980 if (!gdbarch_update_p (info))
3981 internal_error (__FILE__, __LINE__,
3982 _("cris_gdbarch_update: failed to update architecture."));
3986 set_cris_mode (char *ignore_args, int from_tty,
3987 struct cmd_list_element *c)
3989 struct gdbarch_info info;
3991 /* Update the current architecture, if needed. */
3992 gdbarch_info_init (&info);
3993 if (!gdbarch_update_p (info))
3994 internal_error (__FILE__, __LINE__,
3995 "cris_gdbarch_update: failed to update architecture.");
3999 set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
4000 struct cmd_list_element *c)
4002 struct gdbarch_info info;
4004 /* Update the current architecture, if needed. */
4005 gdbarch_info_init (&info);
4006 if (!gdbarch_update_p (info))
4007 internal_error (__FILE__, __LINE__,
4008 _("cris_gdbarch_update: failed to update architecture."));
4011 static struct gdbarch *
4012 cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
4014 struct gdbarch *gdbarch;
4015 struct gdbarch_tdep *tdep;
4018 if (usr_cmd_cris_version_valid)
4020 /* Trust the user's CRIS version setting. */
4021 cris_version = usr_cmd_cris_version;
4023 else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32)
4029 /* Assume it's CRIS version 10. */
4033 /* Make the current settings visible to the user. */
4034 usr_cmd_cris_version = cris_version;
4036 /* Find a candidate among the list of pre-declared architectures. */
4037 for (arches = gdbarch_list_lookup_by_info (arches, &info);
4039 arches = gdbarch_list_lookup_by_info (arches->next, &info))
4041 if ((gdbarch_tdep (arches->gdbarch)->cris_version
4042 == usr_cmd_cris_version)
4043 && (gdbarch_tdep (arches->gdbarch)->cris_mode
4044 == usr_cmd_cris_mode)
4045 && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi
4046 == usr_cmd_cris_dwarf2_cfi))
4047 return arches->gdbarch;
4050 /* No matching architecture was found. Create a new one. */
4051 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
4052 gdbarch = gdbarch_alloc (&info, tdep);
4054 tdep->cris_version = usr_cmd_cris_version;
4055 tdep->cris_mode = usr_cmd_cris_mode;
4056 tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi;
4058 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
4059 switch (info.byte_order)
4061 case BFD_ENDIAN_LITTLE:
4065 case BFD_ENDIAN_BIG:
4066 internal_error (__FILE__, __LINE__,
4067 _("cris_gdbarch_init: big endian byte order in info"));
4071 internal_error (__FILE__, __LINE__,
4072 _("cris_gdbarch_init: unknown byte order in info"));
4075 set_gdbarch_return_value (gdbarch, cris_return_value);
4077 set_gdbarch_sp_regnum (gdbarch, 14);
4079 /* Length of ordinary registers used in push_word and a few other
4080 places. register_size() is the real way to know how big a
4083 set_gdbarch_double_bit (gdbarch, 64);
4084 /* The default definition of a long double is 2 * gdbarch_double_bit,
4085 which means we have to set this explicitly. */
4086 set_gdbarch_long_double_bit (gdbarch, 64);
4088 /* The total amount of space needed to store (in an array called registers)
4089 GDB's copy of the machine's register state. Note: We can not use
4090 cris_register_size at this point, since it relies on gdbarch
4092 switch (tdep->cris_version)
4100 /* Old versions; not supported. */
4101 internal_error (__FILE__, __LINE__,
4102 _("cris_gdbarch_init: unsupported CRIS version"));
4107 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
4108 P7 (32 bits), and P15 (32 bits) have been implemented. */
4109 set_gdbarch_pc_regnum (gdbarch, 15);
4110 set_gdbarch_register_type (gdbarch, cris_register_type);
4111 /* There are 32 registers (some of which may not be implemented). */
4112 set_gdbarch_num_regs (gdbarch, 32);
4113 set_gdbarch_register_name (gdbarch, cris_register_name);
4114 set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register);
4115 set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register);
4117 set_gdbarch_software_single_step (gdbarch, cris_software_single_step);
4121 /* CRIS v32. General registers R0 - R15 (32 bits), special registers
4122 P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
4123 and pseudo-register PC (32 bits). */
4124 set_gdbarch_pc_regnum (gdbarch, 32);
4125 set_gdbarch_register_type (gdbarch, crisv32_register_type);
4126 /* 32 registers + pseudo-register PC + 16 support registers. */
4127 set_gdbarch_num_regs (gdbarch, 32 + 1 + 16);
4128 set_gdbarch_register_name (gdbarch, crisv32_register_name);
4130 set_gdbarch_cannot_store_register
4131 (gdbarch, crisv32_cannot_store_register);
4132 set_gdbarch_cannot_fetch_register
4133 (gdbarch, crisv32_cannot_fetch_register);
4135 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
4137 set_gdbarch_single_step_through_delay
4138 (gdbarch, crisv32_single_step_through_delay);
4143 internal_error (__FILE__, __LINE__,
4144 _("cris_gdbarch_init: unknown CRIS version"));
4147 /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
4148 have the same ABI). */
4149 set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code);
4150 set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call);
4151 set_gdbarch_frame_align (gdbarch, cris_frame_align);
4152 set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue);
4154 /* The stack grows downward. */
4155 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4157 set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc);
4159 set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc);
4160 set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp);
4161 set_gdbarch_dummy_id (gdbarch, cris_dummy_id);
4163 if (tdep->cris_dwarf2_cfi == 1)
4165 /* Hook in the Dwarf-2 frame sniffer. */
4166 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum);
4167 dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg);
4168 dwarf2_append_unwinders (gdbarch);
4171 if (tdep->cris_mode != cris_mode_guru)
4173 frame_unwind_append_unwinder (gdbarch, &cris_sigtramp_frame_unwind);
4176 frame_unwind_append_unwinder (gdbarch, &cris_frame_unwind);
4177 frame_base_set_default (gdbarch, &cris_frame_base);
4179 set_solib_svr4_fetch_link_map_offsets
4180 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
4182 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
4183 disassembler, even when there is no BFD. Does something like
4184 "gdb; target remote; disassmeble *0x123" work? */
4185 set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler);