1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 Contributed by Axis Communications AB.
7 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "frame-unwind.h"
27 #include "frame-base.h"
28 #include "trad-frame.h"
29 #include "dwarf2-frame.h"
37 #include "opcode/cris.h"
38 #include "arch-utils.h"
40 #include "gdb_assert.h"
42 /* To get entry_point_address. */
45 #include "solib.h" /* Support for shared libraries. */
46 #include "solib-svr4.h"
47 #include "gdb_string.h"
52 /* There are no floating point registers. Used in gdbserver low-linux.c. */
55 /* There are 16 general registers. */
58 /* There are 16 special registers. */
61 /* CRISv32 has a pseudo PC register, not noted here. */
63 /* CRISv32 has 16 support registers. */
67 /* Register numbers of various important registers.
68 CRIS_FP_REGNUM Contains address of executing stack frame.
69 STR_REGNUM Contains the address of structure return values.
70 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
71 ARG1_REGNUM Contains the first parameter to a function.
72 ARG2_REGNUM Contains the second parameter to a function.
73 ARG3_REGNUM Contains the third parameter to a function.
74 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
75 gdbarch_sp_regnum Contains address of top of stack.
76 gdbarch_pc_regnum Contains address of next instruction.
77 SRP_REGNUM Subroutine return pointer register.
78 BRP_REGNUM Breakpoint return pointer register. */
82 /* Enums with respect to the general registers, valid for all
83 CRIS versions. The frame pointer is always in R8. */
85 /* ABI related registers. */
93 /* Registers which happen to be common. */
98 /* CRISv10 et. al. specific registers. */
110 /* CRISv32 specific registers. */
123 CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */
125 CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */
145 extern const struct cris_spec_reg cris_spec_regs[];
147 /* CRIS version, set via the user command 'set cris-version'. Affects
148 register names and sizes. */
149 static int usr_cmd_cris_version;
151 /* Indicates whether to trust the above variable. */
152 static int usr_cmd_cris_version_valid = 0;
154 static const char cris_mode_normal[] = "normal";
155 static const char cris_mode_guru[] = "guru";
156 static const char *cris_modes[] = {
162 /* CRIS mode, set via the user command 'set cris-mode'. Affects
163 type of break instruction among other things. */
164 static const char *usr_cmd_cris_mode = cris_mode_normal;
166 /* Whether to make use of Dwarf-2 CFI (default on). */
167 static int usr_cmd_cris_dwarf2_cfi = 1;
169 /* CRIS architecture specific information. */
173 const char *cris_mode;
177 /* Functions for accessing target dependent data. */
182 return (gdbarch_tdep (current_gdbarch)->cris_version);
188 return (gdbarch_tdep (current_gdbarch)->cris_mode);
191 /* Sigtramp identification code copied from i386-linux-tdep.c. */
193 #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
194 #define SIGTRAMP_OFFSET0 0
195 #define SIGTRAMP_INSN1 0xe93d /* break 13 */
196 #define SIGTRAMP_OFFSET1 4
198 static const unsigned short sigtramp_code[] =
200 SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */
201 SIGTRAMP_INSN1 /* break 13 */
204 #define SIGTRAMP_LEN (sizeof sigtramp_code)
206 /* Note: same length as normal sigtramp code. */
208 static const unsigned short rt_sigtramp_code[] =
210 SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */
211 SIGTRAMP_INSN1 /* break 13 */
214 /* If PC is in a sigtramp routine, return the address of the start of
215 the routine. Otherwise, return 0. */
218 cris_sigtramp_start (struct frame_info *next_frame)
220 CORE_ADDR pc = frame_pc_unwind (next_frame);
221 gdb_byte buf[SIGTRAMP_LEN];
223 if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN))
226 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
228 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
231 pc -= SIGTRAMP_OFFSET1;
232 if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN))
236 if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0)
242 /* If PC is in a RT sigtramp routine, return the address of the start of
243 the routine. Otherwise, return 0. */
246 cris_rt_sigtramp_start (struct frame_info *next_frame)
248 CORE_ADDR pc = frame_pc_unwind (next_frame);
249 gdb_byte buf[SIGTRAMP_LEN];
251 if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN))
254 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
256 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
259 pc -= SIGTRAMP_OFFSET1;
260 if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN))
264 if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0)
270 /* Assuming NEXT_FRAME is a frame following a GNU/Linux sigtramp
271 routine, return the address of the associated sigcontext structure. */
274 cris_sigcontext_addr (struct frame_info *next_frame)
280 frame_unwind_register (next_frame,
281 gdbarch_sp_regnum (get_frame_arch (next_frame)), buf);
282 sp = extract_unsigned_integer (buf, 4);
284 /* Look for normal sigtramp frame first. */
285 pc = cris_sigtramp_start (next_frame);
288 /* struct signal_frame (arch/cris/kernel/signal.c) contains
289 struct sigcontext as its first member, meaning the SP points to
294 pc = cris_rt_sigtramp_start (next_frame);
297 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
298 a struct ucontext, which in turn contains a struct sigcontext.
300 4 + 4 + 128 to struct ucontext, then
301 4 + 4 + 12 to struct sigcontext. */
305 error (_("Couldn't recognize signal trampoline."));
309 struct cris_unwind_cache
311 /* The previous frame's inner most stack address. Used as this
312 frame ID's stack_addr. */
314 /* The frame's base, optionally used by the high-level debug info. */
317 /* How far the SP and r8 (FP) have been offset from the start of
318 the stack frame (as defined by the previous frame's stack
324 /* From old frame_extra_info struct. */
328 /* Table indicating the location of each and every register. */
329 struct trad_frame_saved_reg *saved_regs;
332 static struct cris_unwind_cache *
333 cris_sigtramp_frame_unwind_cache (struct frame_info *next_frame,
336 struct gdbarch *gdbarch = get_frame_arch (next_frame);
337 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
338 struct cris_unwind_cache *info;
346 return (*this_cache);
348 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
349 (*this_cache) = info;
350 info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
352 /* Zero all fields. */
358 info->uses_frame = 0;
360 info->leaf_function = 0;
362 frame_unwind_register (next_frame, gdbarch_sp_regnum (gdbarch), buf);
363 info->base = extract_unsigned_integer (buf, 4);
365 addr = cris_sigcontext_addr (next_frame);
367 /* Layout of the sigcontext struct:
370 unsigned long oldmask;
374 if (tdep->cris_version == 10)
376 /* R0 to R13 are stored in reverse order at offset (2 * 4) in
378 for (i = 0; i <= 13; i++)
379 info->saved_regs[i].addr = addr + ((15 - i) * 4);
381 info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4);
382 info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4);
383 info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4);
384 /* Note: IRP is off by 2 at this point. There's no point in correcting
385 it though since that will mean that the backtrace will show a PC
386 different from what is shown when stopped. */
387 info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4);
388 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
389 = info->saved_regs[IRP_REGNUM];
390 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr = addr + (24 * 4);
395 /* R0 to R13 are stored in order at offset (1 * 4) in
397 for (i = 0; i <= 13; i++)
398 info->saved_regs[i].addr = addr + ((i + 1) * 4);
400 info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4);
401 info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4);
402 info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4);
403 info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4);
404 info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4);
405 info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4);
406 info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4);
407 info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4);
408 info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4);
410 /* FIXME: If ERP is in a delay slot at this point then the PC will
411 be wrong at this point. This problem manifests itself in the
412 sigaltstack.exp test case, which occasionally generates FAILs when
413 the signal is received while in a delay slot.
415 This could be solved by a couple of read_memory_unsigned_integer and a
416 trad_frame_set_value. */
417 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
418 = info->saved_regs[ERP_REGNUM];
420 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr
428 cris_sigtramp_frame_this_id (struct frame_info *next_frame, void **this_cache,
429 struct frame_id *this_id)
431 struct cris_unwind_cache *cache =
432 cris_sigtramp_frame_unwind_cache (next_frame, this_cache);
433 (*this_id) = frame_id_build (cache->base, frame_pc_unwind (next_frame));
436 /* Forward declaration. */
438 static void cris_frame_prev_register (struct frame_info *next_frame,
439 void **this_prologue_cache,
440 int regnum, int *optimizedp,
441 enum lval_type *lvalp, CORE_ADDR *addrp,
442 int *realnump, gdb_byte *bufferp);
444 cris_sigtramp_frame_prev_register (struct frame_info *next_frame,
446 int regnum, int *optimizedp,
447 enum lval_type *lvalp, CORE_ADDR *addrp,
448 int *realnump, gdb_byte *valuep)
450 /* Make sure we've initialized the cache. */
451 cris_sigtramp_frame_unwind_cache (next_frame, this_cache);
452 cris_frame_prev_register (next_frame, this_cache, regnum,
453 optimizedp, lvalp, addrp, realnump, valuep);
456 static const struct frame_unwind cris_sigtramp_frame_unwind =
459 cris_sigtramp_frame_this_id,
460 cris_sigtramp_frame_prev_register
463 static const struct frame_unwind *
464 cris_sigtramp_frame_sniffer (struct frame_info *next_frame)
466 if (cris_sigtramp_start (next_frame)
467 || cris_rt_sigtramp_start (next_frame))
468 return &cris_sigtramp_frame_unwind;
474 crisv32_single_step_through_delay (struct gdbarch *gdbarch,
475 struct frame_info *this_frame)
477 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
482 if (cris_mode () == cris_mode_guru)
484 frame_unwind_register (this_frame, NRP_REGNUM, buf);
488 frame_unwind_register (this_frame, ERP_REGNUM, buf);
491 erp = extract_unsigned_integer (buf, 4);
495 /* In delay slot - check if there's a breakpoint at the preceding
497 if (breakpoint_here_p (erp & ~0x1))
503 /* Hardware watchpoint support. */
505 /* We support 6 hardware data watchpoints, but cannot trigger on execute
506 (any combination of read/write is fine). */
509 cris_can_use_hardware_watchpoint (int type, int count, int other)
511 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
513 /* No bookkeeping is done here; it is handled by the remote debug agent. */
515 if (tdep->cris_version != 32)
518 /* CRISv32: Six data watchpoints, one for instructions. */
519 return (((type == bp_read_watchpoint || type == bp_access_watchpoint
520 || type == bp_hardware_watchpoint) && count <= 6)
521 || (type == bp_hardware_breakpoint && count <= 1));
524 /* The CRISv32 hardware data watchpoints work by specifying ranges,
525 which have no alignment or length restrictions. */
528 cris_region_ok_for_watchpoint (CORE_ADDR addr, int len)
533 /* If the inferior has some watchpoint that triggered, return the
534 address associated with that watchpoint. Otherwise, return
538 cris_stopped_data_address (void)
541 eda = get_frame_register_unsigned (get_current_frame (), EDA_REGNUM);
545 /* The instruction environment needed to find single-step breakpoints. */
548 struct instruction_environment
550 unsigned long reg[NUM_GENREGS];
551 unsigned long preg[NUM_SPECREGS];
552 unsigned long branch_break_address;
553 unsigned long delay_slot_pc;
554 unsigned long prefix_value;
559 int delay_slot_pc_active;
561 int disable_interrupt;
564 /* Machine-dependencies in CRIS for opcodes. */
566 /* Instruction sizes. */
567 enum cris_instruction_sizes
574 /* Addressing modes. */
575 enum cris_addressing_modes
582 /* Prefix addressing modes. */
583 enum cris_prefix_addressing_modes
585 PREFIX_INDEX_MODE = 2,
586 PREFIX_ASSIGN_MODE = 3,
588 /* Handle immediate byte offset addressing mode prefix format. */
589 PREFIX_OFFSET_MODE = 2
592 /* Masks for opcodes. */
593 enum cris_opcode_masks
595 BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1,
596 SIGNED_EXTEND_BIT_MASK = 0x2,
597 SIGNED_BYTE_MASK = 0x80,
598 SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00,
599 SIGNED_WORD_MASK = 0x8000,
600 SIGNED_WORD_EXTEND_MASK = 0xFFFF0000,
601 SIGNED_DWORD_MASK = 0x80000000,
602 SIGNED_QUICK_VALUE_MASK = 0x20,
603 SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0
606 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
614 cris_get_operand2 (unsigned short insn)
616 return ((insn & 0xF000) >> 12);
620 cris_get_mode (unsigned short insn)
622 return ((insn & 0x0C00) >> 10);
626 cris_get_opcode (unsigned short insn)
628 return ((insn & 0x03C0) >> 6);
632 cris_get_size (unsigned short insn)
634 return ((insn & 0x0030) >> 4);
638 cris_get_operand1 (unsigned short insn)
640 return (insn & 0x000F);
643 /* Additional functions in order to handle opcodes. */
646 cris_get_quick_value (unsigned short insn)
648 return (insn & 0x003F);
652 cris_get_bdap_quick_offset (unsigned short insn)
654 return (insn & 0x00FF);
658 cris_get_branch_short_offset (unsigned short insn)
660 return (insn & 0x00FF);
664 cris_get_asr_shift_steps (unsigned long value)
666 return (value & 0x3F);
670 cris_get_clear_size (unsigned short insn)
672 return ((insn) & 0xC000);
676 cris_is_signed_extend_bit_on (unsigned short insn)
678 return (((insn) & 0x20) == 0x20);
682 cris_is_xflag_bit_on (unsigned short insn)
684 return (((insn) & 0x1000) == 0x1000);
688 cris_set_size_to_dword (unsigned short *insn)
695 cris_get_signed_offset (unsigned short insn)
697 return ((signed char) (insn & 0x00FF));
700 /* Calls an op function given the op-type, working on the insn and the
702 static void cris_gdb_func (enum cris_op_type, unsigned short, inst_env_type *);
704 static struct gdbarch *cris_gdbarch_init (struct gdbarch_info,
705 struct gdbarch_list *);
707 static void cris_dump_tdep (struct gdbarch *, struct ui_file *);
709 static void set_cris_version (char *ignore_args, int from_tty,
710 struct cmd_list_element *c);
712 static void set_cris_mode (char *ignore_args, int from_tty,
713 struct cmd_list_element *c);
715 static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
716 struct cmd_list_element *c);
718 static CORE_ADDR cris_scan_prologue (CORE_ADDR pc,
719 struct frame_info *next_frame,
720 struct cris_unwind_cache *info);
722 static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc,
723 struct frame_info *next_frame,
724 struct cris_unwind_cache *info);
726 static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch,
727 struct frame_info *next_frame);
729 static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch,
730 struct frame_info *next_frame);
732 /* When arguments must be pushed onto the stack, they go on in reverse
733 order. The below implements a FILO (stack) to do this.
734 Copied from d10v-tdep.c. */
739 struct stack_item *prev;
743 static struct stack_item *
744 push_stack_item (struct stack_item *prev, void *contents, int len)
746 struct stack_item *si;
747 si = xmalloc (sizeof (struct stack_item));
748 si->data = xmalloc (len);
751 memcpy (si->data, contents, len);
755 static struct stack_item *
756 pop_stack_item (struct stack_item *si)
758 struct stack_item *dead = si;
765 /* Put here the code to store, into fi->saved_regs, the addresses of
766 the saved registers of frame described by FRAME_INFO. This
767 includes special registers such as pc and fp saved in special ways
768 in the stack frame. sp is even more special: the address we return
769 for it IS the sp for the next frame. */
771 struct cris_unwind_cache *
772 cris_frame_unwind_cache (struct frame_info *next_frame,
773 void **this_prologue_cache)
776 struct cris_unwind_cache *info;
779 if ((*this_prologue_cache))
780 return (*this_prologue_cache);
782 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
783 (*this_prologue_cache) = info;
784 info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
786 /* Zero all fields. */
792 info->uses_frame = 0;
794 info->leaf_function = 0;
796 /* Prologue analysis does the rest... */
797 if (cris_version () == 32)
798 crisv32_scan_prologue (frame_func_unwind (next_frame, NORMAL_FRAME),
801 cris_scan_prologue (frame_func_unwind (next_frame, NORMAL_FRAME),
807 /* Given a GDB frame, determine the address of the calling function's
808 frame. This will be used to create a new GDB frame struct. */
811 cris_frame_this_id (struct frame_info *next_frame,
812 void **this_prologue_cache,
813 struct frame_id *this_id)
815 struct cris_unwind_cache *info
816 = cris_frame_unwind_cache (next_frame, this_prologue_cache);
821 /* The FUNC is easy. */
822 func = frame_func_unwind (next_frame, NORMAL_FRAME);
824 /* Hopefully the prologue analysis either correctly determined the
825 frame's base (which is the SP from the previous frame), or set
826 that base to "NULL". */
827 base = info->prev_sp;
831 id = frame_id_build (base, func);
837 cris_frame_prev_register (struct frame_info *next_frame,
838 void **this_prologue_cache,
839 int regnum, int *optimizedp,
840 enum lval_type *lvalp, CORE_ADDR *addrp,
841 int *realnump, gdb_byte *bufferp)
843 struct cris_unwind_cache *info
844 = cris_frame_unwind_cache (next_frame, this_prologue_cache);
845 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
846 optimizedp, lvalp, addrp, realnump, bufferp);
849 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
850 dummy frame. The frame ID's base needs to match the TOS value
851 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
854 static struct frame_id
855 cris_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
857 return frame_id_build (cris_unwind_sp (gdbarch, next_frame),
858 frame_pc_unwind (next_frame));
862 cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
864 /* Align to the size of an instruction (so that they can safely be
865 pushed onto the stack). */
870 cris_push_dummy_code (struct gdbarch *gdbarch,
871 CORE_ADDR sp, CORE_ADDR funaddr,
872 struct value **args, int nargs,
873 struct type *value_type,
874 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
875 struct regcache *regcache)
877 /* Allocate space sufficient for a breakpoint. */
879 /* Store the address of that breakpoint */
881 /* CRIS always starts the call at the callee's entry point. */
887 cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
888 struct regcache *regcache, CORE_ADDR bp_addr,
889 int nargs, struct value **args, CORE_ADDR sp,
890 int struct_return, CORE_ADDR struct_addr)
899 /* The function's arguments and memory allocated by gdb for the arguments to
900 point at reside in separate areas on the stack.
901 Both frame pointers grow toward higher addresses. */
905 struct stack_item *si = NULL;
907 /* Push the return address. */
908 regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr);
910 /* Are we returning a value using a structure return or a normal value
911 return? struct_addr is the address of the reserved space for the return
912 structure to be written on the stack. */
915 regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr);
918 /* Now load as many as possible of the first arguments into registers,
919 and push the rest onto the stack. */
920 argreg = ARG1_REGNUM;
923 for (argnum = 0; argnum < nargs; argnum++)
930 len = TYPE_LENGTH (value_type (args[argnum]));
931 val = (char *) value_contents (args[argnum]);
933 /* How may registers worth of storage do we need for this argument? */
934 reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0);
936 if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM))
938 /* Data passed by value. Fits in available register(s). */
939 for (i = 0; i < reg_demand; i++)
941 regcache_cooked_write (regcache, argreg, val);
946 else if (len <= (2 * 4) && argreg <= ARG4_REGNUM)
948 /* Data passed by value. Does not fit in available register(s).
949 Use the register(s) first, then the stack. */
950 for (i = 0; i < reg_demand; i++)
952 if (argreg <= ARG4_REGNUM)
954 regcache_cooked_write (regcache, argreg, val);
960 /* Push item for later so that pushed arguments
961 come in the right order. */
962 si = push_stack_item (si, val, 4);
967 else if (len > (2 * 4))
969 /* Data passed by reference. Push copy of data onto stack
970 and pass pointer to this copy as argument. */
971 sp = (sp - len) & ~3;
972 write_memory (sp, val, len);
974 if (argreg <= ARG4_REGNUM)
976 regcache_cooked_write_unsigned (regcache, argreg, sp);
982 store_unsigned_integer (buf, 4, sp);
983 si = push_stack_item (si, buf, 4);
988 /* Data passed by value. No available registers. Put it on
990 si = push_stack_item (si, val, len);
996 /* fp_arg must be word-aligned (i.e., don't += len) to match
997 the function prologue. */
998 sp = (sp - si->len) & ~3;
999 write_memory (sp, si->data, si->len);
1000 si = pop_stack_item (si);
1003 /* Finally, update the SP register. */
1004 regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp);
1009 static const struct frame_unwind cris_frame_unwind =
1013 cris_frame_prev_register
1016 const struct frame_unwind *
1017 cris_frame_sniffer (struct frame_info *next_frame)
1019 return &cris_frame_unwind;
1023 cris_frame_base_address (struct frame_info *next_frame, void **this_cache)
1025 struct cris_unwind_cache *info
1026 = cris_frame_unwind_cache (next_frame, this_cache);
1030 static const struct frame_base cris_frame_base =
1033 cris_frame_base_address,
1034 cris_frame_base_address,
1035 cris_frame_base_address
1038 /* Frames information. The definition of the struct frame_info is
1042 enum frame_type type;
1046 If the compilation option -fno-omit-frame-pointer is present the
1047 variable frame will be set to the content of R8 which is the frame
1050 The variable pc contains the address where execution is performed
1051 in the present frame. The innermost frame contains the current content
1052 of the register PC. All other frames contain the content of the
1053 register PC in the next frame.
1055 The variable `type' indicates the frame's type: normal, SIGTRAMP
1056 (associated with a signal handler), dummy (associated with a dummy
1059 The variable return_pc contains the address where execution should be
1060 resumed when the present frame has finished, the return address.
1062 The variable leaf_function is 1 if the return address is in the register
1063 SRP, and 0 if it is on the stack.
1065 Prologue instructions C-code.
1066 The prologue may consist of (-fno-omit-frame-pointer)
1070 move.d sp,r8 move.d sp,r8
1072 movem rY,[sp] movem rY,[sp]
1073 move.S rZ,[r8-U] move.S rZ,[r8-U]
1075 where 1 is a non-terminal function, and 2 is a leaf-function.
1077 Note that this assumption is extremely brittle, and will break at the
1078 slightest change in GCC's prologue.
1080 If local variables are declared or register contents are saved on stack
1081 the subq-instruction will be present with X as the number of bytes
1082 needed for storage. The reshuffle with respect to r8 may be performed
1083 with any size S (b, w, d) and any of the general registers Z={0..13}.
1084 The offset U should be representable by a signed 8-bit value in all cases.
1085 Thus, the prefix word is assumed to be immediate byte offset mode followed
1086 by another word containing the instruction.
1095 Prologue instructions C++-code.
1096 Case 1) and 2) in the C-code may be followed by
1098 move.d r10,rS ; this
1102 move.S [r8+U],rZ ; P4
1104 if any of the call parameters are stored. The host expects these
1105 instructions to be executed in order to get the call parameters right. */
1107 /* Examine the prologue of a function. The variable ip is the address of
1108 the first instruction of the prologue. The variable limit is the address
1109 of the first instruction after the prologue. The variable fi contains the
1110 information in struct frame_info. The variable frameless_p controls whether
1111 the entire prologue is examined (0) or just enough instructions to
1112 determine that it is a prologue (1). */
1115 cris_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame,
1116 struct cris_unwind_cache *info)
1118 struct gdbarch *gdbarch = get_frame_arch (next_frame);
1119 /* Present instruction. */
1120 unsigned short insn;
1122 /* Next instruction, lookahead. */
1123 unsigned short insn_next;
1126 /* Is there a push fp? */
1129 /* Number of byte on stack used for local variables and movem. */
1132 /* Highest register number in a movem. */
1135 /* move.d r<source_register>,rS */
1136 short source_register;
1141 /* This frame is with respect to a leaf until a push srp is found. */
1144 info->leaf_function = 1;
1147 /* Assume nothing on stack. */
1151 /* If we were called without a next_frame, that means we were called
1152 from cris_skip_prologue which already tried to find the end of the
1153 prologue through the symbol information. 64 instructions past current
1154 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
1155 limit = next_frame ? frame_pc_unwind (next_frame) : pc + 64;
1157 /* Find the prologue instructions. */
1158 while (pc > 0 && pc < limit)
1160 insn = read_memory_unsigned_integer (pc, 2);
1164 /* push <reg> 32 bit instruction */
1165 insn_next = read_memory_unsigned_integer (pc, 2);
1167 regno = cris_get_operand2 (insn_next);
1170 info->sp_offset += 4;
1172 /* This check, meant to recognize srp, used to be regno ==
1173 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
1174 if (insn_next == 0xBE7E)
1178 info->leaf_function = 0;
1181 else if (insn_next == 0x8FEE)
1186 info->r8_offset = info->sp_offset;
1190 else if (insn == 0x866E)
1195 info->uses_frame = 1;
1199 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1200 && cris_get_mode (insn) == 0x0000
1201 && cris_get_opcode (insn) == 0x000A)
1206 info->sp_offset += cris_get_quick_value (insn);
1209 else if (cris_get_mode (insn) == 0x0002
1210 && cris_get_opcode (insn) == 0x000F
1211 && cris_get_size (insn) == 0x0003
1212 && cris_get_operand1 (insn) == gdbarch_sp_regnum (gdbarch))
1214 /* movem r<regsave>,[sp] */
1215 regsave = cris_get_operand2 (insn);
1217 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1218 && ((insn & 0x0F00) >> 8) == 0x0001
1219 && (cris_get_signed_offset (insn) < 0))
1221 /* Immediate byte offset addressing prefix word with sp as base
1222 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1223 is between 64 and 128.
1224 movem r<regsave>,[sp=sp-<val>] */
1227 info->sp_offset += -cris_get_signed_offset (insn);
1229 insn_next = read_memory_unsigned_integer (pc, 2);
1231 if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE
1232 && cris_get_opcode (insn_next) == 0x000F
1233 && cris_get_size (insn_next) == 0x0003
1234 && cris_get_operand1 (insn_next) == gdbarch_sp_regnum
1237 regsave = cris_get_operand2 (insn_next);
1241 /* The prologue ended before the limit was reached. */
1246 else if (cris_get_mode (insn) == 0x0001
1247 && cris_get_opcode (insn) == 0x0009
1248 && cris_get_size (insn) == 0x0002)
1250 /* move.d r<10..13>,r<0..15> */
1251 source_register = cris_get_operand1 (insn);
1253 /* FIXME? In the glibc solibs, the prologue might contain something
1254 like (this example taken from relocate_doit):
1256 sub.d 0xfffef426,$r0
1257 which isn't covered by the source_register check below. Question
1258 is whether to add a check for this combo, or make better use of
1259 the limit variable instead. */
1260 if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM)
1262 /* The prologue ended before the limit was reached. */
1267 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1268 /* The size is a fixed-size. */
1269 && ((insn & 0x0F00) >> 8) == 0x0001
1270 /* A negative offset. */
1271 && (cris_get_signed_offset (insn) < 0))
1273 /* move.S rZ,[r8-U] (?) */
1274 insn_next = read_memory_unsigned_integer (pc, 2);
1276 regno = cris_get_operand2 (insn_next);
1277 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1278 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1279 && cris_get_opcode (insn_next) == 0x000F)
1281 /* move.S rZ,[r8-U] */
1286 /* The prologue ended before the limit was reached. */
1291 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1292 /* The size is a fixed-size. */
1293 && ((insn & 0x0F00) >> 8) == 0x0001
1294 /* A positive offset. */
1295 && (cris_get_signed_offset (insn) > 0))
1297 /* move.S [r8+U],rZ (?) */
1298 insn_next = read_memory_unsigned_integer (pc, 2);
1300 regno = cris_get_operand2 (insn_next);
1301 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1302 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1303 && cris_get_opcode (insn_next) == 0x0009
1304 && cris_get_operand1 (insn_next) == regno)
1306 /* move.S [r8+U],rZ */
1311 /* The prologue ended before the limit was reached. */
1318 /* The prologue ended before the limit was reached. */
1324 /* We only want to know the end of the prologue when next_frame and info
1325 are NULL (called from cris_skip_prologue i.e.). */
1326 if (next_frame == NULL && info == NULL)
1331 info->size = info->sp_offset;
1333 /* Compute the previous frame's stack pointer (which is also the
1334 frame's ID's stack address), and this frame's base pointer. */
1335 if (info->uses_frame)
1338 /* The SP was moved to the FP. This indicates that a new frame
1339 was created. Get THIS frame's FP value by unwinding it from
1341 frame_unwind_unsigned_register (next_frame, CRIS_FP_REGNUM,
1343 info->base = this_base;
1344 info->saved_regs[CRIS_FP_REGNUM].addr = info->base;
1346 /* The FP points at the last saved register. Adjust the FP back
1347 to before the first saved register giving the SP. */
1348 info->prev_sp = info->base + info->r8_offset;
1353 /* Assume that the FP is this frame's SP but with that pushed
1354 stack space added back. */
1355 frame_unwind_unsigned_register (next_frame, gdbarch_sp_regnum (gdbarch),
1357 info->base = this_base;
1358 info->prev_sp = info->base + info->size;
1361 /* Calculate the addresses for the saved registers on the stack. */
1362 /* FIXME: The address calculation should really be done on the fly while
1363 we're analyzing the prologue (we only hold one regsave value as it is
1365 val = info->sp_offset;
1367 for (regno = regsave; regno >= 0; regno--)
1369 info->saved_regs[regno].addr = info->base + info->r8_offset - val;
1373 /* The previous frame's SP needed to be computed. Save the computed
1375 trad_frame_set_value (info->saved_regs,
1376 gdbarch_sp_regnum (gdbarch), info->prev_sp);
1378 if (!info->leaf_function)
1380 /* SRP saved on the stack. But where? */
1381 if (info->r8_offset == 0)
1383 /* R8 not pushed yet. */
1384 info->saved_regs[SRP_REGNUM].addr = info->base;
1388 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1389 info->saved_regs[SRP_REGNUM].addr = info->base + 4;
1393 /* The PC is found in SRP (the actual register or located on the stack). */
1394 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1395 = info->saved_regs[SRP_REGNUM];
1401 crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame,
1402 struct cris_unwind_cache *info)
1404 struct gdbarch *gdbarch = get_frame_arch (next_frame);
1407 /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not
1408 meant to be a full-fledged prologue scanner. It is only needed for
1409 the cases where we end up in code always lacking DWARF-2 CFI, notably:
1411 * PLT stubs (library calls)
1413 * signal trampolines
1415 For those cases, it is assumed that there is no actual prologue; that
1416 the stack pointer is not adjusted, and (as a consequence) the return
1417 address is not pushed onto the stack. */
1419 /* We only want to know the end of the prologue when next_frame and info
1420 are NULL (called from cris_skip_prologue i.e.). */
1421 if (next_frame == NULL && info == NULL)
1426 /* The SP is assumed to be unaltered. */
1427 frame_unwind_unsigned_register (next_frame, gdbarch_sp_regnum (gdbarch),
1429 info->base = this_base;
1430 info->prev_sp = this_base;
1432 /* The PC is assumed to be found in SRP. */
1433 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1434 = info->saved_regs[SRP_REGNUM];
1439 /* Advance pc beyond any function entry prologue instructions at pc
1440 to reach some "real" code. */
1442 /* Given a PC value corresponding to the start of a function, return the PC
1443 of the first instruction after the function prologue. */
1446 cris_skip_prologue (CORE_ADDR pc)
1448 CORE_ADDR func_addr, func_end;
1449 struct symtab_and_line sal;
1450 CORE_ADDR pc_after_prologue;
1452 /* If we have line debugging information, then the end of the prologue
1453 should the first assembly instruction of the first source line. */
1454 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1456 sal = find_pc_line (func_addr, 0);
1457 if (sal.end > 0 && sal.end < func_end)
1461 if (cris_version () == 32)
1462 pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL);
1464 pc_after_prologue = cris_scan_prologue (pc, NULL, NULL);
1466 return pc_after_prologue;
1470 cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1473 frame_unwind_unsigned_register (next_frame,
1474 gdbarch_pc_regnum (gdbarch), &pc);
1479 cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1482 frame_unwind_unsigned_register (next_frame,
1483 gdbarch_sp_regnum (gdbarch), &sp);
1487 /* Use the program counter to determine the contents and size of a breakpoint
1488 instruction. It returns a pointer to a string of bytes that encode a
1489 breakpoint instruction, stores the length of the string to *lenptr, and
1490 adjusts pcptr (if necessary) to point to the actual memory location where
1491 the breakpoint should be inserted. */
1493 static const unsigned char *
1494 cris_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
1496 static unsigned char break8_insn[] = {0x38, 0xe9};
1497 static unsigned char break15_insn[] = {0x3f, 0xe9};
1500 if (cris_mode () == cris_mode_guru)
1501 return break15_insn;
1506 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1510 cris_spec_reg_applicable (struct cris_spec_reg spec_reg)
1512 int version = cris_version ();
1514 switch (spec_reg.applicable_version)
1516 case cris_ver_version_all:
1518 case cris_ver_warning:
1519 /* Indeterminate/obsolete. */
1522 return (version >= 0 && version <= 3);
1524 return (version >= 3);
1526 return (version == 8 || version == 9);
1528 return (version >= 8);
1529 case cris_ver_v0_10:
1530 return (version >= 0 && version <= 10);
1531 case cris_ver_v3_10:
1532 return (version >= 3 && version <= 10);
1533 case cris_ver_v8_10:
1534 return (version >= 8 && version <= 10);
1536 return (version == 10);
1538 return (version >= 10);
1540 return (version >= 32);
1542 /* Invalid cris version. */
1547 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1548 register, -1 for an invalid register. */
1551 cris_register_size (int regno)
1553 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1557 if (regno >= 0 && regno < NUM_GENREGS)
1559 /* General registers (R0 - R15) are 32 bits. */
1562 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1564 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1565 Adjust regno accordingly. */
1566 spec_regno = regno - NUM_GENREGS;
1568 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1570 if (cris_spec_regs[i].number == spec_regno
1571 && cris_spec_reg_applicable (cris_spec_regs[i]))
1572 /* Go with the first applicable register. */
1573 return cris_spec_regs[i].reg_size;
1575 /* Special register not applicable to this CRIS version. */
1578 else if (regno >= gdbarch_pc_regnum (current_gdbarch)
1579 && regno < gdbarch_num_regs (current_gdbarch))
1581 /* This will apply to CRISv32 only where there are additional registers
1582 after the special registers (pseudo PC and support registers). */
1590 /* Nonzero if regno should not be fetched from the target. This is the case
1591 for unimplemented (size 0) and non-existant registers. */
1594 cris_cannot_fetch_register (int regno)
1596 return ((regno < 0 || regno >= gdbarch_num_regs (current_gdbarch))
1597 || (cris_register_size (regno) == 0));
1600 /* Nonzero if regno should not be written to the target, for various
1604 cris_cannot_store_register (int regno)
1606 /* There are three kinds of registers we refuse to write to.
1607 1. Those that not implemented.
1608 2. Those that are read-only (depends on the processor mode).
1609 3. Those registers to which a write has no effect.
1613 || regno >= gdbarch_num_regs (current_gdbarch)
1614 || cris_register_size (regno) == 0)
1615 /* Not implemented. */
1618 else if (regno == VR_REGNUM)
1622 else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM)
1623 /* Writing has no effect. */
1626 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
1627 agent decide whether they are writable. */
1632 /* Nonzero if regno should not be fetched from the target. This is the case
1633 for unimplemented (size 0) and non-existant registers. */
1636 crisv32_cannot_fetch_register (int regno)
1638 return ((regno < 0 || regno >= gdbarch_num_regs (current_gdbarch))
1639 || (cris_register_size (regno) == 0));
1642 /* Nonzero if regno should not be written to the target, for various
1646 crisv32_cannot_store_register (int regno)
1648 /* There are three kinds of registers we refuse to write to.
1649 1. Those that not implemented.
1650 2. Those that are read-only (depends on the processor mode).
1651 3. Those registers to which a write has no effect.
1655 || regno >= gdbarch_num_regs (current_gdbarch)
1656 || cris_register_size (regno) == 0)
1657 /* Not implemented. */
1660 else if (regno == VR_REGNUM)
1664 else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM)
1665 /* Writing has no effect. */
1668 /* Many special registers are read-only in user mode. Let the debug
1669 agent decide whether they are writable. */
1674 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1675 of data in register regno. */
1677 static struct type *
1678 cris_register_type (struct gdbarch *gdbarch, int regno)
1680 if (regno == gdbarch_pc_regnum (gdbarch))
1681 return builtin_type_void_func_ptr;
1682 else if (regno == gdbarch_sp_regnum (gdbarch)
1683 || regno == CRIS_FP_REGNUM)
1684 return builtin_type_void_data_ptr;
1685 else if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1686 || (regno >= MOF_REGNUM && regno <= USP_REGNUM))
1687 /* Note: R8 taken care of previous clause. */
1688 return builtin_type_uint32;
1689 else if (regno >= P4_REGNUM && regno <= CCR_REGNUM)
1690 return builtin_type_uint16;
1691 else if (regno >= P0_REGNUM && regno <= VR_REGNUM)
1692 return builtin_type_uint8;
1694 /* Invalid (unimplemented) register. */
1695 return builtin_type_int0;
1698 static struct type *
1699 crisv32_register_type (struct gdbarch *gdbarch, int regno)
1701 if (regno == gdbarch_pc_regnum (gdbarch))
1702 return builtin_type_void_func_ptr;
1703 else if (regno == gdbarch_sp_regnum (gdbarch)
1704 || regno == CRIS_FP_REGNUM)
1705 return builtin_type_void_data_ptr;
1706 else if ((regno >= 0 && regno <= ACR_REGNUM)
1707 || (regno >= EXS_REGNUM && regno <= SPC_REGNUM)
1708 || (regno == PID_REGNUM)
1709 || (regno >= S0_REGNUM && regno <= S15_REGNUM))
1710 /* Note: R8 and SP taken care of by previous clause. */
1711 return builtin_type_uint32;
1712 else if (regno == WZ_REGNUM)
1713 return builtin_type_uint16;
1714 else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM)
1715 return builtin_type_uint8;
1718 /* Invalid (unimplemented) register. Should not happen as there are
1719 no unimplemented CRISv32 registers. */
1720 warning (_("crisv32_register_type: unknown regno %d"), regno);
1721 return builtin_type_int0;
1725 /* Stores a function return value of type type, where valbuf is the address
1726 of the value to be stored. */
1728 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1731 cris_store_return_value (struct type *type, struct regcache *regcache,
1735 int len = TYPE_LENGTH (type);
1739 /* Put the return value in R10. */
1740 val = extract_unsigned_integer (valbuf, len);
1741 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1745 /* Put the return value in R10 and R11. */
1746 val = extract_unsigned_integer (valbuf, 4);
1747 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1748 val = extract_unsigned_integer ((char *)valbuf + 4, len - 4);
1749 regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val);
1752 error (_("cris_store_return_value: type length too large."));
1755 /* Return the name of register regno as a string. Return NULL for an invalid or
1756 unimplemented register. */
1759 cris_special_register_name (int regno)
1764 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1765 Adjust regno accordingly. */
1766 spec_regno = regno - NUM_GENREGS;
1768 /* Assume nothing about the layout of the cris_spec_regs struct
1770 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1772 if (cris_spec_regs[i].number == spec_regno
1773 && cris_spec_reg_applicable (cris_spec_regs[i]))
1774 /* Go with the first applicable register. */
1775 return cris_spec_regs[i].name;
1777 /* Special register not applicable to this CRIS version. */
1782 cris_register_name (int regno)
1784 static char *cris_genreg_names[] =
1785 { "r0", "r1", "r2", "r3", \
1786 "r4", "r5", "r6", "r7", \
1787 "r8", "r9", "r10", "r11", \
1788 "r12", "r13", "sp", "pc" };
1790 if (regno >= 0 && regno < NUM_GENREGS)
1792 /* General register. */
1793 return cris_genreg_names[regno];
1795 else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (current_gdbarch))
1797 return cris_special_register_name (regno);
1801 /* Invalid register. */
1807 crisv32_register_name (int regno)
1809 static char *crisv32_genreg_names[] =
1810 { "r0", "r1", "r2", "r3", \
1811 "r4", "r5", "r6", "r7", \
1812 "r8", "r9", "r10", "r11", \
1813 "r12", "r13", "sp", "acr"
1816 static char *crisv32_sreg_names[] =
1817 { "s0", "s1", "s2", "s3", \
1818 "s4", "s5", "s6", "s7", \
1819 "s8", "s9", "s10", "s11", \
1820 "s12", "s13", "s14", "s15"
1823 if (regno >= 0 && regno < NUM_GENREGS)
1825 /* General register. */
1826 return crisv32_genreg_names[regno];
1828 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1830 return cris_special_register_name (regno);
1832 else if (regno == gdbarch_pc_regnum (current_gdbarch))
1836 else if (regno >= S0_REGNUM && regno <= S15_REGNUM)
1838 return crisv32_sreg_names[regno - S0_REGNUM];
1842 /* Invalid register. */
1847 /* Convert DWARF register number REG to the appropriate register
1848 number used by GDB. */
1851 cris_dwarf2_reg_to_regnum (int reg)
1853 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1854 numbering, MOF is 18).
1855 Adapted from gcc/config/cris/cris.h. */
1856 static int cris_dwarf_regmap[] = {
1868 if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap))
1869 regnum = cris_dwarf_regmap[reg];
1872 warning (_("Unmapped DWARF Register #%d encountered."), reg);
1877 /* DWARF-2 frame support. */
1880 cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1881 struct dwarf2_frame_state_reg *reg,
1882 struct frame_info *next_frame)
1884 /* The return address column. */
1885 if (regnum == gdbarch_pc_regnum (gdbarch))
1886 reg->how = DWARF2_FRAME_REG_RA;
1888 /* The call frame address. */
1889 else if (regnum == gdbarch_sp_regnum (gdbarch))
1890 reg->how = DWARF2_FRAME_REG_CFA;
1893 /* Extract from an array regbuf containing the raw register state a function
1894 return value of type type, and copy that, in virtual format, into
1897 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1900 cris_extract_return_value (struct type *type, struct regcache *regcache,
1904 int len = TYPE_LENGTH (type);
1908 /* Get the return value from R10. */
1909 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1910 store_unsigned_integer (valbuf, len, val);
1914 /* Get the return value from R10 and R11. */
1915 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1916 store_unsigned_integer (valbuf, 4, val);
1917 regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val);
1918 store_unsigned_integer ((char *)valbuf + 4, len - 4, val);
1921 error (_("cris_extract_return_value: type length too large"));
1924 /* Handle the CRIS return value convention. */
1926 static enum return_value_convention
1927 cris_return_value (struct gdbarch *gdbarch, struct type *type,
1928 struct regcache *regcache, gdb_byte *readbuf,
1929 const gdb_byte *writebuf)
1931 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1932 || TYPE_CODE (type) == TYPE_CODE_UNION
1933 || TYPE_LENGTH (type) > 8)
1934 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1935 goes on the stack. */
1936 return RETURN_VALUE_STRUCT_CONVENTION;
1939 cris_extract_return_value (type, regcache, readbuf);
1941 cris_store_return_value (type, regcache, writebuf);
1943 return RETURN_VALUE_REGISTER_CONVENTION;
1946 /* Calculates a value that measures how good inst_args constraints an
1947 instruction. It stems from cris_constraint, found in cris-dis.c. */
1950 constraint (unsigned int insn, const signed char *inst_args,
1951 inst_env_type *inst_env)
1956 const char *s = inst_args;
1962 if ((insn & 0x30) == 0x30)
1967 /* A prefix operand. */
1968 if (inst_env->prefix_found)
1974 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1975 valid "push" size. In case of special register, it may be != 4. */
1976 if (inst_env->prefix_found)
1982 retval = (((insn >> 0xC) & 0xF) == (insn & 0xF));
1990 tmp = (insn >> 0xC) & 0xF;
1992 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1994 /* Since we match four bits, we will give a value of
1995 4 - 1 = 3 in a match. If there is a corresponding
1996 exact match of a special register in another pattern, it
1997 will get a value of 4, which will be higher. This should
1998 be correct in that an exact pattern would match better that
2000 Note that there is a reason for not returning zero; the
2001 pattern for "clear" is partly matched in the bit-pattern
2002 (the two lower bits must be zero), while the bit-pattern
2003 for a move from a special register is matched in the
2004 register constraint.
2005 This also means we will will have a race condition if
2006 there is a partly match in three bits in the bit pattern. */
2007 if (tmp == cris_spec_regs[i].number)
2014 if (cris_spec_regs[i].name == NULL)
2021 /* Returns the number of bits set in the variable value. */
2024 number_of_bits (unsigned int value)
2026 int number_of_bits = 0;
2030 number_of_bits += 1;
2031 value &= (value - 1);
2033 return number_of_bits;
2036 /* Finds the address that should contain the single step breakpoint(s).
2037 It stems from code in cris-dis.c. */
2040 find_cris_op (unsigned short insn, inst_env_type *inst_env)
2043 int max_level_of_match = -1;
2044 int max_matched = -1;
2047 for (i = 0; cris_opcodes[i].name != NULL; i++)
2049 if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match)
2050 && ((cris_opcodes[i].lose & insn) == 0)
2051 /* Only CRISv10 instructions, please. */
2052 && (cris_opcodes[i].applicable_version != cris_ver_v32p))
2054 level_of_match = constraint (insn, cris_opcodes[i].args, inst_env);
2055 if (level_of_match >= 0)
2058 number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose);
2059 if (level_of_match > max_level_of_match)
2062 max_level_of_match = level_of_match;
2063 if (level_of_match == 16)
2065 /* All bits matched, cannot find better. */
2075 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
2076 actually an internal error. */
2079 find_step_target (struct frame_info *frame, inst_env_type *inst_env)
2083 unsigned short insn;
2084 struct gdbarch *gdbarch = get_frame_arch (frame);
2086 /* Create a local register image and set the initial state. */
2087 for (i = 0; i < NUM_GENREGS; i++)
2090 (unsigned long) get_frame_register_unsigned (frame, i);
2092 offset = NUM_GENREGS;
2093 for (i = 0; i < NUM_SPECREGS; i++)
2096 (unsigned long) get_frame_register_unsigned (frame, offset + i);
2098 inst_env->branch_found = 0;
2099 inst_env->slot_needed = 0;
2100 inst_env->delay_slot_pc_active = 0;
2101 inst_env->prefix_found = 0;
2102 inst_env->invalid = 0;
2103 inst_env->xflag_found = 0;
2104 inst_env->disable_interrupt = 0;
2106 /* Look for a step target. */
2109 /* Read an instruction from the client. */
2110 insn = read_memory_unsigned_integer
2111 (inst_env->reg[gdbarch_pc_regnum (gdbarch)], 2);
2113 /* If the instruction is not in a delay slot the new content of the
2114 PC is [PC] + 2. If the instruction is in a delay slot it is not
2115 that simple. Since a instruction in a delay slot cannot change
2116 the content of the PC, it does not matter what value PC will have.
2117 Just make sure it is a valid instruction. */
2118 if (!inst_env->delay_slot_pc_active)
2120 inst_env->reg[gdbarch_pc_regnum (gdbarch)] += 2;
2124 inst_env->delay_slot_pc_active = 0;
2125 inst_env->reg[gdbarch_pc_regnum (gdbarch)]
2126 = inst_env->delay_slot_pc;
2128 /* Analyse the present instruction. */
2129 i = find_cris_op (insn, inst_env);
2132 inst_env->invalid = 1;
2136 cris_gdb_func (cris_opcodes[i].op, insn, inst_env);
2138 } while (!inst_env->invalid
2139 && (inst_env->prefix_found || inst_env->xflag_found
2140 || inst_env->slot_needed));
2144 /* There is no hardware single-step support. The function find_step_target
2145 digs through the opcodes in order to find all possible targets.
2146 Either one ordinary target or two targets for branches may be found. */
2149 cris_software_single_step (struct frame_info *frame)
2151 inst_env_type inst_env;
2153 /* Analyse the present instruction environment and insert
2155 int status = find_step_target (frame, &inst_env);
2158 /* Could not find a target. Things are likely to go downhill
2160 warning (_("CRIS software single step could not find a step target."));
2164 /* Insert at most two breakpoints. One for the next PC content
2165 and possibly another one for a branch, jump, etc. */
2167 (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (get_frame_arch (frame))];
2168 insert_single_step_breakpoint (next_pc);
2169 if (inst_env.branch_found
2170 && (CORE_ADDR) inst_env.branch_break_address != next_pc)
2172 CORE_ADDR branch_target_address
2173 = (CORE_ADDR) inst_env.branch_break_address;
2174 insert_single_step_breakpoint (branch_target_address);
2181 /* Calculates the prefix value for quick offset addressing mode. */
2184 quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2186 /* It's invalid to be in a delay slot. You can't have a prefix to this
2187 instruction (not 100% sure). */
2188 if (inst_env->slot_needed || inst_env->prefix_found)
2190 inst_env->invalid = 1;
2194 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2195 inst_env->prefix_value += cris_get_bdap_quick_offset (inst);
2197 /* A prefix doesn't change the xflag_found. But the rest of the flags
2199 inst_env->slot_needed = 0;
2200 inst_env->prefix_found = 1;
2203 /* Updates the autoincrement register. The size of the increment is derived
2204 from the size of the operation. The PC is always kept aligned on even
2208 process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env)
2210 if (size == INST_BYTE_SIZE)
2212 inst_env->reg[cris_get_operand1 (inst)] += 1;
2214 /* The PC must be word aligned, so increase the PC with one
2215 word even if the size is byte. */
2216 if (cris_get_operand1 (inst) == REG_PC)
2218 inst_env->reg[REG_PC] += 1;
2221 else if (size == INST_WORD_SIZE)
2223 inst_env->reg[cris_get_operand1 (inst)] += 2;
2225 else if (size == INST_DWORD_SIZE)
2227 inst_env->reg[cris_get_operand1 (inst)] += 4;
2232 inst_env->invalid = 1;
2236 /* Just a forward declaration. */
2238 static unsigned long get_data_from_address (unsigned short *inst,
2241 /* Calculates the prefix value for the general case of offset addressing
2245 bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2250 /* It's invalid to be in a delay slot. */
2251 if (inst_env->slot_needed || inst_env->prefix_found)
2253 inst_env->invalid = 1;
2257 /* The calculation of prefix_value used to be after process_autoincrement,
2258 but that fails for an instruction such as jsr [$r0+12] which is encoded
2259 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
2260 mustn't be incremented until we have read it and what it points at. */
2261 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2263 /* The offset is an indirection of the contents of the operand1 register. */
2264 inst_env->prefix_value +=
2265 get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)]);
2267 if (cris_get_mode (inst) == AUTOINC_MODE)
2269 process_autoincrement (cris_get_size (inst), inst, inst_env);
2272 /* A prefix doesn't change the xflag_found. But the rest of the flags
2274 inst_env->slot_needed = 0;
2275 inst_env->prefix_found = 1;
2278 /* Calculates the prefix value for the index addressing mode. */
2281 biap_prefix (unsigned short inst, inst_env_type *inst_env)
2283 /* It's invalid to be in a delay slot. I can't see that it's possible to
2284 have a prefix to this instruction. So I will treat this as invalid. */
2285 if (inst_env->slot_needed || inst_env->prefix_found)
2287 inst_env->invalid = 1;
2291 inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)];
2293 /* The offset is the operand2 value shifted the size of the instruction
2295 inst_env->prefix_value +=
2296 inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst);
2298 /* If the PC is operand1 (base) the address used is the address after
2299 the main instruction, i.e. address + 2 (the PC is already compensated
2300 for the prefix operation). */
2301 if (cris_get_operand1 (inst) == REG_PC)
2303 inst_env->prefix_value += 2;
2306 /* A prefix doesn't change the xflag_found. But the rest of the flags
2308 inst_env->slot_needed = 0;
2309 inst_env->xflag_found = 0;
2310 inst_env->prefix_found = 1;
2313 /* Calculates the prefix value for the double indirect addressing mode. */
2316 dip_prefix (unsigned short inst, inst_env_type *inst_env)
2321 /* It's invalid to be in a delay slot. */
2322 if (inst_env->slot_needed || inst_env->prefix_found)
2324 inst_env->invalid = 1;
2328 /* The prefix value is one dereference of the contents of the operand1
2330 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2331 inst_env->prefix_value = read_memory_unsigned_integer (address, 4);
2333 /* Check if the mode is autoincrement. */
2334 if (cris_get_mode (inst) == AUTOINC_MODE)
2336 inst_env->reg[cris_get_operand1 (inst)] += 4;
2339 /* A prefix doesn't change the xflag_found. But the rest of the flags
2341 inst_env->slot_needed = 0;
2342 inst_env->xflag_found = 0;
2343 inst_env->prefix_found = 1;
2346 /* Finds the destination for a branch with 8-bits offset. */
2349 eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2354 /* If we have a prefix or are in a delay slot it's bad. */
2355 if (inst_env->slot_needed || inst_env->prefix_found)
2357 inst_env->invalid = 1;
2361 /* We have a branch, find out where the branch will land. */
2362 offset = cris_get_branch_short_offset (inst);
2364 /* Check if the offset is signed. */
2365 if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK)
2370 /* The offset ends with the sign bit, set it to zero. The address
2371 should always be word aligned. */
2372 offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK;
2374 inst_env->branch_found = 1;
2375 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2377 inst_env->slot_needed = 1;
2378 inst_env->prefix_found = 0;
2379 inst_env->xflag_found = 0;
2380 inst_env->disable_interrupt = 1;
2383 /* Finds the destination for a branch with 16-bits offset. */
2386 sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2390 /* If we have a prefix or is in a delay slot it's bad. */
2391 if (inst_env->slot_needed || inst_env->prefix_found)
2393 inst_env->invalid = 1;
2397 /* We have a branch, find out the offset for the branch. */
2398 offset = read_memory_integer (inst_env->reg[REG_PC], 2);
2400 /* The instruction is one word longer than normal, so add one word
2402 inst_env->reg[REG_PC] += 2;
2404 inst_env->branch_found = 1;
2405 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2408 inst_env->slot_needed = 1;
2409 inst_env->prefix_found = 0;
2410 inst_env->xflag_found = 0;
2411 inst_env->disable_interrupt = 1;
2414 /* Handles the ABS instruction. */
2417 abs_op (unsigned short inst, inst_env_type *inst_env)
2422 /* ABS can't have a prefix, so it's bad if it does. */
2423 if (inst_env->prefix_found)
2425 inst_env->invalid = 1;
2429 /* Check if the operation affects the PC. */
2430 if (cris_get_operand2 (inst) == REG_PC)
2433 /* It's invalid to change to the PC if we are in a delay slot. */
2434 if (inst_env->slot_needed)
2436 inst_env->invalid = 1;
2440 value = (long) inst_env->reg[REG_PC];
2442 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
2443 if (value != SIGNED_DWORD_MASK)
2446 inst_env->reg[REG_PC] = (long) value;
2450 inst_env->slot_needed = 0;
2451 inst_env->prefix_found = 0;
2452 inst_env->xflag_found = 0;
2453 inst_env->disable_interrupt = 0;
2456 /* Handles the ADDI instruction. */
2459 addi_op (unsigned short inst, inst_env_type *inst_env)
2461 /* It's invalid to have the PC as base register. And ADDI can't have
2463 if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC))
2465 inst_env->invalid = 1;
2469 inst_env->slot_needed = 0;
2470 inst_env->prefix_found = 0;
2471 inst_env->xflag_found = 0;
2472 inst_env->disable_interrupt = 0;
2475 /* Handles the ASR instruction. */
2478 asr_op (unsigned short inst, inst_env_type *inst_env)
2481 unsigned long value;
2482 unsigned long signed_extend_mask = 0;
2484 /* ASR can't have a prefix, so check that it doesn't. */
2485 if (inst_env->prefix_found)
2487 inst_env->invalid = 1;
2491 /* Check if the PC is the target register. */
2492 if (cris_get_operand2 (inst) == REG_PC)
2494 /* It's invalid to change the PC in a delay slot. */
2495 if (inst_env->slot_needed)
2497 inst_env->invalid = 1;
2500 /* Get the number of bits to shift. */
2501 shift_steps = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]);
2502 value = inst_env->reg[REG_PC];
2504 /* Find out how many bits the operation should apply to. */
2505 if (cris_get_size (inst) == INST_BYTE_SIZE)
2507 if (value & SIGNED_BYTE_MASK)
2509 signed_extend_mask = 0xFF;
2510 signed_extend_mask = signed_extend_mask >> shift_steps;
2511 signed_extend_mask = ~signed_extend_mask;
2513 value = value >> shift_steps;
2514 value |= signed_extend_mask;
2516 inst_env->reg[REG_PC] &= 0xFFFFFF00;
2517 inst_env->reg[REG_PC] |= value;
2519 else if (cris_get_size (inst) == INST_WORD_SIZE)
2521 if (value & SIGNED_WORD_MASK)
2523 signed_extend_mask = 0xFFFF;
2524 signed_extend_mask = signed_extend_mask >> shift_steps;
2525 signed_extend_mask = ~signed_extend_mask;
2527 value = value >> shift_steps;
2528 value |= signed_extend_mask;
2530 inst_env->reg[REG_PC] &= 0xFFFF0000;
2531 inst_env->reg[REG_PC] |= value;
2533 else if (cris_get_size (inst) == INST_DWORD_SIZE)
2535 if (value & SIGNED_DWORD_MASK)
2537 signed_extend_mask = 0xFFFFFFFF;
2538 signed_extend_mask = signed_extend_mask >> shift_steps;
2539 signed_extend_mask = ~signed_extend_mask;
2541 value = value >> shift_steps;
2542 value |= signed_extend_mask;
2543 inst_env->reg[REG_PC] = value;
2546 inst_env->slot_needed = 0;
2547 inst_env->prefix_found = 0;
2548 inst_env->xflag_found = 0;
2549 inst_env->disable_interrupt = 0;
2552 /* Handles the ASRQ instruction. */
2555 asrq_op (unsigned short inst, inst_env_type *inst_env)
2559 unsigned long value;
2560 unsigned long signed_extend_mask = 0;
2562 /* ASRQ can't have a prefix, so check that it doesn't. */
2563 if (inst_env->prefix_found)
2565 inst_env->invalid = 1;
2569 /* Check if the PC is the target register. */
2570 if (cris_get_operand2 (inst) == REG_PC)
2573 /* It's invalid to change the PC in a delay slot. */
2574 if (inst_env->slot_needed)
2576 inst_env->invalid = 1;
2579 /* The shift size is given as a 5 bit quick value, i.e. we don't
2580 want the the sign bit of the quick value. */
2581 shift_steps = cris_get_asr_shift_steps (inst);
2582 value = inst_env->reg[REG_PC];
2583 if (value & SIGNED_DWORD_MASK)
2585 signed_extend_mask = 0xFFFFFFFF;
2586 signed_extend_mask = signed_extend_mask >> shift_steps;
2587 signed_extend_mask = ~signed_extend_mask;
2589 value = value >> shift_steps;
2590 value |= signed_extend_mask;
2591 inst_env->reg[REG_PC] = value;
2593 inst_env->slot_needed = 0;
2594 inst_env->prefix_found = 0;
2595 inst_env->xflag_found = 0;
2596 inst_env->disable_interrupt = 0;
2599 /* Handles the AX, EI and SETF instruction. */
2602 ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env)
2604 if (inst_env->prefix_found)
2606 inst_env->invalid = 1;
2609 /* Check if the instruction is setting the X flag. */
2610 if (cris_is_xflag_bit_on (inst))
2612 inst_env->xflag_found = 1;
2616 inst_env->xflag_found = 0;
2618 inst_env->slot_needed = 0;
2619 inst_env->prefix_found = 0;
2620 inst_env->disable_interrupt = 1;
2623 /* Checks if the instruction is in assign mode. If so, it updates the assign
2624 register. Note that check_assign assumes that the caller has checked that
2625 there is a prefix to this instruction. The mode check depends on this. */
2628 check_assign (unsigned short inst, inst_env_type *inst_env)
2630 /* Check if it's an assign addressing mode. */
2631 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2633 /* Assign the prefix value to operand 1. */
2634 inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value;
2638 /* Handles the 2-operand BOUND instruction. */
2641 two_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2643 /* It's invalid to have the PC as the index operand. */
2644 if (cris_get_operand2 (inst) == REG_PC)
2646 inst_env->invalid = 1;
2649 /* Check if we have a prefix. */
2650 if (inst_env->prefix_found)
2652 check_assign (inst, inst_env);
2654 /* Check if this is an autoincrement mode. */
2655 else if (cris_get_mode (inst) == AUTOINC_MODE)
2657 /* It's invalid to change the PC in a delay slot. */
2658 if (inst_env->slot_needed)
2660 inst_env->invalid = 1;
2663 process_autoincrement (cris_get_size (inst), inst, inst_env);
2665 inst_env->slot_needed = 0;
2666 inst_env->prefix_found = 0;
2667 inst_env->xflag_found = 0;
2668 inst_env->disable_interrupt = 0;
2671 /* Handles the 3-operand BOUND instruction. */
2674 three_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2676 /* It's an error if we haven't got a prefix. And it's also an error
2677 if the PC is the destination register. */
2678 if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC))
2680 inst_env->invalid = 1;
2683 inst_env->slot_needed = 0;
2684 inst_env->prefix_found = 0;
2685 inst_env->xflag_found = 0;
2686 inst_env->disable_interrupt = 0;
2689 /* Clears the status flags in inst_env. */
2692 btst_nop_op (unsigned short inst, inst_env_type *inst_env)
2694 /* It's an error if we have got a prefix. */
2695 if (inst_env->prefix_found)
2697 inst_env->invalid = 1;
2701 inst_env->slot_needed = 0;
2702 inst_env->prefix_found = 0;
2703 inst_env->xflag_found = 0;
2704 inst_env->disable_interrupt = 0;
2707 /* Clears the status flags in inst_env. */
2710 clearf_di_op (unsigned short inst, inst_env_type *inst_env)
2712 /* It's an error if we have got a prefix. */
2713 if (inst_env->prefix_found)
2715 inst_env->invalid = 1;
2719 inst_env->slot_needed = 0;
2720 inst_env->prefix_found = 0;
2721 inst_env->xflag_found = 0;
2722 inst_env->disable_interrupt = 1;
2725 /* Handles the CLEAR instruction if it's in register mode. */
2728 reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env)
2730 /* Check if the target is the PC. */
2731 if (cris_get_operand2 (inst) == REG_PC)
2733 /* The instruction will clear the instruction's size bits. */
2734 int clear_size = cris_get_clear_size (inst);
2735 if (clear_size == INST_BYTE_SIZE)
2737 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00;
2739 if (clear_size == INST_WORD_SIZE)
2741 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000;
2743 if (clear_size == INST_DWORD_SIZE)
2745 inst_env->delay_slot_pc = 0x0;
2747 /* The jump will be delayed with one delay slot. So we need a delay
2749 inst_env->slot_needed = 1;
2750 inst_env->delay_slot_pc_active = 1;
2754 /* The PC will not change => no delay slot. */
2755 inst_env->slot_needed = 0;
2757 inst_env->prefix_found = 0;
2758 inst_env->xflag_found = 0;
2759 inst_env->disable_interrupt = 0;
2762 /* Handles the TEST instruction if it's in register mode. */
2765 reg_mode_test_op (unsigned short inst, inst_env_type *inst_env)
2767 /* It's an error if we have got a prefix. */
2768 if (inst_env->prefix_found)
2770 inst_env->invalid = 1;
2773 inst_env->slot_needed = 0;
2774 inst_env->prefix_found = 0;
2775 inst_env->xflag_found = 0;
2776 inst_env->disable_interrupt = 0;
2780 /* Handles the CLEAR and TEST instruction if the instruction isn't
2781 in register mode. */
2784 none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env)
2786 /* Check if we are in a prefix mode. */
2787 if (inst_env->prefix_found)
2789 /* The only way the PC can change is if this instruction is in
2790 assign addressing mode. */
2791 check_assign (inst, inst_env);
2793 /* Indirect mode can't change the PC so just check if the mode is
2795 else if (cris_get_mode (inst) == AUTOINC_MODE)
2797 process_autoincrement (cris_get_size (inst), inst, inst_env);
2799 inst_env->slot_needed = 0;
2800 inst_env->prefix_found = 0;
2801 inst_env->xflag_found = 0;
2802 inst_env->disable_interrupt = 0;
2805 /* Checks that the PC isn't the destination register or the instructions has
2809 dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env)
2811 /* It's invalid to have the PC as the destination. The instruction can't
2813 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2815 inst_env->invalid = 1;
2819 inst_env->slot_needed = 0;
2820 inst_env->prefix_found = 0;
2821 inst_env->xflag_found = 0;
2822 inst_env->disable_interrupt = 0;
2825 /* Checks that the instruction doesn't have a prefix. */
2828 break_op (unsigned short inst, inst_env_type *inst_env)
2830 /* The instruction can't have a prefix. */
2831 if (inst_env->prefix_found)
2833 inst_env->invalid = 1;
2837 inst_env->slot_needed = 0;
2838 inst_env->prefix_found = 0;
2839 inst_env->xflag_found = 0;
2840 inst_env->disable_interrupt = 1;
2843 /* Checks that the PC isn't the destination register and that the instruction
2844 doesn't have a prefix. */
2847 scc_op (unsigned short inst, inst_env_type *inst_env)
2849 /* It's invalid to have the PC as the destination. The instruction can't
2851 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2853 inst_env->invalid = 1;
2857 inst_env->slot_needed = 0;
2858 inst_env->prefix_found = 0;
2859 inst_env->xflag_found = 0;
2860 inst_env->disable_interrupt = 1;
2863 /* Handles the register mode JUMP instruction. */
2866 reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2868 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2869 you can't have a prefix. */
2870 if ((inst_env->slot_needed) || (inst_env->prefix_found))
2872 inst_env->invalid = 1;
2876 /* Just change the PC. */
2877 inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)];
2878 inst_env->slot_needed = 0;
2879 inst_env->prefix_found = 0;
2880 inst_env->xflag_found = 0;
2881 inst_env->disable_interrupt = 1;
2884 /* Handles the JUMP instruction for all modes except register. */
2887 none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2889 unsigned long newpc;
2892 /* It's invalid to do a JUMP in a delay slot. */
2893 if (inst_env->slot_needed)
2895 inst_env->invalid = 1;
2899 /* Check if we have a prefix. */
2900 if (inst_env->prefix_found)
2902 check_assign (inst, inst_env);
2904 /* Get the new value for the the PC. */
2906 read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value,
2911 /* Get the new value for the PC. */
2912 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2913 newpc = read_memory_unsigned_integer (address, 4);
2915 /* Check if we should increment a register. */
2916 if (cris_get_mode (inst) == AUTOINC_MODE)
2918 inst_env->reg[cris_get_operand1 (inst)] += 4;
2921 inst_env->reg[REG_PC] = newpc;
2923 inst_env->slot_needed = 0;
2924 inst_env->prefix_found = 0;
2925 inst_env->xflag_found = 0;
2926 inst_env->disable_interrupt = 1;
2929 /* Handles moves to special registers (aka P-register) for all modes. */
2932 move_to_preg_op (unsigned short inst, inst_env_type *inst_env)
2934 if (inst_env->prefix_found)
2936 /* The instruction has a prefix that means we are only interested if
2937 the instruction is in assign mode. */
2938 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2940 /* The prefix handles the problem if we are in a delay slot. */
2941 if (cris_get_operand1 (inst) == REG_PC)
2943 /* Just take care of the assign. */
2944 check_assign (inst, inst_env);
2948 else if (cris_get_mode (inst) == AUTOINC_MODE)
2950 /* The instruction doesn't have a prefix, the only case left that we
2951 are interested in is the autoincrement mode. */
2952 if (cris_get_operand1 (inst) == REG_PC)
2954 /* If the PC is to be incremented it's invalid to be in a
2956 if (inst_env->slot_needed)
2958 inst_env->invalid = 1;
2962 /* The increment depends on the size of the special register. */
2963 if (cris_register_size (cris_get_operand2 (inst)) == 1)
2965 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2967 else if (cris_register_size (cris_get_operand2 (inst)) == 2)
2969 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2973 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2977 inst_env->slot_needed = 0;
2978 inst_env->prefix_found = 0;
2979 inst_env->xflag_found = 0;
2980 inst_env->disable_interrupt = 1;
2983 /* Handles moves from special registers (aka P-register) for all modes
2987 none_reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env)
2989 if (inst_env->prefix_found)
2991 /* The instruction has a prefix that means we are only interested if
2992 the instruction is in assign mode. */
2993 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2995 /* The prefix handles the problem if we are in a delay slot. */
2996 if (cris_get_operand1 (inst) == REG_PC)
2998 /* Just take care of the assign. */
2999 check_assign (inst, inst_env);
3003 /* The instruction doesn't have a prefix, the only case left that we
3004 are interested in is the autoincrement mode. */
3005 else if (cris_get_mode (inst) == AUTOINC_MODE)
3007 if (cris_get_operand1 (inst) == REG_PC)
3009 /* If the PC is to be incremented it's invalid to be in a
3011 if (inst_env->slot_needed)
3013 inst_env->invalid = 1;
3017 /* The increment depends on the size of the special register. */
3018 if (cris_register_size (cris_get_operand2 (inst)) == 1)
3020 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
3022 else if (cris_register_size (cris_get_operand2 (inst)) == 2)
3024 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
3028 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
3032 inst_env->slot_needed = 0;
3033 inst_env->prefix_found = 0;
3034 inst_env->xflag_found = 0;
3035 inst_env->disable_interrupt = 1;
3038 /* Handles moves from special registers (aka P-register) when the mode
3042 reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env)
3044 /* Register mode move from special register can't have a prefix. */
3045 if (inst_env->prefix_found)
3047 inst_env->invalid = 1;
3051 if (cris_get_operand1 (inst) == REG_PC)
3053 /* It's invalid to change the PC in a delay slot. */
3054 if (inst_env->slot_needed)
3056 inst_env->invalid = 1;
3059 /* The destination is the PC, the jump will have a delay slot. */
3060 inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)];
3061 inst_env->slot_needed = 1;
3062 inst_env->delay_slot_pc_active = 1;
3066 /* If the destination isn't PC, there will be no jump. */
3067 inst_env->slot_needed = 0;
3069 inst_env->prefix_found = 0;
3070 inst_env->xflag_found = 0;
3071 inst_env->disable_interrupt = 1;
3074 /* Handles the MOVEM from memory to general register instruction. */
3077 move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env)
3079 if (inst_env->prefix_found)
3081 /* The prefix handles the problem if we are in a delay slot. Is the
3082 MOVEM instruction going to change the PC? */
3083 if (cris_get_operand2 (inst) >= REG_PC)
3085 inst_env->reg[REG_PC] =
3086 read_memory_unsigned_integer (inst_env->prefix_value, 4);
3088 /* The assign value is the value after the increment. Normally, the
3089 assign value is the value before the increment. */
3090 if ((cris_get_operand1 (inst) == REG_PC)
3091 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3093 inst_env->reg[REG_PC] = inst_env->prefix_value;
3094 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3099 /* Is the MOVEM instruction going to change the PC? */
3100 if (cris_get_operand2 (inst) == REG_PC)
3102 /* It's invalid to change the PC in a delay slot. */
3103 if (inst_env->slot_needed)
3105 inst_env->invalid = 1;
3108 inst_env->reg[REG_PC] =
3109 read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)],
3112 /* The increment is not depending on the size, instead it's depending
3113 on the number of registers loaded from memory. */
3114 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3116 /* It's invalid to change the PC in a delay slot. */
3117 if (inst_env->slot_needed)
3119 inst_env->invalid = 1;
3122 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3125 inst_env->slot_needed = 0;
3126 inst_env->prefix_found = 0;
3127 inst_env->xflag_found = 0;
3128 inst_env->disable_interrupt = 0;
3131 /* Handles the MOVEM to memory from general register instruction. */
3134 move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env)
3136 if (inst_env->prefix_found)
3138 /* The assign value is the value after the increment. Normally, the
3139 assign value is the value before the increment. */
3140 if ((cris_get_operand1 (inst) == REG_PC) &&
3141 (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3143 /* The prefix handles the problem if we are in a delay slot. */
3144 inst_env->reg[REG_PC] = inst_env->prefix_value;
3145 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3150 /* The increment is not depending on the size, instead it's depending
3151 on the number of registers loaded to memory. */
3152 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3154 /* It's invalid to change the PC in a delay slot. */
3155 if (inst_env->slot_needed)
3157 inst_env->invalid = 1;
3160 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3163 inst_env->slot_needed = 0;
3164 inst_env->prefix_found = 0;
3165 inst_env->xflag_found = 0;
3166 inst_env->disable_interrupt = 0;
3169 /* Handles the intructions that's not yet implemented, by setting
3170 inst_env->invalid to true. */
3173 not_implemented_op (unsigned short inst, inst_env_type *inst_env)
3175 inst_env->invalid = 1;
3178 /* Handles the XOR instruction. */
3181 xor_op (unsigned short inst, inst_env_type *inst_env)
3183 /* XOR can't have a prefix. */
3184 if (inst_env->prefix_found)
3186 inst_env->invalid = 1;
3190 /* Check if the PC is the target. */
3191 if (cris_get_operand2 (inst) == REG_PC)
3193 /* It's invalid to change the PC in a delay slot. */
3194 if (inst_env->slot_needed)
3196 inst_env->invalid = 1;
3199 inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)];
3201 inst_env->slot_needed = 0;
3202 inst_env->prefix_found = 0;
3203 inst_env->xflag_found = 0;
3204 inst_env->disable_interrupt = 0;
3207 /* Handles the MULS instruction. */
3210 muls_op (unsigned short inst, inst_env_type *inst_env)
3212 /* MULS/U can't have a prefix. */
3213 if (inst_env->prefix_found)
3215 inst_env->invalid = 1;
3219 /* Consider it invalid if the PC is the target. */
3220 if (cris_get_operand2 (inst) == REG_PC)
3222 inst_env->invalid = 1;
3225 inst_env->slot_needed = 0;
3226 inst_env->prefix_found = 0;
3227 inst_env->xflag_found = 0;
3228 inst_env->disable_interrupt = 0;
3231 /* Handles the MULU instruction. */
3234 mulu_op (unsigned short inst, inst_env_type *inst_env)
3236 /* MULS/U can't have a prefix. */
3237 if (inst_env->prefix_found)
3239 inst_env->invalid = 1;
3243 /* Consider it invalid if the PC is the target. */
3244 if (cris_get_operand2 (inst) == REG_PC)
3246 inst_env->invalid = 1;
3249 inst_env->slot_needed = 0;
3250 inst_env->prefix_found = 0;
3251 inst_env->xflag_found = 0;
3252 inst_env->disable_interrupt = 0;
3255 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
3256 The MOVE instruction is the move from source to register. */
3259 add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env,
3260 unsigned long source1, unsigned long source2)
3262 unsigned long pc_mask;
3263 unsigned long operation_mask;
3265 /* Find out how many bits the operation should apply to. */
3266 if (cris_get_size (inst) == INST_BYTE_SIZE)
3268 pc_mask = 0xFFFFFF00;
3269 operation_mask = 0xFF;
3271 else if (cris_get_size (inst) == INST_WORD_SIZE)
3273 pc_mask = 0xFFFF0000;
3274 operation_mask = 0xFFFF;
3276 else if (cris_get_size (inst) == INST_DWORD_SIZE)
3279 operation_mask = 0xFFFFFFFF;
3283 /* The size is out of range. */
3284 inst_env->invalid = 1;
3288 /* The instruction just works on uw_operation_mask bits. */
3289 source2 &= operation_mask;
3290 source1 &= operation_mask;
3292 /* Now calculate the result. The opcode's 3 first bits separates
3293 the different actions. */
3294 switch (cris_get_opcode (inst) & 7)
3304 case 2: /* subtract */
3308 case 3: /* compare */
3320 inst_env->invalid = 1;
3326 /* Make sure that the result doesn't contain more than the instruction
3328 source2 &= operation_mask;
3330 /* Calculate the new breakpoint address. */
3331 inst_env->reg[REG_PC] &= pc_mask;
3332 inst_env->reg[REG_PC] |= source1;
3336 /* Extends the value from either byte or word size to a dword. If the mode
3337 is zero extend then the value is extended with zero. If instead the mode
3338 is signed extend the sign bit of the value is taken into consideration. */
3340 static unsigned long
3341 do_sign_or_zero_extend (unsigned long value, unsigned short *inst)
3343 /* The size can be either byte or word, check which one it is.
3344 Don't check the highest bit, it's indicating if it's a zero
3346 if (cris_get_size (*inst) & INST_WORD_SIZE)
3351 /* Check if the instruction is signed extend. If so, check if value has
3353 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK))
3355 value |= SIGNED_WORD_EXTEND_MASK;
3363 /* Check if the instruction is signed extend. If so, check if value has
3365 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK))
3367 value |= SIGNED_BYTE_EXTEND_MASK;
3370 /* The size should now be dword. */
3371 cris_set_size_to_dword (inst);
3375 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3376 instruction. The MOVE instruction is the move from source to register. */
3379 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3380 inst_env_type *inst_env)
3382 unsigned long operand1;
3383 unsigned long operand2;
3385 /* It's invalid to have a prefix to the instruction. This is a register
3386 mode instruction and can't have a prefix. */
3387 if (inst_env->prefix_found)
3389 inst_env->invalid = 1;
3392 /* Check if the instruction has PC as its target. */
3393 if (cris_get_operand2 (inst) == REG_PC)
3395 if (inst_env->slot_needed)
3397 inst_env->invalid = 1;
3400 /* The instruction has the PC as its target register. */
3401 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3402 operand2 = inst_env->reg[REG_PC];
3404 /* Check if it's a extend, signed or zero instruction. */
3405 if (cris_get_opcode (inst) < 4)
3407 operand1 = do_sign_or_zero_extend (operand1, &inst);
3409 /* Calculate the PC value after the instruction, i.e. where the
3410 breakpoint should be. The order of the udw_operands is vital. */
3411 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3413 inst_env->slot_needed = 0;
3414 inst_env->prefix_found = 0;
3415 inst_env->xflag_found = 0;
3416 inst_env->disable_interrupt = 0;
3419 /* Returns the data contained at address. The size of the data is derived from
3420 the size of the operation. If the instruction is a zero or signed
3421 extend instruction, the size field is changed in instruction. */
3423 static unsigned long
3424 get_data_from_address (unsigned short *inst, CORE_ADDR address)
3426 int size = cris_get_size (*inst);
3427 unsigned long value;
3429 /* If it's an extend instruction we don't want the signed extend bit,
3430 because it influences the size. */
3431 if (cris_get_opcode (*inst) < 4)
3433 size &= ~SIGNED_EXTEND_BIT_MASK;
3435 /* Is there a need for checking the size? Size should contain the number of
3438 value = read_memory_unsigned_integer (address, size);
3440 /* Check if it's an extend, signed or zero instruction. */
3441 if (cris_get_opcode (*inst) < 4)
3443 value = do_sign_or_zero_extend (value, inst);
3448 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3449 instructions. The MOVE instruction is the move from source to register. */
3452 handle_prefix_assign_mode_for_aritm_op (unsigned short inst,
3453 inst_env_type *inst_env)
3455 unsigned long operand2;
3456 unsigned long operand3;
3458 check_assign (inst, inst_env);
3459 if (cris_get_operand2 (inst) == REG_PC)
3461 operand2 = inst_env->reg[REG_PC];
3463 /* Get the value of the third operand. */
3464 operand3 = get_data_from_address (&inst, inst_env->prefix_value);
3466 /* Calculate the PC value after the instruction, i.e. where the
3467 breakpoint should be. The order of the udw_operands is vital. */
3468 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3470 inst_env->slot_needed = 0;
3471 inst_env->prefix_found = 0;
3472 inst_env->xflag_found = 0;
3473 inst_env->disable_interrupt = 0;
3476 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3477 OR instructions. Note that for this to work as expected, the calling
3478 function must have made sure that there is a prefix to this instruction. */
3481 three_operand_add_sub_cmp_and_or_op (unsigned short inst,
3482 inst_env_type *inst_env)
3484 unsigned long operand2;
3485 unsigned long operand3;
3487 if (cris_get_operand1 (inst) == REG_PC)
3489 /* The PC will be changed by the instruction. */
3490 operand2 = inst_env->reg[cris_get_operand2 (inst)];
3492 /* Get the value of the third operand. */
3493 operand3 = get_data_from_address (&inst, inst_env->prefix_value);
3495 /* Calculate the PC value after the instruction, i.e. where the
3496 breakpoint should be. */
3497 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3499 inst_env->slot_needed = 0;
3500 inst_env->prefix_found = 0;
3501 inst_env->xflag_found = 0;
3502 inst_env->disable_interrupt = 0;
3505 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3506 instructions. The MOVE instruction is the move from source to register. */
3509 handle_prefix_index_mode_for_aritm_op (unsigned short inst,
3510 inst_env_type *inst_env)
3512 if (cris_get_operand1 (inst) != cris_get_operand2 (inst))
3514 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
3515 SUB, AND or OR something weird is going on (if everything works these
3516 instructions should end up in the three operand version). */
3517 inst_env->invalid = 1;
3522 /* three_operand_add_sub_cmp_and_or does the same as we should do here
3524 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3526 inst_env->slot_needed = 0;
3527 inst_env->prefix_found = 0;
3528 inst_env->xflag_found = 0;
3529 inst_env->disable_interrupt = 0;
3532 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3533 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
3534 source to register. */
3537 handle_inc_and_index_mode_for_aritm_op (unsigned short inst,
3538 inst_env_type *inst_env)
3540 unsigned long operand1;
3541 unsigned long operand2;
3542 unsigned long operand3;
3545 /* The instruction is either an indirect or autoincrement addressing mode.
3546 Check if the destination register is the PC. */
3547 if (cris_get_operand2 (inst) == REG_PC)
3549 /* Must be done here, get_data_from_address may change the size
3551 size = cris_get_size (inst);
3552 operand2 = inst_env->reg[REG_PC];
3554 /* Get the value of the third operand, i.e. the indirect operand. */
3555 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3556 operand3 = get_data_from_address (&inst, operand1);
3558 /* Calculate the PC value after the instruction, i.e. where the
3559 breakpoint should be. The order of the udw_operands is vital. */
3560 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3562 /* If this is an autoincrement addressing mode, check if the increment
3564 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3566 /* Get the size field. */
3567 size = cris_get_size (inst);
3569 /* If it's an extend instruction we don't want the signed extend bit,
3570 because it influences the size. */
3571 if (cris_get_opcode (inst) < 4)
3573 size &= ~SIGNED_EXTEND_BIT_MASK;
3575 process_autoincrement (size, inst, inst_env);
3577 inst_env->slot_needed = 0;
3578 inst_env->prefix_found = 0;
3579 inst_env->xflag_found = 0;
3580 inst_env->disable_interrupt = 0;
3583 /* Handles the two-operand addressing mode, all modes except register, for
3584 the ADD, SUB CMP, AND and OR instruction. */
3587 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3588 inst_env_type *inst_env)
3590 if (inst_env->prefix_found)
3592 if (cris_get_mode (inst) == PREFIX_INDEX_MODE)
3594 handle_prefix_index_mode_for_aritm_op (inst, inst_env);
3596 else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
3598 handle_prefix_assign_mode_for_aritm_op (inst, inst_env);
3602 /* The mode is invalid for a prefixed base instruction. */
3603 inst_env->invalid = 1;
3609 handle_inc_and_index_mode_for_aritm_op (inst, inst_env);
3613 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3616 quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env)
3618 unsigned long operand1;
3619 unsigned long operand2;
3621 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3622 instruction and can't have a prefix. */
3623 if (inst_env->prefix_found)
3625 inst_env->invalid = 1;
3629 /* Check if the instruction has PC as its target. */
3630 if (cris_get_operand2 (inst) == REG_PC)
3632 if (inst_env->slot_needed)
3634 inst_env->invalid = 1;
3637 operand1 = cris_get_quick_value (inst);
3638 operand2 = inst_env->reg[REG_PC];
3640 /* The size should now be dword. */
3641 cris_set_size_to_dword (&inst);
3643 /* Calculate the PC value after the instruction, i.e. where the
3644 breakpoint should be. */
3645 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3647 inst_env->slot_needed = 0;
3648 inst_env->prefix_found = 0;
3649 inst_env->xflag_found = 0;
3650 inst_env->disable_interrupt = 0;
3653 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3656 quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env)
3658 unsigned long operand1;
3659 unsigned long operand2;
3661 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3662 instruction and can't have a prefix. */
3663 if (inst_env->prefix_found)
3665 inst_env->invalid = 1;
3668 /* Check if the instruction has PC as its target. */
3669 if (cris_get_operand2 (inst) == REG_PC)
3671 if (inst_env->slot_needed)
3673 inst_env->invalid = 1;
3676 /* The instruction has the PC as its target register. */
3677 operand1 = cris_get_quick_value (inst);
3678 operand2 = inst_env->reg[REG_PC];
3680 /* The quick value is signed, so check if we must do a signed extend. */
3681 if (operand1 & SIGNED_QUICK_VALUE_MASK)
3684 operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK;
3686 /* The size should now be dword. */
3687 cris_set_size_to_dword (&inst);
3689 /* Calculate the PC value after the instruction, i.e. where the
3690 breakpoint should be. */
3691 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3693 inst_env->slot_needed = 0;
3694 inst_env->prefix_found = 0;
3695 inst_env->xflag_found = 0;
3696 inst_env->disable_interrupt = 0;
3699 /* Translate op_type to a function and call it. */
3702 cris_gdb_func (enum cris_op_type op_type, unsigned short inst,
3703 inst_env_type *inst_env)
3707 case cris_not_implemented_op:
3708 not_implemented_op (inst, inst_env);
3712 abs_op (inst, inst_env);
3716 addi_op (inst, inst_env);
3720 asr_op (inst, inst_env);
3724 asrq_op (inst, inst_env);
3727 case cris_ax_ei_setf_op:
3728 ax_ei_setf_op (inst, inst_env);
3731 case cris_bdap_prefix:
3732 bdap_prefix (inst, inst_env);
3735 case cris_biap_prefix:
3736 biap_prefix (inst, inst_env);
3740 break_op (inst, inst_env);
3743 case cris_btst_nop_op:
3744 btst_nop_op (inst, inst_env);
3747 case cris_clearf_di_op:
3748 clearf_di_op (inst, inst_env);
3751 case cris_dip_prefix:
3752 dip_prefix (inst, inst_env);
3755 case cris_dstep_logshift_mstep_neg_not_op:
3756 dstep_logshift_mstep_neg_not_op (inst, inst_env);
3759 case cris_eight_bit_offset_branch_op:
3760 eight_bit_offset_branch_op (inst, inst_env);
3763 case cris_move_mem_to_reg_movem_op:
3764 move_mem_to_reg_movem_op (inst, inst_env);
3767 case cris_move_reg_to_mem_movem_op:
3768 move_reg_to_mem_movem_op (inst, inst_env);
3771 case cris_move_to_preg_op:
3772 move_to_preg_op (inst, inst_env);
3776 muls_op (inst, inst_env);
3780 mulu_op (inst, inst_env);
3783 case cris_none_reg_mode_add_sub_cmp_and_or_move_op:
3784 none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3787 case cris_none_reg_mode_clear_test_op:
3788 none_reg_mode_clear_test_op (inst, inst_env);
3791 case cris_none_reg_mode_jump_op:
3792 none_reg_mode_jump_op (inst, inst_env);
3795 case cris_none_reg_mode_move_from_preg_op:
3796 none_reg_mode_move_from_preg_op (inst, inst_env);
3799 case cris_quick_mode_add_sub_op:
3800 quick_mode_add_sub_op (inst, inst_env);
3803 case cris_quick_mode_and_cmp_move_or_op:
3804 quick_mode_and_cmp_move_or_op (inst, inst_env);
3807 case cris_quick_mode_bdap_prefix:
3808 quick_mode_bdap_prefix (inst, inst_env);
3811 case cris_reg_mode_add_sub_cmp_and_or_move_op:
3812 reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3815 case cris_reg_mode_clear_op:
3816 reg_mode_clear_op (inst, inst_env);
3819 case cris_reg_mode_jump_op:
3820 reg_mode_jump_op (inst, inst_env);
3823 case cris_reg_mode_move_from_preg_op:
3824 reg_mode_move_from_preg_op (inst, inst_env);
3827 case cris_reg_mode_test_op:
3828 reg_mode_test_op (inst, inst_env);
3832 scc_op (inst, inst_env);
3835 case cris_sixteen_bit_offset_branch_op:
3836 sixteen_bit_offset_branch_op (inst, inst_env);
3839 case cris_three_operand_add_sub_cmp_and_or_op:
3840 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3843 case cris_three_operand_bound_op:
3844 three_operand_bound_op (inst, inst_env);
3847 case cris_two_operand_bound_op:
3848 two_operand_bound_op (inst, inst_env);
3852 xor_op (inst, inst_env);
3857 /* This wrapper is to avoid cris_get_assembler being called before
3858 exec_bfd has been set. */
3861 cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info)
3863 int (*print_insn) (bfd_vma addr, struct disassemble_info *info);
3864 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3865 disassembler, even when there is no BFD. Does something like
3866 "gdb; target remote; disassmeble *0x123" work? */
3867 gdb_assert (exec_bfd != NULL);
3868 print_insn = cris_get_disassembler (exec_bfd);
3869 gdb_assert (print_insn != NULL);
3870 return print_insn (addr, info);
3873 /* Copied from <asm/elf.h>. */
3874 typedef unsigned long elf_greg_t;
3876 /* Same as user_regs_struct struct in <asm/user.h>. */
3877 #define CRISV10_ELF_NGREG 35
3878 typedef elf_greg_t elf_gregset_t[CRISV10_ELF_NGREG];
3880 #define CRISV32_ELF_NGREG 32
3881 typedef elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG];
3883 /* Unpack an elf_gregset_t into GDB's register cache. */
3886 cris_supply_gregset (struct regcache *regcache, elf_gregset_t *gregsetp)
3888 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3889 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3891 elf_greg_t *regp = *gregsetp;
3892 static char zerobuf[4] = {0};
3894 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3895 knows about the actual size of each register so that's no problem. */
3896 for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++)
3898 regcache_raw_supply (regcache, i, (char *)®p[i]);
3901 if (tdep->cris_version == 32)
3903 /* Needed to set pseudo-register PC for CRISv32. */
3904 /* FIXME: If ERP is in a delay slot at this point then the PC will
3905 be wrong. Issue a warning to alert the user. */
3906 regcache_raw_supply (regcache, gdbarch_pc_regnum (gdbarch),
3907 (char *)®p[ERP_REGNUM]);
3909 if (*(char *)®p[ERP_REGNUM] & 0x1)
3910 fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n");
3914 /* Use a local version of this function to get the correct types for
3915 regsets, until multi-arch core support is ready. */
3918 fetch_core_registers (struct regcache *regcache,
3919 char *core_reg_sect, unsigned core_reg_size,
3920 int which, CORE_ADDR reg_addr)
3922 elf_gregset_t gregset;
3927 if (core_reg_size != sizeof (elf_gregset_t)
3928 && core_reg_size != sizeof (crisv32_elf_gregset_t))
3930 warning (_("wrong size gregset struct in core file"));
3934 memcpy (&gregset, core_reg_sect, sizeof (gregset));
3935 cris_supply_gregset (regcache, &gregset);
3939 /* We've covered all the kinds of registers we know about here,
3940 so this must be something we wouldn't know what to do with
3941 anyway. Just ignore it. */
3946 static struct core_fns cris_elf_core_fns =
3948 bfd_target_elf_flavour, /* core_flavour */
3949 default_check_format, /* check_format */
3950 default_core_sniffer, /* core_sniffer */
3951 fetch_core_registers, /* core_read_registers */
3955 extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */
3958 _initialize_cris_tdep (void)
3960 static struct cmd_list_element *cris_set_cmdlist;
3961 static struct cmd_list_element *cris_show_cmdlist;
3963 struct cmd_list_element *c;
3965 gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep);
3967 /* CRIS-specific user-commands. */
3968 add_setshow_uinteger_cmd ("cris-version", class_support,
3969 &usr_cmd_cris_version,
3970 _("Set the current CRIS version."),
3971 _("Show the current CRIS version."),
3973 Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\
3976 NULL, /* FIXME: i18n: Current CRIS version is %s. */
3977 &setlist, &showlist);
3979 add_setshow_enum_cmd ("cris-mode", class_support,
3980 cris_modes, &usr_cmd_cris_mode,
3981 _("Set the current CRIS mode."),
3982 _("Show the current CRIS mode."),
3984 Set to CRIS_MODE_GURU when debugging in guru mode.\n\
3985 Makes GDB use the NRP register instead of the ERP register in certain cases."),
3987 NULL, /* FIXME: i18n: Current CRIS version is %s. */
3988 &setlist, &showlist);
3990 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support,
3991 &usr_cmd_cris_dwarf2_cfi,
3992 _("Set the usage of Dwarf-2 CFI for CRIS."),
3993 _("Show the usage of Dwarf-2 CFI for CRIS."),
3994 _("Set this to \"off\" if using gcc-cris < R59."),
3995 set_cris_dwarf2_cfi,
3996 NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI for CRIS is %d. */
3997 &setlist, &showlist);
3999 deprecated_add_core_fns (&cris_elf_core_fns);
4002 /* Prints out all target specific values. */
4005 cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
4007 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4010 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n",
4011 tdep->cris_version);
4012 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n",
4014 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
4015 tdep->cris_dwarf2_cfi);
4020 set_cris_version (char *ignore_args, int from_tty,
4021 struct cmd_list_element *c)
4023 struct gdbarch_info info;
4025 usr_cmd_cris_version_valid = 1;
4027 /* Update the current architecture, if needed. */
4028 gdbarch_info_init (&info);
4029 if (!gdbarch_update_p (info))
4030 internal_error (__FILE__, __LINE__,
4031 _("cris_gdbarch_update: failed to update architecture."));
4035 set_cris_mode (char *ignore_args, int from_tty,
4036 struct cmd_list_element *c)
4038 struct gdbarch_info info;
4040 /* Update the current architecture, if needed. */
4041 gdbarch_info_init (&info);
4042 if (!gdbarch_update_p (info))
4043 internal_error (__FILE__, __LINE__,
4044 "cris_gdbarch_update: failed to update architecture.");
4048 set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
4049 struct cmd_list_element *c)
4051 struct gdbarch_info info;
4053 /* Update the current architecture, if needed. */
4054 gdbarch_info_init (&info);
4055 if (!gdbarch_update_p (info))
4056 internal_error (__FILE__, __LINE__,
4057 _("cris_gdbarch_update: failed to update architecture."));
4060 static struct gdbarch *
4061 cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
4063 struct gdbarch *gdbarch;
4064 struct gdbarch_tdep *tdep;
4067 if (usr_cmd_cris_version_valid)
4069 /* Trust the user's CRIS version setting. */
4070 cris_version = usr_cmd_cris_version;
4072 else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32)
4078 /* Assume it's CRIS version 10. */
4082 /* Make the current settings visible to the user. */
4083 usr_cmd_cris_version = cris_version;
4085 /* Find a candidate among the list of pre-declared architectures. */
4086 for (arches = gdbarch_list_lookup_by_info (arches, &info);
4088 arches = gdbarch_list_lookup_by_info (arches->next, &info))
4090 if ((gdbarch_tdep (arches->gdbarch)->cris_version
4091 == usr_cmd_cris_version)
4092 && (gdbarch_tdep (arches->gdbarch)->cris_mode
4093 == usr_cmd_cris_mode)
4094 && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi
4095 == usr_cmd_cris_dwarf2_cfi))
4096 return arches->gdbarch;
4099 /* No matching architecture was found. Create a new one. */
4100 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
4101 gdbarch = gdbarch_alloc (&info, tdep);
4103 tdep->cris_version = usr_cmd_cris_version;
4104 tdep->cris_mode = usr_cmd_cris_mode;
4105 tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi;
4107 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
4108 switch (info.byte_order)
4110 case BFD_ENDIAN_LITTLE:
4114 case BFD_ENDIAN_BIG:
4115 internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: big endian byte order in info"));
4119 internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: unknown byte order in info"));
4122 set_gdbarch_return_value (gdbarch, cris_return_value);
4124 set_gdbarch_sp_regnum (gdbarch, 14);
4126 /* Length of ordinary registers used in push_word and a few other
4127 places. register_size() is the real way to know how big a
4130 set_gdbarch_double_bit (gdbarch, 64);
4131 /* The default definition of a long double is 2 * gdbarch_double_bit,
4132 which means we have to set this explicitly. */
4133 set_gdbarch_long_double_bit (gdbarch, 64);
4135 /* The total amount of space needed to store (in an array called registers)
4136 GDB's copy of the machine's register state. Note: We can not use
4137 cris_register_size at this point, since it relies on current_gdbarch
4139 switch (tdep->cris_version)
4147 /* Old versions; not supported. */
4148 internal_error (__FILE__, __LINE__,
4149 _("cris_gdbarch_init: unsupported CRIS version"));
4154 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
4155 P7 (32 bits), and P15 (32 bits) have been implemented. */
4156 set_gdbarch_pc_regnum (gdbarch, 15);
4157 set_gdbarch_register_type (gdbarch, cris_register_type);
4158 /* There are 32 registers (some of which may not be implemented). */
4159 set_gdbarch_num_regs (gdbarch, 32);
4160 set_gdbarch_register_name (gdbarch, cris_register_name);
4161 set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register);
4162 set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register);
4164 set_gdbarch_software_single_step (gdbarch, cris_software_single_step);
4168 /* CRIS v32. General registers R0 - R15 (32 bits), special registers
4169 P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
4170 and pseudo-register PC (32 bits). */
4171 set_gdbarch_pc_regnum (gdbarch, 32);
4172 set_gdbarch_register_type (gdbarch, crisv32_register_type);
4173 /* 32 registers + pseudo-register PC + 16 support registers. */
4174 set_gdbarch_num_regs (gdbarch, 32 + 1 + 16);
4175 set_gdbarch_register_name (gdbarch, crisv32_register_name);
4177 set_gdbarch_cannot_store_register
4178 (gdbarch, crisv32_cannot_store_register);
4179 set_gdbarch_cannot_fetch_register
4180 (gdbarch, crisv32_cannot_fetch_register);
4182 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
4184 set_gdbarch_single_step_through_delay
4185 (gdbarch, crisv32_single_step_through_delay);
4190 internal_error (__FILE__, __LINE__,
4191 _("cris_gdbarch_init: unknown CRIS version"));
4194 /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
4195 have the same ABI). */
4196 set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code);
4197 set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call);
4198 set_gdbarch_frame_align (gdbarch, cris_frame_align);
4199 set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue);
4201 /* The stack grows downward. */
4202 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4204 set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc);
4206 set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc);
4207 set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp);
4208 set_gdbarch_unwind_dummy_id (gdbarch, cris_unwind_dummy_id);
4210 if (tdep->cris_dwarf2_cfi == 1)
4212 /* Hook in the Dwarf-2 frame sniffer. */
4213 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum);
4214 dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg);
4215 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
4218 if (tdep->cris_mode != cris_mode_guru)
4220 frame_unwind_append_sniffer (gdbarch, cris_sigtramp_frame_sniffer);
4223 frame_unwind_append_sniffer (gdbarch, cris_frame_sniffer);
4224 frame_base_set_default (gdbarch, &cris_frame_base);
4226 set_solib_svr4_fetch_link_map_offsets
4227 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
4229 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
4230 disassembler, even when there is no BFD. Does something like
4231 "gdb; target remote; disassmeble *0x123" work? */
4232 set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler);