1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
3 Copyright (C) 2001-2012 Free Software Foundation, Inc.
5 Contributed by Axis Communications AB.
6 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include "frame-unwind.h"
26 #include "frame-base.h"
27 #include "trad-frame.h"
28 #include "dwarf2-frame.h"
36 #include "opcode/cris.h"
37 #include "arch-utils.h"
39 #include "gdb_assert.h"
43 #include "solib.h" /* Support for shared libraries. */
44 #include "solib-svr4.h"
45 #include "gdb_string.h"
50 /* There are no floating point registers. Used in gdbserver low-linux.c. */
53 /* There are 16 general registers. */
56 /* There are 16 special registers. */
59 /* CRISv32 has a pseudo PC register, not noted here. */
61 /* CRISv32 has 16 support registers. */
65 /* Register numbers of various important registers.
66 CRIS_FP_REGNUM Contains address of executing stack frame.
67 STR_REGNUM Contains the address of structure return values.
68 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
69 ARG1_REGNUM Contains the first parameter to a function.
70 ARG2_REGNUM Contains the second parameter to a function.
71 ARG3_REGNUM Contains the third parameter to a function.
72 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
73 gdbarch_sp_regnum Contains address of top of stack.
74 gdbarch_pc_regnum Contains address of next instruction.
75 SRP_REGNUM Subroutine return pointer register.
76 BRP_REGNUM Breakpoint return pointer register. */
80 /* Enums with respect to the general registers, valid for all
81 CRIS versions. The frame pointer is always in R8. */
83 /* ABI related registers. */
91 /* Registers which happen to be common. */
96 /* CRISv10 et al. specific registers. */
108 /* CRISv32 specific registers. */
121 CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */
123 CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */
143 extern const struct cris_spec_reg cris_spec_regs[];
145 /* CRIS version, set via the user command 'set cris-version'. Affects
146 register names and sizes. */
147 static int usr_cmd_cris_version;
149 /* Indicates whether to trust the above variable. */
150 static int usr_cmd_cris_version_valid = 0;
152 static const char cris_mode_normal[] = "normal";
153 static const char cris_mode_guru[] = "guru";
154 static const char *const cris_modes[] = {
160 /* CRIS mode, set via the user command 'set cris-mode'. Affects
161 type of break instruction among other things. */
162 static const char *usr_cmd_cris_mode = cris_mode_normal;
164 /* Whether to make use of Dwarf-2 CFI (default on). */
165 static int usr_cmd_cris_dwarf2_cfi = 1;
167 /* CRIS architecture specific information. */
171 const char *cris_mode;
175 /* Sigtramp identification code copied from i386-linux-tdep.c. */
177 #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
178 #define SIGTRAMP_OFFSET0 0
179 #define SIGTRAMP_INSN1 0xe93d /* break 13 */
180 #define SIGTRAMP_OFFSET1 4
182 static const unsigned short sigtramp_code[] =
184 SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */
185 SIGTRAMP_INSN1 /* break 13 */
188 #define SIGTRAMP_LEN (sizeof sigtramp_code)
190 /* Note: same length as normal sigtramp code. */
192 static const unsigned short rt_sigtramp_code[] =
194 SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */
195 SIGTRAMP_INSN1 /* break 13 */
198 /* If PC is in a sigtramp routine, return the address of the start of
199 the routine. Otherwise, return 0. */
202 cris_sigtramp_start (struct frame_info *this_frame)
204 CORE_ADDR pc = get_frame_pc (this_frame);
205 gdb_byte buf[SIGTRAMP_LEN];
207 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
210 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
212 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
215 pc -= SIGTRAMP_OFFSET1;
216 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
220 if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0)
226 /* If PC is in a RT sigtramp routine, return the address of the start of
227 the routine. Otherwise, return 0. */
230 cris_rt_sigtramp_start (struct frame_info *this_frame)
232 CORE_ADDR pc = get_frame_pc (this_frame);
233 gdb_byte buf[SIGTRAMP_LEN];
235 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
238 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
240 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
243 pc -= SIGTRAMP_OFFSET1;
244 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
248 if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0)
254 /* Assuming THIS_FRAME is a frame for a GNU/Linux sigtramp routine,
255 return the address of the associated sigcontext structure. */
258 cris_sigcontext_addr (struct frame_info *this_frame)
260 struct gdbarch *gdbarch = get_frame_arch (this_frame);
261 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
266 get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
267 sp = extract_unsigned_integer (buf, 4, byte_order);
269 /* Look for normal sigtramp frame first. */
270 pc = cris_sigtramp_start (this_frame);
273 /* struct signal_frame (arch/cris/kernel/signal.c) contains
274 struct sigcontext as its first member, meaning the SP points to
279 pc = cris_rt_sigtramp_start (this_frame);
282 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
283 a struct ucontext, which in turn contains a struct sigcontext.
285 4 + 4 + 128 to struct ucontext, then
286 4 + 4 + 12 to struct sigcontext. */
290 error (_("Couldn't recognize signal trampoline."));
294 struct cris_unwind_cache
296 /* The previous frame's inner most stack address. Used as this
297 frame ID's stack_addr. */
299 /* The frame's base, optionally used by the high-level debug info. */
302 /* How far the SP and r8 (FP) have been offset from the start of
303 the stack frame (as defined by the previous frame's stack
309 /* From old frame_extra_info struct. */
313 /* Table indicating the location of each and every register. */
314 struct trad_frame_saved_reg *saved_regs;
317 static struct cris_unwind_cache *
318 cris_sigtramp_frame_unwind_cache (struct frame_info *this_frame,
321 struct gdbarch *gdbarch = get_frame_arch (this_frame);
322 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
323 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
324 struct cris_unwind_cache *info;
332 return (*this_cache);
334 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
335 (*this_cache) = info;
336 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
338 /* Zero all fields. */
344 info->uses_frame = 0;
346 info->leaf_function = 0;
348 get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
349 info->base = extract_unsigned_integer (buf, 4, byte_order);
351 addr = cris_sigcontext_addr (this_frame);
353 /* Layout of the sigcontext struct:
356 unsigned long oldmask;
360 if (tdep->cris_version == 10)
362 /* R0 to R13 are stored in reverse order at offset (2 * 4) in
364 for (i = 0; i <= 13; i++)
365 info->saved_regs[i].addr = addr + ((15 - i) * 4);
367 info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4);
368 info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4);
369 info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4);
370 /* Note: IRP is off by 2 at this point. There's no point in correcting
371 it though since that will mean that the backtrace will show a PC
372 different from what is shown when stopped. */
373 info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4);
374 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
375 = info->saved_regs[IRP_REGNUM];
376 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr = addr + (24 * 4);
381 /* R0 to R13 are stored in order at offset (1 * 4) in
383 for (i = 0; i <= 13; i++)
384 info->saved_regs[i].addr = addr + ((i + 1) * 4);
386 info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4);
387 info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4);
388 info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4);
389 info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4);
390 info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4);
391 info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4);
392 info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4);
393 info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4);
394 info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4);
396 /* FIXME: If ERP is in a delay slot at this point then the PC will
397 be wrong at this point. This problem manifests itself in the
398 sigaltstack.exp test case, which occasionally generates FAILs when
399 the signal is received while in a delay slot.
401 This could be solved by a couple of read_memory_unsigned_integer and a
402 trad_frame_set_value. */
403 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
404 = info->saved_regs[ERP_REGNUM];
406 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr
414 cris_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
415 struct frame_id *this_id)
417 struct cris_unwind_cache *cache =
418 cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
419 (*this_id) = frame_id_build (cache->base, get_frame_pc (this_frame));
422 /* Forward declaration. */
424 static struct value *cris_frame_prev_register (struct frame_info *this_frame,
425 void **this_cache, int regnum);
426 static struct value *
427 cris_sigtramp_frame_prev_register (struct frame_info *this_frame,
428 void **this_cache, int regnum)
430 /* Make sure we've initialized the cache. */
431 cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
432 return cris_frame_prev_register (this_frame, this_cache, regnum);
436 cris_sigtramp_frame_sniffer (const struct frame_unwind *self,
437 struct frame_info *this_frame,
440 if (cris_sigtramp_start (this_frame)
441 || cris_rt_sigtramp_start (this_frame))
447 static const struct frame_unwind cris_sigtramp_frame_unwind =
450 default_frame_unwind_stop_reason,
451 cris_sigtramp_frame_this_id,
452 cris_sigtramp_frame_prev_register,
454 cris_sigtramp_frame_sniffer
458 crisv32_single_step_through_delay (struct gdbarch *gdbarch,
459 struct frame_info *this_frame)
461 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
465 if (tdep->cris_mode == cris_mode_guru)
466 erp = get_frame_register_unsigned (this_frame, NRP_REGNUM);
468 erp = get_frame_register_unsigned (this_frame, ERP_REGNUM);
472 /* In delay slot - check if there's a breakpoint at the preceding
474 if (breakpoint_here_p (get_frame_address_space (this_frame), erp & ~0x1))
480 /* The instruction environment needed to find single-step breakpoints. */
483 struct instruction_environment
485 unsigned long reg[NUM_GENREGS];
486 unsigned long preg[NUM_SPECREGS];
487 unsigned long branch_break_address;
488 unsigned long delay_slot_pc;
489 unsigned long prefix_value;
494 int delay_slot_pc_active;
496 int disable_interrupt;
500 /* Machine-dependencies in CRIS for opcodes. */
502 /* Instruction sizes. */
503 enum cris_instruction_sizes
510 /* Addressing modes. */
511 enum cris_addressing_modes
518 /* Prefix addressing modes. */
519 enum cris_prefix_addressing_modes
521 PREFIX_INDEX_MODE = 2,
522 PREFIX_ASSIGN_MODE = 3,
524 /* Handle immediate byte offset addressing mode prefix format. */
525 PREFIX_OFFSET_MODE = 2
528 /* Masks for opcodes. */
529 enum cris_opcode_masks
531 BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1,
532 SIGNED_EXTEND_BIT_MASK = 0x2,
533 SIGNED_BYTE_MASK = 0x80,
534 SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00,
535 SIGNED_WORD_MASK = 0x8000,
536 SIGNED_WORD_EXTEND_MASK = 0xFFFF0000,
537 SIGNED_DWORD_MASK = 0x80000000,
538 SIGNED_QUICK_VALUE_MASK = 0x20,
539 SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0
542 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
550 cris_get_operand2 (unsigned short insn)
552 return ((insn & 0xF000) >> 12);
556 cris_get_mode (unsigned short insn)
558 return ((insn & 0x0C00) >> 10);
562 cris_get_opcode (unsigned short insn)
564 return ((insn & 0x03C0) >> 6);
568 cris_get_size (unsigned short insn)
570 return ((insn & 0x0030) >> 4);
574 cris_get_operand1 (unsigned short insn)
576 return (insn & 0x000F);
579 /* Additional functions in order to handle opcodes. */
582 cris_get_quick_value (unsigned short insn)
584 return (insn & 0x003F);
588 cris_get_bdap_quick_offset (unsigned short insn)
590 return (insn & 0x00FF);
594 cris_get_branch_short_offset (unsigned short insn)
596 return (insn & 0x00FF);
600 cris_get_asr_shift_steps (unsigned long value)
602 return (value & 0x3F);
606 cris_get_clear_size (unsigned short insn)
608 return ((insn) & 0xC000);
612 cris_is_signed_extend_bit_on (unsigned short insn)
614 return (((insn) & 0x20) == 0x20);
618 cris_is_xflag_bit_on (unsigned short insn)
620 return (((insn) & 0x1000) == 0x1000);
624 cris_set_size_to_dword (unsigned short *insn)
631 cris_get_signed_offset (unsigned short insn)
633 return ((signed char) (insn & 0x00FF));
636 /* Calls an op function given the op-type, working on the insn and the
638 static void cris_gdb_func (struct gdbarch *, enum cris_op_type, unsigned short,
641 static struct gdbarch *cris_gdbarch_init (struct gdbarch_info,
642 struct gdbarch_list *);
644 static void cris_dump_tdep (struct gdbarch *, struct ui_file *);
646 static void set_cris_version (char *ignore_args, int from_tty,
647 struct cmd_list_element *c);
649 static void set_cris_mode (char *ignore_args, int from_tty,
650 struct cmd_list_element *c);
652 static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
653 struct cmd_list_element *c);
655 static CORE_ADDR cris_scan_prologue (CORE_ADDR pc,
656 struct frame_info *this_frame,
657 struct cris_unwind_cache *info);
659 static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc,
660 struct frame_info *this_frame,
661 struct cris_unwind_cache *info);
663 static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch,
664 struct frame_info *next_frame);
666 static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch,
667 struct frame_info *next_frame);
669 /* When arguments must be pushed onto the stack, they go on in reverse
670 order. The below implements a FILO (stack) to do this.
671 Copied from d10v-tdep.c. */
676 struct stack_item *prev;
680 static struct stack_item *
681 push_stack_item (struct stack_item *prev, void *contents, int len)
683 struct stack_item *si;
684 si = xmalloc (sizeof (struct stack_item));
685 si->data = xmalloc (len);
688 memcpy (si->data, contents, len);
692 static struct stack_item *
693 pop_stack_item (struct stack_item *si)
695 struct stack_item *dead = si;
702 /* Put here the code to store, into fi->saved_regs, the addresses of
703 the saved registers of frame described by FRAME_INFO. This
704 includes special registers such as pc and fp saved in special ways
705 in the stack frame. sp is even more special: the address we return
706 for it IS the sp for the next frame. */
708 static struct cris_unwind_cache *
709 cris_frame_unwind_cache (struct frame_info *this_frame,
710 void **this_prologue_cache)
712 struct gdbarch *gdbarch = get_frame_arch (this_frame);
713 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
715 struct cris_unwind_cache *info;
718 if ((*this_prologue_cache))
719 return (*this_prologue_cache);
721 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
722 (*this_prologue_cache) = info;
723 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
725 /* Zero all fields. */
731 info->uses_frame = 0;
733 info->leaf_function = 0;
735 /* Prologue analysis does the rest... */
736 if (tdep->cris_version == 32)
737 crisv32_scan_prologue (get_frame_func (this_frame), this_frame, info);
739 cris_scan_prologue (get_frame_func (this_frame), this_frame, info);
744 /* Given a GDB frame, determine the address of the calling function's
745 frame. This will be used to create a new GDB frame struct. */
748 cris_frame_this_id (struct frame_info *this_frame,
749 void **this_prologue_cache,
750 struct frame_id *this_id)
752 struct cris_unwind_cache *info
753 = cris_frame_unwind_cache (this_frame, this_prologue_cache);
758 /* The FUNC is easy. */
759 func = get_frame_func (this_frame);
761 /* Hopefully the prologue analysis either correctly determined the
762 frame's base (which is the SP from the previous frame), or set
763 that base to "NULL". */
764 base = info->prev_sp;
768 id = frame_id_build (base, func);
773 static struct value *
774 cris_frame_prev_register (struct frame_info *this_frame,
775 void **this_prologue_cache, int regnum)
777 struct cris_unwind_cache *info
778 = cris_frame_unwind_cache (this_frame, this_prologue_cache);
779 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
782 /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
783 frame. The frame ID's base needs to match the TOS value saved by
784 save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */
786 static struct frame_id
787 cris_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
790 sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
791 return frame_id_build (sp, get_frame_pc (this_frame));
795 cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
797 /* Align to the size of an instruction (so that they can safely be
798 pushed onto the stack). */
803 cris_push_dummy_code (struct gdbarch *gdbarch,
804 CORE_ADDR sp, CORE_ADDR funaddr,
805 struct value **args, int nargs,
806 struct type *value_type,
807 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
808 struct regcache *regcache)
810 /* Allocate space sufficient for a breakpoint. */
812 /* Store the address of that breakpoint */
814 /* CRIS always starts the call at the callee's entry point. */
820 cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
821 struct regcache *regcache, CORE_ADDR bp_addr,
822 int nargs, struct value **args, CORE_ADDR sp,
823 int struct_return, CORE_ADDR struct_addr)
825 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
833 /* The function's arguments and memory allocated by gdb for the arguments to
834 point at reside in separate areas on the stack.
835 Both frame pointers grow toward higher addresses. */
839 struct stack_item *si = NULL;
841 /* Push the return address. */
842 regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr);
844 /* Are we returning a value using a structure return or a normal value
845 return? struct_addr is the address of the reserved space for the return
846 structure to be written on the stack. */
849 regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr);
852 /* Now load as many as possible of the first arguments into registers,
853 and push the rest onto the stack. */
854 argreg = ARG1_REGNUM;
857 for (argnum = 0; argnum < nargs; argnum++)
864 len = TYPE_LENGTH (value_type (args[argnum]));
865 val = (char *) value_contents (args[argnum]);
867 /* How may registers worth of storage do we need for this argument? */
868 reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0);
870 if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM))
872 /* Data passed by value. Fits in available register(s). */
873 for (i = 0; i < reg_demand; i++)
875 regcache_cooked_write (regcache, argreg, val);
880 else if (len <= (2 * 4) && argreg <= ARG4_REGNUM)
882 /* Data passed by value. Does not fit in available register(s).
883 Use the register(s) first, then the stack. */
884 for (i = 0; i < reg_demand; i++)
886 if (argreg <= ARG4_REGNUM)
888 regcache_cooked_write (regcache, argreg, val);
894 /* Push item for later so that pushed arguments
895 come in the right order. */
896 si = push_stack_item (si, val, 4);
901 else if (len > (2 * 4))
903 /* Data passed by reference. Push copy of data onto stack
904 and pass pointer to this copy as argument. */
905 sp = (sp - len) & ~3;
906 write_memory (sp, val, len);
908 if (argreg <= ARG4_REGNUM)
910 regcache_cooked_write_unsigned (regcache, argreg, sp);
916 store_unsigned_integer (buf, 4, byte_order, sp);
917 si = push_stack_item (si, buf, 4);
922 /* Data passed by value. No available registers. Put it on
924 si = push_stack_item (si, val, len);
930 /* fp_arg must be word-aligned (i.e., don't += len) to match
931 the function prologue. */
932 sp = (sp - si->len) & ~3;
933 write_memory (sp, si->data, si->len);
934 si = pop_stack_item (si);
937 /* Finally, update the SP register. */
938 regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp);
943 static const struct frame_unwind cris_frame_unwind =
946 default_frame_unwind_stop_reason,
948 cris_frame_prev_register,
950 default_frame_sniffer
954 cris_frame_base_address (struct frame_info *this_frame, void **this_cache)
956 struct cris_unwind_cache *info
957 = cris_frame_unwind_cache (this_frame, this_cache);
961 static const struct frame_base cris_frame_base =
964 cris_frame_base_address,
965 cris_frame_base_address,
966 cris_frame_base_address
969 /* Frames information. The definition of the struct frame_info is
973 enum frame_type type;
977 If the compilation option -fno-omit-frame-pointer is present the
978 variable frame will be set to the content of R8 which is the frame
981 The variable pc contains the address where execution is performed
982 in the present frame. The innermost frame contains the current content
983 of the register PC. All other frames contain the content of the
984 register PC in the next frame.
986 The variable `type' indicates the frame's type: normal, SIGTRAMP
987 (associated with a signal handler), dummy (associated with a dummy
990 The variable return_pc contains the address where execution should be
991 resumed when the present frame has finished, the return address.
993 The variable leaf_function is 1 if the return address is in the register
994 SRP, and 0 if it is on the stack.
996 Prologue instructions C-code.
997 The prologue may consist of (-fno-omit-frame-pointer)
1001 move.d sp,r8 move.d sp,r8
1003 movem rY,[sp] movem rY,[sp]
1004 move.S rZ,[r8-U] move.S rZ,[r8-U]
1006 where 1 is a non-terminal function, and 2 is a leaf-function.
1008 Note that this assumption is extremely brittle, and will break at the
1009 slightest change in GCC's prologue.
1011 If local variables are declared or register contents are saved on stack
1012 the subq-instruction will be present with X as the number of bytes
1013 needed for storage. The reshuffle with respect to r8 may be performed
1014 with any size S (b, w, d) and any of the general registers Z={0..13}.
1015 The offset U should be representable by a signed 8-bit value in all cases.
1016 Thus, the prefix word is assumed to be immediate byte offset mode followed
1017 by another word containing the instruction.
1026 Prologue instructions C++-code.
1027 Case 1) and 2) in the C-code may be followed by
1029 move.d r10,rS ; this
1033 move.S [r8+U],rZ ; P4
1035 if any of the call parameters are stored. The host expects these
1036 instructions to be executed in order to get the call parameters right. */
1038 /* Examine the prologue of a function. The variable ip is the address of
1039 the first instruction of the prologue. The variable limit is the address
1040 of the first instruction after the prologue. The variable fi contains the
1041 information in struct frame_info. The variable frameless_p controls whether
1042 the entire prologue is examined (0) or just enough instructions to
1043 determine that it is a prologue (1). */
1046 cris_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
1047 struct cris_unwind_cache *info)
1049 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1050 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1052 /* Present instruction. */
1053 unsigned short insn;
1055 /* Next instruction, lookahead. */
1056 unsigned short insn_next;
1059 /* Is there a push fp? */
1062 /* Number of byte on stack used for local variables and movem. */
1065 /* Highest register number in a movem. */
1068 /* move.d r<source_register>,rS */
1069 short source_register;
1074 /* This frame is with respect to a leaf until a push srp is found. */
1077 info->leaf_function = 1;
1080 /* Assume nothing on stack. */
1084 /* If we were called without a this_frame, that means we were called
1085 from cris_skip_prologue which already tried to find the end of the
1086 prologue through the symbol information. 64 instructions past current
1087 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
1088 limit = this_frame ? get_frame_pc (this_frame) : pc + 64;
1090 /* Find the prologue instructions. */
1091 while (pc > 0 && pc < limit)
1093 insn = read_memory_unsigned_integer (pc, 2, byte_order);
1097 /* push <reg> 32 bit instruction. */
1098 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1100 regno = cris_get_operand2 (insn_next);
1103 info->sp_offset += 4;
1105 /* This check, meant to recognize srp, used to be regno ==
1106 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
1107 if (insn_next == 0xBE7E)
1111 info->leaf_function = 0;
1114 else if (insn_next == 0x8FEE)
1119 info->r8_offset = info->sp_offset;
1123 else if (insn == 0x866E)
1128 info->uses_frame = 1;
1132 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1133 && cris_get_mode (insn) == 0x0000
1134 && cris_get_opcode (insn) == 0x000A)
1139 info->sp_offset += cris_get_quick_value (insn);
1142 else if (cris_get_mode (insn) == 0x0002
1143 && cris_get_opcode (insn) == 0x000F
1144 && cris_get_size (insn) == 0x0003
1145 && cris_get_operand1 (insn) == gdbarch_sp_regnum (gdbarch))
1147 /* movem r<regsave>,[sp] */
1148 regsave = cris_get_operand2 (insn);
1150 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1151 && ((insn & 0x0F00) >> 8) == 0x0001
1152 && (cris_get_signed_offset (insn) < 0))
1154 /* Immediate byte offset addressing prefix word with sp as base
1155 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1156 is between 64 and 128.
1157 movem r<regsave>,[sp=sp-<val>] */
1160 info->sp_offset += -cris_get_signed_offset (insn);
1162 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1164 if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE
1165 && cris_get_opcode (insn_next) == 0x000F
1166 && cris_get_size (insn_next) == 0x0003
1167 && cris_get_operand1 (insn_next) == gdbarch_sp_regnum
1170 regsave = cris_get_operand2 (insn_next);
1174 /* The prologue ended before the limit was reached. */
1179 else if (cris_get_mode (insn) == 0x0001
1180 && cris_get_opcode (insn) == 0x0009
1181 && cris_get_size (insn) == 0x0002)
1183 /* move.d r<10..13>,r<0..15> */
1184 source_register = cris_get_operand1 (insn);
1186 /* FIXME? In the glibc solibs, the prologue might contain something
1187 like (this example taken from relocate_doit):
1189 sub.d 0xfffef426,$r0
1190 which isn't covered by the source_register check below. Question
1191 is whether to add a check for this combo, or make better use of
1192 the limit variable instead. */
1193 if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM)
1195 /* The prologue ended before the limit was reached. */
1200 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1201 /* The size is a fixed-size. */
1202 && ((insn & 0x0F00) >> 8) == 0x0001
1203 /* A negative offset. */
1204 && (cris_get_signed_offset (insn) < 0))
1206 /* move.S rZ,[r8-U] (?) */
1207 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1209 regno = cris_get_operand2 (insn_next);
1210 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1211 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1212 && cris_get_opcode (insn_next) == 0x000F)
1214 /* move.S rZ,[r8-U] */
1219 /* The prologue ended before the limit was reached. */
1224 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1225 /* The size is a fixed-size. */
1226 && ((insn & 0x0F00) >> 8) == 0x0001
1227 /* A positive offset. */
1228 && (cris_get_signed_offset (insn) > 0))
1230 /* move.S [r8+U],rZ (?) */
1231 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1233 regno = cris_get_operand2 (insn_next);
1234 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1235 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1236 && cris_get_opcode (insn_next) == 0x0009
1237 && cris_get_operand1 (insn_next) == regno)
1239 /* move.S [r8+U],rZ */
1244 /* The prologue ended before the limit was reached. */
1251 /* The prologue ended before the limit was reached. */
1257 /* We only want to know the end of the prologue when this_frame and info
1258 are NULL (called from cris_skip_prologue i.e.). */
1259 if (this_frame == NULL && info == NULL)
1264 info->size = info->sp_offset;
1266 /* Compute the previous frame's stack pointer (which is also the
1267 frame's ID's stack address), and this frame's base pointer. */
1268 if (info->uses_frame)
1271 /* The SP was moved to the FP. This indicates that a new frame
1272 was created. Get THIS frame's FP value by unwinding it from
1274 this_base = get_frame_register_unsigned (this_frame, CRIS_FP_REGNUM);
1275 info->base = this_base;
1276 info->saved_regs[CRIS_FP_REGNUM].addr = info->base;
1278 /* The FP points at the last saved register. Adjust the FP back
1279 to before the first saved register giving the SP. */
1280 info->prev_sp = info->base + info->r8_offset;
1285 /* Assume that the FP is this frame's SP but with that pushed
1286 stack space added back. */
1287 this_base = get_frame_register_unsigned (this_frame,
1288 gdbarch_sp_regnum (gdbarch));
1289 info->base = this_base;
1290 info->prev_sp = info->base + info->size;
1293 /* Calculate the addresses for the saved registers on the stack. */
1294 /* FIXME: The address calculation should really be done on the fly while
1295 we're analyzing the prologue (we only hold one regsave value as it is
1297 val = info->sp_offset;
1299 for (regno = regsave; regno >= 0; regno--)
1301 info->saved_regs[regno].addr = info->base + info->r8_offset - val;
1305 /* The previous frame's SP needed to be computed. Save the computed
1307 trad_frame_set_value (info->saved_regs,
1308 gdbarch_sp_regnum (gdbarch), info->prev_sp);
1310 if (!info->leaf_function)
1312 /* SRP saved on the stack. But where? */
1313 if (info->r8_offset == 0)
1315 /* R8 not pushed yet. */
1316 info->saved_regs[SRP_REGNUM].addr = info->base;
1320 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1321 info->saved_regs[SRP_REGNUM].addr = info->base + 4;
1325 /* The PC is found in SRP (the actual register or located on the stack). */
1326 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1327 = info->saved_regs[SRP_REGNUM];
1333 crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
1334 struct cris_unwind_cache *info)
1336 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1339 /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not
1340 meant to be a full-fledged prologue scanner. It is only needed for
1341 the cases where we end up in code always lacking DWARF-2 CFI, notably:
1343 * PLT stubs (library calls)
1345 * signal trampolines
1347 For those cases, it is assumed that there is no actual prologue; that
1348 the stack pointer is not adjusted, and (as a consequence) the return
1349 address is not pushed onto the stack. */
1351 /* We only want to know the end of the prologue when this_frame and info
1352 are NULL (called from cris_skip_prologue i.e.). */
1353 if (this_frame == NULL && info == NULL)
1358 /* The SP is assumed to be unaltered. */
1359 this_base = get_frame_register_unsigned (this_frame,
1360 gdbarch_sp_regnum (gdbarch));
1361 info->base = this_base;
1362 info->prev_sp = this_base;
1364 /* The PC is assumed to be found in SRP. */
1365 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1366 = info->saved_regs[SRP_REGNUM];
1371 /* Advance pc beyond any function entry prologue instructions at pc
1372 to reach some "real" code. */
1374 /* Given a PC value corresponding to the start of a function, return the PC
1375 of the first instruction after the function prologue. */
1378 cris_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1380 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1381 CORE_ADDR func_addr, func_end;
1382 struct symtab_and_line sal;
1383 CORE_ADDR pc_after_prologue;
1385 /* If we have line debugging information, then the end of the prologue
1386 should the first assembly instruction of the first source line. */
1387 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1389 sal = find_pc_line (func_addr, 0);
1390 if (sal.end > 0 && sal.end < func_end)
1394 if (tdep->cris_version == 32)
1395 pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL);
1397 pc_after_prologue = cris_scan_prologue (pc, NULL, NULL);
1399 return pc_after_prologue;
1403 cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1406 pc = frame_unwind_register_unsigned (next_frame,
1407 gdbarch_pc_regnum (gdbarch));
1412 cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1415 sp = frame_unwind_register_unsigned (next_frame,
1416 gdbarch_sp_regnum (gdbarch));
1420 /* Use the program counter to determine the contents and size of a breakpoint
1421 instruction. It returns a pointer to a string of bytes that encode a
1422 breakpoint instruction, stores the length of the string to *lenptr, and
1423 adjusts pcptr (if necessary) to point to the actual memory location where
1424 the breakpoint should be inserted. */
1426 static const unsigned char *
1427 cris_breakpoint_from_pc (struct gdbarch *gdbarch,
1428 CORE_ADDR *pcptr, int *lenptr)
1430 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1431 static unsigned char break8_insn[] = {0x38, 0xe9};
1432 static unsigned char break15_insn[] = {0x3f, 0xe9};
1435 if (tdep->cris_mode == cris_mode_guru)
1436 return break15_insn;
1441 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1445 cris_spec_reg_applicable (struct gdbarch *gdbarch,
1446 struct cris_spec_reg spec_reg)
1448 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1449 int version = tdep->cris_version;
1451 switch (spec_reg.applicable_version)
1453 case cris_ver_version_all:
1455 case cris_ver_warning:
1456 /* Indeterminate/obsolete. */
1459 return (version >= 0 && version <= 3);
1461 return (version >= 3);
1463 return (version == 8 || version == 9);
1465 return (version >= 8);
1466 case cris_ver_v0_10:
1467 return (version >= 0 && version <= 10);
1468 case cris_ver_v3_10:
1469 return (version >= 3 && version <= 10);
1470 case cris_ver_v8_10:
1471 return (version >= 8 && version <= 10);
1473 return (version == 10);
1475 return (version >= 10);
1477 return (version >= 32);
1479 /* Invalid cris version. */
1484 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1485 register, -1 for an invalid register. */
1488 cris_register_size (struct gdbarch *gdbarch, int regno)
1490 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1494 if (regno >= 0 && regno < NUM_GENREGS)
1496 /* General registers (R0 - R15) are 32 bits. */
1499 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1501 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1502 Adjust regno accordingly. */
1503 spec_regno = regno - NUM_GENREGS;
1505 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1507 if (cris_spec_regs[i].number == spec_regno
1508 && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i]))
1509 /* Go with the first applicable register. */
1510 return cris_spec_regs[i].reg_size;
1512 /* Special register not applicable to this CRIS version. */
1515 else if (regno >= gdbarch_pc_regnum (gdbarch)
1516 && regno < gdbarch_num_regs (gdbarch))
1518 /* This will apply to CRISv32 only where there are additional registers
1519 after the special registers (pseudo PC and support registers). */
1527 /* Nonzero if regno should not be fetched from the target. This is the case
1528 for unimplemented (size 0) and non-existant registers. */
1531 cris_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1533 return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1534 || (cris_register_size (gdbarch, regno) == 0));
1537 /* Nonzero if regno should not be written to the target, for various
1541 cris_cannot_store_register (struct gdbarch *gdbarch, int regno)
1543 /* There are three kinds of registers we refuse to write to.
1544 1. Those that not implemented.
1545 2. Those that are read-only (depends on the processor mode).
1546 3. Those registers to which a write has no effect. */
1549 || regno >= gdbarch_num_regs (gdbarch)
1550 || cris_register_size (gdbarch, regno) == 0)
1551 /* Not implemented. */
1554 else if (regno == VR_REGNUM)
1558 else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM)
1559 /* Writing has no effect. */
1562 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
1563 agent decide whether they are writable. */
1568 /* Nonzero if regno should not be fetched from the target. This is the case
1569 for unimplemented (size 0) and non-existant registers. */
1572 crisv32_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1574 return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1575 || (cris_register_size (gdbarch, regno) == 0));
1578 /* Nonzero if regno should not be written to the target, for various
1582 crisv32_cannot_store_register (struct gdbarch *gdbarch, int regno)
1584 /* There are three kinds of registers we refuse to write to.
1585 1. Those that not implemented.
1586 2. Those that are read-only (depends on the processor mode).
1587 3. Those registers to which a write has no effect. */
1590 || regno >= gdbarch_num_regs (gdbarch)
1591 || cris_register_size (gdbarch, regno) == 0)
1592 /* Not implemented. */
1595 else if (regno == VR_REGNUM)
1599 else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM)
1600 /* Writing has no effect. */
1603 /* Many special registers are read-only in user mode. Let the debug
1604 agent decide whether they are writable. */
1609 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1610 of data in register regno. */
1612 static struct type *
1613 cris_register_type (struct gdbarch *gdbarch, int regno)
1615 if (regno == gdbarch_pc_regnum (gdbarch))
1616 return builtin_type (gdbarch)->builtin_func_ptr;
1617 else if (regno == gdbarch_sp_regnum (gdbarch)
1618 || regno == CRIS_FP_REGNUM)
1619 return builtin_type (gdbarch)->builtin_data_ptr;
1620 else if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1621 || (regno >= MOF_REGNUM && regno <= USP_REGNUM))
1622 /* Note: R8 taken care of previous clause. */
1623 return builtin_type (gdbarch)->builtin_uint32;
1624 else if (regno >= P4_REGNUM && regno <= CCR_REGNUM)
1625 return builtin_type (gdbarch)->builtin_uint16;
1626 else if (regno >= P0_REGNUM && regno <= VR_REGNUM)
1627 return builtin_type (gdbarch)->builtin_uint8;
1629 /* Invalid (unimplemented) register. */
1630 return builtin_type (gdbarch)->builtin_int0;
1633 static struct type *
1634 crisv32_register_type (struct gdbarch *gdbarch, int regno)
1636 if (regno == gdbarch_pc_regnum (gdbarch))
1637 return builtin_type (gdbarch)->builtin_func_ptr;
1638 else if (regno == gdbarch_sp_regnum (gdbarch)
1639 || regno == CRIS_FP_REGNUM)
1640 return builtin_type (gdbarch)->builtin_data_ptr;
1641 else if ((regno >= 0 && regno <= ACR_REGNUM)
1642 || (regno >= EXS_REGNUM && regno <= SPC_REGNUM)
1643 || (regno == PID_REGNUM)
1644 || (regno >= S0_REGNUM && regno <= S15_REGNUM))
1645 /* Note: R8 and SP taken care of by previous clause. */
1646 return builtin_type (gdbarch)->builtin_uint32;
1647 else if (regno == WZ_REGNUM)
1648 return builtin_type (gdbarch)->builtin_uint16;
1649 else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM)
1650 return builtin_type (gdbarch)->builtin_uint8;
1653 /* Invalid (unimplemented) register. Should not happen as there are
1654 no unimplemented CRISv32 registers. */
1655 warning (_("crisv32_register_type: unknown regno %d"), regno);
1656 return builtin_type (gdbarch)->builtin_int0;
1660 /* Stores a function return value of type type, where valbuf is the address
1661 of the value to be stored. */
1663 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1666 cris_store_return_value (struct type *type, struct regcache *regcache,
1669 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1670 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1672 int len = TYPE_LENGTH (type);
1676 /* Put the return value in R10. */
1677 val = extract_unsigned_integer (valbuf, len, byte_order);
1678 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1682 /* Put the return value in R10 and R11. */
1683 val = extract_unsigned_integer (valbuf, 4, byte_order);
1684 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1685 val = extract_unsigned_integer ((char *)valbuf + 4, len - 4, byte_order);
1686 regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val);
1689 error (_("cris_store_return_value: type length too large."));
1692 /* Return the name of register regno as a string. Return NULL for an
1693 invalid or unimplemented register. */
1696 cris_special_register_name (struct gdbarch *gdbarch, int regno)
1701 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1702 Adjust regno accordingly. */
1703 spec_regno = regno - NUM_GENREGS;
1705 /* Assume nothing about the layout of the cris_spec_regs struct
1707 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1709 if (cris_spec_regs[i].number == spec_regno
1710 && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i]))
1711 /* Go with the first applicable register. */
1712 return cris_spec_regs[i].name;
1714 /* Special register not applicable to this CRIS version. */
1719 cris_register_name (struct gdbarch *gdbarch, int regno)
1721 static char *cris_genreg_names[] =
1722 { "r0", "r1", "r2", "r3", \
1723 "r4", "r5", "r6", "r7", \
1724 "r8", "r9", "r10", "r11", \
1725 "r12", "r13", "sp", "pc" };
1727 if (regno >= 0 && regno < NUM_GENREGS)
1729 /* General register. */
1730 return cris_genreg_names[regno];
1732 else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (gdbarch))
1734 return cris_special_register_name (gdbarch, regno);
1738 /* Invalid register. */
1744 crisv32_register_name (struct gdbarch *gdbarch, int regno)
1746 static char *crisv32_genreg_names[] =
1747 { "r0", "r1", "r2", "r3", \
1748 "r4", "r5", "r6", "r7", \
1749 "r8", "r9", "r10", "r11", \
1750 "r12", "r13", "sp", "acr"
1753 static char *crisv32_sreg_names[] =
1754 { "s0", "s1", "s2", "s3", \
1755 "s4", "s5", "s6", "s7", \
1756 "s8", "s9", "s10", "s11", \
1757 "s12", "s13", "s14", "s15"
1760 if (regno >= 0 && regno < NUM_GENREGS)
1762 /* General register. */
1763 return crisv32_genreg_names[regno];
1765 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1767 return cris_special_register_name (gdbarch, regno);
1769 else if (regno == gdbarch_pc_regnum (gdbarch))
1773 else if (regno >= S0_REGNUM && regno <= S15_REGNUM)
1775 return crisv32_sreg_names[regno - S0_REGNUM];
1779 /* Invalid register. */
1784 /* Convert DWARF register number REG to the appropriate register
1785 number used by GDB. */
1788 cris_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1790 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1791 numbering, MOF is 18).
1792 Adapted from gcc/config/cris/cris.h. */
1793 static int cris_dwarf_regmap[] = {
1805 if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap))
1806 regnum = cris_dwarf_regmap[reg];
1809 warning (_("Unmapped DWARF Register #%d encountered."), reg);
1814 /* DWARF-2 frame support. */
1817 cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1818 struct dwarf2_frame_state_reg *reg,
1819 struct frame_info *this_frame)
1821 /* The return address column. */
1822 if (regnum == gdbarch_pc_regnum (gdbarch))
1823 reg->how = DWARF2_FRAME_REG_RA;
1825 /* The call frame address. */
1826 else if (regnum == gdbarch_sp_regnum (gdbarch))
1827 reg->how = DWARF2_FRAME_REG_CFA;
1830 /* Extract from an array regbuf containing the raw register state a function
1831 return value of type type, and copy that, in virtual format, into
1834 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1837 cris_extract_return_value (struct type *type, struct regcache *regcache,
1840 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1841 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1843 int len = TYPE_LENGTH (type);
1847 /* Get the return value from R10. */
1848 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1849 store_unsigned_integer (valbuf, len, byte_order, val);
1853 /* Get the return value from R10 and R11. */
1854 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1855 store_unsigned_integer (valbuf, 4, byte_order, val);
1856 regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val);
1857 store_unsigned_integer ((char *)valbuf + 4, len - 4, byte_order, val);
1860 error (_("cris_extract_return_value: type length too large"));
1863 /* Handle the CRIS return value convention. */
1865 static enum return_value_convention
1866 cris_return_value (struct gdbarch *gdbarch, struct type *func_type,
1867 struct type *type, struct regcache *regcache,
1868 gdb_byte *readbuf, const gdb_byte *writebuf)
1870 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1871 || TYPE_CODE (type) == TYPE_CODE_UNION
1872 || TYPE_LENGTH (type) > 8)
1873 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1874 goes on the stack. */
1875 return RETURN_VALUE_STRUCT_CONVENTION;
1878 cris_extract_return_value (type, regcache, readbuf);
1880 cris_store_return_value (type, regcache, writebuf);
1882 return RETURN_VALUE_REGISTER_CONVENTION;
1885 /* Calculates a value that measures how good inst_args constraints an
1886 instruction. It stems from cris_constraint, found in cris-dis.c. */
1889 constraint (unsigned int insn, const signed char *inst_args,
1890 inst_env_type *inst_env)
1895 const char *s = inst_args;
1901 if ((insn & 0x30) == 0x30)
1906 /* A prefix operand. */
1907 if (inst_env->prefix_found)
1913 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1914 valid "push" size. In case of special register, it may be != 4. */
1915 if (inst_env->prefix_found)
1921 retval = (((insn >> 0xC) & 0xF) == (insn & 0xF));
1929 tmp = (insn >> 0xC) & 0xF;
1931 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1933 /* Since we match four bits, we will give a value of
1934 4 - 1 = 3 in a match. If there is a corresponding
1935 exact match of a special register in another pattern, it
1936 will get a value of 4, which will be higher. This should
1937 be correct in that an exact pattern would match better that
1939 Note that there is a reason for not returning zero; the
1940 pattern for "clear" is partly matched in the bit-pattern
1941 (the two lower bits must be zero), while the bit-pattern
1942 for a move from a special register is matched in the
1943 register constraint.
1944 This also means we will will have a race condition if
1945 there is a partly match in three bits in the bit pattern. */
1946 if (tmp == cris_spec_regs[i].number)
1953 if (cris_spec_regs[i].name == NULL)
1960 /* Returns the number of bits set in the variable value. */
1963 number_of_bits (unsigned int value)
1965 int number_of_bits = 0;
1969 number_of_bits += 1;
1970 value &= (value - 1);
1972 return number_of_bits;
1975 /* Finds the address that should contain the single step breakpoint(s).
1976 It stems from code in cris-dis.c. */
1979 find_cris_op (unsigned short insn, inst_env_type *inst_env)
1982 int max_level_of_match = -1;
1983 int max_matched = -1;
1986 for (i = 0; cris_opcodes[i].name != NULL; i++)
1988 if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match)
1989 && ((cris_opcodes[i].lose & insn) == 0)
1990 /* Only CRISv10 instructions, please. */
1991 && (cris_opcodes[i].applicable_version != cris_ver_v32p))
1993 level_of_match = constraint (insn, cris_opcodes[i].args, inst_env);
1994 if (level_of_match >= 0)
1997 number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose);
1998 if (level_of_match > max_level_of_match)
2001 max_level_of_match = level_of_match;
2002 if (level_of_match == 16)
2004 /* All bits matched, cannot find better. */
2014 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
2015 actually an internal error. */
2018 find_step_target (struct frame_info *frame, inst_env_type *inst_env)
2022 unsigned short insn;
2023 struct gdbarch *gdbarch = get_frame_arch (frame);
2024 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2026 /* Create a local register image and set the initial state. */
2027 for (i = 0; i < NUM_GENREGS; i++)
2030 (unsigned long) get_frame_register_unsigned (frame, i);
2032 offset = NUM_GENREGS;
2033 for (i = 0; i < NUM_SPECREGS; i++)
2036 (unsigned long) get_frame_register_unsigned (frame, offset + i);
2038 inst_env->branch_found = 0;
2039 inst_env->slot_needed = 0;
2040 inst_env->delay_slot_pc_active = 0;
2041 inst_env->prefix_found = 0;
2042 inst_env->invalid = 0;
2043 inst_env->xflag_found = 0;
2044 inst_env->disable_interrupt = 0;
2045 inst_env->byte_order = byte_order;
2047 /* Look for a step target. */
2050 /* Read an instruction from the client. */
2051 insn = read_memory_unsigned_integer
2052 (inst_env->reg[gdbarch_pc_regnum (gdbarch)], 2, byte_order);
2054 /* If the instruction is not in a delay slot the new content of the
2055 PC is [PC] + 2. If the instruction is in a delay slot it is not
2056 that simple. Since a instruction in a delay slot cannot change
2057 the content of the PC, it does not matter what value PC will have.
2058 Just make sure it is a valid instruction. */
2059 if (!inst_env->delay_slot_pc_active)
2061 inst_env->reg[gdbarch_pc_regnum (gdbarch)] += 2;
2065 inst_env->delay_slot_pc_active = 0;
2066 inst_env->reg[gdbarch_pc_regnum (gdbarch)]
2067 = inst_env->delay_slot_pc;
2069 /* Analyse the present instruction. */
2070 i = find_cris_op (insn, inst_env);
2073 inst_env->invalid = 1;
2077 cris_gdb_func (gdbarch, cris_opcodes[i].op, insn, inst_env);
2079 } while (!inst_env->invalid
2080 && (inst_env->prefix_found || inst_env->xflag_found
2081 || inst_env->slot_needed));
2085 /* There is no hardware single-step support. The function find_step_target
2086 digs through the opcodes in order to find all possible targets.
2087 Either one ordinary target or two targets for branches may be found. */
2090 cris_software_single_step (struct frame_info *frame)
2092 struct gdbarch *gdbarch = get_frame_arch (frame);
2093 struct address_space *aspace = get_frame_address_space (frame);
2094 inst_env_type inst_env;
2096 /* Analyse the present instruction environment and insert
2098 int status = find_step_target (frame, &inst_env);
2101 /* Could not find a target. Things are likely to go downhill
2103 warning (_("CRIS software single step could not find a step target."));
2107 /* Insert at most two breakpoints. One for the next PC content
2108 and possibly another one for a branch, jump, etc. */
2110 = (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (gdbarch)];
2111 insert_single_step_breakpoint (gdbarch, aspace, next_pc);
2112 if (inst_env.branch_found
2113 && (CORE_ADDR) inst_env.branch_break_address != next_pc)
2115 CORE_ADDR branch_target_address
2116 = (CORE_ADDR) inst_env.branch_break_address;
2117 insert_single_step_breakpoint (gdbarch,
2118 aspace, branch_target_address);
2125 /* Calculates the prefix value for quick offset addressing mode. */
2128 quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2130 /* It's invalid to be in a delay slot. You can't have a prefix to this
2131 instruction (not 100% sure). */
2132 if (inst_env->slot_needed || inst_env->prefix_found)
2134 inst_env->invalid = 1;
2138 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2139 inst_env->prefix_value += cris_get_bdap_quick_offset (inst);
2141 /* A prefix doesn't change the xflag_found. But the rest of the flags
2143 inst_env->slot_needed = 0;
2144 inst_env->prefix_found = 1;
2147 /* Updates the autoincrement register. The size of the increment is derived
2148 from the size of the operation. The PC is always kept aligned on even
2152 process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env)
2154 if (size == INST_BYTE_SIZE)
2156 inst_env->reg[cris_get_operand1 (inst)] += 1;
2158 /* The PC must be word aligned, so increase the PC with one
2159 word even if the size is byte. */
2160 if (cris_get_operand1 (inst) == REG_PC)
2162 inst_env->reg[REG_PC] += 1;
2165 else if (size == INST_WORD_SIZE)
2167 inst_env->reg[cris_get_operand1 (inst)] += 2;
2169 else if (size == INST_DWORD_SIZE)
2171 inst_env->reg[cris_get_operand1 (inst)] += 4;
2176 inst_env->invalid = 1;
2180 /* Just a forward declaration. */
2182 static unsigned long get_data_from_address (unsigned short *inst,
2184 enum bfd_endian byte_order);
2186 /* Calculates the prefix value for the general case of offset addressing
2190 bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2195 /* It's invalid to be in a delay slot. */
2196 if (inst_env->slot_needed || inst_env->prefix_found)
2198 inst_env->invalid = 1;
2202 /* The calculation of prefix_value used to be after process_autoincrement,
2203 but that fails for an instruction such as jsr [$r0+12] which is encoded
2204 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
2205 mustn't be incremented until we have read it and what it points at. */
2206 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2208 /* The offset is an indirection of the contents of the operand1 register. */
2209 inst_env->prefix_value +=
2210 get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)],
2211 inst_env->byte_order);
2213 if (cris_get_mode (inst) == AUTOINC_MODE)
2215 process_autoincrement (cris_get_size (inst), inst, inst_env);
2218 /* A prefix doesn't change the xflag_found. But the rest of the flags
2220 inst_env->slot_needed = 0;
2221 inst_env->prefix_found = 1;
2224 /* Calculates the prefix value for the index addressing mode. */
2227 biap_prefix (unsigned short inst, inst_env_type *inst_env)
2229 /* It's invalid to be in a delay slot. I can't see that it's possible to
2230 have a prefix to this instruction. So I will treat this as invalid. */
2231 if (inst_env->slot_needed || inst_env->prefix_found)
2233 inst_env->invalid = 1;
2237 inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)];
2239 /* The offset is the operand2 value shifted the size of the instruction
2241 inst_env->prefix_value +=
2242 inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst);
2244 /* If the PC is operand1 (base) the address used is the address after
2245 the main instruction, i.e. address + 2 (the PC is already compensated
2246 for the prefix operation). */
2247 if (cris_get_operand1 (inst) == REG_PC)
2249 inst_env->prefix_value += 2;
2252 /* A prefix doesn't change the xflag_found. But the rest of the flags
2254 inst_env->slot_needed = 0;
2255 inst_env->xflag_found = 0;
2256 inst_env->prefix_found = 1;
2259 /* Calculates the prefix value for the double indirect addressing mode. */
2262 dip_prefix (unsigned short inst, inst_env_type *inst_env)
2267 /* It's invalid to be in a delay slot. */
2268 if (inst_env->slot_needed || inst_env->prefix_found)
2270 inst_env->invalid = 1;
2274 /* The prefix value is one dereference of the contents of the operand1
2276 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2277 inst_env->prefix_value
2278 = read_memory_unsigned_integer (address, 4, inst_env->byte_order);
2280 /* Check if the mode is autoincrement. */
2281 if (cris_get_mode (inst) == AUTOINC_MODE)
2283 inst_env->reg[cris_get_operand1 (inst)] += 4;
2286 /* A prefix doesn't change the xflag_found. But the rest of the flags
2288 inst_env->slot_needed = 0;
2289 inst_env->xflag_found = 0;
2290 inst_env->prefix_found = 1;
2293 /* Finds the destination for a branch with 8-bits offset. */
2296 eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2301 /* If we have a prefix or are in a delay slot it's bad. */
2302 if (inst_env->slot_needed || inst_env->prefix_found)
2304 inst_env->invalid = 1;
2308 /* We have a branch, find out where the branch will land. */
2309 offset = cris_get_branch_short_offset (inst);
2311 /* Check if the offset is signed. */
2312 if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK)
2317 /* The offset ends with the sign bit, set it to zero. The address
2318 should always be word aligned. */
2319 offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK;
2321 inst_env->branch_found = 1;
2322 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2324 inst_env->slot_needed = 1;
2325 inst_env->prefix_found = 0;
2326 inst_env->xflag_found = 0;
2327 inst_env->disable_interrupt = 1;
2330 /* Finds the destination for a branch with 16-bits offset. */
2333 sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2337 /* If we have a prefix or is in a delay slot it's bad. */
2338 if (inst_env->slot_needed || inst_env->prefix_found)
2340 inst_env->invalid = 1;
2344 /* We have a branch, find out the offset for the branch. */
2345 offset = read_memory_integer (inst_env->reg[REG_PC], 2,
2346 inst_env->byte_order);
2348 /* The instruction is one word longer than normal, so add one word
2350 inst_env->reg[REG_PC] += 2;
2352 inst_env->branch_found = 1;
2353 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2356 inst_env->slot_needed = 1;
2357 inst_env->prefix_found = 0;
2358 inst_env->xflag_found = 0;
2359 inst_env->disable_interrupt = 1;
2362 /* Handles the ABS instruction. */
2365 abs_op (unsigned short inst, inst_env_type *inst_env)
2370 /* ABS can't have a prefix, so it's bad if it does. */
2371 if (inst_env->prefix_found)
2373 inst_env->invalid = 1;
2377 /* Check if the operation affects the PC. */
2378 if (cris_get_operand2 (inst) == REG_PC)
2381 /* It's invalid to change to the PC if we are in a delay slot. */
2382 if (inst_env->slot_needed)
2384 inst_env->invalid = 1;
2388 value = (long) inst_env->reg[REG_PC];
2390 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
2391 if (value != SIGNED_DWORD_MASK)
2394 inst_env->reg[REG_PC] = (long) value;
2398 inst_env->slot_needed = 0;
2399 inst_env->prefix_found = 0;
2400 inst_env->xflag_found = 0;
2401 inst_env->disable_interrupt = 0;
2404 /* Handles the ADDI instruction. */
2407 addi_op (unsigned short inst, inst_env_type *inst_env)
2409 /* It's invalid to have the PC as base register. And ADDI can't have
2411 if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC))
2413 inst_env->invalid = 1;
2417 inst_env->slot_needed = 0;
2418 inst_env->prefix_found = 0;
2419 inst_env->xflag_found = 0;
2420 inst_env->disable_interrupt = 0;
2423 /* Handles the ASR instruction. */
2426 asr_op (unsigned short inst, inst_env_type *inst_env)
2429 unsigned long value;
2430 unsigned long signed_extend_mask = 0;
2432 /* ASR can't have a prefix, so check that it doesn't. */
2433 if (inst_env->prefix_found)
2435 inst_env->invalid = 1;
2439 /* Check if the PC is the target register. */
2440 if (cris_get_operand2 (inst) == REG_PC)
2442 /* It's invalid to change the PC in a delay slot. */
2443 if (inst_env->slot_needed)
2445 inst_env->invalid = 1;
2448 /* Get the number of bits to shift. */
2450 = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]);
2451 value = inst_env->reg[REG_PC];
2453 /* Find out how many bits the operation should apply to. */
2454 if (cris_get_size (inst) == INST_BYTE_SIZE)
2456 if (value & SIGNED_BYTE_MASK)
2458 signed_extend_mask = 0xFF;
2459 signed_extend_mask = signed_extend_mask >> shift_steps;
2460 signed_extend_mask = ~signed_extend_mask;
2462 value = value >> shift_steps;
2463 value |= signed_extend_mask;
2465 inst_env->reg[REG_PC] &= 0xFFFFFF00;
2466 inst_env->reg[REG_PC] |= value;
2468 else if (cris_get_size (inst) == INST_WORD_SIZE)
2470 if (value & SIGNED_WORD_MASK)
2472 signed_extend_mask = 0xFFFF;
2473 signed_extend_mask = signed_extend_mask >> shift_steps;
2474 signed_extend_mask = ~signed_extend_mask;
2476 value = value >> shift_steps;
2477 value |= signed_extend_mask;
2479 inst_env->reg[REG_PC] &= 0xFFFF0000;
2480 inst_env->reg[REG_PC] |= value;
2482 else if (cris_get_size (inst) == INST_DWORD_SIZE)
2484 if (value & SIGNED_DWORD_MASK)
2486 signed_extend_mask = 0xFFFFFFFF;
2487 signed_extend_mask = signed_extend_mask >> shift_steps;
2488 signed_extend_mask = ~signed_extend_mask;
2490 value = value >> shift_steps;
2491 value |= signed_extend_mask;
2492 inst_env->reg[REG_PC] = value;
2495 inst_env->slot_needed = 0;
2496 inst_env->prefix_found = 0;
2497 inst_env->xflag_found = 0;
2498 inst_env->disable_interrupt = 0;
2501 /* Handles the ASRQ instruction. */
2504 asrq_op (unsigned short inst, inst_env_type *inst_env)
2508 unsigned long value;
2509 unsigned long signed_extend_mask = 0;
2511 /* ASRQ can't have a prefix, so check that it doesn't. */
2512 if (inst_env->prefix_found)
2514 inst_env->invalid = 1;
2518 /* Check if the PC is the target register. */
2519 if (cris_get_operand2 (inst) == REG_PC)
2522 /* It's invalid to change the PC in a delay slot. */
2523 if (inst_env->slot_needed)
2525 inst_env->invalid = 1;
2528 /* The shift size is given as a 5 bit quick value, i.e. we don't
2529 want the sign bit of the quick value. */
2530 shift_steps = cris_get_asr_shift_steps (inst);
2531 value = inst_env->reg[REG_PC];
2532 if (value & SIGNED_DWORD_MASK)
2534 signed_extend_mask = 0xFFFFFFFF;
2535 signed_extend_mask = signed_extend_mask >> shift_steps;
2536 signed_extend_mask = ~signed_extend_mask;
2538 value = value >> shift_steps;
2539 value |= signed_extend_mask;
2540 inst_env->reg[REG_PC] = value;
2542 inst_env->slot_needed = 0;
2543 inst_env->prefix_found = 0;
2544 inst_env->xflag_found = 0;
2545 inst_env->disable_interrupt = 0;
2548 /* Handles the AX, EI and SETF instruction. */
2551 ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env)
2553 if (inst_env->prefix_found)
2555 inst_env->invalid = 1;
2558 /* Check if the instruction is setting the X flag. */
2559 if (cris_is_xflag_bit_on (inst))
2561 inst_env->xflag_found = 1;
2565 inst_env->xflag_found = 0;
2567 inst_env->slot_needed = 0;
2568 inst_env->prefix_found = 0;
2569 inst_env->disable_interrupt = 1;
2572 /* Checks if the instruction is in assign mode. If so, it updates the assign
2573 register. Note that check_assign assumes that the caller has checked that
2574 there is a prefix to this instruction. The mode check depends on this. */
2577 check_assign (unsigned short inst, inst_env_type *inst_env)
2579 /* Check if it's an assign addressing mode. */
2580 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2582 /* Assign the prefix value to operand 1. */
2583 inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value;
2587 /* Handles the 2-operand BOUND instruction. */
2590 two_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2592 /* It's invalid to have the PC as the index operand. */
2593 if (cris_get_operand2 (inst) == REG_PC)
2595 inst_env->invalid = 1;
2598 /* Check if we have a prefix. */
2599 if (inst_env->prefix_found)
2601 check_assign (inst, inst_env);
2603 /* Check if this is an autoincrement mode. */
2604 else if (cris_get_mode (inst) == AUTOINC_MODE)
2606 /* It's invalid to change the PC in a delay slot. */
2607 if (inst_env->slot_needed)
2609 inst_env->invalid = 1;
2612 process_autoincrement (cris_get_size (inst), inst, inst_env);
2614 inst_env->slot_needed = 0;
2615 inst_env->prefix_found = 0;
2616 inst_env->xflag_found = 0;
2617 inst_env->disable_interrupt = 0;
2620 /* Handles the 3-operand BOUND instruction. */
2623 three_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2625 /* It's an error if we haven't got a prefix. And it's also an error
2626 if the PC is the destination register. */
2627 if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC))
2629 inst_env->invalid = 1;
2632 inst_env->slot_needed = 0;
2633 inst_env->prefix_found = 0;
2634 inst_env->xflag_found = 0;
2635 inst_env->disable_interrupt = 0;
2638 /* Clears the status flags in inst_env. */
2641 btst_nop_op (unsigned short inst, inst_env_type *inst_env)
2643 /* It's an error if we have got a prefix. */
2644 if (inst_env->prefix_found)
2646 inst_env->invalid = 1;
2650 inst_env->slot_needed = 0;
2651 inst_env->prefix_found = 0;
2652 inst_env->xflag_found = 0;
2653 inst_env->disable_interrupt = 0;
2656 /* Clears the status flags in inst_env. */
2659 clearf_di_op (unsigned short inst, inst_env_type *inst_env)
2661 /* It's an error if we have got a prefix. */
2662 if (inst_env->prefix_found)
2664 inst_env->invalid = 1;
2668 inst_env->slot_needed = 0;
2669 inst_env->prefix_found = 0;
2670 inst_env->xflag_found = 0;
2671 inst_env->disable_interrupt = 1;
2674 /* Handles the CLEAR instruction if it's in register mode. */
2677 reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env)
2679 /* Check if the target is the PC. */
2680 if (cris_get_operand2 (inst) == REG_PC)
2682 /* The instruction will clear the instruction's size bits. */
2683 int clear_size = cris_get_clear_size (inst);
2684 if (clear_size == INST_BYTE_SIZE)
2686 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00;
2688 if (clear_size == INST_WORD_SIZE)
2690 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000;
2692 if (clear_size == INST_DWORD_SIZE)
2694 inst_env->delay_slot_pc = 0x0;
2696 /* The jump will be delayed with one delay slot. So we need a delay
2698 inst_env->slot_needed = 1;
2699 inst_env->delay_slot_pc_active = 1;
2703 /* The PC will not change => no delay slot. */
2704 inst_env->slot_needed = 0;
2706 inst_env->prefix_found = 0;
2707 inst_env->xflag_found = 0;
2708 inst_env->disable_interrupt = 0;
2711 /* Handles the TEST instruction if it's in register mode. */
2714 reg_mode_test_op (unsigned short inst, inst_env_type *inst_env)
2716 /* It's an error if we have got a prefix. */
2717 if (inst_env->prefix_found)
2719 inst_env->invalid = 1;
2722 inst_env->slot_needed = 0;
2723 inst_env->prefix_found = 0;
2724 inst_env->xflag_found = 0;
2725 inst_env->disable_interrupt = 0;
2729 /* Handles the CLEAR and TEST instruction if the instruction isn't
2730 in register mode. */
2733 none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env)
2735 /* Check if we are in a prefix mode. */
2736 if (inst_env->prefix_found)
2738 /* The only way the PC can change is if this instruction is in
2739 assign addressing mode. */
2740 check_assign (inst, inst_env);
2742 /* Indirect mode can't change the PC so just check if the mode is
2744 else if (cris_get_mode (inst) == AUTOINC_MODE)
2746 process_autoincrement (cris_get_size (inst), inst, inst_env);
2748 inst_env->slot_needed = 0;
2749 inst_env->prefix_found = 0;
2750 inst_env->xflag_found = 0;
2751 inst_env->disable_interrupt = 0;
2754 /* Checks that the PC isn't the destination register or the instructions has
2758 dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env)
2760 /* It's invalid to have the PC as the destination. The instruction can't
2762 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2764 inst_env->invalid = 1;
2768 inst_env->slot_needed = 0;
2769 inst_env->prefix_found = 0;
2770 inst_env->xflag_found = 0;
2771 inst_env->disable_interrupt = 0;
2774 /* Checks that the instruction doesn't have a prefix. */
2777 break_op (unsigned short inst, inst_env_type *inst_env)
2779 /* The instruction can't have a prefix. */
2780 if (inst_env->prefix_found)
2782 inst_env->invalid = 1;
2786 inst_env->slot_needed = 0;
2787 inst_env->prefix_found = 0;
2788 inst_env->xflag_found = 0;
2789 inst_env->disable_interrupt = 1;
2792 /* Checks that the PC isn't the destination register and that the instruction
2793 doesn't have a prefix. */
2796 scc_op (unsigned short inst, inst_env_type *inst_env)
2798 /* It's invalid to have the PC as the destination. The instruction can't
2800 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2802 inst_env->invalid = 1;
2806 inst_env->slot_needed = 0;
2807 inst_env->prefix_found = 0;
2808 inst_env->xflag_found = 0;
2809 inst_env->disable_interrupt = 1;
2812 /* Handles the register mode JUMP instruction. */
2815 reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2817 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2818 you can't have a prefix. */
2819 if ((inst_env->slot_needed) || (inst_env->prefix_found))
2821 inst_env->invalid = 1;
2825 /* Just change the PC. */
2826 inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)];
2827 inst_env->slot_needed = 0;
2828 inst_env->prefix_found = 0;
2829 inst_env->xflag_found = 0;
2830 inst_env->disable_interrupt = 1;
2833 /* Handles the JUMP instruction for all modes except register. */
2836 none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2838 unsigned long newpc;
2841 /* It's invalid to do a JUMP in a delay slot. */
2842 if (inst_env->slot_needed)
2844 inst_env->invalid = 1;
2848 /* Check if we have a prefix. */
2849 if (inst_env->prefix_found)
2851 check_assign (inst, inst_env);
2853 /* Get the new value for the PC. */
2855 read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value,
2856 4, inst_env->byte_order);
2860 /* Get the new value for the PC. */
2861 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2862 newpc = read_memory_unsigned_integer (address,
2863 4, inst_env->byte_order);
2865 /* Check if we should increment a register. */
2866 if (cris_get_mode (inst) == AUTOINC_MODE)
2868 inst_env->reg[cris_get_operand1 (inst)] += 4;
2871 inst_env->reg[REG_PC] = newpc;
2873 inst_env->slot_needed = 0;
2874 inst_env->prefix_found = 0;
2875 inst_env->xflag_found = 0;
2876 inst_env->disable_interrupt = 1;
2879 /* Handles moves to special registers (aka P-register) for all modes. */
2882 move_to_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2883 inst_env_type *inst_env)
2885 if (inst_env->prefix_found)
2887 /* The instruction has a prefix that means we are only interested if
2888 the instruction is in assign mode. */
2889 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2891 /* The prefix handles the problem if we are in a delay slot. */
2892 if (cris_get_operand1 (inst) == REG_PC)
2894 /* Just take care of the assign. */
2895 check_assign (inst, inst_env);
2899 else if (cris_get_mode (inst) == AUTOINC_MODE)
2901 /* The instruction doesn't have a prefix, the only case left that we
2902 are interested in is the autoincrement mode. */
2903 if (cris_get_operand1 (inst) == REG_PC)
2905 /* If the PC is to be incremented it's invalid to be in a
2907 if (inst_env->slot_needed)
2909 inst_env->invalid = 1;
2913 /* The increment depends on the size of the special register. */
2914 if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
2916 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2918 else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
2920 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2924 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2928 inst_env->slot_needed = 0;
2929 inst_env->prefix_found = 0;
2930 inst_env->xflag_found = 0;
2931 inst_env->disable_interrupt = 1;
2934 /* Handles moves from special registers (aka P-register) for all modes
2938 none_reg_mode_move_from_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2939 inst_env_type *inst_env)
2941 if (inst_env->prefix_found)
2943 /* The instruction has a prefix that means we are only interested if
2944 the instruction is in assign mode. */
2945 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2947 /* The prefix handles the problem if we are in a delay slot. */
2948 if (cris_get_operand1 (inst) == REG_PC)
2950 /* Just take care of the assign. */
2951 check_assign (inst, inst_env);
2955 /* The instruction doesn't have a prefix, the only case left that we
2956 are interested in is the autoincrement mode. */
2957 else if (cris_get_mode (inst) == AUTOINC_MODE)
2959 if (cris_get_operand1 (inst) == REG_PC)
2961 /* If the PC is to be incremented it's invalid to be in a
2963 if (inst_env->slot_needed)
2965 inst_env->invalid = 1;
2969 /* The increment depends on the size of the special register. */
2970 if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
2972 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2974 else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
2976 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2980 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2984 inst_env->slot_needed = 0;
2985 inst_env->prefix_found = 0;
2986 inst_env->xflag_found = 0;
2987 inst_env->disable_interrupt = 1;
2990 /* Handles moves from special registers (aka P-register) when the mode
2994 reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env)
2996 /* Register mode move from special register can't have a prefix. */
2997 if (inst_env->prefix_found)
2999 inst_env->invalid = 1;
3003 if (cris_get_operand1 (inst) == REG_PC)
3005 /* It's invalid to change the PC in a delay slot. */
3006 if (inst_env->slot_needed)
3008 inst_env->invalid = 1;
3011 /* The destination is the PC, the jump will have a delay slot. */
3012 inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)];
3013 inst_env->slot_needed = 1;
3014 inst_env->delay_slot_pc_active = 1;
3018 /* If the destination isn't PC, there will be no jump. */
3019 inst_env->slot_needed = 0;
3021 inst_env->prefix_found = 0;
3022 inst_env->xflag_found = 0;
3023 inst_env->disable_interrupt = 1;
3026 /* Handles the MOVEM from memory to general register instruction. */
3029 move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env)
3031 if (inst_env->prefix_found)
3033 /* The prefix handles the problem if we are in a delay slot. Is the
3034 MOVEM instruction going to change the PC? */
3035 if (cris_get_operand2 (inst) >= REG_PC)
3037 inst_env->reg[REG_PC] =
3038 read_memory_unsigned_integer (inst_env->prefix_value,
3039 4, inst_env->byte_order);
3041 /* The assign value is the value after the increment. Normally, the
3042 assign value is the value before the increment. */
3043 if ((cris_get_operand1 (inst) == REG_PC)
3044 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3046 inst_env->reg[REG_PC] = inst_env->prefix_value;
3047 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3052 /* Is the MOVEM instruction going to change the PC? */
3053 if (cris_get_operand2 (inst) == REG_PC)
3055 /* It's invalid to change the PC in a delay slot. */
3056 if (inst_env->slot_needed)
3058 inst_env->invalid = 1;
3061 inst_env->reg[REG_PC] =
3062 read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)],
3063 4, inst_env->byte_order);
3065 /* The increment is not depending on the size, instead it's depending
3066 on the number of registers loaded from memory. */
3067 if ((cris_get_operand1 (inst) == REG_PC)
3068 && (cris_get_mode (inst) == AUTOINC_MODE))
3070 /* It's invalid to change the PC in a delay slot. */
3071 if (inst_env->slot_needed)
3073 inst_env->invalid = 1;
3076 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3079 inst_env->slot_needed = 0;
3080 inst_env->prefix_found = 0;
3081 inst_env->xflag_found = 0;
3082 inst_env->disable_interrupt = 0;
3085 /* Handles the MOVEM to memory from general register instruction. */
3088 move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env)
3090 if (inst_env->prefix_found)
3092 /* The assign value is the value after the increment. Normally, the
3093 assign value is the value before the increment. */
3094 if ((cris_get_operand1 (inst) == REG_PC)
3095 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3097 /* The prefix handles the problem if we are in a delay slot. */
3098 inst_env->reg[REG_PC] = inst_env->prefix_value;
3099 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3104 /* The increment is not depending on the size, instead it's depending
3105 on the number of registers loaded to memory. */
3106 if ((cris_get_operand1 (inst) == REG_PC)
3107 && (cris_get_mode (inst) == AUTOINC_MODE))
3109 /* It's invalid to change the PC in a delay slot. */
3110 if (inst_env->slot_needed)
3112 inst_env->invalid = 1;
3115 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3118 inst_env->slot_needed = 0;
3119 inst_env->prefix_found = 0;
3120 inst_env->xflag_found = 0;
3121 inst_env->disable_interrupt = 0;
3124 /* Handles the intructions that's not yet implemented, by setting
3125 inst_env->invalid to true. */
3128 not_implemented_op (unsigned short inst, inst_env_type *inst_env)
3130 inst_env->invalid = 1;
3133 /* Handles the XOR instruction. */
3136 xor_op (unsigned short inst, inst_env_type *inst_env)
3138 /* XOR can't have a prefix. */
3139 if (inst_env->prefix_found)
3141 inst_env->invalid = 1;
3145 /* Check if the PC is the target. */
3146 if (cris_get_operand2 (inst) == REG_PC)
3148 /* It's invalid to change the PC in a delay slot. */
3149 if (inst_env->slot_needed)
3151 inst_env->invalid = 1;
3154 inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)];
3156 inst_env->slot_needed = 0;
3157 inst_env->prefix_found = 0;
3158 inst_env->xflag_found = 0;
3159 inst_env->disable_interrupt = 0;
3162 /* Handles the MULS instruction. */
3165 muls_op (unsigned short inst, inst_env_type *inst_env)
3167 /* MULS/U can't have a prefix. */
3168 if (inst_env->prefix_found)
3170 inst_env->invalid = 1;
3174 /* Consider it invalid if the PC is the target. */
3175 if (cris_get_operand2 (inst) == REG_PC)
3177 inst_env->invalid = 1;
3180 inst_env->slot_needed = 0;
3181 inst_env->prefix_found = 0;
3182 inst_env->xflag_found = 0;
3183 inst_env->disable_interrupt = 0;
3186 /* Handles the MULU instruction. */
3189 mulu_op (unsigned short inst, inst_env_type *inst_env)
3191 /* MULS/U can't have a prefix. */
3192 if (inst_env->prefix_found)
3194 inst_env->invalid = 1;
3198 /* Consider it invalid if the PC is the target. */
3199 if (cris_get_operand2 (inst) == REG_PC)
3201 inst_env->invalid = 1;
3204 inst_env->slot_needed = 0;
3205 inst_env->prefix_found = 0;
3206 inst_env->xflag_found = 0;
3207 inst_env->disable_interrupt = 0;
3210 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
3211 The MOVE instruction is the move from source to register. */
3214 add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env,
3215 unsigned long source1, unsigned long source2)
3217 unsigned long pc_mask;
3218 unsigned long operation_mask;
3220 /* Find out how many bits the operation should apply to. */
3221 if (cris_get_size (inst) == INST_BYTE_SIZE)
3223 pc_mask = 0xFFFFFF00;
3224 operation_mask = 0xFF;
3226 else if (cris_get_size (inst) == INST_WORD_SIZE)
3228 pc_mask = 0xFFFF0000;
3229 operation_mask = 0xFFFF;
3231 else if (cris_get_size (inst) == INST_DWORD_SIZE)
3234 operation_mask = 0xFFFFFFFF;
3238 /* The size is out of range. */
3239 inst_env->invalid = 1;
3243 /* The instruction just works on uw_operation_mask bits. */
3244 source2 &= operation_mask;
3245 source1 &= operation_mask;
3247 /* Now calculate the result. The opcode's 3 first bits separates
3248 the different actions. */
3249 switch (cris_get_opcode (inst) & 7)
3259 case 2: /* subtract */
3263 case 3: /* compare */
3275 inst_env->invalid = 1;
3281 /* Make sure that the result doesn't contain more than the instruction
3283 source2 &= operation_mask;
3285 /* Calculate the new breakpoint address. */
3286 inst_env->reg[REG_PC] &= pc_mask;
3287 inst_env->reg[REG_PC] |= source1;
3291 /* Extends the value from either byte or word size to a dword. If the mode
3292 is zero extend then the value is extended with zero. If instead the mode
3293 is signed extend the sign bit of the value is taken into consideration. */
3295 static unsigned long
3296 do_sign_or_zero_extend (unsigned long value, unsigned short *inst)
3298 /* The size can be either byte or word, check which one it is.
3299 Don't check the highest bit, it's indicating if it's a zero
3301 if (cris_get_size (*inst) & INST_WORD_SIZE)
3306 /* Check if the instruction is signed extend. If so, check if value has
3308 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK))
3310 value |= SIGNED_WORD_EXTEND_MASK;
3318 /* Check if the instruction is signed extend. If so, check if value has
3320 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK))
3322 value |= SIGNED_BYTE_EXTEND_MASK;
3325 /* The size should now be dword. */
3326 cris_set_size_to_dword (inst);
3330 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3331 instruction. The MOVE instruction is the move from source to register. */
3334 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3335 inst_env_type *inst_env)
3337 unsigned long operand1;
3338 unsigned long operand2;
3340 /* It's invalid to have a prefix to the instruction. This is a register
3341 mode instruction and can't have a prefix. */
3342 if (inst_env->prefix_found)
3344 inst_env->invalid = 1;
3347 /* Check if the instruction has PC as its target. */
3348 if (cris_get_operand2 (inst) == REG_PC)
3350 if (inst_env->slot_needed)
3352 inst_env->invalid = 1;
3355 /* The instruction has the PC as its target register. */
3356 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3357 operand2 = inst_env->reg[REG_PC];
3359 /* Check if it's a extend, signed or zero instruction. */
3360 if (cris_get_opcode (inst) < 4)
3362 operand1 = do_sign_or_zero_extend (operand1, &inst);
3364 /* Calculate the PC value after the instruction, i.e. where the
3365 breakpoint should be. The order of the udw_operands is vital. */
3366 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3368 inst_env->slot_needed = 0;
3369 inst_env->prefix_found = 0;
3370 inst_env->xflag_found = 0;
3371 inst_env->disable_interrupt = 0;
3374 /* Returns the data contained at address. The size of the data is derived from
3375 the size of the operation. If the instruction is a zero or signed
3376 extend instruction, the size field is changed in instruction. */
3378 static unsigned long
3379 get_data_from_address (unsigned short *inst, CORE_ADDR address,
3380 enum bfd_endian byte_order)
3382 int size = cris_get_size (*inst);
3383 unsigned long value;
3385 /* If it's an extend instruction we don't want the signed extend bit,
3386 because it influences the size. */
3387 if (cris_get_opcode (*inst) < 4)
3389 size &= ~SIGNED_EXTEND_BIT_MASK;
3391 /* Is there a need for checking the size? Size should contain the number of
3394 value = read_memory_unsigned_integer (address, size, byte_order);
3396 /* Check if it's an extend, signed or zero instruction. */
3397 if (cris_get_opcode (*inst) < 4)
3399 value = do_sign_or_zero_extend (value, inst);
3404 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3405 instructions. The MOVE instruction is the move from source to register. */
3408 handle_prefix_assign_mode_for_aritm_op (unsigned short inst,
3409 inst_env_type *inst_env)
3411 unsigned long operand2;
3412 unsigned long operand3;
3414 check_assign (inst, inst_env);
3415 if (cris_get_operand2 (inst) == REG_PC)
3417 operand2 = inst_env->reg[REG_PC];
3419 /* Get the value of the third operand. */
3420 operand3 = get_data_from_address (&inst, inst_env->prefix_value,
3421 inst_env->byte_order);
3423 /* Calculate the PC value after the instruction, i.e. where the
3424 breakpoint should be. The order of the udw_operands is vital. */
3425 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3427 inst_env->slot_needed = 0;
3428 inst_env->prefix_found = 0;
3429 inst_env->xflag_found = 0;
3430 inst_env->disable_interrupt = 0;
3433 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3434 OR instructions. Note that for this to work as expected, the calling
3435 function must have made sure that there is a prefix to this instruction. */
3438 three_operand_add_sub_cmp_and_or_op (unsigned short inst,
3439 inst_env_type *inst_env)
3441 unsigned long operand2;
3442 unsigned long operand3;
3444 if (cris_get_operand1 (inst) == REG_PC)
3446 /* The PC will be changed by the instruction. */
3447 operand2 = inst_env->reg[cris_get_operand2 (inst)];
3449 /* Get the value of the third operand. */
3450 operand3 = get_data_from_address (&inst, inst_env->prefix_value,
3451 inst_env->byte_order);
3453 /* Calculate the PC value after the instruction, i.e. where the
3454 breakpoint should be. */
3455 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3457 inst_env->slot_needed = 0;
3458 inst_env->prefix_found = 0;
3459 inst_env->xflag_found = 0;
3460 inst_env->disable_interrupt = 0;
3463 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3464 instructions. The MOVE instruction is the move from source to register. */
3467 handle_prefix_index_mode_for_aritm_op (unsigned short inst,
3468 inst_env_type *inst_env)
3470 if (cris_get_operand1 (inst) != cris_get_operand2 (inst))
3472 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
3473 SUB, AND or OR something weird is going on (if everything works these
3474 instructions should end up in the three operand version). */
3475 inst_env->invalid = 1;
3480 /* three_operand_add_sub_cmp_and_or does the same as we should do here
3482 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3484 inst_env->slot_needed = 0;
3485 inst_env->prefix_found = 0;
3486 inst_env->xflag_found = 0;
3487 inst_env->disable_interrupt = 0;
3490 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3491 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
3492 source to register. */
3495 handle_inc_and_index_mode_for_aritm_op (unsigned short inst,
3496 inst_env_type *inst_env)
3498 unsigned long operand1;
3499 unsigned long operand2;
3500 unsigned long operand3;
3503 /* The instruction is either an indirect or autoincrement addressing mode.
3504 Check if the destination register is the PC. */
3505 if (cris_get_operand2 (inst) == REG_PC)
3507 /* Must be done here, get_data_from_address may change the size
3509 size = cris_get_size (inst);
3510 operand2 = inst_env->reg[REG_PC];
3512 /* Get the value of the third operand, i.e. the indirect operand. */
3513 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3514 operand3 = get_data_from_address (&inst, operand1, inst_env->byte_order);
3516 /* Calculate the PC value after the instruction, i.e. where the
3517 breakpoint should be. The order of the udw_operands is vital. */
3518 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3520 /* If this is an autoincrement addressing mode, check if the increment
3522 if ((cris_get_operand1 (inst) == REG_PC)
3523 && (cris_get_mode (inst) == AUTOINC_MODE))
3525 /* Get the size field. */
3526 size = cris_get_size (inst);
3528 /* If it's an extend instruction we don't want the signed extend bit,
3529 because it influences the size. */
3530 if (cris_get_opcode (inst) < 4)
3532 size &= ~SIGNED_EXTEND_BIT_MASK;
3534 process_autoincrement (size, inst, inst_env);
3536 inst_env->slot_needed = 0;
3537 inst_env->prefix_found = 0;
3538 inst_env->xflag_found = 0;
3539 inst_env->disable_interrupt = 0;
3542 /* Handles the two-operand addressing mode, all modes except register, for
3543 the ADD, SUB CMP, AND and OR instruction. */
3546 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3547 inst_env_type *inst_env)
3549 if (inst_env->prefix_found)
3551 if (cris_get_mode (inst) == PREFIX_INDEX_MODE)
3553 handle_prefix_index_mode_for_aritm_op (inst, inst_env);
3555 else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
3557 handle_prefix_assign_mode_for_aritm_op (inst, inst_env);
3561 /* The mode is invalid for a prefixed base instruction. */
3562 inst_env->invalid = 1;
3568 handle_inc_and_index_mode_for_aritm_op (inst, inst_env);
3572 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3575 quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env)
3577 unsigned long operand1;
3578 unsigned long operand2;
3580 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3581 instruction and can't have a prefix. */
3582 if (inst_env->prefix_found)
3584 inst_env->invalid = 1;
3588 /* Check if the instruction has PC as its target. */
3589 if (cris_get_operand2 (inst) == REG_PC)
3591 if (inst_env->slot_needed)
3593 inst_env->invalid = 1;
3596 operand1 = cris_get_quick_value (inst);
3597 operand2 = inst_env->reg[REG_PC];
3599 /* The size should now be dword. */
3600 cris_set_size_to_dword (&inst);
3602 /* Calculate the PC value after the instruction, i.e. where the
3603 breakpoint should be. */
3604 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3606 inst_env->slot_needed = 0;
3607 inst_env->prefix_found = 0;
3608 inst_env->xflag_found = 0;
3609 inst_env->disable_interrupt = 0;
3612 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3615 quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env)
3617 unsigned long operand1;
3618 unsigned long operand2;
3620 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3621 instruction and can't have a prefix. */
3622 if (inst_env->prefix_found)
3624 inst_env->invalid = 1;
3627 /* Check if the instruction has PC as its target. */
3628 if (cris_get_operand2 (inst) == REG_PC)
3630 if (inst_env->slot_needed)
3632 inst_env->invalid = 1;
3635 /* The instruction has the PC as its target register. */
3636 operand1 = cris_get_quick_value (inst);
3637 operand2 = inst_env->reg[REG_PC];
3639 /* The quick value is signed, so check if we must do a signed extend. */
3640 if (operand1 & SIGNED_QUICK_VALUE_MASK)
3643 operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK;
3645 /* The size should now be dword. */
3646 cris_set_size_to_dword (&inst);
3648 /* Calculate the PC value after the instruction, i.e. where the
3649 breakpoint should be. */
3650 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3652 inst_env->slot_needed = 0;
3653 inst_env->prefix_found = 0;
3654 inst_env->xflag_found = 0;
3655 inst_env->disable_interrupt = 0;
3658 /* Translate op_type to a function and call it. */
3661 cris_gdb_func (struct gdbarch *gdbarch, enum cris_op_type op_type,
3662 unsigned short inst, inst_env_type *inst_env)
3666 case cris_not_implemented_op:
3667 not_implemented_op (inst, inst_env);
3671 abs_op (inst, inst_env);
3675 addi_op (inst, inst_env);
3679 asr_op (inst, inst_env);
3683 asrq_op (inst, inst_env);
3686 case cris_ax_ei_setf_op:
3687 ax_ei_setf_op (inst, inst_env);
3690 case cris_bdap_prefix:
3691 bdap_prefix (inst, inst_env);
3694 case cris_biap_prefix:
3695 biap_prefix (inst, inst_env);
3699 break_op (inst, inst_env);
3702 case cris_btst_nop_op:
3703 btst_nop_op (inst, inst_env);
3706 case cris_clearf_di_op:
3707 clearf_di_op (inst, inst_env);
3710 case cris_dip_prefix:
3711 dip_prefix (inst, inst_env);
3714 case cris_dstep_logshift_mstep_neg_not_op:
3715 dstep_logshift_mstep_neg_not_op (inst, inst_env);
3718 case cris_eight_bit_offset_branch_op:
3719 eight_bit_offset_branch_op (inst, inst_env);
3722 case cris_move_mem_to_reg_movem_op:
3723 move_mem_to_reg_movem_op (inst, inst_env);
3726 case cris_move_reg_to_mem_movem_op:
3727 move_reg_to_mem_movem_op (inst, inst_env);
3730 case cris_move_to_preg_op:
3731 move_to_preg_op (gdbarch, inst, inst_env);
3735 muls_op (inst, inst_env);
3739 mulu_op (inst, inst_env);
3742 case cris_none_reg_mode_add_sub_cmp_and_or_move_op:
3743 none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3746 case cris_none_reg_mode_clear_test_op:
3747 none_reg_mode_clear_test_op (inst, inst_env);
3750 case cris_none_reg_mode_jump_op:
3751 none_reg_mode_jump_op (inst, inst_env);
3754 case cris_none_reg_mode_move_from_preg_op:
3755 none_reg_mode_move_from_preg_op (gdbarch, inst, inst_env);
3758 case cris_quick_mode_add_sub_op:
3759 quick_mode_add_sub_op (inst, inst_env);
3762 case cris_quick_mode_and_cmp_move_or_op:
3763 quick_mode_and_cmp_move_or_op (inst, inst_env);
3766 case cris_quick_mode_bdap_prefix:
3767 quick_mode_bdap_prefix (inst, inst_env);
3770 case cris_reg_mode_add_sub_cmp_and_or_move_op:
3771 reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3774 case cris_reg_mode_clear_op:
3775 reg_mode_clear_op (inst, inst_env);
3778 case cris_reg_mode_jump_op:
3779 reg_mode_jump_op (inst, inst_env);
3782 case cris_reg_mode_move_from_preg_op:
3783 reg_mode_move_from_preg_op (inst, inst_env);
3786 case cris_reg_mode_test_op:
3787 reg_mode_test_op (inst, inst_env);
3791 scc_op (inst, inst_env);
3794 case cris_sixteen_bit_offset_branch_op:
3795 sixteen_bit_offset_branch_op (inst, inst_env);
3798 case cris_three_operand_add_sub_cmp_and_or_op:
3799 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3802 case cris_three_operand_bound_op:
3803 three_operand_bound_op (inst, inst_env);
3806 case cris_two_operand_bound_op:
3807 two_operand_bound_op (inst, inst_env);
3811 xor_op (inst, inst_env);
3816 /* This wrapper is to avoid cris_get_assembler being called before
3817 exec_bfd has been set. */
3820 cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info)
3822 int (*print_insn) (bfd_vma addr, struct disassemble_info *info);
3823 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3824 disassembler, even when there is no BFD. Does something like
3825 "gdb; target remote; disassmeble *0x123" work? */
3826 gdb_assert (exec_bfd != NULL);
3827 print_insn = cris_get_disassembler (exec_bfd);
3828 gdb_assert (print_insn != NULL);
3829 return print_insn (addr, info);
3832 /* Copied from <asm/elf.h>. */
3833 typedef unsigned long elf_greg_t;
3835 /* Same as user_regs_struct struct in <asm/user.h>. */
3836 #define CRISV10_ELF_NGREG 35
3837 typedef elf_greg_t elf_gregset_t[CRISV10_ELF_NGREG];
3839 #define CRISV32_ELF_NGREG 32
3840 typedef elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG];
3842 /* Unpack an elf_gregset_t into GDB's register cache. */
3845 cris_supply_gregset (struct regcache *regcache, elf_gregset_t *gregsetp)
3847 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3848 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3850 elf_greg_t *regp = *gregsetp;
3851 static char zerobuf[4] = {0};
3853 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3854 knows about the actual size of each register so that's no problem. */
3855 for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++)
3857 regcache_raw_supply (regcache, i, (char *)®p[i]);
3860 if (tdep->cris_version == 32)
3862 /* Needed to set pseudo-register PC for CRISv32. */
3863 /* FIXME: If ERP is in a delay slot at this point then the PC will
3864 be wrong. Issue a warning to alert the user. */
3865 regcache_raw_supply (regcache, gdbarch_pc_regnum (gdbarch),
3866 (char *)®p[ERP_REGNUM]);
3868 if (*(char *)®p[ERP_REGNUM] & 0x1)
3869 fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n");
3873 /* Use a local version of this function to get the correct types for
3874 regsets, until multi-arch core support is ready. */
3877 fetch_core_registers (struct regcache *regcache,
3878 char *core_reg_sect, unsigned core_reg_size,
3879 int which, CORE_ADDR reg_addr)
3881 elf_gregset_t gregset;
3886 if (core_reg_size != sizeof (elf_gregset_t)
3887 && core_reg_size != sizeof (crisv32_elf_gregset_t))
3889 warning (_("wrong size gregset struct in core file"));
3893 memcpy (&gregset, core_reg_sect, sizeof (gregset));
3894 cris_supply_gregset (regcache, &gregset);
3898 /* We've covered all the kinds of registers we know about here,
3899 so this must be something we wouldn't know what to do with
3900 anyway. Just ignore it. */
3905 static struct core_fns cris_elf_core_fns =
3907 bfd_target_elf_flavour, /* core_flavour */
3908 default_check_format, /* check_format */
3909 default_core_sniffer, /* core_sniffer */
3910 fetch_core_registers, /* core_read_registers */
3914 extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */
3917 _initialize_cris_tdep (void)
3919 static struct cmd_list_element *cris_set_cmdlist;
3920 static struct cmd_list_element *cris_show_cmdlist;
3922 struct cmd_list_element *c;
3924 gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep);
3926 /* CRIS-specific user-commands. */
3927 add_setshow_uinteger_cmd ("cris-version", class_support,
3928 &usr_cmd_cris_version,
3929 _("Set the current CRIS version."),
3930 _("Show the current CRIS version."),
3932 Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\
3935 NULL, /* FIXME: i18n: Current CRIS version
3937 &setlist, &showlist);
3939 add_setshow_enum_cmd ("cris-mode", class_support,
3940 cris_modes, &usr_cmd_cris_mode,
3941 _("Set the current CRIS mode."),
3942 _("Show the current CRIS mode."),
3944 Set to CRIS_MODE_GURU when debugging in guru mode.\n\
3945 Makes GDB use the NRP register instead of the ERP register in certain cases."),
3947 NULL, /* FIXME: i18n: Current CRIS version is %s. */
3948 &setlist, &showlist);
3950 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support,
3951 &usr_cmd_cris_dwarf2_cfi,
3952 _("Set the usage of Dwarf-2 CFI for CRIS."),
3953 _("Show the usage of Dwarf-2 CFI for CRIS."),
3954 _("Set this to \"off\" if using gcc-cris < R59."),
3955 set_cris_dwarf2_cfi,
3956 NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI
3958 &setlist, &showlist);
3960 deprecated_add_core_fns (&cris_elf_core_fns);
3963 /* Prints out all target specific values. */
3966 cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3968 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3971 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n",
3972 tdep->cris_version);
3973 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n",
3975 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
3976 tdep->cris_dwarf2_cfi);
3981 set_cris_version (char *ignore_args, int from_tty,
3982 struct cmd_list_element *c)
3984 struct gdbarch_info info;
3986 usr_cmd_cris_version_valid = 1;
3988 /* Update the current architecture, if needed. */
3989 gdbarch_info_init (&info);
3990 if (!gdbarch_update_p (info))
3991 internal_error (__FILE__, __LINE__,
3992 _("cris_gdbarch_update: failed to update architecture."));
3996 set_cris_mode (char *ignore_args, int from_tty,
3997 struct cmd_list_element *c)
3999 struct gdbarch_info info;
4001 /* Update the current architecture, if needed. */
4002 gdbarch_info_init (&info);
4003 if (!gdbarch_update_p (info))
4004 internal_error (__FILE__, __LINE__,
4005 "cris_gdbarch_update: failed to update architecture.");
4009 set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
4010 struct cmd_list_element *c)
4012 struct gdbarch_info info;
4014 /* Update the current architecture, if needed. */
4015 gdbarch_info_init (&info);
4016 if (!gdbarch_update_p (info))
4017 internal_error (__FILE__, __LINE__,
4018 _("cris_gdbarch_update: failed to update architecture."));
4021 static struct gdbarch *
4022 cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
4024 struct gdbarch *gdbarch;
4025 struct gdbarch_tdep *tdep;
4028 if (usr_cmd_cris_version_valid)
4030 /* Trust the user's CRIS version setting. */
4031 cris_version = usr_cmd_cris_version;
4033 else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32)
4039 /* Assume it's CRIS version 10. */
4043 /* Make the current settings visible to the user. */
4044 usr_cmd_cris_version = cris_version;
4046 /* Find a candidate among the list of pre-declared architectures. */
4047 for (arches = gdbarch_list_lookup_by_info (arches, &info);
4049 arches = gdbarch_list_lookup_by_info (arches->next, &info))
4051 if ((gdbarch_tdep (arches->gdbarch)->cris_version
4052 == usr_cmd_cris_version)
4053 && (gdbarch_tdep (arches->gdbarch)->cris_mode
4054 == usr_cmd_cris_mode)
4055 && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi
4056 == usr_cmd_cris_dwarf2_cfi))
4057 return arches->gdbarch;
4060 /* No matching architecture was found. Create a new one. */
4061 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
4062 gdbarch = gdbarch_alloc (&info, tdep);
4064 tdep->cris_version = usr_cmd_cris_version;
4065 tdep->cris_mode = usr_cmd_cris_mode;
4066 tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi;
4068 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
4069 switch (info.byte_order)
4071 case BFD_ENDIAN_LITTLE:
4075 case BFD_ENDIAN_BIG:
4076 internal_error (__FILE__, __LINE__,
4077 _("cris_gdbarch_init: big endian byte order in info"));
4081 internal_error (__FILE__, __LINE__,
4082 _("cris_gdbarch_init: unknown byte order in info"));
4085 set_gdbarch_return_value (gdbarch, cris_return_value);
4087 set_gdbarch_sp_regnum (gdbarch, 14);
4089 /* Length of ordinary registers used in push_word and a few other
4090 places. register_size() is the real way to know how big a
4093 set_gdbarch_double_bit (gdbarch, 64);
4094 /* The default definition of a long double is 2 * gdbarch_double_bit,
4095 which means we have to set this explicitly. */
4096 set_gdbarch_long_double_bit (gdbarch, 64);
4098 /* The total amount of space needed to store (in an array called registers)
4099 GDB's copy of the machine's register state. Note: We can not use
4100 cris_register_size at this point, since it relies on gdbarch
4102 switch (tdep->cris_version)
4110 /* Old versions; not supported. */
4111 internal_error (__FILE__, __LINE__,
4112 _("cris_gdbarch_init: unsupported CRIS version"));
4117 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
4118 P7 (32 bits), and P15 (32 bits) have been implemented. */
4119 set_gdbarch_pc_regnum (gdbarch, 15);
4120 set_gdbarch_register_type (gdbarch, cris_register_type);
4121 /* There are 32 registers (some of which may not be implemented). */
4122 set_gdbarch_num_regs (gdbarch, 32);
4123 set_gdbarch_register_name (gdbarch, cris_register_name);
4124 set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register);
4125 set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register);
4127 set_gdbarch_software_single_step (gdbarch, cris_software_single_step);
4131 /* CRIS v32. General registers R0 - R15 (32 bits), special registers
4132 P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
4133 and pseudo-register PC (32 bits). */
4134 set_gdbarch_pc_regnum (gdbarch, 32);
4135 set_gdbarch_register_type (gdbarch, crisv32_register_type);
4136 /* 32 registers + pseudo-register PC + 16 support registers. */
4137 set_gdbarch_num_regs (gdbarch, 32 + 1 + 16);
4138 set_gdbarch_register_name (gdbarch, crisv32_register_name);
4140 set_gdbarch_cannot_store_register
4141 (gdbarch, crisv32_cannot_store_register);
4142 set_gdbarch_cannot_fetch_register
4143 (gdbarch, crisv32_cannot_fetch_register);
4145 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
4147 set_gdbarch_single_step_through_delay
4148 (gdbarch, crisv32_single_step_through_delay);
4153 internal_error (__FILE__, __LINE__,
4154 _("cris_gdbarch_init: unknown CRIS version"));
4157 /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
4158 have the same ABI). */
4159 set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code);
4160 set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call);
4161 set_gdbarch_frame_align (gdbarch, cris_frame_align);
4162 set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue);
4164 /* The stack grows downward. */
4165 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4167 set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc);
4169 set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc);
4170 set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp);
4171 set_gdbarch_dummy_id (gdbarch, cris_dummy_id);
4173 if (tdep->cris_dwarf2_cfi == 1)
4175 /* Hook in the Dwarf-2 frame sniffer. */
4176 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum);
4177 dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg);
4178 dwarf2_append_unwinders (gdbarch);
4181 if (tdep->cris_mode != cris_mode_guru)
4183 frame_unwind_append_unwinder (gdbarch, &cris_sigtramp_frame_unwind);
4186 frame_unwind_append_unwinder (gdbarch, &cris_frame_unwind);
4187 frame_base_set_default (gdbarch, &cris_frame_base);
4189 set_solib_svr4_fetch_link_map_offsets
4190 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
4192 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
4193 disassembler, even when there is no BFD. Does something like
4194 "gdb; target remote; disassmeble *0x123" work? */
4195 set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler);