1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 Contributed by Axis Communications AB.
7 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "frame-unwind.h"
27 #include "frame-base.h"
28 #include "trad-frame.h"
29 #include "dwarf2-frame.h"
37 #include "opcode/cris.h"
38 #include "arch-utils.h"
40 #include "gdb_assert.h"
42 /* To get entry_point_address. */
45 #include "solib.h" /* Support for shared libraries. */
46 #include "solib-svr4.h"
47 #include "gdb_string.h"
52 /* There are no floating point registers. Used in gdbserver low-linux.c. */
55 /* There are 16 general registers. */
58 /* There are 16 special registers. */
61 /* CRISv32 has a pseudo PC register, not noted here. */
63 /* CRISv32 has 16 support registers. */
67 /* Register numbers of various important registers.
68 CRIS_FP_REGNUM Contains address of executing stack frame.
69 STR_REGNUM Contains the address of structure return values.
70 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
71 ARG1_REGNUM Contains the first parameter to a function.
72 ARG2_REGNUM Contains the second parameter to a function.
73 ARG3_REGNUM Contains the third parameter to a function.
74 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
75 gdbarch_sp_regnum Contains address of top of stack.
76 gdbarch_pc_regnum Contains address of next instruction.
77 SRP_REGNUM Subroutine return pointer register.
78 BRP_REGNUM Breakpoint return pointer register. */
82 /* Enums with respect to the general registers, valid for all
83 CRIS versions. The frame pointer is always in R8. */
85 /* ABI related registers. */
93 /* Registers which happen to be common. */
98 /* CRISv10 et. al. specific registers. */
110 /* CRISv32 specific registers. */
123 CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */
125 CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */
145 extern const struct cris_spec_reg cris_spec_regs[];
147 /* CRIS version, set via the user command 'set cris-version'. Affects
148 register names and sizes. */
149 static int usr_cmd_cris_version;
151 /* Indicates whether to trust the above variable. */
152 static int usr_cmd_cris_version_valid = 0;
154 static const char cris_mode_normal[] = "normal";
155 static const char cris_mode_guru[] = "guru";
156 static const char *cris_modes[] = {
162 /* CRIS mode, set via the user command 'set cris-mode'. Affects
163 type of break instruction among other things. */
164 static const char *usr_cmd_cris_mode = cris_mode_normal;
166 /* Whether to make use of Dwarf-2 CFI (default on). */
167 static int usr_cmd_cris_dwarf2_cfi = 1;
169 /* CRIS architecture specific information. */
173 const char *cris_mode;
177 /* Sigtramp identification code copied from i386-linux-tdep.c. */
179 #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
180 #define SIGTRAMP_OFFSET0 0
181 #define SIGTRAMP_INSN1 0xe93d /* break 13 */
182 #define SIGTRAMP_OFFSET1 4
184 static const unsigned short sigtramp_code[] =
186 SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */
187 SIGTRAMP_INSN1 /* break 13 */
190 #define SIGTRAMP_LEN (sizeof sigtramp_code)
192 /* Note: same length as normal sigtramp code. */
194 static const unsigned short rt_sigtramp_code[] =
196 SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */
197 SIGTRAMP_INSN1 /* break 13 */
200 /* If PC is in a sigtramp routine, return the address of the start of
201 the routine. Otherwise, return 0. */
204 cris_sigtramp_start (struct frame_info *this_frame)
206 CORE_ADDR pc = get_frame_pc (this_frame);
207 gdb_byte buf[SIGTRAMP_LEN];
209 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
212 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
214 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
217 pc -= SIGTRAMP_OFFSET1;
218 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
222 if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0)
228 /* If PC is in a RT sigtramp routine, return the address of the start of
229 the routine. Otherwise, return 0. */
232 cris_rt_sigtramp_start (struct frame_info *this_frame)
234 CORE_ADDR pc = get_frame_pc (this_frame);
235 gdb_byte buf[SIGTRAMP_LEN];
237 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
240 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
242 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
245 pc -= SIGTRAMP_OFFSET1;
246 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
250 if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0)
256 /* Assuming THIS_FRAME is a frame for a GNU/Linux sigtramp routine,
257 return the address of the associated sigcontext structure. */
260 cris_sigcontext_addr (struct frame_info *this_frame)
266 get_frame_register (this_frame,
267 gdbarch_sp_regnum (get_frame_arch (this_frame)), buf);
268 sp = extract_unsigned_integer (buf, 4);
270 /* Look for normal sigtramp frame first. */
271 pc = cris_sigtramp_start (this_frame);
274 /* struct signal_frame (arch/cris/kernel/signal.c) contains
275 struct sigcontext as its first member, meaning the SP points to
280 pc = cris_rt_sigtramp_start (this_frame);
283 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
284 a struct ucontext, which in turn contains a struct sigcontext.
286 4 + 4 + 128 to struct ucontext, then
287 4 + 4 + 12 to struct sigcontext. */
291 error (_("Couldn't recognize signal trampoline."));
295 struct cris_unwind_cache
297 /* The previous frame's inner most stack address. Used as this
298 frame ID's stack_addr. */
300 /* The frame's base, optionally used by the high-level debug info. */
303 /* How far the SP and r8 (FP) have been offset from the start of
304 the stack frame (as defined by the previous frame's stack
310 /* From old frame_extra_info struct. */
314 /* Table indicating the location of each and every register. */
315 struct trad_frame_saved_reg *saved_regs;
318 static struct cris_unwind_cache *
319 cris_sigtramp_frame_unwind_cache (struct frame_info *this_frame,
322 struct gdbarch *gdbarch = get_frame_arch (this_frame);
323 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
324 struct cris_unwind_cache *info;
332 return (*this_cache);
334 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
335 (*this_cache) = info;
336 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
338 /* Zero all fields. */
344 info->uses_frame = 0;
346 info->leaf_function = 0;
348 get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
349 info->base = extract_unsigned_integer (buf, 4);
351 addr = cris_sigcontext_addr (this_frame);
353 /* Layout of the sigcontext struct:
356 unsigned long oldmask;
360 if (tdep->cris_version == 10)
362 /* R0 to R13 are stored in reverse order at offset (2 * 4) in
364 for (i = 0; i <= 13; i++)
365 info->saved_regs[i].addr = addr + ((15 - i) * 4);
367 info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4);
368 info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4);
369 info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4);
370 /* Note: IRP is off by 2 at this point. There's no point in correcting
371 it though since that will mean that the backtrace will show a PC
372 different from what is shown when stopped. */
373 info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4);
374 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
375 = info->saved_regs[IRP_REGNUM];
376 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr = addr + (24 * 4);
381 /* R0 to R13 are stored in order at offset (1 * 4) in
383 for (i = 0; i <= 13; i++)
384 info->saved_regs[i].addr = addr + ((i + 1) * 4);
386 info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4);
387 info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4);
388 info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4);
389 info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4);
390 info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4);
391 info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4);
392 info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4);
393 info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4);
394 info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4);
396 /* FIXME: If ERP is in a delay slot at this point then the PC will
397 be wrong at this point. This problem manifests itself in the
398 sigaltstack.exp test case, which occasionally generates FAILs when
399 the signal is received while in a delay slot.
401 This could be solved by a couple of read_memory_unsigned_integer and a
402 trad_frame_set_value. */
403 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
404 = info->saved_regs[ERP_REGNUM];
406 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr
414 cris_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
415 struct frame_id *this_id)
417 struct cris_unwind_cache *cache =
418 cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
419 (*this_id) = frame_id_build (cache->base, get_frame_pc (this_frame));
422 /* Forward declaration. */
424 static struct value *cris_frame_prev_register (struct frame_info *this_frame,
425 void **this_cache, int regnum);
426 static struct value *
427 cris_sigtramp_frame_prev_register (struct frame_info *this_frame,
428 void **this_cache, int regnum)
430 /* Make sure we've initialized the cache. */
431 cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
432 return cris_frame_prev_register (this_frame, this_cache, regnum);
436 cris_sigtramp_frame_sniffer (const struct frame_unwind *self,
437 struct frame_info *this_frame,
440 if (cris_sigtramp_start (this_frame)
441 || cris_rt_sigtramp_start (this_frame))
447 static const struct frame_unwind cris_sigtramp_frame_unwind =
450 cris_sigtramp_frame_this_id,
451 cris_sigtramp_frame_prev_register,
453 cris_sigtramp_frame_sniffer
457 crisv32_single_step_through_delay (struct gdbarch *gdbarch,
458 struct frame_info *this_frame)
460 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
464 if (tdep->cris_mode == cris_mode_guru)
465 erp = get_frame_register_unsigned (this_frame, NRP_REGNUM);
467 erp = get_frame_register_unsigned (this_frame, ERP_REGNUM);
471 /* In delay slot - check if there's a breakpoint at the preceding
473 if (breakpoint_here_p (erp & ~0x1))
479 /* Hardware watchpoint support. */
481 /* We support 6 hardware data watchpoints, but cannot trigger on execute
482 (any combination of read/write is fine). */
485 cris_can_use_hardware_watchpoint (int type, int count, int other)
487 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
489 /* No bookkeeping is done here; it is handled by the remote debug agent. */
491 if (tdep->cris_version != 32)
494 /* CRISv32: Six data watchpoints, one for instructions. */
495 return (((type == bp_read_watchpoint || type == bp_access_watchpoint
496 || type == bp_hardware_watchpoint) && count <= 6)
497 || (type == bp_hardware_breakpoint && count <= 1));
500 /* The CRISv32 hardware data watchpoints work by specifying ranges,
501 which have no alignment or length restrictions. */
504 cris_region_ok_for_watchpoint (CORE_ADDR addr, int len)
509 /* If the inferior has some watchpoint that triggered, return the
510 address associated with that watchpoint. Otherwise, return
514 cris_stopped_data_address (void)
517 eda = get_frame_register_unsigned (get_current_frame (), EDA_REGNUM);
521 /* The instruction environment needed to find single-step breakpoints. */
524 struct instruction_environment
526 unsigned long reg[NUM_GENREGS];
527 unsigned long preg[NUM_SPECREGS];
528 unsigned long branch_break_address;
529 unsigned long delay_slot_pc;
530 unsigned long prefix_value;
535 int delay_slot_pc_active;
537 int disable_interrupt;
540 /* Machine-dependencies in CRIS for opcodes. */
542 /* Instruction sizes. */
543 enum cris_instruction_sizes
550 /* Addressing modes. */
551 enum cris_addressing_modes
558 /* Prefix addressing modes. */
559 enum cris_prefix_addressing_modes
561 PREFIX_INDEX_MODE = 2,
562 PREFIX_ASSIGN_MODE = 3,
564 /* Handle immediate byte offset addressing mode prefix format. */
565 PREFIX_OFFSET_MODE = 2
568 /* Masks for opcodes. */
569 enum cris_opcode_masks
571 BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1,
572 SIGNED_EXTEND_BIT_MASK = 0x2,
573 SIGNED_BYTE_MASK = 0x80,
574 SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00,
575 SIGNED_WORD_MASK = 0x8000,
576 SIGNED_WORD_EXTEND_MASK = 0xFFFF0000,
577 SIGNED_DWORD_MASK = 0x80000000,
578 SIGNED_QUICK_VALUE_MASK = 0x20,
579 SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0
582 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
590 cris_get_operand2 (unsigned short insn)
592 return ((insn & 0xF000) >> 12);
596 cris_get_mode (unsigned short insn)
598 return ((insn & 0x0C00) >> 10);
602 cris_get_opcode (unsigned short insn)
604 return ((insn & 0x03C0) >> 6);
608 cris_get_size (unsigned short insn)
610 return ((insn & 0x0030) >> 4);
614 cris_get_operand1 (unsigned short insn)
616 return (insn & 0x000F);
619 /* Additional functions in order to handle opcodes. */
622 cris_get_quick_value (unsigned short insn)
624 return (insn & 0x003F);
628 cris_get_bdap_quick_offset (unsigned short insn)
630 return (insn & 0x00FF);
634 cris_get_branch_short_offset (unsigned short insn)
636 return (insn & 0x00FF);
640 cris_get_asr_shift_steps (unsigned long value)
642 return (value & 0x3F);
646 cris_get_clear_size (unsigned short insn)
648 return ((insn) & 0xC000);
652 cris_is_signed_extend_bit_on (unsigned short insn)
654 return (((insn) & 0x20) == 0x20);
658 cris_is_xflag_bit_on (unsigned short insn)
660 return (((insn) & 0x1000) == 0x1000);
664 cris_set_size_to_dword (unsigned short *insn)
671 cris_get_signed_offset (unsigned short insn)
673 return ((signed char) (insn & 0x00FF));
676 /* Calls an op function given the op-type, working on the insn and the
678 static void cris_gdb_func (struct gdbarch *, enum cris_op_type, unsigned short,
681 static struct gdbarch *cris_gdbarch_init (struct gdbarch_info,
682 struct gdbarch_list *);
684 static void cris_dump_tdep (struct gdbarch *, struct ui_file *);
686 static void set_cris_version (char *ignore_args, int from_tty,
687 struct cmd_list_element *c);
689 static void set_cris_mode (char *ignore_args, int from_tty,
690 struct cmd_list_element *c);
692 static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
693 struct cmd_list_element *c);
695 static CORE_ADDR cris_scan_prologue (CORE_ADDR pc,
696 struct frame_info *this_frame,
697 struct cris_unwind_cache *info);
699 static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc,
700 struct frame_info *this_frame,
701 struct cris_unwind_cache *info);
703 static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch,
704 struct frame_info *next_frame);
706 static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch,
707 struct frame_info *next_frame);
709 /* When arguments must be pushed onto the stack, they go on in reverse
710 order. The below implements a FILO (stack) to do this.
711 Copied from d10v-tdep.c. */
716 struct stack_item *prev;
720 static struct stack_item *
721 push_stack_item (struct stack_item *prev, void *contents, int len)
723 struct stack_item *si;
724 si = xmalloc (sizeof (struct stack_item));
725 si->data = xmalloc (len);
728 memcpy (si->data, contents, len);
732 static struct stack_item *
733 pop_stack_item (struct stack_item *si)
735 struct stack_item *dead = si;
742 /* Put here the code to store, into fi->saved_regs, the addresses of
743 the saved registers of frame described by FRAME_INFO. This
744 includes special registers such as pc and fp saved in special ways
745 in the stack frame. sp is even more special: the address we return
746 for it IS the sp for the next frame. */
748 struct cris_unwind_cache *
749 cris_frame_unwind_cache (struct frame_info *this_frame,
750 void **this_prologue_cache)
752 struct gdbarch *gdbarch = get_frame_arch (this_frame);
753 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
755 struct cris_unwind_cache *info;
758 if ((*this_prologue_cache))
759 return (*this_prologue_cache);
761 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
762 (*this_prologue_cache) = info;
763 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
765 /* Zero all fields. */
771 info->uses_frame = 0;
773 info->leaf_function = 0;
775 /* Prologue analysis does the rest... */
776 if (tdep->cris_version == 32)
777 crisv32_scan_prologue (get_frame_func (this_frame), this_frame, info);
779 cris_scan_prologue (get_frame_func (this_frame), this_frame, info);
784 /* Given a GDB frame, determine the address of the calling function's
785 frame. This will be used to create a new GDB frame struct. */
788 cris_frame_this_id (struct frame_info *this_frame,
789 void **this_prologue_cache,
790 struct frame_id *this_id)
792 struct cris_unwind_cache *info
793 = cris_frame_unwind_cache (this_frame, this_prologue_cache);
798 /* The FUNC is easy. */
799 func = get_frame_func (this_frame);
801 /* Hopefully the prologue analysis either correctly determined the
802 frame's base (which is the SP from the previous frame), or set
803 that base to "NULL". */
804 base = info->prev_sp;
808 id = frame_id_build (base, func);
813 static struct value *
814 cris_frame_prev_register (struct frame_info *this_frame,
815 void **this_prologue_cache, int regnum)
817 struct cris_unwind_cache *info
818 = cris_frame_unwind_cache (this_frame, this_prologue_cache);
819 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
822 /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
823 frame. The frame ID's base needs to match the TOS value saved by
824 save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */
826 static struct frame_id
827 cris_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
830 sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
831 return frame_id_build (sp, get_frame_pc (this_frame));
835 cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
837 /* Align to the size of an instruction (so that they can safely be
838 pushed onto the stack). */
843 cris_push_dummy_code (struct gdbarch *gdbarch,
844 CORE_ADDR sp, CORE_ADDR funaddr,
845 struct value **args, int nargs,
846 struct type *value_type,
847 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
848 struct regcache *regcache)
850 /* Allocate space sufficient for a breakpoint. */
852 /* Store the address of that breakpoint */
854 /* CRIS always starts the call at the callee's entry point. */
860 cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
861 struct regcache *regcache, CORE_ADDR bp_addr,
862 int nargs, struct value **args, CORE_ADDR sp,
863 int struct_return, CORE_ADDR struct_addr)
872 /* The function's arguments and memory allocated by gdb for the arguments to
873 point at reside in separate areas on the stack.
874 Both frame pointers grow toward higher addresses. */
878 struct stack_item *si = NULL;
880 /* Push the return address. */
881 regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr);
883 /* Are we returning a value using a structure return or a normal value
884 return? struct_addr is the address of the reserved space for the return
885 structure to be written on the stack. */
888 regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr);
891 /* Now load as many as possible of the first arguments into registers,
892 and push the rest onto the stack. */
893 argreg = ARG1_REGNUM;
896 for (argnum = 0; argnum < nargs; argnum++)
903 len = TYPE_LENGTH (value_type (args[argnum]));
904 val = (char *) value_contents (args[argnum]);
906 /* How may registers worth of storage do we need for this argument? */
907 reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0);
909 if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM))
911 /* Data passed by value. Fits in available register(s). */
912 for (i = 0; i < reg_demand; i++)
914 regcache_cooked_write (regcache, argreg, val);
919 else if (len <= (2 * 4) && argreg <= ARG4_REGNUM)
921 /* Data passed by value. Does not fit in available register(s).
922 Use the register(s) first, then the stack. */
923 for (i = 0; i < reg_demand; i++)
925 if (argreg <= ARG4_REGNUM)
927 regcache_cooked_write (regcache, argreg, val);
933 /* Push item for later so that pushed arguments
934 come in the right order. */
935 si = push_stack_item (si, val, 4);
940 else if (len > (2 * 4))
942 /* Data passed by reference. Push copy of data onto stack
943 and pass pointer to this copy as argument. */
944 sp = (sp - len) & ~3;
945 write_memory (sp, val, len);
947 if (argreg <= ARG4_REGNUM)
949 regcache_cooked_write_unsigned (regcache, argreg, sp);
955 store_unsigned_integer (buf, 4, sp);
956 si = push_stack_item (si, buf, 4);
961 /* Data passed by value. No available registers. Put it on
963 si = push_stack_item (si, val, len);
969 /* fp_arg must be word-aligned (i.e., don't += len) to match
970 the function prologue. */
971 sp = (sp - si->len) & ~3;
972 write_memory (sp, si->data, si->len);
973 si = pop_stack_item (si);
976 /* Finally, update the SP register. */
977 regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp);
982 static const struct frame_unwind cris_frame_unwind =
986 cris_frame_prev_register,
988 default_frame_sniffer
992 cris_frame_base_address (struct frame_info *this_frame, void **this_cache)
994 struct cris_unwind_cache *info
995 = cris_frame_unwind_cache (this_frame, this_cache);
999 static const struct frame_base cris_frame_base =
1002 cris_frame_base_address,
1003 cris_frame_base_address,
1004 cris_frame_base_address
1007 /* Frames information. The definition of the struct frame_info is
1011 enum frame_type type;
1015 If the compilation option -fno-omit-frame-pointer is present the
1016 variable frame will be set to the content of R8 which is the frame
1019 The variable pc contains the address where execution is performed
1020 in the present frame. The innermost frame contains the current content
1021 of the register PC. All other frames contain the content of the
1022 register PC in the next frame.
1024 The variable `type' indicates the frame's type: normal, SIGTRAMP
1025 (associated with a signal handler), dummy (associated with a dummy
1028 The variable return_pc contains the address where execution should be
1029 resumed when the present frame has finished, the return address.
1031 The variable leaf_function is 1 if the return address is in the register
1032 SRP, and 0 if it is on the stack.
1034 Prologue instructions C-code.
1035 The prologue may consist of (-fno-omit-frame-pointer)
1039 move.d sp,r8 move.d sp,r8
1041 movem rY,[sp] movem rY,[sp]
1042 move.S rZ,[r8-U] move.S rZ,[r8-U]
1044 where 1 is a non-terminal function, and 2 is a leaf-function.
1046 Note that this assumption is extremely brittle, and will break at the
1047 slightest change in GCC's prologue.
1049 If local variables are declared or register contents are saved on stack
1050 the subq-instruction will be present with X as the number of bytes
1051 needed for storage. The reshuffle with respect to r8 may be performed
1052 with any size S (b, w, d) and any of the general registers Z={0..13}.
1053 The offset U should be representable by a signed 8-bit value in all cases.
1054 Thus, the prefix word is assumed to be immediate byte offset mode followed
1055 by another word containing the instruction.
1064 Prologue instructions C++-code.
1065 Case 1) and 2) in the C-code may be followed by
1067 move.d r10,rS ; this
1071 move.S [r8+U],rZ ; P4
1073 if any of the call parameters are stored. The host expects these
1074 instructions to be executed in order to get the call parameters right. */
1076 /* Examine the prologue of a function. The variable ip is the address of
1077 the first instruction of the prologue. The variable limit is the address
1078 of the first instruction after the prologue. The variable fi contains the
1079 information in struct frame_info. The variable frameless_p controls whether
1080 the entire prologue is examined (0) or just enough instructions to
1081 determine that it is a prologue (1). */
1084 cris_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
1085 struct cris_unwind_cache *info)
1087 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1088 /* Present instruction. */
1089 unsigned short insn;
1091 /* Next instruction, lookahead. */
1092 unsigned short insn_next;
1095 /* Is there a push fp? */
1098 /* Number of byte on stack used for local variables and movem. */
1101 /* Highest register number in a movem. */
1104 /* move.d r<source_register>,rS */
1105 short source_register;
1110 /* This frame is with respect to a leaf until a push srp is found. */
1113 info->leaf_function = 1;
1116 /* Assume nothing on stack. */
1120 /* If we were called without a this_frame, that means we were called
1121 from cris_skip_prologue which already tried to find the end of the
1122 prologue through the symbol information. 64 instructions past current
1123 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
1124 limit = this_frame ? get_frame_pc (this_frame) : pc + 64;
1126 /* Find the prologue instructions. */
1127 while (pc > 0 && pc < limit)
1129 insn = read_memory_unsigned_integer (pc, 2);
1133 /* push <reg> 32 bit instruction */
1134 insn_next = read_memory_unsigned_integer (pc, 2);
1136 regno = cris_get_operand2 (insn_next);
1139 info->sp_offset += 4;
1141 /* This check, meant to recognize srp, used to be regno ==
1142 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
1143 if (insn_next == 0xBE7E)
1147 info->leaf_function = 0;
1150 else if (insn_next == 0x8FEE)
1155 info->r8_offset = info->sp_offset;
1159 else if (insn == 0x866E)
1164 info->uses_frame = 1;
1168 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1169 && cris_get_mode (insn) == 0x0000
1170 && cris_get_opcode (insn) == 0x000A)
1175 info->sp_offset += cris_get_quick_value (insn);
1178 else if (cris_get_mode (insn) == 0x0002
1179 && cris_get_opcode (insn) == 0x000F
1180 && cris_get_size (insn) == 0x0003
1181 && cris_get_operand1 (insn) == gdbarch_sp_regnum (gdbarch))
1183 /* movem r<regsave>,[sp] */
1184 regsave = cris_get_operand2 (insn);
1186 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1187 && ((insn & 0x0F00) >> 8) == 0x0001
1188 && (cris_get_signed_offset (insn) < 0))
1190 /* Immediate byte offset addressing prefix word with sp as base
1191 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1192 is between 64 and 128.
1193 movem r<regsave>,[sp=sp-<val>] */
1196 info->sp_offset += -cris_get_signed_offset (insn);
1198 insn_next = read_memory_unsigned_integer (pc, 2);
1200 if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE
1201 && cris_get_opcode (insn_next) == 0x000F
1202 && cris_get_size (insn_next) == 0x0003
1203 && cris_get_operand1 (insn_next) == gdbarch_sp_regnum
1206 regsave = cris_get_operand2 (insn_next);
1210 /* The prologue ended before the limit was reached. */
1215 else if (cris_get_mode (insn) == 0x0001
1216 && cris_get_opcode (insn) == 0x0009
1217 && cris_get_size (insn) == 0x0002)
1219 /* move.d r<10..13>,r<0..15> */
1220 source_register = cris_get_operand1 (insn);
1222 /* FIXME? In the glibc solibs, the prologue might contain something
1223 like (this example taken from relocate_doit):
1225 sub.d 0xfffef426,$r0
1226 which isn't covered by the source_register check below. Question
1227 is whether to add a check for this combo, or make better use of
1228 the limit variable instead. */
1229 if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM)
1231 /* The prologue ended before the limit was reached. */
1236 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1237 /* The size is a fixed-size. */
1238 && ((insn & 0x0F00) >> 8) == 0x0001
1239 /* A negative offset. */
1240 && (cris_get_signed_offset (insn) < 0))
1242 /* move.S rZ,[r8-U] (?) */
1243 insn_next = read_memory_unsigned_integer (pc, 2);
1245 regno = cris_get_operand2 (insn_next);
1246 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1247 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1248 && cris_get_opcode (insn_next) == 0x000F)
1250 /* move.S rZ,[r8-U] */
1255 /* The prologue ended before the limit was reached. */
1260 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1261 /* The size is a fixed-size. */
1262 && ((insn & 0x0F00) >> 8) == 0x0001
1263 /* A positive offset. */
1264 && (cris_get_signed_offset (insn) > 0))
1266 /* move.S [r8+U],rZ (?) */
1267 insn_next = read_memory_unsigned_integer (pc, 2);
1269 regno = cris_get_operand2 (insn_next);
1270 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1271 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1272 && cris_get_opcode (insn_next) == 0x0009
1273 && cris_get_operand1 (insn_next) == regno)
1275 /* move.S [r8+U],rZ */
1280 /* The prologue ended before the limit was reached. */
1287 /* The prologue ended before the limit was reached. */
1293 /* We only want to know the end of the prologue when this_frame and info
1294 are NULL (called from cris_skip_prologue i.e.). */
1295 if (this_frame == NULL && info == NULL)
1300 info->size = info->sp_offset;
1302 /* Compute the previous frame's stack pointer (which is also the
1303 frame's ID's stack address), and this frame's base pointer. */
1304 if (info->uses_frame)
1307 /* The SP was moved to the FP. This indicates that a new frame
1308 was created. Get THIS frame's FP value by unwinding it from
1310 this_base = get_frame_register_unsigned (this_frame, CRIS_FP_REGNUM);
1311 info->base = this_base;
1312 info->saved_regs[CRIS_FP_REGNUM].addr = info->base;
1314 /* The FP points at the last saved register. Adjust the FP back
1315 to before the first saved register giving the SP. */
1316 info->prev_sp = info->base + info->r8_offset;
1321 /* Assume that the FP is this frame's SP but with that pushed
1322 stack space added back. */
1323 this_base = get_frame_register_unsigned (this_frame,
1324 gdbarch_sp_regnum (gdbarch));
1325 info->base = this_base;
1326 info->prev_sp = info->base + info->size;
1329 /* Calculate the addresses for the saved registers on the stack. */
1330 /* FIXME: The address calculation should really be done on the fly while
1331 we're analyzing the prologue (we only hold one regsave value as it is
1333 val = info->sp_offset;
1335 for (regno = regsave; regno >= 0; regno--)
1337 info->saved_regs[regno].addr = info->base + info->r8_offset - val;
1341 /* The previous frame's SP needed to be computed. Save the computed
1343 trad_frame_set_value (info->saved_regs,
1344 gdbarch_sp_regnum (gdbarch), info->prev_sp);
1346 if (!info->leaf_function)
1348 /* SRP saved on the stack. But where? */
1349 if (info->r8_offset == 0)
1351 /* R8 not pushed yet. */
1352 info->saved_regs[SRP_REGNUM].addr = info->base;
1356 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1357 info->saved_regs[SRP_REGNUM].addr = info->base + 4;
1361 /* The PC is found in SRP (the actual register or located on the stack). */
1362 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1363 = info->saved_regs[SRP_REGNUM];
1369 crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
1370 struct cris_unwind_cache *info)
1372 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1375 /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not
1376 meant to be a full-fledged prologue scanner. It is only needed for
1377 the cases where we end up in code always lacking DWARF-2 CFI, notably:
1379 * PLT stubs (library calls)
1381 * signal trampolines
1383 For those cases, it is assumed that there is no actual prologue; that
1384 the stack pointer is not adjusted, and (as a consequence) the return
1385 address is not pushed onto the stack. */
1387 /* We only want to know the end of the prologue when this_frame and info
1388 are NULL (called from cris_skip_prologue i.e.). */
1389 if (this_frame == NULL && info == NULL)
1394 /* The SP is assumed to be unaltered. */
1395 this_base = get_frame_register_unsigned (this_frame,
1396 gdbarch_sp_regnum (gdbarch));
1397 info->base = this_base;
1398 info->prev_sp = this_base;
1400 /* The PC is assumed to be found in SRP. */
1401 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1402 = info->saved_regs[SRP_REGNUM];
1407 /* Advance pc beyond any function entry prologue instructions at pc
1408 to reach some "real" code. */
1410 /* Given a PC value corresponding to the start of a function, return the PC
1411 of the first instruction after the function prologue. */
1414 cris_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1416 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1417 CORE_ADDR func_addr, func_end;
1418 struct symtab_and_line sal;
1419 CORE_ADDR pc_after_prologue;
1421 /* If we have line debugging information, then the end of the prologue
1422 should the first assembly instruction of the first source line. */
1423 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1425 sal = find_pc_line (func_addr, 0);
1426 if (sal.end > 0 && sal.end < func_end)
1430 if (tdep->cris_version == 32)
1431 pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL);
1433 pc_after_prologue = cris_scan_prologue (pc, NULL, NULL);
1435 return pc_after_prologue;
1439 cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1442 pc = frame_unwind_register_unsigned (next_frame,
1443 gdbarch_pc_regnum (gdbarch));
1448 cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1451 sp = frame_unwind_register_unsigned (next_frame,
1452 gdbarch_sp_regnum (gdbarch));
1456 /* Use the program counter to determine the contents and size of a breakpoint
1457 instruction. It returns a pointer to a string of bytes that encode a
1458 breakpoint instruction, stores the length of the string to *lenptr, and
1459 adjusts pcptr (if necessary) to point to the actual memory location where
1460 the breakpoint should be inserted. */
1462 static const unsigned char *
1463 cris_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
1465 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1466 static unsigned char break8_insn[] = {0x38, 0xe9};
1467 static unsigned char break15_insn[] = {0x3f, 0xe9};
1470 if (tdep->cris_mode == cris_mode_guru)
1471 return break15_insn;
1476 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1480 cris_spec_reg_applicable (struct gdbarch *gdbarch,
1481 struct cris_spec_reg spec_reg)
1483 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1484 int version = tdep->cris_version;
1486 switch (spec_reg.applicable_version)
1488 case cris_ver_version_all:
1490 case cris_ver_warning:
1491 /* Indeterminate/obsolete. */
1494 return (version >= 0 && version <= 3);
1496 return (version >= 3);
1498 return (version == 8 || version == 9);
1500 return (version >= 8);
1501 case cris_ver_v0_10:
1502 return (version >= 0 && version <= 10);
1503 case cris_ver_v3_10:
1504 return (version >= 3 && version <= 10);
1505 case cris_ver_v8_10:
1506 return (version >= 8 && version <= 10);
1508 return (version == 10);
1510 return (version >= 10);
1512 return (version >= 32);
1514 /* Invalid cris version. */
1519 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1520 register, -1 for an invalid register. */
1523 cris_register_size (struct gdbarch *gdbarch, int regno)
1525 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1529 if (regno >= 0 && regno < NUM_GENREGS)
1531 /* General registers (R0 - R15) are 32 bits. */
1534 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1536 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1537 Adjust regno accordingly. */
1538 spec_regno = regno - NUM_GENREGS;
1540 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1542 if (cris_spec_regs[i].number == spec_regno
1543 && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i]))
1544 /* Go with the first applicable register. */
1545 return cris_spec_regs[i].reg_size;
1547 /* Special register not applicable to this CRIS version. */
1550 else if (regno >= gdbarch_pc_regnum (gdbarch)
1551 && regno < gdbarch_num_regs (gdbarch))
1553 /* This will apply to CRISv32 only where there are additional registers
1554 after the special registers (pseudo PC and support registers). */
1562 /* Nonzero if regno should not be fetched from the target. This is the case
1563 for unimplemented (size 0) and non-existant registers. */
1566 cris_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1568 return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1569 || (cris_register_size (gdbarch, regno) == 0));
1572 /* Nonzero if regno should not be written to the target, for various
1576 cris_cannot_store_register (struct gdbarch *gdbarch, int regno)
1578 /* There are three kinds of registers we refuse to write to.
1579 1. Those that not implemented.
1580 2. Those that are read-only (depends on the processor mode).
1581 3. Those registers to which a write has no effect.
1585 || regno >= gdbarch_num_regs (gdbarch)
1586 || cris_register_size (gdbarch, regno) == 0)
1587 /* Not implemented. */
1590 else if (regno == VR_REGNUM)
1594 else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM)
1595 /* Writing has no effect. */
1598 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
1599 agent decide whether they are writable. */
1604 /* Nonzero if regno should not be fetched from the target. This is the case
1605 for unimplemented (size 0) and non-existant registers. */
1608 crisv32_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1610 return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1611 || (cris_register_size (gdbarch, regno) == 0));
1614 /* Nonzero if regno should not be written to the target, for various
1618 crisv32_cannot_store_register (struct gdbarch *gdbarch, int regno)
1620 /* There are three kinds of registers we refuse to write to.
1621 1. Those that not implemented.
1622 2. Those that are read-only (depends on the processor mode).
1623 3. Those registers to which a write has no effect.
1627 || regno >= gdbarch_num_regs (gdbarch)
1628 || cris_register_size (gdbarch, regno) == 0)
1629 /* Not implemented. */
1632 else if (regno == VR_REGNUM)
1636 else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM)
1637 /* Writing has no effect. */
1640 /* Many special registers are read-only in user mode. Let the debug
1641 agent decide whether they are writable. */
1646 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1647 of data in register regno. */
1649 static struct type *
1650 cris_register_type (struct gdbarch *gdbarch, int regno)
1652 if (regno == gdbarch_pc_regnum (gdbarch))
1653 return builtin_type_void_func_ptr;
1654 else if (regno == gdbarch_sp_regnum (gdbarch)
1655 || regno == CRIS_FP_REGNUM)
1656 return builtin_type_void_data_ptr;
1657 else if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1658 || (regno >= MOF_REGNUM && regno <= USP_REGNUM))
1659 /* Note: R8 taken care of previous clause. */
1660 return builtin_type_uint32;
1661 else if (regno >= P4_REGNUM && regno <= CCR_REGNUM)
1662 return builtin_type_uint16;
1663 else if (regno >= P0_REGNUM && regno <= VR_REGNUM)
1664 return builtin_type_uint8;
1666 /* Invalid (unimplemented) register. */
1667 return builtin_type_int0;
1670 static struct type *
1671 crisv32_register_type (struct gdbarch *gdbarch, int regno)
1673 if (regno == gdbarch_pc_regnum (gdbarch))
1674 return builtin_type_void_func_ptr;
1675 else if (regno == gdbarch_sp_regnum (gdbarch)
1676 || regno == CRIS_FP_REGNUM)
1677 return builtin_type_void_data_ptr;
1678 else if ((regno >= 0 && regno <= ACR_REGNUM)
1679 || (regno >= EXS_REGNUM && regno <= SPC_REGNUM)
1680 || (regno == PID_REGNUM)
1681 || (regno >= S0_REGNUM && regno <= S15_REGNUM))
1682 /* Note: R8 and SP taken care of by previous clause. */
1683 return builtin_type_uint32;
1684 else if (regno == WZ_REGNUM)
1685 return builtin_type_uint16;
1686 else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM)
1687 return builtin_type_uint8;
1690 /* Invalid (unimplemented) register. Should not happen as there are
1691 no unimplemented CRISv32 registers. */
1692 warning (_("crisv32_register_type: unknown regno %d"), regno);
1693 return builtin_type_int0;
1697 /* Stores a function return value of type type, where valbuf is the address
1698 of the value to be stored. */
1700 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1703 cris_store_return_value (struct type *type, struct regcache *regcache,
1707 int len = TYPE_LENGTH (type);
1711 /* Put the return value in R10. */
1712 val = extract_unsigned_integer (valbuf, len);
1713 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1717 /* Put the return value in R10 and R11. */
1718 val = extract_unsigned_integer (valbuf, 4);
1719 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1720 val = extract_unsigned_integer ((char *)valbuf + 4, len - 4);
1721 regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val);
1724 error (_("cris_store_return_value: type length too large."));
1727 /* Return the name of register regno as a string. Return NULL for an invalid or
1728 unimplemented register. */
1731 cris_special_register_name (struct gdbarch *gdbarch, int regno)
1736 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1737 Adjust regno accordingly. */
1738 spec_regno = regno - NUM_GENREGS;
1740 /* Assume nothing about the layout of the cris_spec_regs struct
1742 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1744 if (cris_spec_regs[i].number == spec_regno
1745 && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i]))
1746 /* Go with the first applicable register. */
1747 return cris_spec_regs[i].name;
1749 /* Special register not applicable to this CRIS version. */
1754 cris_register_name (struct gdbarch *gdbarch, int regno)
1756 static char *cris_genreg_names[] =
1757 { "r0", "r1", "r2", "r3", \
1758 "r4", "r5", "r6", "r7", \
1759 "r8", "r9", "r10", "r11", \
1760 "r12", "r13", "sp", "pc" };
1762 if (regno >= 0 && regno < NUM_GENREGS)
1764 /* General register. */
1765 return cris_genreg_names[regno];
1767 else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (gdbarch))
1769 return cris_special_register_name (gdbarch, regno);
1773 /* Invalid register. */
1779 crisv32_register_name (struct gdbarch *gdbarch, int regno)
1781 static char *crisv32_genreg_names[] =
1782 { "r0", "r1", "r2", "r3", \
1783 "r4", "r5", "r6", "r7", \
1784 "r8", "r9", "r10", "r11", \
1785 "r12", "r13", "sp", "acr"
1788 static char *crisv32_sreg_names[] =
1789 { "s0", "s1", "s2", "s3", \
1790 "s4", "s5", "s6", "s7", \
1791 "s8", "s9", "s10", "s11", \
1792 "s12", "s13", "s14", "s15"
1795 if (regno >= 0 && regno < NUM_GENREGS)
1797 /* General register. */
1798 return crisv32_genreg_names[regno];
1800 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1802 return cris_special_register_name (gdbarch, regno);
1804 else if (regno == gdbarch_pc_regnum (gdbarch))
1808 else if (regno >= S0_REGNUM && regno <= S15_REGNUM)
1810 return crisv32_sreg_names[regno - S0_REGNUM];
1814 /* Invalid register. */
1819 /* Convert DWARF register number REG to the appropriate register
1820 number used by GDB. */
1823 cris_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1825 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1826 numbering, MOF is 18).
1827 Adapted from gcc/config/cris/cris.h. */
1828 static int cris_dwarf_regmap[] = {
1840 if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap))
1841 regnum = cris_dwarf_regmap[reg];
1844 warning (_("Unmapped DWARF Register #%d encountered."), reg);
1849 /* DWARF-2 frame support. */
1852 cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1853 struct dwarf2_frame_state_reg *reg,
1854 struct frame_info *this_frame)
1856 /* The return address column. */
1857 if (regnum == gdbarch_pc_regnum (gdbarch))
1858 reg->how = DWARF2_FRAME_REG_RA;
1860 /* The call frame address. */
1861 else if (regnum == gdbarch_sp_regnum (gdbarch))
1862 reg->how = DWARF2_FRAME_REG_CFA;
1865 /* Extract from an array regbuf containing the raw register state a function
1866 return value of type type, and copy that, in virtual format, into
1869 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1872 cris_extract_return_value (struct type *type, struct regcache *regcache,
1876 int len = TYPE_LENGTH (type);
1880 /* Get the return value from R10. */
1881 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1882 store_unsigned_integer (valbuf, len, val);
1886 /* Get the return value from R10 and R11. */
1887 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1888 store_unsigned_integer (valbuf, 4, val);
1889 regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val);
1890 store_unsigned_integer ((char *)valbuf + 4, len - 4, val);
1893 error (_("cris_extract_return_value: type length too large"));
1896 /* Handle the CRIS return value convention. */
1898 static enum return_value_convention
1899 cris_return_value (struct gdbarch *gdbarch, struct type *func_type,
1900 struct type *type, struct regcache *regcache,
1901 gdb_byte *readbuf, const gdb_byte *writebuf)
1903 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1904 || TYPE_CODE (type) == TYPE_CODE_UNION
1905 || TYPE_LENGTH (type) > 8)
1906 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1907 goes on the stack. */
1908 return RETURN_VALUE_STRUCT_CONVENTION;
1911 cris_extract_return_value (type, regcache, readbuf);
1913 cris_store_return_value (type, regcache, writebuf);
1915 return RETURN_VALUE_REGISTER_CONVENTION;
1918 /* Calculates a value that measures how good inst_args constraints an
1919 instruction. It stems from cris_constraint, found in cris-dis.c. */
1922 constraint (unsigned int insn, const signed char *inst_args,
1923 inst_env_type *inst_env)
1928 const char *s = inst_args;
1934 if ((insn & 0x30) == 0x30)
1939 /* A prefix operand. */
1940 if (inst_env->prefix_found)
1946 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1947 valid "push" size. In case of special register, it may be != 4. */
1948 if (inst_env->prefix_found)
1954 retval = (((insn >> 0xC) & 0xF) == (insn & 0xF));
1962 tmp = (insn >> 0xC) & 0xF;
1964 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1966 /* Since we match four bits, we will give a value of
1967 4 - 1 = 3 in a match. If there is a corresponding
1968 exact match of a special register in another pattern, it
1969 will get a value of 4, which will be higher. This should
1970 be correct in that an exact pattern would match better that
1972 Note that there is a reason for not returning zero; the
1973 pattern for "clear" is partly matched in the bit-pattern
1974 (the two lower bits must be zero), while the bit-pattern
1975 for a move from a special register is matched in the
1976 register constraint.
1977 This also means we will will have a race condition if
1978 there is a partly match in three bits in the bit pattern. */
1979 if (tmp == cris_spec_regs[i].number)
1986 if (cris_spec_regs[i].name == NULL)
1993 /* Returns the number of bits set in the variable value. */
1996 number_of_bits (unsigned int value)
1998 int number_of_bits = 0;
2002 number_of_bits += 1;
2003 value &= (value - 1);
2005 return number_of_bits;
2008 /* Finds the address that should contain the single step breakpoint(s).
2009 It stems from code in cris-dis.c. */
2012 find_cris_op (unsigned short insn, inst_env_type *inst_env)
2015 int max_level_of_match = -1;
2016 int max_matched = -1;
2019 for (i = 0; cris_opcodes[i].name != NULL; i++)
2021 if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match)
2022 && ((cris_opcodes[i].lose & insn) == 0)
2023 /* Only CRISv10 instructions, please. */
2024 && (cris_opcodes[i].applicable_version != cris_ver_v32p))
2026 level_of_match = constraint (insn, cris_opcodes[i].args, inst_env);
2027 if (level_of_match >= 0)
2030 number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose);
2031 if (level_of_match > max_level_of_match)
2034 max_level_of_match = level_of_match;
2035 if (level_of_match == 16)
2037 /* All bits matched, cannot find better. */
2047 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
2048 actually an internal error. */
2051 find_step_target (struct frame_info *frame, inst_env_type *inst_env)
2055 unsigned short insn;
2056 struct gdbarch *gdbarch = get_frame_arch (frame);
2058 /* Create a local register image and set the initial state. */
2059 for (i = 0; i < NUM_GENREGS; i++)
2062 (unsigned long) get_frame_register_unsigned (frame, i);
2064 offset = NUM_GENREGS;
2065 for (i = 0; i < NUM_SPECREGS; i++)
2068 (unsigned long) get_frame_register_unsigned (frame, offset + i);
2070 inst_env->branch_found = 0;
2071 inst_env->slot_needed = 0;
2072 inst_env->delay_slot_pc_active = 0;
2073 inst_env->prefix_found = 0;
2074 inst_env->invalid = 0;
2075 inst_env->xflag_found = 0;
2076 inst_env->disable_interrupt = 0;
2078 /* Look for a step target. */
2081 /* Read an instruction from the client. */
2082 insn = read_memory_unsigned_integer
2083 (inst_env->reg[gdbarch_pc_regnum (gdbarch)], 2);
2085 /* If the instruction is not in a delay slot the new content of the
2086 PC is [PC] + 2. If the instruction is in a delay slot it is not
2087 that simple. Since a instruction in a delay slot cannot change
2088 the content of the PC, it does not matter what value PC will have.
2089 Just make sure it is a valid instruction. */
2090 if (!inst_env->delay_slot_pc_active)
2092 inst_env->reg[gdbarch_pc_regnum (gdbarch)] += 2;
2096 inst_env->delay_slot_pc_active = 0;
2097 inst_env->reg[gdbarch_pc_regnum (gdbarch)]
2098 = inst_env->delay_slot_pc;
2100 /* Analyse the present instruction. */
2101 i = find_cris_op (insn, inst_env);
2104 inst_env->invalid = 1;
2108 cris_gdb_func (gdbarch, cris_opcodes[i].op, insn, inst_env);
2110 } while (!inst_env->invalid
2111 && (inst_env->prefix_found || inst_env->xflag_found
2112 || inst_env->slot_needed));
2116 /* There is no hardware single-step support. The function find_step_target
2117 digs through the opcodes in order to find all possible targets.
2118 Either one ordinary target or two targets for branches may be found. */
2121 cris_software_single_step (struct frame_info *frame)
2123 inst_env_type inst_env;
2125 /* Analyse the present instruction environment and insert
2127 int status = find_step_target (frame, &inst_env);
2130 /* Could not find a target. Things are likely to go downhill
2132 warning (_("CRIS software single step could not find a step target."));
2136 /* Insert at most two breakpoints. One for the next PC content
2137 and possibly another one for a branch, jump, etc. */
2139 (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (get_frame_arch (frame))];
2140 insert_single_step_breakpoint (next_pc);
2141 if (inst_env.branch_found
2142 && (CORE_ADDR) inst_env.branch_break_address != next_pc)
2144 CORE_ADDR branch_target_address
2145 = (CORE_ADDR) inst_env.branch_break_address;
2146 insert_single_step_breakpoint (branch_target_address);
2153 /* Calculates the prefix value for quick offset addressing mode. */
2156 quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2158 /* It's invalid to be in a delay slot. You can't have a prefix to this
2159 instruction (not 100% sure). */
2160 if (inst_env->slot_needed || inst_env->prefix_found)
2162 inst_env->invalid = 1;
2166 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2167 inst_env->prefix_value += cris_get_bdap_quick_offset (inst);
2169 /* A prefix doesn't change the xflag_found. But the rest of the flags
2171 inst_env->slot_needed = 0;
2172 inst_env->prefix_found = 1;
2175 /* Updates the autoincrement register. The size of the increment is derived
2176 from the size of the operation. The PC is always kept aligned on even
2180 process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env)
2182 if (size == INST_BYTE_SIZE)
2184 inst_env->reg[cris_get_operand1 (inst)] += 1;
2186 /* The PC must be word aligned, so increase the PC with one
2187 word even if the size is byte. */
2188 if (cris_get_operand1 (inst) == REG_PC)
2190 inst_env->reg[REG_PC] += 1;
2193 else if (size == INST_WORD_SIZE)
2195 inst_env->reg[cris_get_operand1 (inst)] += 2;
2197 else if (size == INST_DWORD_SIZE)
2199 inst_env->reg[cris_get_operand1 (inst)] += 4;
2204 inst_env->invalid = 1;
2208 /* Just a forward declaration. */
2210 static unsigned long get_data_from_address (unsigned short *inst,
2213 /* Calculates the prefix value for the general case of offset addressing
2217 bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2222 /* It's invalid to be in a delay slot. */
2223 if (inst_env->slot_needed || inst_env->prefix_found)
2225 inst_env->invalid = 1;
2229 /* The calculation of prefix_value used to be after process_autoincrement,
2230 but that fails for an instruction such as jsr [$r0+12] which is encoded
2231 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
2232 mustn't be incremented until we have read it and what it points at. */
2233 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2235 /* The offset is an indirection of the contents of the operand1 register. */
2236 inst_env->prefix_value +=
2237 get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)]);
2239 if (cris_get_mode (inst) == AUTOINC_MODE)
2241 process_autoincrement (cris_get_size (inst), inst, inst_env);
2244 /* A prefix doesn't change the xflag_found. But the rest of the flags
2246 inst_env->slot_needed = 0;
2247 inst_env->prefix_found = 1;
2250 /* Calculates the prefix value for the index addressing mode. */
2253 biap_prefix (unsigned short inst, inst_env_type *inst_env)
2255 /* It's invalid to be in a delay slot. I can't see that it's possible to
2256 have a prefix to this instruction. So I will treat this as invalid. */
2257 if (inst_env->slot_needed || inst_env->prefix_found)
2259 inst_env->invalid = 1;
2263 inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)];
2265 /* The offset is the operand2 value shifted the size of the instruction
2267 inst_env->prefix_value +=
2268 inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst);
2270 /* If the PC is operand1 (base) the address used is the address after
2271 the main instruction, i.e. address + 2 (the PC is already compensated
2272 for the prefix operation). */
2273 if (cris_get_operand1 (inst) == REG_PC)
2275 inst_env->prefix_value += 2;
2278 /* A prefix doesn't change the xflag_found. But the rest of the flags
2280 inst_env->slot_needed = 0;
2281 inst_env->xflag_found = 0;
2282 inst_env->prefix_found = 1;
2285 /* Calculates the prefix value for the double indirect addressing mode. */
2288 dip_prefix (unsigned short inst, inst_env_type *inst_env)
2293 /* It's invalid to be in a delay slot. */
2294 if (inst_env->slot_needed || inst_env->prefix_found)
2296 inst_env->invalid = 1;
2300 /* The prefix value is one dereference of the contents of the operand1
2302 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2303 inst_env->prefix_value = read_memory_unsigned_integer (address, 4);
2305 /* Check if the mode is autoincrement. */
2306 if (cris_get_mode (inst) == AUTOINC_MODE)
2308 inst_env->reg[cris_get_operand1 (inst)] += 4;
2311 /* A prefix doesn't change the xflag_found. But the rest of the flags
2313 inst_env->slot_needed = 0;
2314 inst_env->xflag_found = 0;
2315 inst_env->prefix_found = 1;
2318 /* Finds the destination for a branch with 8-bits offset. */
2321 eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2326 /* If we have a prefix or are in a delay slot it's bad. */
2327 if (inst_env->slot_needed || inst_env->prefix_found)
2329 inst_env->invalid = 1;
2333 /* We have a branch, find out where the branch will land. */
2334 offset = cris_get_branch_short_offset (inst);
2336 /* Check if the offset is signed. */
2337 if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK)
2342 /* The offset ends with the sign bit, set it to zero. The address
2343 should always be word aligned. */
2344 offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK;
2346 inst_env->branch_found = 1;
2347 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2349 inst_env->slot_needed = 1;
2350 inst_env->prefix_found = 0;
2351 inst_env->xflag_found = 0;
2352 inst_env->disable_interrupt = 1;
2355 /* Finds the destination for a branch with 16-bits offset. */
2358 sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2362 /* If we have a prefix or is in a delay slot it's bad. */
2363 if (inst_env->slot_needed || inst_env->prefix_found)
2365 inst_env->invalid = 1;
2369 /* We have a branch, find out the offset for the branch. */
2370 offset = read_memory_integer (inst_env->reg[REG_PC], 2);
2372 /* The instruction is one word longer than normal, so add one word
2374 inst_env->reg[REG_PC] += 2;
2376 inst_env->branch_found = 1;
2377 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2380 inst_env->slot_needed = 1;
2381 inst_env->prefix_found = 0;
2382 inst_env->xflag_found = 0;
2383 inst_env->disable_interrupt = 1;
2386 /* Handles the ABS instruction. */
2389 abs_op (unsigned short inst, inst_env_type *inst_env)
2394 /* ABS can't have a prefix, so it's bad if it does. */
2395 if (inst_env->prefix_found)
2397 inst_env->invalid = 1;
2401 /* Check if the operation affects the PC. */
2402 if (cris_get_operand2 (inst) == REG_PC)
2405 /* It's invalid to change to the PC if we are in a delay slot. */
2406 if (inst_env->slot_needed)
2408 inst_env->invalid = 1;
2412 value = (long) inst_env->reg[REG_PC];
2414 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
2415 if (value != SIGNED_DWORD_MASK)
2418 inst_env->reg[REG_PC] = (long) value;
2422 inst_env->slot_needed = 0;
2423 inst_env->prefix_found = 0;
2424 inst_env->xflag_found = 0;
2425 inst_env->disable_interrupt = 0;
2428 /* Handles the ADDI instruction. */
2431 addi_op (unsigned short inst, inst_env_type *inst_env)
2433 /* It's invalid to have the PC as base register. And ADDI can't have
2435 if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC))
2437 inst_env->invalid = 1;
2441 inst_env->slot_needed = 0;
2442 inst_env->prefix_found = 0;
2443 inst_env->xflag_found = 0;
2444 inst_env->disable_interrupt = 0;
2447 /* Handles the ASR instruction. */
2450 asr_op (unsigned short inst, inst_env_type *inst_env)
2453 unsigned long value;
2454 unsigned long signed_extend_mask = 0;
2456 /* ASR can't have a prefix, so check that it doesn't. */
2457 if (inst_env->prefix_found)
2459 inst_env->invalid = 1;
2463 /* Check if the PC is the target register. */
2464 if (cris_get_operand2 (inst) == REG_PC)
2466 /* It's invalid to change the PC in a delay slot. */
2467 if (inst_env->slot_needed)
2469 inst_env->invalid = 1;
2472 /* Get the number of bits to shift. */
2473 shift_steps = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]);
2474 value = inst_env->reg[REG_PC];
2476 /* Find out how many bits the operation should apply to. */
2477 if (cris_get_size (inst) == INST_BYTE_SIZE)
2479 if (value & SIGNED_BYTE_MASK)
2481 signed_extend_mask = 0xFF;
2482 signed_extend_mask = signed_extend_mask >> shift_steps;
2483 signed_extend_mask = ~signed_extend_mask;
2485 value = value >> shift_steps;
2486 value |= signed_extend_mask;
2488 inst_env->reg[REG_PC] &= 0xFFFFFF00;
2489 inst_env->reg[REG_PC] |= value;
2491 else if (cris_get_size (inst) == INST_WORD_SIZE)
2493 if (value & SIGNED_WORD_MASK)
2495 signed_extend_mask = 0xFFFF;
2496 signed_extend_mask = signed_extend_mask >> shift_steps;
2497 signed_extend_mask = ~signed_extend_mask;
2499 value = value >> shift_steps;
2500 value |= signed_extend_mask;
2502 inst_env->reg[REG_PC] &= 0xFFFF0000;
2503 inst_env->reg[REG_PC] |= value;
2505 else if (cris_get_size (inst) == INST_DWORD_SIZE)
2507 if (value & SIGNED_DWORD_MASK)
2509 signed_extend_mask = 0xFFFFFFFF;
2510 signed_extend_mask = signed_extend_mask >> shift_steps;
2511 signed_extend_mask = ~signed_extend_mask;
2513 value = value >> shift_steps;
2514 value |= signed_extend_mask;
2515 inst_env->reg[REG_PC] = value;
2518 inst_env->slot_needed = 0;
2519 inst_env->prefix_found = 0;
2520 inst_env->xflag_found = 0;
2521 inst_env->disable_interrupt = 0;
2524 /* Handles the ASRQ instruction. */
2527 asrq_op (unsigned short inst, inst_env_type *inst_env)
2531 unsigned long value;
2532 unsigned long signed_extend_mask = 0;
2534 /* ASRQ can't have a prefix, so check that it doesn't. */
2535 if (inst_env->prefix_found)
2537 inst_env->invalid = 1;
2541 /* Check if the PC is the target register. */
2542 if (cris_get_operand2 (inst) == REG_PC)
2545 /* It's invalid to change the PC in a delay slot. */
2546 if (inst_env->slot_needed)
2548 inst_env->invalid = 1;
2551 /* The shift size is given as a 5 bit quick value, i.e. we don't
2552 want the the sign bit of the quick value. */
2553 shift_steps = cris_get_asr_shift_steps (inst);
2554 value = inst_env->reg[REG_PC];
2555 if (value & SIGNED_DWORD_MASK)
2557 signed_extend_mask = 0xFFFFFFFF;
2558 signed_extend_mask = signed_extend_mask >> shift_steps;
2559 signed_extend_mask = ~signed_extend_mask;
2561 value = value >> shift_steps;
2562 value |= signed_extend_mask;
2563 inst_env->reg[REG_PC] = value;
2565 inst_env->slot_needed = 0;
2566 inst_env->prefix_found = 0;
2567 inst_env->xflag_found = 0;
2568 inst_env->disable_interrupt = 0;
2571 /* Handles the AX, EI and SETF instruction. */
2574 ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env)
2576 if (inst_env->prefix_found)
2578 inst_env->invalid = 1;
2581 /* Check if the instruction is setting the X flag. */
2582 if (cris_is_xflag_bit_on (inst))
2584 inst_env->xflag_found = 1;
2588 inst_env->xflag_found = 0;
2590 inst_env->slot_needed = 0;
2591 inst_env->prefix_found = 0;
2592 inst_env->disable_interrupt = 1;
2595 /* Checks if the instruction is in assign mode. If so, it updates the assign
2596 register. Note that check_assign assumes that the caller has checked that
2597 there is a prefix to this instruction. The mode check depends on this. */
2600 check_assign (unsigned short inst, inst_env_type *inst_env)
2602 /* Check if it's an assign addressing mode. */
2603 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2605 /* Assign the prefix value to operand 1. */
2606 inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value;
2610 /* Handles the 2-operand BOUND instruction. */
2613 two_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2615 /* It's invalid to have the PC as the index operand. */
2616 if (cris_get_operand2 (inst) == REG_PC)
2618 inst_env->invalid = 1;
2621 /* Check if we have a prefix. */
2622 if (inst_env->prefix_found)
2624 check_assign (inst, inst_env);
2626 /* Check if this is an autoincrement mode. */
2627 else if (cris_get_mode (inst) == AUTOINC_MODE)
2629 /* It's invalid to change the PC in a delay slot. */
2630 if (inst_env->slot_needed)
2632 inst_env->invalid = 1;
2635 process_autoincrement (cris_get_size (inst), inst, inst_env);
2637 inst_env->slot_needed = 0;
2638 inst_env->prefix_found = 0;
2639 inst_env->xflag_found = 0;
2640 inst_env->disable_interrupt = 0;
2643 /* Handles the 3-operand BOUND instruction. */
2646 three_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2648 /* It's an error if we haven't got a prefix. And it's also an error
2649 if the PC is the destination register. */
2650 if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC))
2652 inst_env->invalid = 1;
2655 inst_env->slot_needed = 0;
2656 inst_env->prefix_found = 0;
2657 inst_env->xflag_found = 0;
2658 inst_env->disable_interrupt = 0;
2661 /* Clears the status flags in inst_env. */
2664 btst_nop_op (unsigned short inst, inst_env_type *inst_env)
2666 /* It's an error if we have got a prefix. */
2667 if (inst_env->prefix_found)
2669 inst_env->invalid = 1;
2673 inst_env->slot_needed = 0;
2674 inst_env->prefix_found = 0;
2675 inst_env->xflag_found = 0;
2676 inst_env->disable_interrupt = 0;
2679 /* Clears the status flags in inst_env. */
2682 clearf_di_op (unsigned short inst, inst_env_type *inst_env)
2684 /* It's an error if we have got a prefix. */
2685 if (inst_env->prefix_found)
2687 inst_env->invalid = 1;
2691 inst_env->slot_needed = 0;
2692 inst_env->prefix_found = 0;
2693 inst_env->xflag_found = 0;
2694 inst_env->disable_interrupt = 1;
2697 /* Handles the CLEAR instruction if it's in register mode. */
2700 reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env)
2702 /* Check if the target is the PC. */
2703 if (cris_get_operand2 (inst) == REG_PC)
2705 /* The instruction will clear the instruction's size bits. */
2706 int clear_size = cris_get_clear_size (inst);
2707 if (clear_size == INST_BYTE_SIZE)
2709 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00;
2711 if (clear_size == INST_WORD_SIZE)
2713 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000;
2715 if (clear_size == INST_DWORD_SIZE)
2717 inst_env->delay_slot_pc = 0x0;
2719 /* The jump will be delayed with one delay slot. So we need a delay
2721 inst_env->slot_needed = 1;
2722 inst_env->delay_slot_pc_active = 1;
2726 /* The PC will not change => no delay slot. */
2727 inst_env->slot_needed = 0;
2729 inst_env->prefix_found = 0;
2730 inst_env->xflag_found = 0;
2731 inst_env->disable_interrupt = 0;
2734 /* Handles the TEST instruction if it's in register mode. */
2737 reg_mode_test_op (unsigned short inst, inst_env_type *inst_env)
2739 /* It's an error if we have got a prefix. */
2740 if (inst_env->prefix_found)
2742 inst_env->invalid = 1;
2745 inst_env->slot_needed = 0;
2746 inst_env->prefix_found = 0;
2747 inst_env->xflag_found = 0;
2748 inst_env->disable_interrupt = 0;
2752 /* Handles the CLEAR and TEST instruction if the instruction isn't
2753 in register mode. */
2756 none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env)
2758 /* Check if we are in a prefix mode. */
2759 if (inst_env->prefix_found)
2761 /* The only way the PC can change is if this instruction is in
2762 assign addressing mode. */
2763 check_assign (inst, inst_env);
2765 /* Indirect mode can't change the PC so just check if the mode is
2767 else if (cris_get_mode (inst) == AUTOINC_MODE)
2769 process_autoincrement (cris_get_size (inst), inst, inst_env);
2771 inst_env->slot_needed = 0;
2772 inst_env->prefix_found = 0;
2773 inst_env->xflag_found = 0;
2774 inst_env->disable_interrupt = 0;
2777 /* Checks that the PC isn't the destination register or the instructions has
2781 dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env)
2783 /* It's invalid to have the PC as the destination. The instruction can't
2785 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2787 inst_env->invalid = 1;
2791 inst_env->slot_needed = 0;
2792 inst_env->prefix_found = 0;
2793 inst_env->xflag_found = 0;
2794 inst_env->disable_interrupt = 0;
2797 /* Checks that the instruction doesn't have a prefix. */
2800 break_op (unsigned short inst, inst_env_type *inst_env)
2802 /* The instruction can't have a prefix. */
2803 if (inst_env->prefix_found)
2805 inst_env->invalid = 1;
2809 inst_env->slot_needed = 0;
2810 inst_env->prefix_found = 0;
2811 inst_env->xflag_found = 0;
2812 inst_env->disable_interrupt = 1;
2815 /* Checks that the PC isn't the destination register and that the instruction
2816 doesn't have a prefix. */
2819 scc_op (unsigned short inst, inst_env_type *inst_env)
2821 /* It's invalid to have the PC as the destination. The instruction can't
2823 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2825 inst_env->invalid = 1;
2829 inst_env->slot_needed = 0;
2830 inst_env->prefix_found = 0;
2831 inst_env->xflag_found = 0;
2832 inst_env->disable_interrupt = 1;
2835 /* Handles the register mode JUMP instruction. */
2838 reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2840 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2841 you can't have a prefix. */
2842 if ((inst_env->slot_needed) || (inst_env->prefix_found))
2844 inst_env->invalid = 1;
2848 /* Just change the PC. */
2849 inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)];
2850 inst_env->slot_needed = 0;
2851 inst_env->prefix_found = 0;
2852 inst_env->xflag_found = 0;
2853 inst_env->disable_interrupt = 1;
2856 /* Handles the JUMP instruction for all modes except register. */
2859 none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2861 unsigned long newpc;
2864 /* It's invalid to do a JUMP in a delay slot. */
2865 if (inst_env->slot_needed)
2867 inst_env->invalid = 1;
2871 /* Check if we have a prefix. */
2872 if (inst_env->prefix_found)
2874 check_assign (inst, inst_env);
2876 /* Get the new value for the the PC. */
2878 read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value,
2883 /* Get the new value for the PC. */
2884 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2885 newpc = read_memory_unsigned_integer (address, 4);
2887 /* Check if we should increment a register. */
2888 if (cris_get_mode (inst) == AUTOINC_MODE)
2890 inst_env->reg[cris_get_operand1 (inst)] += 4;
2893 inst_env->reg[REG_PC] = newpc;
2895 inst_env->slot_needed = 0;
2896 inst_env->prefix_found = 0;
2897 inst_env->xflag_found = 0;
2898 inst_env->disable_interrupt = 1;
2901 /* Handles moves to special registers (aka P-register) for all modes. */
2904 move_to_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2905 inst_env_type *inst_env)
2907 if (inst_env->prefix_found)
2909 /* The instruction has a prefix that means we are only interested if
2910 the instruction is in assign mode. */
2911 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2913 /* The prefix handles the problem if we are in a delay slot. */
2914 if (cris_get_operand1 (inst) == REG_PC)
2916 /* Just take care of the assign. */
2917 check_assign (inst, inst_env);
2921 else if (cris_get_mode (inst) == AUTOINC_MODE)
2923 /* The instruction doesn't have a prefix, the only case left that we
2924 are interested in is the autoincrement mode. */
2925 if (cris_get_operand1 (inst) == REG_PC)
2927 /* If the PC is to be incremented it's invalid to be in a
2929 if (inst_env->slot_needed)
2931 inst_env->invalid = 1;
2935 /* The increment depends on the size of the special register. */
2936 if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
2938 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2940 else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
2942 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2946 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2950 inst_env->slot_needed = 0;
2951 inst_env->prefix_found = 0;
2952 inst_env->xflag_found = 0;
2953 inst_env->disable_interrupt = 1;
2956 /* Handles moves from special registers (aka P-register) for all modes
2960 none_reg_mode_move_from_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2961 inst_env_type *inst_env)
2963 if (inst_env->prefix_found)
2965 /* The instruction has a prefix that means we are only interested if
2966 the instruction is in assign mode. */
2967 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2969 /* The prefix handles the problem if we are in a delay slot. */
2970 if (cris_get_operand1 (inst) == REG_PC)
2972 /* Just take care of the assign. */
2973 check_assign (inst, inst_env);
2977 /* The instruction doesn't have a prefix, the only case left that we
2978 are interested in is the autoincrement mode. */
2979 else if (cris_get_mode (inst) == AUTOINC_MODE)
2981 if (cris_get_operand1 (inst) == REG_PC)
2983 /* If the PC is to be incremented it's invalid to be in a
2985 if (inst_env->slot_needed)
2987 inst_env->invalid = 1;
2991 /* The increment depends on the size of the special register. */
2992 if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
2994 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2996 else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
2998 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
3002 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
3006 inst_env->slot_needed = 0;
3007 inst_env->prefix_found = 0;
3008 inst_env->xflag_found = 0;
3009 inst_env->disable_interrupt = 1;
3012 /* Handles moves from special registers (aka P-register) when the mode
3016 reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env)
3018 /* Register mode move from special register can't have a prefix. */
3019 if (inst_env->prefix_found)
3021 inst_env->invalid = 1;
3025 if (cris_get_operand1 (inst) == REG_PC)
3027 /* It's invalid to change the PC in a delay slot. */
3028 if (inst_env->slot_needed)
3030 inst_env->invalid = 1;
3033 /* The destination is the PC, the jump will have a delay slot. */
3034 inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)];
3035 inst_env->slot_needed = 1;
3036 inst_env->delay_slot_pc_active = 1;
3040 /* If the destination isn't PC, there will be no jump. */
3041 inst_env->slot_needed = 0;
3043 inst_env->prefix_found = 0;
3044 inst_env->xflag_found = 0;
3045 inst_env->disable_interrupt = 1;
3048 /* Handles the MOVEM from memory to general register instruction. */
3051 move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env)
3053 if (inst_env->prefix_found)
3055 /* The prefix handles the problem if we are in a delay slot. Is the
3056 MOVEM instruction going to change the PC? */
3057 if (cris_get_operand2 (inst) >= REG_PC)
3059 inst_env->reg[REG_PC] =
3060 read_memory_unsigned_integer (inst_env->prefix_value, 4);
3062 /* The assign value is the value after the increment. Normally, the
3063 assign value is the value before the increment. */
3064 if ((cris_get_operand1 (inst) == REG_PC)
3065 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3067 inst_env->reg[REG_PC] = inst_env->prefix_value;
3068 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3073 /* Is the MOVEM instruction going to change the PC? */
3074 if (cris_get_operand2 (inst) == REG_PC)
3076 /* It's invalid to change the PC in a delay slot. */
3077 if (inst_env->slot_needed)
3079 inst_env->invalid = 1;
3082 inst_env->reg[REG_PC] =
3083 read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)],
3086 /* The increment is not depending on the size, instead it's depending
3087 on the number of registers loaded from memory. */
3088 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3090 /* It's invalid to change the PC in a delay slot. */
3091 if (inst_env->slot_needed)
3093 inst_env->invalid = 1;
3096 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3099 inst_env->slot_needed = 0;
3100 inst_env->prefix_found = 0;
3101 inst_env->xflag_found = 0;
3102 inst_env->disable_interrupt = 0;
3105 /* Handles the MOVEM to memory from general register instruction. */
3108 move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env)
3110 if (inst_env->prefix_found)
3112 /* The assign value is the value after the increment. Normally, the
3113 assign value is the value before the increment. */
3114 if ((cris_get_operand1 (inst) == REG_PC) &&
3115 (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3117 /* The prefix handles the problem if we are in a delay slot. */
3118 inst_env->reg[REG_PC] = inst_env->prefix_value;
3119 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3124 /* The increment is not depending on the size, instead it's depending
3125 on the number of registers loaded to memory. */
3126 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3128 /* It's invalid to change the PC in a delay slot. */
3129 if (inst_env->slot_needed)
3131 inst_env->invalid = 1;
3134 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3137 inst_env->slot_needed = 0;
3138 inst_env->prefix_found = 0;
3139 inst_env->xflag_found = 0;
3140 inst_env->disable_interrupt = 0;
3143 /* Handles the intructions that's not yet implemented, by setting
3144 inst_env->invalid to true. */
3147 not_implemented_op (unsigned short inst, inst_env_type *inst_env)
3149 inst_env->invalid = 1;
3152 /* Handles the XOR instruction. */
3155 xor_op (unsigned short inst, inst_env_type *inst_env)
3157 /* XOR can't have a prefix. */
3158 if (inst_env->prefix_found)
3160 inst_env->invalid = 1;
3164 /* Check if the PC is the target. */
3165 if (cris_get_operand2 (inst) == REG_PC)
3167 /* It's invalid to change the PC in a delay slot. */
3168 if (inst_env->slot_needed)
3170 inst_env->invalid = 1;
3173 inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)];
3175 inst_env->slot_needed = 0;
3176 inst_env->prefix_found = 0;
3177 inst_env->xflag_found = 0;
3178 inst_env->disable_interrupt = 0;
3181 /* Handles the MULS instruction. */
3184 muls_op (unsigned short inst, inst_env_type *inst_env)
3186 /* MULS/U can't have a prefix. */
3187 if (inst_env->prefix_found)
3189 inst_env->invalid = 1;
3193 /* Consider it invalid if the PC is the target. */
3194 if (cris_get_operand2 (inst) == REG_PC)
3196 inst_env->invalid = 1;
3199 inst_env->slot_needed = 0;
3200 inst_env->prefix_found = 0;
3201 inst_env->xflag_found = 0;
3202 inst_env->disable_interrupt = 0;
3205 /* Handles the MULU instruction. */
3208 mulu_op (unsigned short inst, inst_env_type *inst_env)
3210 /* MULS/U can't have a prefix. */
3211 if (inst_env->prefix_found)
3213 inst_env->invalid = 1;
3217 /* Consider it invalid if the PC is the target. */
3218 if (cris_get_operand2 (inst) == REG_PC)
3220 inst_env->invalid = 1;
3223 inst_env->slot_needed = 0;
3224 inst_env->prefix_found = 0;
3225 inst_env->xflag_found = 0;
3226 inst_env->disable_interrupt = 0;
3229 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
3230 The MOVE instruction is the move from source to register. */
3233 add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env,
3234 unsigned long source1, unsigned long source2)
3236 unsigned long pc_mask;
3237 unsigned long operation_mask;
3239 /* Find out how many bits the operation should apply to. */
3240 if (cris_get_size (inst) == INST_BYTE_SIZE)
3242 pc_mask = 0xFFFFFF00;
3243 operation_mask = 0xFF;
3245 else if (cris_get_size (inst) == INST_WORD_SIZE)
3247 pc_mask = 0xFFFF0000;
3248 operation_mask = 0xFFFF;
3250 else if (cris_get_size (inst) == INST_DWORD_SIZE)
3253 operation_mask = 0xFFFFFFFF;
3257 /* The size is out of range. */
3258 inst_env->invalid = 1;
3262 /* The instruction just works on uw_operation_mask bits. */
3263 source2 &= operation_mask;
3264 source1 &= operation_mask;
3266 /* Now calculate the result. The opcode's 3 first bits separates
3267 the different actions. */
3268 switch (cris_get_opcode (inst) & 7)
3278 case 2: /* subtract */
3282 case 3: /* compare */
3294 inst_env->invalid = 1;
3300 /* Make sure that the result doesn't contain more than the instruction
3302 source2 &= operation_mask;
3304 /* Calculate the new breakpoint address. */
3305 inst_env->reg[REG_PC] &= pc_mask;
3306 inst_env->reg[REG_PC] |= source1;
3310 /* Extends the value from either byte or word size to a dword. If the mode
3311 is zero extend then the value is extended with zero. If instead the mode
3312 is signed extend the sign bit of the value is taken into consideration. */
3314 static unsigned long
3315 do_sign_or_zero_extend (unsigned long value, unsigned short *inst)
3317 /* The size can be either byte or word, check which one it is.
3318 Don't check the highest bit, it's indicating if it's a zero
3320 if (cris_get_size (*inst) & INST_WORD_SIZE)
3325 /* Check if the instruction is signed extend. If so, check if value has
3327 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK))
3329 value |= SIGNED_WORD_EXTEND_MASK;
3337 /* Check if the instruction is signed extend. If so, check if value has
3339 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK))
3341 value |= SIGNED_BYTE_EXTEND_MASK;
3344 /* The size should now be dword. */
3345 cris_set_size_to_dword (inst);
3349 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3350 instruction. The MOVE instruction is the move from source to register. */
3353 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3354 inst_env_type *inst_env)
3356 unsigned long operand1;
3357 unsigned long operand2;
3359 /* It's invalid to have a prefix to the instruction. This is a register
3360 mode instruction and can't have a prefix. */
3361 if (inst_env->prefix_found)
3363 inst_env->invalid = 1;
3366 /* Check if the instruction has PC as its target. */
3367 if (cris_get_operand2 (inst) == REG_PC)
3369 if (inst_env->slot_needed)
3371 inst_env->invalid = 1;
3374 /* The instruction has the PC as its target register. */
3375 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3376 operand2 = inst_env->reg[REG_PC];
3378 /* Check if it's a extend, signed or zero instruction. */
3379 if (cris_get_opcode (inst) < 4)
3381 operand1 = do_sign_or_zero_extend (operand1, &inst);
3383 /* Calculate the PC value after the instruction, i.e. where the
3384 breakpoint should be. The order of the udw_operands is vital. */
3385 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3387 inst_env->slot_needed = 0;
3388 inst_env->prefix_found = 0;
3389 inst_env->xflag_found = 0;
3390 inst_env->disable_interrupt = 0;
3393 /* Returns the data contained at address. The size of the data is derived from
3394 the size of the operation. If the instruction is a zero or signed
3395 extend instruction, the size field is changed in instruction. */
3397 static unsigned long
3398 get_data_from_address (unsigned short *inst, CORE_ADDR address)
3400 int size = cris_get_size (*inst);
3401 unsigned long value;
3403 /* If it's an extend instruction we don't want the signed extend bit,
3404 because it influences the size. */
3405 if (cris_get_opcode (*inst) < 4)
3407 size &= ~SIGNED_EXTEND_BIT_MASK;
3409 /* Is there a need for checking the size? Size should contain the number of
3412 value = read_memory_unsigned_integer (address, size);
3414 /* Check if it's an extend, signed or zero instruction. */
3415 if (cris_get_opcode (*inst) < 4)
3417 value = do_sign_or_zero_extend (value, inst);
3422 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3423 instructions. The MOVE instruction is the move from source to register. */
3426 handle_prefix_assign_mode_for_aritm_op (unsigned short inst,
3427 inst_env_type *inst_env)
3429 unsigned long operand2;
3430 unsigned long operand3;
3432 check_assign (inst, inst_env);
3433 if (cris_get_operand2 (inst) == REG_PC)
3435 operand2 = inst_env->reg[REG_PC];
3437 /* Get the value of the third operand. */
3438 operand3 = get_data_from_address (&inst, inst_env->prefix_value);
3440 /* Calculate the PC value after the instruction, i.e. where the
3441 breakpoint should be. The order of the udw_operands is vital. */
3442 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3444 inst_env->slot_needed = 0;
3445 inst_env->prefix_found = 0;
3446 inst_env->xflag_found = 0;
3447 inst_env->disable_interrupt = 0;
3450 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3451 OR instructions. Note that for this to work as expected, the calling
3452 function must have made sure that there is a prefix to this instruction. */
3455 three_operand_add_sub_cmp_and_or_op (unsigned short inst,
3456 inst_env_type *inst_env)
3458 unsigned long operand2;
3459 unsigned long operand3;
3461 if (cris_get_operand1 (inst) == REG_PC)
3463 /* The PC will be changed by the instruction. */
3464 operand2 = inst_env->reg[cris_get_operand2 (inst)];
3466 /* Get the value of the third operand. */
3467 operand3 = get_data_from_address (&inst, inst_env->prefix_value);
3469 /* Calculate the PC value after the instruction, i.e. where the
3470 breakpoint should be. */
3471 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3473 inst_env->slot_needed = 0;
3474 inst_env->prefix_found = 0;
3475 inst_env->xflag_found = 0;
3476 inst_env->disable_interrupt = 0;
3479 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3480 instructions. The MOVE instruction is the move from source to register. */
3483 handle_prefix_index_mode_for_aritm_op (unsigned short inst,
3484 inst_env_type *inst_env)
3486 if (cris_get_operand1 (inst) != cris_get_operand2 (inst))
3488 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
3489 SUB, AND or OR something weird is going on (if everything works these
3490 instructions should end up in the three operand version). */
3491 inst_env->invalid = 1;
3496 /* three_operand_add_sub_cmp_and_or does the same as we should do here
3498 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3500 inst_env->slot_needed = 0;
3501 inst_env->prefix_found = 0;
3502 inst_env->xflag_found = 0;
3503 inst_env->disable_interrupt = 0;
3506 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3507 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
3508 source to register. */
3511 handle_inc_and_index_mode_for_aritm_op (unsigned short inst,
3512 inst_env_type *inst_env)
3514 unsigned long operand1;
3515 unsigned long operand2;
3516 unsigned long operand3;
3519 /* The instruction is either an indirect or autoincrement addressing mode.
3520 Check if the destination register is the PC. */
3521 if (cris_get_operand2 (inst) == REG_PC)
3523 /* Must be done here, get_data_from_address may change the size
3525 size = cris_get_size (inst);
3526 operand2 = inst_env->reg[REG_PC];
3528 /* Get the value of the third operand, i.e. the indirect operand. */
3529 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3530 operand3 = get_data_from_address (&inst, operand1);
3532 /* Calculate the PC value after the instruction, i.e. where the
3533 breakpoint should be. The order of the udw_operands is vital. */
3534 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3536 /* If this is an autoincrement addressing mode, check if the increment
3538 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3540 /* Get the size field. */
3541 size = cris_get_size (inst);
3543 /* If it's an extend instruction we don't want the signed extend bit,
3544 because it influences the size. */
3545 if (cris_get_opcode (inst) < 4)
3547 size &= ~SIGNED_EXTEND_BIT_MASK;
3549 process_autoincrement (size, inst, inst_env);
3551 inst_env->slot_needed = 0;
3552 inst_env->prefix_found = 0;
3553 inst_env->xflag_found = 0;
3554 inst_env->disable_interrupt = 0;
3557 /* Handles the two-operand addressing mode, all modes except register, for
3558 the ADD, SUB CMP, AND and OR instruction. */
3561 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3562 inst_env_type *inst_env)
3564 if (inst_env->prefix_found)
3566 if (cris_get_mode (inst) == PREFIX_INDEX_MODE)
3568 handle_prefix_index_mode_for_aritm_op (inst, inst_env);
3570 else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
3572 handle_prefix_assign_mode_for_aritm_op (inst, inst_env);
3576 /* The mode is invalid for a prefixed base instruction. */
3577 inst_env->invalid = 1;
3583 handle_inc_and_index_mode_for_aritm_op (inst, inst_env);
3587 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3590 quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env)
3592 unsigned long operand1;
3593 unsigned long operand2;
3595 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3596 instruction and can't have a prefix. */
3597 if (inst_env->prefix_found)
3599 inst_env->invalid = 1;
3603 /* Check if the instruction has PC as its target. */
3604 if (cris_get_operand2 (inst) == REG_PC)
3606 if (inst_env->slot_needed)
3608 inst_env->invalid = 1;
3611 operand1 = cris_get_quick_value (inst);
3612 operand2 = inst_env->reg[REG_PC];
3614 /* The size should now be dword. */
3615 cris_set_size_to_dword (&inst);
3617 /* Calculate the PC value after the instruction, i.e. where the
3618 breakpoint should be. */
3619 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3621 inst_env->slot_needed = 0;
3622 inst_env->prefix_found = 0;
3623 inst_env->xflag_found = 0;
3624 inst_env->disable_interrupt = 0;
3627 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3630 quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env)
3632 unsigned long operand1;
3633 unsigned long operand2;
3635 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3636 instruction and can't have a prefix. */
3637 if (inst_env->prefix_found)
3639 inst_env->invalid = 1;
3642 /* Check if the instruction has PC as its target. */
3643 if (cris_get_operand2 (inst) == REG_PC)
3645 if (inst_env->slot_needed)
3647 inst_env->invalid = 1;
3650 /* The instruction has the PC as its target register. */
3651 operand1 = cris_get_quick_value (inst);
3652 operand2 = inst_env->reg[REG_PC];
3654 /* The quick value is signed, so check if we must do a signed extend. */
3655 if (operand1 & SIGNED_QUICK_VALUE_MASK)
3658 operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK;
3660 /* The size should now be dword. */
3661 cris_set_size_to_dword (&inst);
3663 /* Calculate the PC value after the instruction, i.e. where the
3664 breakpoint should be. */
3665 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3667 inst_env->slot_needed = 0;
3668 inst_env->prefix_found = 0;
3669 inst_env->xflag_found = 0;
3670 inst_env->disable_interrupt = 0;
3673 /* Translate op_type to a function and call it. */
3676 cris_gdb_func (struct gdbarch *gdbarch, enum cris_op_type op_type,
3677 unsigned short inst, inst_env_type *inst_env)
3681 case cris_not_implemented_op:
3682 not_implemented_op (inst, inst_env);
3686 abs_op (inst, inst_env);
3690 addi_op (inst, inst_env);
3694 asr_op (inst, inst_env);
3698 asrq_op (inst, inst_env);
3701 case cris_ax_ei_setf_op:
3702 ax_ei_setf_op (inst, inst_env);
3705 case cris_bdap_prefix:
3706 bdap_prefix (inst, inst_env);
3709 case cris_biap_prefix:
3710 biap_prefix (inst, inst_env);
3714 break_op (inst, inst_env);
3717 case cris_btst_nop_op:
3718 btst_nop_op (inst, inst_env);
3721 case cris_clearf_di_op:
3722 clearf_di_op (inst, inst_env);
3725 case cris_dip_prefix:
3726 dip_prefix (inst, inst_env);
3729 case cris_dstep_logshift_mstep_neg_not_op:
3730 dstep_logshift_mstep_neg_not_op (inst, inst_env);
3733 case cris_eight_bit_offset_branch_op:
3734 eight_bit_offset_branch_op (inst, inst_env);
3737 case cris_move_mem_to_reg_movem_op:
3738 move_mem_to_reg_movem_op (inst, inst_env);
3741 case cris_move_reg_to_mem_movem_op:
3742 move_reg_to_mem_movem_op (inst, inst_env);
3745 case cris_move_to_preg_op:
3746 move_to_preg_op (gdbarch, inst, inst_env);
3750 muls_op (inst, inst_env);
3754 mulu_op (inst, inst_env);
3757 case cris_none_reg_mode_add_sub_cmp_and_or_move_op:
3758 none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3761 case cris_none_reg_mode_clear_test_op:
3762 none_reg_mode_clear_test_op (inst, inst_env);
3765 case cris_none_reg_mode_jump_op:
3766 none_reg_mode_jump_op (inst, inst_env);
3769 case cris_none_reg_mode_move_from_preg_op:
3770 none_reg_mode_move_from_preg_op (gdbarch, inst, inst_env);
3773 case cris_quick_mode_add_sub_op:
3774 quick_mode_add_sub_op (inst, inst_env);
3777 case cris_quick_mode_and_cmp_move_or_op:
3778 quick_mode_and_cmp_move_or_op (inst, inst_env);
3781 case cris_quick_mode_bdap_prefix:
3782 quick_mode_bdap_prefix (inst, inst_env);
3785 case cris_reg_mode_add_sub_cmp_and_or_move_op:
3786 reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3789 case cris_reg_mode_clear_op:
3790 reg_mode_clear_op (inst, inst_env);
3793 case cris_reg_mode_jump_op:
3794 reg_mode_jump_op (inst, inst_env);
3797 case cris_reg_mode_move_from_preg_op:
3798 reg_mode_move_from_preg_op (inst, inst_env);
3801 case cris_reg_mode_test_op:
3802 reg_mode_test_op (inst, inst_env);
3806 scc_op (inst, inst_env);
3809 case cris_sixteen_bit_offset_branch_op:
3810 sixteen_bit_offset_branch_op (inst, inst_env);
3813 case cris_three_operand_add_sub_cmp_and_or_op:
3814 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3817 case cris_three_operand_bound_op:
3818 three_operand_bound_op (inst, inst_env);
3821 case cris_two_operand_bound_op:
3822 two_operand_bound_op (inst, inst_env);
3826 xor_op (inst, inst_env);
3831 /* This wrapper is to avoid cris_get_assembler being called before
3832 exec_bfd has been set. */
3835 cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info)
3837 int (*print_insn) (bfd_vma addr, struct disassemble_info *info);
3838 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3839 disassembler, even when there is no BFD. Does something like
3840 "gdb; target remote; disassmeble *0x123" work? */
3841 gdb_assert (exec_bfd != NULL);
3842 print_insn = cris_get_disassembler (exec_bfd);
3843 gdb_assert (print_insn != NULL);
3844 return print_insn (addr, info);
3847 /* Copied from <asm/elf.h>. */
3848 typedef unsigned long elf_greg_t;
3850 /* Same as user_regs_struct struct in <asm/user.h>. */
3851 #define CRISV10_ELF_NGREG 35
3852 typedef elf_greg_t elf_gregset_t[CRISV10_ELF_NGREG];
3854 #define CRISV32_ELF_NGREG 32
3855 typedef elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG];
3857 /* Unpack an elf_gregset_t into GDB's register cache. */
3860 cris_supply_gregset (struct regcache *regcache, elf_gregset_t *gregsetp)
3862 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3863 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3865 elf_greg_t *regp = *gregsetp;
3866 static char zerobuf[4] = {0};
3868 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3869 knows about the actual size of each register so that's no problem. */
3870 for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++)
3872 regcache_raw_supply (regcache, i, (char *)®p[i]);
3875 if (tdep->cris_version == 32)
3877 /* Needed to set pseudo-register PC for CRISv32. */
3878 /* FIXME: If ERP is in a delay slot at this point then the PC will
3879 be wrong. Issue a warning to alert the user. */
3880 regcache_raw_supply (regcache, gdbarch_pc_regnum (gdbarch),
3881 (char *)®p[ERP_REGNUM]);
3883 if (*(char *)®p[ERP_REGNUM] & 0x1)
3884 fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n");
3888 /* Use a local version of this function to get the correct types for
3889 regsets, until multi-arch core support is ready. */
3892 fetch_core_registers (struct regcache *regcache,
3893 char *core_reg_sect, unsigned core_reg_size,
3894 int which, CORE_ADDR reg_addr)
3896 elf_gregset_t gregset;
3901 if (core_reg_size != sizeof (elf_gregset_t)
3902 && core_reg_size != sizeof (crisv32_elf_gregset_t))
3904 warning (_("wrong size gregset struct in core file"));
3908 memcpy (&gregset, core_reg_sect, sizeof (gregset));
3909 cris_supply_gregset (regcache, &gregset);
3913 /* We've covered all the kinds of registers we know about here,
3914 so this must be something we wouldn't know what to do with
3915 anyway. Just ignore it. */
3920 static struct core_fns cris_elf_core_fns =
3922 bfd_target_elf_flavour, /* core_flavour */
3923 default_check_format, /* check_format */
3924 default_core_sniffer, /* core_sniffer */
3925 fetch_core_registers, /* core_read_registers */
3929 extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */
3932 _initialize_cris_tdep (void)
3934 static struct cmd_list_element *cris_set_cmdlist;
3935 static struct cmd_list_element *cris_show_cmdlist;
3937 struct cmd_list_element *c;
3939 gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep);
3941 /* CRIS-specific user-commands. */
3942 add_setshow_uinteger_cmd ("cris-version", class_support,
3943 &usr_cmd_cris_version,
3944 _("Set the current CRIS version."),
3945 _("Show the current CRIS version."),
3947 Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\
3950 NULL, /* FIXME: i18n: Current CRIS version is %s. */
3951 &setlist, &showlist);
3953 add_setshow_enum_cmd ("cris-mode", class_support,
3954 cris_modes, &usr_cmd_cris_mode,
3955 _("Set the current CRIS mode."),
3956 _("Show the current CRIS mode."),
3958 Set to CRIS_MODE_GURU when debugging in guru mode.\n\
3959 Makes GDB use the NRP register instead of the ERP register in certain cases."),
3961 NULL, /* FIXME: i18n: Current CRIS version is %s. */
3962 &setlist, &showlist);
3964 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support,
3965 &usr_cmd_cris_dwarf2_cfi,
3966 _("Set the usage of Dwarf-2 CFI for CRIS."),
3967 _("Show the usage of Dwarf-2 CFI for CRIS."),
3968 _("Set this to \"off\" if using gcc-cris < R59."),
3969 set_cris_dwarf2_cfi,
3970 NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI for CRIS is %d. */
3971 &setlist, &showlist);
3973 deprecated_add_core_fns (&cris_elf_core_fns);
3976 /* Prints out all target specific values. */
3979 cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3981 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3984 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n",
3985 tdep->cris_version);
3986 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n",
3988 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
3989 tdep->cris_dwarf2_cfi);
3994 set_cris_version (char *ignore_args, int from_tty,
3995 struct cmd_list_element *c)
3997 struct gdbarch_info info;
3999 usr_cmd_cris_version_valid = 1;
4001 /* Update the current architecture, if needed. */
4002 gdbarch_info_init (&info);
4003 if (!gdbarch_update_p (info))
4004 internal_error (__FILE__, __LINE__,
4005 _("cris_gdbarch_update: failed to update architecture."));
4009 set_cris_mode (char *ignore_args, int from_tty,
4010 struct cmd_list_element *c)
4012 struct gdbarch_info info;
4014 /* Update the current architecture, if needed. */
4015 gdbarch_info_init (&info);
4016 if (!gdbarch_update_p (info))
4017 internal_error (__FILE__, __LINE__,
4018 "cris_gdbarch_update: failed to update architecture.");
4022 set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
4023 struct cmd_list_element *c)
4025 struct gdbarch_info info;
4027 /* Update the current architecture, if needed. */
4028 gdbarch_info_init (&info);
4029 if (!gdbarch_update_p (info))
4030 internal_error (__FILE__, __LINE__,
4031 _("cris_gdbarch_update: failed to update architecture."));
4034 static struct gdbarch *
4035 cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
4037 struct gdbarch *gdbarch;
4038 struct gdbarch_tdep *tdep;
4041 if (usr_cmd_cris_version_valid)
4043 /* Trust the user's CRIS version setting. */
4044 cris_version = usr_cmd_cris_version;
4046 else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32)
4052 /* Assume it's CRIS version 10. */
4056 /* Make the current settings visible to the user. */
4057 usr_cmd_cris_version = cris_version;
4059 /* Find a candidate among the list of pre-declared architectures. */
4060 for (arches = gdbarch_list_lookup_by_info (arches, &info);
4062 arches = gdbarch_list_lookup_by_info (arches->next, &info))
4064 if ((gdbarch_tdep (arches->gdbarch)->cris_version
4065 == usr_cmd_cris_version)
4066 && (gdbarch_tdep (arches->gdbarch)->cris_mode
4067 == usr_cmd_cris_mode)
4068 && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi
4069 == usr_cmd_cris_dwarf2_cfi))
4070 return arches->gdbarch;
4073 /* No matching architecture was found. Create a new one. */
4074 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
4075 gdbarch = gdbarch_alloc (&info, tdep);
4077 tdep->cris_version = usr_cmd_cris_version;
4078 tdep->cris_mode = usr_cmd_cris_mode;
4079 tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi;
4081 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
4082 switch (info.byte_order)
4084 case BFD_ENDIAN_LITTLE:
4088 case BFD_ENDIAN_BIG:
4089 internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: big endian byte order in info"));
4093 internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: unknown byte order in info"));
4096 set_gdbarch_return_value (gdbarch, cris_return_value);
4098 set_gdbarch_sp_regnum (gdbarch, 14);
4100 /* Length of ordinary registers used in push_word and a few other
4101 places. register_size() is the real way to know how big a
4104 set_gdbarch_double_bit (gdbarch, 64);
4105 /* The default definition of a long double is 2 * gdbarch_double_bit,
4106 which means we have to set this explicitly. */
4107 set_gdbarch_long_double_bit (gdbarch, 64);
4109 /* The total amount of space needed to store (in an array called registers)
4110 GDB's copy of the machine's register state. Note: We can not use
4111 cris_register_size at this point, since it relies on gdbarch
4113 switch (tdep->cris_version)
4121 /* Old versions; not supported. */
4122 internal_error (__FILE__, __LINE__,
4123 _("cris_gdbarch_init: unsupported CRIS version"));
4128 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
4129 P7 (32 bits), and P15 (32 bits) have been implemented. */
4130 set_gdbarch_pc_regnum (gdbarch, 15);
4131 set_gdbarch_register_type (gdbarch, cris_register_type);
4132 /* There are 32 registers (some of which may not be implemented). */
4133 set_gdbarch_num_regs (gdbarch, 32);
4134 set_gdbarch_register_name (gdbarch, cris_register_name);
4135 set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register);
4136 set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register);
4138 set_gdbarch_software_single_step (gdbarch, cris_software_single_step);
4142 /* CRIS v32. General registers R0 - R15 (32 bits), special registers
4143 P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
4144 and pseudo-register PC (32 bits). */
4145 set_gdbarch_pc_regnum (gdbarch, 32);
4146 set_gdbarch_register_type (gdbarch, crisv32_register_type);
4147 /* 32 registers + pseudo-register PC + 16 support registers. */
4148 set_gdbarch_num_regs (gdbarch, 32 + 1 + 16);
4149 set_gdbarch_register_name (gdbarch, crisv32_register_name);
4151 set_gdbarch_cannot_store_register
4152 (gdbarch, crisv32_cannot_store_register);
4153 set_gdbarch_cannot_fetch_register
4154 (gdbarch, crisv32_cannot_fetch_register);
4156 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
4158 set_gdbarch_single_step_through_delay
4159 (gdbarch, crisv32_single_step_through_delay);
4164 internal_error (__FILE__, __LINE__,
4165 _("cris_gdbarch_init: unknown CRIS version"));
4168 /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
4169 have the same ABI). */
4170 set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code);
4171 set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call);
4172 set_gdbarch_frame_align (gdbarch, cris_frame_align);
4173 set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue);
4175 /* The stack grows downward. */
4176 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4178 set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc);
4180 set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc);
4181 set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp);
4182 set_gdbarch_dummy_id (gdbarch, cris_dummy_id);
4184 if (tdep->cris_dwarf2_cfi == 1)
4186 /* Hook in the Dwarf-2 frame sniffer. */
4187 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum);
4188 dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg);
4189 dwarf2_append_unwinders (gdbarch);
4192 if (tdep->cris_mode != cris_mode_guru)
4194 frame_unwind_append_unwinder (gdbarch, &cris_sigtramp_frame_unwind);
4197 frame_unwind_append_unwinder (gdbarch, &cris_frame_unwind);
4198 frame_base_set_default (gdbarch, &cris_frame_base);
4200 set_solib_svr4_fetch_link_map_offsets
4201 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
4203 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
4204 disassembler, even when there is no BFD. Does something like
4205 "gdb; target remote; disassmeble *0x123" work? */
4206 set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler);