1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
3 Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 Contributed by Axis Communications AB.
6 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
26 #include "frame-unwind.h"
27 #include "frame-base.h"
28 #include "trad-frame.h"
29 #include "dwarf2-frame.h"
37 #include "opcode/cris.h"
38 #include "arch-utils.h"
40 #include "gdb_assert.h"
42 /* To get entry_point_address. */
45 #include "solib.h" /* Support for shared libraries. */
46 #include "solib-svr4.h" /* For struct link_map_offsets. */
47 #include "gdb_string.h"
53 /* There are no floating point registers. Used in gdbserver low-linux.c. */
56 /* There are 16 general registers. */
59 /* There are 16 special registers. */
63 /* Register numbers of various important registers.
64 CRIS_FP_REGNUM Contains address of executing stack frame.
65 STR_REGNUM Contains the address of structure return values.
66 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
67 ARG1_REGNUM Contains the first parameter to a function.
68 ARG2_REGNUM Contains the second parameter to a function.
69 ARG3_REGNUM Contains the third parameter to a function.
70 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
71 SP_REGNUM Contains address of top of stack.
72 PC_REGNUM Contains address of next instruction.
73 SRP_REGNUM Subroutine return pointer register.
74 BRP_REGNUM Breakpoint return pointer register. */
78 /* Enums with respect to the general registers, valid for all
88 /* Enums with respect to the special registers, some of which may not be
89 applicable to all CRIS versions. */
107 extern const struct cris_spec_reg cris_spec_regs[];
109 /* CRIS version, set via the user command 'set cris-version'. Affects
110 register names and sizes.*/
111 static int usr_cmd_cris_version;
113 /* Indicates whether to trust the above variable. */
114 static int usr_cmd_cris_version_valid = 0;
116 /* CRIS mode, set via the user command 'set cris-mode'. Affects availability
117 of some registers. */
118 static const char *usr_cmd_cris_mode;
120 /* Indicates whether to trust the above variable. */
121 static int usr_cmd_cris_mode_valid = 0;
123 static const char CRIS_MODE_USER[] = "CRIS_MODE_USER";
124 static const char CRIS_MODE_SUPERVISOR[] = "CRIS_MODE_SUPERVISOR";
125 static const char *cris_mode_enums[] =
128 CRIS_MODE_SUPERVISOR,
132 /* CRIS architecture specific information. */
136 const char *cris_mode;
139 /* Functions for accessing target dependent data. */
144 return (gdbarch_tdep (current_gdbarch)->cris_version);
150 return (gdbarch_tdep (current_gdbarch)->cris_mode);
153 struct cris_unwind_cache
155 /* The previous frame's inner most stack address. Used as this
156 frame ID's stack_addr. */
158 /* The frame's base, optionally used by the high-level debug info. */
161 /* How far the SP and r8 (FP) have been offset from the start of
162 the stack frame (as defined by the previous frame's stack
168 /* From old frame_extra_info struct. */
172 /* Table indicating the location of each and every register. */
173 struct trad_frame_saved_reg *saved_regs;
176 /* The instruction environment needed to find single-step breakpoints. */
178 struct instruction_environment
180 unsigned long reg[NUM_GENREGS];
181 unsigned long preg[NUM_SPECREGS];
182 unsigned long branch_break_address;
183 unsigned long delay_slot_pc;
184 unsigned long prefix_value;
189 int delay_slot_pc_active;
191 int disable_interrupt;
194 /* Save old breakpoints in order to restore the state before a single_step.
195 At most, two breakpoints will have to be remembered. */
197 char binsn_quantum[BREAKPOINT_MAX];
198 static binsn_quantum break_mem[2];
199 static CORE_ADDR next_pc = 0;
200 static CORE_ADDR branch_target_address = 0;
201 static unsigned char branch_break_inserted = 0;
203 /* Machine-dependencies in CRIS for opcodes. */
205 /* Instruction sizes. */
206 enum cris_instruction_sizes
213 /* Addressing modes. */
214 enum cris_addressing_modes
221 /* Prefix addressing modes. */
222 enum cris_prefix_addressing_modes
224 PREFIX_INDEX_MODE = 2,
225 PREFIX_ASSIGN_MODE = 3,
227 /* Handle immediate byte offset addressing mode prefix format. */
228 PREFIX_OFFSET_MODE = 2
231 /* Masks for opcodes. */
232 enum cris_opcode_masks
234 BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1,
235 SIGNED_EXTEND_BIT_MASK = 0x2,
236 SIGNED_BYTE_MASK = 0x80,
237 SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00,
238 SIGNED_WORD_MASK = 0x8000,
239 SIGNED_WORD_EXTEND_MASK = 0xFFFF0000,
240 SIGNED_DWORD_MASK = 0x80000000,
241 SIGNED_QUICK_VALUE_MASK = 0x20,
242 SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0
245 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
253 cris_get_operand2 (unsigned short insn)
255 return ((insn & 0xF000) >> 12);
259 cris_get_mode (unsigned short insn)
261 return ((insn & 0x0C00) >> 10);
265 cris_get_opcode (unsigned short insn)
267 return ((insn & 0x03C0) >> 6);
271 cris_get_size (unsigned short insn)
273 return ((insn & 0x0030) >> 4);
277 cris_get_operand1 (unsigned short insn)
279 return (insn & 0x000F);
282 /* Additional functions in order to handle opcodes. */
285 cris_get_quick_value (unsigned short insn)
287 return (insn & 0x003F);
291 cris_get_bdap_quick_offset (unsigned short insn)
293 return (insn & 0x00FF);
297 cris_get_branch_short_offset (unsigned short insn)
299 return (insn & 0x00FF);
303 cris_get_asr_shift_steps (unsigned long value)
305 return (value & 0x3F);
309 cris_get_clear_size (unsigned short insn)
311 return ((insn) & 0xC000);
315 cris_is_signed_extend_bit_on (unsigned short insn)
317 return (((insn) & 0x20) == 0x20);
321 cris_is_xflag_bit_on (unsigned short insn)
323 return (((insn) & 0x1000) == 0x1000);
327 cris_set_size_to_dword (unsigned short *insn)
334 cris_get_signed_offset (unsigned short insn)
336 return ((signed char) (insn & 0x00FF));
339 /* Calls an op function given the op-type, working on the insn and the
341 static void cris_gdb_func (enum cris_op_type, unsigned short, inst_env_type *);
343 static struct gdbarch *cris_gdbarch_init (struct gdbarch_info,
344 struct gdbarch_list *);
346 static void cris_dump_tdep (struct gdbarch *, struct ui_file *);
348 static void cris_version_update (char *ignore_args, int from_tty,
349 struct cmd_list_element *c);
351 static void cris_mode_update (char *ignore_args, int from_tty,
352 struct cmd_list_element *c);
354 static CORE_ADDR cris_scan_prologue (CORE_ADDR pc,
355 struct frame_info *next_frame,
356 struct cris_unwind_cache *info);
358 static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch,
359 struct frame_info *next_frame);
361 static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch,
362 struct frame_info *next_frame);
364 /* When arguments must be pushed onto the stack, they go on in reverse
365 order. The below implements a FILO (stack) to do this. */
367 /* Borrowed from d10v-tdep.c. */
372 struct stack_item *prev;
376 static struct stack_item *
377 push_stack_item (struct stack_item *prev, void *contents, int len)
379 struct stack_item *si;
380 si = xmalloc (sizeof (struct stack_item));
381 si->data = xmalloc (len);
384 memcpy (si->data, contents, len);
388 static struct stack_item *
389 pop_stack_item (struct stack_item *si)
391 struct stack_item *dead = si;
398 /* Put here the code to store, into fi->saved_regs, the addresses of
399 the saved registers of frame described by FRAME_INFO. This
400 includes special registers such as pc and fp saved in special ways
401 in the stack frame. sp is even more special: the address we return
402 for it IS the sp for the next frame. */
404 struct cris_unwind_cache *
405 cris_frame_unwind_cache (struct frame_info *next_frame,
406 void **this_prologue_cache)
409 struct cris_unwind_cache *info;
412 if ((*this_prologue_cache))
413 return (*this_prologue_cache);
415 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
416 (*this_prologue_cache) = info;
417 info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
419 /* Zero all fields. */
425 info->uses_frame = 0;
427 info->leaf_function = 0;
429 /* Prologue analysis does the rest... */
430 cris_scan_prologue (frame_func_unwind (next_frame), next_frame, info);
435 /* Given a GDB frame, determine the address of the calling function's
436 frame. This will be used to create a new GDB frame struct. */
439 cris_frame_this_id (struct frame_info *next_frame,
440 void **this_prologue_cache,
441 struct frame_id *this_id)
443 struct cris_unwind_cache *info
444 = cris_frame_unwind_cache (next_frame, this_prologue_cache);
449 /* The FUNC is easy. */
450 func = frame_func_unwind (next_frame);
452 /* Hopefully the prologue analysis either correctly determined the
453 frame's base (which is the SP from the previous frame), or set
454 that base to "NULL". */
455 base = info->prev_sp;
459 id = frame_id_build (base, func);
465 cris_frame_prev_register (struct frame_info *next_frame,
466 void **this_prologue_cache,
467 int regnum, int *optimizedp,
468 enum lval_type *lvalp, CORE_ADDR *addrp,
469 int *realnump, void *bufferp)
471 struct cris_unwind_cache *info
472 = cris_frame_unwind_cache (next_frame, this_prologue_cache);
473 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
474 optimizedp, lvalp, addrp, realnump, bufferp);
477 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
478 dummy frame. The frame ID's base needs to match the TOS value
479 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
482 static struct frame_id
483 cris_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
485 return frame_id_build (cris_unwind_sp (gdbarch, next_frame),
486 frame_pc_unwind (next_frame));
490 cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
492 /* Align to the size of an instruction (so that they can safely be
493 pushed onto the stack). */
498 cris_push_dummy_code (struct gdbarch *gdbarch,
499 CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc,
500 struct value **args, int nargs,
501 struct type *value_type,
502 CORE_ADDR *real_pc, CORE_ADDR *bp_addr)
504 /* Allocate space sufficient for a breakpoint. */
506 /* Store the address of that breakpoint */
508 /* CRIS always starts the call at the callee's entry point. */
514 cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
515 struct regcache *regcache, CORE_ADDR bp_addr,
516 int nargs, struct value **args, CORE_ADDR sp,
517 int struct_return, CORE_ADDR struct_addr)
526 /* The function's arguments and memory allocated by gdb for the arguments to
527 point at reside in separate areas on the stack.
528 Both frame pointers grow toward higher addresses. */
532 struct stack_item *si = NULL;
534 /* Push the return address. */
535 regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr);
537 /* Are we returning a value using a structure return or a normal value
538 return? struct_addr is the address of the reserved space for the return
539 structure to be written on the stack. */
542 regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr);
545 /* Now load as many as possible of the first arguments into registers,
546 and push the rest onto the stack. */
547 argreg = ARG1_REGNUM;
550 for (argnum = 0; argnum < nargs; argnum++)
557 len = TYPE_LENGTH (VALUE_TYPE (args[argnum]));
558 val = (char *) VALUE_CONTENTS (args[argnum]);
560 /* How may registers worth of storage do we need for this argument? */
561 reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0);
563 if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM))
565 /* Data passed by value. Fits in available register(s). */
566 for (i = 0; i < reg_demand; i++)
568 regcache_cooked_write_unsigned (regcache, argreg,
569 *(unsigned long *) val);
574 else if (len <= (2 * 4) && argreg <= ARG4_REGNUM)
576 /* Data passed by value. Does not fit in available register(s).
577 Use the register(s) first, then the stack. */
578 for (i = 0; i < reg_demand; i++)
580 if (argreg <= ARG4_REGNUM)
582 regcache_cooked_write_unsigned (regcache, argreg,
583 *(unsigned long *) val);
589 /* Push item for later so that pushed arguments
590 come in the right order. */
591 si = push_stack_item (si, val, 4);
596 else if (len > (2 * 4))
599 internal_error (__FILE__, __LINE__, "We don't do this");
603 /* Data passed by value. No available registers. Put it on
605 si = push_stack_item (si, val, len);
611 /* fp_arg must be word-aligned (i.e., don't += len) to match
612 the function prologue. */
613 sp = (sp - si->len) & ~3;
614 write_memory (sp, si->data, si->len);
615 si = pop_stack_item (si);
618 /* Finally, update the SP register. */
619 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
624 static const struct frame_unwind cris_frame_unwind = {
627 cris_frame_prev_register
630 const struct frame_unwind *
631 cris_frame_sniffer (struct frame_info *next_frame)
633 return &cris_frame_unwind;
637 cris_frame_base_address (struct frame_info *next_frame, void **this_cache)
639 struct cris_unwind_cache *info
640 = cris_frame_unwind_cache (next_frame, this_cache);
644 static const struct frame_base cris_frame_base = {
646 cris_frame_base_address,
647 cris_frame_base_address,
648 cris_frame_base_address
651 /* Frames information. The definition of the struct frame_info is
655 enum frame_type type;
659 If the compilation option -fno-omit-frame-pointer is present the
660 variable frame will be set to the content of R8 which is the frame
663 The variable pc contains the address where execution is performed
664 in the present frame. The innermost frame contains the current content
665 of the register PC. All other frames contain the content of the
666 register PC in the next frame.
668 The variable `type' indicates the frame's type: normal, SIGTRAMP
669 (associated with a signal handler), dummy (associated with a dummy
672 The variable return_pc contains the address where execution should be
673 resumed when the present frame has finished, the return address.
675 The variable leaf_function is 1 if the return address is in the register
676 SRP, and 0 if it is on the stack.
678 Prologue instructions C-code.
679 The prologue may consist of (-fno-omit-frame-pointer)
683 move.d sp,r8 move.d sp,r8
685 movem rY,[sp] movem rY,[sp]
686 move.S rZ,[r8-U] move.S rZ,[r8-U]
688 where 1 is a non-terminal function, and 2 is a leaf-function.
690 Note that this assumption is extremely brittle, and will break at the
691 slightest change in GCC's prologue.
693 If local variables are declared or register contents are saved on stack
694 the subq-instruction will be present with X as the number of bytes
695 needed for storage. The reshuffle with respect to r8 may be performed
696 with any size S (b, w, d) and any of the general registers Z={0..13}.
697 The offset U should be representable by a signed 8-bit value in all cases.
698 Thus, the prefix word is assumed to be immediate byte offset mode followed
699 by another word containing the instruction.
708 Prologue instructions C++-code.
709 Case 1) and 2) in the C-code may be followed by
715 move.S [r8+U],rZ ; P4
717 if any of the call parameters are stored. The host expects these
718 instructions to be executed in order to get the call parameters right. */
720 /* Examine the prologue of a function. The variable ip is the address of
721 the first instruction of the prologue. The variable limit is the address
722 of the first instruction after the prologue. The variable fi contains the
723 information in struct frame_info. The variable frameless_p controls whether
724 the entire prologue is examined (0) or just enough instructions to
725 determine that it is a prologue (1). */
728 cris_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame,
729 struct cris_unwind_cache *info)
731 /* Present instruction. */
734 /* Next instruction, lookahead. */
735 unsigned short insn_next;
738 /* Is there a push fp? */
741 /* Number of byte on stack used for local variables and movem. */
744 /* Highest register number in a movem. */
747 /* move.d r<source_register>,rS */
748 short source_register;
753 /* This frame is with respect to a leaf until a push srp is found. */
756 info->leaf_function = 1;
759 /* Assume nothing on stack. */
763 /* If we were called without a next_frame, that means we were called
764 from cris_skip_prologue which already tried to find the end of the
765 prologue through the symbol information. 64 instructions past current
766 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
767 limit = next_frame ? frame_pc_unwind (next_frame) : pc + 64;
769 /* Find the prologue instructions. */
772 insn = read_memory_unsigned_integer (pc, 2);
776 /* push <reg> 32 bit instruction */
777 insn_next = read_memory_unsigned_integer (pc, 2);
779 regno = cris_get_operand2 (insn_next);
782 info->sp_offset += 4;
784 /* This check, meant to recognize srp, used to be regno ==
785 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
786 if (insn_next == 0xBE7E)
790 info->leaf_function = 0;
793 else if (insn_next == 0x8FEE)
798 info->r8_offset = info->sp_offset;
802 else if (insn == 0x866E)
807 info->uses_frame = 1;
811 else if (cris_get_operand2 (insn) == SP_REGNUM
812 && cris_get_mode (insn) == 0x0000
813 && cris_get_opcode (insn) == 0x000A)
818 info->sp_offset += cris_get_quick_value (insn);
821 else if (cris_get_mode (insn) == 0x0002
822 && cris_get_opcode (insn) == 0x000F
823 && cris_get_size (insn) == 0x0003
824 && cris_get_operand1 (insn) == SP_REGNUM)
826 /* movem r<regsave>,[sp] */
827 regsave = cris_get_operand2 (insn);
829 else if (cris_get_operand2 (insn) == SP_REGNUM
830 && ((insn & 0x0F00) >> 8) == 0x0001
831 && (cris_get_signed_offset (insn) < 0))
833 /* Immediate byte offset addressing prefix word with sp as base
834 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
835 is between 64 and 128.
836 movem r<regsave>,[sp=sp-<val>] */
839 info->sp_offset += -cris_get_signed_offset (insn);
841 insn_next = read_memory_unsigned_integer (pc, 2);
843 if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE
844 && cris_get_opcode (insn_next) == 0x000F
845 && cris_get_size (insn_next) == 0x0003
846 && cris_get_operand1 (insn_next) == SP_REGNUM)
848 regsave = cris_get_operand2 (insn_next);
852 /* The prologue ended before the limit was reached. */
857 else if (cris_get_mode (insn) == 0x0001
858 && cris_get_opcode (insn) == 0x0009
859 && cris_get_size (insn) == 0x0002)
861 /* move.d r<10..13>,r<0..15> */
862 source_register = cris_get_operand1 (insn);
864 /* FIXME? In the glibc solibs, the prologue might contain something
865 like (this example taken from relocate_doit):
868 which isn't covered by the source_register check below. Question
869 is whether to add a check for this combo, or make better use of
870 the limit variable instead. */
871 if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM)
873 /* The prologue ended before the limit was reached. */
878 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
879 /* The size is a fixed-size. */
880 && ((insn & 0x0F00) >> 8) == 0x0001
881 /* A negative offset. */
882 && (cris_get_signed_offset (insn) < 0))
884 /* move.S rZ,[r8-U] (?) */
885 insn_next = read_memory_unsigned_integer (pc, 2);
887 regno = cris_get_operand2 (insn_next);
888 if ((regno >= 0 && regno < SP_REGNUM)
889 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
890 && cris_get_opcode (insn_next) == 0x000F)
892 /* move.S rZ,[r8-U] */
897 /* The prologue ended before the limit was reached. */
902 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
903 /* The size is a fixed-size. */
904 && ((insn & 0x0F00) >> 8) == 0x0001
905 /* A positive offset. */
906 && (cris_get_signed_offset (insn) > 0))
908 /* move.S [r8+U],rZ (?) */
909 insn_next = read_memory_unsigned_integer (pc, 2);
911 regno = cris_get_operand2 (insn_next);
912 if ((regno >= 0 && regno < SP_REGNUM)
913 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
914 && cris_get_opcode (insn_next) == 0x0009
915 && cris_get_operand1 (insn_next) == regno)
917 /* move.S [r8+U],rZ */
922 /* The prologue ended before the limit was reached. */
929 /* The prologue ended before the limit was reached. */
935 /* We only want to know the end of the prologue when next_frame and info
936 are NULL (called from cris_skip_prologue i.e.). */
937 if (next_frame == NULL && info == NULL)
942 info->size = info->sp_offset;
944 /* Compute the previous frame's stack pointer (which is also the
945 frame's ID's stack address), and this frame's base pointer. */
946 if (info->uses_frame)
949 /* The SP was moved to the FP. This indicates that a new frame
950 was created. Get THIS frame's FP value by unwinding it from
952 frame_unwind_unsigned_register (next_frame, CRIS_FP_REGNUM,
954 info->base = this_base;
955 info->saved_regs[CRIS_FP_REGNUM].addr = info->base;
957 /* The FP points at the last saved register. Adjust the FP back
958 to before the first saved register giving the SP. */
959 info->prev_sp = info->base + info->r8_offset;
964 /* Assume that the FP is this frame's SP but with that pushed
965 stack space added back. */
966 frame_unwind_unsigned_register (next_frame, SP_REGNUM, &this_base);
967 info->base = this_base;
968 info->prev_sp = info->base + info->size;
971 /* Calculate the addresses for the saved registers on the stack. */
972 /* FIXME: The address calculation should really be done on the fly while
973 we're analyzing the prologue (we only hold one regsave value as it is
975 val = info->sp_offset;
977 for (regno = regsave; regno >= 0; regno--)
979 info->saved_regs[regno].addr = info->base + info->r8_offset - val;
983 /* The previous frame's SP needed to be computed. Save the computed
985 trad_frame_set_value (info->saved_regs, SP_REGNUM, info->prev_sp);
987 if (!info->leaf_function)
989 /* SRP saved on the stack. But where? */
990 if (info->r8_offset == 0)
992 /* R8 not pushed yet. */
993 info->saved_regs[SRP_REGNUM].addr = info->base;
997 /* R8 pushed, but SP may or may not be moved to R8 yet. */
998 info->saved_regs[SRP_REGNUM].addr = info->base + 4;
1002 /* The PC is found in SRP (the actual register or located on the stack). */
1003 info->saved_regs[PC_REGNUM] = info->saved_regs[SRP_REGNUM];
1008 /* Advance pc beyond any function entry prologue instructions at pc
1009 to reach some "real" code. */
1011 /* Given a PC value corresponding to the start of a function, return the PC
1012 of the first instruction after the function prologue. */
1015 cris_skip_prologue (CORE_ADDR pc)
1017 CORE_ADDR func_addr, func_end;
1018 struct symtab_and_line sal;
1019 CORE_ADDR pc_after_prologue;
1021 /* If we have line debugging information, then the end of the prologue
1022 should the first assembly instruction of the first source line. */
1023 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1025 sal = find_pc_line (func_addr, 0);
1026 if (sal.end > 0 && sal.end < func_end)
1030 pc_after_prologue = cris_scan_prologue (pc, NULL, NULL);
1031 return pc_after_prologue;
1035 cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1038 frame_unwind_unsigned_register (next_frame, PC_REGNUM, &pc);
1043 cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1046 frame_unwind_unsigned_register (next_frame, SP_REGNUM, &sp);
1050 /* Use the program counter to determine the contents and size of a breakpoint
1051 instruction. It returns a pointer to a string of bytes that encode a
1052 breakpoint instruction, stores the length of the string to *lenptr, and
1053 adjusts pcptr (if necessary) to point to the actual memory location where
1054 the breakpoint should be inserted. */
1056 static const unsigned char *
1057 cris_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
1059 static unsigned char break_insn[] = {0x38, 0xe9};
1065 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1069 cris_spec_reg_applicable (struct cris_spec_reg spec_reg)
1071 int version = cris_version ();
1073 switch (spec_reg.applicable_version)
1075 case cris_ver_version_all:
1077 case cris_ver_warning:
1078 /* Indeterminate/obsolete. */
1081 /* Simulator only. */
1084 return (version >= 0 && version <= 3);
1086 return (version >= 3);
1088 return (version == 8 || version == 9);
1090 return (version >= 8);
1092 return (version >= 10);
1094 /* Invalid cris version. */
1099 /* Nonzero if regno should not be fetched from the target. This is the case
1100 for unimplemented (size 0) and non-existant registers. */
1103 cris_cannot_fetch_register (int regno)
1105 return ((regno < 0 || regno >= NUM_REGS)
1106 || (cris_register_size (regno) == 0));
1109 /* Nonzero if regno should not be written to the target, for various
1113 cris_cannot_store_register (int regno)
1115 /* There are three kinds of registers we refuse to write to.
1116 1. Those that not implemented.
1117 2. Those that are read-only (depends on the processor mode).
1118 3. Those registers to which a write has no effect.
1121 if (regno < 0 || regno >= NUM_REGS || cris_register_size (regno) == 0)
1122 /* Not implemented. */
1125 else if (regno == VR_REGNUM)
1129 else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM)
1130 /* Writing has no effect. */
1133 else if (cris_mode () == CRIS_MODE_USER)
1135 if (regno == IBR_REGNUM || regno == BAR_REGNUM || regno == BRP_REGNUM
1136 || regno == IRP_REGNUM)
1137 /* Read-only in user mode. */
1144 /* Returns the register offset for the first byte of register regno's space
1145 in the saved register state. Returns -1 for an invalid or unimplemented
1149 cris_register_offset (int regno)
1155 if (regno >= 0 && regno < NUM_REGS)
1157 /* FIXME: The offsets should be cached and calculated only once,
1158 when the architecture being debugged has changed. */
1159 for (i = 0; i < regno; i++)
1160 offset += cris_register_size (i);
1166 /* Invalid register. */
1171 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1172 of data in register regno. */
1174 static struct type *
1175 cris_register_type (struct gdbarch *gdbarch, int regno)
1177 if (regno == SP_REGNUM || regno == PC_REGNUM
1178 || (regno > P8_REGNUM && regno < USP_REGNUM))
1180 /* SP, PC, IBR, IRP, SRP, BAR, DCCR, BRP */
1181 return lookup_pointer_type (builtin_type_void);
1183 else if (regno == P8_REGNUM || regno == USP_REGNUM
1184 || (regno >= 0 && regno < SP_REGNUM))
1186 /* R0 - R13, P8, P15 */
1187 return builtin_type_unsigned_long;
1189 else if (regno > P3_REGNUM && regno < P8_REGNUM)
1191 /* P4, CCR, DCR0, DCR1 */
1192 return builtin_type_unsigned_short;
1194 else if (regno > PC_REGNUM && regno < P4_REGNUM)
1196 /* P0, P1, P2, P3 */
1197 return builtin_type_unsigned_char;
1201 /* Invalid register. */
1202 return builtin_type_void;
1206 /* Stores a function return value of type type, where valbuf is the address
1207 of the value to be stored. */
1209 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1212 cris_store_return_value (struct type *type, struct regcache *regcache,
1216 int len = TYPE_LENGTH (type);
1220 /* Put the return value in R10. */
1221 val = extract_unsigned_integer (valbuf, len);
1222 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1226 /* Put the return value in R10 and R11. */
1227 val = extract_unsigned_integer (valbuf, 4);
1228 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1229 val = extract_unsigned_integer ((char *)valbuf + 4, len - 4);
1230 regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val);
1233 error ("cris_store_return_value: type length too large.");
1236 /* Return the name of register regno as a string. Return NULL for an invalid or
1237 unimplemented register. */
1240 cris_register_name (int regno)
1242 static char *cris_genreg_names[] =
1243 { "r0", "r1", "r2", "r3", \
1244 "r4", "r5", "r6", "r7", \
1245 "r8", "r9", "r10", "r11", \
1246 "r12", "r13", "sp", "pc" };
1251 if (regno >= 0 && regno < NUM_GENREGS)
1253 /* General register. */
1254 return cris_genreg_names[regno];
1256 else if (regno >= NUM_GENREGS && regno < NUM_REGS)
1258 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1259 Adjust regno accordingly. */
1260 spec_regno = regno - NUM_GENREGS;
1262 /* The entries in cris_spec_regs are stored in register number order,
1263 which means we can shortcut into the array when searching it. */
1264 for (i = spec_regno; cris_spec_regs[i].name != NULL; i++)
1266 if (cris_spec_regs[i].number == spec_regno
1267 && cris_spec_reg_applicable (cris_spec_regs[i]))
1268 /* Go with the first applicable register. */
1269 return cris_spec_regs[i].name;
1271 /* Special register not applicable to this CRIS version. */
1276 /* Invalid register. */
1282 cris_register_bytes_ok (long bytes)
1284 return (bytes == deprecated_register_bytes ());
1287 /* Extract from an array regbuf containing the raw register state a function
1288 return value of type type, and copy that, in virtual format, into
1291 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1294 cris_extract_return_value (struct type *type, struct regcache *regcache,
1298 int len = TYPE_LENGTH (type);
1302 /* Get the return value from R10. */
1303 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1304 store_unsigned_integer (valbuf, len, val);
1308 /* Get the return value from R10 and R11. */
1309 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1310 store_unsigned_integer (valbuf, 4, val);
1311 regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val);
1312 store_unsigned_integer ((char *)valbuf + 4, len - 4, val);
1315 error ("cris_extract_return_value: type length too large");
1318 /* Handle the CRIS return value convention. */
1320 static enum return_value_convention
1321 cris_return_value (struct gdbarch *gdbarch, struct type *type,
1322 struct regcache *regcache, void *readbuf,
1323 const void *writebuf)
1325 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1326 || TYPE_CODE (type) == TYPE_CODE_UNION
1327 || TYPE_LENGTH (type) > 8)
1328 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1329 goes on the stack. */
1330 return RETURN_VALUE_STRUCT_CONVENTION;
1333 cris_extract_return_value (type, regcache, readbuf);
1335 cris_store_return_value (type, regcache, writebuf);
1337 return RETURN_VALUE_REGISTER_CONVENTION;
1340 /* Returns 1 if the given type will be passed by pointer rather than
1343 /* In the CRIS ABI, arguments shorter than or equal to 64 bits are passed
1347 cris_reg_struct_has_addr (int gcc_p, struct type *type)
1349 return (TYPE_LENGTH (type) > 8);
1352 /* Calculates a value that measures how good inst_args constraints an
1353 instruction. It stems from cris_constraint, found in cris-dis.c. */
1356 constraint (unsigned int insn, const signed char *inst_args,
1357 inst_env_type *inst_env)
1362 const char *s = inst_args;
1368 if ((insn & 0x30) == 0x30)
1373 /* A prefix operand. */
1374 if (inst_env->prefix_found)
1380 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1381 valid "push" size. In case of special register, it may be != 4. */
1382 if (inst_env->prefix_found)
1388 retval = (((insn >> 0xC) & 0xF) == (insn & 0xF));
1396 tmp = (insn >> 0xC) & 0xF;
1398 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1400 /* Since we match four bits, we will give a value of
1401 4 - 1 = 3 in a match. If there is a corresponding
1402 exact match of a special register in another pattern, it
1403 will get a value of 4, which will be higher. This should
1404 be correct in that an exact pattern would match better that
1406 Note that there is a reason for not returning zero; the
1407 pattern for "clear" is partly matched in the bit-pattern
1408 (the two lower bits must be zero), while the bit-pattern
1409 for a move from a special register is matched in the
1410 register constraint.
1411 This also means we will will have a race condition if
1412 there is a partly match in three bits in the bit pattern. */
1413 if (tmp == cris_spec_regs[i].number)
1420 if (cris_spec_regs[i].name == NULL)
1427 /* Returns the number of bits set in the variable value. */
1430 number_of_bits (unsigned int value)
1432 int number_of_bits = 0;
1436 number_of_bits += 1;
1437 value &= (value - 1);
1439 return number_of_bits;
1442 /* Finds the address that should contain the single step breakpoint(s).
1443 It stems from code in cris-dis.c. */
1446 find_cris_op (unsigned short insn, inst_env_type *inst_env)
1449 int max_level_of_match = -1;
1450 int max_matched = -1;
1453 for (i = 0; cris_opcodes[i].name != NULL; i++)
1455 if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match)
1456 && ((cris_opcodes[i].lose & insn) == 0))
1458 level_of_match = constraint (insn, cris_opcodes[i].args, inst_env);
1459 if (level_of_match >= 0)
1462 number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose);
1463 if (level_of_match > max_level_of_match)
1466 max_level_of_match = level_of_match;
1467 if (level_of_match == 16)
1469 /* All bits matched, cannot find better. */
1479 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
1480 actually an internal error. */
1483 find_step_target (inst_env_type *inst_env)
1487 unsigned short insn;
1489 /* Create a local register image and set the initial state. */
1490 for (i = 0; i < NUM_GENREGS; i++)
1492 inst_env->reg[i] = (unsigned long) read_register (i);
1494 offset = NUM_GENREGS;
1495 for (i = 0; i < NUM_SPECREGS; i++)
1497 inst_env->preg[i] = (unsigned long) read_register (offset + i);
1499 inst_env->branch_found = 0;
1500 inst_env->slot_needed = 0;
1501 inst_env->delay_slot_pc_active = 0;
1502 inst_env->prefix_found = 0;
1503 inst_env->invalid = 0;
1504 inst_env->xflag_found = 0;
1505 inst_env->disable_interrupt = 0;
1507 /* Look for a step target. */
1510 /* Read an instruction from the client. */
1511 insn = read_memory_unsigned_integer (inst_env->reg[PC_REGNUM], 2);
1513 /* If the instruction is not in a delay slot the new content of the
1514 PC is [PC] + 2. If the instruction is in a delay slot it is not
1515 that simple. Since a instruction in a delay slot cannot change
1516 the content of the PC, it does not matter what value PC will have.
1517 Just make sure it is a valid instruction. */
1518 if (!inst_env->delay_slot_pc_active)
1520 inst_env->reg[PC_REGNUM] += 2;
1524 inst_env->delay_slot_pc_active = 0;
1525 inst_env->reg[PC_REGNUM] = inst_env->delay_slot_pc;
1527 /* Analyse the present instruction. */
1528 i = find_cris_op (insn, inst_env);
1531 inst_env->invalid = 1;
1535 cris_gdb_func (cris_opcodes[i].op, insn, inst_env);
1537 } while (!inst_env->invalid
1538 && (inst_env->prefix_found || inst_env->xflag_found
1539 || inst_env->slot_needed));
1543 /* There is no hardware single-step support. The function find_step_target
1544 digs through the opcodes in order to find all possible targets.
1545 Either one ordinary target or two targets for branches may be found. */
1548 cris_software_single_step (enum target_signal ignore, int insert_breakpoints)
1550 inst_env_type inst_env;
1552 if (insert_breakpoints)
1554 /* Analyse the present instruction environment and insert
1556 int status = find_step_target (&inst_env);
1559 /* Could not find a target. FIXME: Should do something. */
1563 /* Insert at most two breakpoints. One for the next PC content
1564 and possibly another one for a branch, jump, etc. */
1565 next_pc = (CORE_ADDR) inst_env.reg[PC_REGNUM];
1566 target_insert_breakpoint (next_pc, break_mem[0]);
1567 if (inst_env.branch_found
1568 && (CORE_ADDR) inst_env.branch_break_address != next_pc)
1570 branch_target_address =
1571 (CORE_ADDR) inst_env.branch_break_address;
1572 target_insert_breakpoint (branch_target_address, break_mem[1]);
1573 branch_break_inserted = 1;
1579 /* Remove breakpoints. */
1580 target_remove_breakpoint (next_pc, break_mem[0]);
1581 if (branch_break_inserted)
1583 target_remove_breakpoint (branch_target_address, break_mem[1]);
1584 branch_break_inserted = 0;
1589 /* Calculates the prefix value for quick offset addressing mode. */
1592 quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env)
1594 /* It's invalid to be in a delay slot. You can't have a prefix to this
1595 instruction (not 100% sure). */
1596 if (inst_env->slot_needed || inst_env->prefix_found)
1598 inst_env->invalid = 1;
1602 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
1603 inst_env->prefix_value += cris_get_bdap_quick_offset (inst);
1605 /* A prefix doesn't change the xflag_found. But the rest of the flags
1607 inst_env->slot_needed = 0;
1608 inst_env->prefix_found = 1;
1611 /* Updates the autoincrement register. The size of the increment is derived
1612 from the size of the operation. The PC is always kept aligned on even
1616 process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env)
1618 if (size == INST_BYTE_SIZE)
1620 inst_env->reg[cris_get_operand1 (inst)] += 1;
1622 /* The PC must be word aligned, so increase the PC with one
1623 word even if the size is byte. */
1624 if (cris_get_operand1 (inst) == REG_PC)
1626 inst_env->reg[REG_PC] += 1;
1629 else if (size == INST_WORD_SIZE)
1631 inst_env->reg[cris_get_operand1 (inst)] += 2;
1633 else if (size == INST_DWORD_SIZE)
1635 inst_env->reg[cris_get_operand1 (inst)] += 4;
1640 inst_env->invalid = 1;
1644 /* Just a forward declaration. */
1646 static unsigned long get_data_from_address (unsigned short *inst,
1649 /* Calculates the prefix value for the general case of offset addressing
1653 bdap_prefix (unsigned short inst, inst_env_type *inst_env)
1658 /* It's invalid to be in a delay slot. */
1659 if (inst_env->slot_needed || inst_env->prefix_found)
1661 inst_env->invalid = 1;
1665 /* The calculation of prefix_value used to be after process_autoincrement,
1666 but that fails for an instruction such as jsr [$r0+12] which is encoded
1667 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
1668 mustn't be incremented until we have read it and what it points at. */
1669 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
1671 /* The offset is an indirection of the contents of the operand1 register. */
1672 inst_env->prefix_value +=
1673 get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)]);
1675 if (cris_get_mode (inst) == AUTOINC_MODE)
1677 process_autoincrement (cris_get_size (inst), inst, inst_env);
1680 /* A prefix doesn't change the xflag_found. But the rest of the flags
1682 inst_env->slot_needed = 0;
1683 inst_env->prefix_found = 1;
1686 /* Calculates the prefix value for the index addressing mode. */
1689 biap_prefix (unsigned short inst, inst_env_type *inst_env)
1691 /* It's invalid to be in a delay slot. I can't see that it's possible to
1692 have a prefix to this instruction. So I will treat this as invalid. */
1693 if (inst_env->slot_needed || inst_env->prefix_found)
1695 inst_env->invalid = 1;
1699 inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)];
1701 /* The offset is the operand2 value shifted the size of the instruction
1703 inst_env->prefix_value +=
1704 inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst);
1706 /* If the PC is operand1 (base) the address used is the address after
1707 the main instruction, i.e. address + 2 (the PC is already compensated
1708 for the prefix operation). */
1709 if (cris_get_operand1 (inst) == REG_PC)
1711 inst_env->prefix_value += 2;
1714 /* A prefix doesn't change the xflag_found. But the rest of the flags
1716 inst_env->slot_needed = 0;
1717 inst_env->xflag_found = 0;
1718 inst_env->prefix_found = 1;
1721 /* Calculates the prefix value for the double indirect addressing mode. */
1724 dip_prefix (unsigned short inst, inst_env_type *inst_env)
1729 /* It's invalid to be in a delay slot. */
1730 if (inst_env->slot_needed || inst_env->prefix_found)
1732 inst_env->invalid = 1;
1736 /* The prefix value is one dereference of the contents of the operand1
1738 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
1739 inst_env->prefix_value = read_memory_unsigned_integer (address, 4);
1741 /* Check if the mode is autoincrement. */
1742 if (cris_get_mode (inst) == AUTOINC_MODE)
1744 inst_env->reg[cris_get_operand1 (inst)] += 4;
1747 /* A prefix doesn't change the xflag_found. But the rest of the flags
1749 inst_env->slot_needed = 0;
1750 inst_env->xflag_found = 0;
1751 inst_env->prefix_found = 1;
1754 /* Finds the destination for a branch with 8-bits offset. */
1757 eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
1762 /* If we have a prefix or are in a delay slot it's bad. */
1763 if (inst_env->slot_needed || inst_env->prefix_found)
1765 inst_env->invalid = 1;
1769 /* We have a branch, find out where the branch will land. */
1770 offset = cris_get_branch_short_offset (inst);
1772 /* Check if the offset is signed. */
1773 if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK)
1778 /* The offset ends with the sign bit, set it to zero. The address
1779 should always be word aligned. */
1780 offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK;
1782 inst_env->branch_found = 1;
1783 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
1785 inst_env->slot_needed = 1;
1786 inst_env->prefix_found = 0;
1787 inst_env->xflag_found = 0;
1788 inst_env->disable_interrupt = 1;
1791 /* Finds the destination for a branch with 16-bits offset. */
1794 sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
1798 /* If we have a prefix or is in a delay slot it's bad. */
1799 if (inst_env->slot_needed || inst_env->prefix_found)
1801 inst_env->invalid = 1;
1805 /* We have a branch, find out the offset for the branch. */
1806 offset = read_memory_integer (inst_env->reg[REG_PC], 2);
1808 /* The instruction is one word longer than normal, so add one word
1810 inst_env->reg[REG_PC] += 2;
1812 inst_env->branch_found = 1;
1813 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
1816 inst_env->slot_needed = 1;
1817 inst_env->prefix_found = 0;
1818 inst_env->xflag_found = 0;
1819 inst_env->disable_interrupt = 1;
1822 /* Handles the ABS instruction. */
1825 abs_op (unsigned short inst, inst_env_type *inst_env)
1830 /* ABS can't have a prefix, so it's bad if it does. */
1831 if (inst_env->prefix_found)
1833 inst_env->invalid = 1;
1837 /* Check if the operation affects the PC. */
1838 if (cris_get_operand2 (inst) == REG_PC)
1841 /* It's invalid to change to the PC if we are in a delay slot. */
1842 if (inst_env->slot_needed)
1844 inst_env->invalid = 1;
1848 value = (long) inst_env->reg[REG_PC];
1850 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
1851 if (value != SIGNED_DWORD_MASK)
1854 inst_env->reg[REG_PC] = (long) value;
1858 inst_env->slot_needed = 0;
1859 inst_env->prefix_found = 0;
1860 inst_env->xflag_found = 0;
1861 inst_env->disable_interrupt = 0;
1864 /* Handles the ADDI instruction. */
1867 addi_op (unsigned short inst, inst_env_type *inst_env)
1869 /* It's invalid to have the PC as base register. And ADDI can't have
1871 if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC))
1873 inst_env->invalid = 1;
1877 inst_env->slot_needed = 0;
1878 inst_env->prefix_found = 0;
1879 inst_env->xflag_found = 0;
1880 inst_env->disable_interrupt = 0;
1883 /* Handles the ASR instruction. */
1886 asr_op (unsigned short inst, inst_env_type *inst_env)
1889 unsigned long value;
1890 unsigned long signed_extend_mask = 0;
1892 /* ASR can't have a prefix, so check that it doesn't. */
1893 if (inst_env->prefix_found)
1895 inst_env->invalid = 1;
1899 /* Check if the PC is the target register. */
1900 if (cris_get_operand2 (inst) == REG_PC)
1902 /* It's invalid to change the PC in a delay slot. */
1903 if (inst_env->slot_needed)
1905 inst_env->invalid = 1;
1908 /* Get the number of bits to shift. */
1909 shift_steps = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]);
1910 value = inst_env->reg[REG_PC];
1912 /* Find out how many bits the operation should apply to. */
1913 if (cris_get_size (inst) == INST_BYTE_SIZE)
1915 if (value & SIGNED_BYTE_MASK)
1917 signed_extend_mask = 0xFF;
1918 signed_extend_mask = signed_extend_mask >> shift_steps;
1919 signed_extend_mask = ~signed_extend_mask;
1921 value = value >> shift_steps;
1922 value |= signed_extend_mask;
1924 inst_env->reg[REG_PC] &= 0xFFFFFF00;
1925 inst_env->reg[REG_PC] |= value;
1927 else if (cris_get_size (inst) == INST_WORD_SIZE)
1929 if (value & SIGNED_WORD_MASK)
1931 signed_extend_mask = 0xFFFF;
1932 signed_extend_mask = signed_extend_mask >> shift_steps;
1933 signed_extend_mask = ~signed_extend_mask;
1935 value = value >> shift_steps;
1936 value |= signed_extend_mask;
1938 inst_env->reg[REG_PC] &= 0xFFFF0000;
1939 inst_env->reg[REG_PC] |= value;
1941 else if (cris_get_size (inst) == INST_DWORD_SIZE)
1943 if (value & SIGNED_DWORD_MASK)
1945 signed_extend_mask = 0xFFFFFFFF;
1946 signed_extend_mask = signed_extend_mask >> shift_steps;
1947 signed_extend_mask = ~signed_extend_mask;
1949 value = value >> shift_steps;
1950 value |= signed_extend_mask;
1951 inst_env->reg[REG_PC] = value;
1954 inst_env->slot_needed = 0;
1955 inst_env->prefix_found = 0;
1956 inst_env->xflag_found = 0;
1957 inst_env->disable_interrupt = 0;
1960 /* Handles the ASRQ instruction. */
1963 asrq_op (unsigned short inst, inst_env_type *inst_env)
1967 unsigned long value;
1968 unsigned long signed_extend_mask = 0;
1970 /* ASRQ can't have a prefix, so check that it doesn't. */
1971 if (inst_env->prefix_found)
1973 inst_env->invalid = 1;
1977 /* Check if the PC is the target register. */
1978 if (cris_get_operand2 (inst) == REG_PC)
1981 /* It's invalid to change the PC in a delay slot. */
1982 if (inst_env->slot_needed)
1984 inst_env->invalid = 1;
1987 /* The shift size is given as a 5 bit quick value, i.e. we don't
1988 want the the sign bit of the quick value. */
1989 shift_steps = cris_get_asr_shift_steps (inst);
1990 value = inst_env->reg[REG_PC];
1991 if (value & SIGNED_DWORD_MASK)
1993 signed_extend_mask = 0xFFFFFFFF;
1994 signed_extend_mask = signed_extend_mask >> shift_steps;
1995 signed_extend_mask = ~signed_extend_mask;
1997 value = value >> shift_steps;
1998 value |= signed_extend_mask;
1999 inst_env->reg[REG_PC] = value;
2001 inst_env->slot_needed = 0;
2002 inst_env->prefix_found = 0;
2003 inst_env->xflag_found = 0;
2004 inst_env->disable_interrupt = 0;
2007 /* Handles the AX, EI and SETF instruction. */
2010 ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env)
2012 if (inst_env->prefix_found)
2014 inst_env->invalid = 1;
2017 /* Check if the instruction is setting the X flag. */
2018 if (cris_is_xflag_bit_on (inst))
2020 inst_env->xflag_found = 1;
2024 inst_env->xflag_found = 0;
2026 inst_env->slot_needed = 0;
2027 inst_env->prefix_found = 0;
2028 inst_env->disable_interrupt = 1;
2031 /* Checks if the instruction is in assign mode. If so, it updates the assign
2032 register. Note that check_assign assumes that the caller has checked that
2033 there is a prefix to this instruction. The mode check depends on this. */
2036 check_assign (unsigned short inst, inst_env_type *inst_env)
2038 /* Check if it's an assign addressing mode. */
2039 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2041 /* Assign the prefix value to operand 1. */
2042 inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value;
2046 /* Handles the 2-operand BOUND instruction. */
2049 two_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2051 /* It's invalid to have the PC as the index operand. */
2052 if (cris_get_operand2 (inst) == REG_PC)
2054 inst_env->invalid = 1;
2057 /* Check if we have a prefix. */
2058 if (inst_env->prefix_found)
2060 check_assign (inst, inst_env);
2062 /* Check if this is an autoincrement mode. */
2063 else if (cris_get_mode (inst) == AUTOINC_MODE)
2065 /* It's invalid to change the PC in a delay slot. */
2066 if (inst_env->slot_needed)
2068 inst_env->invalid = 1;
2071 process_autoincrement (cris_get_size (inst), inst, inst_env);
2073 inst_env->slot_needed = 0;
2074 inst_env->prefix_found = 0;
2075 inst_env->xflag_found = 0;
2076 inst_env->disable_interrupt = 0;
2079 /* Handles the 3-operand BOUND instruction. */
2082 three_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2084 /* It's an error if we haven't got a prefix. And it's also an error
2085 if the PC is the destination register. */
2086 if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC))
2088 inst_env->invalid = 1;
2091 inst_env->slot_needed = 0;
2092 inst_env->prefix_found = 0;
2093 inst_env->xflag_found = 0;
2094 inst_env->disable_interrupt = 0;
2097 /* Clears the status flags in inst_env. */
2100 btst_nop_op (unsigned short inst, inst_env_type *inst_env)
2102 /* It's an error if we have got a prefix. */
2103 if (inst_env->prefix_found)
2105 inst_env->invalid = 1;
2109 inst_env->slot_needed = 0;
2110 inst_env->prefix_found = 0;
2111 inst_env->xflag_found = 0;
2112 inst_env->disable_interrupt = 0;
2115 /* Clears the status flags in inst_env. */
2118 clearf_di_op (unsigned short inst, inst_env_type *inst_env)
2120 /* It's an error if we have got a prefix. */
2121 if (inst_env->prefix_found)
2123 inst_env->invalid = 1;
2127 inst_env->slot_needed = 0;
2128 inst_env->prefix_found = 0;
2129 inst_env->xflag_found = 0;
2130 inst_env->disable_interrupt = 1;
2133 /* Handles the CLEAR instruction if it's in register mode. */
2136 reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env)
2138 /* Check if the target is the PC. */
2139 if (cris_get_operand2 (inst) == REG_PC)
2141 /* The instruction will clear the instruction's size bits. */
2142 int clear_size = cris_get_clear_size (inst);
2143 if (clear_size == INST_BYTE_SIZE)
2145 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00;
2147 if (clear_size == INST_WORD_SIZE)
2149 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000;
2151 if (clear_size == INST_DWORD_SIZE)
2153 inst_env->delay_slot_pc = 0x0;
2155 /* The jump will be delayed with one delay slot. So we need a delay
2157 inst_env->slot_needed = 1;
2158 inst_env->delay_slot_pc_active = 1;
2162 /* The PC will not change => no delay slot. */
2163 inst_env->slot_needed = 0;
2165 inst_env->prefix_found = 0;
2166 inst_env->xflag_found = 0;
2167 inst_env->disable_interrupt = 0;
2170 /* Handles the TEST instruction if it's in register mode. */
2173 reg_mode_test_op (unsigned short inst, inst_env_type *inst_env)
2175 /* It's an error if we have got a prefix. */
2176 if (inst_env->prefix_found)
2178 inst_env->invalid = 1;
2181 inst_env->slot_needed = 0;
2182 inst_env->prefix_found = 0;
2183 inst_env->xflag_found = 0;
2184 inst_env->disable_interrupt = 0;
2188 /* Handles the CLEAR and TEST instruction if the instruction isn't
2189 in register mode. */
2192 none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env)
2194 /* Check if we are in a prefix mode. */
2195 if (inst_env->prefix_found)
2197 /* The only way the PC can change is if this instruction is in
2198 assign addressing mode. */
2199 check_assign (inst, inst_env);
2201 /* Indirect mode can't change the PC so just check if the mode is
2203 else if (cris_get_mode (inst) == AUTOINC_MODE)
2205 process_autoincrement (cris_get_size (inst), inst, inst_env);
2207 inst_env->slot_needed = 0;
2208 inst_env->prefix_found = 0;
2209 inst_env->xflag_found = 0;
2210 inst_env->disable_interrupt = 0;
2213 /* Checks that the PC isn't the destination register or the instructions has
2217 dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env)
2219 /* It's invalid to have the PC as the destination. The instruction can't
2221 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2223 inst_env->invalid = 1;
2227 inst_env->slot_needed = 0;
2228 inst_env->prefix_found = 0;
2229 inst_env->xflag_found = 0;
2230 inst_env->disable_interrupt = 0;
2233 /* Checks that the instruction doesn't have a prefix. */
2236 break_op (unsigned short inst, inst_env_type *inst_env)
2238 /* The instruction can't have a prefix. */
2239 if (inst_env->prefix_found)
2241 inst_env->invalid = 1;
2245 inst_env->slot_needed = 0;
2246 inst_env->prefix_found = 0;
2247 inst_env->xflag_found = 0;
2248 inst_env->disable_interrupt = 1;
2251 /* Checks that the PC isn't the destination register and that the instruction
2252 doesn't have a prefix. */
2255 scc_op (unsigned short inst, inst_env_type *inst_env)
2257 /* It's invalid to have the PC as the destination. The instruction can't
2259 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2261 inst_env->invalid = 1;
2265 inst_env->slot_needed = 0;
2266 inst_env->prefix_found = 0;
2267 inst_env->xflag_found = 0;
2268 inst_env->disable_interrupt = 1;
2271 /* Handles the register mode JUMP instruction. */
2274 reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2276 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2277 you can't have a prefix. */
2278 if ((inst_env->slot_needed) || (inst_env->prefix_found))
2280 inst_env->invalid = 1;
2284 /* Just change the PC. */
2285 inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)];
2286 inst_env->slot_needed = 0;
2287 inst_env->prefix_found = 0;
2288 inst_env->xflag_found = 0;
2289 inst_env->disable_interrupt = 1;
2292 /* Handles the JUMP instruction for all modes except register. */
2295 none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2297 unsigned long newpc;
2300 /* It's invalid to do a JUMP in a delay slot. */
2301 if (inst_env->slot_needed)
2303 inst_env->invalid = 1;
2307 /* Check if we have a prefix. */
2308 if (inst_env->prefix_found)
2310 check_assign (inst, inst_env);
2312 /* Get the new value for the the PC. */
2314 read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value,
2319 /* Get the new value for the PC. */
2320 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2321 newpc = read_memory_unsigned_integer (address, 4);
2323 /* Check if we should increment a register. */
2324 if (cris_get_mode (inst) == AUTOINC_MODE)
2326 inst_env->reg[cris_get_operand1 (inst)] += 4;
2329 inst_env->reg[REG_PC] = newpc;
2331 inst_env->slot_needed = 0;
2332 inst_env->prefix_found = 0;
2333 inst_env->xflag_found = 0;
2334 inst_env->disable_interrupt = 1;
2337 /* Handles moves to special registers (aka P-register) for all modes. */
2340 move_to_preg_op (unsigned short inst, inst_env_type *inst_env)
2342 if (inst_env->prefix_found)
2344 /* The instruction has a prefix that means we are only interested if
2345 the instruction is in assign mode. */
2346 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2348 /* The prefix handles the problem if we are in a delay slot. */
2349 if (cris_get_operand1 (inst) == REG_PC)
2351 /* Just take care of the assign. */
2352 check_assign (inst, inst_env);
2356 else if (cris_get_mode (inst) == AUTOINC_MODE)
2358 /* The instruction doesn't have a prefix, the only case left that we
2359 are interested in is the autoincrement mode. */
2360 if (cris_get_operand1 (inst) == REG_PC)
2362 /* If the PC is to be incremented it's invalid to be in a
2364 if (inst_env->slot_needed)
2366 inst_env->invalid = 1;
2370 /* The increment depends on the size of the special register. */
2371 if (cris_register_size (cris_get_operand2 (inst)) == 1)
2373 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2375 else if (cris_register_size (cris_get_operand2 (inst)) == 2)
2377 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2381 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2385 inst_env->slot_needed = 0;
2386 inst_env->prefix_found = 0;
2387 inst_env->xflag_found = 0;
2388 inst_env->disable_interrupt = 1;
2391 /* Handles moves from special registers (aka P-register) for all modes
2395 none_reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env)
2397 if (inst_env->prefix_found)
2399 /* The instruction has a prefix that means we are only interested if
2400 the instruction is in assign mode. */
2401 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2403 /* The prefix handles the problem if we are in a delay slot. */
2404 if (cris_get_operand1 (inst) == REG_PC)
2406 /* Just take care of the assign. */
2407 check_assign (inst, inst_env);
2411 /* The instruction doesn't have a prefix, the only case left that we
2412 are interested in is the autoincrement mode. */
2413 else if (cris_get_mode (inst) == AUTOINC_MODE)
2415 if (cris_get_operand1 (inst) == REG_PC)
2417 /* If the PC is to be incremented it's invalid to be in a
2419 if (inst_env->slot_needed)
2421 inst_env->invalid = 1;
2425 /* The increment depends on the size of the special register. */
2426 if (cris_register_size (cris_get_operand2 (inst)) == 1)
2428 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2430 else if (cris_register_size (cris_get_operand2 (inst)) == 2)
2432 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2436 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2440 inst_env->slot_needed = 0;
2441 inst_env->prefix_found = 0;
2442 inst_env->xflag_found = 0;
2443 inst_env->disable_interrupt = 1;
2446 /* Handles moves from special registers (aka P-register) when the mode
2450 reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env)
2452 /* Register mode move from special register can't have a prefix. */
2453 if (inst_env->prefix_found)
2455 inst_env->invalid = 1;
2459 if (cris_get_operand1 (inst) == REG_PC)
2461 /* It's invalid to change the PC in a delay slot. */
2462 if (inst_env->slot_needed)
2464 inst_env->invalid = 1;
2467 /* The destination is the PC, the jump will have a delay slot. */
2468 inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)];
2469 inst_env->slot_needed = 1;
2470 inst_env->delay_slot_pc_active = 1;
2474 /* If the destination isn't PC, there will be no jump. */
2475 inst_env->slot_needed = 0;
2477 inst_env->prefix_found = 0;
2478 inst_env->xflag_found = 0;
2479 inst_env->disable_interrupt = 1;
2482 /* Handles the MOVEM from memory to general register instruction. */
2485 move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env)
2487 if (inst_env->prefix_found)
2489 /* The prefix handles the problem if we are in a delay slot. Is the
2490 MOVEM instruction going to change the PC? */
2491 if (cris_get_operand2 (inst) >= REG_PC)
2493 inst_env->reg[REG_PC] =
2494 read_memory_unsigned_integer (inst_env->prefix_value, 4);
2496 /* The assign value is the value after the increment. Normally, the
2497 assign value is the value before the increment. */
2498 if ((cris_get_operand1 (inst) == REG_PC)
2499 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
2501 inst_env->reg[REG_PC] = inst_env->prefix_value;
2502 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
2507 /* Is the MOVEM instruction going to change the PC? */
2508 if (cris_get_operand2 (inst) == REG_PC)
2510 /* It's invalid to change the PC in a delay slot. */
2511 if (inst_env->slot_needed)
2513 inst_env->invalid = 1;
2516 inst_env->reg[REG_PC] =
2517 read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)],
2520 /* The increment is not depending on the size, instead it's depending
2521 on the number of registers loaded from memory. */
2522 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
2524 /* It's invalid to change the PC in a delay slot. */
2525 if (inst_env->slot_needed)
2527 inst_env->invalid = 1;
2530 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
2533 inst_env->slot_needed = 0;
2534 inst_env->prefix_found = 0;
2535 inst_env->xflag_found = 0;
2536 inst_env->disable_interrupt = 0;
2539 /* Handles the MOVEM to memory from general register instruction. */
2542 move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env)
2544 if (inst_env->prefix_found)
2546 /* The assign value is the value after the increment. Normally, the
2547 assign value is the value before the increment. */
2548 if ((cris_get_operand1 (inst) == REG_PC) &&
2549 (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
2551 /* The prefix handles the problem if we are in a delay slot. */
2552 inst_env->reg[REG_PC] = inst_env->prefix_value;
2553 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
2558 /* The increment is not depending on the size, instead it's depending
2559 on the number of registers loaded to memory. */
2560 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
2562 /* It's invalid to change the PC in a delay slot. */
2563 if (inst_env->slot_needed)
2565 inst_env->invalid = 1;
2568 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
2571 inst_env->slot_needed = 0;
2572 inst_env->prefix_found = 0;
2573 inst_env->xflag_found = 0;
2574 inst_env->disable_interrupt = 0;
2577 /* Handles the intructions that's not yet implemented, by setting
2578 inst_env->invalid to true. */
2581 not_implemented_op (unsigned short inst, inst_env_type *inst_env)
2583 inst_env->invalid = 1;
2586 /* Handles the XOR instruction. */
2589 xor_op (unsigned short inst, inst_env_type *inst_env)
2591 /* XOR can't have a prefix. */
2592 if (inst_env->prefix_found)
2594 inst_env->invalid = 1;
2598 /* Check if the PC is the target. */
2599 if (cris_get_operand2 (inst) == REG_PC)
2601 /* It's invalid to change the PC in a delay slot. */
2602 if (inst_env->slot_needed)
2604 inst_env->invalid = 1;
2607 inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)];
2609 inst_env->slot_needed = 0;
2610 inst_env->prefix_found = 0;
2611 inst_env->xflag_found = 0;
2612 inst_env->disable_interrupt = 0;
2615 /* Handles the MULS instruction. */
2618 muls_op (unsigned short inst, inst_env_type *inst_env)
2620 /* MULS/U can't have a prefix. */
2621 if (inst_env->prefix_found)
2623 inst_env->invalid = 1;
2627 /* Consider it invalid if the PC is the target. */
2628 if (cris_get_operand2 (inst) == REG_PC)
2630 inst_env->invalid = 1;
2633 inst_env->slot_needed = 0;
2634 inst_env->prefix_found = 0;
2635 inst_env->xflag_found = 0;
2636 inst_env->disable_interrupt = 0;
2639 /* Handles the MULU instruction. */
2642 mulu_op (unsigned short inst, inst_env_type *inst_env)
2644 /* MULS/U can't have a prefix. */
2645 if (inst_env->prefix_found)
2647 inst_env->invalid = 1;
2651 /* Consider it invalid if the PC is the target. */
2652 if (cris_get_operand2 (inst) == REG_PC)
2654 inst_env->invalid = 1;
2657 inst_env->slot_needed = 0;
2658 inst_env->prefix_found = 0;
2659 inst_env->xflag_found = 0;
2660 inst_env->disable_interrupt = 0;
2663 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
2664 The MOVE instruction is the move from source to register. */
2667 add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env,
2668 unsigned long source1, unsigned long source2)
2670 unsigned long pc_mask;
2671 unsigned long operation_mask;
2673 /* Find out how many bits the operation should apply to. */
2674 if (cris_get_size (inst) == INST_BYTE_SIZE)
2676 pc_mask = 0xFFFFFF00;
2677 operation_mask = 0xFF;
2679 else if (cris_get_size (inst) == INST_WORD_SIZE)
2681 pc_mask = 0xFFFF0000;
2682 operation_mask = 0xFFFF;
2684 else if (cris_get_size (inst) == INST_DWORD_SIZE)
2687 operation_mask = 0xFFFFFFFF;
2691 /* The size is out of range. */
2692 inst_env->invalid = 1;
2696 /* The instruction just works on uw_operation_mask bits. */
2697 source2 &= operation_mask;
2698 source1 &= operation_mask;
2700 /* Now calculate the result. The opcode's 3 first bits separates
2701 the different actions. */
2702 switch (cris_get_opcode (inst) & 7)
2712 case 2: /* subtract */
2716 case 3: /* compare */
2728 inst_env->invalid = 1;
2734 /* Make sure that the result doesn't contain more than the instruction
2736 source2 &= operation_mask;
2738 /* Calculate the new breakpoint address. */
2739 inst_env->reg[REG_PC] &= pc_mask;
2740 inst_env->reg[REG_PC] |= source1;
2744 /* Extends the value from either byte or word size to a dword. If the mode
2745 is zero extend then the value is extended with zero. If instead the mode
2746 is signed extend the sign bit of the value is taken into consideration. */
2748 static unsigned long
2749 do_sign_or_zero_extend (unsigned long value, unsigned short *inst)
2751 /* The size can be either byte or word, check which one it is.
2752 Don't check the highest bit, it's indicating if it's a zero
2754 if (cris_get_size (*inst) & INST_WORD_SIZE)
2759 /* Check if the instruction is signed extend. If so, check if value has
2761 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK))
2763 value |= SIGNED_WORD_EXTEND_MASK;
2771 /* Check if the instruction is signed extend. If so, check if value has
2773 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK))
2775 value |= SIGNED_BYTE_EXTEND_MASK;
2778 /* The size should now be dword. */
2779 cris_set_size_to_dword (inst);
2783 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
2784 instruction. The MOVE instruction is the move from source to register. */
2787 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
2788 inst_env_type *inst_env)
2790 unsigned long operand1;
2791 unsigned long operand2;
2793 /* It's invalid to have a prefix to the instruction. This is a register
2794 mode instruction and can't have a prefix. */
2795 if (inst_env->prefix_found)
2797 inst_env->invalid = 1;
2800 /* Check if the instruction has PC as its target. */
2801 if (cris_get_operand2 (inst) == REG_PC)
2803 if (inst_env->slot_needed)
2805 inst_env->invalid = 1;
2808 /* The instruction has the PC as its target register. */
2809 operand1 = inst_env->reg[cris_get_operand1 (inst)];
2810 operand2 = inst_env->reg[REG_PC];
2812 /* Check if it's a extend, signed or zero instruction. */
2813 if (cris_get_opcode (inst) < 4)
2815 operand1 = do_sign_or_zero_extend (operand1, &inst);
2817 /* Calculate the PC value after the instruction, i.e. where the
2818 breakpoint should be. The order of the udw_operands is vital. */
2819 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
2821 inst_env->slot_needed = 0;
2822 inst_env->prefix_found = 0;
2823 inst_env->xflag_found = 0;
2824 inst_env->disable_interrupt = 0;
2827 /* Returns the data contained at address. The size of the data is derived from
2828 the size of the operation. If the instruction is a zero or signed
2829 extend instruction, the size field is changed in instruction. */
2831 static unsigned long
2832 get_data_from_address (unsigned short *inst, CORE_ADDR address)
2834 int size = cris_get_size (*inst);
2835 unsigned long value;
2837 /* If it's an extend instruction we don't want the signed extend bit,
2838 because it influences the size. */
2839 if (cris_get_opcode (*inst) < 4)
2841 size &= ~SIGNED_EXTEND_BIT_MASK;
2843 /* Is there a need for checking the size? Size should contain the number of
2846 value = read_memory_unsigned_integer (address, size);
2848 /* Check if it's an extend, signed or zero instruction. */
2849 if (cris_get_opcode (*inst) < 4)
2851 value = do_sign_or_zero_extend (value, inst);
2856 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
2857 instructions. The MOVE instruction is the move from source to register. */
2860 handle_prefix_assign_mode_for_aritm_op (unsigned short inst,
2861 inst_env_type *inst_env)
2863 unsigned long operand2;
2864 unsigned long operand3;
2866 check_assign (inst, inst_env);
2867 if (cris_get_operand2 (inst) == REG_PC)
2869 operand2 = inst_env->reg[REG_PC];
2871 /* Get the value of the third operand. */
2872 operand3 = get_data_from_address (&inst, inst_env->prefix_value);
2874 /* Calculate the PC value after the instruction, i.e. where the
2875 breakpoint should be. The order of the udw_operands is vital. */
2876 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
2878 inst_env->slot_needed = 0;
2879 inst_env->prefix_found = 0;
2880 inst_env->xflag_found = 0;
2881 inst_env->disable_interrupt = 0;
2884 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
2885 OR instructions. Note that for this to work as expected, the calling
2886 function must have made sure that there is a prefix to this instruction. */
2889 three_operand_add_sub_cmp_and_or_op (unsigned short inst,
2890 inst_env_type *inst_env)
2892 unsigned long operand2;
2893 unsigned long operand3;
2895 if (cris_get_operand1 (inst) == REG_PC)
2897 /* The PC will be changed by the instruction. */
2898 operand2 = inst_env->reg[cris_get_operand2 (inst)];
2900 /* Get the value of the third operand. */
2901 operand3 = get_data_from_address (&inst, inst_env->prefix_value);
2903 /* Calculate the PC value after the instruction, i.e. where the
2904 breakpoint should be. */
2905 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
2907 inst_env->slot_needed = 0;
2908 inst_env->prefix_found = 0;
2909 inst_env->xflag_found = 0;
2910 inst_env->disable_interrupt = 0;
2913 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
2914 instructions. The MOVE instruction is the move from source to register. */
2917 handle_prefix_index_mode_for_aritm_op (unsigned short inst,
2918 inst_env_type *inst_env)
2920 if (cris_get_operand1 (inst) != cris_get_operand2 (inst))
2922 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
2923 SUB, AND or OR something weird is going on (if everything works these
2924 instructions should end up in the three operand version). */
2925 inst_env->invalid = 1;
2930 /* three_operand_add_sub_cmp_and_or does the same as we should do here
2932 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
2934 inst_env->slot_needed = 0;
2935 inst_env->prefix_found = 0;
2936 inst_env->xflag_found = 0;
2937 inst_env->disable_interrupt = 0;
2940 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
2941 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
2942 source to register. */
2945 handle_inc_and_index_mode_for_aritm_op (unsigned short inst,
2946 inst_env_type *inst_env)
2948 unsigned long operand1;
2949 unsigned long operand2;
2950 unsigned long operand3;
2953 /* The instruction is either an indirect or autoincrement addressing mode.
2954 Check if the destination register is the PC. */
2955 if (cris_get_operand2 (inst) == REG_PC)
2957 /* Must be done here, get_data_from_address may change the size
2959 size = cris_get_size (inst);
2960 operand2 = inst_env->reg[REG_PC];
2962 /* Get the value of the third operand, i.e. the indirect operand. */
2963 operand1 = inst_env->reg[cris_get_operand1 (inst)];
2964 operand3 = get_data_from_address (&inst, operand1);
2966 /* Calculate the PC value after the instruction, i.e. where the
2967 breakpoint should be. The order of the udw_operands is vital. */
2968 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
2970 /* If this is an autoincrement addressing mode, check if the increment
2972 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
2974 /* Get the size field. */
2975 size = cris_get_size (inst);
2977 /* If it's an extend instruction we don't want the signed extend bit,
2978 because it influences the size. */
2979 if (cris_get_opcode (inst) < 4)
2981 size &= ~SIGNED_EXTEND_BIT_MASK;
2983 process_autoincrement (size, inst, inst_env);
2985 inst_env->slot_needed = 0;
2986 inst_env->prefix_found = 0;
2987 inst_env->xflag_found = 0;
2988 inst_env->disable_interrupt = 0;
2991 /* Handles the two-operand addressing mode, all modes except register, for
2992 the ADD, SUB CMP, AND and OR instruction. */
2995 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
2996 inst_env_type *inst_env)
2998 if (inst_env->prefix_found)
3000 if (cris_get_mode (inst) == PREFIX_INDEX_MODE)
3002 handle_prefix_index_mode_for_aritm_op (inst, inst_env);
3004 else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
3006 handle_prefix_assign_mode_for_aritm_op (inst, inst_env);
3010 /* The mode is invalid for a prefixed base instruction. */
3011 inst_env->invalid = 1;
3017 handle_inc_and_index_mode_for_aritm_op (inst, inst_env);
3021 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3024 quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env)
3026 unsigned long operand1;
3027 unsigned long operand2;
3029 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3030 instruction and can't have a prefix. */
3031 if (inst_env->prefix_found)
3033 inst_env->invalid = 1;
3037 /* Check if the instruction has PC as its target. */
3038 if (cris_get_operand2 (inst) == REG_PC)
3040 if (inst_env->slot_needed)
3042 inst_env->invalid = 1;
3045 operand1 = cris_get_quick_value (inst);
3046 operand2 = inst_env->reg[REG_PC];
3048 /* The size should now be dword. */
3049 cris_set_size_to_dword (&inst);
3051 /* Calculate the PC value after the instruction, i.e. where the
3052 breakpoint should be. */
3053 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3055 inst_env->slot_needed = 0;
3056 inst_env->prefix_found = 0;
3057 inst_env->xflag_found = 0;
3058 inst_env->disable_interrupt = 0;
3061 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3064 quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env)
3066 unsigned long operand1;
3067 unsigned long operand2;
3069 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3070 instruction and can't have a prefix. */
3071 if (inst_env->prefix_found)
3073 inst_env->invalid = 1;
3076 /* Check if the instruction has PC as its target. */
3077 if (cris_get_operand2 (inst) == REG_PC)
3079 if (inst_env->slot_needed)
3081 inst_env->invalid = 1;
3084 /* The instruction has the PC as its target register. */
3085 operand1 = cris_get_quick_value (inst);
3086 operand2 = inst_env->reg[REG_PC];
3088 /* The quick value is signed, so check if we must do a signed extend. */
3089 if (operand1 & SIGNED_QUICK_VALUE_MASK)
3092 operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK;
3094 /* The size should now be dword. */
3095 cris_set_size_to_dword (&inst);
3097 /* Calculate the PC value after the instruction, i.e. where the
3098 breakpoint should be. */
3099 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3101 inst_env->slot_needed = 0;
3102 inst_env->prefix_found = 0;
3103 inst_env->xflag_found = 0;
3104 inst_env->disable_interrupt = 0;
3107 /* Translate op_type to a function and call it. */
3110 cris_gdb_func (enum cris_op_type op_type, unsigned short inst,
3111 inst_env_type *inst_env)
3115 case cris_not_implemented_op:
3116 not_implemented_op (inst, inst_env);
3120 abs_op (inst, inst_env);
3124 addi_op (inst, inst_env);
3128 asr_op (inst, inst_env);
3132 asrq_op (inst, inst_env);
3135 case cris_ax_ei_setf_op:
3136 ax_ei_setf_op (inst, inst_env);
3139 case cris_bdap_prefix:
3140 bdap_prefix (inst, inst_env);
3143 case cris_biap_prefix:
3144 biap_prefix (inst, inst_env);
3148 break_op (inst, inst_env);
3151 case cris_btst_nop_op:
3152 btst_nop_op (inst, inst_env);
3155 case cris_clearf_di_op:
3156 clearf_di_op (inst, inst_env);
3159 case cris_dip_prefix:
3160 dip_prefix (inst, inst_env);
3163 case cris_dstep_logshift_mstep_neg_not_op:
3164 dstep_logshift_mstep_neg_not_op (inst, inst_env);
3167 case cris_eight_bit_offset_branch_op:
3168 eight_bit_offset_branch_op (inst, inst_env);
3171 case cris_move_mem_to_reg_movem_op:
3172 move_mem_to_reg_movem_op (inst, inst_env);
3175 case cris_move_reg_to_mem_movem_op:
3176 move_reg_to_mem_movem_op (inst, inst_env);
3179 case cris_move_to_preg_op:
3180 move_to_preg_op (inst, inst_env);
3184 muls_op (inst, inst_env);
3188 mulu_op (inst, inst_env);
3191 case cris_none_reg_mode_add_sub_cmp_and_or_move_op:
3192 none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3195 case cris_none_reg_mode_clear_test_op:
3196 none_reg_mode_clear_test_op (inst, inst_env);
3199 case cris_none_reg_mode_jump_op:
3200 none_reg_mode_jump_op (inst, inst_env);
3203 case cris_none_reg_mode_move_from_preg_op:
3204 none_reg_mode_move_from_preg_op (inst, inst_env);
3207 case cris_quick_mode_add_sub_op:
3208 quick_mode_add_sub_op (inst, inst_env);
3211 case cris_quick_mode_and_cmp_move_or_op:
3212 quick_mode_and_cmp_move_or_op (inst, inst_env);
3215 case cris_quick_mode_bdap_prefix:
3216 quick_mode_bdap_prefix (inst, inst_env);
3219 case cris_reg_mode_add_sub_cmp_and_or_move_op:
3220 reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3223 case cris_reg_mode_clear_op:
3224 reg_mode_clear_op (inst, inst_env);
3227 case cris_reg_mode_jump_op:
3228 reg_mode_jump_op (inst, inst_env);
3231 case cris_reg_mode_move_from_preg_op:
3232 reg_mode_move_from_preg_op (inst, inst_env);
3235 case cris_reg_mode_test_op:
3236 reg_mode_test_op (inst, inst_env);
3240 scc_op (inst, inst_env);
3243 case cris_sixteen_bit_offset_branch_op:
3244 sixteen_bit_offset_branch_op (inst, inst_env);
3247 case cris_three_operand_add_sub_cmp_and_or_op:
3248 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3251 case cris_three_operand_bound_op:
3252 three_operand_bound_op (inst, inst_env);
3255 case cris_two_operand_bound_op:
3256 two_operand_bound_op (inst, inst_env);
3260 xor_op (inst, inst_env);
3265 /* This wrapper is to avoid cris_get_assembler being called before
3266 exec_bfd has been set. */
3269 cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info)
3271 int (*print_insn) (bfd_vma addr, struct disassemble_info *info);
3272 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3273 disassembler, even when there is no BFD. Does something like
3274 "gdb; target remote; disassmeble *0x123" work? */
3275 gdb_assert (exec_bfd != NULL);
3276 print_insn = cris_get_disassembler (exec_bfd);
3277 gdb_assert (print_insn != NULL);
3278 return print_insn (addr, info);
3281 /* Copied from <asm/elf.h>. */
3282 typedef unsigned long elf_greg_t;
3284 /* Same as user_regs_struct struct in <asm/user.h>. */
3285 typedef elf_greg_t elf_gregset_t[35];
3287 /* Unpack an elf_gregset_t into GDB's register cache. */
3290 supply_gregset (elf_gregset_t *gregsetp)
3293 elf_greg_t *regp = *gregsetp;
3294 static char zerobuf[4] = {0};
3296 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3297 knows about the actual size of each register so that's no problem. */
3298 for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++)
3300 regcache_raw_supply (current_regcache, i, (char *)®p[i]);
3304 /* Use a local version of this function to get the correct types for
3305 regsets, until multi-arch core support is ready. */
3308 fetch_core_registers (char *core_reg_sect, unsigned core_reg_size,
3309 int which, CORE_ADDR reg_addr)
3311 elf_gregset_t gregset;
3316 if (core_reg_size != sizeof (gregset))
3318 warning ("wrong size gregset struct in core file");
3322 memcpy (&gregset, core_reg_sect, sizeof (gregset));
3323 supply_gregset (&gregset);
3327 /* We've covered all the kinds of registers we know about here,
3328 so this must be something we wouldn't know what to do with
3329 anyway. Just ignore it. */
3334 static struct core_fns cris_elf_core_fns =
3336 bfd_target_elf_flavour, /* core_flavour */
3337 default_check_format, /* check_format */
3338 default_core_sniffer, /* core_sniffer */
3339 fetch_core_registers, /* core_read_registers */
3343 /* Fetch (and possibly build) an appropriate link_map_offsets
3344 structure for native GNU/Linux CRIS targets using the struct
3345 offsets defined in link.h (but without actual reference to that
3348 This makes it possible to access GNU/Linux CRIS shared libraries
3349 from a GDB that was not built on an GNU/Linux CRIS host (for cross
3352 See gdb/solib-svr4.h for an explanation of these fields. */
3354 static struct link_map_offsets *
3355 cris_linux_svr4_fetch_link_map_offsets (void)
3357 static struct link_map_offsets lmo;
3358 static struct link_map_offsets *lmp = NULL;
3364 lmo.r_debug_size = 8; /* The actual size is 20 bytes, but
3365 this is all we need. */
3366 lmo.r_map_offset = 4;
3369 lmo.link_map_size = 20;
3371 lmo.l_addr_offset = 0;
3372 lmo.l_addr_size = 4;
3374 lmo.l_name_offset = 4;
3375 lmo.l_name_size = 4;
3377 lmo.l_next_offset = 12;
3378 lmo.l_next_size = 4;
3380 lmo.l_prev_offset = 16;
3381 lmo.l_prev_size = 4;
3388 cris_fpless_backtrace (char *noargs, int from_tty)
3390 /* Points at the instruction after the jsr (except when in innermost frame
3391 where it points at the original pc). */
3394 /* Temporary variable, used for parsing from the start of the function that
3395 the pc is in, up to the pc. */
3396 CORE_ADDR tmp_pc = 0;
3399 /* Information about current frame. */
3400 struct symtab_and_line sal;
3403 /* Present instruction. */
3404 unsigned short insn;
3406 /* Next instruction, lookahead. */
3407 unsigned short insn_next;
3409 /* This is to store the offset between sp at start of function and until we
3410 reach push srp (if any). */
3411 int sp_add_later = 0;
3412 int push_srp_found = 0;
3416 /* Frame counter. */
3419 /* For the innermost frame, we want to look at srp in case it's a leaf
3420 function (since there's no push srp in that case). */
3421 int innermost_frame = 1;
3423 deprecated_read_register_gen (PC_REGNUM, (char *) &pc);
3424 deprecated_read_register_gen (SP_REGNUM, (char *) &sp);
3426 /* We make an explicit return when we can't find an outer frame. */
3429 /* Get file name and line number. */
3430 sal = find_pc_line (pc, 0);
3432 /* Get function name. */
3433 find_pc_partial_function (pc, &func_name, (CORE_ADDR *) NULL,
3434 (CORE_ADDR *) NULL);
3436 /* Print information about current frame. */
3437 printf_unfiltered ("#%i 0x%08lx in %s", frame++, pc, func_name);
3440 printf_unfiltered (" at %s:%i", sal.symtab->filename, sal.line);
3442 printf_unfiltered ("\n");
3444 /* Get the start address of this function. */
3445 tmp_pc = get_pc_function_start (pc);
3447 /* Mini parser, only meant to find push sp and sub ...,sp from the start
3448 of the function, up to the pc. */
3451 insn = read_memory_unsigned_integer (tmp_pc, sizeof (short));
3452 tmp_pc += sizeof (short);
3455 /* push <reg> 32 bit instruction */
3456 insn_next = read_memory_unsigned_integer (tmp_pc,
3458 tmp_pc += sizeof (short);
3460 /* Recognize srp. */
3461 if (insn_next == 0xBE7E)
3463 /* For subsequent (not this one though) push or sub which
3464 affects sp, adjust sp immediately. */
3467 /* Note: this will break if we ever encounter a
3468 push vr (1 byte) or push ccr (2 bytes). */
3473 /* Some other register was pushed. */
3484 else if (cris_get_operand2 (insn) == SP_REGNUM
3485 && cris_get_mode (insn) == 0x0000
3486 && cris_get_opcode (insn) == 0x000A)
3489 val = cris_get_quick_value (insn);
3497 sp_add_later += val;
3501 else if (cris_get_operand2 (insn) == SP_REGNUM
3502 /* Autoincrement addressing mode. */
3503 && cris_get_mode (insn) == 0x0003
3505 && ((insn) & 0x03E0) >> 5 == 0x0004)
3508 val = get_data_from_address (&insn, tmp_pc);
3516 sp_add_later += val;
3519 else if (cris_get_operand2 (insn) == SP_REGNUM
3520 && ((insn & 0x0F00) >> 8) == 0x0001
3521 && (cris_get_signed_offset (insn) < 0))
3523 /* Immediate byte offset addressing prefix word with sp as base
3524 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
3525 is between 64 and 128.
3526 movem r<regsave>,[sp=sp-<val>] */
3527 val = -cris_get_signed_offset (insn);
3528 insn_next = read_memory_unsigned_integer (tmp_pc,
3530 tmp_pc += sizeof (short);
3532 if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE
3533 && cris_get_opcode (insn_next) == 0x000F
3534 && cris_get_size (insn_next) == 0x0003
3535 && cris_get_operand1 (insn_next) == SP_REGNUM)
3543 sp_add_later += val;
3554 /* sp should now point at where srp is stored on the stack. Update
3555 the pc to the srp. */
3556 pc = read_memory_unsigned_integer (sp, 4);
3558 else if (innermost_frame)
3560 /* We couldn't find a push srp in the prologue, so this must be
3561 a leaf function, and thus we use the srp register directly.
3562 This should happen at most once, for the innermost function. */
3563 deprecated_read_register_gen (SRP_REGNUM, (char *) &pc);
3567 /* Couldn't find an outer frame. */
3571 /* Reset flag. (In case the innermost frame wasn't a leaf, we don't
3572 want to look at the srp register later either). */
3573 innermost_frame = 0;
3575 /* Now, add the offset for everything up to, and including push srp,
3576 that was held back during the prologue parsing. */
3582 extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */
3585 _initialize_cris_tdep (void)
3587 struct cmd_list_element *c;
3589 gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep);
3591 /* CRIS-specific user-commands. */
3592 c = add_set_cmd ("cris-version", class_support, var_integer,
3593 (char *) &usr_cmd_cris_version,
3594 "Set the current CRIS version.", &setlist);
3595 set_cmd_sfunc (c, cris_version_update);
3596 deprecated_add_show_from_set (c, &showlist);
3598 c = add_set_enum_cmd ("cris-mode", class_support, cris_mode_enums,
3600 "Set the current CRIS mode.", &setlist);
3601 set_cmd_sfunc (c, cris_mode_update);
3602 deprecated_add_show_from_set (c, &showlist);
3604 c = add_cmd ("cris-fpless-backtrace", class_support, cris_fpless_backtrace,
3605 "Display call chain using the subroutine return pointer.\n"
3606 "Note that this displays the address after the jump to the "
3607 "subroutine.", &cmdlist);
3609 deprecated_add_core_fns (&cris_elf_core_fns);
3613 /* Prints out all target specific values. */
3616 cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3618 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3621 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n",
3622 tdep->cris_version);
3623 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n",
3629 cris_version_update (char *ignore_args, int from_tty,
3630 struct cmd_list_element *c)
3632 struct gdbarch_info info;
3634 /* NOTE: cagney/2002-03-17: The deprecated_add_show_from_set()
3635 function clones the set command passed as a parameter. The clone
3636 operation will include (BUG?) any ``set'' command callback, if
3637 present. Commands like ``info set'' call all the ``show''
3638 command callbacks. Unfortunately, for ``show'' commands cloned
3639 from ``set'', this includes callbacks belonging to ``set''
3640 commands. Making this worse, this only occures if
3641 deprecated_add_show_from_set() is called after add_cmd_sfunc()
3644 /* From here on, trust the user's CRIS version setting. */
3645 if (cmd_type (c) == set_cmd)
3647 usr_cmd_cris_version_valid = 1;
3649 /* Update the current architecture, if needed. */
3650 gdbarch_info_init (&info);
3651 if (!gdbarch_update_p (info))
3652 internal_error (__FILE__, __LINE__, "cris_gdbarch_update: failed to update architecture.");
3657 cris_mode_update (char *ignore_args, int from_tty,
3658 struct cmd_list_element *c)
3660 struct gdbarch_info info;
3662 /* NOTE: cagney/2002-03-17: The deprecated_add_show_from_set()
3663 function clones the set command passed as a parameter. The clone
3664 operation will include (BUG?) any ``set'' command callback, if
3665 present. Commands like ``info set'' call all the ``show''
3666 command callbacks. Unfortunately, for ``show'' commands cloned
3667 from ``set'', this includes callbacks belonging to ``set''
3668 commands. Making this worse, this only occures if
3669 deprecated_add_show_from_set() is called after add_cmd_sfunc()
3672 /* From here on, trust the user's CRIS mode setting. */
3673 if (cmd_type (c) == set_cmd)
3675 usr_cmd_cris_mode_valid = 1;
3677 /* Update the current architecture, if needed. */
3678 gdbarch_info_init (&info);
3679 if (!gdbarch_update_p (info))
3680 internal_error (__FILE__, __LINE__, "cris_gdbarch_update: failed to update architecture.");
3684 static struct gdbarch *
3685 cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3687 struct gdbarch *gdbarch;
3688 struct gdbarch_tdep *tdep;
3690 const char *cris_mode;
3693 if (usr_cmd_cris_version_valid)
3695 /* Trust the user's CRIS version setting. */
3696 cris_version = usr_cmd_cris_version;
3700 /* Assume it's CRIS version 10. */
3704 if (usr_cmd_cris_mode_valid)
3706 /* Trust the user's CRIS mode setting. */
3707 cris_mode = usr_cmd_cris_mode;
3709 else if (cris_version == 10)
3711 /* Assume CRIS version 10 is in user mode. */
3712 cris_mode = CRIS_MODE_USER;
3716 /* Strictly speaking, older CRIS version don't have a supervisor mode,
3717 but we regard its only mode as supervisor mode. */
3718 cris_mode = CRIS_MODE_SUPERVISOR;
3721 /* Make the current settings visible to the user. */
3722 usr_cmd_cris_version = cris_version;
3723 usr_cmd_cris_mode = cris_mode;
3725 /* Find a candidate among the list of pre-declared architectures. Both
3726 CRIS version and ABI must match. */
3727 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3729 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3731 if ((gdbarch_tdep (arches->gdbarch)->cris_version == cris_version)
3732 && (gdbarch_tdep (arches->gdbarch)->cris_mode == cris_mode))
3733 return arches->gdbarch;
3736 /* No matching architecture was found. Create a new one. */
3737 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
3738 gdbarch = gdbarch_alloc (&info, tdep);
3740 tdep->cris_version = cris_version;
3741 tdep->cris_mode = cris_mode;
3743 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
3744 switch (info.byte_order)
3746 case BFD_ENDIAN_LITTLE:
3750 case BFD_ENDIAN_BIG:
3751 internal_error (__FILE__, __LINE__, "cris_gdbarch_init: big endian byte order in info");
3755 internal_error (__FILE__, __LINE__, "cris_gdbarch_init: unknown byte order in info");
3758 set_gdbarch_return_value (gdbarch, cris_return_value);
3759 set_gdbarch_deprecated_reg_struct_has_addr (gdbarch,
3760 cris_reg_struct_has_addr);
3761 set_gdbarch_deprecated_use_struct_convention (gdbarch, always_use_struct_convention);
3763 /* There are 32 registers (some of which may not be implemented). */
3764 set_gdbarch_num_regs (gdbarch, 32);
3765 set_gdbarch_sp_regnum (gdbarch, 14);
3766 set_gdbarch_pc_regnum (gdbarch, 15);
3767 set_gdbarch_register_name (gdbarch, cris_register_name);
3769 /* Length of ordinary registers used in push_word and a few other
3770 places. register_size() is the real way to know how big a
3772 set_gdbarch_deprecated_register_size (gdbarch, 4);
3773 set_gdbarch_double_bit (gdbarch, 64);
3774 /* The default definition of a long double is 2 * TARGET_DOUBLE_BIT,
3775 which means we have to set this explicitly. */
3776 set_gdbarch_long_double_bit (gdbarch, 64);
3777 set_gdbarch_register_bytes_ok (gdbarch, cris_register_bytes_ok);
3778 set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register);
3779 set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register);
3781 /* The total amount of space needed to store (in an array called registers)
3782 GDB's copy of the machine's register state. Note: We can not use
3783 cris_register_size at this point, since it relies on current_gdbarch
3785 switch (tdep->cris_version)
3791 /* Support for these may be added later. */
3792 internal_error (__FILE__, __LINE__, "cris_gdbarch_init: unsupported CRIS version");
3797 /* CRIS v8 and v9, a.k.a. ETRAX 100. General registers R0 - R15
3798 (32 bits), special registers P0 - P1 (8 bits), P4 - P5 (16 bits),
3799 and P8 - P14 (32 bits). */
3800 register_bytes = (16 * 4) + (2 * 1) + (2 * 2) + (7 * 4);
3805 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
3806 P7 (32 bits), and P15 (32 bits) have been implemented. */
3807 register_bytes = (16 * 4) + (2 * 1) + (2 * 2) + (9 * 4);
3811 internal_error (__FILE__, __LINE__, "cris_gdbarch_init: unknown CRIS version");
3814 /* Returns the register offset for the first byte of register regno's space
3815 in the saved register state. */
3816 set_gdbarch_deprecated_register_byte (gdbarch, cris_register_offset);
3818 set_gdbarch_register_type (gdbarch, cris_register_type);
3820 /* Dummy frame functions. */
3821 set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code);
3822 set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call);
3823 set_gdbarch_frame_align (gdbarch, cris_frame_align);
3825 set_gdbarch_software_single_step (gdbarch, cris_software_single_step);
3826 set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue);
3828 /* The stack grows downward. */
3829 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3831 set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc);
3833 set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc);
3834 set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp);
3835 set_gdbarch_unwind_dummy_id (gdbarch, cris_unwind_dummy_id);
3837 /* FIXME: Hook in the DWARF CFI frame unwinder.
3838 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
3840 frame_unwind_append_sniffer (gdbarch, cris_frame_sniffer);
3841 frame_base_set_default (gdbarch, &cris_frame_base);
3843 /* Use target_specific function to define link map offsets. */
3844 set_solib_svr4_fetch_link_map_offsets
3845 (gdbarch, cris_linux_svr4_fetch_link_map_offsets);
3847 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3848 disassembler, even when there is no BFD. Does something like
3849 "gdb; target remote; disassmeble *0x123" work? */
3850 set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler);