1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 Contributed by Axis Communications AB.
7 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
28 #include "frame-unwind.h"
29 #include "frame-base.h"
30 #include "trad-frame.h"
31 #include "dwarf2-frame.h"
39 #include "opcode/cris.h"
40 #include "arch-utils.h"
42 #include "gdb_assert.h"
44 /* To get entry_point_address. */
47 #include "solib.h" /* Support for shared libraries. */
48 #include "solib-svr4.h"
49 #include "gdb_string.h"
54 /* There are no floating point registers. Used in gdbserver low-linux.c. */
57 /* There are 16 general registers. */
60 /* There are 16 special registers. */
63 /* CRISv32 has a pseudo PC register, not noted here. */
65 /* CRISv32 has 16 support registers. */
69 /* Register numbers of various important registers.
70 CRIS_FP_REGNUM Contains address of executing stack frame.
71 STR_REGNUM Contains the address of structure return values.
72 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
73 ARG1_REGNUM Contains the first parameter to a function.
74 ARG2_REGNUM Contains the second parameter to a function.
75 ARG3_REGNUM Contains the third parameter to a function.
76 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
77 SP_REGNUM Contains address of top of stack.
78 PC_REGNUM Contains address of next instruction.
79 SRP_REGNUM Subroutine return pointer register.
80 BRP_REGNUM Breakpoint return pointer register. */
84 /* Enums with respect to the general registers, valid for all
85 CRIS versions. The frame pointer is always in R8. */
87 /* ABI related registers. */
95 /* Registers which happen to be common. */
100 /* CRISv10 et. al. specific registers. */
112 /* CRISv32 specific registers. */
125 CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */
127 CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */
147 extern const struct cris_spec_reg cris_spec_regs[];
149 /* CRIS version, set via the user command 'set cris-version'. Affects
150 register names and sizes. */
151 static int usr_cmd_cris_version;
153 /* Indicates whether to trust the above variable. */
154 static int usr_cmd_cris_version_valid = 0;
156 static const char cris_mode_normal[] = "normal";
157 static const char cris_mode_guru[] = "guru";
158 static const char *cris_modes[] = {
164 /* CRIS mode, set via the user command 'set cris-mode'. Affects
165 type of break instruction among other things. */
166 static const char *usr_cmd_cris_mode = cris_mode_normal;
168 /* Whether to make use of Dwarf-2 CFI (default on). */
169 static int usr_cmd_cris_dwarf2_cfi = 1;
171 /* CRIS architecture specific information. */
175 const char *cris_mode;
179 /* Functions for accessing target dependent data. */
184 return (gdbarch_tdep (current_gdbarch)->cris_version);
190 return (gdbarch_tdep (current_gdbarch)->cris_mode);
193 /* Sigtramp identification code copied from i386-linux-tdep.c. */
195 #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
196 #define SIGTRAMP_OFFSET0 0
197 #define SIGTRAMP_INSN1 0xe93d /* break 13 */
198 #define SIGTRAMP_OFFSET1 4
200 static const unsigned short sigtramp_code[] =
202 SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */
203 SIGTRAMP_INSN1 /* break 13 */
206 #define SIGTRAMP_LEN (sizeof sigtramp_code)
208 /* Note: same length as normal sigtramp code. */
210 static const unsigned short rt_sigtramp_code[] =
212 SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */
213 SIGTRAMP_INSN1 /* break 13 */
216 /* If PC is in a sigtramp routine, return the address of the start of
217 the routine. Otherwise, return 0. */
220 cris_sigtramp_start (struct frame_info *next_frame)
222 CORE_ADDR pc = frame_pc_unwind (next_frame);
223 gdb_byte buf[SIGTRAMP_LEN];
225 if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN))
228 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
230 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
233 pc -= SIGTRAMP_OFFSET1;
234 if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN))
238 if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0)
244 /* If PC is in a RT sigtramp routine, return the address of the start of
245 the routine. Otherwise, return 0. */
248 cris_rt_sigtramp_start (struct frame_info *next_frame)
250 CORE_ADDR pc = frame_pc_unwind (next_frame);
251 gdb_byte buf[SIGTRAMP_LEN];
253 if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN))
256 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
258 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
261 pc -= SIGTRAMP_OFFSET1;
262 if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN))
266 if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0)
272 /* Assuming NEXT_FRAME is a frame following a GNU/Linux sigtramp
273 routine, return the address of the associated sigcontext structure. */
276 cris_sigcontext_addr (struct frame_info *next_frame)
282 frame_unwind_register (next_frame, SP_REGNUM, buf);
283 sp = extract_unsigned_integer (buf, 4);
285 /* Look for normal sigtramp frame first. */
286 pc = cris_sigtramp_start (next_frame);
289 /* struct signal_frame (arch/cris/kernel/signal.c) contains
290 struct sigcontext as its first member, meaning the SP points to
295 pc = cris_rt_sigtramp_start (next_frame);
298 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
299 a struct ucontext, which in turn contains a struct sigcontext.
301 4 + 4 + 128 to struct ucontext, then
302 4 + 4 + 12 to struct sigcontext. */
306 error (_("Couldn't recognize signal trampoline."));
310 struct cris_unwind_cache
312 /* The previous frame's inner most stack address. Used as this
313 frame ID's stack_addr. */
315 /* The frame's base, optionally used by the high-level debug info. */
318 /* How far the SP and r8 (FP) have been offset from the start of
319 the stack frame (as defined by the previous frame's stack
325 /* From old frame_extra_info struct. */
329 /* Table indicating the location of each and every register. */
330 struct trad_frame_saved_reg *saved_regs;
333 static struct cris_unwind_cache *
334 cris_sigtramp_frame_unwind_cache (struct frame_info *next_frame,
337 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
338 struct cris_unwind_cache *info;
346 return (*this_cache);
348 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
349 (*this_cache) = info;
350 info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
352 /* Zero all fields. */
358 info->uses_frame = 0;
360 info->leaf_function = 0;
362 frame_unwind_register (next_frame, SP_REGNUM, buf);
363 info->base = extract_unsigned_integer (buf, 4);
365 addr = cris_sigcontext_addr (next_frame);
367 /* Layout of the sigcontext struct:
370 unsigned long oldmask;
374 if (tdep->cris_version == 10)
376 /* R0 to R13 are stored in reverse order at offset (2 * 4) in
378 for (i = 0; i <= 13; i++)
379 info->saved_regs[i].addr = addr + ((15 - i) * 4);
381 info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4);
382 info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4);
383 info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4);
384 /* Note: IRP is off by 2 at this point. There's no point in correcting
385 it though since that will mean that the backtrace will show a PC
386 different from what is shown when stopped. */
387 info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4);
388 info->saved_regs[PC_REGNUM] = info->saved_regs[IRP_REGNUM];
389 info->saved_regs[SP_REGNUM].addr = addr + (24 * 4);
394 /* R0 to R13 are stored in order at offset (1 * 4) in
396 for (i = 0; i <= 13; i++)
397 info->saved_regs[i].addr = addr + ((i + 1) * 4);
399 info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4);
400 info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4);
401 info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4);
402 info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4);
403 info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4);
404 info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4);
405 info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4);
406 info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4);
407 info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4);
409 /* FIXME: If ERP is in a delay slot at this point then the PC will
410 be wrong at this point. This problem manifests itself in the
411 sigaltstack.exp test case, which occasionally generates FAILs when
412 the signal is received while in a delay slot.
414 This could be solved by a couple of read_memory_unsigned_integer and a
415 trad_frame_set_value. */
416 info->saved_regs[PC_REGNUM] = info->saved_regs[ERP_REGNUM];
418 info->saved_regs[SP_REGNUM].addr = addr + (25 * 4);
425 cris_sigtramp_frame_this_id (struct frame_info *next_frame, void **this_cache,
426 struct frame_id *this_id)
428 struct cris_unwind_cache *cache =
429 cris_sigtramp_frame_unwind_cache (next_frame, this_cache);
430 (*this_id) = frame_id_build (cache->base, frame_pc_unwind (next_frame));
433 /* Forward declaration. */
435 static void cris_frame_prev_register (struct frame_info *next_frame,
436 void **this_prologue_cache,
437 int regnum, int *optimizedp,
438 enum lval_type *lvalp, CORE_ADDR *addrp,
439 int *realnump, gdb_byte *bufferp);
441 cris_sigtramp_frame_prev_register (struct frame_info *next_frame,
443 int regnum, int *optimizedp,
444 enum lval_type *lvalp, CORE_ADDR *addrp,
445 int *realnump, gdb_byte *valuep)
447 /* Make sure we've initialized the cache. */
448 cris_sigtramp_frame_unwind_cache (next_frame, this_cache);
449 cris_frame_prev_register (next_frame, this_cache, regnum,
450 optimizedp, lvalp, addrp, realnump, valuep);
453 static const struct frame_unwind cris_sigtramp_frame_unwind =
456 cris_sigtramp_frame_this_id,
457 cris_sigtramp_frame_prev_register
460 static const struct frame_unwind *
461 cris_sigtramp_frame_sniffer (struct frame_info *next_frame)
463 if (cris_sigtramp_start (next_frame)
464 || cris_rt_sigtramp_start (next_frame))
465 return &cris_sigtramp_frame_unwind;
471 crisv32_single_step_through_delay (struct gdbarch *gdbarch,
472 struct frame_info *this_frame)
474 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
479 if (cris_mode () == cris_mode_guru)
481 frame_unwind_register (this_frame, NRP_REGNUM, buf);
485 frame_unwind_register (this_frame, ERP_REGNUM, buf);
488 erp = extract_unsigned_integer (buf, 4);
492 /* In delay slot - check if there's a breakpoint at the preceding
494 if (breakpoint_here_p (erp & ~0x1))
500 /* Hardware watchpoint support. */
502 /* We support 6 hardware data watchpoints, but cannot trigger on execute
503 (any combination of read/write is fine). */
506 cris_can_use_hardware_watchpoint (int type, int count, int other)
508 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
510 /* No bookkeeping is done here; it is handled by the remote debug agent. */
512 if (tdep->cris_version != 32)
515 /* CRISv32: Six data watchpoints, one for instructions. */
516 return (((type == bp_read_watchpoint || type == bp_access_watchpoint
517 || type == bp_hardware_watchpoint) && count <= 6)
518 || (type == bp_hardware_breakpoint && count <= 1));
521 /* The CRISv32 hardware data watchpoints work by specifying ranges,
522 which have no alignment or length restrictions. */
525 cris_region_ok_for_watchpoint (CORE_ADDR addr, int len)
530 /* If the inferior has some watchpoint that triggered, return the
531 address associated with that watchpoint. Otherwise, return
535 cris_stopped_data_address (void)
538 eda = read_register (EDA_REGNUM);
542 /* The instruction environment needed to find single-step breakpoints. */
545 struct instruction_environment
547 unsigned long reg[NUM_GENREGS];
548 unsigned long preg[NUM_SPECREGS];
549 unsigned long branch_break_address;
550 unsigned long delay_slot_pc;
551 unsigned long prefix_value;
556 int delay_slot_pc_active;
558 int disable_interrupt;
561 /* Save old breakpoints in order to restore the state before a single_step.
562 At most, two breakpoints will have to be remembered. */
564 char binsn_quantum[BREAKPOINT_MAX];
565 static binsn_quantum break_mem[2];
566 static CORE_ADDR next_pc = 0;
567 static CORE_ADDR branch_target_address = 0;
568 static unsigned char branch_break_inserted = 0;
570 /* Machine-dependencies in CRIS for opcodes. */
572 /* Instruction sizes. */
573 enum cris_instruction_sizes
580 /* Addressing modes. */
581 enum cris_addressing_modes
588 /* Prefix addressing modes. */
589 enum cris_prefix_addressing_modes
591 PREFIX_INDEX_MODE = 2,
592 PREFIX_ASSIGN_MODE = 3,
594 /* Handle immediate byte offset addressing mode prefix format. */
595 PREFIX_OFFSET_MODE = 2
598 /* Masks for opcodes. */
599 enum cris_opcode_masks
601 BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1,
602 SIGNED_EXTEND_BIT_MASK = 0x2,
603 SIGNED_BYTE_MASK = 0x80,
604 SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00,
605 SIGNED_WORD_MASK = 0x8000,
606 SIGNED_WORD_EXTEND_MASK = 0xFFFF0000,
607 SIGNED_DWORD_MASK = 0x80000000,
608 SIGNED_QUICK_VALUE_MASK = 0x20,
609 SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0
612 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
620 cris_get_operand2 (unsigned short insn)
622 return ((insn & 0xF000) >> 12);
626 cris_get_mode (unsigned short insn)
628 return ((insn & 0x0C00) >> 10);
632 cris_get_opcode (unsigned short insn)
634 return ((insn & 0x03C0) >> 6);
638 cris_get_size (unsigned short insn)
640 return ((insn & 0x0030) >> 4);
644 cris_get_operand1 (unsigned short insn)
646 return (insn & 0x000F);
649 /* Additional functions in order to handle opcodes. */
652 cris_get_quick_value (unsigned short insn)
654 return (insn & 0x003F);
658 cris_get_bdap_quick_offset (unsigned short insn)
660 return (insn & 0x00FF);
664 cris_get_branch_short_offset (unsigned short insn)
666 return (insn & 0x00FF);
670 cris_get_asr_shift_steps (unsigned long value)
672 return (value & 0x3F);
676 cris_get_clear_size (unsigned short insn)
678 return ((insn) & 0xC000);
682 cris_is_signed_extend_bit_on (unsigned short insn)
684 return (((insn) & 0x20) == 0x20);
688 cris_is_xflag_bit_on (unsigned short insn)
690 return (((insn) & 0x1000) == 0x1000);
694 cris_set_size_to_dword (unsigned short *insn)
701 cris_get_signed_offset (unsigned short insn)
703 return ((signed char) (insn & 0x00FF));
706 /* Calls an op function given the op-type, working on the insn and the
708 static void cris_gdb_func (enum cris_op_type, unsigned short, inst_env_type *);
710 static struct gdbarch *cris_gdbarch_init (struct gdbarch_info,
711 struct gdbarch_list *);
713 static void cris_dump_tdep (struct gdbarch *, struct ui_file *);
715 static void set_cris_version (char *ignore_args, int from_tty,
716 struct cmd_list_element *c);
718 static void set_cris_mode (char *ignore_args, int from_tty,
719 struct cmd_list_element *c);
721 static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
722 struct cmd_list_element *c);
724 static CORE_ADDR cris_scan_prologue (CORE_ADDR pc,
725 struct frame_info *next_frame,
726 struct cris_unwind_cache *info);
728 static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc,
729 struct frame_info *next_frame,
730 struct cris_unwind_cache *info);
732 static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch,
733 struct frame_info *next_frame);
735 static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch,
736 struct frame_info *next_frame);
738 /* When arguments must be pushed onto the stack, they go on in reverse
739 order. The below implements a FILO (stack) to do this.
740 Copied from d10v-tdep.c. */
745 struct stack_item *prev;
749 static struct stack_item *
750 push_stack_item (struct stack_item *prev, void *contents, int len)
752 struct stack_item *si;
753 si = xmalloc (sizeof (struct stack_item));
754 si->data = xmalloc (len);
757 memcpy (si->data, contents, len);
761 static struct stack_item *
762 pop_stack_item (struct stack_item *si)
764 struct stack_item *dead = si;
771 /* Put here the code to store, into fi->saved_regs, the addresses of
772 the saved registers of frame described by FRAME_INFO. This
773 includes special registers such as pc and fp saved in special ways
774 in the stack frame. sp is even more special: the address we return
775 for it IS the sp for the next frame. */
777 struct cris_unwind_cache *
778 cris_frame_unwind_cache (struct frame_info *next_frame,
779 void **this_prologue_cache)
782 struct cris_unwind_cache *info;
785 if ((*this_prologue_cache))
786 return (*this_prologue_cache);
788 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
789 (*this_prologue_cache) = info;
790 info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
792 /* Zero all fields. */
798 info->uses_frame = 0;
800 info->leaf_function = 0;
802 /* Prologue analysis does the rest... */
803 if (cris_version () == 32)
804 crisv32_scan_prologue (frame_func_unwind (next_frame), next_frame, info);
806 cris_scan_prologue (frame_func_unwind (next_frame), next_frame, info);
811 /* Given a GDB frame, determine the address of the calling function's
812 frame. This will be used to create a new GDB frame struct. */
815 cris_frame_this_id (struct frame_info *next_frame,
816 void **this_prologue_cache,
817 struct frame_id *this_id)
819 struct cris_unwind_cache *info
820 = cris_frame_unwind_cache (next_frame, this_prologue_cache);
825 /* The FUNC is easy. */
826 func = frame_func_unwind (next_frame);
828 /* Hopefully the prologue analysis either correctly determined the
829 frame's base (which is the SP from the previous frame), or set
830 that base to "NULL". */
831 base = info->prev_sp;
835 id = frame_id_build (base, func);
841 cris_frame_prev_register (struct frame_info *next_frame,
842 void **this_prologue_cache,
843 int regnum, int *optimizedp,
844 enum lval_type *lvalp, CORE_ADDR *addrp,
845 int *realnump, gdb_byte *bufferp)
847 struct cris_unwind_cache *info
848 = cris_frame_unwind_cache (next_frame, this_prologue_cache);
849 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
850 optimizedp, lvalp, addrp, realnump, bufferp);
853 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
854 dummy frame. The frame ID's base needs to match the TOS value
855 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
858 static struct frame_id
859 cris_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
861 return frame_id_build (cris_unwind_sp (gdbarch, next_frame),
862 frame_pc_unwind (next_frame));
866 cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
868 /* Align to the size of an instruction (so that they can safely be
869 pushed onto the stack). */
874 cris_push_dummy_code (struct gdbarch *gdbarch,
875 CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc,
876 struct value **args, int nargs,
877 struct type *value_type,
878 CORE_ADDR *real_pc, CORE_ADDR *bp_addr)
880 /* Allocate space sufficient for a breakpoint. */
882 /* Store the address of that breakpoint */
884 /* CRIS always starts the call at the callee's entry point. */
890 cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
891 struct regcache *regcache, CORE_ADDR bp_addr,
892 int nargs, struct value **args, CORE_ADDR sp,
893 int struct_return, CORE_ADDR struct_addr)
902 /* The function's arguments and memory allocated by gdb for the arguments to
903 point at reside in separate areas on the stack.
904 Both frame pointers grow toward higher addresses. */
908 struct stack_item *si = NULL;
910 /* Push the return address. */
911 regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr);
913 /* Are we returning a value using a structure return or a normal value
914 return? struct_addr is the address of the reserved space for the return
915 structure to be written on the stack. */
918 regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr);
921 /* Now load as many as possible of the first arguments into registers,
922 and push the rest onto the stack. */
923 argreg = ARG1_REGNUM;
926 for (argnum = 0; argnum < nargs; argnum++)
933 len = TYPE_LENGTH (value_type (args[argnum]));
934 val = (char *) value_contents (args[argnum]);
936 /* How may registers worth of storage do we need for this argument? */
937 reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0);
939 if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM))
941 /* Data passed by value. Fits in available register(s). */
942 for (i = 0; i < reg_demand; i++)
944 regcache_cooked_write_unsigned (regcache, argreg,
945 *(unsigned long *) val);
950 else if (len <= (2 * 4) && argreg <= ARG4_REGNUM)
952 /* Data passed by value. Does not fit in available register(s).
953 Use the register(s) first, then the stack. */
954 for (i = 0; i < reg_demand; i++)
956 if (argreg <= ARG4_REGNUM)
958 regcache_cooked_write_unsigned (regcache, argreg,
959 *(unsigned long *) val);
965 /* Push item for later so that pushed arguments
966 come in the right order. */
967 si = push_stack_item (si, val, 4);
972 else if (len > (2 * 4))
975 internal_error (__FILE__, __LINE__, _("We don't do this"));
979 /* Data passed by value. No available registers. Put it on
981 si = push_stack_item (si, val, len);
987 /* fp_arg must be word-aligned (i.e., don't += len) to match
988 the function prologue. */
989 sp = (sp - si->len) & ~3;
990 write_memory (sp, si->data, si->len);
991 si = pop_stack_item (si);
994 /* Finally, update the SP register. */
995 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1000 static const struct frame_unwind cris_frame_unwind =
1004 cris_frame_prev_register
1007 const struct frame_unwind *
1008 cris_frame_sniffer (struct frame_info *next_frame)
1010 return &cris_frame_unwind;
1014 cris_frame_base_address (struct frame_info *next_frame, void **this_cache)
1016 struct cris_unwind_cache *info
1017 = cris_frame_unwind_cache (next_frame, this_cache);
1021 static const struct frame_base cris_frame_base =
1024 cris_frame_base_address,
1025 cris_frame_base_address,
1026 cris_frame_base_address
1029 /* Frames information. The definition of the struct frame_info is
1033 enum frame_type type;
1037 If the compilation option -fno-omit-frame-pointer is present the
1038 variable frame will be set to the content of R8 which is the frame
1041 The variable pc contains the address where execution is performed
1042 in the present frame. The innermost frame contains the current content
1043 of the register PC. All other frames contain the content of the
1044 register PC in the next frame.
1046 The variable `type' indicates the frame's type: normal, SIGTRAMP
1047 (associated with a signal handler), dummy (associated with a dummy
1050 The variable return_pc contains the address where execution should be
1051 resumed when the present frame has finished, the return address.
1053 The variable leaf_function is 1 if the return address is in the register
1054 SRP, and 0 if it is on the stack.
1056 Prologue instructions C-code.
1057 The prologue may consist of (-fno-omit-frame-pointer)
1061 move.d sp,r8 move.d sp,r8
1063 movem rY,[sp] movem rY,[sp]
1064 move.S rZ,[r8-U] move.S rZ,[r8-U]
1066 where 1 is a non-terminal function, and 2 is a leaf-function.
1068 Note that this assumption is extremely brittle, and will break at the
1069 slightest change in GCC's prologue.
1071 If local variables are declared or register contents are saved on stack
1072 the subq-instruction will be present with X as the number of bytes
1073 needed for storage. The reshuffle with respect to r8 may be performed
1074 with any size S (b, w, d) and any of the general registers Z={0..13}.
1075 The offset U should be representable by a signed 8-bit value in all cases.
1076 Thus, the prefix word is assumed to be immediate byte offset mode followed
1077 by another word containing the instruction.
1086 Prologue instructions C++-code.
1087 Case 1) and 2) in the C-code may be followed by
1089 move.d r10,rS ; this
1093 move.S [r8+U],rZ ; P4
1095 if any of the call parameters are stored. The host expects these
1096 instructions to be executed in order to get the call parameters right. */
1098 /* Examine the prologue of a function. The variable ip is the address of
1099 the first instruction of the prologue. The variable limit is the address
1100 of the first instruction after the prologue. The variable fi contains the
1101 information in struct frame_info. The variable frameless_p controls whether
1102 the entire prologue is examined (0) or just enough instructions to
1103 determine that it is a prologue (1). */
1106 cris_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame,
1107 struct cris_unwind_cache *info)
1109 /* Present instruction. */
1110 unsigned short insn;
1112 /* Next instruction, lookahead. */
1113 unsigned short insn_next;
1116 /* Is there a push fp? */
1119 /* Number of byte on stack used for local variables and movem. */
1122 /* Highest register number in a movem. */
1125 /* move.d r<source_register>,rS */
1126 short source_register;
1131 /* This frame is with respect to a leaf until a push srp is found. */
1134 info->leaf_function = 1;
1137 /* Assume nothing on stack. */
1141 /* If we were called without a next_frame, that means we were called
1142 from cris_skip_prologue which already tried to find the end of the
1143 prologue through the symbol information. 64 instructions past current
1144 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
1145 limit = next_frame ? frame_pc_unwind (next_frame) : pc + 64;
1147 /* Find the prologue instructions. */
1148 while (pc > 0 && pc < limit)
1150 insn = read_memory_unsigned_integer (pc, 2);
1154 /* push <reg> 32 bit instruction */
1155 insn_next = read_memory_unsigned_integer (pc, 2);
1157 regno = cris_get_operand2 (insn_next);
1160 info->sp_offset += 4;
1162 /* This check, meant to recognize srp, used to be regno ==
1163 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
1164 if (insn_next == 0xBE7E)
1168 info->leaf_function = 0;
1171 else if (insn_next == 0x8FEE)
1176 info->r8_offset = info->sp_offset;
1180 else if (insn == 0x866E)
1185 info->uses_frame = 1;
1189 else if (cris_get_operand2 (insn) == SP_REGNUM
1190 && cris_get_mode (insn) == 0x0000
1191 && cris_get_opcode (insn) == 0x000A)
1196 info->sp_offset += cris_get_quick_value (insn);
1199 else if (cris_get_mode (insn) == 0x0002
1200 && cris_get_opcode (insn) == 0x000F
1201 && cris_get_size (insn) == 0x0003
1202 && cris_get_operand1 (insn) == SP_REGNUM)
1204 /* movem r<regsave>,[sp] */
1205 regsave = cris_get_operand2 (insn);
1207 else if (cris_get_operand2 (insn) == SP_REGNUM
1208 && ((insn & 0x0F00) >> 8) == 0x0001
1209 && (cris_get_signed_offset (insn) < 0))
1211 /* Immediate byte offset addressing prefix word with sp as base
1212 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1213 is between 64 and 128.
1214 movem r<regsave>,[sp=sp-<val>] */
1217 info->sp_offset += -cris_get_signed_offset (insn);
1219 insn_next = read_memory_unsigned_integer (pc, 2);
1221 if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE
1222 && cris_get_opcode (insn_next) == 0x000F
1223 && cris_get_size (insn_next) == 0x0003
1224 && cris_get_operand1 (insn_next) == SP_REGNUM)
1226 regsave = cris_get_operand2 (insn_next);
1230 /* The prologue ended before the limit was reached. */
1235 else if (cris_get_mode (insn) == 0x0001
1236 && cris_get_opcode (insn) == 0x0009
1237 && cris_get_size (insn) == 0x0002)
1239 /* move.d r<10..13>,r<0..15> */
1240 source_register = cris_get_operand1 (insn);
1242 /* FIXME? In the glibc solibs, the prologue might contain something
1243 like (this example taken from relocate_doit):
1245 sub.d 0xfffef426,$r0
1246 which isn't covered by the source_register check below. Question
1247 is whether to add a check for this combo, or make better use of
1248 the limit variable instead. */
1249 if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM)
1251 /* The prologue ended before the limit was reached. */
1256 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1257 /* The size is a fixed-size. */
1258 && ((insn & 0x0F00) >> 8) == 0x0001
1259 /* A negative offset. */
1260 && (cris_get_signed_offset (insn) < 0))
1262 /* move.S rZ,[r8-U] (?) */
1263 insn_next = read_memory_unsigned_integer (pc, 2);
1265 regno = cris_get_operand2 (insn_next);
1266 if ((regno >= 0 && regno < SP_REGNUM)
1267 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1268 && cris_get_opcode (insn_next) == 0x000F)
1270 /* move.S rZ,[r8-U] */
1275 /* The prologue ended before the limit was reached. */
1280 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1281 /* The size is a fixed-size. */
1282 && ((insn & 0x0F00) >> 8) == 0x0001
1283 /* A positive offset. */
1284 && (cris_get_signed_offset (insn) > 0))
1286 /* move.S [r8+U],rZ (?) */
1287 insn_next = read_memory_unsigned_integer (pc, 2);
1289 regno = cris_get_operand2 (insn_next);
1290 if ((regno >= 0 && regno < SP_REGNUM)
1291 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1292 && cris_get_opcode (insn_next) == 0x0009
1293 && cris_get_operand1 (insn_next) == regno)
1295 /* move.S [r8+U],rZ */
1300 /* The prologue ended before the limit was reached. */
1307 /* The prologue ended before the limit was reached. */
1313 /* We only want to know the end of the prologue when next_frame and info
1314 are NULL (called from cris_skip_prologue i.e.). */
1315 if (next_frame == NULL && info == NULL)
1320 info->size = info->sp_offset;
1322 /* Compute the previous frame's stack pointer (which is also the
1323 frame's ID's stack address), and this frame's base pointer. */
1324 if (info->uses_frame)
1327 /* The SP was moved to the FP. This indicates that a new frame
1328 was created. Get THIS frame's FP value by unwinding it from
1330 frame_unwind_unsigned_register (next_frame, CRIS_FP_REGNUM,
1332 info->base = this_base;
1333 info->saved_regs[CRIS_FP_REGNUM].addr = info->base;
1335 /* The FP points at the last saved register. Adjust the FP back
1336 to before the first saved register giving the SP. */
1337 info->prev_sp = info->base + info->r8_offset;
1342 /* Assume that the FP is this frame's SP but with that pushed
1343 stack space added back. */
1344 frame_unwind_unsigned_register (next_frame, SP_REGNUM, &this_base);
1345 info->base = this_base;
1346 info->prev_sp = info->base + info->size;
1349 /* Calculate the addresses for the saved registers on the stack. */
1350 /* FIXME: The address calculation should really be done on the fly while
1351 we're analyzing the prologue (we only hold one regsave value as it is
1353 val = info->sp_offset;
1355 for (regno = regsave; regno >= 0; regno--)
1357 info->saved_regs[regno].addr = info->base + info->r8_offset - val;
1361 /* The previous frame's SP needed to be computed. Save the computed
1363 trad_frame_set_value (info->saved_regs, SP_REGNUM, info->prev_sp);
1365 if (!info->leaf_function)
1367 /* SRP saved on the stack. But where? */
1368 if (info->r8_offset == 0)
1370 /* R8 not pushed yet. */
1371 info->saved_regs[SRP_REGNUM].addr = info->base;
1375 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1376 info->saved_regs[SRP_REGNUM].addr = info->base + 4;
1380 /* The PC is found in SRP (the actual register or located on the stack). */
1381 info->saved_regs[PC_REGNUM] = info->saved_regs[SRP_REGNUM];
1387 crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame,
1388 struct cris_unwind_cache *info)
1392 /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not
1393 meant to be a full-fledged prologue scanner. It is only needed for
1394 the cases where we end up in code always lacking DWARF-2 CFI, notably:
1396 * PLT stubs (library calls)
1398 * signal trampolines
1400 For those cases, it is assumed that there is no actual prologue; that
1401 the stack pointer is not adjusted, and (as a consequence) the return
1402 address is not pushed onto the stack. */
1404 /* We only want to know the end of the prologue when next_frame and info
1405 are NULL (called from cris_skip_prologue i.e.). */
1406 if (next_frame == NULL && info == NULL)
1411 /* The SP is assumed to be unaltered. */
1412 frame_unwind_unsigned_register (next_frame, SP_REGNUM, &this_base);
1413 info->base = this_base;
1414 info->prev_sp = this_base;
1416 /* The PC is assumed to be found in SRP. */
1417 info->saved_regs[PC_REGNUM] = info->saved_regs[SRP_REGNUM];
1422 /* Advance pc beyond any function entry prologue instructions at pc
1423 to reach some "real" code. */
1425 /* Given a PC value corresponding to the start of a function, return the PC
1426 of the first instruction after the function prologue. */
1429 cris_skip_prologue (CORE_ADDR pc)
1431 CORE_ADDR func_addr, func_end;
1432 struct symtab_and_line sal;
1433 CORE_ADDR pc_after_prologue;
1435 /* If we have line debugging information, then the end of the prologue
1436 should the first assembly instruction of the first source line. */
1437 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1439 sal = find_pc_line (func_addr, 0);
1440 if (sal.end > 0 && sal.end < func_end)
1444 if (cris_version () == 32)
1445 pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL);
1447 pc_after_prologue = cris_scan_prologue (pc, NULL, NULL);
1449 return pc_after_prologue;
1453 cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1456 frame_unwind_unsigned_register (next_frame, PC_REGNUM, &pc);
1461 cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1464 frame_unwind_unsigned_register (next_frame, SP_REGNUM, &sp);
1468 /* Use the program counter to determine the contents and size of a breakpoint
1469 instruction. It returns a pointer to a string of bytes that encode a
1470 breakpoint instruction, stores the length of the string to *lenptr, and
1471 adjusts pcptr (if necessary) to point to the actual memory location where
1472 the breakpoint should be inserted. */
1474 static const unsigned char *
1475 cris_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
1477 static unsigned char break8_insn[] = {0x38, 0xe9};
1478 static unsigned char break15_insn[] = {0x3f, 0xe9};
1481 if (cris_mode () == cris_mode_guru)
1482 return break15_insn;
1487 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1491 cris_spec_reg_applicable (struct cris_spec_reg spec_reg)
1493 int version = cris_version ();
1495 switch (spec_reg.applicable_version)
1497 case cris_ver_version_all:
1499 case cris_ver_warning:
1500 /* Indeterminate/obsolete. */
1503 return (version >= 0 && version <= 3);
1505 return (version >= 3);
1507 return (version == 8 || version == 9);
1509 return (version >= 8);
1510 case cris_ver_v0_10:
1511 return (version >= 0 && version <= 10);
1512 case cris_ver_v3_10:
1513 return (version >= 3 && version <= 10);
1514 case cris_ver_v8_10:
1515 return (version >= 8 && version <= 10);
1517 return (version == 10);
1519 return (version >= 10);
1521 return (version >= 32);
1523 /* Invalid cris version. */
1528 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1529 register, -1 for an invalid register. */
1532 cris_register_size (int regno)
1534 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1538 if (regno >= 0 && regno < NUM_GENREGS)
1540 /* General registers (R0 - R15) are 32 bits. */
1543 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1545 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1546 Adjust regno accordingly. */
1547 spec_regno = regno - NUM_GENREGS;
1549 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1551 if (cris_spec_regs[i].number == spec_regno
1552 && cris_spec_reg_applicable (cris_spec_regs[i]))
1553 /* Go with the first applicable register. */
1554 return cris_spec_regs[i].reg_size;
1556 /* Special register not applicable to this CRIS version. */
1559 else if (regno >= PC_REGNUM && regno < NUM_REGS)
1561 /* This will apply to CRISv32 only where there are additional registers
1562 after the special registers (pseudo PC and support registers). */
1570 /* Nonzero if regno should not be fetched from the target. This is the case
1571 for unimplemented (size 0) and non-existant registers. */
1574 cris_cannot_fetch_register (int regno)
1576 return ((regno < 0 || regno >= NUM_REGS)
1577 || (cris_register_size (regno) == 0));
1580 /* Nonzero if regno should not be written to the target, for various
1584 cris_cannot_store_register (int regno)
1586 /* There are three kinds of registers we refuse to write to.
1587 1. Those that not implemented.
1588 2. Those that are read-only (depends on the processor mode).
1589 3. Those registers to which a write has no effect.
1592 if (regno < 0 || regno >= NUM_REGS || cris_register_size (regno) == 0)
1593 /* Not implemented. */
1596 else if (regno == VR_REGNUM)
1600 else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM)
1601 /* Writing has no effect. */
1604 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
1605 agent decide whether they are writable. */
1610 /* Nonzero if regno should not be fetched from the target. This is the case
1611 for unimplemented (size 0) and non-existant registers. */
1614 crisv32_cannot_fetch_register (int regno)
1616 return ((regno < 0 || regno >= NUM_REGS)
1617 || (cris_register_size (regno) == 0));
1620 /* Nonzero if regno should not be written to the target, for various
1624 crisv32_cannot_store_register (int regno)
1626 /* There are three kinds of registers we refuse to write to.
1627 1. Those that not implemented.
1628 2. Those that are read-only (depends on the processor mode).
1629 3. Those registers to which a write has no effect.
1632 if (regno < 0 || regno >= NUM_REGS || cris_register_size (regno) == 0)
1633 /* Not implemented. */
1636 else if (regno == VR_REGNUM)
1640 else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM)
1641 /* Writing has no effect. */
1644 /* Many special registers are read-only in user mode. Let the debug
1645 agent decide whether they are writable. */
1650 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1651 of data in register regno. */
1653 static struct type *
1654 cris_register_type (struct gdbarch *gdbarch, int regno)
1656 if (regno == PC_REGNUM)
1657 return builtin_type_void_func_ptr;
1658 else if (regno == SP_REGNUM || regno == CRIS_FP_REGNUM)
1659 return builtin_type_void_data_ptr;
1660 else if ((regno >= 0 && regno < SP_REGNUM)
1661 || (regno >= MOF_REGNUM && regno <= USP_REGNUM))
1662 /* Note: R8 taken care of previous clause. */
1663 return builtin_type_uint32;
1664 else if (regno >= P4_REGNUM && regno <= CCR_REGNUM)
1665 return builtin_type_uint16;
1666 else if (regno >= P0_REGNUM && regno <= VR_REGNUM)
1667 return builtin_type_uint8;
1669 /* Invalid (unimplemented) register. */
1670 return builtin_type_int0;
1673 static struct type *
1674 crisv32_register_type (struct gdbarch *gdbarch, int regno)
1676 if (regno == PC_REGNUM)
1677 return builtin_type_void_func_ptr;
1678 else if (regno == SP_REGNUM || regno == CRIS_FP_REGNUM)
1679 return builtin_type_void_data_ptr;
1680 else if ((regno >= 0 && regno <= ACR_REGNUM)
1681 || (regno >= EXS_REGNUM && regno <= SPC_REGNUM)
1682 || (regno == PID_REGNUM)
1683 || (regno >= S0_REGNUM && regno <= S15_REGNUM))
1684 /* Note: R8 and SP taken care of by previous clause. */
1685 return builtin_type_uint32;
1686 else if (regno == WZ_REGNUM)
1687 return builtin_type_uint16;
1688 else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM)
1689 return builtin_type_uint8;
1692 /* Invalid (unimplemented) register. Should not happen as there are
1693 no unimplemented CRISv32 registers. */
1694 warning (_("crisv32_register_type: unknown regno %d"), regno);
1695 return builtin_type_int0;
1699 /* Stores a function return value of type type, where valbuf is the address
1700 of the value to be stored. */
1702 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1705 cris_store_return_value (struct type *type, struct regcache *regcache,
1709 int len = TYPE_LENGTH (type);
1713 /* Put the return value in R10. */
1714 val = extract_unsigned_integer (valbuf, len);
1715 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1719 /* Put the return value in R10 and R11. */
1720 val = extract_unsigned_integer (valbuf, 4);
1721 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1722 val = extract_unsigned_integer ((char *)valbuf + 4, len - 4);
1723 regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val);
1726 error (_("cris_store_return_value: type length too large."));
1729 /* Return the name of register regno as a string. Return NULL for an invalid or
1730 unimplemented register. */
1733 cris_special_register_name (int regno)
1738 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1739 Adjust regno accordingly. */
1740 spec_regno = regno - NUM_GENREGS;
1742 /* Assume nothing about the layout of the cris_spec_regs struct
1744 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1746 if (cris_spec_regs[i].number == spec_regno
1747 && cris_spec_reg_applicable (cris_spec_regs[i]))
1748 /* Go with the first applicable register. */
1749 return cris_spec_regs[i].name;
1751 /* Special register not applicable to this CRIS version. */
1756 cris_register_name (int regno)
1758 static char *cris_genreg_names[] =
1759 { "r0", "r1", "r2", "r3", \
1760 "r4", "r5", "r6", "r7", \
1761 "r8", "r9", "r10", "r11", \
1762 "r12", "r13", "sp", "pc" };
1764 if (regno >= 0 && regno < NUM_GENREGS)
1766 /* General register. */
1767 return cris_genreg_names[regno];
1769 else if (regno >= NUM_GENREGS && regno < NUM_REGS)
1771 return cris_special_register_name (regno);
1775 /* Invalid register. */
1781 crisv32_register_name (int regno)
1783 static char *crisv32_genreg_names[] =
1784 { "r0", "r1", "r2", "r3", \
1785 "r4", "r5", "r6", "r7", \
1786 "r8", "r9", "r10", "r11", \
1787 "r12", "r13", "sp", "acr"
1790 static char *crisv32_sreg_names[] =
1791 { "s0", "s1", "s2", "s3", \
1792 "s4", "s5", "s6", "s7", \
1793 "s8", "s9", "s10", "s11", \
1794 "s12", "s13", "s14", "s15"
1797 if (regno >= 0 && regno < NUM_GENREGS)
1799 /* General register. */
1800 return crisv32_genreg_names[regno];
1802 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1804 return cris_special_register_name (regno);
1806 else if (regno == PC_REGNUM)
1810 else if (regno >= S0_REGNUM && regno <= S15_REGNUM)
1812 return crisv32_sreg_names[regno - S0_REGNUM];
1816 /* Invalid register. */
1821 /* Convert DWARF register number REG to the appropriate register
1822 number used by GDB. */
1825 cris_dwarf2_reg_to_regnum (int reg)
1827 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1828 numbering, MOF is 18).
1829 Adapted from gcc/config/cris/cris.h. */
1830 static int cris_dwarf_regmap[] = {
1842 if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap))
1843 regnum = cris_dwarf_regmap[reg];
1846 warning (_("Unmapped DWARF Register #%d encountered."), reg);
1851 /* DWARF-2 frame support. */
1854 cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1855 struct dwarf2_frame_state_reg *reg,
1856 struct frame_info *next_frame)
1858 /* The return address column. */
1859 if (regnum == PC_REGNUM)
1860 reg->how = DWARF2_FRAME_REG_RA;
1862 /* The call frame address. */
1863 else if (regnum == SP_REGNUM)
1864 reg->how = DWARF2_FRAME_REG_CFA;
1867 /* Extract from an array regbuf containing the raw register state a function
1868 return value of type type, and copy that, in virtual format, into
1871 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1874 cris_extract_return_value (struct type *type, struct regcache *regcache,
1878 int len = TYPE_LENGTH (type);
1882 /* Get the return value from R10. */
1883 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1884 store_unsigned_integer (valbuf, len, val);
1888 /* Get the return value from R10 and R11. */
1889 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1890 store_unsigned_integer (valbuf, 4, val);
1891 regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val);
1892 store_unsigned_integer ((char *)valbuf + 4, len - 4, val);
1895 error (_("cris_extract_return_value: type length too large"));
1898 /* Handle the CRIS return value convention. */
1900 static enum return_value_convention
1901 cris_return_value (struct gdbarch *gdbarch, struct type *type,
1902 struct regcache *regcache, gdb_byte *readbuf,
1903 const gdb_byte *writebuf)
1905 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1906 || TYPE_CODE (type) == TYPE_CODE_UNION
1907 || TYPE_LENGTH (type) > 8)
1908 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1909 goes on the stack. */
1910 return RETURN_VALUE_STRUCT_CONVENTION;
1913 cris_extract_return_value (type, regcache, readbuf);
1915 cris_store_return_value (type, regcache, writebuf);
1917 return RETURN_VALUE_REGISTER_CONVENTION;
1920 /* Returns 1 if the given type will be passed by pointer rather than
1923 /* In the CRIS ABI, arguments shorter than or equal to 64 bits are passed
1927 cris_reg_struct_has_addr (int gcc_p, struct type *type)
1929 return (TYPE_LENGTH (type) > 8);
1932 /* Calculates a value that measures how good inst_args constraints an
1933 instruction. It stems from cris_constraint, found in cris-dis.c. */
1936 constraint (unsigned int insn, const signed char *inst_args,
1937 inst_env_type *inst_env)
1942 const char *s = inst_args;
1948 if ((insn & 0x30) == 0x30)
1953 /* A prefix operand. */
1954 if (inst_env->prefix_found)
1960 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1961 valid "push" size. In case of special register, it may be != 4. */
1962 if (inst_env->prefix_found)
1968 retval = (((insn >> 0xC) & 0xF) == (insn & 0xF));
1976 tmp = (insn >> 0xC) & 0xF;
1978 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1980 /* Since we match four bits, we will give a value of
1981 4 - 1 = 3 in a match. If there is a corresponding
1982 exact match of a special register in another pattern, it
1983 will get a value of 4, which will be higher. This should
1984 be correct in that an exact pattern would match better that
1986 Note that there is a reason for not returning zero; the
1987 pattern for "clear" is partly matched in the bit-pattern
1988 (the two lower bits must be zero), while the bit-pattern
1989 for a move from a special register is matched in the
1990 register constraint.
1991 This also means we will will have a race condition if
1992 there is a partly match in three bits in the bit pattern. */
1993 if (tmp == cris_spec_regs[i].number)
2000 if (cris_spec_regs[i].name == NULL)
2007 /* Returns the number of bits set in the variable value. */
2010 number_of_bits (unsigned int value)
2012 int number_of_bits = 0;
2016 number_of_bits += 1;
2017 value &= (value - 1);
2019 return number_of_bits;
2022 /* Finds the address that should contain the single step breakpoint(s).
2023 It stems from code in cris-dis.c. */
2026 find_cris_op (unsigned short insn, inst_env_type *inst_env)
2029 int max_level_of_match = -1;
2030 int max_matched = -1;
2033 for (i = 0; cris_opcodes[i].name != NULL; i++)
2035 if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match)
2036 && ((cris_opcodes[i].lose & insn) == 0)
2037 /* Only CRISv10 instructions, please. */
2038 && (cris_opcodes[i].applicable_version != cris_ver_v32p))
2040 level_of_match = constraint (insn, cris_opcodes[i].args, inst_env);
2041 if (level_of_match >= 0)
2044 number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose);
2045 if (level_of_match > max_level_of_match)
2048 max_level_of_match = level_of_match;
2049 if (level_of_match == 16)
2051 /* All bits matched, cannot find better. */
2061 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
2062 actually an internal error. */
2065 find_step_target (inst_env_type *inst_env)
2069 unsigned short insn;
2071 /* Create a local register image and set the initial state. */
2072 for (i = 0; i < NUM_GENREGS; i++)
2074 inst_env->reg[i] = (unsigned long) read_register (i);
2076 offset = NUM_GENREGS;
2077 for (i = 0; i < NUM_SPECREGS; i++)
2079 inst_env->preg[i] = (unsigned long) read_register (offset + i);
2081 inst_env->branch_found = 0;
2082 inst_env->slot_needed = 0;
2083 inst_env->delay_slot_pc_active = 0;
2084 inst_env->prefix_found = 0;
2085 inst_env->invalid = 0;
2086 inst_env->xflag_found = 0;
2087 inst_env->disable_interrupt = 0;
2089 /* Look for a step target. */
2092 /* Read an instruction from the client. */
2093 insn = read_memory_unsigned_integer (inst_env->reg[PC_REGNUM], 2);
2095 /* If the instruction is not in a delay slot the new content of the
2096 PC is [PC] + 2. If the instruction is in a delay slot it is not
2097 that simple. Since a instruction in a delay slot cannot change
2098 the content of the PC, it does not matter what value PC will have.
2099 Just make sure it is a valid instruction. */
2100 if (!inst_env->delay_slot_pc_active)
2102 inst_env->reg[PC_REGNUM] += 2;
2106 inst_env->delay_slot_pc_active = 0;
2107 inst_env->reg[PC_REGNUM] = inst_env->delay_slot_pc;
2109 /* Analyse the present instruction. */
2110 i = find_cris_op (insn, inst_env);
2113 inst_env->invalid = 1;
2117 cris_gdb_func (cris_opcodes[i].op, insn, inst_env);
2119 } while (!inst_env->invalid
2120 && (inst_env->prefix_found || inst_env->xflag_found
2121 || inst_env->slot_needed));
2125 /* There is no hardware single-step support. The function find_step_target
2126 digs through the opcodes in order to find all possible targets.
2127 Either one ordinary target or two targets for branches may be found. */
2130 cris_software_single_step (enum target_signal ignore, int insert_breakpoints)
2132 inst_env_type inst_env;
2134 if (insert_breakpoints)
2136 /* Analyse the present instruction environment and insert
2138 int status = find_step_target (&inst_env);
2141 /* Could not find a target. Things are likely to go downhill
2143 warning (_("CRIS software single step could not find a step target."));
2147 /* Insert at most two breakpoints. One for the next PC content
2148 and possibly another one for a branch, jump, etc. */
2149 next_pc = (CORE_ADDR) inst_env.reg[PC_REGNUM];
2150 target_insert_breakpoint (next_pc, break_mem[0]);
2151 if (inst_env.branch_found
2152 && (CORE_ADDR) inst_env.branch_break_address != next_pc)
2154 branch_target_address =
2155 (CORE_ADDR) inst_env.branch_break_address;
2156 target_insert_breakpoint (branch_target_address, break_mem[1]);
2157 branch_break_inserted = 1;
2163 /* Remove breakpoints. */
2164 target_remove_breakpoint (next_pc, break_mem[0]);
2165 if (branch_break_inserted)
2167 target_remove_breakpoint (branch_target_address, break_mem[1]);
2168 branch_break_inserted = 0;
2173 /* Calculates the prefix value for quick offset addressing mode. */
2176 quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2178 /* It's invalid to be in a delay slot. You can't have a prefix to this
2179 instruction (not 100% sure). */
2180 if (inst_env->slot_needed || inst_env->prefix_found)
2182 inst_env->invalid = 1;
2186 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2187 inst_env->prefix_value += cris_get_bdap_quick_offset (inst);
2189 /* A prefix doesn't change the xflag_found. But the rest of the flags
2191 inst_env->slot_needed = 0;
2192 inst_env->prefix_found = 1;
2195 /* Updates the autoincrement register. The size of the increment is derived
2196 from the size of the operation. The PC is always kept aligned on even
2200 process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env)
2202 if (size == INST_BYTE_SIZE)
2204 inst_env->reg[cris_get_operand1 (inst)] += 1;
2206 /* The PC must be word aligned, so increase the PC with one
2207 word even if the size is byte. */
2208 if (cris_get_operand1 (inst) == REG_PC)
2210 inst_env->reg[REG_PC] += 1;
2213 else if (size == INST_WORD_SIZE)
2215 inst_env->reg[cris_get_operand1 (inst)] += 2;
2217 else if (size == INST_DWORD_SIZE)
2219 inst_env->reg[cris_get_operand1 (inst)] += 4;
2224 inst_env->invalid = 1;
2228 /* Just a forward declaration. */
2230 static unsigned long get_data_from_address (unsigned short *inst,
2233 /* Calculates the prefix value for the general case of offset addressing
2237 bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2242 /* It's invalid to be in a delay slot. */
2243 if (inst_env->slot_needed || inst_env->prefix_found)
2245 inst_env->invalid = 1;
2249 /* The calculation of prefix_value used to be after process_autoincrement,
2250 but that fails for an instruction such as jsr [$r0+12] which is encoded
2251 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
2252 mustn't be incremented until we have read it and what it points at. */
2253 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2255 /* The offset is an indirection of the contents of the operand1 register. */
2256 inst_env->prefix_value +=
2257 get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)]);
2259 if (cris_get_mode (inst) == AUTOINC_MODE)
2261 process_autoincrement (cris_get_size (inst), inst, inst_env);
2264 /* A prefix doesn't change the xflag_found. But the rest of the flags
2266 inst_env->slot_needed = 0;
2267 inst_env->prefix_found = 1;
2270 /* Calculates the prefix value for the index addressing mode. */
2273 biap_prefix (unsigned short inst, inst_env_type *inst_env)
2275 /* It's invalid to be in a delay slot. I can't see that it's possible to
2276 have a prefix to this instruction. So I will treat this as invalid. */
2277 if (inst_env->slot_needed || inst_env->prefix_found)
2279 inst_env->invalid = 1;
2283 inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)];
2285 /* The offset is the operand2 value shifted the size of the instruction
2287 inst_env->prefix_value +=
2288 inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst);
2290 /* If the PC is operand1 (base) the address used is the address after
2291 the main instruction, i.e. address + 2 (the PC is already compensated
2292 for the prefix operation). */
2293 if (cris_get_operand1 (inst) == REG_PC)
2295 inst_env->prefix_value += 2;
2298 /* A prefix doesn't change the xflag_found. But the rest of the flags
2300 inst_env->slot_needed = 0;
2301 inst_env->xflag_found = 0;
2302 inst_env->prefix_found = 1;
2305 /* Calculates the prefix value for the double indirect addressing mode. */
2308 dip_prefix (unsigned short inst, inst_env_type *inst_env)
2313 /* It's invalid to be in a delay slot. */
2314 if (inst_env->slot_needed || inst_env->prefix_found)
2316 inst_env->invalid = 1;
2320 /* The prefix value is one dereference of the contents of the operand1
2322 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2323 inst_env->prefix_value = read_memory_unsigned_integer (address, 4);
2325 /* Check if the mode is autoincrement. */
2326 if (cris_get_mode (inst) == AUTOINC_MODE)
2328 inst_env->reg[cris_get_operand1 (inst)] += 4;
2331 /* A prefix doesn't change the xflag_found. But the rest of the flags
2333 inst_env->slot_needed = 0;
2334 inst_env->xflag_found = 0;
2335 inst_env->prefix_found = 1;
2338 /* Finds the destination for a branch with 8-bits offset. */
2341 eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2346 /* If we have a prefix or are in a delay slot it's bad. */
2347 if (inst_env->slot_needed || inst_env->prefix_found)
2349 inst_env->invalid = 1;
2353 /* We have a branch, find out where the branch will land. */
2354 offset = cris_get_branch_short_offset (inst);
2356 /* Check if the offset is signed. */
2357 if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK)
2362 /* The offset ends with the sign bit, set it to zero. The address
2363 should always be word aligned. */
2364 offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK;
2366 inst_env->branch_found = 1;
2367 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2369 inst_env->slot_needed = 1;
2370 inst_env->prefix_found = 0;
2371 inst_env->xflag_found = 0;
2372 inst_env->disable_interrupt = 1;
2375 /* Finds the destination for a branch with 16-bits offset. */
2378 sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2382 /* If we have a prefix or is in a delay slot it's bad. */
2383 if (inst_env->slot_needed || inst_env->prefix_found)
2385 inst_env->invalid = 1;
2389 /* We have a branch, find out the offset for the branch. */
2390 offset = read_memory_integer (inst_env->reg[REG_PC], 2);
2392 /* The instruction is one word longer than normal, so add one word
2394 inst_env->reg[REG_PC] += 2;
2396 inst_env->branch_found = 1;
2397 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2400 inst_env->slot_needed = 1;
2401 inst_env->prefix_found = 0;
2402 inst_env->xflag_found = 0;
2403 inst_env->disable_interrupt = 1;
2406 /* Handles the ABS instruction. */
2409 abs_op (unsigned short inst, inst_env_type *inst_env)
2414 /* ABS can't have a prefix, so it's bad if it does. */
2415 if (inst_env->prefix_found)
2417 inst_env->invalid = 1;
2421 /* Check if the operation affects the PC. */
2422 if (cris_get_operand2 (inst) == REG_PC)
2425 /* It's invalid to change to the PC if we are in a delay slot. */
2426 if (inst_env->slot_needed)
2428 inst_env->invalid = 1;
2432 value = (long) inst_env->reg[REG_PC];
2434 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
2435 if (value != SIGNED_DWORD_MASK)
2438 inst_env->reg[REG_PC] = (long) value;
2442 inst_env->slot_needed = 0;
2443 inst_env->prefix_found = 0;
2444 inst_env->xflag_found = 0;
2445 inst_env->disable_interrupt = 0;
2448 /* Handles the ADDI instruction. */
2451 addi_op (unsigned short inst, inst_env_type *inst_env)
2453 /* It's invalid to have the PC as base register. And ADDI can't have
2455 if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC))
2457 inst_env->invalid = 1;
2461 inst_env->slot_needed = 0;
2462 inst_env->prefix_found = 0;
2463 inst_env->xflag_found = 0;
2464 inst_env->disable_interrupt = 0;
2467 /* Handles the ASR instruction. */
2470 asr_op (unsigned short inst, inst_env_type *inst_env)
2473 unsigned long value;
2474 unsigned long signed_extend_mask = 0;
2476 /* ASR can't have a prefix, so check that it doesn't. */
2477 if (inst_env->prefix_found)
2479 inst_env->invalid = 1;
2483 /* Check if the PC is the target register. */
2484 if (cris_get_operand2 (inst) == REG_PC)
2486 /* It's invalid to change the PC in a delay slot. */
2487 if (inst_env->slot_needed)
2489 inst_env->invalid = 1;
2492 /* Get the number of bits to shift. */
2493 shift_steps = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]);
2494 value = inst_env->reg[REG_PC];
2496 /* Find out how many bits the operation should apply to. */
2497 if (cris_get_size (inst) == INST_BYTE_SIZE)
2499 if (value & SIGNED_BYTE_MASK)
2501 signed_extend_mask = 0xFF;
2502 signed_extend_mask = signed_extend_mask >> shift_steps;
2503 signed_extend_mask = ~signed_extend_mask;
2505 value = value >> shift_steps;
2506 value |= signed_extend_mask;
2508 inst_env->reg[REG_PC] &= 0xFFFFFF00;
2509 inst_env->reg[REG_PC] |= value;
2511 else if (cris_get_size (inst) == INST_WORD_SIZE)
2513 if (value & SIGNED_WORD_MASK)
2515 signed_extend_mask = 0xFFFF;
2516 signed_extend_mask = signed_extend_mask >> shift_steps;
2517 signed_extend_mask = ~signed_extend_mask;
2519 value = value >> shift_steps;
2520 value |= signed_extend_mask;
2522 inst_env->reg[REG_PC] &= 0xFFFF0000;
2523 inst_env->reg[REG_PC] |= value;
2525 else if (cris_get_size (inst) == INST_DWORD_SIZE)
2527 if (value & SIGNED_DWORD_MASK)
2529 signed_extend_mask = 0xFFFFFFFF;
2530 signed_extend_mask = signed_extend_mask >> shift_steps;
2531 signed_extend_mask = ~signed_extend_mask;
2533 value = value >> shift_steps;
2534 value |= signed_extend_mask;
2535 inst_env->reg[REG_PC] = value;
2538 inst_env->slot_needed = 0;
2539 inst_env->prefix_found = 0;
2540 inst_env->xflag_found = 0;
2541 inst_env->disable_interrupt = 0;
2544 /* Handles the ASRQ instruction. */
2547 asrq_op (unsigned short inst, inst_env_type *inst_env)
2551 unsigned long value;
2552 unsigned long signed_extend_mask = 0;
2554 /* ASRQ can't have a prefix, so check that it doesn't. */
2555 if (inst_env->prefix_found)
2557 inst_env->invalid = 1;
2561 /* Check if the PC is the target register. */
2562 if (cris_get_operand2 (inst) == REG_PC)
2565 /* It's invalid to change the PC in a delay slot. */
2566 if (inst_env->slot_needed)
2568 inst_env->invalid = 1;
2571 /* The shift size is given as a 5 bit quick value, i.e. we don't
2572 want the the sign bit of the quick value. */
2573 shift_steps = cris_get_asr_shift_steps (inst);
2574 value = inst_env->reg[REG_PC];
2575 if (value & SIGNED_DWORD_MASK)
2577 signed_extend_mask = 0xFFFFFFFF;
2578 signed_extend_mask = signed_extend_mask >> shift_steps;
2579 signed_extend_mask = ~signed_extend_mask;
2581 value = value >> shift_steps;
2582 value |= signed_extend_mask;
2583 inst_env->reg[REG_PC] = value;
2585 inst_env->slot_needed = 0;
2586 inst_env->prefix_found = 0;
2587 inst_env->xflag_found = 0;
2588 inst_env->disable_interrupt = 0;
2591 /* Handles the AX, EI and SETF instruction. */
2594 ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env)
2596 if (inst_env->prefix_found)
2598 inst_env->invalid = 1;
2601 /* Check if the instruction is setting the X flag. */
2602 if (cris_is_xflag_bit_on (inst))
2604 inst_env->xflag_found = 1;
2608 inst_env->xflag_found = 0;
2610 inst_env->slot_needed = 0;
2611 inst_env->prefix_found = 0;
2612 inst_env->disable_interrupt = 1;
2615 /* Checks if the instruction is in assign mode. If so, it updates the assign
2616 register. Note that check_assign assumes that the caller has checked that
2617 there is a prefix to this instruction. The mode check depends on this. */
2620 check_assign (unsigned short inst, inst_env_type *inst_env)
2622 /* Check if it's an assign addressing mode. */
2623 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2625 /* Assign the prefix value to operand 1. */
2626 inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value;
2630 /* Handles the 2-operand BOUND instruction. */
2633 two_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2635 /* It's invalid to have the PC as the index operand. */
2636 if (cris_get_operand2 (inst) == REG_PC)
2638 inst_env->invalid = 1;
2641 /* Check if we have a prefix. */
2642 if (inst_env->prefix_found)
2644 check_assign (inst, inst_env);
2646 /* Check if this is an autoincrement mode. */
2647 else if (cris_get_mode (inst) == AUTOINC_MODE)
2649 /* It's invalid to change the PC in a delay slot. */
2650 if (inst_env->slot_needed)
2652 inst_env->invalid = 1;
2655 process_autoincrement (cris_get_size (inst), inst, inst_env);
2657 inst_env->slot_needed = 0;
2658 inst_env->prefix_found = 0;
2659 inst_env->xflag_found = 0;
2660 inst_env->disable_interrupt = 0;
2663 /* Handles the 3-operand BOUND instruction. */
2666 three_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2668 /* It's an error if we haven't got a prefix. And it's also an error
2669 if the PC is the destination register. */
2670 if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC))
2672 inst_env->invalid = 1;
2675 inst_env->slot_needed = 0;
2676 inst_env->prefix_found = 0;
2677 inst_env->xflag_found = 0;
2678 inst_env->disable_interrupt = 0;
2681 /* Clears the status flags in inst_env. */
2684 btst_nop_op (unsigned short inst, inst_env_type *inst_env)
2686 /* It's an error if we have got a prefix. */
2687 if (inst_env->prefix_found)
2689 inst_env->invalid = 1;
2693 inst_env->slot_needed = 0;
2694 inst_env->prefix_found = 0;
2695 inst_env->xflag_found = 0;
2696 inst_env->disable_interrupt = 0;
2699 /* Clears the status flags in inst_env. */
2702 clearf_di_op (unsigned short inst, inst_env_type *inst_env)
2704 /* It's an error if we have got a prefix. */
2705 if (inst_env->prefix_found)
2707 inst_env->invalid = 1;
2711 inst_env->slot_needed = 0;
2712 inst_env->prefix_found = 0;
2713 inst_env->xflag_found = 0;
2714 inst_env->disable_interrupt = 1;
2717 /* Handles the CLEAR instruction if it's in register mode. */
2720 reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env)
2722 /* Check if the target is the PC. */
2723 if (cris_get_operand2 (inst) == REG_PC)
2725 /* The instruction will clear the instruction's size bits. */
2726 int clear_size = cris_get_clear_size (inst);
2727 if (clear_size == INST_BYTE_SIZE)
2729 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00;
2731 if (clear_size == INST_WORD_SIZE)
2733 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000;
2735 if (clear_size == INST_DWORD_SIZE)
2737 inst_env->delay_slot_pc = 0x0;
2739 /* The jump will be delayed with one delay slot. So we need a delay
2741 inst_env->slot_needed = 1;
2742 inst_env->delay_slot_pc_active = 1;
2746 /* The PC will not change => no delay slot. */
2747 inst_env->slot_needed = 0;
2749 inst_env->prefix_found = 0;
2750 inst_env->xflag_found = 0;
2751 inst_env->disable_interrupt = 0;
2754 /* Handles the TEST instruction if it's in register mode. */
2757 reg_mode_test_op (unsigned short inst, inst_env_type *inst_env)
2759 /* It's an error if we have got a prefix. */
2760 if (inst_env->prefix_found)
2762 inst_env->invalid = 1;
2765 inst_env->slot_needed = 0;
2766 inst_env->prefix_found = 0;
2767 inst_env->xflag_found = 0;
2768 inst_env->disable_interrupt = 0;
2772 /* Handles the CLEAR and TEST instruction if the instruction isn't
2773 in register mode. */
2776 none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env)
2778 /* Check if we are in a prefix mode. */
2779 if (inst_env->prefix_found)
2781 /* The only way the PC can change is if this instruction is in
2782 assign addressing mode. */
2783 check_assign (inst, inst_env);
2785 /* Indirect mode can't change the PC so just check if the mode is
2787 else if (cris_get_mode (inst) == AUTOINC_MODE)
2789 process_autoincrement (cris_get_size (inst), inst, inst_env);
2791 inst_env->slot_needed = 0;
2792 inst_env->prefix_found = 0;
2793 inst_env->xflag_found = 0;
2794 inst_env->disable_interrupt = 0;
2797 /* Checks that the PC isn't the destination register or the instructions has
2801 dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env)
2803 /* It's invalid to have the PC as the destination. The instruction can't
2805 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2807 inst_env->invalid = 1;
2811 inst_env->slot_needed = 0;
2812 inst_env->prefix_found = 0;
2813 inst_env->xflag_found = 0;
2814 inst_env->disable_interrupt = 0;
2817 /* Checks that the instruction doesn't have a prefix. */
2820 break_op (unsigned short inst, inst_env_type *inst_env)
2822 /* The instruction can't have a prefix. */
2823 if (inst_env->prefix_found)
2825 inst_env->invalid = 1;
2829 inst_env->slot_needed = 0;
2830 inst_env->prefix_found = 0;
2831 inst_env->xflag_found = 0;
2832 inst_env->disable_interrupt = 1;
2835 /* Checks that the PC isn't the destination register and that the instruction
2836 doesn't have a prefix. */
2839 scc_op (unsigned short inst, inst_env_type *inst_env)
2841 /* It's invalid to have the PC as the destination. The instruction can't
2843 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2845 inst_env->invalid = 1;
2849 inst_env->slot_needed = 0;
2850 inst_env->prefix_found = 0;
2851 inst_env->xflag_found = 0;
2852 inst_env->disable_interrupt = 1;
2855 /* Handles the register mode JUMP instruction. */
2858 reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2860 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2861 you can't have a prefix. */
2862 if ((inst_env->slot_needed) || (inst_env->prefix_found))
2864 inst_env->invalid = 1;
2868 /* Just change the PC. */
2869 inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)];
2870 inst_env->slot_needed = 0;
2871 inst_env->prefix_found = 0;
2872 inst_env->xflag_found = 0;
2873 inst_env->disable_interrupt = 1;
2876 /* Handles the JUMP instruction for all modes except register. */
2879 none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2881 unsigned long newpc;
2884 /* It's invalid to do a JUMP in a delay slot. */
2885 if (inst_env->slot_needed)
2887 inst_env->invalid = 1;
2891 /* Check if we have a prefix. */
2892 if (inst_env->prefix_found)
2894 check_assign (inst, inst_env);
2896 /* Get the new value for the the PC. */
2898 read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value,
2903 /* Get the new value for the PC. */
2904 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2905 newpc = read_memory_unsigned_integer (address, 4);
2907 /* Check if we should increment a register. */
2908 if (cris_get_mode (inst) == AUTOINC_MODE)
2910 inst_env->reg[cris_get_operand1 (inst)] += 4;
2913 inst_env->reg[REG_PC] = newpc;
2915 inst_env->slot_needed = 0;
2916 inst_env->prefix_found = 0;
2917 inst_env->xflag_found = 0;
2918 inst_env->disable_interrupt = 1;
2921 /* Handles moves to special registers (aka P-register) for all modes. */
2924 move_to_preg_op (unsigned short inst, inst_env_type *inst_env)
2926 if (inst_env->prefix_found)
2928 /* The instruction has a prefix that means we are only interested if
2929 the instruction is in assign mode. */
2930 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2932 /* The prefix handles the problem if we are in a delay slot. */
2933 if (cris_get_operand1 (inst) == REG_PC)
2935 /* Just take care of the assign. */
2936 check_assign (inst, inst_env);
2940 else if (cris_get_mode (inst) == AUTOINC_MODE)
2942 /* The instruction doesn't have a prefix, the only case left that we
2943 are interested in is the autoincrement mode. */
2944 if (cris_get_operand1 (inst) == REG_PC)
2946 /* If the PC is to be incremented it's invalid to be in a
2948 if (inst_env->slot_needed)
2950 inst_env->invalid = 1;
2954 /* The increment depends on the size of the special register. */
2955 if (cris_register_size (cris_get_operand2 (inst)) == 1)
2957 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2959 else if (cris_register_size (cris_get_operand2 (inst)) == 2)
2961 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2965 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2969 inst_env->slot_needed = 0;
2970 inst_env->prefix_found = 0;
2971 inst_env->xflag_found = 0;
2972 inst_env->disable_interrupt = 1;
2975 /* Handles moves from special registers (aka P-register) for all modes
2979 none_reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env)
2981 if (inst_env->prefix_found)
2983 /* The instruction has a prefix that means we are only interested if
2984 the instruction is in assign mode. */
2985 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2987 /* The prefix handles the problem if we are in a delay slot. */
2988 if (cris_get_operand1 (inst) == REG_PC)
2990 /* Just take care of the assign. */
2991 check_assign (inst, inst_env);
2995 /* The instruction doesn't have a prefix, the only case left that we
2996 are interested in is the autoincrement mode. */
2997 else if (cris_get_mode (inst) == AUTOINC_MODE)
2999 if (cris_get_operand1 (inst) == REG_PC)
3001 /* If the PC is to be incremented it's invalid to be in a
3003 if (inst_env->slot_needed)
3005 inst_env->invalid = 1;
3009 /* The increment depends on the size of the special register. */
3010 if (cris_register_size (cris_get_operand2 (inst)) == 1)
3012 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
3014 else if (cris_register_size (cris_get_operand2 (inst)) == 2)
3016 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
3020 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
3024 inst_env->slot_needed = 0;
3025 inst_env->prefix_found = 0;
3026 inst_env->xflag_found = 0;
3027 inst_env->disable_interrupt = 1;
3030 /* Handles moves from special registers (aka P-register) when the mode
3034 reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env)
3036 /* Register mode move from special register can't have a prefix. */
3037 if (inst_env->prefix_found)
3039 inst_env->invalid = 1;
3043 if (cris_get_operand1 (inst) == REG_PC)
3045 /* It's invalid to change the PC in a delay slot. */
3046 if (inst_env->slot_needed)
3048 inst_env->invalid = 1;
3051 /* The destination is the PC, the jump will have a delay slot. */
3052 inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)];
3053 inst_env->slot_needed = 1;
3054 inst_env->delay_slot_pc_active = 1;
3058 /* If the destination isn't PC, there will be no jump. */
3059 inst_env->slot_needed = 0;
3061 inst_env->prefix_found = 0;
3062 inst_env->xflag_found = 0;
3063 inst_env->disable_interrupt = 1;
3066 /* Handles the MOVEM from memory to general register instruction. */
3069 move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env)
3071 if (inst_env->prefix_found)
3073 /* The prefix handles the problem if we are in a delay slot. Is the
3074 MOVEM instruction going to change the PC? */
3075 if (cris_get_operand2 (inst) >= REG_PC)
3077 inst_env->reg[REG_PC] =
3078 read_memory_unsigned_integer (inst_env->prefix_value, 4);
3080 /* The assign value is the value after the increment. Normally, the
3081 assign value is the value before the increment. */
3082 if ((cris_get_operand1 (inst) == REG_PC)
3083 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3085 inst_env->reg[REG_PC] = inst_env->prefix_value;
3086 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3091 /* Is the MOVEM instruction going to change the PC? */
3092 if (cris_get_operand2 (inst) == REG_PC)
3094 /* It's invalid to change the PC in a delay slot. */
3095 if (inst_env->slot_needed)
3097 inst_env->invalid = 1;
3100 inst_env->reg[REG_PC] =
3101 read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)],
3104 /* The increment is not depending on the size, instead it's depending
3105 on the number of registers loaded from memory. */
3106 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3108 /* It's invalid to change the PC in a delay slot. */
3109 if (inst_env->slot_needed)
3111 inst_env->invalid = 1;
3114 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3117 inst_env->slot_needed = 0;
3118 inst_env->prefix_found = 0;
3119 inst_env->xflag_found = 0;
3120 inst_env->disable_interrupt = 0;
3123 /* Handles the MOVEM to memory from general register instruction. */
3126 move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env)
3128 if (inst_env->prefix_found)
3130 /* The assign value is the value after the increment. Normally, the
3131 assign value is the value before the increment. */
3132 if ((cris_get_operand1 (inst) == REG_PC) &&
3133 (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3135 /* The prefix handles the problem if we are in a delay slot. */
3136 inst_env->reg[REG_PC] = inst_env->prefix_value;
3137 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3142 /* The increment is not depending on the size, instead it's depending
3143 on the number of registers loaded to memory. */
3144 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3146 /* It's invalid to change the PC in a delay slot. */
3147 if (inst_env->slot_needed)
3149 inst_env->invalid = 1;
3152 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3155 inst_env->slot_needed = 0;
3156 inst_env->prefix_found = 0;
3157 inst_env->xflag_found = 0;
3158 inst_env->disable_interrupt = 0;
3161 /* Handles the intructions that's not yet implemented, by setting
3162 inst_env->invalid to true. */
3165 not_implemented_op (unsigned short inst, inst_env_type *inst_env)
3167 inst_env->invalid = 1;
3170 /* Handles the XOR instruction. */
3173 xor_op (unsigned short inst, inst_env_type *inst_env)
3175 /* XOR can't have a prefix. */
3176 if (inst_env->prefix_found)
3178 inst_env->invalid = 1;
3182 /* Check if the PC is the target. */
3183 if (cris_get_operand2 (inst) == REG_PC)
3185 /* It's invalid to change the PC in a delay slot. */
3186 if (inst_env->slot_needed)
3188 inst_env->invalid = 1;
3191 inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)];
3193 inst_env->slot_needed = 0;
3194 inst_env->prefix_found = 0;
3195 inst_env->xflag_found = 0;
3196 inst_env->disable_interrupt = 0;
3199 /* Handles the MULS instruction. */
3202 muls_op (unsigned short inst, inst_env_type *inst_env)
3204 /* MULS/U can't have a prefix. */
3205 if (inst_env->prefix_found)
3207 inst_env->invalid = 1;
3211 /* Consider it invalid if the PC is the target. */
3212 if (cris_get_operand2 (inst) == REG_PC)
3214 inst_env->invalid = 1;
3217 inst_env->slot_needed = 0;
3218 inst_env->prefix_found = 0;
3219 inst_env->xflag_found = 0;
3220 inst_env->disable_interrupt = 0;
3223 /* Handles the MULU instruction. */
3226 mulu_op (unsigned short inst, inst_env_type *inst_env)
3228 /* MULS/U can't have a prefix. */
3229 if (inst_env->prefix_found)
3231 inst_env->invalid = 1;
3235 /* Consider it invalid if the PC is the target. */
3236 if (cris_get_operand2 (inst) == REG_PC)
3238 inst_env->invalid = 1;
3241 inst_env->slot_needed = 0;
3242 inst_env->prefix_found = 0;
3243 inst_env->xflag_found = 0;
3244 inst_env->disable_interrupt = 0;
3247 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
3248 The MOVE instruction is the move from source to register. */
3251 add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env,
3252 unsigned long source1, unsigned long source2)
3254 unsigned long pc_mask;
3255 unsigned long operation_mask;
3257 /* Find out how many bits the operation should apply to. */
3258 if (cris_get_size (inst) == INST_BYTE_SIZE)
3260 pc_mask = 0xFFFFFF00;
3261 operation_mask = 0xFF;
3263 else if (cris_get_size (inst) == INST_WORD_SIZE)
3265 pc_mask = 0xFFFF0000;
3266 operation_mask = 0xFFFF;
3268 else if (cris_get_size (inst) == INST_DWORD_SIZE)
3271 operation_mask = 0xFFFFFFFF;
3275 /* The size is out of range. */
3276 inst_env->invalid = 1;
3280 /* The instruction just works on uw_operation_mask bits. */
3281 source2 &= operation_mask;
3282 source1 &= operation_mask;
3284 /* Now calculate the result. The opcode's 3 first bits separates
3285 the different actions. */
3286 switch (cris_get_opcode (inst) & 7)
3296 case 2: /* subtract */
3300 case 3: /* compare */
3312 inst_env->invalid = 1;
3318 /* Make sure that the result doesn't contain more than the instruction
3320 source2 &= operation_mask;
3322 /* Calculate the new breakpoint address. */
3323 inst_env->reg[REG_PC] &= pc_mask;
3324 inst_env->reg[REG_PC] |= source1;
3328 /* Extends the value from either byte or word size to a dword. If the mode
3329 is zero extend then the value is extended with zero. If instead the mode
3330 is signed extend the sign bit of the value is taken into consideration. */
3332 static unsigned long
3333 do_sign_or_zero_extend (unsigned long value, unsigned short *inst)
3335 /* The size can be either byte or word, check which one it is.
3336 Don't check the highest bit, it's indicating if it's a zero
3338 if (cris_get_size (*inst) & INST_WORD_SIZE)
3343 /* Check if the instruction is signed extend. If so, check if value has
3345 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK))
3347 value |= SIGNED_WORD_EXTEND_MASK;
3355 /* Check if the instruction is signed extend. If so, check if value has
3357 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK))
3359 value |= SIGNED_BYTE_EXTEND_MASK;
3362 /* The size should now be dword. */
3363 cris_set_size_to_dword (inst);
3367 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3368 instruction. The MOVE instruction is the move from source to register. */
3371 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3372 inst_env_type *inst_env)
3374 unsigned long operand1;
3375 unsigned long operand2;
3377 /* It's invalid to have a prefix to the instruction. This is a register
3378 mode instruction and can't have a prefix. */
3379 if (inst_env->prefix_found)
3381 inst_env->invalid = 1;
3384 /* Check if the instruction has PC as its target. */
3385 if (cris_get_operand2 (inst) == REG_PC)
3387 if (inst_env->slot_needed)
3389 inst_env->invalid = 1;
3392 /* The instruction has the PC as its target register. */
3393 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3394 operand2 = inst_env->reg[REG_PC];
3396 /* Check if it's a extend, signed or zero instruction. */
3397 if (cris_get_opcode (inst) < 4)
3399 operand1 = do_sign_or_zero_extend (operand1, &inst);
3401 /* Calculate the PC value after the instruction, i.e. where the
3402 breakpoint should be. The order of the udw_operands is vital. */
3403 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3405 inst_env->slot_needed = 0;
3406 inst_env->prefix_found = 0;
3407 inst_env->xflag_found = 0;
3408 inst_env->disable_interrupt = 0;
3411 /* Returns the data contained at address. The size of the data is derived from
3412 the size of the operation. If the instruction is a zero or signed
3413 extend instruction, the size field is changed in instruction. */
3415 static unsigned long
3416 get_data_from_address (unsigned short *inst, CORE_ADDR address)
3418 int size = cris_get_size (*inst);
3419 unsigned long value;
3421 /* If it's an extend instruction we don't want the signed extend bit,
3422 because it influences the size. */
3423 if (cris_get_opcode (*inst) < 4)
3425 size &= ~SIGNED_EXTEND_BIT_MASK;
3427 /* Is there a need for checking the size? Size should contain the number of
3430 value = read_memory_unsigned_integer (address, size);
3432 /* Check if it's an extend, signed or zero instruction. */
3433 if (cris_get_opcode (*inst) < 4)
3435 value = do_sign_or_zero_extend (value, inst);
3440 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3441 instructions. The MOVE instruction is the move from source to register. */
3444 handle_prefix_assign_mode_for_aritm_op (unsigned short inst,
3445 inst_env_type *inst_env)
3447 unsigned long operand2;
3448 unsigned long operand3;
3450 check_assign (inst, inst_env);
3451 if (cris_get_operand2 (inst) == REG_PC)
3453 operand2 = inst_env->reg[REG_PC];
3455 /* Get the value of the third operand. */
3456 operand3 = get_data_from_address (&inst, inst_env->prefix_value);
3458 /* Calculate the PC value after the instruction, i.e. where the
3459 breakpoint should be. The order of the udw_operands is vital. */
3460 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3462 inst_env->slot_needed = 0;
3463 inst_env->prefix_found = 0;
3464 inst_env->xflag_found = 0;
3465 inst_env->disable_interrupt = 0;
3468 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3469 OR instructions. Note that for this to work as expected, the calling
3470 function must have made sure that there is a prefix to this instruction. */
3473 three_operand_add_sub_cmp_and_or_op (unsigned short inst,
3474 inst_env_type *inst_env)
3476 unsigned long operand2;
3477 unsigned long operand3;
3479 if (cris_get_operand1 (inst) == REG_PC)
3481 /* The PC will be changed by the instruction. */
3482 operand2 = inst_env->reg[cris_get_operand2 (inst)];
3484 /* Get the value of the third operand. */
3485 operand3 = get_data_from_address (&inst, inst_env->prefix_value);
3487 /* Calculate the PC value after the instruction, i.e. where the
3488 breakpoint should be. */
3489 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3491 inst_env->slot_needed = 0;
3492 inst_env->prefix_found = 0;
3493 inst_env->xflag_found = 0;
3494 inst_env->disable_interrupt = 0;
3497 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3498 instructions. The MOVE instruction is the move from source to register. */
3501 handle_prefix_index_mode_for_aritm_op (unsigned short inst,
3502 inst_env_type *inst_env)
3504 if (cris_get_operand1 (inst) != cris_get_operand2 (inst))
3506 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
3507 SUB, AND or OR something weird is going on (if everything works these
3508 instructions should end up in the three operand version). */
3509 inst_env->invalid = 1;
3514 /* three_operand_add_sub_cmp_and_or does the same as we should do here
3516 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3518 inst_env->slot_needed = 0;
3519 inst_env->prefix_found = 0;
3520 inst_env->xflag_found = 0;
3521 inst_env->disable_interrupt = 0;
3524 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3525 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
3526 source to register. */
3529 handle_inc_and_index_mode_for_aritm_op (unsigned short inst,
3530 inst_env_type *inst_env)
3532 unsigned long operand1;
3533 unsigned long operand2;
3534 unsigned long operand3;
3537 /* The instruction is either an indirect or autoincrement addressing mode.
3538 Check if the destination register is the PC. */
3539 if (cris_get_operand2 (inst) == REG_PC)
3541 /* Must be done here, get_data_from_address may change the size
3543 size = cris_get_size (inst);
3544 operand2 = inst_env->reg[REG_PC];
3546 /* Get the value of the third operand, i.e. the indirect operand. */
3547 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3548 operand3 = get_data_from_address (&inst, operand1);
3550 /* Calculate the PC value after the instruction, i.e. where the
3551 breakpoint should be. The order of the udw_operands is vital. */
3552 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3554 /* If this is an autoincrement addressing mode, check if the increment
3556 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3558 /* Get the size field. */
3559 size = cris_get_size (inst);
3561 /* If it's an extend instruction we don't want the signed extend bit,
3562 because it influences the size. */
3563 if (cris_get_opcode (inst) < 4)
3565 size &= ~SIGNED_EXTEND_BIT_MASK;
3567 process_autoincrement (size, inst, inst_env);
3569 inst_env->slot_needed = 0;
3570 inst_env->prefix_found = 0;
3571 inst_env->xflag_found = 0;
3572 inst_env->disable_interrupt = 0;
3575 /* Handles the two-operand addressing mode, all modes except register, for
3576 the ADD, SUB CMP, AND and OR instruction. */
3579 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3580 inst_env_type *inst_env)
3582 if (inst_env->prefix_found)
3584 if (cris_get_mode (inst) == PREFIX_INDEX_MODE)
3586 handle_prefix_index_mode_for_aritm_op (inst, inst_env);
3588 else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
3590 handle_prefix_assign_mode_for_aritm_op (inst, inst_env);
3594 /* The mode is invalid for a prefixed base instruction. */
3595 inst_env->invalid = 1;
3601 handle_inc_and_index_mode_for_aritm_op (inst, inst_env);
3605 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3608 quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env)
3610 unsigned long operand1;
3611 unsigned long operand2;
3613 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3614 instruction and can't have a prefix. */
3615 if (inst_env->prefix_found)
3617 inst_env->invalid = 1;
3621 /* Check if the instruction has PC as its target. */
3622 if (cris_get_operand2 (inst) == REG_PC)
3624 if (inst_env->slot_needed)
3626 inst_env->invalid = 1;
3629 operand1 = cris_get_quick_value (inst);
3630 operand2 = inst_env->reg[REG_PC];
3632 /* The size should now be dword. */
3633 cris_set_size_to_dword (&inst);
3635 /* Calculate the PC value after the instruction, i.e. where the
3636 breakpoint should be. */
3637 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3639 inst_env->slot_needed = 0;
3640 inst_env->prefix_found = 0;
3641 inst_env->xflag_found = 0;
3642 inst_env->disable_interrupt = 0;
3645 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3648 quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env)
3650 unsigned long operand1;
3651 unsigned long operand2;
3653 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3654 instruction and can't have a prefix. */
3655 if (inst_env->prefix_found)
3657 inst_env->invalid = 1;
3660 /* Check if the instruction has PC as its target. */
3661 if (cris_get_operand2 (inst) == REG_PC)
3663 if (inst_env->slot_needed)
3665 inst_env->invalid = 1;
3668 /* The instruction has the PC as its target register. */
3669 operand1 = cris_get_quick_value (inst);
3670 operand2 = inst_env->reg[REG_PC];
3672 /* The quick value is signed, so check if we must do a signed extend. */
3673 if (operand1 & SIGNED_QUICK_VALUE_MASK)
3676 operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK;
3678 /* The size should now be dword. */
3679 cris_set_size_to_dword (&inst);
3681 /* Calculate the PC value after the instruction, i.e. where the
3682 breakpoint should be. */
3683 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3685 inst_env->slot_needed = 0;
3686 inst_env->prefix_found = 0;
3687 inst_env->xflag_found = 0;
3688 inst_env->disable_interrupt = 0;
3691 /* Translate op_type to a function and call it. */
3694 cris_gdb_func (enum cris_op_type op_type, unsigned short inst,
3695 inst_env_type *inst_env)
3699 case cris_not_implemented_op:
3700 not_implemented_op (inst, inst_env);
3704 abs_op (inst, inst_env);
3708 addi_op (inst, inst_env);
3712 asr_op (inst, inst_env);
3716 asrq_op (inst, inst_env);
3719 case cris_ax_ei_setf_op:
3720 ax_ei_setf_op (inst, inst_env);
3723 case cris_bdap_prefix:
3724 bdap_prefix (inst, inst_env);
3727 case cris_biap_prefix:
3728 biap_prefix (inst, inst_env);
3732 break_op (inst, inst_env);
3735 case cris_btst_nop_op:
3736 btst_nop_op (inst, inst_env);
3739 case cris_clearf_di_op:
3740 clearf_di_op (inst, inst_env);
3743 case cris_dip_prefix:
3744 dip_prefix (inst, inst_env);
3747 case cris_dstep_logshift_mstep_neg_not_op:
3748 dstep_logshift_mstep_neg_not_op (inst, inst_env);
3751 case cris_eight_bit_offset_branch_op:
3752 eight_bit_offset_branch_op (inst, inst_env);
3755 case cris_move_mem_to_reg_movem_op:
3756 move_mem_to_reg_movem_op (inst, inst_env);
3759 case cris_move_reg_to_mem_movem_op:
3760 move_reg_to_mem_movem_op (inst, inst_env);
3763 case cris_move_to_preg_op:
3764 move_to_preg_op (inst, inst_env);
3768 muls_op (inst, inst_env);
3772 mulu_op (inst, inst_env);
3775 case cris_none_reg_mode_add_sub_cmp_and_or_move_op:
3776 none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3779 case cris_none_reg_mode_clear_test_op:
3780 none_reg_mode_clear_test_op (inst, inst_env);
3783 case cris_none_reg_mode_jump_op:
3784 none_reg_mode_jump_op (inst, inst_env);
3787 case cris_none_reg_mode_move_from_preg_op:
3788 none_reg_mode_move_from_preg_op (inst, inst_env);
3791 case cris_quick_mode_add_sub_op:
3792 quick_mode_add_sub_op (inst, inst_env);
3795 case cris_quick_mode_and_cmp_move_or_op:
3796 quick_mode_and_cmp_move_or_op (inst, inst_env);
3799 case cris_quick_mode_bdap_prefix:
3800 quick_mode_bdap_prefix (inst, inst_env);
3803 case cris_reg_mode_add_sub_cmp_and_or_move_op:
3804 reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3807 case cris_reg_mode_clear_op:
3808 reg_mode_clear_op (inst, inst_env);
3811 case cris_reg_mode_jump_op:
3812 reg_mode_jump_op (inst, inst_env);
3815 case cris_reg_mode_move_from_preg_op:
3816 reg_mode_move_from_preg_op (inst, inst_env);
3819 case cris_reg_mode_test_op:
3820 reg_mode_test_op (inst, inst_env);
3824 scc_op (inst, inst_env);
3827 case cris_sixteen_bit_offset_branch_op:
3828 sixteen_bit_offset_branch_op (inst, inst_env);
3831 case cris_three_operand_add_sub_cmp_and_or_op:
3832 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3835 case cris_three_operand_bound_op:
3836 three_operand_bound_op (inst, inst_env);
3839 case cris_two_operand_bound_op:
3840 two_operand_bound_op (inst, inst_env);
3844 xor_op (inst, inst_env);
3849 /* This wrapper is to avoid cris_get_assembler being called before
3850 exec_bfd has been set. */
3853 cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info)
3855 int (*print_insn) (bfd_vma addr, struct disassemble_info *info);
3856 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3857 disassembler, even when there is no BFD. Does something like
3858 "gdb; target remote; disassmeble *0x123" work? */
3859 gdb_assert (exec_bfd != NULL);
3860 print_insn = cris_get_disassembler (exec_bfd);
3861 gdb_assert (print_insn != NULL);
3862 return print_insn (addr, info);
3865 /* Copied from <asm/elf.h>. */
3866 typedef unsigned long elf_greg_t;
3868 /* Same as user_regs_struct struct in <asm/user.h>. */
3869 #define CRISV10_ELF_NGREG 35
3870 typedef elf_greg_t elf_gregset_t[CRISV10_ELF_NGREG];
3872 #define CRISV32_ELF_NGREG 32
3873 typedef elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG];
3875 /* Unpack an elf_gregset_t into GDB's register cache. */
3878 supply_gregset (elf_gregset_t *gregsetp)
3880 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3882 elf_greg_t *regp = *gregsetp;
3883 static char zerobuf[4] = {0};
3885 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3886 knows about the actual size of each register so that's no problem. */
3887 for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++)
3889 regcache_raw_supply (current_regcache, i, (char *)®p[i]);
3892 if (tdep->cris_version == 32)
3894 /* Needed to set pseudo-register PC for CRISv32. */
3895 /* FIXME: If ERP is in a delay slot at this point then the PC will
3896 be wrong. Issue a warning to alert the user. */
3897 regcache_raw_supply (current_regcache, PC_REGNUM,
3898 (char *)®p[ERP_REGNUM]);
3900 if (*(char *)®p[ERP_REGNUM] & 0x1)
3901 fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n");
3905 /* Use a local version of this function to get the correct types for
3906 regsets, until multi-arch core support is ready. */
3909 fetch_core_registers (char *core_reg_sect, unsigned core_reg_size,
3910 int which, CORE_ADDR reg_addr)
3912 elf_gregset_t gregset;
3917 if (core_reg_size != sizeof (elf_gregset_t)
3918 && core_reg_size != sizeof (crisv32_elf_gregset_t))
3920 warning (_("wrong size gregset struct in core file"));
3924 memcpy (&gregset, core_reg_sect, sizeof (gregset));
3925 supply_gregset (&gregset);
3929 /* We've covered all the kinds of registers we know about here,
3930 so this must be something we wouldn't know what to do with
3931 anyway. Just ignore it. */
3936 static struct core_fns cris_elf_core_fns =
3938 bfd_target_elf_flavour, /* core_flavour */
3939 default_check_format, /* check_format */
3940 default_core_sniffer, /* core_sniffer */
3941 fetch_core_registers, /* core_read_registers */
3945 extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */
3948 _initialize_cris_tdep (void)
3950 static struct cmd_list_element *cris_set_cmdlist;
3951 static struct cmd_list_element *cris_show_cmdlist;
3953 struct cmd_list_element *c;
3955 gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep);
3957 /* CRIS-specific user-commands. */
3958 add_setshow_uinteger_cmd ("cris-version", class_support,
3959 &usr_cmd_cris_version,
3960 _("Set the current CRIS version."),
3961 _("Show the current CRIS version."),
3963 Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\
3966 NULL, /* FIXME: i18n: Current CRIS version is %s. */
3967 &setlist, &showlist);
3969 add_setshow_enum_cmd ("cris-mode", class_support,
3970 cris_modes, &usr_cmd_cris_mode,
3971 _("Set the current CRIS mode."),
3972 _("Show the current CRIS mode."),
3974 Set to CRIS_MODE_GURU when debugging in guru mode.\n\
3975 Makes GDB use the NRP register instead of the ERP register in certain cases."),
3977 NULL, /* FIXME: i18n: Current CRIS version is %s. */
3978 &setlist, &showlist);
3980 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support,
3981 &usr_cmd_cris_dwarf2_cfi,
3982 _("Set the usage of Dwarf-2 CFI for CRIS."),
3983 _("Show the usage of Dwarf-2 CFI for CRIS."),
3984 _("Set this to \"off\" if using gcc-cris < R59."),
3985 set_cris_dwarf2_cfi,
3986 NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI for CRIS is %d. */
3987 &setlist, &showlist);
3989 deprecated_add_core_fns (&cris_elf_core_fns);
3992 /* Prints out all target specific values. */
3995 cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3997 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4000 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n",
4001 tdep->cris_version);
4002 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n",
4004 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
4005 tdep->cris_dwarf2_cfi);
4010 set_cris_version (char *ignore_args, int from_tty,
4011 struct cmd_list_element *c)
4013 struct gdbarch_info info;
4015 usr_cmd_cris_version_valid = 1;
4017 /* Update the current architecture, if needed. */
4018 gdbarch_info_init (&info);
4019 if (!gdbarch_update_p (info))
4020 internal_error (__FILE__, __LINE__,
4021 _("cris_gdbarch_update: failed to update architecture."));
4025 set_cris_mode (char *ignore_args, int from_tty,
4026 struct cmd_list_element *c)
4028 struct gdbarch_info info;
4030 /* Update the current architecture, if needed. */
4031 gdbarch_info_init (&info);
4032 if (!gdbarch_update_p (info))
4033 internal_error (__FILE__, __LINE__,
4034 "cris_gdbarch_update: failed to update architecture.");
4038 set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
4039 struct cmd_list_element *c)
4041 struct gdbarch_info info;
4043 /* Update the current architecture, if needed. */
4044 gdbarch_info_init (&info);
4045 if (!gdbarch_update_p (info))
4046 internal_error (__FILE__, __LINE__,
4047 _("cris_gdbarch_update: failed to update architecture."));
4050 static struct gdbarch *
4051 cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
4053 struct gdbarch *gdbarch;
4054 struct gdbarch_tdep *tdep;
4057 if (usr_cmd_cris_version_valid)
4059 /* Trust the user's CRIS version setting. */
4060 cris_version = usr_cmd_cris_version;
4062 else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32)
4068 /* Assume it's CRIS version 10. */
4072 /* Make the current settings visible to the user. */
4073 usr_cmd_cris_version = cris_version;
4075 /* Find a candidate among the list of pre-declared architectures. */
4076 for (arches = gdbarch_list_lookup_by_info (arches, &info);
4078 arches = gdbarch_list_lookup_by_info (arches->next, &info))
4080 if ((gdbarch_tdep (arches->gdbarch)->cris_version
4081 == usr_cmd_cris_version)
4082 && (gdbarch_tdep (arches->gdbarch)->cris_mode
4083 == usr_cmd_cris_mode)
4084 && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi
4085 == usr_cmd_cris_dwarf2_cfi))
4086 return arches->gdbarch;
4089 /* No matching architecture was found. Create a new one. */
4090 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
4091 gdbarch = gdbarch_alloc (&info, tdep);
4093 tdep->cris_version = usr_cmd_cris_version;
4094 tdep->cris_mode = usr_cmd_cris_mode;
4095 tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi;
4097 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
4098 switch (info.byte_order)
4100 case BFD_ENDIAN_LITTLE:
4104 case BFD_ENDIAN_BIG:
4105 internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: big endian byte order in info"));
4109 internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: unknown byte order in info"));
4112 set_gdbarch_return_value (gdbarch, cris_return_value);
4113 set_gdbarch_deprecated_reg_struct_has_addr (gdbarch,
4114 cris_reg_struct_has_addr);
4115 set_gdbarch_deprecated_use_struct_convention (gdbarch, always_use_struct_convention);
4117 set_gdbarch_sp_regnum (gdbarch, 14);
4119 /* Length of ordinary registers used in push_word and a few other
4120 places. register_size() is the real way to know how big a
4123 set_gdbarch_double_bit (gdbarch, 64);
4124 /* The default definition of a long double is 2 * TARGET_DOUBLE_BIT,
4125 which means we have to set this explicitly. */
4126 set_gdbarch_long_double_bit (gdbarch, 64);
4128 /* The total amount of space needed to store (in an array called registers)
4129 GDB's copy of the machine's register state. Note: We can not use
4130 cris_register_size at this point, since it relies on current_gdbarch
4132 switch (tdep->cris_version)
4140 /* Old versions; not supported. */
4141 internal_error (__FILE__, __LINE__,
4142 _("cris_gdbarch_init: unsupported CRIS version"));
4147 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
4148 P7 (32 bits), and P15 (32 bits) have been implemented. */
4149 set_gdbarch_pc_regnum (gdbarch, 15);
4150 set_gdbarch_register_type (gdbarch, cris_register_type);
4151 /* There are 32 registers (some of which may not be implemented). */
4152 set_gdbarch_num_regs (gdbarch, 32);
4153 set_gdbarch_register_name (gdbarch, cris_register_name);
4154 set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register);
4155 set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register);
4157 set_gdbarch_software_single_step (gdbarch, cris_software_single_step);
4161 /* CRIS v32. General registers R0 - R15 (32 bits), special registers
4162 P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
4163 and pseudo-register PC (32 bits). */
4164 set_gdbarch_pc_regnum (gdbarch, 32);
4165 set_gdbarch_register_type (gdbarch, crisv32_register_type);
4166 /* 32 registers + pseudo-register PC + 16 support registers. */
4167 set_gdbarch_num_regs (gdbarch, 32 + 1 + 16);
4168 set_gdbarch_register_name (gdbarch, crisv32_register_name);
4170 set_gdbarch_cannot_store_register
4171 (gdbarch, crisv32_cannot_store_register);
4172 set_gdbarch_cannot_fetch_register
4173 (gdbarch, crisv32_cannot_fetch_register);
4175 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
4177 set_gdbarch_single_step_through_delay
4178 (gdbarch, crisv32_single_step_through_delay);
4183 internal_error (__FILE__, __LINE__,
4184 _("cris_gdbarch_init: unknown CRIS version"));
4187 /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
4188 have the same ABI). */
4189 set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code);
4190 set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call);
4191 set_gdbarch_frame_align (gdbarch, cris_frame_align);
4192 set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue);
4194 /* The stack grows downward. */
4195 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4197 set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc);
4199 set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc);
4200 set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp);
4201 set_gdbarch_unwind_dummy_id (gdbarch, cris_unwind_dummy_id);
4203 if (tdep->cris_dwarf2_cfi == 1)
4205 /* Hook in the Dwarf-2 frame sniffer. */
4206 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum);
4207 dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg);
4208 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
4211 if (tdep->cris_mode != cris_mode_guru)
4213 frame_unwind_append_sniffer (gdbarch, cris_sigtramp_frame_sniffer);
4216 frame_unwind_append_sniffer (gdbarch, cris_frame_sniffer);
4217 frame_base_set_default (gdbarch, &cris_frame_base);
4219 set_solib_svr4_fetch_link_map_offsets
4220 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
4222 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
4223 disassembler, even when there is no BFD. Does something like
4224 "gdb; target remote; disassmeble *0x123" work? */
4225 set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler);