1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 Contributed by Axis Communications AB.
7 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "frame-unwind.h"
27 #include "frame-base.h"
28 #include "trad-frame.h"
29 #include "dwarf2-frame.h"
37 #include "opcode/cris.h"
38 #include "arch-utils.h"
40 #include "gdb_assert.h"
44 #include "solib.h" /* Support for shared libraries. */
45 #include "solib-svr4.h"
46 #include "gdb_string.h"
51 /* There are no floating point registers. Used in gdbserver low-linux.c. */
54 /* There are 16 general registers. */
57 /* There are 16 special registers. */
60 /* CRISv32 has a pseudo PC register, not noted here. */
62 /* CRISv32 has 16 support registers. */
66 /* Register numbers of various important registers.
67 CRIS_FP_REGNUM Contains address of executing stack frame.
68 STR_REGNUM Contains the address of structure return values.
69 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
70 ARG1_REGNUM Contains the first parameter to a function.
71 ARG2_REGNUM Contains the second parameter to a function.
72 ARG3_REGNUM Contains the third parameter to a function.
73 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
74 gdbarch_sp_regnum Contains address of top of stack.
75 gdbarch_pc_regnum Contains address of next instruction.
76 SRP_REGNUM Subroutine return pointer register.
77 BRP_REGNUM Breakpoint return pointer register. */
81 /* Enums with respect to the general registers, valid for all
82 CRIS versions. The frame pointer is always in R8. */
84 /* ABI related registers. */
92 /* Registers which happen to be common. */
97 /* CRISv10 et. al. specific registers. */
109 /* CRISv32 specific registers. */
122 CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */
124 CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */
144 extern const struct cris_spec_reg cris_spec_regs[];
146 /* CRIS version, set via the user command 'set cris-version'. Affects
147 register names and sizes. */
148 static int usr_cmd_cris_version;
150 /* Indicates whether to trust the above variable. */
151 static int usr_cmd_cris_version_valid = 0;
153 static const char cris_mode_normal[] = "normal";
154 static const char cris_mode_guru[] = "guru";
155 static const char *cris_modes[] = {
161 /* CRIS mode, set via the user command 'set cris-mode'. Affects
162 type of break instruction among other things. */
163 static const char *usr_cmd_cris_mode = cris_mode_normal;
165 /* Whether to make use of Dwarf-2 CFI (default on). */
166 static int usr_cmd_cris_dwarf2_cfi = 1;
168 /* CRIS architecture specific information. */
172 const char *cris_mode;
176 /* Sigtramp identification code copied from i386-linux-tdep.c. */
178 #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
179 #define SIGTRAMP_OFFSET0 0
180 #define SIGTRAMP_INSN1 0xe93d /* break 13 */
181 #define SIGTRAMP_OFFSET1 4
183 static const unsigned short sigtramp_code[] =
185 SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */
186 SIGTRAMP_INSN1 /* break 13 */
189 #define SIGTRAMP_LEN (sizeof sigtramp_code)
191 /* Note: same length as normal sigtramp code. */
193 static const unsigned short rt_sigtramp_code[] =
195 SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */
196 SIGTRAMP_INSN1 /* break 13 */
199 /* If PC is in a sigtramp routine, return the address of the start of
200 the routine. Otherwise, return 0. */
203 cris_sigtramp_start (struct frame_info *this_frame)
205 CORE_ADDR pc = get_frame_pc (this_frame);
206 gdb_byte buf[SIGTRAMP_LEN];
208 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
211 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
213 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
216 pc -= SIGTRAMP_OFFSET1;
217 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
221 if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0)
227 /* If PC is in a RT sigtramp routine, return the address of the start of
228 the routine. Otherwise, return 0. */
231 cris_rt_sigtramp_start (struct frame_info *this_frame)
233 CORE_ADDR pc = get_frame_pc (this_frame);
234 gdb_byte buf[SIGTRAMP_LEN];
236 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
239 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
241 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
244 pc -= SIGTRAMP_OFFSET1;
245 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
249 if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0)
255 /* Assuming THIS_FRAME is a frame for a GNU/Linux sigtramp routine,
256 return the address of the associated sigcontext structure. */
259 cris_sigcontext_addr (struct frame_info *this_frame)
261 struct gdbarch *gdbarch = get_frame_arch (this_frame);
262 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
267 get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
268 sp = extract_unsigned_integer (buf, 4, byte_order);
270 /* Look for normal sigtramp frame first. */
271 pc = cris_sigtramp_start (this_frame);
274 /* struct signal_frame (arch/cris/kernel/signal.c) contains
275 struct sigcontext as its first member, meaning the SP points to
280 pc = cris_rt_sigtramp_start (this_frame);
283 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
284 a struct ucontext, which in turn contains a struct sigcontext.
286 4 + 4 + 128 to struct ucontext, then
287 4 + 4 + 12 to struct sigcontext. */
291 error (_("Couldn't recognize signal trampoline."));
295 struct cris_unwind_cache
297 /* The previous frame's inner most stack address. Used as this
298 frame ID's stack_addr. */
300 /* The frame's base, optionally used by the high-level debug info. */
303 /* How far the SP and r8 (FP) have been offset from the start of
304 the stack frame (as defined by the previous frame's stack
310 /* From old frame_extra_info struct. */
314 /* Table indicating the location of each and every register. */
315 struct trad_frame_saved_reg *saved_regs;
318 static struct cris_unwind_cache *
319 cris_sigtramp_frame_unwind_cache (struct frame_info *this_frame,
322 struct gdbarch *gdbarch = get_frame_arch (this_frame);
323 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
324 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
325 struct cris_unwind_cache *info;
333 return (*this_cache);
335 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
336 (*this_cache) = info;
337 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
339 /* Zero all fields. */
345 info->uses_frame = 0;
347 info->leaf_function = 0;
349 get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
350 info->base = extract_unsigned_integer (buf, 4, byte_order);
352 addr = cris_sigcontext_addr (this_frame);
354 /* Layout of the sigcontext struct:
357 unsigned long oldmask;
361 if (tdep->cris_version == 10)
363 /* R0 to R13 are stored in reverse order at offset (2 * 4) in
365 for (i = 0; i <= 13; i++)
366 info->saved_regs[i].addr = addr + ((15 - i) * 4);
368 info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4);
369 info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4);
370 info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4);
371 /* Note: IRP is off by 2 at this point. There's no point in correcting
372 it though since that will mean that the backtrace will show a PC
373 different from what is shown when stopped. */
374 info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4);
375 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
376 = info->saved_regs[IRP_REGNUM];
377 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr = addr + (24 * 4);
382 /* R0 to R13 are stored in order at offset (1 * 4) in
384 for (i = 0; i <= 13; i++)
385 info->saved_regs[i].addr = addr + ((i + 1) * 4);
387 info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4);
388 info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4);
389 info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4);
390 info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4);
391 info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4);
392 info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4);
393 info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4);
394 info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4);
395 info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4);
397 /* FIXME: If ERP is in a delay slot at this point then the PC will
398 be wrong at this point. This problem manifests itself in the
399 sigaltstack.exp test case, which occasionally generates FAILs when
400 the signal is received while in a delay slot.
402 This could be solved by a couple of read_memory_unsigned_integer and a
403 trad_frame_set_value. */
404 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
405 = info->saved_regs[ERP_REGNUM];
407 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr
415 cris_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
416 struct frame_id *this_id)
418 struct cris_unwind_cache *cache =
419 cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
420 (*this_id) = frame_id_build (cache->base, get_frame_pc (this_frame));
423 /* Forward declaration. */
425 static struct value *cris_frame_prev_register (struct frame_info *this_frame,
426 void **this_cache, int regnum);
427 static struct value *
428 cris_sigtramp_frame_prev_register (struct frame_info *this_frame,
429 void **this_cache, int regnum)
431 /* Make sure we've initialized the cache. */
432 cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
433 return cris_frame_prev_register (this_frame, this_cache, regnum);
437 cris_sigtramp_frame_sniffer (const struct frame_unwind *self,
438 struct frame_info *this_frame,
441 if (cris_sigtramp_start (this_frame)
442 || cris_rt_sigtramp_start (this_frame))
448 static const struct frame_unwind cris_sigtramp_frame_unwind =
451 cris_sigtramp_frame_this_id,
452 cris_sigtramp_frame_prev_register,
454 cris_sigtramp_frame_sniffer
458 crisv32_single_step_through_delay (struct gdbarch *gdbarch,
459 struct frame_info *this_frame)
461 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
465 if (tdep->cris_mode == cris_mode_guru)
466 erp = get_frame_register_unsigned (this_frame, NRP_REGNUM);
468 erp = get_frame_register_unsigned (this_frame, ERP_REGNUM);
472 /* In delay slot - check if there's a breakpoint at the preceding
474 if (breakpoint_here_p (erp & ~0x1))
480 /* Hardware watchpoint support. */
482 /* We support 6 hardware data watchpoints, but cannot trigger on execute
483 (any combination of read/write is fine). */
486 cris_can_use_hardware_watchpoint (int type, int count, int other)
488 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
490 /* No bookkeeping is done here; it is handled by the remote debug agent. */
492 if (tdep->cris_version != 32)
495 /* CRISv32: Six data watchpoints, one for instructions. */
496 return (((type == bp_read_watchpoint || type == bp_access_watchpoint
497 || type == bp_hardware_watchpoint) && count <= 6)
498 || (type == bp_hardware_breakpoint && count <= 1));
501 /* The CRISv32 hardware data watchpoints work by specifying ranges,
502 which have no alignment or length restrictions. */
505 cris_region_ok_for_watchpoint (CORE_ADDR addr, int len)
510 /* If the inferior has some watchpoint that triggered, return the
511 address associated with that watchpoint. Otherwise, return
515 cris_stopped_data_address (void)
518 eda = get_frame_register_unsigned (get_current_frame (), EDA_REGNUM);
522 /* The instruction environment needed to find single-step breakpoints. */
525 struct instruction_environment
527 unsigned long reg[NUM_GENREGS];
528 unsigned long preg[NUM_SPECREGS];
529 unsigned long branch_break_address;
530 unsigned long delay_slot_pc;
531 unsigned long prefix_value;
536 int delay_slot_pc_active;
538 int disable_interrupt;
542 /* Machine-dependencies in CRIS for opcodes. */
544 /* Instruction sizes. */
545 enum cris_instruction_sizes
552 /* Addressing modes. */
553 enum cris_addressing_modes
560 /* Prefix addressing modes. */
561 enum cris_prefix_addressing_modes
563 PREFIX_INDEX_MODE = 2,
564 PREFIX_ASSIGN_MODE = 3,
566 /* Handle immediate byte offset addressing mode prefix format. */
567 PREFIX_OFFSET_MODE = 2
570 /* Masks for opcodes. */
571 enum cris_opcode_masks
573 BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1,
574 SIGNED_EXTEND_BIT_MASK = 0x2,
575 SIGNED_BYTE_MASK = 0x80,
576 SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00,
577 SIGNED_WORD_MASK = 0x8000,
578 SIGNED_WORD_EXTEND_MASK = 0xFFFF0000,
579 SIGNED_DWORD_MASK = 0x80000000,
580 SIGNED_QUICK_VALUE_MASK = 0x20,
581 SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0
584 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
592 cris_get_operand2 (unsigned short insn)
594 return ((insn & 0xF000) >> 12);
598 cris_get_mode (unsigned short insn)
600 return ((insn & 0x0C00) >> 10);
604 cris_get_opcode (unsigned short insn)
606 return ((insn & 0x03C0) >> 6);
610 cris_get_size (unsigned short insn)
612 return ((insn & 0x0030) >> 4);
616 cris_get_operand1 (unsigned short insn)
618 return (insn & 0x000F);
621 /* Additional functions in order to handle opcodes. */
624 cris_get_quick_value (unsigned short insn)
626 return (insn & 0x003F);
630 cris_get_bdap_quick_offset (unsigned short insn)
632 return (insn & 0x00FF);
636 cris_get_branch_short_offset (unsigned short insn)
638 return (insn & 0x00FF);
642 cris_get_asr_shift_steps (unsigned long value)
644 return (value & 0x3F);
648 cris_get_clear_size (unsigned short insn)
650 return ((insn) & 0xC000);
654 cris_is_signed_extend_bit_on (unsigned short insn)
656 return (((insn) & 0x20) == 0x20);
660 cris_is_xflag_bit_on (unsigned short insn)
662 return (((insn) & 0x1000) == 0x1000);
666 cris_set_size_to_dword (unsigned short *insn)
673 cris_get_signed_offset (unsigned short insn)
675 return ((signed char) (insn & 0x00FF));
678 /* Calls an op function given the op-type, working on the insn and the
680 static void cris_gdb_func (struct gdbarch *, enum cris_op_type, unsigned short,
683 static struct gdbarch *cris_gdbarch_init (struct gdbarch_info,
684 struct gdbarch_list *);
686 static void cris_dump_tdep (struct gdbarch *, struct ui_file *);
688 static void set_cris_version (char *ignore_args, int from_tty,
689 struct cmd_list_element *c);
691 static void set_cris_mode (char *ignore_args, int from_tty,
692 struct cmd_list_element *c);
694 static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
695 struct cmd_list_element *c);
697 static CORE_ADDR cris_scan_prologue (CORE_ADDR pc,
698 struct frame_info *this_frame,
699 struct cris_unwind_cache *info);
701 static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc,
702 struct frame_info *this_frame,
703 struct cris_unwind_cache *info);
705 static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch,
706 struct frame_info *next_frame);
708 static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch,
709 struct frame_info *next_frame);
711 /* When arguments must be pushed onto the stack, they go on in reverse
712 order. The below implements a FILO (stack) to do this.
713 Copied from d10v-tdep.c. */
718 struct stack_item *prev;
722 static struct stack_item *
723 push_stack_item (struct stack_item *prev, void *contents, int len)
725 struct stack_item *si;
726 si = xmalloc (sizeof (struct stack_item));
727 si->data = xmalloc (len);
730 memcpy (si->data, contents, len);
734 static struct stack_item *
735 pop_stack_item (struct stack_item *si)
737 struct stack_item *dead = si;
744 /* Put here the code to store, into fi->saved_regs, the addresses of
745 the saved registers of frame described by FRAME_INFO. This
746 includes special registers such as pc and fp saved in special ways
747 in the stack frame. sp is even more special: the address we return
748 for it IS the sp for the next frame. */
750 static struct cris_unwind_cache *
751 cris_frame_unwind_cache (struct frame_info *this_frame,
752 void **this_prologue_cache)
754 struct gdbarch *gdbarch = get_frame_arch (this_frame);
755 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
757 struct cris_unwind_cache *info;
760 if ((*this_prologue_cache))
761 return (*this_prologue_cache);
763 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
764 (*this_prologue_cache) = info;
765 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
767 /* Zero all fields. */
773 info->uses_frame = 0;
775 info->leaf_function = 0;
777 /* Prologue analysis does the rest... */
778 if (tdep->cris_version == 32)
779 crisv32_scan_prologue (get_frame_func (this_frame), this_frame, info);
781 cris_scan_prologue (get_frame_func (this_frame), this_frame, info);
786 /* Given a GDB frame, determine the address of the calling function's
787 frame. This will be used to create a new GDB frame struct. */
790 cris_frame_this_id (struct frame_info *this_frame,
791 void **this_prologue_cache,
792 struct frame_id *this_id)
794 struct cris_unwind_cache *info
795 = cris_frame_unwind_cache (this_frame, this_prologue_cache);
800 /* The FUNC is easy. */
801 func = get_frame_func (this_frame);
803 /* Hopefully the prologue analysis either correctly determined the
804 frame's base (which is the SP from the previous frame), or set
805 that base to "NULL". */
806 base = info->prev_sp;
810 id = frame_id_build (base, func);
815 static struct value *
816 cris_frame_prev_register (struct frame_info *this_frame,
817 void **this_prologue_cache, int regnum)
819 struct cris_unwind_cache *info
820 = cris_frame_unwind_cache (this_frame, this_prologue_cache);
821 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
824 /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
825 frame. The frame ID's base needs to match the TOS value saved by
826 save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */
828 static struct frame_id
829 cris_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
832 sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
833 return frame_id_build (sp, get_frame_pc (this_frame));
837 cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
839 /* Align to the size of an instruction (so that they can safely be
840 pushed onto the stack). */
845 cris_push_dummy_code (struct gdbarch *gdbarch,
846 CORE_ADDR sp, CORE_ADDR funaddr,
847 struct value **args, int nargs,
848 struct type *value_type,
849 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
850 struct regcache *regcache)
852 /* Allocate space sufficient for a breakpoint. */
854 /* Store the address of that breakpoint */
856 /* CRIS always starts the call at the callee's entry point. */
862 cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
863 struct regcache *regcache, CORE_ADDR bp_addr,
864 int nargs, struct value **args, CORE_ADDR sp,
865 int struct_return, CORE_ADDR struct_addr)
867 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
875 /* The function's arguments and memory allocated by gdb for the arguments to
876 point at reside in separate areas on the stack.
877 Both frame pointers grow toward higher addresses. */
881 struct stack_item *si = NULL;
883 /* Push the return address. */
884 regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr);
886 /* Are we returning a value using a structure return or a normal value
887 return? struct_addr is the address of the reserved space for the return
888 structure to be written on the stack. */
891 regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr);
894 /* Now load as many as possible of the first arguments into registers,
895 and push the rest onto the stack. */
896 argreg = ARG1_REGNUM;
899 for (argnum = 0; argnum < nargs; argnum++)
906 len = TYPE_LENGTH (value_type (args[argnum]));
907 val = (char *) value_contents (args[argnum]);
909 /* How may registers worth of storage do we need for this argument? */
910 reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0);
912 if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM))
914 /* Data passed by value. Fits in available register(s). */
915 for (i = 0; i < reg_demand; i++)
917 regcache_cooked_write (regcache, argreg, val);
922 else if (len <= (2 * 4) && argreg <= ARG4_REGNUM)
924 /* Data passed by value. Does not fit in available register(s).
925 Use the register(s) first, then the stack. */
926 for (i = 0; i < reg_demand; i++)
928 if (argreg <= ARG4_REGNUM)
930 regcache_cooked_write (regcache, argreg, val);
936 /* Push item for later so that pushed arguments
937 come in the right order. */
938 si = push_stack_item (si, val, 4);
943 else if (len > (2 * 4))
945 /* Data passed by reference. Push copy of data onto stack
946 and pass pointer to this copy as argument. */
947 sp = (sp - len) & ~3;
948 write_memory (sp, val, len);
950 if (argreg <= ARG4_REGNUM)
952 regcache_cooked_write_unsigned (regcache, argreg, sp);
958 store_unsigned_integer (buf, 4, byte_order, sp);
959 si = push_stack_item (si, buf, 4);
964 /* Data passed by value. No available registers. Put it on
966 si = push_stack_item (si, val, len);
972 /* fp_arg must be word-aligned (i.e., don't += len) to match
973 the function prologue. */
974 sp = (sp - si->len) & ~3;
975 write_memory (sp, si->data, si->len);
976 si = pop_stack_item (si);
979 /* Finally, update the SP register. */
980 regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp);
985 static const struct frame_unwind cris_frame_unwind =
989 cris_frame_prev_register,
991 default_frame_sniffer
995 cris_frame_base_address (struct frame_info *this_frame, void **this_cache)
997 struct cris_unwind_cache *info
998 = cris_frame_unwind_cache (this_frame, this_cache);
1002 static const struct frame_base cris_frame_base =
1005 cris_frame_base_address,
1006 cris_frame_base_address,
1007 cris_frame_base_address
1010 /* Frames information. The definition of the struct frame_info is
1014 enum frame_type type;
1018 If the compilation option -fno-omit-frame-pointer is present the
1019 variable frame will be set to the content of R8 which is the frame
1022 The variable pc contains the address where execution is performed
1023 in the present frame. The innermost frame contains the current content
1024 of the register PC. All other frames contain the content of the
1025 register PC in the next frame.
1027 The variable `type' indicates the frame's type: normal, SIGTRAMP
1028 (associated with a signal handler), dummy (associated with a dummy
1031 The variable return_pc contains the address where execution should be
1032 resumed when the present frame has finished, the return address.
1034 The variable leaf_function is 1 if the return address is in the register
1035 SRP, and 0 if it is on the stack.
1037 Prologue instructions C-code.
1038 The prologue may consist of (-fno-omit-frame-pointer)
1042 move.d sp,r8 move.d sp,r8
1044 movem rY,[sp] movem rY,[sp]
1045 move.S rZ,[r8-U] move.S rZ,[r8-U]
1047 where 1 is a non-terminal function, and 2 is a leaf-function.
1049 Note that this assumption is extremely brittle, and will break at the
1050 slightest change in GCC's prologue.
1052 If local variables are declared or register contents are saved on stack
1053 the subq-instruction will be present with X as the number of bytes
1054 needed for storage. The reshuffle with respect to r8 may be performed
1055 with any size S (b, w, d) and any of the general registers Z={0..13}.
1056 The offset U should be representable by a signed 8-bit value in all cases.
1057 Thus, the prefix word is assumed to be immediate byte offset mode followed
1058 by another word containing the instruction.
1067 Prologue instructions C++-code.
1068 Case 1) and 2) in the C-code may be followed by
1070 move.d r10,rS ; this
1074 move.S [r8+U],rZ ; P4
1076 if any of the call parameters are stored. The host expects these
1077 instructions to be executed in order to get the call parameters right. */
1079 /* Examine the prologue of a function. The variable ip is the address of
1080 the first instruction of the prologue. The variable limit is the address
1081 of the first instruction after the prologue. The variable fi contains the
1082 information in struct frame_info. The variable frameless_p controls whether
1083 the entire prologue is examined (0) or just enough instructions to
1084 determine that it is a prologue (1). */
1087 cris_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
1088 struct cris_unwind_cache *info)
1090 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1091 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1093 /* Present instruction. */
1094 unsigned short insn;
1096 /* Next instruction, lookahead. */
1097 unsigned short insn_next;
1100 /* Is there a push fp? */
1103 /* Number of byte on stack used for local variables and movem. */
1106 /* Highest register number in a movem. */
1109 /* move.d r<source_register>,rS */
1110 short source_register;
1115 /* This frame is with respect to a leaf until a push srp is found. */
1118 info->leaf_function = 1;
1121 /* Assume nothing on stack. */
1125 /* If we were called without a this_frame, that means we were called
1126 from cris_skip_prologue which already tried to find the end of the
1127 prologue through the symbol information. 64 instructions past current
1128 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
1129 limit = this_frame ? get_frame_pc (this_frame) : pc + 64;
1131 /* Find the prologue instructions. */
1132 while (pc > 0 && pc < limit)
1134 insn = read_memory_unsigned_integer (pc, 2, byte_order);
1138 /* push <reg> 32 bit instruction */
1139 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1141 regno = cris_get_operand2 (insn_next);
1144 info->sp_offset += 4;
1146 /* This check, meant to recognize srp, used to be regno ==
1147 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
1148 if (insn_next == 0xBE7E)
1152 info->leaf_function = 0;
1155 else if (insn_next == 0x8FEE)
1160 info->r8_offset = info->sp_offset;
1164 else if (insn == 0x866E)
1169 info->uses_frame = 1;
1173 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1174 && cris_get_mode (insn) == 0x0000
1175 && cris_get_opcode (insn) == 0x000A)
1180 info->sp_offset += cris_get_quick_value (insn);
1183 else if (cris_get_mode (insn) == 0x0002
1184 && cris_get_opcode (insn) == 0x000F
1185 && cris_get_size (insn) == 0x0003
1186 && cris_get_operand1 (insn) == gdbarch_sp_regnum (gdbarch))
1188 /* movem r<regsave>,[sp] */
1189 regsave = cris_get_operand2 (insn);
1191 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1192 && ((insn & 0x0F00) >> 8) == 0x0001
1193 && (cris_get_signed_offset (insn) < 0))
1195 /* Immediate byte offset addressing prefix word with sp as base
1196 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1197 is between 64 and 128.
1198 movem r<regsave>,[sp=sp-<val>] */
1201 info->sp_offset += -cris_get_signed_offset (insn);
1203 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1205 if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE
1206 && cris_get_opcode (insn_next) == 0x000F
1207 && cris_get_size (insn_next) == 0x0003
1208 && cris_get_operand1 (insn_next) == gdbarch_sp_regnum
1211 regsave = cris_get_operand2 (insn_next);
1215 /* The prologue ended before the limit was reached. */
1220 else if (cris_get_mode (insn) == 0x0001
1221 && cris_get_opcode (insn) == 0x0009
1222 && cris_get_size (insn) == 0x0002)
1224 /* move.d r<10..13>,r<0..15> */
1225 source_register = cris_get_operand1 (insn);
1227 /* FIXME? In the glibc solibs, the prologue might contain something
1228 like (this example taken from relocate_doit):
1230 sub.d 0xfffef426,$r0
1231 which isn't covered by the source_register check below. Question
1232 is whether to add a check for this combo, or make better use of
1233 the limit variable instead. */
1234 if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM)
1236 /* The prologue ended before the limit was reached. */
1241 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1242 /* The size is a fixed-size. */
1243 && ((insn & 0x0F00) >> 8) == 0x0001
1244 /* A negative offset. */
1245 && (cris_get_signed_offset (insn) < 0))
1247 /* move.S rZ,[r8-U] (?) */
1248 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1250 regno = cris_get_operand2 (insn_next);
1251 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1252 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1253 && cris_get_opcode (insn_next) == 0x000F)
1255 /* move.S rZ,[r8-U] */
1260 /* The prologue ended before the limit was reached. */
1265 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1266 /* The size is a fixed-size. */
1267 && ((insn & 0x0F00) >> 8) == 0x0001
1268 /* A positive offset. */
1269 && (cris_get_signed_offset (insn) > 0))
1271 /* move.S [r8+U],rZ (?) */
1272 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1274 regno = cris_get_operand2 (insn_next);
1275 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1276 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1277 && cris_get_opcode (insn_next) == 0x0009
1278 && cris_get_operand1 (insn_next) == regno)
1280 /* move.S [r8+U],rZ */
1285 /* The prologue ended before the limit was reached. */
1292 /* The prologue ended before the limit was reached. */
1298 /* We only want to know the end of the prologue when this_frame and info
1299 are NULL (called from cris_skip_prologue i.e.). */
1300 if (this_frame == NULL && info == NULL)
1305 info->size = info->sp_offset;
1307 /* Compute the previous frame's stack pointer (which is also the
1308 frame's ID's stack address), and this frame's base pointer. */
1309 if (info->uses_frame)
1312 /* The SP was moved to the FP. This indicates that a new frame
1313 was created. Get THIS frame's FP value by unwinding it from
1315 this_base = get_frame_register_unsigned (this_frame, CRIS_FP_REGNUM);
1316 info->base = this_base;
1317 info->saved_regs[CRIS_FP_REGNUM].addr = info->base;
1319 /* The FP points at the last saved register. Adjust the FP back
1320 to before the first saved register giving the SP. */
1321 info->prev_sp = info->base + info->r8_offset;
1326 /* Assume that the FP is this frame's SP but with that pushed
1327 stack space added back. */
1328 this_base = get_frame_register_unsigned (this_frame,
1329 gdbarch_sp_regnum (gdbarch));
1330 info->base = this_base;
1331 info->prev_sp = info->base + info->size;
1334 /* Calculate the addresses for the saved registers on the stack. */
1335 /* FIXME: The address calculation should really be done on the fly while
1336 we're analyzing the prologue (we only hold one regsave value as it is
1338 val = info->sp_offset;
1340 for (regno = regsave; regno >= 0; regno--)
1342 info->saved_regs[regno].addr = info->base + info->r8_offset - val;
1346 /* The previous frame's SP needed to be computed. Save the computed
1348 trad_frame_set_value (info->saved_regs,
1349 gdbarch_sp_regnum (gdbarch), info->prev_sp);
1351 if (!info->leaf_function)
1353 /* SRP saved on the stack. But where? */
1354 if (info->r8_offset == 0)
1356 /* R8 not pushed yet. */
1357 info->saved_regs[SRP_REGNUM].addr = info->base;
1361 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1362 info->saved_regs[SRP_REGNUM].addr = info->base + 4;
1366 /* The PC is found in SRP (the actual register or located on the stack). */
1367 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1368 = info->saved_regs[SRP_REGNUM];
1374 crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
1375 struct cris_unwind_cache *info)
1377 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1380 /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not
1381 meant to be a full-fledged prologue scanner. It is only needed for
1382 the cases where we end up in code always lacking DWARF-2 CFI, notably:
1384 * PLT stubs (library calls)
1386 * signal trampolines
1388 For those cases, it is assumed that there is no actual prologue; that
1389 the stack pointer is not adjusted, and (as a consequence) the return
1390 address is not pushed onto the stack. */
1392 /* We only want to know the end of the prologue when this_frame and info
1393 are NULL (called from cris_skip_prologue i.e.). */
1394 if (this_frame == NULL && info == NULL)
1399 /* The SP is assumed to be unaltered. */
1400 this_base = get_frame_register_unsigned (this_frame,
1401 gdbarch_sp_regnum (gdbarch));
1402 info->base = this_base;
1403 info->prev_sp = this_base;
1405 /* The PC is assumed to be found in SRP. */
1406 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1407 = info->saved_regs[SRP_REGNUM];
1412 /* Advance pc beyond any function entry prologue instructions at pc
1413 to reach some "real" code. */
1415 /* Given a PC value corresponding to the start of a function, return the PC
1416 of the first instruction after the function prologue. */
1419 cris_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1421 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1422 CORE_ADDR func_addr, func_end;
1423 struct symtab_and_line sal;
1424 CORE_ADDR pc_after_prologue;
1426 /* If we have line debugging information, then the end of the prologue
1427 should the first assembly instruction of the first source line. */
1428 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1430 sal = find_pc_line (func_addr, 0);
1431 if (sal.end > 0 && sal.end < func_end)
1435 if (tdep->cris_version == 32)
1436 pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL);
1438 pc_after_prologue = cris_scan_prologue (pc, NULL, NULL);
1440 return pc_after_prologue;
1444 cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1447 pc = frame_unwind_register_unsigned (next_frame,
1448 gdbarch_pc_regnum (gdbarch));
1453 cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1456 sp = frame_unwind_register_unsigned (next_frame,
1457 gdbarch_sp_regnum (gdbarch));
1461 /* Use the program counter to determine the contents and size of a breakpoint
1462 instruction. It returns a pointer to a string of bytes that encode a
1463 breakpoint instruction, stores the length of the string to *lenptr, and
1464 adjusts pcptr (if necessary) to point to the actual memory location where
1465 the breakpoint should be inserted. */
1467 static const unsigned char *
1468 cris_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
1470 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1471 static unsigned char break8_insn[] = {0x38, 0xe9};
1472 static unsigned char break15_insn[] = {0x3f, 0xe9};
1475 if (tdep->cris_mode == cris_mode_guru)
1476 return break15_insn;
1481 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1485 cris_spec_reg_applicable (struct gdbarch *gdbarch,
1486 struct cris_spec_reg spec_reg)
1488 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1489 int version = tdep->cris_version;
1491 switch (spec_reg.applicable_version)
1493 case cris_ver_version_all:
1495 case cris_ver_warning:
1496 /* Indeterminate/obsolete. */
1499 return (version >= 0 && version <= 3);
1501 return (version >= 3);
1503 return (version == 8 || version == 9);
1505 return (version >= 8);
1506 case cris_ver_v0_10:
1507 return (version >= 0 && version <= 10);
1508 case cris_ver_v3_10:
1509 return (version >= 3 && version <= 10);
1510 case cris_ver_v8_10:
1511 return (version >= 8 && version <= 10);
1513 return (version == 10);
1515 return (version >= 10);
1517 return (version >= 32);
1519 /* Invalid cris version. */
1524 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1525 register, -1 for an invalid register. */
1528 cris_register_size (struct gdbarch *gdbarch, int regno)
1530 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1534 if (regno >= 0 && regno < NUM_GENREGS)
1536 /* General registers (R0 - R15) are 32 bits. */
1539 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1541 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1542 Adjust regno accordingly. */
1543 spec_regno = regno - NUM_GENREGS;
1545 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1547 if (cris_spec_regs[i].number == spec_regno
1548 && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i]))
1549 /* Go with the first applicable register. */
1550 return cris_spec_regs[i].reg_size;
1552 /* Special register not applicable to this CRIS version. */
1555 else if (regno >= gdbarch_pc_regnum (gdbarch)
1556 && regno < gdbarch_num_regs (gdbarch))
1558 /* This will apply to CRISv32 only where there are additional registers
1559 after the special registers (pseudo PC and support registers). */
1567 /* Nonzero if regno should not be fetched from the target. This is the case
1568 for unimplemented (size 0) and non-existant registers. */
1571 cris_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1573 return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1574 || (cris_register_size (gdbarch, regno) == 0));
1577 /* Nonzero if regno should not be written to the target, for various
1581 cris_cannot_store_register (struct gdbarch *gdbarch, int regno)
1583 /* There are three kinds of registers we refuse to write to.
1584 1. Those that not implemented.
1585 2. Those that are read-only (depends on the processor mode).
1586 3. Those registers to which a write has no effect.
1590 || regno >= gdbarch_num_regs (gdbarch)
1591 || cris_register_size (gdbarch, regno) == 0)
1592 /* Not implemented. */
1595 else if (regno == VR_REGNUM)
1599 else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM)
1600 /* Writing has no effect. */
1603 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
1604 agent decide whether they are writable. */
1609 /* Nonzero if regno should not be fetched from the target. This is the case
1610 for unimplemented (size 0) and non-existant registers. */
1613 crisv32_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1615 return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1616 || (cris_register_size (gdbarch, regno) == 0));
1619 /* Nonzero if regno should not be written to the target, for various
1623 crisv32_cannot_store_register (struct gdbarch *gdbarch, int regno)
1625 /* There are three kinds of registers we refuse to write to.
1626 1. Those that not implemented.
1627 2. Those that are read-only (depends on the processor mode).
1628 3. Those registers to which a write has no effect.
1632 || regno >= gdbarch_num_regs (gdbarch)
1633 || cris_register_size (gdbarch, regno) == 0)
1634 /* Not implemented. */
1637 else if (regno == VR_REGNUM)
1641 else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM)
1642 /* Writing has no effect. */
1645 /* Many special registers are read-only in user mode. Let the debug
1646 agent decide whether they are writable. */
1651 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1652 of data in register regno. */
1654 static struct type *
1655 cris_register_type (struct gdbarch *gdbarch, int regno)
1657 if (regno == gdbarch_pc_regnum (gdbarch))
1658 return builtin_type (gdbarch)->builtin_func_ptr;
1659 else if (regno == gdbarch_sp_regnum (gdbarch)
1660 || regno == CRIS_FP_REGNUM)
1661 return builtin_type (gdbarch)->builtin_data_ptr;
1662 else if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1663 || (regno >= MOF_REGNUM && regno <= USP_REGNUM))
1664 /* Note: R8 taken care of previous clause. */
1665 return builtin_type (gdbarch)->builtin_uint32;
1666 else if (regno >= P4_REGNUM && regno <= CCR_REGNUM)
1667 return builtin_type (gdbarch)->builtin_uint16;
1668 else if (regno >= P0_REGNUM && regno <= VR_REGNUM)
1669 return builtin_type (gdbarch)->builtin_uint8;
1671 /* Invalid (unimplemented) register. */
1672 return builtin_type (gdbarch)->builtin_int0;
1675 static struct type *
1676 crisv32_register_type (struct gdbarch *gdbarch, int regno)
1678 if (regno == gdbarch_pc_regnum (gdbarch))
1679 return builtin_type (gdbarch)->builtin_func_ptr;
1680 else if (regno == gdbarch_sp_regnum (gdbarch)
1681 || regno == CRIS_FP_REGNUM)
1682 return builtin_type (gdbarch)->builtin_data_ptr;
1683 else if ((regno >= 0 && regno <= ACR_REGNUM)
1684 || (regno >= EXS_REGNUM && regno <= SPC_REGNUM)
1685 || (regno == PID_REGNUM)
1686 || (regno >= S0_REGNUM && regno <= S15_REGNUM))
1687 /* Note: R8 and SP taken care of by previous clause. */
1688 return builtin_type (gdbarch)->builtin_uint32;
1689 else if (regno == WZ_REGNUM)
1690 return builtin_type (gdbarch)->builtin_uint16;
1691 else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM)
1692 return builtin_type (gdbarch)->builtin_uint8;
1695 /* Invalid (unimplemented) register. Should not happen as there are
1696 no unimplemented CRISv32 registers. */
1697 warning (_("crisv32_register_type: unknown regno %d"), regno);
1698 return builtin_type (gdbarch)->builtin_int0;
1702 /* Stores a function return value of type type, where valbuf is the address
1703 of the value to be stored. */
1705 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1708 cris_store_return_value (struct type *type, struct regcache *regcache,
1711 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1712 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1714 int len = TYPE_LENGTH (type);
1718 /* Put the return value in R10. */
1719 val = extract_unsigned_integer (valbuf, len, byte_order);
1720 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1724 /* Put the return value in R10 and R11. */
1725 val = extract_unsigned_integer (valbuf, 4, byte_order);
1726 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1727 val = extract_unsigned_integer ((char *)valbuf + 4, len - 4, byte_order);
1728 regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val);
1731 error (_("cris_store_return_value: type length too large."));
1734 /* Return the name of register regno as a string. Return NULL for an invalid or
1735 unimplemented register. */
1738 cris_special_register_name (struct gdbarch *gdbarch, int regno)
1743 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1744 Adjust regno accordingly. */
1745 spec_regno = regno - NUM_GENREGS;
1747 /* Assume nothing about the layout of the cris_spec_regs struct
1749 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1751 if (cris_spec_regs[i].number == spec_regno
1752 && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i]))
1753 /* Go with the first applicable register. */
1754 return cris_spec_regs[i].name;
1756 /* Special register not applicable to this CRIS version. */
1761 cris_register_name (struct gdbarch *gdbarch, int regno)
1763 static char *cris_genreg_names[] =
1764 { "r0", "r1", "r2", "r3", \
1765 "r4", "r5", "r6", "r7", \
1766 "r8", "r9", "r10", "r11", \
1767 "r12", "r13", "sp", "pc" };
1769 if (regno >= 0 && regno < NUM_GENREGS)
1771 /* General register. */
1772 return cris_genreg_names[regno];
1774 else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (gdbarch))
1776 return cris_special_register_name (gdbarch, regno);
1780 /* Invalid register. */
1786 crisv32_register_name (struct gdbarch *gdbarch, int regno)
1788 static char *crisv32_genreg_names[] =
1789 { "r0", "r1", "r2", "r3", \
1790 "r4", "r5", "r6", "r7", \
1791 "r8", "r9", "r10", "r11", \
1792 "r12", "r13", "sp", "acr"
1795 static char *crisv32_sreg_names[] =
1796 { "s0", "s1", "s2", "s3", \
1797 "s4", "s5", "s6", "s7", \
1798 "s8", "s9", "s10", "s11", \
1799 "s12", "s13", "s14", "s15"
1802 if (regno >= 0 && regno < NUM_GENREGS)
1804 /* General register. */
1805 return crisv32_genreg_names[regno];
1807 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1809 return cris_special_register_name (gdbarch, regno);
1811 else if (regno == gdbarch_pc_regnum (gdbarch))
1815 else if (regno >= S0_REGNUM && regno <= S15_REGNUM)
1817 return crisv32_sreg_names[regno - S0_REGNUM];
1821 /* Invalid register. */
1826 /* Convert DWARF register number REG to the appropriate register
1827 number used by GDB. */
1830 cris_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1832 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1833 numbering, MOF is 18).
1834 Adapted from gcc/config/cris/cris.h. */
1835 static int cris_dwarf_regmap[] = {
1847 if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap))
1848 regnum = cris_dwarf_regmap[reg];
1851 warning (_("Unmapped DWARF Register #%d encountered."), reg);
1856 /* DWARF-2 frame support. */
1859 cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1860 struct dwarf2_frame_state_reg *reg,
1861 struct frame_info *this_frame)
1863 /* The return address column. */
1864 if (regnum == gdbarch_pc_regnum (gdbarch))
1865 reg->how = DWARF2_FRAME_REG_RA;
1867 /* The call frame address. */
1868 else if (regnum == gdbarch_sp_regnum (gdbarch))
1869 reg->how = DWARF2_FRAME_REG_CFA;
1872 /* Extract from an array regbuf containing the raw register state a function
1873 return value of type type, and copy that, in virtual format, into
1876 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1879 cris_extract_return_value (struct type *type, struct regcache *regcache,
1882 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1883 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1885 int len = TYPE_LENGTH (type);
1889 /* Get the return value from R10. */
1890 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1891 store_unsigned_integer (valbuf, len, byte_order, val);
1895 /* Get the return value from R10 and R11. */
1896 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1897 store_unsigned_integer (valbuf, 4, byte_order, val);
1898 regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val);
1899 store_unsigned_integer ((char *)valbuf + 4, len - 4, byte_order, val);
1902 error (_("cris_extract_return_value: type length too large"));
1905 /* Handle the CRIS return value convention. */
1907 static enum return_value_convention
1908 cris_return_value (struct gdbarch *gdbarch, struct type *func_type,
1909 struct type *type, struct regcache *regcache,
1910 gdb_byte *readbuf, const gdb_byte *writebuf)
1912 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1913 || TYPE_CODE (type) == TYPE_CODE_UNION
1914 || TYPE_LENGTH (type) > 8)
1915 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1916 goes on the stack. */
1917 return RETURN_VALUE_STRUCT_CONVENTION;
1920 cris_extract_return_value (type, regcache, readbuf);
1922 cris_store_return_value (type, regcache, writebuf);
1924 return RETURN_VALUE_REGISTER_CONVENTION;
1927 /* Calculates a value that measures how good inst_args constraints an
1928 instruction. It stems from cris_constraint, found in cris-dis.c. */
1931 constraint (unsigned int insn, const signed char *inst_args,
1932 inst_env_type *inst_env)
1937 const char *s = inst_args;
1943 if ((insn & 0x30) == 0x30)
1948 /* A prefix operand. */
1949 if (inst_env->prefix_found)
1955 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1956 valid "push" size. In case of special register, it may be != 4. */
1957 if (inst_env->prefix_found)
1963 retval = (((insn >> 0xC) & 0xF) == (insn & 0xF));
1971 tmp = (insn >> 0xC) & 0xF;
1973 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1975 /* Since we match four bits, we will give a value of
1976 4 - 1 = 3 in a match. If there is a corresponding
1977 exact match of a special register in another pattern, it
1978 will get a value of 4, which will be higher. This should
1979 be correct in that an exact pattern would match better that
1981 Note that there is a reason for not returning zero; the
1982 pattern for "clear" is partly matched in the bit-pattern
1983 (the two lower bits must be zero), while the bit-pattern
1984 for a move from a special register is matched in the
1985 register constraint.
1986 This also means we will will have a race condition if
1987 there is a partly match in three bits in the bit pattern. */
1988 if (tmp == cris_spec_regs[i].number)
1995 if (cris_spec_regs[i].name == NULL)
2002 /* Returns the number of bits set in the variable value. */
2005 number_of_bits (unsigned int value)
2007 int number_of_bits = 0;
2011 number_of_bits += 1;
2012 value &= (value - 1);
2014 return number_of_bits;
2017 /* Finds the address that should contain the single step breakpoint(s).
2018 It stems from code in cris-dis.c. */
2021 find_cris_op (unsigned short insn, inst_env_type *inst_env)
2024 int max_level_of_match = -1;
2025 int max_matched = -1;
2028 for (i = 0; cris_opcodes[i].name != NULL; i++)
2030 if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match)
2031 && ((cris_opcodes[i].lose & insn) == 0)
2032 /* Only CRISv10 instructions, please. */
2033 && (cris_opcodes[i].applicable_version != cris_ver_v32p))
2035 level_of_match = constraint (insn, cris_opcodes[i].args, inst_env);
2036 if (level_of_match >= 0)
2039 number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose);
2040 if (level_of_match > max_level_of_match)
2043 max_level_of_match = level_of_match;
2044 if (level_of_match == 16)
2046 /* All bits matched, cannot find better. */
2056 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
2057 actually an internal error. */
2060 find_step_target (struct frame_info *frame, inst_env_type *inst_env)
2064 unsigned short insn;
2065 struct gdbarch *gdbarch = get_frame_arch (frame);
2066 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2068 /* Create a local register image and set the initial state. */
2069 for (i = 0; i < NUM_GENREGS; i++)
2072 (unsigned long) get_frame_register_unsigned (frame, i);
2074 offset = NUM_GENREGS;
2075 for (i = 0; i < NUM_SPECREGS; i++)
2078 (unsigned long) get_frame_register_unsigned (frame, offset + i);
2080 inst_env->branch_found = 0;
2081 inst_env->slot_needed = 0;
2082 inst_env->delay_slot_pc_active = 0;
2083 inst_env->prefix_found = 0;
2084 inst_env->invalid = 0;
2085 inst_env->xflag_found = 0;
2086 inst_env->disable_interrupt = 0;
2087 inst_env->byte_order = byte_order;
2089 /* Look for a step target. */
2092 /* Read an instruction from the client. */
2093 insn = read_memory_unsigned_integer
2094 (inst_env->reg[gdbarch_pc_regnum (gdbarch)], 2, byte_order);
2096 /* If the instruction is not in a delay slot the new content of the
2097 PC is [PC] + 2. If the instruction is in a delay slot it is not
2098 that simple. Since a instruction in a delay slot cannot change
2099 the content of the PC, it does not matter what value PC will have.
2100 Just make sure it is a valid instruction. */
2101 if (!inst_env->delay_slot_pc_active)
2103 inst_env->reg[gdbarch_pc_regnum (gdbarch)] += 2;
2107 inst_env->delay_slot_pc_active = 0;
2108 inst_env->reg[gdbarch_pc_regnum (gdbarch)]
2109 = inst_env->delay_slot_pc;
2111 /* Analyse the present instruction. */
2112 i = find_cris_op (insn, inst_env);
2115 inst_env->invalid = 1;
2119 cris_gdb_func (gdbarch, cris_opcodes[i].op, insn, inst_env);
2121 } while (!inst_env->invalid
2122 && (inst_env->prefix_found || inst_env->xflag_found
2123 || inst_env->slot_needed));
2127 /* There is no hardware single-step support. The function find_step_target
2128 digs through the opcodes in order to find all possible targets.
2129 Either one ordinary target or two targets for branches may be found. */
2132 cris_software_single_step (struct frame_info *frame)
2134 struct gdbarch *gdbarch = get_frame_arch (frame);
2135 inst_env_type inst_env;
2137 /* Analyse the present instruction environment and insert
2139 int status = find_step_target (frame, &inst_env);
2142 /* Could not find a target. Things are likely to go downhill
2144 warning (_("CRIS software single step could not find a step target."));
2148 /* Insert at most two breakpoints. One for the next PC content
2149 and possibly another one for a branch, jump, etc. */
2151 = (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (gdbarch)];
2152 insert_single_step_breakpoint (gdbarch, next_pc);
2153 if (inst_env.branch_found
2154 && (CORE_ADDR) inst_env.branch_break_address != next_pc)
2156 CORE_ADDR branch_target_address
2157 = (CORE_ADDR) inst_env.branch_break_address;
2158 insert_single_step_breakpoint (gdbarch, branch_target_address);
2165 /* Calculates the prefix value for quick offset addressing mode. */
2168 quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2170 /* It's invalid to be in a delay slot. You can't have a prefix to this
2171 instruction (not 100% sure). */
2172 if (inst_env->slot_needed || inst_env->prefix_found)
2174 inst_env->invalid = 1;
2178 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2179 inst_env->prefix_value += cris_get_bdap_quick_offset (inst);
2181 /* A prefix doesn't change the xflag_found. But the rest of the flags
2183 inst_env->slot_needed = 0;
2184 inst_env->prefix_found = 1;
2187 /* Updates the autoincrement register. The size of the increment is derived
2188 from the size of the operation. The PC is always kept aligned on even
2192 process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env)
2194 if (size == INST_BYTE_SIZE)
2196 inst_env->reg[cris_get_operand1 (inst)] += 1;
2198 /* The PC must be word aligned, so increase the PC with one
2199 word even if the size is byte. */
2200 if (cris_get_operand1 (inst) == REG_PC)
2202 inst_env->reg[REG_PC] += 1;
2205 else if (size == INST_WORD_SIZE)
2207 inst_env->reg[cris_get_operand1 (inst)] += 2;
2209 else if (size == INST_DWORD_SIZE)
2211 inst_env->reg[cris_get_operand1 (inst)] += 4;
2216 inst_env->invalid = 1;
2220 /* Just a forward declaration. */
2222 static unsigned long get_data_from_address (unsigned short *inst,
2224 enum bfd_endian byte_order);
2226 /* Calculates the prefix value for the general case of offset addressing
2230 bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2235 /* It's invalid to be in a delay slot. */
2236 if (inst_env->slot_needed || inst_env->prefix_found)
2238 inst_env->invalid = 1;
2242 /* The calculation of prefix_value used to be after process_autoincrement,
2243 but that fails for an instruction such as jsr [$r0+12] which is encoded
2244 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
2245 mustn't be incremented until we have read it and what it points at. */
2246 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2248 /* The offset is an indirection of the contents of the operand1 register. */
2249 inst_env->prefix_value +=
2250 get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)],
2251 inst_env->byte_order);
2253 if (cris_get_mode (inst) == AUTOINC_MODE)
2255 process_autoincrement (cris_get_size (inst), inst, inst_env);
2258 /* A prefix doesn't change the xflag_found. But the rest of the flags
2260 inst_env->slot_needed = 0;
2261 inst_env->prefix_found = 1;
2264 /* Calculates the prefix value for the index addressing mode. */
2267 biap_prefix (unsigned short inst, inst_env_type *inst_env)
2269 /* It's invalid to be in a delay slot. I can't see that it's possible to
2270 have a prefix to this instruction. So I will treat this as invalid. */
2271 if (inst_env->slot_needed || inst_env->prefix_found)
2273 inst_env->invalid = 1;
2277 inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)];
2279 /* The offset is the operand2 value shifted the size of the instruction
2281 inst_env->prefix_value +=
2282 inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst);
2284 /* If the PC is operand1 (base) the address used is the address after
2285 the main instruction, i.e. address + 2 (the PC is already compensated
2286 for the prefix operation). */
2287 if (cris_get_operand1 (inst) == REG_PC)
2289 inst_env->prefix_value += 2;
2292 /* A prefix doesn't change the xflag_found. But the rest of the flags
2294 inst_env->slot_needed = 0;
2295 inst_env->xflag_found = 0;
2296 inst_env->prefix_found = 1;
2299 /* Calculates the prefix value for the double indirect addressing mode. */
2302 dip_prefix (unsigned short inst, inst_env_type *inst_env)
2307 /* It's invalid to be in a delay slot. */
2308 if (inst_env->slot_needed || inst_env->prefix_found)
2310 inst_env->invalid = 1;
2314 /* The prefix value is one dereference of the contents of the operand1
2316 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2317 inst_env->prefix_value
2318 = read_memory_unsigned_integer (address, 4, inst_env->byte_order);
2320 /* Check if the mode is autoincrement. */
2321 if (cris_get_mode (inst) == AUTOINC_MODE)
2323 inst_env->reg[cris_get_operand1 (inst)] += 4;
2326 /* A prefix doesn't change the xflag_found. But the rest of the flags
2328 inst_env->slot_needed = 0;
2329 inst_env->xflag_found = 0;
2330 inst_env->prefix_found = 1;
2333 /* Finds the destination for a branch with 8-bits offset. */
2336 eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2341 /* If we have a prefix or are in a delay slot it's bad. */
2342 if (inst_env->slot_needed || inst_env->prefix_found)
2344 inst_env->invalid = 1;
2348 /* We have a branch, find out where the branch will land. */
2349 offset = cris_get_branch_short_offset (inst);
2351 /* Check if the offset is signed. */
2352 if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK)
2357 /* The offset ends with the sign bit, set it to zero. The address
2358 should always be word aligned. */
2359 offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK;
2361 inst_env->branch_found = 1;
2362 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2364 inst_env->slot_needed = 1;
2365 inst_env->prefix_found = 0;
2366 inst_env->xflag_found = 0;
2367 inst_env->disable_interrupt = 1;
2370 /* Finds the destination for a branch with 16-bits offset. */
2373 sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2377 /* If we have a prefix or is in a delay slot it's bad. */
2378 if (inst_env->slot_needed || inst_env->prefix_found)
2380 inst_env->invalid = 1;
2384 /* We have a branch, find out the offset for the branch. */
2385 offset = read_memory_integer (inst_env->reg[REG_PC], 2, inst_env->byte_order);
2387 /* The instruction is one word longer than normal, so add one word
2389 inst_env->reg[REG_PC] += 2;
2391 inst_env->branch_found = 1;
2392 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2395 inst_env->slot_needed = 1;
2396 inst_env->prefix_found = 0;
2397 inst_env->xflag_found = 0;
2398 inst_env->disable_interrupt = 1;
2401 /* Handles the ABS instruction. */
2404 abs_op (unsigned short inst, inst_env_type *inst_env)
2409 /* ABS can't have a prefix, so it's bad if it does. */
2410 if (inst_env->prefix_found)
2412 inst_env->invalid = 1;
2416 /* Check if the operation affects the PC. */
2417 if (cris_get_operand2 (inst) == REG_PC)
2420 /* It's invalid to change to the PC if we are in a delay slot. */
2421 if (inst_env->slot_needed)
2423 inst_env->invalid = 1;
2427 value = (long) inst_env->reg[REG_PC];
2429 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
2430 if (value != SIGNED_DWORD_MASK)
2433 inst_env->reg[REG_PC] = (long) value;
2437 inst_env->slot_needed = 0;
2438 inst_env->prefix_found = 0;
2439 inst_env->xflag_found = 0;
2440 inst_env->disable_interrupt = 0;
2443 /* Handles the ADDI instruction. */
2446 addi_op (unsigned short inst, inst_env_type *inst_env)
2448 /* It's invalid to have the PC as base register. And ADDI can't have
2450 if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC))
2452 inst_env->invalid = 1;
2456 inst_env->slot_needed = 0;
2457 inst_env->prefix_found = 0;
2458 inst_env->xflag_found = 0;
2459 inst_env->disable_interrupt = 0;
2462 /* Handles the ASR instruction. */
2465 asr_op (unsigned short inst, inst_env_type *inst_env)
2468 unsigned long value;
2469 unsigned long signed_extend_mask = 0;
2471 /* ASR can't have a prefix, so check that it doesn't. */
2472 if (inst_env->prefix_found)
2474 inst_env->invalid = 1;
2478 /* Check if the PC is the target register. */
2479 if (cris_get_operand2 (inst) == REG_PC)
2481 /* It's invalid to change the PC in a delay slot. */
2482 if (inst_env->slot_needed)
2484 inst_env->invalid = 1;
2487 /* Get the number of bits to shift. */
2488 shift_steps = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]);
2489 value = inst_env->reg[REG_PC];
2491 /* Find out how many bits the operation should apply to. */
2492 if (cris_get_size (inst) == INST_BYTE_SIZE)
2494 if (value & SIGNED_BYTE_MASK)
2496 signed_extend_mask = 0xFF;
2497 signed_extend_mask = signed_extend_mask >> shift_steps;
2498 signed_extend_mask = ~signed_extend_mask;
2500 value = value >> shift_steps;
2501 value |= signed_extend_mask;
2503 inst_env->reg[REG_PC] &= 0xFFFFFF00;
2504 inst_env->reg[REG_PC] |= value;
2506 else if (cris_get_size (inst) == INST_WORD_SIZE)
2508 if (value & SIGNED_WORD_MASK)
2510 signed_extend_mask = 0xFFFF;
2511 signed_extend_mask = signed_extend_mask >> shift_steps;
2512 signed_extend_mask = ~signed_extend_mask;
2514 value = value >> shift_steps;
2515 value |= signed_extend_mask;
2517 inst_env->reg[REG_PC] &= 0xFFFF0000;
2518 inst_env->reg[REG_PC] |= value;
2520 else if (cris_get_size (inst) == INST_DWORD_SIZE)
2522 if (value & SIGNED_DWORD_MASK)
2524 signed_extend_mask = 0xFFFFFFFF;
2525 signed_extend_mask = signed_extend_mask >> shift_steps;
2526 signed_extend_mask = ~signed_extend_mask;
2528 value = value >> shift_steps;
2529 value |= signed_extend_mask;
2530 inst_env->reg[REG_PC] = value;
2533 inst_env->slot_needed = 0;
2534 inst_env->prefix_found = 0;
2535 inst_env->xflag_found = 0;
2536 inst_env->disable_interrupt = 0;
2539 /* Handles the ASRQ instruction. */
2542 asrq_op (unsigned short inst, inst_env_type *inst_env)
2546 unsigned long value;
2547 unsigned long signed_extend_mask = 0;
2549 /* ASRQ can't have a prefix, so check that it doesn't. */
2550 if (inst_env->prefix_found)
2552 inst_env->invalid = 1;
2556 /* Check if the PC is the target register. */
2557 if (cris_get_operand2 (inst) == REG_PC)
2560 /* It's invalid to change the PC in a delay slot. */
2561 if (inst_env->slot_needed)
2563 inst_env->invalid = 1;
2566 /* The shift size is given as a 5 bit quick value, i.e. we don't
2567 want the the sign bit of the quick value. */
2568 shift_steps = cris_get_asr_shift_steps (inst);
2569 value = inst_env->reg[REG_PC];
2570 if (value & SIGNED_DWORD_MASK)
2572 signed_extend_mask = 0xFFFFFFFF;
2573 signed_extend_mask = signed_extend_mask >> shift_steps;
2574 signed_extend_mask = ~signed_extend_mask;
2576 value = value >> shift_steps;
2577 value |= signed_extend_mask;
2578 inst_env->reg[REG_PC] = value;
2580 inst_env->slot_needed = 0;
2581 inst_env->prefix_found = 0;
2582 inst_env->xflag_found = 0;
2583 inst_env->disable_interrupt = 0;
2586 /* Handles the AX, EI and SETF instruction. */
2589 ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env)
2591 if (inst_env->prefix_found)
2593 inst_env->invalid = 1;
2596 /* Check if the instruction is setting the X flag. */
2597 if (cris_is_xflag_bit_on (inst))
2599 inst_env->xflag_found = 1;
2603 inst_env->xflag_found = 0;
2605 inst_env->slot_needed = 0;
2606 inst_env->prefix_found = 0;
2607 inst_env->disable_interrupt = 1;
2610 /* Checks if the instruction is in assign mode. If so, it updates the assign
2611 register. Note that check_assign assumes that the caller has checked that
2612 there is a prefix to this instruction. The mode check depends on this. */
2615 check_assign (unsigned short inst, inst_env_type *inst_env)
2617 /* Check if it's an assign addressing mode. */
2618 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2620 /* Assign the prefix value to operand 1. */
2621 inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value;
2625 /* Handles the 2-operand BOUND instruction. */
2628 two_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2630 /* It's invalid to have the PC as the index operand. */
2631 if (cris_get_operand2 (inst) == REG_PC)
2633 inst_env->invalid = 1;
2636 /* Check if we have a prefix. */
2637 if (inst_env->prefix_found)
2639 check_assign (inst, inst_env);
2641 /* Check if this is an autoincrement mode. */
2642 else if (cris_get_mode (inst) == AUTOINC_MODE)
2644 /* It's invalid to change the PC in a delay slot. */
2645 if (inst_env->slot_needed)
2647 inst_env->invalid = 1;
2650 process_autoincrement (cris_get_size (inst), inst, inst_env);
2652 inst_env->slot_needed = 0;
2653 inst_env->prefix_found = 0;
2654 inst_env->xflag_found = 0;
2655 inst_env->disable_interrupt = 0;
2658 /* Handles the 3-operand BOUND instruction. */
2661 three_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2663 /* It's an error if we haven't got a prefix. And it's also an error
2664 if the PC is the destination register. */
2665 if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC))
2667 inst_env->invalid = 1;
2670 inst_env->slot_needed = 0;
2671 inst_env->prefix_found = 0;
2672 inst_env->xflag_found = 0;
2673 inst_env->disable_interrupt = 0;
2676 /* Clears the status flags in inst_env. */
2679 btst_nop_op (unsigned short inst, inst_env_type *inst_env)
2681 /* It's an error if we have got a prefix. */
2682 if (inst_env->prefix_found)
2684 inst_env->invalid = 1;
2688 inst_env->slot_needed = 0;
2689 inst_env->prefix_found = 0;
2690 inst_env->xflag_found = 0;
2691 inst_env->disable_interrupt = 0;
2694 /* Clears the status flags in inst_env. */
2697 clearf_di_op (unsigned short inst, inst_env_type *inst_env)
2699 /* It's an error if we have got a prefix. */
2700 if (inst_env->prefix_found)
2702 inst_env->invalid = 1;
2706 inst_env->slot_needed = 0;
2707 inst_env->prefix_found = 0;
2708 inst_env->xflag_found = 0;
2709 inst_env->disable_interrupt = 1;
2712 /* Handles the CLEAR instruction if it's in register mode. */
2715 reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env)
2717 /* Check if the target is the PC. */
2718 if (cris_get_operand2 (inst) == REG_PC)
2720 /* The instruction will clear the instruction's size bits. */
2721 int clear_size = cris_get_clear_size (inst);
2722 if (clear_size == INST_BYTE_SIZE)
2724 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00;
2726 if (clear_size == INST_WORD_SIZE)
2728 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000;
2730 if (clear_size == INST_DWORD_SIZE)
2732 inst_env->delay_slot_pc = 0x0;
2734 /* The jump will be delayed with one delay slot. So we need a delay
2736 inst_env->slot_needed = 1;
2737 inst_env->delay_slot_pc_active = 1;
2741 /* The PC will not change => no delay slot. */
2742 inst_env->slot_needed = 0;
2744 inst_env->prefix_found = 0;
2745 inst_env->xflag_found = 0;
2746 inst_env->disable_interrupt = 0;
2749 /* Handles the TEST instruction if it's in register mode. */
2752 reg_mode_test_op (unsigned short inst, inst_env_type *inst_env)
2754 /* It's an error if we have got a prefix. */
2755 if (inst_env->prefix_found)
2757 inst_env->invalid = 1;
2760 inst_env->slot_needed = 0;
2761 inst_env->prefix_found = 0;
2762 inst_env->xflag_found = 0;
2763 inst_env->disable_interrupt = 0;
2767 /* Handles the CLEAR and TEST instruction if the instruction isn't
2768 in register mode. */
2771 none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env)
2773 /* Check if we are in a prefix mode. */
2774 if (inst_env->prefix_found)
2776 /* The only way the PC can change is if this instruction is in
2777 assign addressing mode. */
2778 check_assign (inst, inst_env);
2780 /* Indirect mode can't change the PC so just check if the mode is
2782 else if (cris_get_mode (inst) == AUTOINC_MODE)
2784 process_autoincrement (cris_get_size (inst), inst, inst_env);
2786 inst_env->slot_needed = 0;
2787 inst_env->prefix_found = 0;
2788 inst_env->xflag_found = 0;
2789 inst_env->disable_interrupt = 0;
2792 /* Checks that the PC isn't the destination register or the instructions has
2796 dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env)
2798 /* It's invalid to have the PC as the destination. The instruction can't
2800 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2802 inst_env->invalid = 1;
2806 inst_env->slot_needed = 0;
2807 inst_env->prefix_found = 0;
2808 inst_env->xflag_found = 0;
2809 inst_env->disable_interrupt = 0;
2812 /* Checks that the instruction doesn't have a prefix. */
2815 break_op (unsigned short inst, inst_env_type *inst_env)
2817 /* The instruction can't have a prefix. */
2818 if (inst_env->prefix_found)
2820 inst_env->invalid = 1;
2824 inst_env->slot_needed = 0;
2825 inst_env->prefix_found = 0;
2826 inst_env->xflag_found = 0;
2827 inst_env->disable_interrupt = 1;
2830 /* Checks that the PC isn't the destination register and that the instruction
2831 doesn't have a prefix. */
2834 scc_op (unsigned short inst, inst_env_type *inst_env)
2836 /* It's invalid to have the PC as the destination. The instruction can't
2838 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2840 inst_env->invalid = 1;
2844 inst_env->slot_needed = 0;
2845 inst_env->prefix_found = 0;
2846 inst_env->xflag_found = 0;
2847 inst_env->disable_interrupt = 1;
2850 /* Handles the register mode JUMP instruction. */
2853 reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2855 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2856 you can't have a prefix. */
2857 if ((inst_env->slot_needed) || (inst_env->prefix_found))
2859 inst_env->invalid = 1;
2863 /* Just change the PC. */
2864 inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)];
2865 inst_env->slot_needed = 0;
2866 inst_env->prefix_found = 0;
2867 inst_env->xflag_found = 0;
2868 inst_env->disable_interrupt = 1;
2871 /* Handles the JUMP instruction for all modes except register. */
2874 none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2876 unsigned long newpc;
2879 /* It's invalid to do a JUMP in a delay slot. */
2880 if (inst_env->slot_needed)
2882 inst_env->invalid = 1;
2886 /* Check if we have a prefix. */
2887 if (inst_env->prefix_found)
2889 check_assign (inst, inst_env);
2891 /* Get the new value for the the PC. */
2893 read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value,
2894 4, inst_env->byte_order);
2898 /* Get the new value for the PC. */
2899 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2900 newpc = read_memory_unsigned_integer (address,
2901 4, inst_env->byte_order);
2903 /* Check if we should increment a register. */
2904 if (cris_get_mode (inst) == AUTOINC_MODE)
2906 inst_env->reg[cris_get_operand1 (inst)] += 4;
2909 inst_env->reg[REG_PC] = newpc;
2911 inst_env->slot_needed = 0;
2912 inst_env->prefix_found = 0;
2913 inst_env->xflag_found = 0;
2914 inst_env->disable_interrupt = 1;
2917 /* Handles moves to special registers (aka P-register) for all modes. */
2920 move_to_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2921 inst_env_type *inst_env)
2923 if (inst_env->prefix_found)
2925 /* The instruction has a prefix that means we are only interested if
2926 the instruction is in assign mode. */
2927 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2929 /* The prefix handles the problem if we are in a delay slot. */
2930 if (cris_get_operand1 (inst) == REG_PC)
2932 /* Just take care of the assign. */
2933 check_assign (inst, inst_env);
2937 else if (cris_get_mode (inst) == AUTOINC_MODE)
2939 /* The instruction doesn't have a prefix, the only case left that we
2940 are interested in is the autoincrement mode. */
2941 if (cris_get_operand1 (inst) == REG_PC)
2943 /* If the PC is to be incremented it's invalid to be in a
2945 if (inst_env->slot_needed)
2947 inst_env->invalid = 1;
2951 /* The increment depends on the size of the special register. */
2952 if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
2954 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2956 else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
2958 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2962 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2966 inst_env->slot_needed = 0;
2967 inst_env->prefix_found = 0;
2968 inst_env->xflag_found = 0;
2969 inst_env->disable_interrupt = 1;
2972 /* Handles moves from special registers (aka P-register) for all modes
2976 none_reg_mode_move_from_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2977 inst_env_type *inst_env)
2979 if (inst_env->prefix_found)
2981 /* The instruction has a prefix that means we are only interested if
2982 the instruction is in assign mode. */
2983 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2985 /* The prefix handles the problem if we are in a delay slot. */
2986 if (cris_get_operand1 (inst) == REG_PC)
2988 /* Just take care of the assign. */
2989 check_assign (inst, inst_env);
2993 /* The instruction doesn't have a prefix, the only case left that we
2994 are interested in is the autoincrement mode. */
2995 else if (cris_get_mode (inst) == AUTOINC_MODE)
2997 if (cris_get_operand1 (inst) == REG_PC)
2999 /* If the PC is to be incremented it's invalid to be in a
3001 if (inst_env->slot_needed)
3003 inst_env->invalid = 1;
3007 /* The increment depends on the size of the special register. */
3008 if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
3010 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
3012 else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
3014 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
3018 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
3022 inst_env->slot_needed = 0;
3023 inst_env->prefix_found = 0;
3024 inst_env->xflag_found = 0;
3025 inst_env->disable_interrupt = 1;
3028 /* Handles moves from special registers (aka P-register) when the mode
3032 reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env)
3034 /* Register mode move from special register can't have a prefix. */
3035 if (inst_env->prefix_found)
3037 inst_env->invalid = 1;
3041 if (cris_get_operand1 (inst) == REG_PC)
3043 /* It's invalid to change the PC in a delay slot. */
3044 if (inst_env->slot_needed)
3046 inst_env->invalid = 1;
3049 /* The destination is the PC, the jump will have a delay slot. */
3050 inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)];
3051 inst_env->slot_needed = 1;
3052 inst_env->delay_slot_pc_active = 1;
3056 /* If the destination isn't PC, there will be no jump. */
3057 inst_env->slot_needed = 0;
3059 inst_env->prefix_found = 0;
3060 inst_env->xflag_found = 0;
3061 inst_env->disable_interrupt = 1;
3064 /* Handles the MOVEM from memory to general register instruction. */
3067 move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env)
3069 if (inst_env->prefix_found)
3071 /* The prefix handles the problem if we are in a delay slot. Is the
3072 MOVEM instruction going to change the PC? */
3073 if (cris_get_operand2 (inst) >= REG_PC)
3075 inst_env->reg[REG_PC] =
3076 read_memory_unsigned_integer (inst_env->prefix_value,
3077 4, inst_env->byte_order);
3079 /* The assign value is the value after the increment. Normally, the
3080 assign value is the value before the increment. */
3081 if ((cris_get_operand1 (inst) == REG_PC)
3082 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3084 inst_env->reg[REG_PC] = inst_env->prefix_value;
3085 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3090 /* Is the MOVEM instruction going to change the PC? */
3091 if (cris_get_operand2 (inst) == REG_PC)
3093 /* It's invalid to change the PC in a delay slot. */
3094 if (inst_env->slot_needed)
3096 inst_env->invalid = 1;
3099 inst_env->reg[REG_PC] =
3100 read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)],
3101 4, inst_env->byte_order);
3103 /* The increment is not depending on the size, instead it's depending
3104 on the number of registers loaded from memory. */
3105 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3107 /* It's invalid to change the PC in a delay slot. */
3108 if (inst_env->slot_needed)
3110 inst_env->invalid = 1;
3113 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3116 inst_env->slot_needed = 0;
3117 inst_env->prefix_found = 0;
3118 inst_env->xflag_found = 0;
3119 inst_env->disable_interrupt = 0;
3122 /* Handles the MOVEM to memory from general register instruction. */
3125 move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env)
3127 if (inst_env->prefix_found)
3129 /* The assign value is the value after the increment. Normally, the
3130 assign value is the value before the increment. */
3131 if ((cris_get_operand1 (inst) == REG_PC)
3132 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3134 /* The prefix handles the problem if we are in a delay slot. */
3135 inst_env->reg[REG_PC] = inst_env->prefix_value;
3136 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3141 /* The increment is not depending on the size, instead it's depending
3142 on the number of registers loaded to memory. */
3143 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3145 /* It's invalid to change the PC in a delay slot. */
3146 if (inst_env->slot_needed)
3148 inst_env->invalid = 1;
3151 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3154 inst_env->slot_needed = 0;
3155 inst_env->prefix_found = 0;
3156 inst_env->xflag_found = 0;
3157 inst_env->disable_interrupt = 0;
3160 /* Handles the intructions that's not yet implemented, by setting
3161 inst_env->invalid to true. */
3164 not_implemented_op (unsigned short inst, inst_env_type *inst_env)
3166 inst_env->invalid = 1;
3169 /* Handles the XOR instruction. */
3172 xor_op (unsigned short inst, inst_env_type *inst_env)
3174 /* XOR can't have a prefix. */
3175 if (inst_env->prefix_found)
3177 inst_env->invalid = 1;
3181 /* Check if the PC is the target. */
3182 if (cris_get_operand2 (inst) == REG_PC)
3184 /* It's invalid to change the PC in a delay slot. */
3185 if (inst_env->slot_needed)
3187 inst_env->invalid = 1;
3190 inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)];
3192 inst_env->slot_needed = 0;
3193 inst_env->prefix_found = 0;
3194 inst_env->xflag_found = 0;
3195 inst_env->disable_interrupt = 0;
3198 /* Handles the MULS instruction. */
3201 muls_op (unsigned short inst, inst_env_type *inst_env)
3203 /* MULS/U can't have a prefix. */
3204 if (inst_env->prefix_found)
3206 inst_env->invalid = 1;
3210 /* Consider it invalid if the PC is the target. */
3211 if (cris_get_operand2 (inst) == REG_PC)
3213 inst_env->invalid = 1;
3216 inst_env->slot_needed = 0;
3217 inst_env->prefix_found = 0;
3218 inst_env->xflag_found = 0;
3219 inst_env->disable_interrupt = 0;
3222 /* Handles the MULU instruction. */
3225 mulu_op (unsigned short inst, inst_env_type *inst_env)
3227 /* MULS/U can't have a prefix. */
3228 if (inst_env->prefix_found)
3230 inst_env->invalid = 1;
3234 /* Consider it invalid if the PC is the target. */
3235 if (cris_get_operand2 (inst) == REG_PC)
3237 inst_env->invalid = 1;
3240 inst_env->slot_needed = 0;
3241 inst_env->prefix_found = 0;
3242 inst_env->xflag_found = 0;
3243 inst_env->disable_interrupt = 0;
3246 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
3247 The MOVE instruction is the move from source to register. */
3250 add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env,
3251 unsigned long source1, unsigned long source2)
3253 unsigned long pc_mask;
3254 unsigned long operation_mask;
3256 /* Find out how many bits the operation should apply to. */
3257 if (cris_get_size (inst) == INST_BYTE_SIZE)
3259 pc_mask = 0xFFFFFF00;
3260 operation_mask = 0xFF;
3262 else if (cris_get_size (inst) == INST_WORD_SIZE)
3264 pc_mask = 0xFFFF0000;
3265 operation_mask = 0xFFFF;
3267 else if (cris_get_size (inst) == INST_DWORD_SIZE)
3270 operation_mask = 0xFFFFFFFF;
3274 /* The size is out of range. */
3275 inst_env->invalid = 1;
3279 /* The instruction just works on uw_operation_mask bits. */
3280 source2 &= operation_mask;
3281 source1 &= operation_mask;
3283 /* Now calculate the result. The opcode's 3 first bits separates
3284 the different actions. */
3285 switch (cris_get_opcode (inst) & 7)
3295 case 2: /* subtract */
3299 case 3: /* compare */
3311 inst_env->invalid = 1;
3317 /* Make sure that the result doesn't contain more than the instruction
3319 source2 &= operation_mask;
3321 /* Calculate the new breakpoint address. */
3322 inst_env->reg[REG_PC] &= pc_mask;
3323 inst_env->reg[REG_PC] |= source1;
3327 /* Extends the value from either byte or word size to a dword. If the mode
3328 is zero extend then the value is extended with zero. If instead the mode
3329 is signed extend the sign bit of the value is taken into consideration. */
3331 static unsigned long
3332 do_sign_or_zero_extend (unsigned long value, unsigned short *inst)
3334 /* The size can be either byte or word, check which one it is.
3335 Don't check the highest bit, it's indicating if it's a zero
3337 if (cris_get_size (*inst) & INST_WORD_SIZE)
3342 /* Check if the instruction is signed extend. If so, check if value has
3344 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK))
3346 value |= SIGNED_WORD_EXTEND_MASK;
3354 /* Check if the instruction is signed extend. If so, check if value has
3356 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK))
3358 value |= SIGNED_BYTE_EXTEND_MASK;
3361 /* The size should now be dword. */
3362 cris_set_size_to_dword (inst);
3366 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3367 instruction. The MOVE instruction is the move from source to register. */
3370 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3371 inst_env_type *inst_env)
3373 unsigned long operand1;
3374 unsigned long operand2;
3376 /* It's invalid to have a prefix to the instruction. This is a register
3377 mode instruction and can't have a prefix. */
3378 if (inst_env->prefix_found)
3380 inst_env->invalid = 1;
3383 /* Check if the instruction has PC as its target. */
3384 if (cris_get_operand2 (inst) == REG_PC)
3386 if (inst_env->slot_needed)
3388 inst_env->invalid = 1;
3391 /* The instruction has the PC as its target register. */
3392 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3393 operand2 = inst_env->reg[REG_PC];
3395 /* Check if it's a extend, signed or zero instruction. */
3396 if (cris_get_opcode (inst) < 4)
3398 operand1 = do_sign_or_zero_extend (operand1, &inst);
3400 /* Calculate the PC value after the instruction, i.e. where the
3401 breakpoint should be. The order of the udw_operands is vital. */
3402 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3404 inst_env->slot_needed = 0;
3405 inst_env->prefix_found = 0;
3406 inst_env->xflag_found = 0;
3407 inst_env->disable_interrupt = 0;
3410 /* Returns the data contained at address. The size of the data is derived from
3411 the size of the operation. If the instruction is a zero or signed
3412 extend instruction, the size field is changed in instruction. */
3414 static unsigned long
3415 get_data_from_address (unsigned short *inst, CORE_ADDR address, enum bfd_endian byte_order)
3417 int size = cris_get_size (*inst);
3418 unsigned long value;
3420 /* If it's an extend instruction we don't want the signed extend bit,
3421 because it influences the size. */
3422 if (cris_get_opcode (*inst) < 4)
3424 size &= ~SIGNED_EXTEND_BIT_MASK;
3426 /* Is there a need for checking the size? Size should contain the number of
3429 value = read_memory_unsigned_integer (address, size, byte_order);
3431 /* Check if it's an extend, signed or zero instruction. */
3432 if (cris_get_opcode (*inst) < 4)
3434 value = do_sign_or_zero_extend (value, inst);
3439 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3440 instructions. The MOVE instruction is the move from source to register. */
3443 handle_prefix_assign_mode_for_aritm_op (unsigned short inst,
3444 inst_env_type *inst_env)
3446 unsigned long operand2;
3447 unsigned long operand3;
3449 check_assign (inst, inst_env);
3450 if (cris_get_operand2 (inst) == REG_PC)
3452 operand2 = inst_env->reg[REG_PC];
3454 /* Get the value of the third operand. */
3455 operand3 = get_data_from_address (&inst, inst_env->prefix_value,
3456 inst_env->byte_order);
3458 /* Calculate the PC value after the instruction, i.e. where the
3459 breakpoint should be. The order of the udw_operands is vital. */
3460 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3462 inst_env->slot_needed = 0;
3463 inst_env->prefix_found = 0;
3464 inst_env->xflag_found = 0;
3465 inst_env->disable_interrupt = 0;
3468 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3469 OR instructions. Note that for this to work as expected, the calling
3470 function must have made sure that there is a prefix to this instruction. */
3473 three_operand_add_sub_cmp_and_or_op (unsigned short inst,
3474 inst_env_type *inst_env)
3476 unsigned long operand2;
3477 unsigned long operand3;
3479 if (cris_get_operand1 (inst) == REG_PC)
3481 /* The PC will be changed by the instruction. */
3482 operand2 = inst_env->reg[cris_get_operand2 (inst)];
3484 /* Get the value of the third operand. */
3485 operand3 = get_data_from_address (&inst, inst_env->prefix_value,
3486 inst_env->byte_order);
3488 /* Calculate the PC value after the instruction, i.e. where the
3489 breakpoint should be. */
3490 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3492 inst_env->slot_needed = 0;
3493 inst_env->prefix_found = 0;
3494 inst_env->xflag_found = 0;
3495 inst_env->disable_interrupt = 0;
3498 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3499 instructions. The MOVE instruction is the move from source to register. */
3502 handle_prefix_index_mode_for_aritm_op (unsigned short inst,
3503 inst_env_type *inst_env)
3505 if (cris_get_operand1 (inst) != cris_get_operand2 (inst))
3507 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
3508 SUB, AND or OR something weird is going on (if everything works these
3509 instructions should end up in the three operand version). */
3510 inst_env->invalid = 1;
3515 /* three_operand_add_sub_cmp_and_or does the same as we should do here
3517 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3519 inst_env->slot_needed = 0;
3520 inst_env->prefix_found = 0;
3521 inst_env->xflag_found = 0;
3522 inst_env->disable_interrupt = 0;
3525 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3526 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
3527 source to register. */
3530 handle_inc_and_index_mode_for_aritm_op (unsigned short inst,
3531 inst_env_type *inst_env)
3533 unsigned long operand1;
3534 unsigned long operand2;
3535 unsigned long operand3;
3538 /* The instruction is either an indirect or autoincrement addressing mode.
3539 Check if the destination register is the PC. */
3540 if (cris_get_operand2 (inst) == REG_PC)
3542 /* Must be done here, get_data_from_address may change the size
3544 size = cris_get_size (inst);
3545 operand2 = inst_env->reg[REG_PC];
3547 /* Get the value of the third operand, i.e. the indirect operand. */
3548 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3549 operand3 = get_data_from_address (&inst, operand1, inst_env->byte_order);
3551 /* Calculate the PC value after the instruction, i.e. where the
3552 breakpoint should be. The order of the udw_operands is vital. */
3553 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3555 /* If this is an autoincrement addressing mode, check if the increment
3557 if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3559 /* Get the size field. */
3560 size = cris_get_size (inst);
3562 /* If it's an extend instruction we don't want the signed extend bit,
3563 because it influences the size. */
3564 if (cris_get_opcode (inst) < 4)
3566 size &= ~SIGNED_EXTEND_BIT_MASK;
3568 process_autoincrement (size, inst, inst_env);
3570 inst_env->slot_needed = 0;
3571 inst_env->prefix_found = 0;
3572 inst_env->xflag_found = 0;
3573 inst_env->disable_interrupt = 0;
3576 /* Handles the two-operand addressing mode, all modes except register, for
3577 the ADD, SUB CMP, AND and OR instruction. */
3580 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3581 inst_env_type *inst_env)
3583 if (inst_env->prefix_found)
3585 if (cris_get_mode (inst) == PREFIX_INDEX_MODE)
3587 handle_prefix_index_mode_for_aritm_op (inst, inst_env);
3589 else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
3591 handle_prefix_assign_mode_for_aritm_op (inst, inst_env);
3595 /* The mode is invalid for a prefixed base instruction. */
3596 inst_env->invalid = 1;
3602 handle_inc_and_index_mode_for_aritm_op (inst, inst_env);
3606 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3609 quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env)
3611 unsigned long operand1;
3612 unsigned long operand2;
3614 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3615 instruction and can't have a prefix. */
3616 if (inst_env->prefix_found)
3618 inst_env->invalid = 1;
3622 /* Check if the instruction has PC as its target. */
3623 if (cris_get_operand2 (inst) == REG_PC)
3625 if (inst_env->slot_needed)
3627 inst_env->invalid = 1;
3630 operand1 = cris_get_quick_value (inst);
3631 operand2 = inst_env->reg[REG_PC];
3633 /* The size should now be dword. */
3634 cris_set_size_to_dword (&inst);
3636 /* Calculate the PC value after the instruction, i.e. where the
3637 breakpoint should be. */
3638 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3640 inst_env->slot_needed = 0;
3641 inst_env->prefix_found = 0;
3642 inst_env->xflag_found = 0;
3643 inst_env->disable_interrupt = 0;
3646 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3649 quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env)
3651 unsigned long operand1;
3652 unsigned long operand2;
3654 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3655 instruction and can't have a prefix. */
3656 if (inst_env->prefix_found)
3658 inst_env->invalid = 1;
3661 /* Check if the instruction has PC as its target. */
3662 if (cris_get_operand2 (inst) == REG_PC)
3664 if (inst_env->slot_needed)
3666 inst_env->invalid = 1;
3669 /* The instruction has the PC as its target register. */
3670 operand1 = cris_get_quick_value (inst);
3671 operand2 = inst_env->reg[REG_PC];
3673 /* The quick value is signed, so check if we must do a signed extend. */
3674 if (operand1 & SIGNED_QUICK_VALUE_MASK)
3677 operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK;
3679 /* The size should now be dword. */
3680 cris_set_size_to_dword (&inst);
3682 /* Calculate the PC value after the instruction, i.e. where the
3683 breakpoint should be. */
3684 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3686 inst_env->slot_needed = 0;
3687 inst_env->prefix_found = 0;
3688 inst_env->xflag_found = 0;
3689 inst_env->disable_interrupt = 0;
3692 /* Translate op_type to a function and call it. */
3695 cris_gdb_func (struct gdbarch *gdbarch, enum cris_op_type op_type,
3696 unsigned short inst, inst_env_type *inst_env)
3700 case cris_not_implemented_op:
3701 not_implemented_op (inst, inst_env);
3705 abs_op (inst, inst_env);
3709 addi_op (inst, inst_env);
3713 asr_op (inst, inst_env);
3717 asrq_op (inst, inst_env);
3720 case cris_ax_ei_setf_op:
3721 ax_ei_setf_op (inst, inst_env);
3724 case cris_bdap_prefix:
3725 bdap_prefix (inst, inst_env);
3728 case cris_biap_prefix:
3729 biap_prefix (inst, inst_env);
3733 break_op (inst, inst_env);
3736 case cris_btst_nop_op:
3737 btst_nop_op (inst, inst_env);
3740 case cris_clearf_di_op:
3741 clearf_di_op (inst, inst_env);
3744 case cris_dip_prefix:
3745 dip_prefix (inst, inst_env);
3748 case cris_dstep_logshift_mstep_neg_not_op:
3749 dstep_logshift_mstep_neg_not_op (inst, inst_env);
3752 case cris_eight_bit_offset_branch_op:
3753 eight_bit_offset_branch_op (inst, inst_env);
3756 case cris_move_mem_to_reg_movem_op:
3757 move_mem_to_reg_movem_op (inst, inst_env);
3760 case cris_move_reg_to_mem_movem_op:
3761 move_reg_to_mem_movem_op (inst, inst_env);
3764 case cris_move_to_preg_op:
3765 move_to_preg_op (gdbarch, inst, inst_env);
3769 muls_op (inst, inst_env);
3773 mulu_op (inst, inst_env);
3776 case cris_none_reg_mode_add_sub_cmp_and_or_move_op:
3777 none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3780 case cris_none_reg_mode_clear_test_op:
3781 none_reg_mode_clear_test_op (inst, inst_env);
3784 case cris_none_reg_mode_jump_op:
3785 none_reg_mode_jump_op (inst, inst_env);
3788 case cris_none_reg_mode_move_from_preg_op:
3789 none_reg_mode_move_from_preg_op (gdbarch, inst, inst_env);
3792 case cris_quick_mode_add_sub_op:
3793 quick_mode_add_sub_op (inst, inst_env);
3796 case cris_quick_mode_and_cmp_move_or_op:
3797 quick_mode_and_cmp_move_or_op (inst, inst_env);
3800 case cris_quick_mode_bdap_prefix:
3801 quick_mode_bdap_prefix (inst, inst_env);
3804 case cris_reg_mode_add_sub_cmp_and_or_move_op:
3805 reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3808 case cris_reg_mode_clear_op:
3809 reg_mode_clear_op (inst, inst_env);
3812 case cris_reg_mode_jump_op:
3813 reg_mode_jump_op (inst, inst_env);
3816 case cris_reg_mode_move_from_preg_op:
3817 reg_mode_move_from_preg_op (inst, inst_env);
3820 case cris_reg_mode_test_op:
3821 reg_mode_test_op (inst, inst_env);
3825 scc_op (inst, inst_env);
3828 case cris_sixteen_bit_offset_branch_op:
3829 sixteen_bit_offset_branch_op (inst, inst_env);
3832 case cris_three_operand_add_sub_cmp_and_or_op:
3833 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3836 case cris_three_operand_bound_op:
3837 three_operand_bound_op (inst, inst_env);
3840 case cris_two_operand_bound_op:
3841 two_operand_bound_op (inst, inst_env);
3845 xor_op (inst, inst_env);
3850 /* This wrapper is to avoid cris_get_assembler being called before
3851 exec_bfd has been set. */
3854 cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info)
3856 int (*print_insn) (bfd_vma addr, struct disassemble_info *info);
3857 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3858 disassembler, even when there is no BFD. Does something like
3859 "gdb; target remote; disassmeble *0x123" work? */
3860 gdb_assert (exec_bfd != NULL);
3861 print_insn = cris_get_disassembler (exec_bfd);
3862 gdb_assert (print_insn != NULL);
3863 return print_insn (addr, info);
3866 /* Copied from <asm/elf.h>. */
3867 typedef unsigned long elf_greg_t;
3869 /* Same as user_regs_struct struct in <asm/user.h>. */
3870 #define CRISV10_ELF_NGREG 35
3871 typedef elf_greg_t elf_gregset_t[CRISV10_ELF_NGREG];
3873 #define CRISV32_ELF_NGREG 32
3874 typedef elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG];
3876 /* Unpack an elf_gregset_t into GDB's register cache. */
3879 cris_supply_gregset (struct regcache *regcache, elf_gregset_t *gregsetp)
3881 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3882 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3884 elf_greg_t *regp = *gregsetp;
3885 static char zerobuf[4] = {0};
3887 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3888 knows about the actual size of each register so that's no problem. */
3889 for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++)
3891 regcache_raw_supply (regcache, i, (char *)®p[i]);
3894 if (tdep->cris_version == 32)
3896 /* Needed to set pseudo-register PC for CRISv32. */
3897 /* FIXME: If ERP is in a delay slot at this point then the PC will
3898 be wrong. Issue a warning to alert the user. */
3899 regcache_raw_supply (regcache, gdbarch_pc_regnum (gdbarch),
3900 (char *)®p[ERP_REGNUM]);
3902 if (*(char *)®p[ERP_REGNUM] & 0x1)
3903 fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n");
3907 /* Use a local version of this function to get the correct types for
3908 regsets, until multi-arch core support is ready. */
3911 fetch_core_registers (struct regcache *regcache,
3912 char *core_reg_sect, unsigned core_reg_size,
3913 int which, CORE_ADDR reg_addr)
3915 elf_gregset_t gregset;
3920 if (core_reg_size != sizeof (elf_gregset_t)
3921 && core_reg_size != sizeof (crisv32_elf_gregset_t))
3923 warning (_("wrong size gregset struct in core file"));
3927 memcpy (&gregset, core_reg_sect, sizeof (gregset));
3928 cris_supply_gregset (regcache, &gregset);
3932 /* We've covered all the kinds of registers we know about here,
3933 so this must be something we wouldn't know what to do with
3934 anyway. Just ignore it. */
3939 static struct core_fns cris_elf_core_fns =
3941 bfd_target_elf_flavour, /* core_flavour */
3942 default_check_format, /* check_format */
3943 default_core_sniffer, /* core_sniffer */
3944 fetch_core_registers, /* core_read_registers */
3948 extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */
3951 _initialize_cris_tdep (void)
3953 static struct cmd_list_element *cris_set_cmdlist;
3954 static struct cmd_list_element *cris_show_cmdlist;
3956 struct cmd_list_element *c;
3958 gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep);
3960 /* CRIS-specific user-commands. */
3961 add_setshow_uinteger_cmd ("cris-version", class_support,
3962 &usr_cmd_cris_version,
3963 _("Set the current CRIS version."),
3964 _("Show the current CRIS version."),
3966 Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\
3969 NULL, /* FIXME: i18n: Current CRIS version is %s. */
3970 &setlist, &showlist);
3972 add_setshow_enum_cmd ("cris-mode", class_support,
3973 cris_modes, &usr_cmd_cris_mode,
3974 _("Set the current CRIS mode."),
3975 _("Show the current CRIS mode."),
3977 Set to CRIS_MODE_GURU when debugging in guru mode.\n\
3978 Makes GDB use the NRP register instead of the ERP register in certain cases."),
3980 NULL, /* FIXME: i18n: Current CRIS version is %s. */
3981 &setlist, &showlist);
3983 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support,
3984 &usr_cmd_cris_dwarf2_cfi,
3985 _("Set the usage of Dwarf-2 CFI for CRIS."),
3986 _("Show the usage of Dwarf-2 CFI for CRIS."),
3987 _("Set this to \"off\" if using gcc-cris < R59."),
3988 set_cris_dwarf2_cfi,
3989 NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI for CRIS is %d. */
3990 &setlist, &showlist);
3992 deprecated_add_core_fns (&cris_elf_core_fns);
3995 /* Prints out all target specific values. */
3998 cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
4000 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4003 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n",
4004 tdep->cris_version);
4005 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n",
4007 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
4008 tdep->cris_dwarf2_cfi);
4013 set_cris_version (char *ignore_args, int from_tty,
4014 struct cmd_list_element *c)
4016 struct gdbarch_info info;
4018 usr_cmd_cris_version_valid = 1;
4020 /* Update the current architecture, if needed. */
4021 gdbarch_info_init (&info);
4022 if (!gdbarch_update_p (info))
4023 internal_error (__FILE__, __LINE__,
4024 _("cris_gdbarch_update: failed to update architecture."));
4028 set_cris_mode (char *ignore_args, int from_tty,
4029 struct cmd_list_element *c)
4031 struct gdbarch_info info;
4033 /* Update the current architecture, if needed. */
4034 gdbarch_info_init (&info);
4035 if (!gdbarch_update_p (info))
4036 internal_error (__FILE__, __LINE__,
4037 "cris_gdbarch_update: failed to update architecture.");
4041 set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
4042 struct cmd_list_element *c)
4044 struct gdbarch_info info;
4046 /* Update the current architecture, if needed. */
4047 gdbarch_info_init (&info);
4048 if (!gdbarch_update_p (info))
4049 internal_error (__FILE__, __LINE__,
4050 _("cris_gdbarch_update: failed to update architecture."));
4053 static struct gdbarch *
4054 cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
4056 struct gdbarch *gdbarch;
4057 struct gdbarch_tdep *tdep;
4060 if (usr_cmd_cris_version_valid)
4062 /* Trust the user's CRIS version setting. */
4063 cris_version = usr_cmd_cris_version;
4065 else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32)
4071 /* Assume it's CRIS version 10. */
4075 /* Make the current settings visible to the user. */
4076 usr_cmd_cris_version = cris_version;
4078 /* Find a candidate among the list of pre-declared architectures. */
4079 for (arches = gdbarch_list_lookup_by_info (arches, &info);
4081 arches = gdbarch_list_lookup_by_info (arches->next, &info))
4083 if ((gdbarch_tdep (arches->gdbarch)->cris_version
4084 == usr_cmd_cris_version)
4085 && (gdbarch_tdep (arches->gdbarch)->cris_mode
4086 == usr_cmd_cris_mode)
4087 && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi
4088 == usr_cmd_cris_dwarf2_cfi))
4089 return arches->gdbarch;
4092 /* No matching architecture was found. Create a new one. */
4093 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
4094 gdbarch = gdbarch_alloc (&info, tdep);
4096 tdep->cris_version = usr_cmd_cris_version;
4097 tdep->cris_mode = usr_cmd_cris_mode;
4098 tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi;
4100 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
4101 switch (info.byte_order)
4103 case BFD_ENDIAN_LITTLE:
4107 case BFD_ENDIAN_BIG:
4108 internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: big endian byte order in info"));
4112 internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: unknown byte order in info"));
4115 set_gdbarch_return_value (gdbarch, cris_return_value);
4117 set_gdbarch_sp_regnum (gdbarch, 14);
4119 /* Length of ordinary registers used in push_word and a few other
4120 places. register_size() is the real way to know how big a
4123 set_gdbarch_double_bit (gdbarch, 64);
4124 /* The default definition of a long double is 2 * gdbarch_double_bit,
4125 which means we have to set this explicitly. */
4126 set_gdbarch_long_double_bit (gdbarch, 64);
4128 /* The total amount of space needed to store (in an array called registers)
4129 GDB's copy of the machine's register state. Note: We can not use
4130 cris_register_size at this point, since it relies on gdbarch
4132 switch (tdep->cris_version)
4140 /* Old versions; not supported. */
4141 internal_error (__FILE__, __LINE__,
4142 _("cris_gdbarch_init: unsupported CRIS version"));
4147 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
4148 P7 (32 bits), and P15 (32 bits) have been implemented. */
4149 set_gdbarch_pc_regnum (gdbarch, 15);
4150 set_gdbarch_register_type (gdbarch, cris_register_type);
4151 /* There are 32 registers (some of which may not be implemented). */
4152 set_gdbarch_num_regs (gdbarch, 32);
4153 set_gdbarch_register_name (gdbarch, cris_register_name);
4154 set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register);
4155 set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register);
4157 set_gdbarch_software_single_step (gdbarch, cris_software_single_step);
4161 /* CRIS v32. General registers R0 - R15 (32 bits), special registers
4162 P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
4163 and pseudo-register PC (32 bits). */
4164 set_gdbarch_pc_regnum (gdbarch, 32);
4165 set_gdbarch_register_type (gdbarch, crisv32_register_type);
4166 /* 32 registers + pseudo-register PC + 16 support registers. */
4167 set_gdbarch_num_regs (gdbarch, 32 + 1 + 16);
4168 set_gdbarch_register_name (gdbarch, crisv32_register_name);
4170 set_gdbarch_cannot_store_register
4171 (gdbarch, crisv32_cannot_store_register);
4172 set_gdbarch_cannot_fetch_register
4173 (gdbarch, crisv32_cannot_fetch_register);
4175 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
4177 set_gdbarch_single_step_through_delay
4178 (gdbarch, crisv32_single_step_through_delay);
4183 internal_error (__FILE__, __LINE__,
4184 _("cris_gdbarch_init: unknown CRIS version"));
4187 /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
4188 have the same ABI). */
4189 set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code);
4190 set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call);
4191 set_gdbarch_frame_align (gdbarch, cris_frame_align);
4192 set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue);
4194 /* The stack grows downward. */
4195 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4197 set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc);
4199 set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc);
4200 set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp);
4201 set_gdbarch_dummy_id (gdbarch, cris_dummy_id);
4203 if (tdep->cris_dwarf2_cfi == 1)
4205 /* Hook in the Dwarf-2 frame sniffer. */
4206 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum);
4207 dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg);
4208 dwarf2_append_unwinders (gdbarch);
4211 if (tdep->cris_mode != cris_mode_guru)
4213 frame_unwind_append_unwinder (gdbarch, &cris_sigtramp_frame_unwind);
4216 frame_unwind_append_unwinder (gdbarch, &cris_frame_unwind);
4217 frame_base_set_default (gdbarch, &cris_frame_base);
4219 set_solib_svr4_fetch_link_map_offsets
4220 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
4222 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
4223 disassembler, even when there is no BFD. Does something like
4224 "gdb; target remote; disassmeble *0x123" work? */
4225 set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler);